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USER`S MANUAL

1. 3 1 Register Addressing Mode Ennan nnne EEEa 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode 3 7 Direct Address Mode 3 10 Indirect Addr ss Mode 3 12 Relative Address Mode 3 13 Iro Ewald 3 14 S3C825A P825A MICROCONTROLLER Chapter 4 Control Registers COVEIMIOW 4 1 Chapter 5 Interrupt Structure 5 1 MENTE FELIU I MIU DC ea I UID 5 2 S3G825A Interr pt StuUCtU E oec ocio TOENE 5 3 Interrupt Vector Addresses 5 5 Enable Disable Interrupt Instructions El 5 7 System Level Interrupt Control 5 7 Interrupt Processing Control 5 8 Peripheral Interrupt Control nennen nennen nnne nnns 5 9 System Mode Register 5 10 Interrupt Mask Register
2. 20 2 21 1 S3P825A Pin Assignments 80 Pin TQFP 21 2 21 2 S3P825A Pin Assignments 80 Pin QFP 21 3 21 3 Operating Voltage 21 5 22 1 SMDS Product Configuration SMDS2 sss 22 2 22 2 TB825A Target Board 22 3 22 3 40 Pin Connectors J101 J102 for 22 5 22 4 S3C825A Cables for 80 TQFP 22 6 xiv S3C825A P825A MICROCONTROLLER List of Tables Table Title Page Number Number 1 1 S3C825A Pin 1 6 2 1 S3C825A Register Type 2 3 4 1 Set 1 Registers INTPND STPCON OSCCON in bank 0 of set 1 4 1 4 2 Set 4 Bank 0 ReglSlerS etc mash ale 4 2 4 3 Set 1 Bank 1 Registers nennen nnn nn nnn nnn nnns nnns 4 3 5 1 Interrupt Vectors iocos a a et 5 6 5 2 Interrupt Control Register 5 7 5 3 Interrupt Source Control and Data 5 9 6 1 In
3. Transmit TIP BR 00 DI 02 X X D4 05 X pe X pr X Sup I RIP Figure 18 9 Timing Diagram for Serial Port Mode 3 Operation 18 10 ELECTRONICS S3C825A P825A UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C8 series multiprocessor communication features lets a master S3C825A send a multiple frame serial message to a slave device in a multi S3C825A configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART modes 2 or 3 In these modes 2 and 3 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON register When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th b
4. eene nennen nnn 5 11 Interrupt Priority Register 5 12 Interrupt Request Register 1 5 14 Interrupt Pending Function Types ssssssssssssseeeeeeneneeeennnnnemennnn nennen 5 15 Interrupt Source Polling Sequence ssssssssssssssssseeeee nennen nennen nnns 5 16 Interrupt Service 00 0 0 sinn nnn trn nnns nns 5 16 Generating Interrupt Vector 0 nennen nnne nnn 5 17 Nesting of Vectored 5 17 Instruction Pointe nd s e ee 5 17 Fast Interr pt Processing iie mama 5 17 Chapter 6 Instruction Set OV STNG Winadi Mu A 6 1 Data LY POS uel rcc Ie 6 1 Register 6 1 Addressing i eo ee ERN 6 1 Flags Register 05 9 6 6 Flag DESCriptiOnSs 6 7 Instruction Set 6 8 6 12 Instruction 6 13 S3C825A P825A MICROCONTROLLER Table of Contents Continued Table of Contents Continued Part Il Hardware De
5. 12 3 13 1 Timer Control Register 13 2 13 2 Interrupt Pending Register 13 3 13 3 Simplified Timer Function Diagram Interval Timer 13 4 13 4 Simplified Timer Function Diagram PWM 13 5 13 5 Simplified Timer 3 Function Diagram Capture 13 6 13 6 Timer 3 Block 13 7 14 1 Watch Timer Control Register 24 4000000 14 2 14 2 Watch Timer Circuit 14 3 15 1 LCD Function 15 1 15 2 EGD Circuit Diagram ttd eene terne dened 15 2 15 3 LCD Display Data RAM Organization 15 3 15 4 LCD Control Register 15 4 15 5 LCD Bias Circuit Connection 15 6 15 6 Example 1 for the Usage of 7 6 15 7 15 7 Example 2 for the Usage of 7 15 8 15 8 LCD Signal Waveforms 1 3 Duty 1 3 15 9 15 9 LCD Signal Waveforms 1 4 Duty 1 3 Bias 15 10 15 10 LCD Signal Waveforms 1 8 Duty 1 4
6. 6 18 BITC Bit Complement RE 6 19 BITR Bit Reset MM 6 20 BITS UM A A Ra AR Ney 6 21 BOR BIEOR e ette 6 22 BTJRF Bit Test Jump Relative on 99 6 23 BTJRT Bit Test Jump Relative on nennen 6 24 BXOR x mx LAM Mx 6 25 CALL Call Procedure ee er eee 6 26 CCF Complement Carry nennen nennen nnne nennen 6 27 CLR T c EE 6 28 eae ee eee eee aaa 6 29 CP 6 30 Compare Increment and Jump on 2 4 4 4400440000 6 31 CPIJNE Compare Increment and Jump on 6 32 DA Decimal Le UC RR 6 33 DEC Decrement RR 6 35 DECW Decrement 6 36 Disable 6 37 DIV Divide 6 38 DJNZ Decrement and Jump if 2 0 6 39 EI Enable 6 40 ENTER EIE 6 41 E Xit e M DUE MIU I ree 6 42 IDLE Idle Operation RR 6 43 INC oa eee ae ee 6 44 INCW Increment Word RR
7. Output low voltage Vpp 4 5 V to 5 5 V All output ports M N O 19 2 ELECTRONICS S3C825A P825A ELECTRICAL DATA Table 19 2 D C Electrical Characteristics Continued 25 C to 85 C Vpp 2 0 V to 5 5 V Input high leakage Vin Vpp current All input pins except XT in XTour ViN Vpp Xm Xour Input low leakage Vin OV current All input pins except RESET X XTn Vin 9 V Xin Xour Xin current All output pins pot current All output pins Pull up resistor Vin OV Vop 5V 25 0 3 uA 20 3 20 3 3 5 100 i i Rosc2 Vpp 5 V 25 C 1500 3000 4500 XTn 0 V LCD voltage Rico 25 C dividing resistor voltage drop 15 uA per common pin I 0 7 25 50 0 0 40 voltage drop 15 uA per common pin uud Middle output Vpp 2 7 V to 5 5 0 8Vpp 0 2 0 8Vpp 0 8Vpp 0 2 voltage LCD clock 0 Hz 0 6Vpp 0 2 0 6Vpp 0 6Vpp 0 2 3 Oscillator feed back Vpp 5 V 25 C 3 7 1500 resistors Xin Xour 0 V ELECTRONICS 19 3 ELECTRICAL DATA S3C825A P825A Table 19 2 D C Electrical Characteristics Concluded TA 25 C to 85 C 2 0 V to 5 5 V Mm Supply Ipp1 Run mode Current 1 Vpp 5 V 10 Crystal oscillator C1 C2 22pF Vpp 3 V
8. ro oft mess Poffo mee a S O 1 0 1 External clock T3CLK falling edge 1 1 0 External clock T3CLK rising edge 4 3 Timer 3 Operating Mode Selection Bits Interval mode Lo 4 Capture mode capture on rising edge counter running OVF can occur 1 Capture mode capture on falling edge counter running OVF can occur 1 PWM mode OVF amp match interrupt can occur 2 Timer 3 Counter Clear Bit NOTE No effect Clear the timer 3 counter when write Timer 3 match capture interrupt enable bit Disable interrupt 1 Enable interrupt 0 Timer 3 overflow interrupt enable Disable overflow interrupt 1 Enable overflow interrupt NOTE When you write a 1 T3CON 2 the timer 3 counter value is cleared to 00H Immediately following the write operation the T3CON 2 value is automatically cleared to O 4 44 ELECTRONICS S3C825A P825A CONTROL REGISTER UARTCON UART Control Register Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Mode 0 shift register 16 x BRDATA 1 Mode 1 8 Bit UART 16 x BRDATA 1 1 0 Mode 2 9 Bit UART fosc 16 1 1 Mode 3 9 Bit UART fogc 16 x BRDATA 1 5 Multiprocessor Communication Enable Bit for modes 2 and 3
9. 7 2 7 6 System Clock Circuit 7 3 7 7 System Clock Control Register 00042 7 4 7 8 Oscillator Control Register 05 2 7 5 7 9 STOP Control Register 0 0422400000 0 7 7 9 1 Port Group 0 Control Register 000 9 4 9 2 Port 2 High Byte Control Register 9 6 9 3 Port 2 Low Byte Control Register 2 9 6 9 4 Port 2 Pull up Control Register 9 7 9 5 Port 2 Interrupt Control Register 9 7 9 6 Port 3 High Byte Control Register 04008 9 8 9 7 Port Low Byte Control Register 9 9 9 8 Port 3 Pull up Control Register 9 9 9 9 Port 4 High Byte Control Register 8 9 10 9 10 Port 4 Low Byte Control Register 9 11 9 11 Port 4 Interrupt Control Register 9 11 9 12 Port 4 Interrupt Pending Control Register 9 12 9 13 Port 4 Interrupt Edge Selection Register P4EDGE 9 12 9 14 Port 5 High Byte Control Register
10. 22 3 SMDS2t Selection SAMB ttem ibus prb inea P Ria ema Ere Ra 22 4 Idle EE vatum ex uc ao E I RON OC KU DU UN 22 4 iedizs Rm 22 4 x S3C825A P825A MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 Block Diagram ER 1 3 1 2 S3C825A Pin Assignments 80 1212 2 1 4 1 3 S3C825A Pin Assignments 80 QFP 1420 1 5 1 4 elc vw EU 1 8 1 5 Pin Circuit Type B RESET nnn 1 8 1 6 PirvGircult TY DO Gebr teri epe erede cadet p 1 8 1 7 Pin Circuit Type E 4 P2 P3 4 P3 7 1 8 1 8 Pin Circuit Type F 16 0 0001 1 9 1 9 Pin Circuit Type 23 1 9 1 10 Pin Circuit Type 32 0 P1 6 8 1 9 2 1 Program Memory Address 2 2 2 2 Internal Register File Organization 404444 2 4 2 3 Register Page Pointer enne 2 5 2 4 Set 1 Set 2 Prime Area Register and LCD Data Register 2 7 2 5 8 Byte Working Register Areas 2 8 2 6 Contiguous 16 Byte Working Register 2 9 2 7 Non Contiguous 16 Byte Working Regi
11. 4 14 LMOD LCD Mode Control 2 4 15 OSSCON Oscillator Control 8 4 16 2 Port 2 Control Register High Byte 4 17 P2CONL Port 2 Control Register LOW 4 18 P2PUR Port 2 P l up Control Register niara aag 1 4 19 P2INT Port 2 Interrupt Control 4 20 P3CONH Port 3 Control Register High 4 21 P3CONL Port 3 Control Register LOW 4 22 PSPUR Port 3 Pull up Control 4 23 P4CONH Port 4 Control Register High 4 24 P4CONL Port 4 Control Register LOW 4 25 P4EDGE Port 4 Interrupt Edge Selection 4 26 PAINT Port 4 Interrupt Control 4 27 P4PND Port 4 Interrupt Pending Register 4 28 P5CONH Port 5 Control Register High 4 29 P5CONL Port 5 Control Register LOW 4 30 P5PUR Port 5 Pull up Control Register 4 31 PGOCON Port Group 0 Control 4 32 PG1CON Port Group 1 Control 4 33
12. 000 00 5 0 1 input pulkupmode o 1 Open drain output mode Push pull output mode 3 and 2 P4 5 INT9 Mode Selection Bits Co o mumm Fo t mumie mds 71129 1 and 0 P4 4 INT8 Mode Selection Bits Input pull up mode Open drain output mode NOTE Pins configured as input can be used as interrupt input with noise filter 4 24 ELECTRONICS S3C825A P825A CONTROL REGISTER PACONL Port 4 Control Register Low Byte E9H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P4 3 INT7 Mode Selection Bits o o mputmoos 1 put pul upmods 0 0 1 Open drain output mode Push pull output mode 5 and 4 P4 2 INT6 Mode Selection Bits of 71129 Open lt ran ouput mode 3 and 2 P4 1 INT5 Mode Selection Bits Fo o mwmd S Fo 1 input puupmede 71129 longano ooo 1 and 0 P4 0 INT4 Mode Selection Bits o o Inputmode o 1 mput pul upmods 00 0 1 Open drain output mode Push pull output mode NOTE Pins configured as input can be used as interrupt input with noise filter ELECTRONICS 4 25 CONTROL REGISTERS S3C825A P825A PAEDGE 4 Interrupt Edge Selection Register E7H Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value
13. 9 13 9 15 Port 5 Low Byte Control Register 5 9 14 9 16 Port 5 Pull up Control Register 9 14 9 17 Port Group 1 Control Register 9 15 xii S3C825A P825A MICROCONTROLLER List of Figures Continued Page Title Page Number Number 10 1 Basic Timer Control Register 10 2 10 2 Basic Timer Block 10 4 10 3 Timer 0 Control Register 10 6 10 4 Interrupt Pending Register 2 00002 4 00 10 7 10 5 Simplified Timer 0 Function Diagram Interval Timer 10 8 10 6 Simplified Timer 0 Function Diagram PWM 10 9 10 7 Simplified Timer 0 Function Diagram Capture Mode 10 10 10 8 Timer 0 Block 10 11 11 1 Timer 1 Control Register 11 2 Timer 1 Functional Block 11 3 11 3 Timer A Control Register 11 5 11 4 Timer B Control Register 11 6 11 5 Timer A B Function Block 11 7 12 1 Timer 2 Control Register 12 2 12 2 Timer 2 Functional Block
14. 18 7 18 7 Timing Diagram for Serial Port Mode 1 Operation 18 8 18 8 Timing Diagram for Serial Port Mode 2 Operation 18 9 18 9 Timing Diagram for Serial Port Mode Operation 18 10 18 10 Connection Example for Multiprocessor Serial Data Communications 18 12 19 1 Input Timing for External Interrupts 2 4 2 7 19 5 19 2 Input Timing for RESET 2 19 5 19 3 Stop Mode Release Timing Initiated by 19 6 19 4 Stop Mode Release Timing Initiated by 19 7 19 5 Serial Data Transfer 0 nnne 19 9 19 6 Clock Timing Measurement at Xy wn i lt natetennsnetanetatenadenatanstencdnnsdetstetadatatenndenstanetnncan 19 11 19 7 Glock Timing Measurement at HT ss cietwsetiacneiirarcuateenutehsduseluielusenateiateinhedenetesenss 19 11 19 8 Operating Voltage 19 12 19 9 Waveform for UART Timing 19 13 19 10 A C Timing Waveform for the UART 19 14 20 1 Package Dimensions 80 1420 20 1 20 2 Package Dimension 80 1212
15. 15 11 15 11 LCD Signal Waveforms 1 8 Duty 1 5 15 13 16 1 A D Converter Control Register 16 2 16 2 A D Converter Data Register 16 3 16 3 A D Converter Functional Block 16 3 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 4 S3C825A P825A MICROCONTROLLER xiii List of Figures Concluded Page Title Page Number Number 17 1 Serial I O Module Control Register 17 2 17 2 SIO Prescaler Register 2 4400224 0 17 3 17 3 SIO Functional Block 17 3 17 4 Serial Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 17 4 17 5 Serial Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 17 4 18 1 UART Control Register 22 2 0 0000 000 18 2 18 2 UART Interrupt Pending Bits 5 00400 18 3 18 3 UART Data Register 18 4 18 4 UART Baud Rate Data Register 18 4 18 5 UART Functional Block 18 6 18 6 Timing Diagram for Serial Port Mode 0 Operation
16. Port 5 Control Register High PSCONH 286 RW Port 5 Control Register Low Byte PSCONL 287 EDH RW Port 5 Pullup Resistors enable Register PSPUR 288 RW Watch timer control register WTCON 29 RW Port 0 Data Register 240 RW 1 Data Register 24 RW Port2DataRegister Pe 242 RW Port 3 Data Register 1 Ps rw Port4DataRegister 244 RW PortSDataRegister P 245 RW Port 6 Data Register Pe 246 RW Port 7 Data Register 247 RW Por8DataRegster 248 rw Port Group 0 Control Register PGOCON 21 RW PortGroupiContolRegister PG1CON 252 FAH RW Locations FBH FFH are not mapped ELECTRONICS 4 3 CONTROL REGISTERS Bit number s that is are appended to the register name for bit addressing Register ID FLAGS System Flags Regis
17. Locations FBH FFH are mapped 8 4 ELECTRONICS S3C825A P825A RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip oscillator for system clock stops and the supply current is reduced to less than 3 LA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by external interrupts for more details see Figure 7 3 NOTE Do not use stop mode if you are using an external clock source because Xy or XTn input must be restricted internally to Vgg to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fxx 16 because CLKCON 3 and CLKCON 4 are cleared to 00 After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrup
18. 18 4 BAUD Rate Calc lations iakat 18 4 Bl ck Diadgra IRE 18 6 UART Mode 0 Function 2 18 7 Serial Port Mode 1 Function 18 8 Serial Port Mode 2 Function 18 9 Serial Port Mode Function 5 00 4 18 10 Serial Communication for Multiprocessor 18 11 S3C825A P825A MICROCONTROLLER Table of Contents Concluded Chapter 19 Electrical Data COVEINIOW 19 1 Chapter 20 Mechanical Data T 20 1 Chapter 21 S3P825A OTP TU M e TC 21 1 Operating Mode 21 4 Chapter 22 Development Tools CRUISE I FM EM ea 22 1 m 22 1 SAMA oe 22 1 Pellis 22 1 2 DTP 22 1 TargebpBOSrds fas tote foes bn 22 1 TB825A Target
19. by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3C825A P825A DECW Decrement Word DECW Operation Flags Format Examples NOTE 6 36 dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Given RO 12H R1 R2 register OFH and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS S3C825A P825A INSTRUCTION SET DI Disable Interrupts DI Operation SYM 0 0 Bit zero of the syste
20. Enable the timer 2 interrupt and clear timer 2 interrupt pending condition T2CON is located in set 1 bank 0 at address EEH and is read write addressable using register addressing mode A reset clears T2CON to 00H This sets timer 2 to disable interval timer mode and disables timer 2 interrupt You can clear the timer 2 counter at any time during normal operation by writing a 1 to T2CON 3 To enable the timer 2 interrupt IRQ2 vector E8H you must write T2CON 2 and T2CON 1 to 1 To detect an interrupt pending condition when 2 is disabled the application program polls pending bit T2CON 0 When a 1 is detected a timer 2 interrupt is pending When the T2INT sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer 2 interrupt pending bit 2 0 Timer 2 Control Register EEH Set 1 Bank 0 R W Timer 2 input clock selection bits Timer 2 interrupt pending bit 000 fxx 256 0 No interrupt pending 001 fxx 64 0 Clear pending bit when write 010 fxx 8 1 Interrupt is pending 011 2 fxx 1112 External clock T2CLK input Timer 2 interrupt enable bit 0 Disable interrupt Not used 1 Enable interrupt Timer 2 counter clear bit Timer 2 count enable bit 0 No affect 0 Disable counting operation 1 Clear the timer 2 counter 1 Enable counting operation when write Figure 12 1 Timer 2 Control Register T2CON 12 2 ELECTRONICS
21. 0 Basic Control Register BTCON D3H Set 1 R W Watchdog timer enable bits Divider clear bit for all timers 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 16 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3C825A P825A BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during n
22. 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 31 0 leave the value 31 BCD in address 27H R1 ELECTRONICS S3C825A P825A INSTRUCTION SET DEC Decrement DEC dst Operation dst lt dst 1 The contents of the destination operand are decremented by Unaffected Set if the result is 0 cleared otherwise Flags 7 5 Set if result is negative cleared otherwise V D H Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 00 R 01 IR Examples Given R1 and register 10H DEC R1 gt R1 02H DEC gt Register 03H OFH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained the destination register
23. A reset clears SYM 1 and SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W logic 0 Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the Fast interrupt level S3C825A selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing aaa 4 Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 an
24. Vict Vi c2 Vica Vi c4 Vics Vss Vice Vi c3 Vi c4 VLC5 SEG0 COMO Figure 15 9 LCD Signal Waveforms 1 4 Duty 1 3 Bias 15 10 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER com BIL comz BIL 1 188 coms LILIL BE com4 como ZZ lol 1 2 3 4 5 el 7l ol 1 2 3 4 sl el 7 VLC1 OOOO VLC2 VLC3 VLC4 VLC5 Vss VLC2 VLC3 VLC4 VLC5 Vss ViC2 VLc3 VLC4 VLC5 Vss VLc2 VLC3 VLC4 VLC5 Vss VLC2 VLC3 VLC4 VLC5 SEG5 COMO OV VLC5 VLC3 VLC4 VLC2 Figure 15 10 LCD Signal Waveforms 1 8 Duty 1 4 Bias ELECTRONICS 15 11 LCD CONTROLLER DRIVER SEG6 COMO lol 112131415161 zl ol 11213 4151 el 7l S3C825A P825A Vic2 Vica VL c4 Vi C5 Vss Vict Vice Vi ca Vics oV VLc5 Vica Vica Vic2 Vict Figure 15 10 LCD Signal Waveforms 1 8 Duty 1 4 Bias Continued 15 12 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER MEIN lol lol 3 BIL IL JL MM cove 5 COM6 OOM 1 FRAME Figure 15 11 LCD Signal Waveforms 1 8 Duty 1 5 Bias ELECTRONICS 15 13 LCD CONTROLLER DRIVER S3C825A P825A lol al alal 1 FRAME SEG5 COMO SEG6 COMO Figure 15 11 LCD Signal Waveforms 1 8 Duty 1 5 Bias Continued 15 14 ELECTRONICS S3C
25. dst src dst dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 52 6 53 r Ir opc SIC dst 3 6 54 R R 55 R IR opc dst SIC 3 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 01H 02H gt Register 01H register 02H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3C825A P825A INSTRUCTION SET BAND Bit AND BAND dst src b BAND dst b src Operation dst O lt dst 0 AND src b or dst b lt dst b AND 0 The specified bit of the source
26. 28segments and 8 common terminals 3 4 and 8 common selectable e Internal resistor circuit for LCD bias Two Power Down Modes mode only CPU clock stops Stop mode system clock and CPU clock stop Oscillation Source e Crystal ceramic or RC for main clock Crystal for sub clock 32 768 kHz Instruction Execution Time 500 ns at fx 8 MHz minimum main clock 122us at fxt 32 768 kHz sub clock Operating Temperature Range e 25 C to 85 Operating Voltage Range 20V to 5 5 V at 4 MHz main clock e 22V to 5 5 V at 8 MHz main clock e 2 0 V to 5 5 V at 32 768 kHz sub clock Package Type 80 pin TQFP 1212 80 pin QFP 1420 ELECTRONICS S3C825A P825A BLOCK DIAGRAM XIN XOUT XTIN XTOUT P2 4 TOCLK P3 7 TOCAP P3 7 TOOUT TOPWM P2 5 T1CLK P2 6 TAOUT P2 7 TBOUT P2 2 T2CLK 2 3 200 P3 6 T3CAP 6 5 0 5 5 1 5 5 2 50 Watchdog Timer P5 0 BUZ P5 4 RXD P5 5 TXD P6 0 P6 3 COM0 COM3 P6 4 P6 7 COM4 COM7 SEGO SEG3 P7 0 P8 3 SEG4 SEG15 P0 0 P1 7 SEG16 SEG31 VLC1 ELECTRONICS Main OSC 8 Bit Timer CounterO L 8 bit Timer 8 bit Timer A 8 Bit Timer Counter2 16 Bit Timer Counter3 Basic Timer Watch Timer LCD Driver Controller P1 4 P1 7 INTO INT3 P4 0 P4 7 INT4 INT11 Port and Interrupt Control SAM88RC Core 48K byte R
27. 6 67 Push User Stack 2 6 68 Reset Carry 6 69 6 70 piscium 6 71 Rotate Left through 6 72 Rotate inen nnn 6 73 Rotate Right through nennen nnns 6 74 Select Bank 0 MM 6 75 Select BANKS i MPH dp 6 76 Subtract with 6 77 SOU Carry Flag I erp2cc D 6 78 Shift Right 5 6 79 Set Register 6 80 Stop 6 81 Slibthach awakens eR eek ILL 6 82 Swap Nibbles MEM 6 83 Test Complement under 6 84 Igi alt SEE 6 85 Wait for 9 nns 6 86 Logical Exclusive 6 87 S3C825A P825A MICROCONTROLLER S3C825A P825A PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes Among the major CPU features are
28. Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode release by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels 3C825A MICROCONTROLLER The S3C825A single chip microcontroller are fabricated using the highly advanced CMOS process Its design is based on the powerful SAM88RC CPU core Stop and idle power down modes were implemented to reduce power consumption The S3C825A is a microcontroller with a 48K byte mask programmable ROM embedded The S3P825A is microcontroller with a 48K byte one time programmable ROM embedded Using the SAM88RC modular design approach the following peripherals were integrated with the SAM88RC CPU core Large number of programmable I O ports Total 67 pins Synchronous SIO module Two 8 bit timer counters Two 16 bit timer counters LCD controller driver A D converter with 4 selectable input pins OTP The S3C825A microcontroller is also available in OTP One Time Programmable version S3P825A The S3P825A microcontroller has an on chip 48K byte one time programmable EPROM instead of masked ROM The S3P825A is comparable to 53 825 both in function and in pin co
29. P3 0 P3 3 4 0 4 7 6 0 6 3 Table 1 1 53 825 Pin Descriptions P Pin Circuit Type Description Type 4 bit programmable I O port H 32 72 79 Input or push pull open drain output and 74 80 1 software assignable pull ups H 32 4 bit programmable I O port Input or push pull open drain output and software assignable pull ups 1 bit programmable I O port Schmitt trigger input or push pull drain output and software assignable pull T2CLK ups 2 P2 4 P2 7 Alternately used for external INTO TOCLK interrupt input Noise filters interrupt enable and pending control re ue 3 1 bit programmable I O port F 16 25 28 ADO AD3 Schmitt trigger input or push pull 27 30 open drain output and software E 4 assignable pull ups TSOUT TSPWM TSCAP TOOUT TOPWM TOCAP drain output and software assignable pull ups P4 0 P4 7 Alternately used for external interrupt input Noise filters interrupt enable and pending control 1 bit programmable port Schmitt trigger input or push pull open drain output and software assignable pull ups 6 4 6 7 56 59 58 61 4 SEGO SEG3 P7 0 P7 7 60 67 62 69 SEG4 SEG11 P8 0 P8 3 68 71 70 73 SEG12 SEG15 NOTE Parentheses indicate pin number for 80 QFP 1420 package push pull open drain output and software assignable pull ups 1 bit programmable I O port Schmitt trigger inp
30. 0 0 0 0 0 O Port 4 Control Register High Byte P4CONH 232 EH 0 0 o 0 Port 4 Control Register Low Byte PACONL 233 eH Port4lntemuptControlRegister Pant 234 EAH 0 Port 4 Interrupt Pending Register 235 0 0 Port 5 Control Register High Byte 2 0 o Port 5 Control Register Low Byte PSCONL 27 EDH 0 0 o 0 0 0 O Port 5 Pullup Resistors enable Register PSPUR 238 0 0 0 0 0 Watch timer control register WTCON 239 PotODataRegster 10 240 oO oO of oO oO oO 1 DataRegister Pot2DataRegster P2 Pot3DataRegster Pot4DataRegster 244 FAH oO o of PotSDataRegster Ps 245 FSH O o of Port 6 Data Register P6 246 Port 7 Data Register P7 Port 8 Data Register P8 Port Group 0 Control Register PGOCON 251 FeH 0 0 0 0 0 0 O Port Group 1 Control Register PGicon 252
31. 02H and register 02H CLR OOH gt Register OOH OOH gt Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to OOH In the second example the statement 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH ELECTRONICS S3C825A P825A INSTRUCTION SET Complement COM dst Operation dst NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM 1 gt R1 OF8H COM QHi gt R1 07H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET S3C825A P825A CP Compare O
32. 4 P7 4 P7 7 SEG8 11 Mode Selection Bits o o inputmode 000 0045 0 1 Input mode puteup o aa Open drain output mode Push pull output mode 3 2 P7 0 P7 3 SEG4 7 Mode Selection Bits 72171 input afo ouput mode SS 1 0 P6 0 P6 3 COMO 3 and P6 4 P6 7 COM4 7 SEGO 3 Mode Selection Bits Input mode pull up Open drain output mode Push pull output mode ELECTRONICS 4 33 CONTROL REGISTERS S3C825A P825A _ Register Page Pointer DFH Set 1 Bit Identifier L7 5 4 2 o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 01010 0 1 1 jDesiaiorpage 1 Desiaiorpage2 1 1 Desiaiorpageg O Destination pages 1 Destination pageS 0 Destination page6 1 Desinaionpage7 3 0 ose ee 7 NOTE In the 53 825 microcontroller the internal register file is configured as eight pages Pages 0 7 The pages 0 6 are used for general purpose register file and page 4 is used for LCD data register or general purpose registers 4 34 ELECTRONICS S3C825A P825A CONTROL REGISTER Register Pointer 0 D6H Set 1 RESET Value 1 1 0 0 0 x Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Re
33. Oscillator control register OSCCON 20 Rw o o o Basic timer control register BTCON 211 mw System clock control register CLKCON 212 rw System flags register Facs 2 RW Register pointer 0 RP 24 Rw Register pointer 1 RW Stack pointer high byte DBH RW Stack pointer low byte RW x x x x x x x x DAH RW DBH RW ofo RW DEH RW 223 RW D7H D8H D9H DAH DBH DCH DDH DEH DFH ELECTRONICS 4 1 CONTROL REGISTERS S3C825A P825A Table 4 2 Set 1 Bank 0 Registers eee Decimal 7 6 54 3 2 SiO conoi regse SIOGON 2 mw si0 Data Register SODATA 2 em mw o o o e o o o o S10 Prescaler Register ee em mw o o o e o o o A D Converter Control Register ADCON ADDATAH x ADDATAL LCD Control Register LCON LCD Mode Register LMOD i Fs r Timer 3 Data Register low byte Timer 3 Control Register Tacon 248 mw LUARTcontolregiser UARTCON 250 FAH Rw Location FCH is not mapped Bas
34. Port 0 and 1 are 8 bit I O ports with nibble configurable pins respectively Port 0 and 1 pins are accessed directly by writing or reading the Port 0 and 1 data registers PO at location FOH and P1 at location F1H in set 1 bank 1 0 0 0 7 and P1 0 P1 7 can serve as inputs with or without pull ups as output open drain or push pull And they can serve as segment pins for LCD also Port Group 0 Control Register PGOCON Port 0 and 1 have a 8 bit control register PGOCON 0 3 for 0 0 7 and PGOCON 4 7 for P1 0 P1 7 A reset clears the PGOCON register to OOH configuring all pins to input mode Port Group 0 Control Register F9H Set 1 Bank 1 R W SEG16 SEG19 SEG28 SEG31 P0 4 P0 7 SEG20 SEG23 P1 0 P1 3 SEG24 SEG27 PGOCON bit pair pin configuration settings Input mode Input mode pull up Output mode open drain Output mode push pull NOTE The shared I O ports with LCD segments should be selected as one of two by LMOD 3 0 Figure 9 1 Port Group 0 Control Register PGOCON 9 4 ELECTRONICS S3C825A P825A PORTS PORT 2 Port 2 is an 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location F2H in set 1 bank 1 P2 0 P2 7 can serve as inputs as outputs push pull or open drain or it can be configured the following functions Low nibble pins 2 0 2 3 T2CLK T2OUT High nibble pins
35. fxx 1024 fxx 256 T3CON 2 fxx 64 fxx 8 Clear fxx 1 MUX 16 Bit Up Counter R T3CLK Read Only T3CON 1 16 Bit Comparator INTPND 3 Match 17 Ej s z y Timer 3 Buffer Register T3CON 4 3 Match T3CON 4 3 Ct T8CON Timer 3 Data Register Data BUS Figure 13 6 Timer 3 Block Diagram ELECTRONICS 13 7 16 BIT TIMER 3 S3C825A P825A NOTES 13 8 ELECTRONICS S3C825A P825A WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 1 of the watch timer control register WTCON 1 to 1 And if you want to service watch timer overflow interrupt IRQ4 vector D6H then set the WTCON 6 to 1 The watch timer overflow interrupt pending condition WTCON 0 must be cleared by software in the application s interrupt service routine by means of writing a to the WTCON O interrupt pending bit After the watch timer starts and elapses a time the watch timer interrupt pending bit WTCON 0 is automatically set to 1 and interrupt requests commence in 3 91 ms 0 25 0 5 and 1 second intervals by setting Watch timer speed selection bits WTCON 3 2 The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an int
36. hardware Descriptions has detailed information about specific hardware components of the S3C825A P825A microcontroller Also included in Part Il are electrical mechanical OTP and development tools data It has 15 chapters Chapter 7 Clock Circuit Chapter 15 LCD Controller Driver Chapter 8 RESET and Power Down Chapter 16 10 bit Analog to Digital Converter Chapter 9 Ports Chapter 17 Serial Interface Chapter 10 Basic Timer and Timer 0 Chapter 18 UART Chapter 11 Timer 1 Chapter 19 Electrical Data Chapter 12 8 bit Timer 2 Chapter 20 Mechanical Data Chapter 13 16 bit Timer 3 Chapter 21 S3P825A OTP Chapter 14 Watch Timer Chapter 22 Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C825A P825A microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3C825A P825A MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S3C8 Series Microcontrollers pue Thre eee reer reir ee eee ee ur uc ur uc ur uo ene ee eee rte ree ee ret 1 1 S3C825A Microcontroller eee 1 1 oj 1 1 50 02 NO Oe gO 1 2 Block DIAQEal tente E HEEL E Eri e UU Earle b o
37. sc 3 6 47 0 Rb opc dst 3 6 47 Rb T NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given RO 06H and general register OOH 05H LDB R0 00H2 gt RO 07H register 05H LDB 00H 0 RO gt RO 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register OOH the value 05H The statement LD R0 00H 2 loads the bit two value of the OOH register into bit zero of the RO register leaving the value 07H in register RO In the second example OOH is the destination register The statement LD 00H 0 RO0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving O4H in general register OOH ELECTRONICS 6 51 INSTRUCTION SET S3C825A P825A LDC LDE Load Memory LDC LDE dst src Operation dst src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and odd an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 10 C3 r Irr a4 dst src 2 2 10 D3 Irr r 12 E7 r
38. the LCD display is turned on If the bit value is the display is turned off Display RAM data are sent out through the segment pins SEGO SEGS 1 using the direct memory access DMA method that is synchronized with the f signal RAM addresses in this location that not used for LCD display can be allocated to general purpose use COM Bit SEGO SEG3 SEG4 SEG30 SEG31 700H 701H 702H 703H 704H 71EH 71FH Figure 15 3 LCD Display Data RAM Organization 0 Al 2 3 4 5 6 7 ELECTRONICS 15 3 LCD CONTROLLER DRIVER S3C825A P825A LCD CONTROL REGISTER LCON The LCD control register LCON is used to turn the LCD display on and off LCD frame frequency and control the flow of the current to the dividing resistors in the LCD circuit After a RESET all LCON values are cleared to 0 This turns the LCD display off and stops the flow of the current to the dividing resistors LCD Control Register LCON F2H Set 1 Bank 0 R W Not used for the S3C825A LCD clock select bits 00 fw 27 256 Hz at fw 32 768 kHz 01 fw 29 512 Hz at fw 32 768 kHz LCD display control bits 10 fw 25 1024 Hz at fw 32 768 kHz 00 Display off P Tr off 11 fw 24 2048 Hz at fw 32 768 kHz 01 Normal display Using VLc1 with external voltage P Tr off Using Vict with LCD duty and bias selection bits P Tron 00 1 3 duty 1 3 bias COMO 2 SEGO 31 01 1 4 duty 1 3 bias COMO S SEGO 31
39. 01H gt Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC OOH rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3C825A P825A INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3C825A P825A SB1 Select Bank 1 SB1 Operation BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex OpC 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3C825A
40. 4 29 CONTROL REGISTERS S3C825A P825A P5CONL Port 5 Control Register Low Byte EDH Set 1 Bank 1 Bit Identifier 6 5 4 2 o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 3 BUZ o o o 0 1 Output mode open drain S 1 0 Alternative function BUZ Output mode push pull 5 4 P5 2 SO o o Imutmde 0 1 Outputmode open drain 1 0 Alternative function SO Output mode push pull 3 2 P5 1 SI S o ouput mose openan y afoma SSS 1 0 P5 0 SCK 0 o Imutmode SCO 0 1 Output mode open drain 1 0 Alternative function SCK out Output mode push pull 4 30 ELECTRONICS S3C825A P825A CONTROL REGISTER P5PUR Port 5 Pull up Control Register EEH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only Not used for the S3C825A J 6 P5 6 Pull up Resistor Enable Bit Pull up disable Pull up enable 5 P5 5 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 4 P5 4 Pull up Resistor Enable Bit Pull up disable Pull up enable 3 P5 3 Pull up Resistor Enable Bit Pull up disable Pull up enable 2 P5 2 Pull
41. CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example 6 32 dst src RA If dst src 0 lt PC RA Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3C825A P825A INSTRUC
42. H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3C825A P825A INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation re rc 1 If r z0 PC PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using
43. LCD Mode Register woo as rw 9 Timer Counter nighbyey Fan of o o o o o o v Timers Counter ow byte tecn ss Timer 3 ContotRegisier rcov 26 o o o v o Cd UART control register Ss UARTCON 250 FAH 0 0 0 0 0 UART Bana Ra aeneae T ERa Ter E M RR KR KR ERR RR ER ER Location FCH is not mapped Basic Timer Counter 253 O j O 0 0 O Location FEH is not mapped intrapt Prony Reger ass x x x x x x x EN EN E EE Lo EN o x x ELECTRONICS 8 3 RESET and POWER DOWN S3C825A P825A Table 8 3 S3C825A Set 1 Bank 1 Register Values after RESET Dec Hex 76 5 4 2 1 2 Control Register High Byte 2 224 EH 0 0 Port 2 Control Register Low Byte P2CONL 225 0 0 0 poser ee 46 P P reer tele Register Port 2 Interrupt Control Register Pant 227 ESH 0 0 0 o o o 0 0 Port 3 Control Register High Byte PSCONH 228 EM 0 0 o Port 3 Control Register Low Byte PSCONL 229 EH 0 0 o o Port 3 Pullup Resistors enable Register PSPUR 230 EH 0 0 0 o Port 4 Interrupt Edge Selection Register 231 eH 0
44. P4 3 interrupt request is pending when read e 2 P4 2 External Interrupt INT6 Pending Flag No interrupt request pending When read Clear pending bit when write 1 P4 2 interrupt request is pending when read 41 External Interrupt INT5 Pending Flag No interrupt request pending When read Clear pending bit when write 1 P4 1 interrupt request is pending when read 0 P4 0 External Interrupt INT4 Pending Flag No interrupt request pending When read Clear pending bit when write P4 0 interrupt request is pending when read je NOTE Writing a 1 to an interrupt pending PAPND 0 7 has no effect 4 28 ELECTRONICS S3C825A P825A CONTROL REGISTER P5CONH Port 5 Control Register High Byte ECH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode ELECTRONICS Register addressing mode only TXD output control bit 0 Disable TXD output at P5 5 Enable TXD output at P5 5 RXD output control bit 0 Disable RXD output at P5 4 Enable RXD output at P5 4 P5 LO Inputmode 0 2 Not avai EX Not available 1 Output mode push pull P5 5 TXD o o mumd o namaa P5 4 RXD 0 Input mode Output mode open drain RXD output depends on P5CONH 6 o 4 9 1 Not available Output mode push pull RXD output depends on P amp CONH 6
45. PP Register Page 4 34 RPO Register Pointer uti a D POROEPPPORMSROSPEREPERI EDS 4 35 RP1 Register 1 4 35 SIOCON SIO Control Register nnne ennemis 4 36 SPH Stack Pointer High 0 244 0 4 37 SPL Stack Pointer Low 4 37 STPCON Stop Control Register sesssssissssssssssseeeeeenennnnn nnne 4 38 SYM System Mode 4 39 TOCON Timer 0 Control 4 40 Timer 1 A Control 4 41 Timer Control 4 42 T2CON Timer 2 Control 4 43 Timer 3 Control Register coercere rerit erre a eens ue re ug 4 44 UARTCON UART Control 4 45 WTCON Watch Timer Control 4 46 S3C825A P825A MICROCONTROLLER xix List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add with Carry nennen nnne trn 6 14 ADD v RS Ud hereby rior UU URL LUE 6 15 AND Logical AND RM 6 16 BAND E ha LIH 6 17 Bit
46. XOR 00H 01H XOR 00H 01H XOR 00H 54H gt 3 E RO 0C5H R1 02H RO OE4H R1 02H register 02H 23H Register 29H register 01H 02H Register OOH 08H register 01H 02H register 02H Register OOH 7FH 28H In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result in the destination register RO ELECTRONICS 6 87 INSTRUCTION SET S3C825A P825A NOTES 6 88 ELECTRONICS S3C825A P825A CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3C825A microcontroller has two oscillator circuits a main clock and a sub clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits The maximum CPU clock frequency of S8C825A is determined by register settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal ceramic resonator RC oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON STOP control register STPCON CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx main clock fxt sub clock fxx selected s
47. cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 4 91 IR Examples Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3C825A P825A RLC Rotate Left Through Carry RLC Operation dst dst 0 C C c dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples 6 72 C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Add
48. conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 5 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH ADDATAL register where it can be read The A D converter then enters an idle state Remember to read the contents of ADDATAH ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD3 input pins during a conversion procedure be kept to an absolute minimum Any change the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 16 1 A D CONVERTER S3C825A P825A CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion When fxx 8 is selected for conv
49. the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE 5 4 Levels Vectors RESET 100 IRQ1 COH C2H C4H C6H C8H CAH CCH CEH t t t NOTES 1 Sources Basic timer overflow Timer 0 match capture Timer 0 overflow Timer B match Timer 1 A match Timer 2 match Timer 3 match capture Timer 3 overflow SIO interrrupt UART data transmit UART data receive Watch timer P1 0 external interrupt P1 1 external interrupt P1 2 external interrupt P1 3 external interrupt P1 4 external interrupt P1 5 external interrupt P1 6 external interrupt P1 7 external interrupt P4 0 external interrupt P4 1 external interrupt P4 2 external interrupt P4 3 external interrupt Reset Clear H W S W H W S W S W S W S W S W H W S W S W S W S W S W S W S W S W S W S W S W S W S W S W S W S W S W Within a given interrupt level the low vect
50. 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 External Interrupt INT11 State Bit Falling edge detection 1 Rising edge detection 6 P4 6 External Interrupt INT10 State Bit Falling edge detection 1 Rising edge detection 5 P4 5 External Interrupt INT9 State Bit Falling edge detection 1 Rising edge detection 4 P4 4 External Interrupt INT8 State Bit Falling edge detection 1 Rising edge detection 3 P4 3 External Interrupt INT7 State Bit Falling edge detection 1 Rising edge detection 2 P4 2 External Interrupt INT6 State Bit Falling edge detection 1 Rising edge detection 4 External Interrupt INT5 State Bit Falling edge detection 1 Rising edge detection 0 P4 0 External Interrupt INT4 State Bit Falling edge detection 1 Rising edge detection 4 26 ELECTRONICS S3C825A P825A CONTROL REGISTER PAINT Port4 Interrupt Control Register EAH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 External Interrupt INT11 Enable Bit Disable interrupt 1 Enable interrupt 6 P4 6 External Interrupt INT10 Enable Bit Disable interrupt Enable interrupt 5 P4 5 External Interrupt INT9 Enable Bit Disable interrupt Enable interrupt 4 P4 4 External Interrupt INT8 E
51. 6 45 IRET Interrupt 6 46 JP Ano EET 6 47 JR Jump 2 6 48 LD amentiam 6 49 LDB Load Bit EIU MU 6 51 S3C825A P825A MICROCONTROLLER xxi Instruction Mnemonic LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD LDCPI LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SBO SB1 SBC SCF SRA SRP SRPO SRP1 STOP SUB SWAP TCM TM WFI XOR xxii List of Instruction Descriptions Continued Full Register Name Page Number Load 6 52 Load Memory and 6 54 Load Memory and 6 55 Load Memory with nnn 6 56 Load Memory with 6 57 load MOLd usc tud cot E cos 6 58 Multiply 6 59 MI AMETE MC Kc PEEL 6 60 NO Operation REM 6 61 Logical vaca cake naka S Akan AAA 6 62 Pop from Cope eee 6 63 Pop User Stack 6 64 Pop User Stack 6 65 PuShitO Sack i Pee esset 6 66 Push User Stack
52. 85 C Vpp 2 0 V to 5 5 V ____Test Condition fx gt 400 kHz Ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xy input high and low level width ty VDD 0 1V 0 1V Figure 19 6 Clock Timing Measurement at Xy Table 19 11 Sub Oscillator Stabilization Time TA 25 C to 85 C Vpp 2 0 V to 5 5 V Test Condition min Max Umi Gy External clock input high and low level width tcr 5 15 us VpD 0 1V 0 1V Figure 19 7 Clock Timing Measurement at XT ELECTRONICS 19 11 ELECTRICAL DATA S3C825A P825A Instruction Clock Main Oscillator Frequency 8 19 kHz Supply Voltage V CPU Clock 1 4n x oscillator frequency n 1 2 8 16 Figure 19 8 Operating Voltage Range 19 12 ELECTRONICS S3C825A P825A ELECTRICAL DATA Table 19 12 UART Timing Characteristics in Mode 0 8 MHz TA 25 C to 85 Vpp 2 0V to 5 5 V Load capacitance 80 pF Serial port clock High Low level width NOTES 1 Alltimings are in nanoseconds ns and assume a 10 MHz CPU clock frequency 2 The unit tepy means one CPU clock period Figure 19 9 Waveform for UART Timing Characteristics ELECTRONICS 19 13 S3C825A P825A ELECTRICAL DATA M tSCK J LI LI LJ LE LJ LI Ld Le M ia tH1 4 15 gt Out eism NOTE The
53. COM7 SEG3 28 segment output pins SEG4 SEG31 4 common output pins nternal resistor circuit for LCD bias pin for controlling the driver and bias voltage The LCD control register LCON is used to turn the LCD display on and off switch the current to the dividing resistors for the LCD display and frame frequency Data written to the LCD display RAM can be automatically transferred to the segment signal pins without any program control When a subsystem clock is selected as the LCD clock source the LCD display is enabled even in the main clock stop or idle mode VLC1 LCD Controller Diver COM4 COM7 SEGO SEGS3 UJ e D D UJ c SEG4 SEG31 Figure 15 1 LCD Function Diagram ELECTRONICS 15 1 LCD CONTROLLER DRIVER LCD CIRCUIT DIAGRAM 15 2 Data Bus Display RAM 3 Seed Page 7 p Timing Controller COM Control or Selector COM Control LCD Voltage Control Figure 15 2 LCD Circuit Diagram S3C825A P825A SEG31 P1 7 SEG4 P7 0 COM7 SEG3 P6 7 COM6 SEG2 P6 6 COM5 SEG1 P6 5 4 5 6 4 COM3 P6 3 2 6 2 COM1 P6 1 6 0 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses of page 7 are used as LCD data memory These locations can be addressed by 1 bit or 8 bit instructions If the bit value of a display segment is 1
54. Control Register SIOCON ELECTRONICS S3C825A P825A SERIAL I O INTERFACE SIO PRE SCALER REGISTER SIOPS The prescaler register for serial I O interface module SIOPS are located at E2H in set 1 bank 0 The value stored in the SIO pre scale register SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock fxx 4 Prescaler value 1 or SCK input clock SIO Pre scaler Register SIOPS E2H Set 1 Bank 0 R W Baud rate fxx 4 SIOPS 1 Figure 17 2 SIO Prescaler Register SIOPS SIO BLOCK DIAGRAM 3 Bit Counter SIOCON O Clear Pending SIOCON 1 SIOCON 3 Interrupt Enable SIOCON 7 SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 SCK Mode Select SIOPS E2H bank 0 CLK g Bit SIO Shift Buffer gt fxx 2 8 bit P S SIODATA E1H bank 0 SIOCON 6 LSB MSB First Mode Select B Figure 17 3 SIO Functional Block Diagram ELECTRONICS 17 3 SERIAL I O INTERFACE S3C825A P825A SERIAL I O TIMING DIAGRAM SIO Transmit IRQ3 N Complete 4 Set SIOCON 3 Figure 17 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 Transmit IRQS N Complete I Set SIOCON 3 Figure 17 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 17 4 ELECTRONICS S3C825A P825A UART UART OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is on
55. DJNZ instruction the working register being used as a counter should be set at the one of location OCOH to OCFH with SRP SRPO or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0 DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3C825A P825A El Enable Interrupts Operation Flags Format Example 6 40 SYM 0 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the EI instruction No flags are affected Bytes Cycles Opcode Hex 1 4 9F Given SYM OOH EI If the SYM regist
56. Electrical 19 5 19 4 Input O tput CGapacltariee etit Eit ERR ER ETANTE AEAN LER ERYRERR RO 19 6 19 5 Data Retention Supply Voltage in Stop Mode 19 6 19 6 A D Converter Electrical 19 8 19 7 Synchronous SIO Electrical Characteristics 224 19 9 19 8 Main Oscillator Characteristics nnn 19 10 19 9 Sub Oscillator 19 10 19 10 Main Oscillator Stabilization 1 2 nn 19 11 19 11 Sub Oscillator Stabilization Time ssssssssss nnn 19 11 19 12 UART Timing Characteristics Mode 0 8 2 19 13 21 1 Descriptions of Pins Used to Read Write the 21 4 21 2 Comparison of 53 825 and 53 825 21 4 21 3 Operating Mode Selection 21 4 22 1 Power Selection Settings for 25 22 4 22 2 The SMDS2 Tool Selection Setting 22 4 xvi S3C825A P825A MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Addre
57. Load an 8 bit value to the UARTCON control register to properly configure the UART I O module For interrupt generation set the UART I O interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit INTPND 4 or INTPND 5 is set to 1 and an UART interrupt request is generated af ELECTRONICS 18 1 UART S3C825A P825A UART CONTROL REGISTER UARTCON The control register for the UART is called UARTCON in set 1 bank 0 at address FAH It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations modes 2 and 3 only UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON UART Control Register UARTCON FAH Set 1 Bank 0 R W vso vs vso wee ve o seo we e Operating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication Received interrupt enable bit enable bit for modes 2 and 3 only 0 Disable 0 Disable 1 Enable 1 Enable Serial data receive enable Location of
58. Mode Hex dst opc dst 2 8 50 R 8 51 IR Examples Given Register 01H register 01H SPH OD8H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Register 01H register 01H 55H SP OOFCH In the first example general register OOH contains the value 01H The statement POP loads the contents of location OOFBH 55H into destination register and then increments the stack pointer by one Register OOH then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3C825A P825A POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example 6 64 dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 92 R IR Given Register OOH 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register contains the value 42H and register 42H the value 6FH the statement POPUD 02H 200H loads the contents of register 42H into the destination reg
59. O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI 6 2 Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst sr
60. P825A INSTRUCTION SET SBC subtract with Carry SBC dst src Operation dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 32 6 33 r Ir opc SIC dst 3 6 34 R R 6 35 R IR opc dst SIC 3 6 36 R IM Examples Given R1 10H R2 1 register 01H 20H register 02H and register OAH SBC R1 R2 SBC R1 R2 R1 OCH R2 03H R1 05H R2 register OAH SBC 01H 02H Reg
61. Read Write lt TBDATA TADATA gt NOTE When 7 is 1 16 bit timer 1 Figure 11 2 Timer 1 Functional Block Diagram ELECTRONICS 11 3 TIMER 1 S3C825A P825A TWO 8 BIT TIMERS MODE TIMER A and B OVERVIEW The 8 bit timer A and B are the 8 bit general purpose timers Timer A and B support interval timer mode using appropriate TACON and TBCON setting respectively Timer A and B have the following functional components Clock frequency divider with multiplexer fxx divided by 256 64 8 or 1 and T1CLK External clock for timer A fxx divided by 256 64 8 or 1 for timer B 8 bit counter TACNT TBCNT 8 bit comparator and 8 bit reference data register TADATA TBDATA Timer A match interrupt IRQ1 vector E6H generation Timer A control register TACON set 1 bank 0 EBH read write Timer B match interrupt IRQ1 vector E4H generation Timer B control register TBCON set 1 bank 0 EAH read write FUNCTION DESCRIPTION Interval Timer Function The timer A and B module can generate an interrupt the timer A match interrupt TAINT and the timer B match interrupt TBINT TAINT belongs to the interrupt level IRQ1 and is assigned a separate vector address E6H TBINT belongs to the interrupt level IRQ1 and is assigned a separate vector address E4H The TAINT and TBINT pending condition should be cleared by software after they are serviced In interval timer mode a match si
62. SIO interrupt an 2 7 external interrupt IRQ5 P2 6 external interrupt 218 P2 5 external interrupt 216 P2 4 external interrupt 198 P4 7 external interrupt 196 P4 6 external interrupt 194 P4 5 external interrupt 192 P4 4 external interrupt P4 3 external interrupt IRQ7 P4 2 external interrupt P4 1 external interrupt P4 0 external interrupt NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 ftwo or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware N N OJO N OOJO N W 5 6 ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTER
63. Set 1 Bank 0 Bank 1 LCD Data Register Area CPU and system control General purpose w Peripheral and I O LCD data register Figure 2 4 Set 1 Set 2 Prime Area Register and LCD Data Register Map ELECTRONICS 2 7 ADDRESS SPACES S3C825A P825A WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 working register block is 16 bytes sixteen 8 bit working registers 15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file T
64. Set 1 Read only IR IRQ2 d IRQ3 IROS IRQ4 IRQ6 IRQ7 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C8254 interrupt structure the timer 0 overflow interrupt IRQO and Timer overflow interrupt IRQ2 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pen
65. XS rr e dst src XS 12 F7 5 dst src XL XL 4 14 A7 r XL rr 6 opc src dst XL XL 4 14 B7 XL rr r 7 dst 0000 DA DA 4 14 A7 r DA 9 opc dst 0001 DA DAY 4 14 A7 r DA 10 opc src 0001 DA DAY 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats and 4 the destination address XS rr and the source address are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA and r source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory 6 52 ELECTRONICS S3C825A P825A LDC LDE Load Memory LDC LDE Continued INSTRUCTION SET Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC LDE LDC note LDE LDC LDE LDC note LDE LDC LDE LDC LDE LDC note LDE RO RR2 RO RR2 RR2 R0 RR2 R0 RO 01H RR2 RO 01H RR2 01H RR2 RO 01H RR2 RO O00H RR2 000H RR2 R0 1104H R0 1104H 1105H RO 1105H RO RO lt contents of program
66. are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one affer a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 15 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the S8C825A the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only st
67. are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3C825A P825A ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3C825A P825A INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H
68. but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used ELECTRONICS S3C825A P825A INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3C825A P825A ADC Add with carry ADC Operation Flags Format Examples dst src dst lt dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffecte
69. by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 E3 Examples Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 RR6 is incremented by one RR6 lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3C825A P825A LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples 6 56 dst src m m 41 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location Th
70. completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 1 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected 1 Bank 1 is selected 4 8 ELECTRONICS S3C825A P825A CONTROL REGISTER IMR Interrupt Mask Register DDH Set 1 RESET Value x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit P4 0 P4 3 Disable mask 1 Enable unmask 6 Interrupt Level 6 IRQ6 Enable Bit P4 4 P4 7 Disable mask le Enable unmask 5 Interrupt Level 5 IRQ5 Enable Bit P2 4 P2 7 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit Watch Timer Disable mask 1 Enable unmask 3 Interrupt Level IRQ3 Enable Bit SIO UART Transmit UART Receive Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Enable Bit Timer 2 Timer 3 match capture or overflow Disable mask 1 Enable unmask Interrupt Level 1 IRQ1 Enable Bit Timer Timer 1 Disable mask 1 Enable unmask 0 Interrupt Level 0 IRQO Enable Bit Timer 0 Match Capture or Overflow Disable mas
71. dod eto eee te ia le el e eoe o e e ice i oiu e e A lA a 12 1 Function 5 12 1 Timer 2 Control Register 12 2 BlockcDIagraitis Ite Deu A 12 3 Chapter 13 16 bit Timer 3 QUI p 13 1 Timer Counter Control Register 13 1 Timer Function Description 13 4 Chapter 14 Watch Timer OVOIVIO Ws ds solcher o Mab Gee Seta dea 14 1 Watch Timer Control Register 7 14 2 Watch Timer Circuit 14 3 Chapter 15 LCD Controller Driver OVEIVICW RM 15 1 ECD Circuits Diagram DI EIE 15 2 EGD Ram Address Arearen en o dn ee b DP PP E E Ee E D 15 3 GD Gontrol Begister aie sume a ne an ce 15 4 LCD Mode Control Register LMOD F3H at Bank 0 of Set 1 15 5 LCD Voltage Dividing 15 6 viii S3C825A P825A MICROCONTROLLER Table of Contents Continued Chapter 16 10 bit Analog to Digital Converter
72. dst src dst dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 22 r r SIC 6 23 r Ir opc SIC dst 3 6 24 R R 6 25 R IR opc dst SIC 3 6 26 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H 1EH register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H OBCH C and S 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtr
73. edges Rx at rising edges le Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit Disable shifter and clock counter 1 Enable shifter and clock counter SIO Interrupt Enable Disable SIO Interrupt Enable SIO Interrupt 1 0 SIO Interrupt Pending Bit No interrupt pending Clear pending condition when write 1 Interrupt is pending 4 36 ELECTRONICS S3C825A P825A CONTROL REGISTER SPH stack Pointer High Byte D8H Set 1 RESET Value X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 RESET Value x x Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 0 ELECTRONICS Register addressing mode only Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0O The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 37 CONTROL REGISTERS S3
74. generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P5 4 pin will cause the UART module to start the serial data receive operation Write to Shift Register UDATA i tw UR NUS oe ace RIP Figure 18 7 Timing Diagram for Serial Port Mode 1 Operation 18 8 ELECTRONICS S3C825A P825A UART SERIAL PORT MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 clock frequency Mode 2 Transmit Procedure 1 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to or 1 2 Write transmission data to the shift register UDATA F9H set 1 bank 0 to start the transmit operation Mode 2 Receive Procedure 1 Select mode 2 and set the receive e
75. interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C825A P825A INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El 5 Q Interrupt Request Register Read only RESET R IRQO IRQ7 Interrupts Interrupt Priority Register Interrupt Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3C825A P825A PERIPHERAL INTERRUPT CONTROL REGISTERS INTERRUPT STRUCTURE For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in
76. into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3C825A P825A Table 6 2 Flag Notation Conventions Flag Description C Z S V D H 0 1 6 8 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3C825A P825A INSTRUCTION SET Table 6 4 Instruction N
77. is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 O NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS S3C825A P825A INSTRUCTION SET BITC Bit Complement BITC dst b Operation dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to O Undefined Unaffected Unaffected Flags TOSONO Format Bytes Cycles Opcode Addr Mode Hex dst 4 57 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address is thre
78. is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3C825A P825A ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Program Memory Address Used Next OPCODE Co s PC Value gt Displacement Current Instruction OPCODE Signed a Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3C825A P825A IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample In
79. only 4 Serial Data Receive Enable Bit 0 3 TB8 Location of the 9th data bit to be transmitted in UART mode 2 or 3 0 or 1 2 RB8 Location of the 9th data bit to be received UART mode 2 or 3 0 or 1 Receive Interrupt Enable Bit Disable Rx interrupt Enable Rx interrupt 0 Transmit Interrupt Enable Bit 0 Disable Tx interrupt Enable Tx interrupt NOTES 1 In mode 2 or 3 if the MCE bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit 0 In mode 1 if MCE 1 the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Rx Txinterrupt pending bits are in INTPND register ELECTRONICS 4 A CONTROL REGISTERS S3C825A P825A WTCON Watch Timer Control Register EFH Set 1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 Watch Timer Clock Selection Bit 79 Select main clock divided by 27 fx 128 Select sub clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 3 2 Watch Timer Speed Selection Bits 0 0 Set waton timer interuptto 1s 0 1 Set waton timer interuptto 0 55s o _1 0 Set waton timer
80. order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 14 ELECTRONICS S3C825A P825A ADDRESS SPACES Selects RPO or RP1 Address OPCODE 1 1 4 bit address Register pointer provides three provides five low order bits high order bits LE MM did Together they create an 8 bit register address Figure 2 11 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register 01110 address 044 201 444 0 NOH 76H Figure 2 12 4 Bit Working Register Addressing Example ELECTRONICS 2 15 ADDRESS SPACES S3C825A P825A 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8
81. sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS S3C825A P825A INSTRUCTION SET STOP Stop Operation STOP Operation Flags Format Example The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F The statement STOP halts all microcontroller operations NOP NOP NOP ELECTRONICS 6 81 INSTRUCTION SET S3C825A P825A SUB Subtract SUB Operation Flags Format Examples 6 82
82. src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3C825A P825A INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD dst src Operation IR IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst SIC 3 8 82 IR R Example Given Register OOH 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register 02H register 01H 05H register 2 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leavin
83. symbols shown in this diagram are defined as follows fSCK 151 152 tH1 tH2 gt tH2 Serial port clock cycle time Output data setup to clock rising edge Clock rising edge to input data valid Output data hold after clock rising edge Input data hold after clock rising edge Figure 19 10 A C Timing Waveform for the UART Module ELECTRONICS 19 14 S3C825A P825A MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C825A microcontroller is currently available in 80 pin QFP and TQFP package 23 90 0 30 80 QFP 1420C e 0 10 MAX o e a N 0 80 0 20 0 35 0 10 9 15 15 MAX 2 65 x 0 10 3 00 MAX 0 80 0 20 ossoa NOTE Dimensions are in millimeters Figure 20 1 Package Dimensions 80 QFP 1420C ELECTRONICS 20 1 MECHANICAL DATA S3C825A P825A 14 00 BSC 0 09 0 20 80 TQFP 1212 14 00 BSC 12 00 BSC 0 60 0 15 Jr 1 00 0 05 1 20 MAX NOTE Dimensions are in millimeters Figure 20 2 Package Dimension 80 TQFP 1212 20 2 ELECTRONICS S3C825A P825A 53 825 OTP 2 1 S3P825A OTP OVERVIEW The S3P825A single chip CMOS microcontroller is the OTP One Time Programmable version of the S8C825A microcontroller It has an on chip OTP ROM instead of a masked ROM The EPROM is accessed by serial data format The S3P825A is fully compatible with the S3C825A both in function in D C electrical characteristics and
84. the 9th data bit that was 0 Disable received in UART mode 2 or 3 0 or 1 1 Enable Location of the 9th data bit to be transmitted in UART mode 2 or 3 or 1 MS1 50 Mode Description Baud Rate Shift register fxx 16 x BRDATA 1 8 bit UART fxx 16 x BRDATA 1 9 bit UART fxx 16 9 bit UART fxx 16 x BRDATA 1 NOTES 1 In mode 2 or 3 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received In mode 0 the UARTCON 5 bit should be 0 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Figure 18 1 UART Control Register UARTCON 18 2 ELECTRONICS S3C825A P825A UART UART INTERRUPT PENDING BITS The UART interrupt pending bits INTPND 5 4 are located in set 1 bank 0 at address DOH it contains the UART data transmit interrupt pending bit INTPND 4 and the receive interrupt pending bit INTPND 5 In mode 0 the receive interrupt pending bit INTPND 5 is set to 1 when the 8th receive data bit has been shifted In mode 1 2 and 3 the INTPND 5 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the INTPND 5 bit must then be cleared by software in the int
85. the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3C825A P825A INSTRUCTION SET CCF Complement Carry Flag CCF Operation C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if 0 the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3C825A P825A CLR Clear CLR dst Operation dst 0 Flags Format Examples 6 28 The destination location is cleared to O No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register register 01H
86. the timer 3 match capture interrupt T3INT T3OVF is belongs to interrupt level IRQ2 vector ECH T3INT also belongs to interrupt level IRQ2 but is assigned the separate vector address EAH A timer 3 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND 2 interrupt pending bit However the timer 3 match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a 0 to the INTPND 3 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer reference data register T3DATAH T3DATAL The match signal generates a timer match interrupt vector EAH and clears the counter If for example you write the value 1087H to T3DATAH TSDATAL the counter will increment until it reaches 1087H At this point the timer interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer 3 output pin is inverted see Figure 13 3 Interrupt Enable Disable T3CON 1 16 Bit Up Counter lt lt IRQ2 16 Bit Comparator Match INT Capture Signal TSOUT P3 6 Timer 3 Buffer Register 4 3 Timer 3 Data Register Figure 13 3 S
87. 0 Timer 0 overflow interrupt enable bit 001 fxx 256 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrupt 011 fxx 8 100 fxx Timer 0 match capture interrupt enable bit 101 External clock 0 Disable interrupt P2 4 TOCLK falling edge 1 Enable interrupt 110 External clock P2 4 TOCLK rising edge 111 Counter stop Timer 0 counter clear bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 operating mode selection bits 00 Interval mode P3 7 TOOUT 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF and match interrupt can occur Figure 10 3 Timer 0 Control Register TOCON 10 6 ELECTRONICS S3C825A P825A BASIC TIMER and TIMER 0 Interrupt Pending Register INTPND DOH Set 1 Bank 0 R W Not used Timer 0 overflow interrupt pending bit Timer 0 match capture interrupt pending bit Timer 3 overflow interrupt pending bit Timer 3 match capture interrupt pending bit Tx interrupt pending bit for UART Rx interrupt pending bit for UART 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 10 4 Interrupt Pending Register INTPND ELECTRONICS 10 7 BASIC TIMER and TIMER 0 S3C825A P825A TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts IRQO Vectors and E2H The timer 0 ca
88. 0H gt Register 00H 98H C 1 RR gt Register 01H 02H register 02H 8BH C 1 In the first example if general register contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3C825A P825A RRC Rotate Right Through Carry RRC Operation dst dst 7 C C lt dst 0 dst n lt dst n 1 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples 6 74 C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 R 4 C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register OOH 2 1 RRC
89. 10 Ippo mode Vpp 5 V 10 Crystal oscillator C1 C2 22pF 4 0 Wax Unis 36 9 ss 25 Eel WE ERN 32kHz Crystal oscillator mode Vpp 3 V 10 32kHz Crystal oscillator Ipps Stop mode 5 V 10 TA 25 C Stop mode Vpp 3 V 10 25 C NOTES 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors and ADC Ipp4 and include power consumption for subsystem clock oscillation Ipp4 are current when main system clock oscillation stops and the subsystem clock is used Ipps is current when main system clock and subsystem clock oscillation stops oP ON Every values in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11B 19 4 ELECTRONICS S3C825A P825A ELECTRICAL DATA Table 19 3 A C Electrical Characteristics 25 C to 85 C Vpp 2 0 V to 5 5 V ma Interrupt input high low tINTH 5 width tINTL 2 4 2 7 4 0 4 7 l9 Figure 19 1 Input Timing for External Interrupts P2 4 P2 7 P4 Figure 19 2 Input Timing for RESET ELECTRONICS 19 5 ELECTRICAL DATA S3C825A P825A Table 19 4 Input Output Capacitance TA 25 C to 85 C Vop 0V Input Cin f 1 MHz unmeasured pins capacitance are returned to Vss Outp
90. 10 1 8 duty 1 4 bias COMO 7 SEG4 31 11 1 8 duty 1 5 bias 7 5 4 31 11 Normal display internal voltage Figure 15 4 LCD Control Register LCON 15 4 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER LCD MODE CONTROL REGISTER LMOD F3H at BANK 0 of SET 1 Table 15 1 LCD Mode Control Register LMOD Organization LMOD 7 4 Not used for the S3C825A LMOD 3 0 0000 All I O port PO P1 6 8 0001 Select LCD COMO 3 4 7 5 0 3 P1 P7 and P8 are I O port 0010 Select LCD COMO 3 4 7 5 0 3 SEG4 7 PO P1 P7 4 P7 7 and P8 are I O port 0011 Select LCD COMO 3 COM4 7 SEG0 3 SEG4 11 P1 and P8 are I O port 0100 Select LCD COMO 3 COM4 7 SEG0 3 SEG4 15 PO and P1are I O port 0101 Select LCD COMO 3 COM4 7 SEG0 3 SEG4 19 P0 4 PO0 7 and P1 are I O port 0110 Select LCD 3 COM4 7 SEG0 3 SEG4 23 P1 is I O port 0111 Select LCD COMO 3 COM4 7 SEGO0 3 SEG4 27 P1 4 P1 7 is port 1000 Select LCD 3 4 7 5 0 3 SEG4 31 NOTE The COM4 7 SEGO 3 signals are controlled by LCON 3 2 ELECTRONICS 15 5 LCD CONTROLLER DRIVER S3C825A P825A LCD VOLTAGE DIVIDING RESISTORS On chip voltage dividing resistors for the LCD drive power supply are fixed to the Vi c4 Vi c5 pins Figure 15 5 shows the bias connections for the S30825A LCD drive power supply To cut off the flow of current through the dividing resistor manip
91. 21 S3 C825A P825A 032002 USER S MANUAL S3C825A P825A 8 Bit CMOS Microcontroller Revision 1 ELECTRONICS 53 825 825 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C825A P825A 8 Bit CMOS Microcontrollers User s Manual Revision 1 Publication Number 21 S3 C825A P825A 032002 2002 Samsung Electronics Typical parameters can and do vary in different applica
92. 25A P825A JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true PC PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LABEL_X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3C825A P825A INSTRUCTION SET LD Load LD dst src Operation dst src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 rC r r8 r dst 2 4 9 R r
93. 25A P825A SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the set 1 address D4H It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W TTA IS IIIS must keep always 0 must keep always 0 Oscillator IRQ wake up Divide by selection bits for function bit CPU clock frequency 0 Enable IRQ for main 00 fxx 16 wake up in power down mode 01 fxx 8 1 Disable IRQ for main 10 fxx 2 wake up in power down mode 11 fxx 1 non divided Figure 7 7 System Clock Control Register CLKCON 7 4 ELECTRONICS S3C825A P825A CLOCK CIRCUIT OSCILLATOR CONTROL REGISTER OSCCON The oscillator control register OSCCON is located in set 1 bank 0 at address D2H It is read write addressable and has the following functions System clock selection Main oscillator control Sub oscillator control OSCCON O register settings select Main clock or Sub clock as system clock After a reset Main clock is selected for system clock because the reset value of OSCCON O is 0 The main oscillator can be stopped or run by setting OSCCON 3 The sub oscillator can be stopped or run by set
94. 5535 ELECTRONICS 6 9 INSTRUCTION SET S3C825A P825A Table 6 5 Opcode Quick Reference EM ND E MON NOE DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM ro Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 12 R2 R1 IR2 R1 R1 IM r2 b RA 4 DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM ro Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 12 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x rl A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 112 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 112 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA 2 IA1 IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs ELECT
95. 5A INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE dst src RA Operation If dst src 0 PC RA Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 7 C row NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Example Given R1 02H R2 and register 03H 02H R1 R2 SKIP R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3C825A P825A
96. 8 2 SEG14 71 L3 P8 1 SEG13 70 L3 P8 0 SEG12 69 L3 P7 7 SEG11 68 2 P7 6 SEG10 67 L3 P7 5 SEG9 66 L3 P7 4 SEG8 65 L3 P7 3 SEG7 P0 7 SEG23 P7 2 SEG6 P1 0 SEG24 P7 1 SEG5 P1 1 SEG25 P7 0 SEG4 P1 2 SEG26 P6 7 SEG3 COM7 P1 3 SEG27 P6 6 SEG2 COM6 P1 4 SEG28 P6 5 SEG1 COM5 P1 5 SEG29 P6 4 SEG0 COM4 P1 6 SEG30 P6 3 COM3 P1 7 SEG31 P6 2 COM2 SDAT P2 0 P6 1 COM1 SCLK P2 1 P6 0 COMO VDD VDD1 S3P825A VDD2 Vss Vssi Vss2 80 QFP 1420C XIN VPP TEST XTIN XTOUT RESET RESET P2 2 T2CLK P2 3 T2OUT P2 4 INTO TOCLK P4 7 INT11 P4 6 INT10 P4 5 INT9 P2 5 INT1 T1CLK P2 6 INT2 TAOUT P4 3 P4 4 P3 5 T3CLK CJ 33 P4 1 P4 2 P2 7 INT3 TBOUT 25 P3 6 T3OUT T3PWM T3CAP Lj 34 P3 7 TOOUT TOPWM TOCAP Cj 35 Figure 21 2 S3P825A Pin Assignments 80 Pin QFP Package ELECTRONICS 21 3 53 825 OTP S3C825A P825A Table 21 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming P2 0 SDAT 8 10 Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port 21 1 SCLK Serial clock pin Input only pin TEST 4 16 Power supply pin for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option RESET RESET 17 19 1 Chip Initialization Chip Chip Initialization Vpp1 Vssi Vp
97. 825A P825A A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10 bit digital values The analog input level must lie between the and values A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type ADC control register ADCON Four multiplexed analog data input pins ADO AD3 10 bit A D conversion data output register ADDATAH ADDATAL 4 bit digital input port Alternately I O port FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must set with alternative function for ADC input enable at port 3 the pin set with alternative function can be used for ADC analog input And you write the channel selection data in the A D converter control register ADCON 4 5 to select one of the four analog input pins 0 3 and set the conversion start or enable bit ADCON O The read write ADCON register is located in set 1 bank 0 at address EFH The pins witch are not used for ADC can be used for normal I O During a normal conversion ADC logic initially sets the successive approximation register to 800H the approximate half way point of an 10 bit register This register is then updated automatically during each
98. Addressing Modes Addressing Modes Modes m Can be Pointed by Register Pointer Can be Pointed by register Pointer Figure 2 9 Register File Addressing 2 12 ELECTRONICS S3C825A P825A ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages LCD Data Registers Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH Figure 2 10 Common Working Register Area ELECTRONICS 2 13 ADDRESS SPACES S3C825A P825A I PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0C0OH LD R2 40H R2 the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead S
99. Addressing for Load 22 3 10 3 11 Direct Addressing for Call and Jump 3 11 3 12 Indirect 0 3 12 3 13 Relative 0 3 13 3 14 Immediate 0 110 3 14 S3C825A P825A MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 4 1 Register Description 4 4 5 1 S3C8 Series Interrupt 5 2 5 2 S8C825A Interrupt 5 4 5 3 ROM Vector Address 5 5 5 4 Interrupt Function nennen 5 8 5 5 System Mode Register 5 1 5 10 5 6 Interrupt Mask Register 5 11 5 7 Interrupt Request Priority 5 12 5 8 Interrupt Priority Register 2022 5 13 5 9 Interrupt Request Register nnns 5 14 6 1 System Flags Register 5 6 6 7 1 Crystal Ceramic Oscillator 0 7 2 7 2 External Oscillator nnn nnns 7 2 7 3 RG OScillator fX eC an ani ae aa ana 7 2 7 4 Crystal Ceramic Oscillator 7 2 7 5 External Oscillator
100. All ports of the S3C825A be configured to input or output mode and PO P6 P8 are shared with LCD signals Table 9 1 gives you a general overview of the 53 825 1 0 port functions ELECTRONICS 9 1 PORTS S3C825A P825A Table 9 1 S3C825A Port Configuration Overview Configuration Options 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull ups P0 0 P0 7 can alternately be used as outputs for LCD segment signals 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull ups 1 0 1 7 can alternately be used as outputs for LCD segment signals 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups P2 4 P2 7 can be used as input for external interrupts INTO INT3 with noise filer and interrupt control and can alternately be used as TOCLK T1CLK TAOUT and TBOUT 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups Alternately 0 7 can be used as ADO AD3 T3CLK T30UT T3PWM T3CAP TOOUT TOPWM TOCAP 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups 4 0 4 7 can alternately be used as inputs for external interrupts I
101. BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3C825A P825A BTJRT sit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b is a 1 then PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3C825A P825A INSTRUCTION SET BXOR Bit XOR BXOR dst src b BXOR
102. C825A P825A STPCON Stop Control Register D1H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated 4 38 ELECTRONICS S3C825A P825A CONTROL REGISTER SYM System Mode Register DEH Set 1 RESET Value 0 E x x x 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used But you must keep 0 6 5 Not used for the S3C825A 4 2 Fast Interrupt Level Selection Bits 1 Fast Interrupt Enable Bit 2 Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 9 Disable all interrupt processing Enable all interrupt processing NOTES 1 You select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O ELECTRONICS 4 39 CONTROL REGISTERS S3C825A P825A TOCON Timer 0 Control Register E5H Set 1 Bank 0 Bit Identifier RESET
103. C825A S3C825A S3C825A Figure 18 10 Connection Example for Multiprocessor Serial Data Communications 18 12 ELECTRONICS S3C825A P825A ELECTRICAL DATA OVERVIEW In this chapter S3C8254A electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings D C electrical characteristics A C electrical characteristics Input output capacitance Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode Serial I O timing characteristics A D converter electrical characteristics ELECTRONICS ELECTRICAL DATA 19 1 ELECTRICAL DATA S3C825A P825A Table 19 1 Absolute Maximum Ratings 25 C Input voltage Output voltage 0 3 0 3 All I O pins active One I O pin active Total pin current for port 100 Table 19 2 D C Electrical Characteristics V V Output current low Output current high One I O pin active o JE TA 25 C to 85 Vpp 2 0 V to 5 5 V Operating voltage fx 0 4 4 MHz 32 8 kHz fx 0 4 8 MHz Input high voltage Ports 0 8 0 8 Vpp RESET 08 Xin XTn Vpp 0 1 Input low voltage Ports 0 8 4 RESET Xour XTn Output high voltage Vpp 4 5 V to 5 5 V All output ports lt o lt lt lt o
104. CON O OVE INTPND O IRQO Data BUS fxx 1024 pou256 TOCON 2 fxx 8 CI ear fxx 1 MUX 8 Bit Up Counter R TOCLK Read Only s 8 Bit Comparator INTPND 1 Match i i V Timer 0 Buffer Register X a TOCON 4 3 Match TOCON 4 3 Ct TOCON Timer 0 Data Register Data BUS Figure 10 8 Timer 0 Block Diagram ELECTRONICS 10 11 BASIC TIMER and TIMER 0 S3C825A P825A NOTES 10 12 ELECTRONICS S3C825A P825A TIMER 1 TIMER 1 ONE 16 BIT TIMER MODE TIMER 1 The 16 bit timer 1 is used in one 16 bit timer or two 8 bit timers mode When TACON 7 is set to 1 it is in one 16 bit timer mode When TACON 7 is set to 0 the timer 1 is used as two 8 bit timers One 16 bit timer mode Timer 1 Two 8 bit timers mode Timer A and B OVERVIEW The 16 bit timer 1 is an 16 bit general purpose timer Timer 1 includes interval timer mode using appropriate TACON setting Timer 1 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 and T1CLK External clock with multiplexer 16 bit counter TACNT TBCNT 16 bit comparator and 16 bit reference data register TADATA TBDATA Timer 1 match interrupt IRQ1 vector E6H generation Timer 1 control register TACON set 1 bank 0 EBH read write FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt the timer 1 match inte
105. ECTRONICS S3C825A P825A CONTROL REGISTER CLKCON System Clock Control Register D4H Set 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 Oscillator IRQ Wake up Function Bit Enable IRQ for main wake up in power down mode Disable IRQ for main wake up in power down mode 6 5 Not used for the S8C825A 4 3 CPU Clock System Clock Selection Bits note LO tede ooo 2 0 Not used for the S8C825A NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS S3C825A P825A FLAGS System Flags Register D5H Set 1 RESET Value X X X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only N arry Flag Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value 1 Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Q 5 1 Operation generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D Add operation
106. FLAGS prime is copied automatically back to the FLAGS register 7 The fast interrupt status bit in FLAGS is cleared automatically Relationship to Interrupt Pending Bit Types As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends 5 18 ELECTRONICS S3C825A P825A INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAMB8 microcontrollers There 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special instructions I
107. GISTER P3CONH Port 3 Control Register High Byte E4H Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 TOOUT TOPWM TOCAP 0 o inputmode TOCAP Output mode open drain 0 Output mode open drain 1 0 Alternative function TOOUT TOPWM Output mode push pull 5 4 P3 6 T3OUT T3PWM T3CAP o Input mode T3CAP EXER Output mode open drain 1 0 Alternative function TJOUT T3PWM Output mode push pull 3 2 P3 5 T3CLK 79111 ouput moge open drain 1 0 4 o o inputmode 00 00 1 Outputmode open drain o 1 0 Not availabe o ELECTRONICS 4 21 CONTROL REGISTERS S3C825A P825A P3CONL Port 3 Control Register Low Byte E5H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 AD3 o 1 Output mode open drain 1 0 Alternative function ADC mode Output mode push pull 5 4 P3 2 AD2 o 0 1 Outputmode open drain 1 0 Alternative function ADC mode Output mode push pull 3 2 P3 1 AD1 Fo o mwmd S ouput mose openan ooOOSSOS S 71129 Aternatve function ADC mode 1 0 P3 0 ADO o
108. ICS S3C825A P825A PORTS PORT 6 7 8 Port 6 and 7 are 8 bit I O port and port 8 is 4 bit I O port with nibble configurable pins respectively Port 6 7 and 8 pins are accessed directly by writing or reading the port 6 7 and 8 data registers P6 at location F6H P7 at location F7H and P8 at location F8H in set 1 bank 1 6 0 6 7 P7 0 P7 7 and 8 0 8 3 can serve as inputs with or without pull ups as output open drain or push pull And they can serve as segment or common pins for LCD also Port Group 1 Control Register PG1CON Port 6 7 and 8 have an 8 bit control register PG1CON 0 1 for 6 0 6 7 PG1CON 2 5 for 7 0 7 7 and PG1CON 6 7 for 8 0 8 3 A reset clears the PG1CON register to configuring all pins to input mode Port Group 1 Control Register FAH Set 1 Bank 1 R W mM 0 P6 7 M M 8 SEG P7 4 P7 7 SEG4 SEG7 SEG8 SEG11 P8 0 P8 3 SEG12 SEG15 PG1CON bit pair pin configuration settings Input mode Input mode pull up Output mode open drain Output mode push pull NOTE Refer to LCD mode control register Figure 9 17 Port Group 1 Control Register PG1CON ELECTRONICS 9 15 PORTS S3C825A P825A NOTES 9 16 ELECTRONICS S3C825A P825A BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3C825A has two default timers an 8 bit basic timer and one 8 bit general purpose timer counter The 8 bit timer count
109. Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3C825A P825A INDIRECT REGISTER ADDRESSING MODE Continued Register File REGISTER Example Instruction References OPCODE Points to Program Peaster Pel 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3C825A P825A ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File ae 1 gt RPO or RP1 eee Selected RP points Program Memory to start fo i working register ee block dst i Working Register gt Point to the ADDRESS Address Working Register tef MENTI Value used in OPERAND eee B Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3C825A P825A INDIRECT REGISTER ADDRESSING MODE Concluded Register File RPO RPO or 1 Selected RP points to start of working register pup We Program Memory 4 bit Working Register Address Lo e c Register Next 2 bit Point Pair p op ee References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data
110. NT4 INT11 with noise filter and interrupt control 1 bit programmable port Schmitt trigger input or push pull open drain output mode selected by software software assignable pull ups Alternately 5 0 5 5 can be used as SCK SI SO BUZ RXD and TXD 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull ups P6 0 P6 7 can alternately be used as outputs for LCD signals 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull ups P7 0 P7 7 can alternately be used as outputs for LCD segment signals 4 bit programmable I O port Input or push pull open drain output mode selected by software software assignable pull ups P8 0 P8 3 can alternately be used as outputs for LCD segment signals 9 2 ELECTRONICS S3C825A P825A PORTS PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all nine S3C825A I O port data registers Data registers for ports 0 1 2 3 4 5 6 7 and 8 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location RW Fon O aata regser Po xo Fo Ww Port 6 data register 246 Seti Baki RW Port 8 data register 8 28 Set Banki RW ELECTRONICS 9 3 PORTS S3C825A P825A PORT 1
111. OM TEST VDD1 VDD2 2064 byte Register File VSS1 VSS2 Figure 1 1 Block Diagram 10 bit ADC PRODUCT OVERVIEW P0 0 PO 7 SEG16 SEG23 P1 0 P1 7 SEG24 SEG31 P2 0 P2 1 P2 2 T2CLK P2 3 T2OUT P2 4 INTO TOCLK P2 5 INT1 T1CLK P2 6 INT2 TAOUT P2 7 INTS TBOUT P3 0 ADO P3 1 AD1 P3 2 AD2 P3 3 AD3 P3 4 P3 5 T3CLK P3 6 T3QUT P P3 6 T3OUT P3 7 TOOUT TOPWM TOCAP 4 0 4 7 INT4 INT11 P5 0 SCK 5 1 5 5 2 50 P5 3 BUZ P5 4 RXD P5 5 TXD 6 0 6 1 1 6 2 2 P6 3 COM3 P6 4 COM4 SEGO P6 5 COMS SEG1 P6 6 COM6 SEG2 P6 7 COM7 SEG3 P7 0 P7 7 SEG4 SEG11 P8 0 P8 3 SEG12 SEG15 P3 0 P3 3 ADO AD3 PRODUCT OVERVIEW PIN ASSIGNMENT P1 1 SEG25 P1 2 SEG26 P1 3 SEG27 P1 4 SEG28 P1 5 SEG29 P1 6 SEG30 P1 7 SEG31 P2 0 P2 1 VDD1 551 XOUT XIN TEST XTIN XTouT RESET P2 2 T2CLK P2 3 T2OUT P2 4 INTO TOCLK 1 4 P0 2 SEG18 7 0 1 5 17 P0 0 SEG16 P8 1 SEG13 P8 0 SEG12 P7 7 SEG11 P7 6 SEG10 P7 5 SEG9 P7 4 SEG8 P7 3 SEG7 P7 2 SEG6 P7 1 SEG5 74 73 72 Ea P1 0 SEG24 79 P0 7 SEG23 PO 6 SEG22 gt gt 5 921 P0 4 SEG20 P0 3 SEG19 31 P8 3 SEG15 P8 2 SEG14 76 75 70 69 68 67 FA 66 65 64 r3 63 FA 62 61 S3C825A 80 1212 P2 5 INTI TICLK 21 P2 6 INT2 TAOUT 22 2 7 Cd 23 P3 5 T3CLK 04 31 P3 6 T3OUT
112. Operation Flags Format Examples 6 26 dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 Given RO 35H R1 21H 1A47H and SP 0002H CALL 3521H SP 0000 Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO SP 0000H 0000H 0001H 49H CALL 40H 9 SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are
113. OtoF 2 4 C7 r D7 Ir E5 R dst src 3 6 E6 R D6 IR opc SIC dst 3 6 F5 IR 3 6 87 r opc 3 6 9 ELECTRONICS sre IM R x r 6 49 S3C825A P825A INSTRUCTION SET L D Load LD Continued Examples Given RO 01H R1 OAH register 01H register 01H 20H register 02H 02H LOOP and register OFFH LD LD LD LD LD LD LD LD LD LD LD LD 6 50 RO 10H R0 01H 01H RO R1 RO QRO R1 00H 01H 02H 00H 00H 0AH 00H 10H 00H 02H gt RO LOOP R1 gt LOOP RO R1 bobo tb bt bk RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register 01H Register OOH OAH Register 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 OAH Register OAH RO 01H R1 OAH ELECTRONICS S3C825A P825A INSTRUCTION SET LDB Load Bit LDB dst src b LDB dst b src Operation dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc sbio
114. P2 4 P2 7 TOCLK TAOUT TBOUT 0 Port 2 Control Registers P2CONH P2CONL Port 2 has two 8 bit control registers P2CONH for P2 4 P2 7 and P2CONL for 2 0 2 3 A reset clears the P2CONH and P2CONL registers to 00H configuring P2 4 P2 7 pins to input mode with interrupt on falling edge and 2 0 2 3 pins to input mode You use control registers setting to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module Port 2 Pull Up Resistor Control Register P2PUR Using the port2 pull up resistor control register P2PUR E2H set 1 bank 1 you can configure pull up resistors to individual port 2 pins Port 2 Interrupt Control Registers P2INT To process external interrupts at the port 2 pins a additional control register is provided the port 2 interrupt control register P2INT E3H set 1 bank 1 The port 2 interrupt control register P2INT lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P2INT register at regular intervals When the interrupt enable bit of any port 2 pin is 1 a falling edge at that pin will generate an in
115. P825A INSTRUCTION SET ADD Add ADD dst src Operation dst dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Setif a carry from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 02 6 03 r Ir opc SIC dst 3 6 04 R R 05 R IR opc dst SIC 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3C825A P825A AND Logical AND AND Operation Flags Format Examples
116. PACES System and Peripheral Control Registers Register Addressing Mode System Registers Register Addressing Mode Working Registers Working Register Addressing Only Page 7 32 Prime Data Registers Bytes All Addressing Modes 00H LCD Display Register S3C825A P825A Page 0 Set 2 Registers Indirect Register Indexed Mode and Stack Operations Page 0 Prime Data Registers All Addressing Modes Figure 2 2 Internal Register File Organization 2 4 ELECTRONICS S3C825A P825A ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3C825A microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source Page 0 NOTE hardware reset operation writes the 4 bit destination an
117. Pull up enable mi ELECTRONICS 4 CONTROL REGISTERS S3C825A P825A P2INT Port2 Interrupt Control Register ESH Set 1 Bank 1 Bit Identifier o8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Port 2 Interrupt Request Pending Bit P2 7 INT3 No interrupt request pending Clear pending bit when write Interrupt request is pending 6 Interrupt Control Settings P2 7 INT3 Disable interrupt P2 7 Enable interrupt at falling edge on P2 7 5 Port 2 Interrupt Request Pending Bit P2 6 INT2 No interrupt request pending 0 Clear pending bit when write Interrupt request is pending 4 Interrupt Control Settings P2 6 INT2 Disable interrupt on P2 6 Enable interrupt at falling edge on P2 6 3 Port 2 Interrupt Request Pending Bit P2 5 INT1 No interrupt request pending Clear pending bit when write 1 Interrupt request is pending 2 Interrupt Control Settings P2 5 INT1 Disable interrupt P2 5 Enable interrupt at falling edge on P2 5 1 Port 2 Interrupt Request Pending Bit P2 4 INTO No interrupt request pending 0 Clear pending bit when write Interrupt request is pending 0 Interrupt Control Settings P2 4 INTO Disable interrupt 2 4 Enable interrupt at falling edge P2 4 4 20 ELECTRONICS S3C825A P825A CONTROL RE
118. R 3 S3C825A P825A Capture Mode In capture mode a signal edge that is detected at the T3CAP P3 6 pin opens a gate and loads the current counter value into the timer 3 data register You can select rising or falling edges to trigger this operation Timer 3 also gives you capture input source the signal edge at the T3CAP P3 6 pin You select the capture input by setting the values of the timer capture input selection bits in the port control register PSCONH 5 4 set 1 bank 1 E4H When PSCONH 5 4 is 00 the T3CAP input is selected Both kinds of timer 3 interrupts can be used in capture mode the timer 3 overflow interrupt is generated whenever a counter overflow occurs the timer 3 match capture interrupt is generated whenever the counter value is loaded into the timer 3 data register By reading the captured data value in T3DATAH T3DATAL and assuming a specific value for the timer clock frequency you can calculate the pulse width duration of the signal that is being input at the T3CAP pin see Figure 13 5 T3CON 0 T3OVF IRQ2 16 Bit Up Counter INTPND 2 Overflow INT Interrupt Enable Disable T3CON 1 IRQ2 T3CAP input INTPND 3 Capture INT P3 6 Match Signal Pending 4 3 4 3 Timer Data Register Figure 13 5 Simplified Timer 3 Function Diagram Capture Mode 13 6 ELECTRONICS S3C825A P825A 16 BIT TIMER 3 0 OVF INTPND 2 IRQ2 Data BUS
119. R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 contents of is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 RR6 1 7FH contents of RO is loaded into external data memory location 2200H 21FFH 1H RO R6 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET S3C825A P825A LDW Load Word LDW Operation Flags Format Examples 6 58 dst src dst src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 C4 RR RR 8 C5 RR IR opc dst SIC 4 8 C6 RR IML 05H R7 02H register 1AH Given R4 06 R5 1CH R6 03H and register OFH register 01H 02H register 02H LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 00H 03H register 01H OFH register 02H register OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register 00H and the va
120. REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W status flag BA Carry flag C Fast interrupt Zero flag 2 status flag FIS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3C825A P825A INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operati
121. RONICS S3C825A P825A INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3C825A P825A CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes _ 0000 Always false 1000 Always true 0111 note Carry 1111 note No carry 0110 note Zero 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal note Il note OO I o N ll O a O O a S S V V Z N 1001 Greater than or equal 0001 1010 0010 1111 note 0111 note 1011 0011 NOTES Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal OR 0 1 V V NWN GD OO x O O T 1 It indicates condition codes that are related to two different mnemonics
122. RP 0COH ADD R3 45H R3 lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low
123. RUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When fast interrupt occurs the contents of the FLAGS register is stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3C825A microcontroller the service routine for any one of the eight interrupt levels 0 IRQ7 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced ron gt Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS
124. Register D2H Set 1 Bank 0 Bit Identifier RESET Value Read Write 7 4 6 5 3 2 9 x 0 0 0 R W R W R W Not used for S3C825A Main Oscillator Control Bit Main oscillator RUN Main oscillator STOP Sub Oscillator Control Bit Sub oscillator RUN 1 Sub oscillator STOP Not used for S8C825A System Clock Selection Bit Select main oscillator for system clock 1 Select sub oscillator for system clock ELECTRONICS S3C825A P825A CONTROL REGISTER P2CONH Port 2 Contro Register High Byte EOH Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 INT3 TBOUT Input mode interrupt on falling edge EXER Output mode open drain 1 0 Alternative function TBOUT Output mode push pull 5 4 P2 6 INT2 TAOUT Input mode interrupt on falling edge EXER Output mode open drain 1 0 Alternative function TAOUT Output mode push pull 3 2 P2 5 INT1 T1CLK Input mode interrupt on falling edge 0 1 Output mode open drain 1 0 Notavaitabe 1 0 P2 4 INTO TOCLK Input mode TOCLK interrupt on falling edge 0 1 Output mode open drain 1 0 Notavaiiable o ELECTRONICS 4 17 CONTROL REGISTERS S3C825A P825A P2CONL Port 2 Control Regist
125. S In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register iw RW Function Description Interrupt mask register IMR R W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQ0 IRQ7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The eight levels of 53 825 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W This register enables disables fast interrupt processing and dynamic global interrupt processing NOTE Before IMR register is changed to any value all
126. S3C825A P825A 8 BIT TIMER 2 BLOCK DIAGRAM Bits 7 6 5 Data Bus T2CLK _ P2 2 fxx 256 8 bit up Counter R 64 Read Only fxx 8 Pendin fxx 1 Timer 2 Buffer Register Counter clear signal T2CON 3 Match signal Timer 2 Data Register Read Write Data Bus Figure 12 2 Timer 2 Functional Block Diagram ELECTRONICS 12 3 8 BIT 2 S3C825A P825A NOTES 12 4 ELECTRONICS S3C825A P825A 16 BIT TIMER 3 16 BIT TIMER 3 OVERVIEW Timer counter 3 has three operating modes one of which you select using the appropriate T3CON setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P3 6 pin PWM mode Timer counter 3 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input P3 5 T3CLK 16 bit counter T3CNTH T3CNTL 16 bit comparator and 16 bit reference data register T3DATAH T3DATAL I O pins for capture input match output PWM output P3 6 T3CAP P3 6 T3OUT P3 6 T3PWM Timer 3 overflow interrupt IRQ2 vector ECH and match capture interrupt IRQ2 vector EAH generation Timer 3 control register T3CON set 1 F8H bank 0 read write TIMER COUNTER 3 CONTROL REGISTER T3CON You use the timer 3 control register T3CON to Select the timer 3 operating mode interval timer capture mode or PWM mode Select the timer 3 input clock frequency Clear th
127. SET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 1P8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET Value X X X x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located the IPH register DAH ELECTRONICS 4 11 CONTROL REGISTERS S3C825A P825A IPR Interrupt Priority Register FFH Set 1 Bank 0 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A and C note Fo 0 Groupprionty undeined oneee O o lojes oO o i ssas Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priorit
128. Set 1 Timer 0 overflow Timer 0 match capture Timer 1 A match Timer B match Timer 3 overflow Timer 3 match capture Timer 2 match UART data receive UART data transmit SIO interrupt P2 7 external interrupt P2 6 external interrupt P2 5 external interrupt P2 4 external interrupt P4 7 external interrupt P4 6 external interrupt P4 5 external interrupt P4 4 external interrupt P4 3 external interrupt P4 2 external interrupt P4 1 external interrupt P4 0 external interrupt ELECTRONICS IRQ3 TOCON TOCNT TODATA INTPND T3CNTH T3CNTL T3DATAL T2CON 2 T2DATA UARTCON UDATA BRDATA SIOCON SIODATA SIOPS IRQ5 P2CONH P2INT IRQ7 P4CONH P4INT P4PND P4EDGE P4CONL P4INT 4PND P4EDGE E5H bank 0 bank 0 E4H bank 0 DOH bank 0 EBH bank 0 E7H bank 0 9 E6H bank 0 E8H bank 0 F8H bank 0 F4H F5H bank 0 F6H F7H bank 0 EEH bank 0 ECH bank 0 EDH bank 0 FAH bank 0 F9H bank 0 FBH bank 0 bank 0 E1H bank 0 E2H bank 0 bank 1 E3H bank 1 E8H bank 1 EAH bank 1 EBH bank 1 E7H bank 1 E9H bank 1 EAH bank 1 EBH bank 1 E7H bank 1 5 9 INTERRUPT STRUCTURE S3C825A P825A SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5
129. Sirm D ToS 16 1 FUNCHON DESC TION cs RICE 16 1 TIMIN iret to 16 2 A D Converter Control Register 16 2 Internal Reference Voltage eene nnne nennen n nnn nter sss 16 3 io fore 16 3 Chapter 17 Serial I O Interface OVIE Wasa coca Ra tact Ud E 17 1 Programming 2 17 1 SIO Control Registers 17 2 SIO Pre Scaler Register 17 3 SIO BIOCIG DIAGEAE a at eat te DU SUE UIS RENE AN 17 3 Serial I O Timing Diagram 5100 17 4 Chapter 18 UART VS VIS Wetten aeu yee ceva ae eee let ag reteset 18 1 Programming 2 0 nennen nnn n nsns 18 1 UART Control Register 18 2 UART Interrupt Pending iesu te ae dees 18 3 VAR T Data Register Waal o tie are dean Oita a Arh Danas D DEDE te at 18 4 UART Baud Rate Data Register
130. T3 TBOUT P3 0 ADO P3 2 AD2 AVss P3 5 T3CLK P3 7 TOOUT TOPWM TOCAP P4 1 INT5 P4 3 INT7 P4 5 INT9 P4 7 INT11 P5 1 SI P5 3 BUZ P5 5 TXD VLC1 VDD2 P6 1 COM1 P6 3 COM3 P6 5 SEG1 COM5 P6 7 SEG3 COM7 P7 1 SEG5 P7 3 SEG7 P7 5 SEG9 P7 7 SEG11 P8 1 SEG13 P8 3 SEG15 P0 1 SEG17 PO 3 SEG19 P0 5 SEG21 P0 7 SEG23 10198uu0o 0 J10198uu0o Utd 0t DEVELOPMENT TOOLS P1 2 SEG26 P1 4 SEG28 P1 6 SEG30 P2 0 VDD1 XOUT TEST XTouT P2 2 T2CLK P2 4 INTO TOCLK P2 6 INT2 TAOUT AVREF P3 1 AD1 P3 3 AD3 P3 4 P3 6 T3OUT T3PWM T3CAP P4 0 INT4 P4 2 INT6 P4 4 INT8 P4 6 INT10 P5 0 SCK P5 2 SO P5 4 RXD P5 6 Vss2 P6 0 COMO P6 2 COM2 P6 4 SEG0 COM4 P6 6 SEG2 COM6 P7 0 SEG4 P7 2 SEG6 P7 4 SEG8 P7 6 SEG10 P8 0 SEG12 P8 2 SEG14 P0 0 SEG16 P0 2 SEG18 P0 4 SEG20 P0 6 SEG22 P1 0 SEG24 Figure 22 3 40 Pin Connectors J101 J102 for TB825A ELECTRONICS 22 5 DEVELOPMENT TOOLS S3C825A P825A Target Board Target System J101 J102 J102 J101 1 2 41 42 41 42 1 2 Target Cable for 40 Pin Connector Part Name AS40D A Order Code SM6306 39 40 79 80 79 80 39 40 Figure 22 4 S3C825A Cables for 80 TQFP Package S10 98UU09 Id 0 A 2 0 5 70 o 5 9 22 6 ELECTRONICS
131. T3PWM T3CAP 32 P3 7 TOOUT TOPWM TOCAP Cj 33 Figure 1 2 S3C825A Pin Assignments 80 TQFP 1212 S3C825A P825A P7 0 SEG4 P6 7 SEG3 COM7 P6 6 SEG2 COM6 P6 5 SEG1 COM5 P6 4 SEG0 COM4 P6 3 COM3 P6 2 COM2 P6 1 COM1 P6 0 COMO VDD2 Vss2 P4 7 INT11 ELECTRONICS S3C825A P825A P0 7 SEG23 P1 0 SEG24 P1 1 SEG25 P1 2 SEG26 P1 3 SEG27 P1 4 SEG28 P1 5 SEG29 P1 6 SEG30 P1 7 SEG31 P2 0 P2 1 VDD1 551 XOUT XIN TEST XTIN XTOUT RESET P2 2 T2CLK P2 3 T2OUT P2 4 INTO TOCLK P2 5 INT1 T1CLK P2 6 INT2 TAOUT ELECTRONICS 80 L3 PO0 6 SEG22 79 L3 0 5 5 21 78 PO 4 SEG20 77 PO 3 SEG19 76 PO 2 SEG18 75 L3 PO 1 SEG17 74 L3 PO 0 SEG16 73 L3 P8 3 SEG15 72 L3 P8 2 SEG14 71 L3 P8 1 SEG13 70 L3 P8 0 SEG12 69 L3 P7 7 SEG11 68 L3 P7 6 SEG10 67 L3 P7 5 SEG9 66 3 P7 4 SEG8 65 L3 P7 3 SEG7 S3C825A 80 QFP 1420C P3 0 ADO 27 P3 1 AD1 C4 28 P3 2 AD2 29 P3 3 AD3 cJ 30 P4 1 P4 2 P3 5 T3CLK CJ 33 P4 0 P2 7 INT3 TBOUT 25 P3 6 T3OUT T3PWM T3CAP Lj 34 P3 7 TOOUT TOPWM TOCAP 4 35 Figure 1 3 S3C825A Pin Assignments 80 QFP 1420 PRODUCT OVERVIEW P7 2 SEG6 P7 1 SEG5 P7 0 SEG4 P6 7 SEG3 COM7 P6 6 SEG2 COM6 P6 5 SEG1 COM5 P6 4 SEG0 COM4 P6 3 COM3 P6 2 COM2 P6 1 COM1 P6 0 COMO VDD2 Vss2 P4 7 INT11 P4 6 INT10 P4 5 INT9 1 5 PRODUCT OVERVIEW S3C825A P825A PIN DESCRIPTIONS 0 0 0 7 1 0 1 7 2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6
132. TAH ADDATAL FOH F1H Set 1 Bank 0 Read Only e 5 eos eon Figure 16 2 A D Converter Data Register ADDATAH ADDATAL INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range to AVper Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AVper BLOCK DIAGRAM ADCON 2 1 ADCON 4 5 i Select one input pin of the assigned pins Clock To ADCON 3 Selector EOC Flag ADCON O AD C Enable Analog S Input Pins Comparator uccessive ADO AD3 Approximation P3 0 P3 3 Logic amp Register ADCON O AD C Enable P3CONL Assign Pins to ADC Input Conversion Result 10 bit D A ADDATAH ADDATAL Converter FOH F1H Set 1 Bank 0 Figure 16 3 A D Converter Functional Block Diagram ELECTRONICS 16 3 A D CONVERTER S3C825A P825A Reference Voltage Input AVREF lt VDD Analog ADO AD3 Input Pin S3C825A Figure 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 4 ELECTRONICS S3C825A P825A SERIAL I O INTERFACE SERIAL I O INTERFACE OVERVIEW Serial modules SIO can interface with various types of external device that require s
133. TION SET DA Decimal Adjust DA dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 06 0 SBC 1 7 F 0 0 9 AO 60 1 1 6 1 6 9A 66 1 Flags C Set if there was a carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3C825A P825A DA Decimal Adjust DA Example 6 34 Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO C e H lt 0 Bits 4 7 3 bits 0 3 C R1 3CH DA R1 R1
134. Timer B counter value is cleared to Immediately following the write operation the TBCON 3 value is automatically cleared to O 4 42 ELECTRONICS S3C825A P825A CONTROL REGISTER T2CON Timer 2 Control Register EEH Set 1 Bank 0 Bit Identifier RESET Value Read Write Addressing Mode 7 5 5 4 3 2 4 9 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer 2 Input Clock Selection Bits External clock T2CLK input Not used for the S3C825A er 2 Counter Clear Bit Note No effect Ti 3 1 Clear the timer 2 counter when write Timer 2 Counter Enable Bit Disable counting operation 1 Enable counting operation Timer 2 Interrupt Enable Bit Disable timer 2 interrupt 1 Enable timer 2 interrupt Timer 2 Interrupt Pending Bit No timer 2 interrupt pending when read Clear timer 2 interrupt pending bit when write T2 interrupt is pending NOTE When you write a 1 to T2CON 3 the timer 2 counter value is cleared to OOH Immediately following the write operation the T2CON 3 value is automatically cleared to 0 ELECTRONICS 4 43 CONTROL REGISTERS S3C825A P825A T3CON Timer 3 Control Register F8H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 3 Input Clock Selection Bits
135. Value Read Write Addressing Mode 7 5 8 4 3 2 4 9 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer 0 Input Clock Selection Bits ooo LOO 1 tws ooo a EO Pw ooo 110060000002 1 1 External clock TOCLK falling edge 1 1 0 External clock TOCLK rising edge Timer 0 Operating Mode Selection Bits Interval mode Lo 4 Capture mode capture on rising edge counter running OVF can occur 1 Capture mode capture on falling edge counter running OVF can occur 1 PWM mode OVF amp match interrupt can occur Timer 0 Counter Clear Bit No effect Clear the timer 0 counter when write Timer 0 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt Timer 0 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt NOTE When you write a 1 to TOCON 2 the timer 0 counter value is cleared to OOH Immediately following the write operation the TOCON 2 value is automatically cleared to O 4 40 S3C825A P825A CONTROL REGISTER TACON Timer 1 A Control Register EBH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Timer 1 Operating Mode Selection Bit Two 8 bit timers mode Timer A B One 16 bit timer mode Timer 1 6 4 Timer 1 A Clock Selecti
136. a Out Output N Channel P Channel I 4 N Channel Disable Figure 1 4 Pin Circuit Type A Figure 1 6 Pin Circuit Type C VDD Open Drain Pull up VDD Resistor lt Pull up Enable Pull up P CH Resistor iei Disable Schmitt Trigger Schmitt Trigger Figure 1 5 Pin Circuit Type B RESET Figure 1 7 Pin Circuit Type E 4 P2 P3 4 P3 7 P4 P5 1 8 ELECTRONICS S3C825A P825A Pull up Enable Open drain Data Output Disable ADCEN ADC Select Data Circuit Type C Figure 1 8 Pin Circuit Type F 16 P3 0 P3 3 Open Drain Data Output Disable1 COM SEG Output Disable2 Circuit Type H 23 PRODUCT OVERVIEW COM SEG Output Disable VLCA4 VLC5 Vss Figure 1 9 Pin Circuit Type H 23 VDD Pull up VDD Resistor lt Resistor Enable P CH Figure 1 10 Pin Circuit Type H 32 P0 P1 P6 P8 ELECTRONICS 1 9 PRODUCT OVERVIEW S3C825A P825A NOTES 1 10 ELECTRONICS S3C825A P825A ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C825A microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The 53 825 has an internal 48 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes
137. ack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 2 18 ELECTRONICS S3C825A P825A ADDRESS SPACES I PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP ELECTRONICS SPL 0FFH PP RPO RP1 R3 R3 RP1 RPO PP SPL lt FFH Normally the SPL is set to OFFH by the initialization routine Stack address OFEH PP Stack address OFDH lt RPO Stack address OFCH lt Stack address OFBH R3 R3 lt Stack address OFBH lt Stack address OFCH RPO lt Stack address OFDH PP lt Stack address 2 19 ADDRESS SPACES S3C825A P825A NOTES 2 20 ELECTRONICS S3C825A P825A ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the pro
138. acts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS S3C825A P825A INSTRUCTION SET SWAP Swap Nibbles SWAP dst Operation dst 0 3 lt gt dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped Flags C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 4 F1 IR Examples Given Register OOH register 02H 03H and register OA4H SWAP OOH gt Register OOH OE3H SWAP 02H gt Register 02H register In the first example if general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value 1110001 1B ELECTRONICS 6 83 INSTRUCTION SET S3C825A P825A TCM rest Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the so
139. al device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S Type 3 One level IRQn multiple vectors V4 V multiple sources 5 Sh S S nai nem In the S3C825A microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 vt 91 51 2 S2 S3 Sn 51 3 IRQn 52 NOTES 1 The number of Sn and Vn value is expandable 2 n the S8C825A implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE S3C825A INTERRUPT STRUCTURE The S3C825A microcontroller supports twenty three interrupt sources All twenty three of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level
140. arts until it ends 2 lapc 5 an operating current of A D converter 19 8 ELECTRONICS S3C825A P825A ELECTRICAL DATA Table 19 7 Synchronous SIO Electrical Characteristics T4 25 C to 85 C Vpp 2 0 V to 5 5 V Mm Max Unit SCK cycle time External SCK source ns we SCK high low width tk External SCK source Internal SCK source w 50 SI setup time to External SCK source SI hold time to External SCK source Output Data Figure 19 5 Serial Data Transfer Timing ELECTRONICS 19 9 ELECTRICAL DATA S3C825A P825A Table 19 8 Main Oscillator Characteristics 25 C to 85 C Crystal Main oscillation 22V 55V frequency 2 0V 55V Ceramic Main oscillation 2 2 5 5 V frequency External clock Xin input 2 29V 5 5 V frequency 2 0 V 5 5 V Frequency 30V 04 T wc puc Table 19 9 Sub Oscillator Characteristics 25 85 Crystal Sub oscillation 2 0 V 5 5 V 32 768 frequency External clock XT jy input 2 0 V 5 5 V frequency exp 19 10 ELECTRONICS S3C825A P825A ELECTRICAL DATA Table 19 10 Main Oscillator Stabilization Time TA 25 C to
141. b NOTE Inthe second byte of the instruction format the destination address is four bits the bit address is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R13 o R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111 ELECTRONICS 6 21 INSTRUCTION SET S3C825A P825A BOR Bit or BOR BOR Operation Flags Format Examples 6 22 dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IO ONO Bytes Cycles Opcode Addr Mode Hex dst src 3 6 6 07 Rb r0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is bit Given R1 07H and register 01H BOR R1 01H 1 R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the f
142. bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These address bits indicate 8 bit 8 bit logical working register address addressing Register pointer hree low order bits provides five high order bits LT TTT tt ty Do 8 bit physical address Figure 2 13 8 Bit Working Register Addressing 2 16 ELECTRONICS S3C825A P825A ADDRESS SPACES RPO Selects RP1 R11 8 bit address Register 1100 form instruction 10101 01 1 address LD R11 R2 OABH Specifies working register addressing Figure 2 14 8 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES S3C825A P825A SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C825A architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC
143. c dst src dst src dst src dst dst src dst src src dst src dst src S3C825A P825A Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONICS S3C825A P825A INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3C825A P825A Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump
144. cted Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR A1 IR Examples Given RO R1 02H register 02H OFH and register 03H INCW RRO gt RO 1AH R1 03H INCW QHR1 gt Register 02H 10H register OOH In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H and register 02H from OFH to 10H NOTE A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3C825A P825A IRET Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal IRET Fast FLAGS SP PC o IP SP lt SP 1 FLAGS lt FLAGS PC SP FIS 0 SP lt SP 2 SYM 0 lt 1 This instruction is used at the of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of t
145. d Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Setif there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 2 4 12 EL 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H register OAH R1 R2 E R1 14H R2 03H R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H gt gt 01H 02H Register 01H 2BH register 02H 03H ADC 01H 11H Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3C825A
146. d source values shown above to the register page pointer These values should be modified to address other pages Figure 2 3 Register Page Pointer PP I PROGRAMMING TIP Using the Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination lt 0 Source 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD PP 10H Destination lt 1 Source lt 0 LD RO 0FFH Page 1 clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR RO 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program ELECTRONICS 2 5 ADDRESS SPACES S3C825A P825A REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contains 57 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers i
147. d 15 H respectively SRPO 80H RPO 80H ADD RO R1 RO lt RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO RO ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles 2 10 ELECTRONICS S3C825A P825A ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte wo
148. d so on When the IMR bit of an interrupt level is cleared to interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W Interrupt level enable bits 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3C825A P825A INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups b
149. ding bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register ELECTRONICS 5 15 INTERRUPT STRUCTURE S3C825A P825A INTERRUPT SOURCE POLLING SEQUENCE The NO a e gt gt interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The Poe dq us CPU then initiates an interrupt machine cycle that completes the fol
150. dst b src Operation dst 0 lt dst 0 XOR src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Flags IOZONO Format Bytes Cycles Opcode Addr Mode Hex dst src opc sbio sc 3 6 27 0 opc dst 3 6 27 Rb T NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 0000001 1B BXOR HR1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3C825A P825A CALL Call Procedure CALL
151. e lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements I PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange lt 48H SRPO 0A0H RPO RP1 lt nochange CLR RPO RPO lt OOH c nochange LD RP1 0F8H RPO lt nochange lt OF8H Register File Contains 32 8 Byte Slices 00001XXX 8 Byte Slice 16 Byte RPT Contiguous Working 00000XXX 8 Byte Slice Register block RPO Figure 2 6 Contiguous 16 Byte Working Register Block ELECTRONICS 2 9 ADDRESS SPACES S3C825A P825A 8 Byte Slice Register File 16 Byte Contains 32 Contiguous 11110 XXX 8 Byte Slices working Register block RPO 00000 XXX 8 Byte Slice RP1 Figure 2 7 Non Contiguous 16 Byte Working Register Block E PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H an
152. e bits and the LSB address value is one bit in length Example Given R1 07H BITC R11 o R1 05H If working register R1 contains the value 07H 000001 11B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101 in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3C825A P825A Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst 4 7 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H R11 o R1 05H If the value of working register R1 is 07H 00000111B the statement R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3C825A P825A INSTRUCTION SET BITS sit set BITS dst b Operation dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst 4 7 r
153. e contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes an even number for program memory and odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F2 r Given RO 77H R6 30H and R7 OOH LDCPD RR 6 RO RR6 RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR 6 RO RR6 RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONICS S3C825A P825A INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI dst src Operation rr rm 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Im or Examples Given RO 7FH
154. e synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Serial with baud rate of fxx 16 x BRDATA 1 8 bit UART mode variable baud rate 9 UART mode fxx 16 9 bit UART mode variable baud rate UART receive and transmit buffers are both accessed via the data register UDATA is set 1 bank 0 at address 9 Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received one of the bytes will be lost In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit INTPND 5 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 2 and 3 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P5 4 and P5 5 to alternative function RxD P5 4 TxD P5 5 for UART module by setting the P5CONH register to appropriatly value
155. e timer counter T3CNTH T3CNTL Enable the timer 3 overflow interrupt or timer 3 match capture interrupt Clear timer 3 match capture interrupt pending condition ELECTRONICS 13 1 16 BIT TIMER 3 S3C825A P825A T3CON is located in set 1 bank 0 at address F8H and is read write addressable using Register addressing mode A reset clears T3CON to OOH This sets timer 3 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 3 interrupts You can clear the timer 3 counter at any time during normal operation by writing a 1 to 2 The timer overflow interrupt T3OVF is interrupt level IRQ2 and has the vector address When a timer overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer 3 match capture interrupt IRQ2 vector EAH you must write T3CON 1 to 1 To detect a match capture interrupt pending condition the application program polls INTPND 3 When a 1 is detected a timer 3 match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer 3 match capture interrupt pending bit INTPND 3 Timer 3 Control Register T3CON F8H Set 1 Bank 0 R W Timer 3 input clock selection bits Timer 3 overflow interrupt enable bit 000 fxx 1024 0 Disable ove
156. ected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 42 6 43 r Ir opc SIC dst 3 6 44 R R 45 R IR opc dst SIC 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR R0 R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01H 00H gt Register OOH 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in destination register The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3C825A P825A INSTRUCTION SET POP Pop From Stack POP dst Operation dst SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one Flags No flags affected Format Bytes Cycles Opcode Addr
157. ed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea Box 37 Suwon 440 900 TEL 82 31 209 1934 FAX 82 31 209 1899 Home Page http www samsungsemi com Printed in the Republic of Korea Preface The S3C825A P825A Microcontroller User s Manual is designed for application designers and programmers who are using the S3C825A P825A microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C825A P825A with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed de
158. egister Figure 10 5 Simplified Timer 0 Function Diagram Interval Timer Mode 10 8 ELECTRONICS S3C825A P825A BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TOPWM P3 7 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer O data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although you can use the match signal to generate a timer 0 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TOPWM P3 7 pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to x 256 see Figure 10 6 TOCON O Capture Signal Interrupt Enable Disable B us TOCON 1 8 Bit Up Counter lt INTPND O Overflow INT TOINT IRQO INTPND 1 8 Bit Comparator INTPND 1 Match INT Pending TOPWM Output P3 7 Timer 0 Buffer Register TOCON 4 3 High level when Match Signal data gt counter lt lt 2 Lower level when TOOVF data lt counter Figure 10 6 Simpl
159. egister F2H Set 1 Bank 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode 7 and 6 5 and 4 3 and 2 1 and 0 Register addressing mode only LCD Display Control Bits o Display of tro Normal display using V c4 with external voltage P Tr off Normal display using V with internal voltage P Tr on Not used for the S3C825A LCD Duty and Bias Selection Bits 0 1 3 duty 1 3 bias COMO COM2 SEGO SEG31 1 1 4 duty 1 3 bias COM0 COM3 SEGO SEG31 1 0 1 8 duty 1 4 bias COM0 COM7 SEG4 SEG31 1 8 duty 1 5 bias COM0 COM7 SEG4 SEG31 LCD Clock Selection Bits 0 tw 27 256 Hz when fw is 32 768 kHz fw 28 512 Hz when fw is 32 768 kHz 1 fw 25 1 024 Hz when fw is 32 768 kHz fw 24 2 048 Hz when fw is 32 768 kHz ELECTRONICS S3C825A P825A CONTROL REGISTER LMOD LCD Mode Control Register F3H Set 1 Bank 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S3C825A 3 0 LCD Port Selection Bit P6 0 P6 4 P7 0 P7 4 P8 0 PO O PO 4 P1 0 P1 4 6 3 6 7 P7 3 P7 7 P8 3 PO 7 P1 3 P1 7 Port 1101010 NOTE The SEGO SEG3 or COM4 COM7 signals are controlled by LCON 3 2 ELECTRONICS 4 15 CONTROL REGISTERS S3C825A P825A OSCCON oscillator Control
160. er Low Byte E1H Set 1 Bank 1 Bit Identifier o8 4 3 2 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 2 3 200 ofo o 0 1 Output mode open drain o 1 0 Alternative function T2OUT Output mode push pull 5 4 P2 2 T2CLK o o Fo 1 ouput mose open drain SSS 3 2 P2 1 Fo o mwmd SSS 1 0 2 0 o 0 1 Outputmode open drain 1 0 Not availabe o 4 18 ELECTRONICS S3C825A P825A CONTROL REGISTER P2PUR Port 2 Pull up Control Register E2H Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P2 7 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 6 P2 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 P2 5 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 P2 4 Pull up Resistor Enable Bit Pull up disable Pull up enable 3 P2 3 Pull up Resistor Enable Bit Pull up disable Pull up enable 2 P2 2 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 1 P2 1 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 0 P2 0 Pull up Resistor Enable Bit Pull up disable 1
161. er contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM O is the enable bit for global interrupt processing ELECTRONICS S3C825A P825A INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 lt IP IP IP IP IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows one example of how to use an ENTER statement Before After Address Address Data IP IP Address Address Data PC 40 Enter PC 40 Enter 1F 41 Address 41 Address 01 42 Address L 42 AddressL 10 43 Address H 43 Address 20 110 Routine 21 IPL 50 22 Data 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3C825A P825A EXIT Exit EXIT Operation Flags Format Example 6 42 IP SP SP e SP 2 PC lt QlP P IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruc
162. er is called timer 0 BASIC TIMER BT You can use the basic timer BT in two different ways 5 a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a reset or a stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write ELECTRONICS 10 1 BASIC TIMER and TIMER 0 S3C825A P825A BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to OOH This enables the watchdog function and selects a basic timer clock frequency of fxx 4096 To disable the watchdog function you must write the signature code 1010 to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for all timers input clock you write a 1 to
163. erial data transfer The components of SIO function block are 8 bit control register SIOCON Clock selector logic 8 bit data buffer SIODATA 8 bit prescaler SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input output pin SCK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps 1 Configure the I O pins at port SCK SI SO by loading the appropriate value to the PSCONL register if necessary Load an 8 bit value to the SIOCON control register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON to 1 When you transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 are set to 1 and SIO interrupt request is generated ELECTRONICS 17 1 SERIAL I O INTERFACE SIO CONTROL REGISTERS SIOCON S3C825A P825A The control register for serial I O interface module SIOCON is located at EOH in set 1 bank 0 It has the control setting for SIO module Interrupt e
164. eripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS S3C825A P825A PORTS I O PORTS OVERVIEW The S3C825A microcontroller has four bit programmable and five nibble programmable ports PO P8 The port 0 4 6 and 7 are 8 bit ports the port 5 is 7 bit port and the port 8 is 4 bit port This gives a total of 67 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required
165. ernal program memory and for external data memory when implemented Register File RPO or RP1 Value used in 1 points to Instruction MN working register block Program Memory 4 Base Address Address dst src E Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3C825A P825A INDEXED ADDRESSING MODE Continued Register File P T NR RPO or RP1 RPO or RP1 Selected RP points to start of Program Memory 22 OFFSET i NEXT 2 Bits 4 bit Working dst src x L Register Register Address Point to Working Pair block Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in em Sample Instructions LDC R4 404H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS S3C825A P825A ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File orna cu RPO or RP1 RPO or RP1 Selected o o RP points to start of working register BEEN block Prog
166. errupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller f Therefore if the watch timer is disabled the LCD controller does not operate Watch timer has the following functional components Real Time and Watch Time Measurement Using a Main Clock Source or Sub clock Clock Source Generation for LCD Controller f O pin for Buzzer Output Frequency Generator P5 3 BUZ Timing Tests in High Speed Mode Watch timer overflow interrupt IRQ4 vector D6H generation Watch timer control register WTCON set 1 bank 1 EFH read write ELECTRONICS 14 1 WATCH TIMER S3C825A P825A WATCH TIMER CONTROL REGISTER WTCON The watch timer control register WTCON is used to select the watch timer interrupt time and Buzzer signal to enable or disable the watch timer function It is located in set 1 bank 1 at address EFH and is read write addressable using register addressing mode A reset clears WTCON to 00H This disable the watch timer So if you want to use the watch timer you must write appropriate value to WTCON Watch Timer Control Register WTCON EFH Set 1 Bank 1 R W Watch timer clock selection bit M timer interrupt pending bit 0 Select main clock divided by 2 fx 128 0 Interrupt request is not pending 1 Select Sub clock fxt Clear pending bit when write 0 1 Inte
167. errupt service routine In mode O0 the transmit interrupt pending bit INTPND 4 is set to 1 when the 8th transmit data bit has been shifted In mode 1 2 or 3 the INTPND 4 bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the INTPND 4 bit must then be cleared by software in the interrupt service routine Interrupt Pending Register INTPND DOH Set 1 Bank 0 R W Not used Timer 0 overflow interrupt pending bit Timer 0 match capture interrupt pending bit Timer 3 overflow interrupt pending bit Timer 3 match capture interrupt pending bit Tx interrupt pending bit for UART Rx interrupt pending bit for UART 0 Interrupt request is not pending pending bit clear when write O 1 Interrupt request is pending Figure 18 2 UART Interrupt Pending Bits INTPND 5 4 ELECTRONICS 18 3 UART S3C825A P825A UART DATA REGISTER UDATA UART Data Register UDATA F9H Set 1 Bank 0 R W Transmit or receive data Figure 18 3 UART Data Register UDATA UART BAUD RATE DATA REGISTER BRDATA The value stored in the UART baud rate register BRDATA lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATA FBH Set 1 Bank 0 R W Baud rate data Figure 18 4 UART Baud Rate Data Register BRDATA BAUD RATE CALCULATIONS Mode 0 Baud Rate Calculation In mode 0 the baud rate is determined by the UART baud rate data regi
168. ersion clock with an 4 5 MHz fxx clock frequency one clock cycle is 1 78 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bit set up time 50 clocks 50 clock x 1 78 us 89 us at 0 56 MHz 4 5 MHz 8 Note that A D converter needs at least 25 for conversion time A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located at address EFH in set 1 bank 0 It has three functions Analog input pin selection bits 4 and 5 End of conversion status detection bit 3 ADC clock selection bits 2 and 1 operation start or enable bit O After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADO AD3 can be selected dynamically by manipulating the ADCON 4 5 bits And the pins not used for analog input can be used for normal I O function A D Converter Control Register ADCON EFH Set 1 Bank 0 R W EOC bit is read only Always logic zero Start or enable bit 0 Disable operation 1 Start operation A D input pin selection bits 00 ADO Clock Selection bits 01 AD1 00 fxx 16 10 AD2 01 fxx 8 11 AD3 10 fxx 4 11 fxx 1 End of conversion bit 0 Not complete Conversion 1 complete Conversion Figure 16 1 A D Converter Control Register ADCON 16 2 ELECTRONICS S3C825A P825A A D CONVERTER Conversion Data Register ADDA
169. essing Register File de cd RPO or RP1 RPO or RP1 Selected RP points to start of working Program Memory 4 bit Working Register dst 2 LL OPERAND gt OPCODE Working Register OPERAND Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the curruntly selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3C825A P825A ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Register addressing mode Program Memory Register File HANE ee e ADDRESS OPCODE Point ta gt Register in Register One Operand 4 File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3
170. ft register UDATA F9H set 1 bank 0 to start the transmission operation Mode 0 Receive Procedure 1 Select mode 0 by setting UARTCON 6 and 7 00B 2 Clear the receive interrupt pending bit INTPND 5 by writing a 0 to INTPND 5 Set the UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD P5 5 pin and will read the data at the RxD P5 4 pin A UART receive interrupt IRQ3 vector D4H occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA RD Daou V 0e X X 9 X 9r 7 TxD Shift Clock c TIP Transmit Write to UARTPND Clear RIP and set RE Shift RxD Data In DO D1 D2 D3 D4 D5 D6 D7 TxD Shift Clock Figure 18 6 Timing Diagram for Serial Port Mode 0 Operation ELECTRONICS 18 7 UART S3C825A P825A SERIAL PORT MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P5 5 pin or received through the RxD P5 4 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01B 3 Write transmission data to the shift register UDATA F9H set 1 bank 0 The start and stop bits are
171. g the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3C825A P825A PUSHUI Push user stack Incrementing PUSHUI Operation Flags Format Example 6 68 dst src IR IR 1 dst src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst SIC 3 8 83 IR R Given Register 03H register 01H 05H and register 2AH PUSHUI 00H 01H Register 04H register 01H 05H register 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3C825A P825A INSTRUCTION SET RCF neset Carry Flag RCF RCF Operation lt 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 CF Example Given C 1 or The instruction RCF clears the car
172. gister pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C825A RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice 2 0 Not used for the S8C825A ELECTRONICS 4 35 CONTROL REGISTERS S3C825A P825A SIOCON sio Control Register EOH Set 1 Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO Shift Clock Selection Bit Internal clock P S clock 1 External clock SCK 6 Data Direction Control Bit MSB first mode LSB first mode le 5 SIO Mode Selection Bit Receive only mode 1 Transmit receive mode 4 Shift Clock Edge Selection Bit Tx at falling
173. gnal is generated when the counter value is identical to the values written to the TA or TB reference data registers TADATA or TBDATA The match signal generates corresponding match interrupt TAINT vector E6H TBINT vector E4H and clears the counter If for example you write the value 10H to TBDATA 0 to TACON 7 and OEH to TBCON the counter will increment until it reaches 10H At this point the TB interrupt request is generated the counter value is reset and counting resumes Timer A and B Control Register TACON TBCON You use the timer A and B control register TACON and TBCON to Enable the timer A and B operating interval timer Select the timer A and B input clock frequency Clear the timer A and B counter TACNT and TBCNT Enable the timer A and B interrupt Clear timer A and B interrupt pending conditions 11 4 ELECTRONICS S3C825A P825A TIMER 1 TACON and TBCON are located in set 1 bank 0 at address EBH and EAH and is read write addressable using register addressing mode A reset clears TACON and TBCON to 00H This sets timer A and B to disable interval timer mode selects an input clock frequency of fxx 256 and disables timer A and B interrupt You can clear the timer A and B counter at any time during normal operation by writing a 1 to TACON 3 and TBCON 3 To enable the timer A and B interrupt IRQ1 vector E6H E4H you must write TACON 7 to 0 TACON 2 TBCON 2 and TACON 1 TBCON 1 t
174. gram counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3C825A P825A REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register rie Address Tha e cou OPERAND d OPCODE Register in Register L One Operand 4 File Instruction Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addr
175. he FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal Opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast OpC 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3C825A P825A INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc is true PC dst T
176. he base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 Slice 31 11111XXX Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 5 8 Byte Working Register Areas Slices 2 8 ELECTRONICS S3C825A P825A ADDRESS SPACES USING THE REGISTER POINTS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to th
177. he conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0to F opc dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W W 1000H PC 1000H JP 00 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3C8
178. he registers INTPND STPCON OSCCON are in bank 0 of set 1 X X 2 2 2 2 2 2 2 2 2 2 2 x x ES x x Lo x EN o 12 13 14 15 16 17 18 19 20 21 22 23 8 2 ELECTRONICS S3C825A P825A RESET and POWER DOWN Table 8 2 S3C825A Set 1 Bank 0 m Values after RESET IE NER convoi regse zw Data Regser sovata zs S10 Prescaier Regeer sors ms Pero canerfepser er TmeroDmaRegser vonata zs Ee Timer 0 ContotRegister tocon em esn o o o Timer B Counter Register een o o o Timer A Counter Register macnt em o o Timer B Data Register Tepara Em 1 1 1 1 Timer A Data Register Tapata mo EM 1 1 1 1 Timer B Control Regier Ew 9 0 Timer 1A Control Register acon 2a5 esa o o 0 Timer2 Counter Register ecn o o Timer2 Data Register er en 1 1 1 1 Timer2 ConrotRegister ew o o o 0 Converter Control Register Ancon 0 0 Converter Data Register ign yie 240 x x x x Converter Data Register ow bye ADDATAL Fm LCD Register tcov ae 0
179. i ele be rre b REEF TREE 1 3 Pine ASSIQBImeLb cats ic cea etic anal astute 1 4 PIN DESCHIPUIONS vieralatsdecacecatavadatedereslegsensadetydecenedasnsaanusetectecentaaytelecaretecrsgasiaascertscoresapeedsaencareesasseevenptceeanaas 1 6 PUG teas LI RR 1 8 Chapter 2 Address Spaces eee eee eae deena eee 2 1 Program Memory 0 0 0 00000 2 2 Register Architecture 0 2 2 3 Register Page Pointer PP iibris 2 5 te 2 6 niti 2 6 Prime Register Space x Vika d n ace de e sa Yaa idu cc set dette 2 7 Working E pe ORDER RE p m E a 2 8 Using the Register 2 9 Register Addressing ices RET a 2 11 Common Working Register Area 2 13 4 Bit Working Register nnn 2 14 8 Bit Working Register 0 nnne nnne nnns 2 16 System and User Stack i tti trt EEUU REA 2 18 Chapter 3 Addressing Modes OVEVIEW
180. ic Timer Counter BTONT 25 RW Location FEH is not mapped Prony Reger m ms ww 4 2 ELECTRONICS S3C825A P825A CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers ENG S ooo Decimal Hex T 65 4 3 2 10 Port 2 Control Register High Byte P2CONH 224 RW Port 2 Control Register Low Byte PeCONL 225 RW Port2PulrupResistosenable Register P2PUR 226 RW Port 2 Interrupt Control Register_ Pant 227 ESH RW Port 3 Control Register High 228 RW Port 3 Control Register Low Byte PSCONL 29 RW Port 3 Pullup Resistors enable Register PSPUR 280 RW Port 4 Interrupt Edge Selection Register PAEDGE 231 RW Port 4 Control Register High PACONH 22 RW Port 4 Control Register Low Byte PACONL 283 RW Port 4 Interrupt Control Register 284 EAH RW Port 4 Interrupt Pending Register PAPND 235 RW
181. ified Timer 0 Function Diagram PWM Mode ELECTRONICS 10 9 BASIC TIMER and TIMER 0 S3C825A P825A Capture Mode In capture mode a signal edge that is detected at the TOCAP P3 7 pin opens a gate and loads the current counter value into the timer 0 data register You can select rising or falling edges to trigger this operation Timer 0 also gives you capture input source the signal edge at the TOCAP P3 7 pin You select the capture input by setting the values of the timer 0 capture input selection bits in the port control register PSCONH 7 6 set 1 bank 1 E4H When PSCONH 7 6 is 00 the TOCAP input is selected Both kinds of timer 0 interrupts can be used in capture mode the timer 0 overflow interrupt is generated whenever a counter overflow occurs the timer 0 match capture interrupt is generated whenever the counter value is loaded into the timer 0 data register By reading the captured data value in TODATA and assuming a specific value for the timer 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the TOCAP pin see Figure 10 7 TOCON O TOOVF IRQO 8 Bit Up Counter INTPND O Overflow INT Interrupt Enable Disable TOCON 1 TOINT IRQO TOCAP input INTPND 1 Capture INT P3 7 Match Signal Pending Timer 0 Data Register Figure 10 7 Simplified Timer 0 Function Diagram Capture Mode 10 10 ELECTRONICS S3C825A P825A BASIC TIMER and TIMER 0 TO
182. implified Timer 3 Function Diagram Interval Timer Mode 13 4 ELECTRONICS S3C825A P825A 16 BIT TIMER 3 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TSPWM P3 6 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 3 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFFFH and then continues incrementing from 0000H Although you can use the match signal to generate a timer 3 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the T3PWM P3 6 pin is held to Low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to x 65536 see Figure 13 4 T3CON 0 Capture Signal Interrupt Enable Disable T3OVF IRQ2 T3CON 1 16 Bit Up Counter lt INTPND 2 LD Overflow INT TSINT IRQ2 INTPND 3 16 Bit Comparator INTPND 3 Match INT Pending T3PWM Output P3 6 Match Signal data gt counter lt _E 2 Lower level when data lt counter Figure 13 4 Simplified Timer 3 Function Diagram PWM Mode ELECTRONICS 13 5 16 BIT TIME
183. in configuration Because of its simple programming requirements the S3P8254 is ideal as an evaluation chip for the S3C825A ELECTRONICS 21 1 53 825 OTP P1 1 SEG25 P1 2 SEG26 P1 3 SEG27 P1 4 SEG28 P1 5 SEG29 P1 6 SEG30 P1 7 SEG31 SDAT P2 0 SCLK P2 1 VDD VDD1 Vss Vss1 XOUT XIN VPP TEST XTIN XTOUT RESET RESET P2 2 T2CLK P2 3 T2OUT P2 4 INTO TOCLK P0 2 SEG18 o 0 1 5 17 P0 0 SEG16 P8 1 SEG13 P8 0 SEG12 P7 7 SEG11 P7 6 SEG10 P7 5 SEG9 P7 4 SEG8 P7 3 SEG7 P7 2 SEG6 P7 1 SEG5 74 73 72 L5 P1 0 SEG24 P0 7 SEG23 P0 6 SEG22 77 0 5 5 21 76 0 4 5 20 PO 3 SEG19 1 P8 3 SEG15 P8 2 SEG14 80 79 78 70 69 68 67 H 66 65 64 r3 63 FA 62 61 Q S3P825A 80 TQFP 1212 P3 5 T3CLK 04 31 P2 5 INT1 TTCLK C3 21 P2 6 INT2 TAOUT 22 P2 7 INT3 TBOUT C323 P3 6 T3OUT T3PWM T3CAP 32 P3 7 TOOUT TOPWM TOCAP Cj 33 S3C825A P825A P7 0 SEG4 P6 7 SEG3 COM7 P6 6 SEG2 COM6 P6 5 SEG1 COM5 P6 4 SEG0 COM4 P6 3 COM3 P6 2 COM2 P6 1 COM1 P6 0 COMO VDD2 Vss2 VLC1 P5 6 P5 5 TXD P5 4 RXD P5 3 BUZ P5 2 SO P5 1 SI P5 0 SCK P4 7 INT11 Figure 21 1 S3P825A Pin Assignments 80 Pin TQFP Package ELECTRONICS S3C825A P825A 53 825 OTP 80 L3 PO0 6 SEG22 79 L3 P0 5 SEG21 78 PO 4 SEG20 77 PO 3 SEG19 76 PO 2 SEG18 75 PO 1 SEG17 74 PO 0 SEG16 73 L3 P8 3 SEG15 72 1 P
184. ing the port 3 control registers must also be enabled in the associated peripheral module Port 3 Pull up Resistor Control Register P3PUR Using the port 3 pull up resistor control register E6H set 1 bank 1 you can configure pull up resistors to individual port 3 pins Port 3 Control Register High Byte E4H Set 1 Bank 1 R W Pu 5 T3CLK P3 6 T3OUT T3PWM T3CAP P3 7 TOOUT TOPWM TOCAP P3CONH bit pair pin configuration settings Input mode T3CLK T3CAP TOCAP Output mode open drain Alternative function T3OUT T3PWM TOOUT TOCAP Output mode push pull Figure 9 6 Port 3 High Byte Control Register 9 8 ELECTRONICS S3C825A P825A Port 3 Control Register Low Byte E5H Set 1 Bank 1 R W P3 2 AD2 P3 3 AD3 bit pair pin configuration settings Input mode Output mode open drain Alternative function ADO AD3 Output mode push pull Figure 9 7 Port 3 Low Byte Control Register PSCONL Port 3 Pull up Control Register E6H Set 1 Bank 1 R W TTTTTTTT P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P3PUR bit configuration settings 0 Disable pull up resistor Enable pull up resistor NOTE corresponding pull up resistor is disabled automatically when a bit of port 3 is selected as output mode Figure 9 8 Port 3 Pull up Control Register P3PUR ELECTRONICS PORTS 9 9 PORTS S3C825A P825A PORT 4 Port 4 is an 8 bit I O por
185. ing position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 72 6 73 r Ir opc SIC dst 3 6 74 R R 6 75 R IR opc dst SIC 3 6 76 R IM Examples Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H TM RO R1 gt RO 0C7H R1 02H Z 0 TM RO R1 gt RO 0C7H R1 02H register 02H 23H Z 0 TM 00H 01H gt Register OOH 2BH register 01H 02H Z 0 00H 01H gt Register 00H 2BH register 01H 02H register 02H 23H 7 0 00H 54H gt Register 00H 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement RO R1 tests bit one in the destination register for 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3C825A P825A WEI wait tor Interrupt WFI Operation Flags Format Example 6 86 The CPU is effective
186. interruptto 0 2855 S 1 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit No interrupt pending when read 0 Clear pending bit when write Interrupt is pending when read 4 46 ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM88RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO IRQ 7 also called level 0 level 7 Each interrupt level directly corresponds to interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C825A interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recogn
187. irst example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 000001 11B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3C825A P825A INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF dst src b Operation If src b is 0 then PC lt PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement
188. ister 01H 1CH register 02H SBC 01H 02H Register 01H 15H register 02H register OAH SBC gt Register 01H 95H C S and V 1 gt gt gt gt In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3C825A P825A SCF set Carry Flag SCF Operation Flags Format Example 6 78 C 1 The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3C825A P825A INSTRUCTION SET SRA shitt Right Arithmetic SRA dst Operation dst 7 lt dst 7 C lt dst 0 dst n lt dst n 1 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags C Setif the bit shifted from the LSB position bit zero was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Always cleared to O D Unaffected H Unaffected Forma
189. ister 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3C825A P825A INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI dst src Operation dst src IR IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 8 93 R IR Example Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register 02H register 01H 70H register 02H 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02H 200H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3C825A P825A PUSH Push To Stack PUSH Operation Flags Format Examples 6 66 src SP SP 1 lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst
190. it is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 18 11 UART S3C825A P825A Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 Set all S8C825A devices masters and slaves to UART mode 2 or 3 Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi 83C825A Interconnect TxD RxD TxD RxD TxD RxD TxD RxD Master Slave 1 Slave 2 Slave n S3C825A S3
191. ized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C825A uses twenty three vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S8C825A interrupt structure there are twenty three possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3C825A P825A INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individu
192. k 1 Enable unmask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 1 ELECTRONICS 4 CONTROL REGISTERS S3C825A P825A INTPND Interrupt Pending Register DOH Set 1 Bank 0 RESET Value S E 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C825A 5 Rx Interrupt Pending Bit for UART Interrupt request is not pending when read pending bit clear when write 0 1 Interrupt request is pending 4 Tx Interrupt Pending Bit for UART Interrupt request is not pending when read pending bit clear when write 0 1 Interrupt request is pending 3 Ti 3 er 3 Match Capture Interrupt Pending Bit Interrupt request is not pending when read pending bit clear when write 0 1 Interrupt request is pending 2 Ti 3 er 3 Overflow Interrupt Pending bit Interrupt request is not pending when read pending bit clear when write 0 1 Interrupt request is pending Timer 0 Match Capture Interrupt Pending Interrupt request is not pending when read pending bit clear when write 0 1 Interrupt request is pending 0 Timer 0 Overflow Interrupt Pending bit Interrupt request is not pending when read pending bit clear when write 0 1 Interrupt request is pending 4 10 ELECTRONICS S3C825A P825A CONTROL REGISTER IPH instruction Pointer High Byte DAH Set 1 RE
193. lags Format Example Address PC IP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex ope 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before After Data Address Address Data 43 Address H 43 Address H ozo 44 Address L 44 Address L 6 60 45 Address 45 Address 120 130 Routine ELECTRONICS S3C825A P825A INSTRUCTION SET NOP No Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3C825A P825A OR Logical OR OR Operation Flags Format Examples 6 62 dst src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaff
194. lags Format Examples 6 54 dst src ro m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes an even number for program memory an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 E2 Given R6 10H R7 33H R8 12H program memory location 1033H external data memory location 1033H ODDH LDCD R8 Q9 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3C825A P825A INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI dst src Operation dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified
195. lowing processing sequence Reset clear to 0 the interrupt enable bit in the SYM register 5 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location oa Fe N gt Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lowe
196. lue OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3C825A P825A INSTRUCTION SET MULT multiply Unsigned MULT dst src Operation dst lt dst x src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Flags C Set if result is gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst sic opc SIC dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 20H register 01H register 02H 09H register 06H MULT 00H 02H gt Register OOH 01H register 01H 20H register 02H 09H MULT 00H Q01H gt Register OOH OOH register 01H OCOH MULT OOH 30H gt Register OOH 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3C825A P825A NEXT next NEXT Operation F
197. ly halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F 1 2 3 The following sample program structure shows the sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3C825A P825A XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored Unaffected Always reset to O Unaffected Unaffected IO cONO opc SIC dst opc dst SIC Set if the result is 0 cleared otherwise Setif the result bit 7 is set cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst 2 4 B2 r B3 r 3 6 B4 R B5 R 3 6 B6 R src r Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H XOR RO R1 XOR RO R1
198. m mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 8F Example Given SYM O1H DI If the value of the SYM register is 01H the statement DI leaves the new value OOH in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3C825A P825A DIV pivide Unsigned DIV dst src Operation dst src dst UPPER REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 41 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected
199. memory Value used in Instruction OPERAND Sample Instructions LDC R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3C825A P825A ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for int
200. memory location 0104H RO 1AH R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working registers R2 no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers R3 no change RO contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory location 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3C825A P825A LDCD LDED Load Memory and Decrement LDCD LDED dstsrc Operation F
201. n Bits LO o abo eso 5 ofa aoi esn oo T 0 AD3 P3 3 3 End of Conversion Bit read only Conversion not complete Conversion complete 2 1 Clock Source Selection Bits LO ted ooo 0 Start or Enable Bit Disable operation 1 Start operation automatically disable operation after conversion complete ELECTRONICS 4 5 CONTROL REGISTERS S3C825A P825A BTCON Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset fifo 1 Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits o mumem 4 Basic Timer Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for all Timers 2 No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to OOH Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to OOH Immediately following the write operation the 0 value is automatically cleared to 0 3 The fxx is selected clock for system 4 6 EL
202. n generate two interrupts the timer 0 overflow interrupt TOOVF and the timer 0 match capture interrupt TOINT TOOVF is belongs to interrupt level IRQO vector E2H TOINT also belongs to interrupt level IRQO but is assigned the separate vector address EOH A timer O overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a 0 to the INTPND O interrupt pending bit However the timer 0 match capture interrupt pending condition must be cleared by the application s interrupt service routine by writing a to the INTPND 1 interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register TODATA The match signal generates a timer 0 match interrupt TOINT vector EOH and clears the counter If for example you write the value 10H to TODATA the counter will increment until it reaches 10H At this point the timer 0 interrupt request is generated the counter value is reset and counting resumes With each match the level of the signal at the timer 0 output pin is inverted see Figure 10 5 Interrupt Enable Disable TOCON 1 8 Bit Up Counter lt TOINT IRQO 8 Bit Comparator Match INT Capture Signal TOOUT P3 7 Timer 0 Buffer Register TOCON 4 3 Timer 0 Data R
203. n set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S8C825A the set 2 address range is accessible on pages 0 7 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area of page 0 is commonly used for stack operations 2 6 ELECTRONICS S3C825A P825A ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes OOH BFH of the S3C825A s eight 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 1 2 3 4 5 6 or 7 you must set the register page pointer PP to the appropriate source and destination values
204. n to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscillation Then after a certain number of machine cycles has elapsed select the main clock by setting OSCCON O to 0 I PROGRAMMING TIP Switching the CPU clock 1 This example shows how to change from the main clock to the sub clock MA2SUB LD OSCCON 01H Switches to the sub clock Stop the main clock oscillation RET 2 This example shows how to change from sub clock to main clock SUB2MA AND OSCCON 07H Start the main clock oscillation CALL DLY16 Delay 16 ms AND OSCCON 06H Switch to the main clock RET DLY16 SRP 0COH LD R0 4 20H DEL NOP DJNZ RO DEL RET 7 6 ELECTRONICS S3C825A P825A CLOCK CIRCUIT STOP Control Register STPCON D1H Bank 0 Set 1 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101B Otherwise the STOP instruction will not execute as well as reset will be generated Figure 7 9 STOP Control Register STPCON ELECTRONICS 7 7 CLOCK CIRCUIT S3C825A P825A NOTES 7 8 ELECTRONICS S3C825A P825A RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a schmitt trigger circuit where it is then synchro
205. nable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first Clock source selection internal or external for shift clock A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first 17 2 Serial Module Control Register SIOCON EOH Set 1 Bank 0 R W SIO shift clock selection bit 0 Internal clock P S Clock 1 External clock SCK Data direction control bit 0 MSB first mode 1 LSB first mode SIO mode selection bit 0 Receive only mode 1 Transmit receive mode Shift clock edge selection bit 0 tx at falling edeges rx at rising edges 1 tx at rising edeges rx at falling edges SIO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIO interrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 17 1 Serial I O Module
206. nable Bit Disable interrupt Enable interrupt 3 P4 3 External Interrupt INT7 Enable Bit Disable interrupt Enable interrupt 2 P4 2 External Interrupt INT6 Enable Bit Disable interrupt Enable interrupt P4 1 External Interrupt INT5 Enable Bit Disable interrupt Enable interrupt 0 P4 0 External Interrupt INT4 Enable Bit Disable interrupt Enable interrupt N J ELECTRONICS 4 CONTROL REGISTERS S3C825A P825A PAPND Port4 Interrupt Pending Register EBH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 External Interrupt INT11 Pending Flag No interrupt request pending When read Clear pending bit when write 1 P4 7 interrupt request is pending when read 6 P4 6 External Interrupt INT10 Pending Flag No interrupt request pending When read Clear pending bit when write 1 P4 6 interrupt request is pending when read 5 P4 5 External Interrupt INT9 Pending Flag No interrupt request pending When read Clear pending bit when write 1 P4 5 interrupt request is pending when read 4 4 4 External Interrupt INT8 Pending Flag No interrupt request pending When read Clear pending bit when write 1 P4 4 interrupt request is pending when read 3 P4 3 External Interrupt INT7 Pending Flag No interrupt request pending When read Clear pending bit when write
207. nable bit RE in the UARTCON register to 1 2 The receive operation starts when the signal at the RxD pin goes to low level Tx Write to Shift Register UARTDATA m O SUM QD 4 039 NUR Transmit TIP is 00 DI 02 X D4 05 X pe X pr X Sup I RIP Figure 18 8 Timing Diagram for Serial Port Mode 2 Operation ELECTRONICS 18 9 UART S3C825A P825A SERIAL PORT MODE 3 FUNCTION DESCRIPTION In mode 3 11 bits are transmitted through the TxD P5 5 pin or received through the RxD P5 4 pin Mode 3 is identical to mode 2 except for baud rate which is variable Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 Mode 3 Transmit Procedure 1 Select the baud rate generated by BRDATA 2 Select mode operation 9 bit UART by setting UARTCON bits 6 and 7 to 1 1B Also select the 9th data bit to be transmitted by writing UARTCON 3 8 to 0 or 1 3 Write transmission data to the shift register UDATA F9H set 1 bank 0 to start the transmit operation Mode 3 Receive Procedure 1 Select the baud rate to be generated by BRDATA 2 Select mode 3 and set the RE Receive Enable bit in the UARTCON register to 1 3 The receive operation will be started when the signal at the RxD P5 4 pin goes to low level Tx Write to Shift Register UARTDATA ii
208. ned 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE S3C825A P825A INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH
209. nfiguration ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU SAM88RC CPU Memory e 2064 byte internal register file including LCD display RAM 48K byte internal program memory area Instruction Set 78 instructions and Stop instructions 67 I O Pins e 31 normal I O pins e 36 pins sharing with LCD signals Interrupts e 8 interrupt levels and 23 internal sources Fast interrupt processing feature 8 Bit Basic Timer Watchdog timer function e kinds of clock source Timer Counter 0 e Programmable 8 bit internal timer e External event counter function PWM and capture function Timer Counter 1 e 16 bit timer counter mode e Two 8 bit timer counters A B mode External event counter function Timer Counter 2 Programmable 8 bit interval timer External event counter function Timer Counter 3 Programmable 16 bit interval timer External event counter function PWM and capture function S3C825A P825A Watch Timer Interval Time 3 19ms 0 255 0 55 1 0s at 32 768 kHz 0 5 1 2 4 kHz buzzer output selectable Analog to Digital Converter e 4 channel analog input 10 bit conversion resolution e 25 5 conversion time Serial I O Interface e 8 bit transmit receive mode 8 receive mode Selectable baud rate or external clock source UART Full duplex serial interface Four programmable operating modes LCD Controller Driver
210. nfigure using the port 5 control registers must also be enabled in the associated peripheral module Port 5 Control Register High Byte ECH Set 1 Bank 1 R W TXD output control bit P5 6 P5 5 TXD P5 4 RXD 0 Disble TXD output at P5 5 RXD output control bit 1 Enable TXD P5 70 AND at Pd 1 Enable RXD output at P5 4 P5CONH bit pair pin configuration settings Input mode RXD Output mode open drain RXD TXD Not available Output mode push pull RXD TXD NOTE The RXD and TXD outputs depend on PSCONH 6 and 7 respectively Figure 9 14 Port 5 High Byte Control Register ELECTRONICS 9 13 PORTS Port 5 Control Register Low Byte PSCONL EDH Set 1 Bank 1 R W 0 5 5 1 51 P5 2 SO P5 3 BUZ P5CONL bit pair pin configuration settings Input mode SCK Sl Output mode open drain Alternative function BUZ SCK SO Output mode push pull Figure 9 15 Port 5 Low Byte Control Register PSCONL Port 5 Pull up Control Register EEH Set 1 Bank 1 R W errr ry Not P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 used P5PUR bit configuration settings 0 Disable pull up resistor Enable pull up resistor NOTE corresponding pull up resistor is disabled automatically when a bit of port 5 is selected as output mode Figure 9 16 Port 5 Pull up Control Register P5PUR S3C825A P825A ELECTRON
211. nized with the CPU clock This procedure brings the S3C825A into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required time of a reset operation for oscillation stabilization is 1 millisecond Whenever a reset occurs during normal operation that is when both and RESET are High level the RESET pin is forced Low level and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation All interrupt is disabled The watchdog function basic timer is enabled Ports 0 8 are set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the Test pin is tied to Vgc A reset enables access to the 48 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appr
212. o 1 To generate the exact time interval you should set TACON 3 TBCON 3 TACON 0 TBCON 0 to 10B which clear counter and interrupt pending bit respectively When the TAINT or TBINT sub routine is serviced the pending condition must be cleared by software by writing a 0 to the timer A or B interrupt pending bits 0 or 0 Timer A Control Register TACON EBH Set 1 Bank 0 R W Timer 1 operation mode selection bit Timer A interrupt pending bit 0 Two 8 bit timers mode Timer A B 0 No interrupt pending 1 One 16 bit timer mode Timer 1 0 Clear pending bit when write 1 Interrupt is pending when read 1 No effect when write Timer A clock selection bits 000 fxx 256 Timer A interrupt enable bit 001 fxx 64 0 Disable interrupt 010 fxx 8 1 Enable interrupt 011 fxx 111 T1CLK Timer A counter run enable bit external clock rising edge 0 Disable counter running 1 Enable counter running Timer A counter clear bit 0 No affect 1 Clear the timer A counter when write Figure 11 3 Timer A Control Register TACON ELECTRONICS 11 5 TIMER 1 S3C825A P825A Timer B Control Register TBCON EAH Set 1 Bank 0 R W Not used the S3C825A Timer B interrupt pending bit 0 No interrupt pending Timer B clock selection bits 0 Clear pending bit when write 00 fxx 256 1 Interrupt is pending when read 01 64 1 No effect when write 10 fx
213. o mputmoos o 0 1 Output mode open drain o 1 0 Alternative function ADC mode Output mode push pull 4 22 ELECTRONICS S3C825A P825A CONTROL REGISTER P3PUR Port 3 Pull up Control Register E6H Set 1 Bank 1 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P3 7 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 6 P3 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 P3 5 Pull up Resistor Enable Bit Pull up disable e Pull up enable 4 P3 4 Pull up Resistor Enable Bit Pull up disable EE Pull up enable 3 P3 3 Pull up Resistor Enable Bit Pull up disable EE Pull up enable 2 P3 2 Pull up Resistor Enable Bit Pull up disable le Pull up enable P3 1 Pull up Resistor Enable Bit Pull up disable EE Pull up enable 0 P3 0 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable N ELECTRONICS 4 CONTROL REGISTERS S3C825A P825A P4CONH Port 4 Control Register High Byte E8H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P4 7 INT11 Mode Selection Bits 0 1 input pultupmode 000 1 Open drain output mode Push pull output mode 5 and 4 P4 6 INT10 Mode Selection Bits
214. occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER and TIMER 0 S3C825A P825A RESET or STOP Basic Timer Control Register y Write 1010xxxxB to Disable Data Bus fxx 4096 fxx 1024 8 Bit Up Counter fxx 128 BTONT Read Only fxx 16 Start the CPU nete NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS S3C825A P825A BASIC TIMER and TIMER 0 8 BIT TIMER COUNTER 0 Timer counter 0 has three operating modes one of which you select using the appropriate setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P3 7 pin PWM mode Timer counter has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 or 1 with multiplexer External clock input P2 4 TOCLK 8 bit counter TOCNT 8 bit comparator and 8 bit reference data register TODATA I O pins for capture input match output or PWM output P3 7 TOCAP P3 7 TOOUT P3 7 TOPWM Timer 0 overflow interrupt IRQO vector E2H and match capture interrupt IRQO vector EOH generation Timer 0 control register TOCON set 1 E5H bank 0 read write TIMER COUNTER 0 CONTROL REGISTER TOCON You use the timer 0 control register TOCON to Select the timer 0 operating mode interval timer captu
215. ock 144 QFP S3E8210 EVA Chip 40 Pin Connector 40 Pin Connector c c Er SM1345A Figure 22 2 TB825A Target Board Configuration ELECTRONICS 22 3 DEVELOPMENT TOOLS S3C825A P825A Table 22 1 Power Selection Settings for TB825A To User Settings To User Vcc Vss gt Operating Mode To User Vcc External Off On TB825A Voc gt Vss gt Comments The SMDS2 SMDS2 supplies Vcc to the target board evaluation chip and the target system The SMDS2 SMDS2 supplies Vcc only to the target board evaluation chip The target system must have its own power supply NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration oon SMDS2 Selection SAM8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 22 2 The SMDS2 Tool Selection Setting SMDS2 fee SMDS2 Operating Mode IDLE LED The Yellow LED is ON when the evaluation chip S3E8250 is in idle mode STOP LED The Red LED is ON when the evaluation chip 53 8250 is in stop mode 22 4 ELECTRONICS S3C825A P825A P1 1 SEG25 P1 3 SEG27 P1 5 SEG29 P1 7 SEG31 P2 1 VSS1 XIN XTIN RESET P2 3 T2OUT P2 5 INT1 T1CLK P2 7 IN
216. on Bits ofofo ee GEN External clock T1CLK rising edge 3 Timer 1 A Counter Clear Bit NOTE No effect 1 Clear the timer 1 A counter when write 2 Timer 1 A Counter Run Enable Bit Disable Counter Running 1 Enable Counter Running Timer 1 A Interrupt Enable Bit Disable interrupt Enable interrupt 0 Timer 1 A Interrupt Pending Bit No interrupt pending when read 0 Clear pending bit when write Interrupt is pending when read NOTE When you write a 1 to TACON 3 the Timer 1 A counter value is cleared to OOH Immediately following the write operation the TACON 3 value is automatically cleared to ELECTRONICS 4 41 CONTROL REGISTERS S3C825A P825A TBCON Timer B Control Register EAH Set 1 RESET Value S E 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 Not used for the S3C825A and 4 Timer B Clock Selection Bits 3 Timer B Counter Clear Bit NOTE No effect Clear the timer B counter when write 2 Timer B Counter Run Enable Bit Disable Counter Running Enable Counter Running Timer Interrupt Enable Bit Disable interrupt Enable interrupt 0 Timer Interrupt Pending No interrupt pending when read 0 Clear pending bit when write Interrupt is pending when read NOTE When you write a 1 to TBCON 3 the
217. on generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction
218. opriate settings to the basic timer control register before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN S3C825A P825A HARDWARE RESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C825A Set 1 Register and Values after RESET UC NETT Mx 7 e s s 2 s eo Dec Interrupt Pending Register NOTE INTPND 208 DOH 0 0 0 0 0 0 STOP Control Register NOTE STPCON 209 DIH 0 0 0 0 0 0 0 0 Oscillator Control Register NOTE OSCCON 210 0 0 0 x x Register Pointer High Byte RPO x interrupt Request Register IRQ System Mode Register SYM 222 Register Page Pointer PP 223 NOTE T
219. or address has high priority For example has higher priority than E2H within the level IRQO the priorities within each level are set at the factory External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3C825A Interrupt Structure S3C825A P825A ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8254A interrupt structure are stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 49 151 48K byte Program Memory Area RESET Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3C825A P825A Table 5 1 Interrupt Vectors Vector Address Interrupt Source Reset Clear Decimal Hex Interrupt Priority in H W S W Value Value Level Level 212 210 Basic timer overflow timer overflow RESET Timer 0 overflow DE Emme A Timer 1 A match IRQ1 NER mea nm Timer 3 overflow IRQ2 Timer 3 match capture Timer 2 match UART data receive IRQ3 UART data transmit
220. or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Flags IOZONO Format Bytes Cycles Opcode Addr Mode Hex dst src 3 6 3 6 67 Rb r0 NOTE Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 O6H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 000001 11B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 000001 10B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3C825A P825A BCP Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it
221. ormal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an internal and an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an internal and an external interrupt When BTCNT 3 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts 2 Ifa power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an internal and external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows When a BTCNT 3 overflow
222. otation Conventions Condition code See list of condition codes in Table 6 6 Working register only Rn n 0 15 Bit b of working register n 0 15 b 0 7 Bit LSB of working register Rn n 0 15 Working register pair RRp p 0 2 4 14 Register or working register reg or Rn reg 0 255 n 0 15 Bit b of register or working register reg b reg 0 255 b 0 7 Register pair or working register pair reg or RRp reg 0 254 even number only where 0 2 14 Indirect addressing mode addr addr 0 254 even number only Indirect working register only Rn n 0 15 Indirect register or indirect working register Rn or reg reg 0 255 n 0 15 Indirect working register pair only RRp p 0 2 14 Indirect register pair or indirect working RRp or reg reg 0 254 even only where register pair 0 2 14 Indexed addressing mode reg Rn reg 0 255 n 0 15 Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 Indexed long offset addressing mode RRp addr range 0 65535 where 0 2 14 Direct addressing mode addr addr range 0 65535 Relative addressing mode addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction Immediate addressing mode data data 0 255 Immediate long addressing mode data data range 0 6
223. p Vss 10 11 12 13 Logic power supply pin VDD should be tied to 5 V during programming NOTE Parentheses indicate pin for 80 pin QFP 1420 package Table 21 2 Comparison of S3P825A and S3C825A Features Program Memory 48 Kbyte EPROM 48 Kbyte mask ROM Operating Voltage Vpp 2 0 V to 5 5 V 2 0 V to 5 5 V OTP Programming Mode Vpp 5 V Vpp TEST 12 5 V Po Pin Configuration 80 TQFP 80 QFP 80 TQFP 80 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST pin of the S3P825A the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 21 3 below Table 21 3 Operating Mode Selection Criteria sv 5v 0 00H 1 EPROMread 12 5 V 0 0000H oo EPROM program 12 5 V o 0000H EPROM verify 12 5 V OE3FH EPROM read protection NOTE 0 means Low level 1 means High level 21 4 ELECTRONICS S3C825A P825A 53 825 OTP Instruction Clock Main Oscillator Frequency 8 19 kHz Supply Voltage V CPU Clock 1 4n x oscillator frequency n 1 2 8 16 Figure 21 3 Operating Voltage Range ELECTRONICS 21 5 53 825 OTP S3C825A P825A NOTES 21 6 ELECTRONICS S3C825A P825A DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in
224. peration Flags Format Examples 6 30 dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Setif a borrow occurred src dst cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 A2 r r SIC 6 r Ir opc SIC dst 3 6 A4 R R 5 R IR opc dst SIC 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS S3C825A P82
225. r 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3C8254 the total number of addressable 8 bit registers is 2137 Of these 2137 registers 13 bytes are for CPU and system control registers 60 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 2048 registers are for general purpose use page 0 page 7 including 32 bytes for LCD display registers You can always address set 1 register locations regardless of which of the eight register pages is currently selected Set 1 locations however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C825A Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte 2 064 common working register area eight 192 byte prime register area including LCD data registers and eight 64 byte set 2 area CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes ELECTRONICS 2 3 ADDRESS S
226. r Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt Register OOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2bEH C 0 In the first example if general register 00H has the value OAAH 10101010B the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3C825A P825A INSTRUCTION SET RR Rotate Right RR dst Operation C lt dst 0 dst 7 lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Examples Given Register OOH 31H register 01H 02H and register 02H 17H RR 0
227. r priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 ELECTRONICS 5 17 INTERRUPT STRUCTURE S3C825A P825A FAST INTER
228. ram Memory OFFSET OFFSET NEXT 2 Bits 1 1 1 1 1 1 1 4 bit Working detis e Register Address Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory gt Register Point to Working Pair 8 Bits 16 Bits OPERAND Value used in mue ae a Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3C825A P825A DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte d U 0 1 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H
229. re mode or PWM mode Select the timer 0 input clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 overflow interrupt or timer 0 match capture interrupt Clear timer 0 match capture interrupt pending condition ELECTRONICS 10 5 BASIC TIMER and TIMER 0 S3C825A P825A TOCON is located in set 1 bank 0 at address E5H and is read write addressable using Register addressing mode A reset clears TOCON to OOH This sets timer 0 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 2 The timer 0 overflow interrupt TOOVF is interrupt level IRQO and has the vector address E2H When a timer 0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer 0 match capture interrupt IRQO vector you must write TOCON 1 to 1 To detect a match capture interrupt pending condition the application program polls INTPND 1 When a 1 is detected a timer 0 match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a to the timer 0 match capture interrupt pending bit INTPND 1 Timer 0 Control Register TOCON E5H Set 1 Bank 0 R W Timer 0 input clock selection bits 00
230. relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3C825A P825A Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRPO SIC SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6 5 INSTRUCTION SET S3C825A P825A FLAGS
231. rflow interrupt 001 fxx 256 1 Enable overflow interrupt 010 fxx 64 011 fxx 8 100 fxx Timer 3 match capture interrupt enable bit 101 External clock 0 Disable interrupt P3 5 T3CLKk falling edge 1 Enable interrupt 110 External clock P3 5 T3CLK rising edge 111 Counter stop 0 No effect Timer 3 counter clear bit 1 Clear the timer 3 counter when write Timer 3 operating mode selection bits 00 Interval mode P3 6 T3OUT 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF and match interrupt can occur Figure 13 1 Timer 3 Control Register T3CON 13 2 ELECTRONICS S3C825A P825A 16 BIT TIMER 3 Interrupt Pending Register INTPND DOH Set 1 Bank 0 R W Not used Timer 0 overflow interrupt pending bit Timer 0 match capture interrupt pending bit Timer 3 overflow interrupt pending bit Timer 3 match capture interrupt pending bit Tx interrupt pending bit for UART Rx interrupt pending bit for UART 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 13 2 Interrupt Pending Register INTPND ELECTRONICS 13 3 16 BIT TIMER 3 S3C825A P825A TIMER 3 FUNCTION DESCRIPTION Timer 3 Interrupts IRQ2 Vectors EAH and ECH The timer 3 can generate two interrupts the timer 3 overflow interrupt T3OVF and
232. rking register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 8 16 Bit Register Pair ELECTRONICS 2 11 ADDRESS SPACES S3C825A P825A Special Purpose Registers General Purpose Register A Bank 1 Bank 0 Control Registers System Registers CFH Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area Register Pointers NOTE the S3C825A microcontroller pages 0 7 are implemented Pages 0 7 contain all of the addressable registers in the internal register file Register Addressing Only Indirect Register Addressing Indexed
233. rrupt T1INT T1INT belongs to the interrupt level IRQ1 and is assigned a separate vector address E6H The T1INT pending condition should be cleared by software after IRQ1 is serviced The T1INT pending bit must be cleared by the application sub routine by writing a 0 to the 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the T1 reference data registers TADATA and TBDATA The match signal generates a timer 1 match interrupt T1INT vector E6H and clears the counter If for example you write the value 10H and 32H to TADATA and TBDATA respectively and 8EH to TACON the counter will increment until it reaches 3210H At this point the T1 interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 11 1 TIMER 1 S3C825A P825A Timer 1 Control Register TACON You use the timer 1 control register TACON to Enable the timer 1 operating interval timer Select the timer 1 input clock frequency Clear the timer 1 counter TACNT and TBCNT Enable the timer 1 interrupt Clear timer 1 interrupt pending conditions TACON is located in set 1 bank 0 at address EBH and is read write addressable using register addressing mode A reset clears TACON to 00H This sets timer 1 to disable interval timer mode selects an input clock frequency of fxx 256 and disables timer 1 interrupt You can clear the
234. rrupt request is pending Watch timer INT Enable Disable bit Watch timer Enable Disable bit 0 Disable watch timer INT 0 Disable watch timer 1 Enable watch timer INT Enable watch timer Buzzer signal selection bits 00 0 5 kHz Watch timer speed selection bits 01 1 kHz 00 Set watch timer interrupt to 1 s 10 2 kHz 01 Set watch timer interrupt to 0 5 s 11 4 kHz 10 Set watch timer interrupt to 0 25 s 11 Set watch timer interrupt to 3 91 ms Figure 14 1 Watch Timer Control Register WTCON 14 2 ELECTRONICS S3C825A P825A WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM wrons wrcon eon H oe Enable Disable WTCON O Pending Bit ELECTRONICS WT INT Enable BUZ P5 3 WTCON 6 6 IM fw 2 4 kHz Selector fw 27 fw 2 3 fw 2 4 fw 215 1 Hz Frequency Dividing 32 768 kHz Circuit Clock Selector fLCD 2048 Hz fx Main clock where fx 4 19 MHz fxt Sub clock 32 768 kHz fxt fx 128 fw Watch timer frequency Figure 14 2 Watch Timer Circuit Diagram 14 3 WATCH TIMER S3C825A P825A NOTES 14 4 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C825A microcontroller can directly drive an up to 224 dot 28 segments x 8 commons LCD panel Its LCD block has the following components LCD controller driver Display RAM for storing display data 4 common segment output pins COM4 SEGO
235. ry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3C825A P825A RET Return RET Operation Flags Format Example 6 70 PC SP SP SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex Opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3C825A P825A INSTRUCTION SET RL Rotate Left RL dst Operation C dst 7 dst 0 dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setifthe result is 0
236. s d E LU ott ttu C E 9 10 POLL Ds sete t DERI 9 13 Orns Se he Se eL ELE e DUM UM e NUR UI 9 15 Chapter 10 Basic Timer and Timer 0 ID SUI 10 1 Duns noD UU E 10 1 Basic Timer Control Register 10 2 Basic Timer Function 10 3 S BitaMMern GountenO Ht 10 5 Timer Counter 0 Control Register 10 5 Timer 0 Function 10 8 S3C825A P825A MICROCONTROLLER vii Table of Contents Continued Chapter 11 Timer 1 One 16 Bit Timer Mode Timer 1 11 1 OVS ING DPI 11 1 FUNCTION EUE E 11 1 Block aA ice PM Sec sa eee 11 3 Two 8 Bit Timers Mode Timer A 11 4 ON SIMO hd Define Saat 11 4 5 i I mM 11 4 Chapter 12 8 bit Timer 2 COVEIVICW oos
237. scriptions Chapter 7 Clock Circuit OVEIVICW cand ido o wo ede o Mo uo Mr 7 1 System Clock Circuit 2 7 1 Main Oscillator GT e 1 dom 7 2 rl TET 7 2 Clock Status During Power Down 7 3 System Clock Control Register 7 4 Oscillator Control Register 7 5 Switching the CPU 7 6 Chapter 8 RESET Power Down System sowie tate fale fade fui idee a a sees a MS 8 1 as obo E EX 8 1 Normal Mode Reset 9 8 1 M ed eau eta ae un Ne at 8 2 Power Down MOCdeS teorie trt rtt DER EXER ER HET ATHE AERE AAEN 8 5 SL ea s ead 8 5 lde HC MEME EE 8 6 Chapter 9 I O Ports 9 1 Port Data Heglslers 3 10 9 3 9 4 xong e 9 5 go Bd sree hectic Sea CIEN REED EIC M E EE EE 9 8 Bond
238. scriptions of the addressing modes that are supported by the SS3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C825A P825A interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part I
239. ss Spaces Using the Page Pointer for RAM clear 0 2 5 Setting the Register Pointers ssicseseseicsascestareacsanedacsaacaacaaasaatanataaadadadenanetad abe kat a kat ead 2 9 Using the RPs to Calculate the Sum of a Series of 2 10 Addressing the Common Working Register 2 14 Standard Stack Operations Using PUSH 2 19 Chapter 7 Clock Circuit Switching the CPU 7 6 S3C825A P825A MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control Register 4 5 BTCON Basic Timer Control nennen 4 6 CLKCON System Clock Control 4 7 FLAGS System Flags nnne nnns 4 8 IMR Interrupt Mask 4 9 INTPND Interrupt Pending 4 10 Instruction Pointer High 4 11 IPL Instruction Pointer LOW Byte 4 11 IPR Interrupt Priority 4 12 IRQ Interrupt Request 4 13 LCON LCD Control
240. ster 2 10 2 8 16 Bit Register 7 2 11 2 9 Register File Addressing 2 inert e xp RE ERREUR EE D ES 2 12 2 10 Common Working Register 2 13 2 11 4 Bit Working Register 0 2 15 2 12 4 Bit Working Register Addressing Example 2 15 2 13 8 Bit Working Register 2 16 2 14 8 Bit Working Register Addressing 20 2 17 2 15 Stack Operatiors 3 2 3 tion oes e abet 2 18 3 1 Register Addressing i ttt ete iet t d it d td tt tre 3 2 3 2 Working Register 3 2 3 3 Indirect Register Addressing to Register 4 244 01 3 3 3 4 Indirect Register Addressing to Program 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data Memory 3 9 3 10 Direct
241. ster BRDATA in set 1 bank 0 at address FBH Mode 0 baud rate fxx 16 x BRDATA 1 Mode 2 Baud Rate Calculation The baud rate in mode 2 is fixed at the fosc clock frequency divided by 16 Mode 2 baud rate fxx 16 Modes 1 and 3 Baud Rate Calculation In modes 1 and 3 the baud rate is determined by the UART baud rate data register BRDATA in set 1 bank 0 at address FBH Mode 1 and 3 baud rate fxx 16 x BRDATA 1 18 4 ELECTRONICS S3C825A P825A UART Table 18 1 Commonly Used Baud Rates Generated by BRDATA Baud Rate Oscillation Clock BRDATA Decima Hexdecmal ELECTRONICS 18 5 UART S3C825A P825A BLOCK DIAGRAM 5 8 Internal Data Bus MSO RxD P5 4 MS1 Write to ERE TxD P5 5 UDATA gt Start Tx Control Tx Clock TIP TxD P5 5 IRQ3 Interrupt Rx Clock RIP Receive Rx Control Shift Transition Detector Shift Bit Detector Value Shift 56 7 Register D UARTDATA RxD P5 4 j SAM8 Internal Data Bus Figure 18 5 UART Functional Block Diagram 18 6 ELECTRONICS S3C825A P825A UART UART MODE 0 FUNCTION DESCRIPTION In mode 0 UART is input and output through the RxD P5 4 pin and TxD P5 5 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 2 Write transmission data to the shi
242. struction LD Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3C825A P825A CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the S3C825A control registers are presented in an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this reference chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C825A register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers INTPND STPCON OSCCON are in bank 0 of set 1 ENNIUS BW Decimal 17 6 5 413 2 10 Interrupt pending register INTPND 208 RW STOP controlregister STPCON 209 RW
243. struction Group 6 2 6 2 Flag Notation 6 8 6 3 Instruction Set 6 8 6 4 Instruction Notation 6 9 6 5 Opcode Quick Reference 6 10 6 6 COGS RR RA RRRARE RAM ERR RR RATE ase 6 12 8 1 S3C825A Set 1 Register and Values after 8 2 8 2 S3C825A Set 1 Bank 0 Register Values after RESET 8 3 8 3 S3C825A Set 1 Bank 1 Register Values after RESET 8 4 9 1 S3C825A Port Configuration 2 9 2 9 2 Port Data Register 0 9 3 15 1 LCD Mode Control Register LMOD 15 5 18 1 Commonly Used Baud Rates Generated by 18 5 S3C825A P825A MICROCONTROLLER List of Tables Continued Table Title Page Number Number 19 1 Absolute Maximum 5 19 2 19 2 D C Electrical 19 2 19 3
244. t Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R 4 D1 IR Examples Given Register 9AH register 02H register 03H OBCH and C 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H 03H register 03H ODEH C 0 In the first example if general register OOH contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register OOH ELECTRONICS 6 79 INSTRUCTION SET S3C825A P825A SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src If src 1 1 src 0 Othen RPO 3 7 lt 3 7 If src 1 0 and src 0 1 then RP1 3 7 lt src 3 7 If src 1 src 0 Othen RPO 4 7 lt 4 7 RPO 3 0 RP1 4 7 lt src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H
245. t that pin will generate an interrupt request The corresponding P4PND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing 0 to the corresponding P4PND bit Port 4 Control Register High Byte PACONH E8H Set 1 Bank 1 R W P4 6 INT10 INT9 P4CONH bit pair pin configuration Schmitt trigger input mode Schmitt trigger input mode pull up resistor Output mode open drain Output mode push pull Figure 9 9 Port 4 High Byte Control Register P4CONH 9 10 ELECTRONICS S3C825A P825A PORTS Port 4 Control Register Low Byte PACONL E9H Set 1 Bank 1 R W INT6 5 P4CONL bit pair pin configuration Schmitt trigger input mode Schmitt trigger input mode pull up resistor Output mode open drain Output mode push pull Figure 9 10 Port 4 Low Byte Control Register P4CONL Port 4 Interrupt Control Register P4INT EAH Set 1 Bank 1 R W TTTTTTTT INT11 INT10 9 8 INT7 6 INT5 PAINT bit configuration settings 0 Disable interrupt Enable interrupt Figure 9 11 Port 4 Interrupt Control Register PAINT ELECTRONICS 9 11 PORTS Port 4 Interrupt Pending Register P4PND Set 1 Bank 1 R W o PND11PND10 PND9 PND8 PND7 PND6 PND5 PND4 P4PND bit configura
246. t with individually configurable pins Port 4 pins are accessed directly by writing or reading the port 4 data register P4 at location F4H in set 1 bank 1 P4 0 P4 7 can serve as inputs with or without pull up as outputs push pull or open drain or you can be configured the following functions Low nibble pins P4 0 P4 3 INT4 INT7 High nibble pins P4 4 P4 7 INT8 INT11 Port 4 Control Registers PACONH PACONL Port 4 has two 8 bit control registers PACONH for P4 4 P4 7 and PACONL for P4 0 P4 3 A reset clears the P4CONH and P4CONL registers to OOH configuring pins to input mode You use control registers setting to select input or output mode push pull or open drain Port 4 Interrupt Enable Pending and Edge Selection Registers PAINT PAPND PAEDGE To process external interrupts at the port 4 pins three additional control registers are provided the port 4 interrupt enable register PAINT EAH set 1 bank 1 the port 4 interrupt pending register PAPND sett bank 1 and the port 4 interrupt edge selection register P4EDGE E7H set 1 bank 1 The port 4 interrupt pending register PAPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the PAPND register at regular intervals When the interrupt enable bit of any port 4 pin is 1 a rising or falling edge a
247. t you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C8254 interrupt structure that can be used to release Stop mode are External interrupts P2 4 P2 7 INTO INT3 and 4 0 4 7 4 11 Please note the following conditions for Stop mode release If you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register If you use an internal or external interrupt for stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed How to Enter into Stop Mode Handling STPCON register then writing Stop instruction keep the order LD STPCON 10100101B STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN S3C825A P825A IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some p
248. ted as output mode Figure 9 4 Port 2 Pull up Control Register P2PUR Port 2 Interrupt Control Register P2INT E3H Set 1 Bank 1 R W TTITTTTTT PND3 INT3 PND2 INT2 PND1 INT1 PNDO INTO INTn bit configuration settings 0 Disable interrupt Enable interrupt PNDn bit configuration settings Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending NOTE n is 0 1 2 and Figure 9 5 Port 2 Interrupt Control Register P2INT PORTS 9 7 PORTS S3C825A P825A PORT 3 Port 3 is an 8 bit I O port with individually configurable pins Port pins are accessed directly by writing or reading the Port data register at location F3H in set 1 bank 1 0 7 can serve as inputs as outputs push pull or open drain or you can configure the following alternative functions Low nibble pins P3 0 P3 3 ADO ADS High nibble pins P3 4 P3 7 T3OUT T3PWM T3CAP TOOUT TOPWM TOCAP Port 3 Control Registers PSCONL Port has two 8 bit control registers PSCONH for 4 7 and PSCONL for 3 0 3 3 A reset clears the P3CONH and P3CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure us
249. ter T2DATA Timer 2 interrupt IRQ2 vector EBH generation Timer 2 control register T2CON set 1 Bank 0 EEH read write FUNCTION DESCRIPTION Interval Timer Function The timer 2 can generate an interrupt the timer 2 match interrupt T2INT T2INT belongs to interrupt level IRQ2 and is assigned the separate vector address E8H The T2INT pending condition should be cleared by software when it has been serviced Even though T2INT is disabled the application s service routine can detect a pending condition of T2INT by the software and execute it s sub routine When this case is used the T2INT pending bit must be cleared by the application subroutine by writing a 0 to the T2CON 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the Timer 2 reference data registers T2DATA The match signal generates a timer 2 match interrupt T2INT vector E8H and clears the counter If for example you write the value 10H to T2DATA and OEH to T2CON the counter will increment until it reaches 10H At this point the Timer 2 interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 12 1 8 BIT 2 S3C825A P825A TIMER 2 CONTROL REGISTER T2CON You use the timer 2 control register T2CON to Enable the timer 2 operating interval timer Select the timer 2 input clock frequency Clear the timer 2 counter T2CNT
250. ter D5H Bit Identifier RESET Value Read Write Bit Addressing Mode R Read only W Write only R W Read write S3C825A P825A Name of individual bit or related bits Register location in the internal register file Register address Register name hexadecimal Set 1 Lr m puro om os x x x x x x x gt 0 R W R W R W R W R W R W R W R W Register addressing modejonly Carry Flag C EN Operation does not generate a carry or borrow condition Operation generates carry out or borrow into high order bit 7 EE Zero Flag Z EN Operation result is a non zero value Operation result is zero Sign Flag 5 Operation generates positive number MSB 0 Operation generates negative number MSB 1 Bit number MSB Bit 7 LSB Bit 0 Description of the effect of specific bit settings Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit 4 4 RESET value notation Not used x Undetermined value 0 Logic zero 1 Logic one Figure 4 1 Register Description Format ELECTRONICS S3C825A P825A CONTROL REGISTER ADCON A D Converter Control Register EFH Set 1 Bank 0 Bit Identifier 8 4 3 2 4 9 0 0 0 0 0 0 RESET Value Read Write R W R W R R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C825A 5 4 A D Input Pin Selectio
251. terrupt request The corresponding pending bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a 0 to the corresponding P2INT bit ELECTRONICS 9 5 PORTS 9 6 Port 2 Control Register High Byte 2 EOH Set 1 Bank 1 R W P2 7 TBOUT P2 6 TAOUT P2 5 TICLK P2 4 TOCLK INT3 INT2 INT1 INTO P2CONH bit pair pin configuration Schmitt trigger input mode interrupt on falling edge TOCLK T1CLK Output mpde open drain Alternative function TAOUT TBOUT Output mode push pull Figure 9 2 Port 2 High Byte Control Register P2CONH Port 2 Control Register Low Byte P2CONL E1H Set 1 Bank 1 R W T2OUT T2CLK P2CONL bit pair pin configuration Schmitt trigger input mode interrupt on falling edge T2CLK Output mode open drain Alternative function T2OUT Output mode push pull Figure 9 3 Port 2 Low Byte Control Register P2CONL S3C825A P825A ELECTRONICS S3C825A P825A ELECTRONICS Port 2 Pull up Control Register P2PUR E2H Set 1 Bank 1 R W P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2141 P2 0 P2PUR bit configuration settings 0 Disable pull up resistor Enable pull up resistor NOTE The corresponding pull up resistor is disabled automatically when a bit of port 2 is selec
252. timer 1 counter at any time during the normal operation by writing a 1 to TACON 3 To enable the timer 1 interrupt IRQ1 vector E6H you must write TACON 7 TACON 2 and TACON 1 to 1 To generate the exact time interval you should set TACON 3 and 0 to 10B which clear counter and interrupt pending bit When the T1INT sub routine is serviced the pending condition must be cleared by software by writing a to the timer 1 interrupt pending bit TACON O Timer 1 Control Register TACON EBH Set 1 Bank 0 R W Timer 1 operation mode selection bit Timer 1 interrupt pending bit 0 Two 8 bit timers mode Timer A B 0 No interrupt pending 1 One 16 bit timer mode Timer 1 0 Clear pending bit when write 1 Interrupt is pending when read Timer 1 clock selection bits 1 No effect when write 000 fxx 256 Timer 1 interrupt enable bit 001 fxx 64 0 Disable interrupt 010 fxx 8 1 Enable interrupt 011 fxx 111 T1CLK Timer 1 counter run enable bit external clock rising edge 0 Disable counter running 1 Enable counter running Timer 1 counter clear bit 0 No affect 1 Clear the timer 1 counter when write Figure 11 1 Timer 1 Control Register TACON 11 2 ELECTRONICS S3C825A P825A TIMER 1 BLOCK DIAGRAM fxx 256 16 Bit Up Counter Read Only lt gt Timer 1 Buffer Register 16 bit Counter Clear Signal Match Signal Timer 1 Data Register
253. ting OSCCON 2 Oscillator Control Register OSCCON D2H Bank 0 Set 1 R W System clock selection bit 0 Main select 1 Sub select Not used for S3C825A Not used for S3C825A Sub system oscillator control bit 0 Sub oscillator RUN 1 Sub oscillator STOP Main system oscillator control bit 0 Main oscillator RUN 1 Main oscillator STOP Figure 7 8 Oscillator Control Register OSCCON ELECTRONICS 7 5 CLOCK CIRCUIT S3C825A P825A SWITCHING THE CPU CLOCK Data loading in the oscillator control register OSCCON determine whether a main or a sub clock is selected as the CPU clock and also how this frequency is to be divided by setting CLKCON This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies 5 0 select the main clock fx or the sub clock fxt for the CPU clock OSCCON 3 start or stop main clock oscillation and OSCCON 2 start or stop sub clock oscillation CLKCON 4 3 control the frequency divider circuit and divide the selected fxx clock by 1 2 8 16 For example you are using the default CPU clock normal operating mode and a main clock of fx 16 and you want to switch from the fx clock to a sub clock and to stop the main clock To do this you need to set CLKCON 4 3 to 11 OSCCON 0 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxt and stops main clock oscillation The following steps must be take
254. tion operand are incremented by Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected Flags TOSONO Format Bytes Cycles dst opc 1 4 opc dst 2 4 Examples Given RO 1BH register OCH and register 1BH OFH INC RO gt RO 1CH INC OOH gt Register 00H INC RO gt RO 1BH register 01H 10H S3C825A P825A Opcode Addr Mode Hex dst rE r r to 20 R 21 IR In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H 6 44 ELECTRONICS S3C825A P825A INSTRUCTION SET INCW ncrement Word INCW dst Operation dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffe
255. tion pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to use an EXIT statement Before After Address Data 0052 Address Data 0060 PCL old PCH 60 Main SP 0022 Exit 22 Data Memory Stack ELECTRONICS S3C825A P825A INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation In application programs a IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F Example The instruction IDLE stops the CPU clock but not the system clock NOP NOP NOP ELECTRONICS 6 43 INSTRUCTION SET INC Increment INC dst Operation dst lt dst 1 The contents of the destina
256. tion settings Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending Figure 9 12 Port 4 Interrupt Pending Control Register P4PND Port 4 Interrupt Edge Selection Register P4EDGE E7H Set 1 Bank 1 R W ERRARE OR RA EDGE11 EDGE10 EDGE9 EDGE8 EDGE7 EDGE6 EDGES EDGE4 P4EDGE bit configuration settings 0 Falling edge detection Rising edge detection Figure 9 13 Port 4 Interrupt Edge Selection Register PAEDGE S3C825A P825A ELECTRONICS S3C825A P825A PORTS PORT 5 Port 5 is an 7 bit I O port with individually configurable pins Port 5 pins are accessed directly by writing or reading the port 5 data register P5 at location F5H in set 1 bank 1 P5 0 P5 6 can serve as inputs or as push pull open drain outputs You can configure the following alternative functions Low nibble pins P5 0 P5 3 SCK SI SO BUZ High nibble pins P5 4 P5 6 TXD Port 5 Control Registers PSCONH P5CONL Port 5 has two 8 bit control registers for P5 4 P5 6 and for 5 0 5 3 and PSCONH 7 6 for TXD RXD output control A reset clears the PSCONH and P5CONL registers to OOH configuring all pins to input mode and TXD RXD to output disable You use control registers settings to select input or output mode and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you co
257. tions All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are design
258. turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for S3C7 S3C6 S3C8 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM88 The 5 5 88 is a relocatable assembler for Samsung s S3C8 series microcontrollers The SASM88 takes a so
259. ulate bits 7 and 6 of the LCON register 1 5 Bias 1 4 Bias 1 3 Bias S3C825A S3C825A S3C825A LCON 7 6 LCON 7 6 LCON 7 6 Figure 15 5 LCD Bias Circuit Connection 15 6 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER In Case of Internal S3C825A LCON 7 6 NOTE For power saving and LCD off LCON 7 6 must be set to For a normal display LCON 7 6 must be set to 11B Figure 15 6 Example 1 for the Usage of LCON 7 6 ELECTRONICS 15 7 LCD CONTROLLER DRIVER S3C825A P825A In Case of Internal S3C825A LCON 7 6 NOTE For power saving and LCD off LCON 7 6 must be set to 00B For a normal display LCON 7 6 must be set to 01B Figure 15 7 Example 2 for the Usage of LCON 7 6 15 8 ELECTRONICS S3C825A P825A LCD CONTROLLER DRIVER SEG2 SEG1 SEGO Vict Vss Vict Vic2 Vi Vics Vss VLC Vic2 Vica Vi Vics Vss Vict Vic2 Vi Vss Vict Vic2 Vi Vics Vss VLC Vic2 Vi Vi c4 Vics Vss Vici 1 8 Vi c4 5 0 OV 1 8 Figure 15 8 LCD Signal Waveforms 1 3 Duty 1 3 Bias ELECTRONICS 15 9 LCD CONTROLLER DRIVER S3C825A P825A SEG1 SEGO Vss COMO COM1 COM2 lt Vict x Vice Vics P o ie Vi Vics Vss Vice Vi c4 Vics Vss Vict Vice Vi Vica Vics Vss Vict Vice Vi c4 Vics
260. up Resistor Enable Bit Pull up disable 1 Pull up enable P5 1 Pull up Resistor Enable Bit Pull up disable Pull up enable 0 5 0 Pull up Resistor Enable Pull up disable 1 Pull up enable ELECTRONICS 4 CONTROL REGISTERS S3C825A P825A PGOCON Port Group 0 Control Register F9H Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 4 1 7 SEG28 31 Mode Selection Bits o o mputmos o 1 Input mode puleup o 1 Open drain output mode Push pull output mode 5 4 P1 0 1 3 SEG24 27 Mode Selection Bits o o inputmode 0 1 00 5 Open drain output mode 1 Open drain output mode Push pull output mode 3 2 P0 4 0 7 SEG20 23 Mode Selection Bits Co o mumm Fo inputmode pulp 71129 1 0 P0 0 0 3 SEG16 19 Mode Selection Bits Input mode pull up Open drain output mode Push pull output mode 4 32 ELECTRONICS S3C825A P825A CONTROL REGISTER PG1CON Port Group 1 Control Register FAH Set 1 Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P8 0 P8 3 SEG12 15 Mode Selection Bits o o 1 o 1 Open drain output mode Push pull output mode 5
261. urce file containing assembly language statements and translates into a corresponding source code object code and comments The SASM88 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code OBJ file by HEX2ROM the value FF is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all S3C8 series microcontrollers All required target system cables and adapters are included with the device specific target board ELECTRONICS 22 1 DEVELOPMENT TOOLS S3C825A P825A IBM PC AT or Compatible RS 232C SMDS2 lt gt PROM OTP Writer Unit Target Application System gt RAM Break Display Unit Trace Timer Unit TB825A lt SAMB8 Base Unit Target Board Eva 4 Power Supply Unit Chip Figure 22 1 SMDS Product Configuration SMDS2 22 2 ELECTRONICS S3C825A P825A DEVELOPMENT TOOLS TB825A TARGET BOARD The TB825A target board is used for the S3C825A microcontroller It is supported with the SMDS2 TB825A Idle Stop Y1 Sub Cl
262. urce mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 2 4 62 ror 6 63 r Ir opc SIC dst 3 6 64 R R 6 65 R IR opc dst SIC 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01H 02H and register 02H 23H TCM RO R1 TCM RO R1 TCM 00H 01H TCM 00H 01H RO 0C7H R1 02H 2 1 RO 0C7H R1 02H register 02H 23H Z 0 Register OOH 2BH register 01H 02H Z 1 Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2BH Z 0 E gt EN In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3C825A P825A INSTRUCTION SET TM Test Under Mask TM dst src Operation dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the correspond
263. using addressing modes A 32 byte LCD display register file is implemented There are 2 137 mapped registers in the internal register file Of these 2 064 are for general purpose This number includes a 16 byte working register common area used as a Scratch area for data operations eight 192 byte prime register areas and eight 64 byte areas Set 2 Thirteen 8 bit registers are used for the CPU and the system control and 60 registers are mapped for peripheral controls and data registers Seven register locations are not mapped ELECTRONICS 2 1 ADDRESS SPACES S3C825A P825A PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C825A has 48K bytes internal mask programmable program memory The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 49 151 48K bytes Internal Program Memory Area Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS S3C825A P825A ADDRESS SPACES REGISTER ARCHITECTURE In the S8C825A implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The uppe
264. ut Cout capacitance I O capacitance Table 19 5 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 C Data retention VpppR 2 0 5 5 V supply voltage Data retention Vpppa 2 25 C 1 uA supply current Stop mode RESET Occurs Oscillation Y Stabilization lt gt Time y Normal lt Data Retention Mode gt Operating Mode Execution of STOP Instrction NOTE _ twar is the same as 4096 x 16 x 1 fxx Figure 19 3 Stop Mode Release Timing Initiated by RESET 19 6 ELECTRONICS S3C825A P825A ELECTRICAL DATA Oscillation Stabilization Time 1 Stop Mode _ gt PNE MS Idle Mode Data Retention Mode A Execution of STOP Instruction Normal Operating Mode Interrupt NOTE _ twaitis the same as 16 x 1 BT clock Figure 19 4 Stop Mode Release Timing Initiated by Interrupts ELECTRONICS 19 7 ELECTRICAL DATA S3C825A P825A Table 19 6 A D Converter Electrical Characteristics TA 25 to 85 C 2 7 V to 5 5 V Vss CPU clock 8 MHz 10 bit resolution 50 x fxx 4 fxx 8 MHz Analog Input Impedance RAN Analog Input Current AVper Vpp OV Analog Block Current 2 AVrer Vpp 5V Vpp 3V 3 pe Vpp SV When power down mode NOTES 1 Conversion time is the time required from the moment a conversion operation st
265. ut or push pull open 4 bit programmable I O port Input or 32 52 55 54 57 0 exp 1 6 ELECTRONICS S3C825A P825A PRODUCT OVERVIEW Table 1 1 S3C825A Pin Descriptions Continued Pin Pin Circuit Pin Type Description Type Numbers note Vppi Power input pins for core block 10 11 12 13 fF 2 12180415 14 16 Xour Main oscillator pins TEST I Test signal input pin must be connected to Reser Je 20 22 P2 4 TSCAP VO Timer3capureinut 14 3284 P36 INT4 INT11 10 External interrupt input pins 02 4 VO input pi SCK SI SO clock serial data input serial data 42 44 44 46 P5 0 P5 2 output RXD TXD VO UART data input output 46 47 48 49 5 4 5 5 VO 0 H 32 Vppe Power input pins for peripheral block VO LCD Common signal output 51 50 51 52 53 52 55 54 57 P6 0 P6 3 SEGO SEG3 LCD Common Segment signal output H 32 56 59 58 61 P6 4 P6 7 COM4 COM7 SEG4 SEG11 LCD segment signal output H 82 60 67 62 69 SEG12 SEG15 68 71 70 73 SEG16 SEG23 72 79 74 80 1 SEG24 SEGS 80 1 7 2 9 NOTE Parentheses indicate pin number for 80 QFP 1420 package ELECTRONICS 1 7 PRODUCT OVERVIEW S3C825A P825A PIN CIRCUITS VDD Open drain P Channel Dat
266. x 8 Timer B interrupt enable bit 11 fxx 0 Disable interrupt 1 Enable interrupt Timer B counter run enable bit 0 Disable counter running 1 Enable counter running Timer B counter clear bit 0 No affect 1 Clear the timer B counter when write Figure 11 4 Timer B Control Register TBCON ELECTRONICS S3C825A P825A TACON 6 4 fxx 256 fxx 64 fxx 8 MUX fxx 5 TACON 2 T1CLK R TA Buffer Register ic TA Counter Clear Signal TA Match Signal TB Counter Clear Signal TB Match Signal TBDATA Lo TB Buffer Register fxx 256 TBCON 2 fxx 64 8 fxx 8 MUX fx p TBCNT R TBCON 5 4 TIMER 1 Clear Match TAOUT Pending TACON 1 gt IRQ1 TBCON 1 0 Pending 1 TBOUT Clear NOTE When 7 is 0 two 8 bit timer Figure 11 5 Timer A and B Function Block Diagram ELECTRONICS TIMER 1 S3C825A P825A NOTES 11 8 ELECTRONICS S3C825A P825A 8 BIT TIMER 2 8 BIT TIMER 2 OVERVIEW The 8 bit timer 2 is an 8 bit general purpose timer Timer 2 has the interval timer mode by using the appropriate T2CON setting Timer 2 has the following functional components Clock frequency divider fxx divided by 256 64 8 or 1 with multiplexer External clock input P2 2 T2CLK 8 bit counter T2CNT 8 bit comparator and 8 bit reference data regis
267. y the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQO IRQ1 GroupB IRQ2 IRQ3 GroupC IRQS5 IRQ6 IRQ7 B21 B22 C21 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A The setting 101B would select the relationship C gt B A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS S3C825A P825A INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority D7 D4 D1 0 IRQO gt IRQ1 1 IRQ1 gt IRQO 0 Undefined Group B 1 gt gt 0 IRQ2 gt IRQ4 0 A gt B gt C 1 IRQ3 IRQ4 gt IRQ2 1 B gt A gt C Subgroup B 0 C gt A gt B 0 IRQ3 gt IRQ4 1 gt gt 1 IRQ4 gt IRQ3 0 A gt C gt B Group C 1 Undefi
268. y Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 2 Interrupt Group Priority Control IRQ2 gt IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO NOTE Interrupt Group A IRQO IRQ1 Interrupt Group B IRQ2 IRQ3 IRQ4 Interrupt Group C IRQ5 IRQ6 IRQ7 S3C825A P825A CONTROL REGISTER IRQ Interrupt Request Register DCH Set 1 Bit Identifier o8 4 3 2 4 9 0 0 0 0 0 0 0 RESET Value 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit External Interrupt P4 0 P4 3 Not pending Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupt P4 4 P4 7 ot pending ending 5 Level 5 IRQ5 Request Pending Bit External Interrupt P2 4 P2 7 ot pending ending 4 Level 4 IRQ4 Request Pending Bit Watch Timer ot pending ending 3 Level 3 IRQ3 Request Pending Bit SIO Transmit UART Receive Not pending Pending 2 Level 2 IRQ2 Request Pending Bit Timer 2 Timer 3 Match Capture or Overflow Not pending Pending 1 Lev 11 IRQ1 Request Pending Bit Timer Timer 1 ot pending ending 0 Level 0 IRQO Request Pending Bit Timer 0 Match Capture or Overflow Not pending Pending m e ELECTRONICS 4 CONTROL REGISTERS S3C825A P825A Control R
269. ystem clock ELECTRONICS 7 1 CLOCK CIRCUIT MAIN OSCILLATOR CIRCUITS XIN XouT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx XIN XOUT Figure 7 3 RC Oscillator fx S3C825A P825A SUB OSCILLATOR CIRCUITS 32 768 kHz Figure 7 4 Crystal Ceramic Oscillator fxt XTIN XTouT Figure 7 5 External Oscillator fxt ELECTRONICS S3C825A P825A CLOCK STATUS DURING POWER DOWN MODES CLOCK CIRCUIT The two power down modes Stop mode and Idle mode affect the system clock as follows n Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter n Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers timer counters and watch timer Idle mode is released by a reset or by an external or internal interrupt Stop Release Main System Oscillator Circuit Selector 1 OSCCON 3 5 0 STOP OSC 1 8 1 4096 inst STPCON Frequency Dividing Circuit 14 31 2 1 8 1 16 Sub system Oscillator Circuit Watch Timer LCD Controller OSCCON 2 Basic Timer Timer Counters Watch Timer LCD Controller SIO A D Converter System Clock CPU Clock IDLE Instruction Figure 7 6 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK CIRCUIT S3C8

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