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TAMC900 - powerbridge.de

1. 44 9 2 1 Data Formata sridi NN 5 44 9 2 2 Clock Duty Cycle 2 11 45 9 3 Shielding sss u n enne reaa Seara ae raae a araa a aaa aaea a aar EHe a Aaaa aa aae Uana Eaa a aeaa a rea Eae Sa 46 47 11 CLOCK DISTRIBUTION ee 48 12 LVDS LINK een 50 13 ON BOARD CPLD eee dead sneket 51 13 1 interface to FPGA Dee en ee enden iai 51 13 2 CPLD Register Description rrrrsvnnnnvvnnnvvnnnnvnnnnnvnnnnvnnnnvnnnnnvnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnennnnnn 52 13 2 1 ADC x Control Register Address 0x00 to 0x07 aaaiaaaaaaaassaassaassanasanassaanaaanaaananansaansaannaanna 53 13 2 2 SiCA Input Register 1 Address 0x08 a2iiaaaaaaaaaasaaassaassaaasaaasaaasaaanaaanaaanaaanaaanaaanaaaanaaanaaana 53 13 2 3 SICA Input Register 2 Address 0x09 aiaaaiaaaaaaaaaasaaasaaassaaasaaasananaaanaaanaaanaaanaaanaaanaaaansaandaana 54 13 2 4 SiCA Output Register 1 Address OXOA iaaaaaaaaasaaaassaassaasaaasaaasaaanaaanaaanaaanaaanaaanaaanaaaanaaana 54 13 2 5 SiCA Output Register 2 Address OXOB 2aaaaaaaaaaaaassaassaassaasaaassaasaaanaaansaanaaansaanaaanaaaanaaana 54 13 2 6 SiCA
2. 31 6 5 Sample Clock Configuration 0 1 32 6 6 Trigger Configuration 0 1 serrnnvrnnnnvnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnennn 33 6 7 333333 1311131 1111111 111 1 1111111 34 6 8 Channel DMA Base Descriptor Addresses 0 2 35 6 9 Channel Pre Trigger Data Size 2 35 6 10 Channel Data 0722 eee areas 36 6 11 General DMA Status sanskrit utearealene 37 6 12 Ch
3. 41 8 2 gt MMC INterface 22 i21 2211iidvlsunsviagnusan aguvana sgavduung av adassundu knsanusa aganu aaangannusangu anada udanska ungdugau itann aan 41 8 3 AMC Interface inci cc cece m dre vene een ae a aane aeaaeae denne en Eee 42 8 4 RAM Interface 2 22aaaa2a2aaaaaannnnnannnnnnnnnnnnnnnAnNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN NAN NUN NN en ee Kenne han 43 8 5 ADC INTC aCe init cae cc tierce cerca ceteteec sat eee ae aeoe haeo adana aduan nenn an nn Ban da genen Een nennen 43 9 44 9 1 ACH DE Characteristics 2 22 2 en re 44 9 1 1 Min Max Sample Rate 1 0 44 9 1 2 Input Voltage Range mist 3 3333 3 3 1 3 44 9 1 3 Input Frequency Range scsi 44 9 2 Operational 6 22
4. 66 17 2 VOCONNECLOr 35s 67 17 3 MMC JTAG Connector Factory Use 69 17 4 Payload JTAG OONN C O T ea a are a et 69 12 2 AMG Connector scx ceed Rn 69 TAMC900 User Manual Issue 2 0 1 Page 6 of 71 List of Tables TABLE 2 1 te tdci 11 TABLE 3 1 AMC MODULE 2222 6 13 TABLE 3 2 AMG MODULE EXTRACTION i 1 13 TABLE 4 1 ADC CHANNEL GROUP 2222 0200
5. 12 3 1 ESD Prot amp cti n 2 2 2 eid 12 3 2 Thermal Considerations si nioa ga saecctetecsttedevseeeduccdeonddetarevseedtqnedessectsstctsandeesetesde 12 3 3 AMC Module Insertion amp HOt Swap rrnssvrnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennn 13 3 3 1 Insertion A a era Huna ute natt 13 3 3 2 XACT ON it Sethe thes We thet seven pee ee arteria rabatten 13 4 FUNCTIONAL PROCEDURES 1 niaaa nianiar daaraan raia 14 4 1 Gh nnel E gic 2 2 22 E E T 15 4 2 2 2 2 0 00 16 4 2 1 Operation Modes 1112 1 661 1 1 1 17 4 3 DMA Engine 2 18 44 3333 0 1333 31 31 1 0 18 4 5 Sample Rate LOGIC 1053 1 20 4 6 20 4 6 1 Power 2 Haren 1111 1 9 20 4 6 2 Pre Initialization Setup
6. Issue Description Date 1 0 Initial Issue April 2008 1 1 Minor changes in chapter 9 May 2008 Added details to chapter 4 3 1 2 Corrections in Crosspoint Switch Control Register August 2008 Different minor corrections and additions 1 0 3 New User Manual Issue Notation January 2009 Correction of MMC JTAG Connector Pin Assignment 2 0 0 Update to TAMC900 V2 0 November 2009 Added FPGA code description 2 0 1 Firmware Upgrade to Version 2 April 2010 Page 3 of 71 TAMC900 User Manual Issue 2 0 1 Table of Contents 1 PRODUCT DESCRIPTION 10 2 TECHNICAL SPECIFICATION 11 3 HANDLING AND OPERATING
7. 14 TABLE 4 2 ADC DATA FORMAT WITH SIGN EXTENSION iaiaaiiaaiaaaaaaasaassaasaasaasnasaannansanananansnannnnananananana 15 TABLE 4 3 DMA 5 0 2 2000 19 TABLE 5 1 TAMC900 PCI DEVICE 2222 0000 24 TABLE 5 2 TAMC900 LOCAL SPACE CONFIGURATION uu nunseersnersnersnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nn nennen 24 TABLE 5 3 TEP TYPE 7 7 7 1 3 3 4 25 TABLE 2 7 Br RR 1 27 TABLE 5 5 DMA DESCRIPTOR 5 nn 27 TABLE 6 1 MODULE STATUS REGISTER ADDRESS 0X0 aiiaiaaiaaaaaaaasaasaasaasnannnannannnannnnnannnanansnannannannnana 28 TABLE 6 2 DCM MULTIPLY DIVIDE REGISTER A
8. DATA IN DQ 17 0 DATA OUT D 17 0 ADDRESS A 17 0 Ri RPS ODR II Ve me x18 Source CLK gt K K C C CLKIN Q Q FPGA DATA IN DQ 17 0 DATA OUT D 17 0 ADDRESS gt A 17 0 Ri QDRIII W gt WPS x18 Source CLK K K C C CLKIN Q Q Figure 10 1 QDR II SRAM Interface The TAMC900 uses 4 Burst SRAM to lower address bus switching speed and simultaneously achieve read and write accesses to independent addresses of the SRAM without any wait cycles The RAM can be clocked with up to 250 MHz Effective maximum access speed depends on FPGA speed and available routing resources For timing details regarding the QDR II SRAM interface please refer to the QDR II SRAM data sheet TAMC900 User Manual Issue 2 0 1 Page 47 of 71 11 Clock Distribution The TAMC900 has several Clock sources e 3 Clock Inputs from the SICA e 1 Clock Input from AMC interface connector e 2 local Clocks e 2 Clock outputs of the FPGA The Clocks are distributed to the ADCs and the FPGA Configuration of the Clock Distribution is done via the on board CPLD Refer to the CPLD registers description for programming details AMC Clock Clock 1 Clock 2 Clock 3 MUX1 FB MGT CLK mar ma za GCLK gi Golbal FPGA Clock 5 Buffer lo N 10 1 3 x x olo ICS 3 02
9. m ADCO Local Clocks 25 ADC1 ADC 2 gt ADC 3 ICS85314 11 ke el Switch SW CLKOUT 2 SW_CLKOUT_3 gt ADC 4 2 5 m ADC5 SY89540U _ pl ADC 6 Differential to LVTTL conversion m ADC 7 of the ADC clock signals is done by ICS853T4 11 Figure 11 1 Clock Distribution Block Diagram MC100ES60T23 devices The external clock inputs Clock 1 Clock 2 and Clock 3 are LVDS compatible AMC Clock is the FCLKA signal from the AMC connector routed through a jitter attenuator ICS874003 02 to achieve a max Jitter below 40ps even if the original FCLKA has much more jitter In most systems FCLKA is a 100 MHz PCI Express reference clock that may be a SSC Spread Spectrum Clock TAMC900 User Manual Issue 2 0 1 Page 48 of 71 The first local Clock LCLK_250 is an on board 250 MHz oscillator with LVDS signaling It is possible to turn the oscillator off via the on board CPLD The second local clock is a 50 MHz single ended clock The following table provides the pin assignment ofthe FPGA local clock inputs Signal Name Virtex 5 Pin LCLK_250 D15 LCLK_250 E15 LCLK_50 AC14 Table 11 1 FPGA Local Clock LCLK_250 Inputs The two FPGA Clock outputs CLKOUTO and CLKOUT1 provide the ability to run the ADCs with user specified clocks that are generated in the FPGA The following table provides the pin assignment of the clock outputs Signal Name Virtex 5 Pin to
10. Differential Signaling 159 Rx20 159 0 Differential Signaling 162 Tx20 162 Tx20 Differential Signaling JTAG Clock Input JTAG TMS Input TRST JTAG Reset Input 170 GND Logic Ground a oa gt SI Table 17 4 Pin Assignment AMC Connector TAMC900 User Manual Issue 2 0 1 Page 71 of 71
11. Setting the Linked List Pointer to 0x0 selects the first DMA descriptor memory address TAMC900 User Manual Issue 2 0 1 Page 19 of 71 Besides this steering information the descriptor stores the information about the pointer address to the DMA memory region inside the host memory and the information about the length of this memory region Be aware that the length is defined in samples Hence the number of required bytes is twice as large as the defined length 4 5 Sample Rate Logic The sample rate logic allows defining two different clocks that can be used as sample rate for the different ADC channel groups There are two Digital Clock Managers DCMs that generate a clock based on a multiply divide ratio The internal control logic employs clock multiplexers for switching the clocks to a certain group The multiplexers are glitch free so that switching can be performed at every time Switching during runtime processing is not recommend In accordance with that both groups can be set into a common clock mode sourced from DCMO or DCM1 or an independent clock mode 4 6 Module Behavior 4 6 1 Power Up Reset The module has reset conditions after it has been activated For this the PCI Express Endpoint s dedicated reset signal is used This means e all registers have their reset value DCMs have reset settings e trigger signals are reset e the QDR memories invalidate their data e all DMA Engines lose their information e
12. 8 differential Analog Input Gain depends on Signal Conditioning Adapter used Analog Input Voltage Range depends on Signal Conditioning Adapter ADC analog input Voltage differential 2Vp p ADC input common mode Voltage 1V to 1 9V ADC INL DNL Error 1 0 5 LSB typical Number of Clock Inputs 3 differential LVDS Number of Trigger Inputs 3 differential LVDS 1 O Connector 120 pin Connector to Signal conditioning adapter that holds the I O Connectors for the analog inputs clocks and trigger signals Physical Data Power Requirements 2A typical 4A max 12V DC Payload Power 50 mA typical 3 3V DC Management Power The exact Power requirement of the TAMC900 depends on Signal Cond Adapter used and FPGA utilization Temperature Range Operating 0 C to 55 C Storage 0 C to 70 C MTBF 391000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment Gs 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Humidity 5 95 non condensing Weight 100g Table 2 1 Technical Specification TAMC900 User Manual Issue 2 0 1 Page 11 of 71 3 Handling and Operating Instructions Do not exceed the maximum input
13. 0 0 0x10 MEM 1024 32 Little Register Space DMA Descriptor 1 1 0x14 MEM 8192 32 Little Space Table 5 2 TAMC900 Local Space Configuration Accessing the module spaces have to be performed in single 32 bit transactions Error handling has been implemented in accordance with PCI Express Specification to ensure system stability This means on the one hand unsupported TLPs compare Table below TLP Type Summary are dumped so that these may not affect the internal logic On the other hand an error message TLP will be generated and transmitted to Root Complex TAMC900 User Manual Issue 2 0 1 Page 24 of 71 TLP Type Handling Memory Read 32 Bit Addressing Permitted Memory Write 32 Bit Addressing Permitted Memory Read 64 Bit Addressing Prohibit Error Message Memory Write 64 Bit Addressing Prohibit Error Message I O Read Prohibit Error Message I O Write Prohibit Error Message Read Locked 32 Bit Addressing Prohibit Error Message Read Locked 64 Bit Addressing Prohibit Error Message Configuration Read 0 1 Permitted Configuration Write 0 1 Permitted Messages Dumped Completion Prohibit Error Message Completion Locked Prohibit Error Message Table 5 3 TAMC900 User Manual Issue 2 0 1 TLP Type Summary Page 25 of 71 5 2 Register Space The register space has been defined to be 32 bit Thus all regist
14. 6 11 General DMA Status In order to bundle the DMA status over all channels this register has been implemented This simplifies the detection of the DMA event generating channel interrupt source Bit Symbol Description Access Reset Value ECH7 ECH6 ECH5 ECH4 The bits indicate an event ECHx on channel x ECH3 1 event pending 0 no event on channel ECH2 ECH1 gt AJOJN ECHO 0 Di DD D DD v v d Oo lo 0 0 0 0 o Table 6 11 Global DMA Status Register Address 0xA4 The channel event information is obtained from the single channel DMA status registers Thus it must not be cleared here TAMC900 User Manual Issue 2 0 1 Page 37 of 71 6 12 Channel DMA Status 0 7 The different events that may occur during processing are shown afterwards There are eight such registers one for every channel which source the General DMA Status register Bit Symbol Description Access Reset Value 15 13 Reserved R 0 12 OFERR This bit indicates that an ADC overflow has occurred R W 0 If this information is desired it can be enabled in the corresponding Channel Configuration register 11 10 Reserved R 0 9 SEQLE The Sequence Last Event SEQLE indicates that a R W 0 Descriptor has been processed that is the last of a Linked List 8 SEQHI Seq
15. Check 30777 7 7377 73 7 1111 1 15 20 4 6 3 Channel 3 313 131 11 1 1 1 1 1111 5 21 47 e Y alal oTe 2 ne a tage an seede 21 4 7 1 Channel Reset uit 3 33 3 3 3 13313111111 9090 21 4 7 2 1 3 231 1 1 1 11 21 4 7 3 Deseript r Change 133 3 3 11 11 1111111111 22 4 7 4 Channel aina 1 23 4 8 138651 PAA E A E A E E A E E E A E E A A a 23 4 8 1 Proc ssing Ciech 42 He eteren akka ral al gk 23 5 ADDRESS MAP 3 0 24 5 1 PCI Express Configuratii z iieiaeie taeao eadar aa Ge 24 5 2 Register Space aksessnett aan eo ea aa ae Aa pakaa EEan cane 26 5 3 DMA Descriptor Space 2u 2 nen coat 27 6 REGISTER DESCRIPTION 28 6 1 Module Status and DCM 0 1 Status Register rrnnnvnnnvvnnnnvennnnvnnnnnnnnnvnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenr 28 6 2 DCM Multiply Divide 0 1 rrnnnvnnnnvennnnvnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 29 6 3 Global Channel ConfiguratiOn rssrrnnnnvnnnnvnnnnvennnnnnnnnnnnnnvennnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennn 30 6 4 Global Reset and Software Trigger 2
16. DMA Descriptor Structure Providing steering information for every descriptor separately allows process steering during runtime and offers a different handling of the descriptors Notice that changing the descriptors after channel activation is not recommended The flags are described afterwards The identifier OxC marks the first instruction word of a set It is used to detect if a descriptor is provided at the currently accessed memory address that can be used by a DMA Engine If the identifier is not set the internal structure will not use the descriptor The Last identifier Flag LF marks the last descriptor of the linked list This information is used to execute post DMA sequence tasks e g stop data acquisition and transmission The information that a certain descriptor has been processed can be sent via an interrupt to the host respective a software driver during processing by setting the Host Interrupt HI flag Processing all linked list DMA buffers in a cyclic manner if required is possible by setting the Continue at Base Address CBA descriptor flag If the bit is set the DMA base descriptor start address compare chapter Channel DMA Base Descriptor Addresses 0 7 is taken next regardless of a defined subsequent descriptor in the current descriptor The Subsequent Linked List Pointer is an address inside the module s descriptor address range see above Due to the 36 kbit Block RAM size the address length is 10 bit
17. MMC The Module Management Controller of the TAMC900 handles the IPMI protocol controls front panel LEDs and the payload power Four on board temperature sensors and the power supplies are observed by the MMC to ensure correct and secure operation of the TAMC900 15 1 Indicators For a quick visual inspection the TAMC900 offers 3 LEDs in the front panel and seven on board LEDs For a detailed description of the on board LEDs please refer to chapter On Board Indicators 15 1 1 Front Panel LEDs TAMC900 User Manual Issue 2 0 1 LED Color State Description HS Blue Off No Power or module is powered Short Blink Hot Swap negotiation extraction Long Blink Hot Swap negotiation insertion On Module is ready to be powered or module is ready to be unpowered FAIL Red Off No fault On Failure or out of service status USER Green Off Board is unpowered On Board is powered and OK Blink controlled by on board FPGA Table 15 1 Front Panel LEDs Page 62 of 71 15 2 Temperature and Voltage Sensors The TAMC900 provides access to four temperature sensors via IPMI TEMP ADC1 Temperature Sensor near ADC 0 3 TEMP ADC2 Temperature Sensor near ADC 4 7 TEMP_RAM Temperature Sensor at the QDR II SRAM devices TEMP_V5 CORE On DIE Temperature Sensor of the Virtex 5 TEMP_ADC1 TEMP_RAM TEMP_ADC2 Figure 15 1 Temperature Sensor Locations The TAMC900 provides access to two voltage s
18. The following table shows the relationship between the analog input voltage the digital ADC output data and the overflow bit OF TAMC900 User Manual Issue 2 0 1 Page 44 of 71 A nt An OF Data Data 2V Range Offset Bin 2 s Compl gt 1 000000V 1 Ox3FFF 0x1 FFF 0 999878V 0 Ox3FFF 0x1 FFF 0 999756V 0 Ox3FFE Ox1 FFE 0 000122V 0 0x2001 0x0001 0 000000V 0 0x2000 0x0000 0 000122V 0 0x1 FFF Ox3FFF 0 000244V 0 Ox1 FFE Ox3FFE 0 999878V 0 0x0001 0x2001 1 000000V 0 0x0000 0x2000 lt 1 000000V 1 0x0000 0x2000 Table 9 1 ADC Output Data Format The FPGA Logic performs a sign extension of the ADC Data Refer to chapter Channel Logic for more information 9 2 2 Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50 duty cycle Using the clock duty cycle stabilizer is recommended for most applications This circuit uses the rising edge of the CLK pin to sample the analog input The falling edge of CLK is ignored and the internal falling edge is generated by a phase locked loop The input clock duty cycle can vary from 40 to 60 and the clock duty cycle stabilizer will maintain a constant 50 internal duty cycle If the clock is turned off for a long period of time the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto
19. ADC V5_CLKOUTO V6 g V5_CLKOUT 0 V7 V5_CLKOUT 1 J5 4 7 V5_CLKOUT 1 J6 Table 11 2 FPGA Clock Outputs The TAMC900 provide two feedback clocks MUX0_FB and MUX1 FB that return the ADC clocks back to the FPGA The following table provides the pin assignment of the feedback clock inputs Signal Name Virtex 5 Pin from ADC MUX0_FB E13 625 MUXO_FB E12 MUX1_FB E18 MUX1_FB F19 Table 11 3 ADC Feedback Clocks TAMC900 User Manual Issue 2 0 1 Page 49 of 71 12 LVDS Link The TAMC900 provides a differential interface from the FPGA to the SICA connector 10 differential pairs out of one FPGA I O bank are routed to the SiCA connector For the Virtex 5 and SiCA connector pin assignment see table below The use of these lines is free to the customer The FPGA programming provided by TEWS does not use these lines Care must be taken to avoid damaging the FPGA Signal Name Virtex 5 Pin SICA Pin LVDS 0 K6 18 LVDS 0 K7 20 1 K8 24 LVDS_1 L7 26 LVDS_2 M7 30 LVDS_2 L8 32 LVDS_3 R6 36 LVDS_3 T7 38 LVDS 4 P6 44 LVDS 4 N6 46 LVDS 5 M6 50 LVDS 5 N7 52 LVDS 6 N8 56 LVDS_6 P8 58 LVDS 7 R8 62 LVDS 7 R7 64 LVDS 8 Y6 68 LVDS 8 Y5 70 LVDS 9 G6 74 LVDS 9 H6 76 Table 12 1 LVDS Link Pin Assignment The maximum input voltage of the Virtex 5 I Os is 2 5 Volt The TAMC900 will
20. Consequently one channel can still be active while the others the group have already finished N Since the channels are handled concurrently the length of the channel DMA windows is Q 4 8 Restrictions 4 8 1 Processing Limit The PCI Express adaptation is currently limited to 1 GByte sec Due to header overhead a fraction of approximately 88 89 888 MByte sec can be continuously transmitted via the module Exceeding this limitation causes the DMA processing to stop after the internal buffer structure has collapsed For all channels at least 256 k samples can be obtained independently of the transmission rate caused by the integration of the QDR II memory in the transmission path refer chapter Tracking Buffer The amount of data can be composed over all channels TAMC900 User Manual Issue 2 0 1 Page 23 of 71 5 Address Map 5 1 PCI Express Configuration The TAMC900 module will be present in the PCI Device Tree with the subsequent information PCI Information Hex Value Description Vendor 0x1498 TEWS TECHNOLOGIES GmbH Device ID 0x8384 TAMC900 Class Code 0x118000 Signal Processing Controller Table 5 1 TAMC900 PCI Device Information The information about the local on board addressable data regions are summarized in the subsequent table Local PCI Base Address PCI Size Port Endian Description Space Offset in PCI Space Byte Width Mode Configuration Mapping Bit Space
21. DMA processing select the base Descriptors as defined through the register map e interrupts are de asserted e CPLD has been reset 4 6 2 Pre Initialization Setup Check Before any operation on the TAMC900 can be performed it has to be checked that e the GSTAT bit inside the Module Status and DCM 0 1 Status register indicates that the module is operational e all unused channels are disabled TAMC900 User Manual Issue 2 0 1 Page 20 of 71 4 6 3 Channel Setup The recommend steps to setup a channel respectively a channel group is described afterwards e Disable all channels in the Channel Group before manipulation e Configure ADCs sample rate o DCM first if necessary to have the correct clock at the ADCs input o Sample Clock Configuration afterwards e Define corresponding Channel Group Trigger Mode o Pre Trigger Data Size if necessary e Provide DMA descriptors and assign a base address to the corresponding channel register e Set Channel Configuration register e Enable the channel in Global Channel Configuration register this will start processing 4 7 Channel Logic 4 7 1 Channel Reset Beside the general reset that has an effect on the complete module every channel can be reset separately Such a reset causes that achannel trigger event if one has occurred is reset e channel DMA information e g remaining window size are obsolete e the DMA base descriptor as defined through the register map is loaded e the
22. FIFO is used for collecting the channel specific data samples besides the QDR II FIFO The buffer is storage for the PCI Express TLPs used during burst writes and in case of a packet retry The TLPs have a static defined packet size see below Due to flexibility considerations a concept of DMA descriptors has been implemented These descriptors built a Linked List LL which allows defining regions windows in host memory for placing channel ADC data Moreover the LL contains additional processing information respectively settings see chapter DMA Descriptors After channel activation or channel reset a DMA Engine uses its DMA base descriptor This is set in the channel specific DMA Base Descriptor Address register If a channel is enabled writing into the channels DMA Base Descriptor register will initiate the reload of the descriptor Starting at the obtained base address data packets are transmitted consecutively The DMA memory is filled in blocks Ifthe defined length sample count of a window has been achieved the subsequent descriptor will be loaded Hence it will be switched to the next list element respectively memory address range The data acquisition and its transmission are performed until the last descriptor of the chain has been processed To reduce PCI Express traffic interrupts will only be generated if additional steering flags demand this After the last descriptor has been processed its successor list
23. SIGNAL CONDITIONING ADAPTER 222222 10 FIGURE 4 1 TAMC900 FPGA SYSTEM STRUCTURE aiiiaaitaaaaaaaaaasaasaasnansnanaasannnannannnnnnannnanansnannansnanana 14 FIGURE 9 1 SHIELDING COVER DIMENSIONS aaiiaiiaaiaaaaaaasaassaanasananaasnannanananansnnnnannaannnnnanananansnannnnsnanana 46 FIGURE 10 1 QDR ISRAM INTERFACE mitron 3 7 47 FIGURE 11 1 CLOCK DISTRIBUTION 6 2222 48 FIGURE 13 1 TIMING OF FPGA CPLD INTERFACE iiiiaaiiaaaaaaaaaaaaasaaasaasaasnasaasnannanananaannnnnannnanansnannannaannana 51 FIGURE 14 1 TAMC900 CONNECTOR AND STANDOFF POSITIONS iiaiiaaiaaiaiiaaiassaasansaasaasananansnannanaannana 60 FIGURE 14 2 MAXIMUM COMPONENT HEIGHT FOR THE SICA iiiiiaaaaaaaaaaasaasaasvasaassaasasasasaassaananananana 61 FIGURE 15 1 TEMPERATURE SENSOR LOCATIONS uursuunssnnsnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnennnen nennen nn 63 FIGURE 16 1 ON BOARD INDICATORS aiiiaaiaiaaaaaaaasassaasaasananasananaasaasnanaannnnnanananansnnnnaunaannnnanannanannnnnnanannnana 65 FIGURE 17 1 CONNECTOR OVERVIEW u nnnnnnessnerssnnnennnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnennnnnnnnnnnnnnnnn en 66 FIGURE 17 2 VO CONNECTOR PIN POSITIONS aiaiaaiaaiaaaaaaaasaasaasnasnasnnana
24. TAMC900 DOG schematics and data sheets of TAMC900 FD Q OS D Q 3 gt 2 3 Q gt a D 5 S g 4 x ADC 14 Bit 105 MHz 8x z Diff E 5 1 Analog ao Input T A lt x8 PCle o 5 2 or User def Jon nari 3 z Clock har link T 1x Clock gt 3x har link 3 gt Clock Trigger 7 Config Se 0020 Trigger Flash H EN Figure 1 1 Block Diagram TAMC900 with Signal Conditioning Adapter TAMC900 User Manual Issue 2 0 1 Page 10 of 71 2 Technical Specification AMC Interface Mechanical Interface Advanced Mezzanine Card AMC confirming to PICMG AMC 0 R2 0 Single Mid Size Module Electrical Interface Virtex 5 FPGA connected to AMC Port 4 11 PICMG AMC 1 R1 0 Type 4 x4 PCI Express or other interfaces defined by customer IPMI IPMI Version 1 5 Front Panel LEDs Blue Hot Swap LED Red Fail LED LED1 Green User LED LED2 On Board Devices Target Chip Xilinx Virtex 5 with integrated PCI Express Endpoint Block and two integrated Gigabit Ethernet MACs RAM 2 x 2 MByte QDR II SRAM ADC 8 x LTC2254 105 MSps 14 bit 1 O Interface Number of Analog Channels
25. descriptor e g the DMA window length will not be detected In such a case the base address must be assigned again or the channels need to be re enabled Manipulating the content of a DMA Base Descriptor Addresses register while the accompany DMA Engine is active is not allowed Moreover changing a Descriptor in memory during its processing is also not allowed TAMC900 User Manual Issue 2 0 1 Page 22 of 71 4 7 4 Channel Start Stop There are some constraints on the configurability of a channel in context of its channel group initially mentioned in this chapter Additionally the channel start conditions for data processing are summarized afterwards The DMA operation can be performed if e DMA operation is enabled e avalid DMA descriptor is defined and loaded the associated QDR II memory is ready for use e the Channel Group Trigger is configured e the channel itself channel configuration is enabled e the channel s global control bits are set If one condition is not met the corresponding channel cannot be used Besides these conditions it has to be considered that the QDR II memories have been filled with valid data as far as required for Pre Trigger Data Gathering if used An active channel is stopped automatically if its associated Linked List has been processed Stopping the processing while it is running if necessary should be done via the DMA Enable Bit see chapter Channel Activation defined separately
26. the input clock For applications where the sample rate needs to be changed quickly the clock duty cycle stabilizer can be disabled If the duty cycle stabilizer is disabled care should be taken to make the sampling clock have a 50 5 duty cycle TAMC900 User Manual Issue 2 0 1 Page 45 of 71 9 3 Shielding The TAMC900 allows adding a cover to shield its ADCs See picture below for cover mounting area dimensions The cover must ensure a minimum free height of 3 mm and sufficient cooling ofthe ADCs 37 50 mm m 34 30 mm 29 90 mm l 26 80 mm 4 3 90 ig R 10 90 mm i T H I I I U 13 10 mm I HAD Am 20 30 mm 23 50 mm 1 40mm 1 7 _ 1830mm 21 50 mm 24 70 mm 1 40 mm Jr 1 H D 1 D 55 30 mm E 52 50 mm 28 60 mm n I 27 40 mm t mm 31 70 mm o 24 30 bid 26 00 mm 20 60 mm 15 00 mm 22 20 mm 1 40 mm 13 80 mm 47 00 mm N 11 80 mm 1 1 1 I I 1 18 50mm 22 80 mm TAMC900 User Manual Issue 2 0 1 rm 28 50 mm m 32 80 mm H 00 mm 8 40 mm Figure 9 1 Shielding cover dimensions Page 46 of 71 10 Memory The TAMC900 provides 4 MByte QDR II SRAM 2 RAM devices with 18 bit wide data bus each are used to implement the 4 MByte RAM of the TAMC900 The two RAMs have fully independent interfaces to the FPGA
27. the link list Due to the initially mentioned restriction the channels of a group are started together and a channel of the group can be restarted first if all other channels of the group are in idle The Post Trigger Data Gathering is the standard case The ADC data obtained after a trigger impulse is used for data transmission Since the mode does not make use of previous data samples there are no restrictions concerning the number of transmitted samples The content of register Channel Pre Trigger Data Size must be zero see below The Pre Trigger Data Gathering is the opposite case If a trigger event has been detected the data that has been monitored before its occurrence will be transmitted For this the content of the QDR II memory is used Consequently the number of samples cannot exceed the QDR II memory depth The value of register Channel Pre Trigger Data Size defines the transmission size Moreover the linked list must match the requested sample count see below The Around Trigger Data Gathering is a mixture of the previous two modes It is used to obtain the data before and after the trigger event Thus it makes also use of the QDR II memory Hence it is subdued the size limitation as the Pre Trigger The implementation is done in accordance to the above two methods The value of register Channel Pre Trigger Data Size defines the demanded tracked samples as starting point Afterwards transmission is performed
28. voltages of the TAMC900 I Os The TAMC900 will be damaged if higher voltage levels are applied 3 1 ESD Protection The TAMC900 is sensitive to static electricity Packing unpacking and all other handling of the TAMC900 has to be done in an ESD EOS protected area 3 2 Thermal Considerations The TAMC900 requires forced air cooling during operation Without forced air cooling damage to the device will occur TAMC900 User Manual Issue 2 0 1 Page 12 of 71 3 3 AMC Module Insertion amp Hot Swap 3 3 1 Insertion Handle Blue LED Description Open Full extracted OFF Insert Module into slot Open Full extracted ON Module is ready to attempt activation Closed Pushed all way in Long Blink Hot Swap Negotiation Closed Pushed all way in OFF Module is ready amp powered Table 3 1 AMC Module Insertion When the blue LED does not go off but returns to the ON state the module FRU information is invalid or the carrier cannot provide the necessary power 3 3 2 Extraction Handle Blue LED Description Pulled out 1 2 OFF Request Hot Swap Pulled out 1 2 Short Blink Hot Swap Negotiation Pulled out 1 2 ON Module is ready to be extracted Open Full extracted ON Extract Module from slot Table 3 2 AMC Module Extraction TAMC900 User Manual Issue 2 0 1 Page 13 of 71 Functional Procedures The following diagram illustrates the structure of the ADC data acq
29. 0 Interrupt IRQCH1 Channel 1 Interrupt IRQCH2 Channel 2 Interrupt IRQCH3 Channel 3 Interrupt r P nfiguration IRQCH4 Channel 4 Interrupt Register en IRQCH5 Channel 5 Interrupt IRQCH6 Channel 6 Interrupt IRQCH7 Channel 7 Interrupt Table 7 2 Interrupt Handling For all interrupts should be noted that every DMA channel is treated as one source This causes that an interrupt that occurs while a pending interrupt is present will not generate a new interrupt signal Consequently interrupts have to be acknowledged after their occurrence The use of Message Signaled Interrupts may introduce spurious interrupts as described in the PCI Specification TAMC900 User Manual Issue 2 0 1 Page 40 of 71 8 FPGA The TAMC900 provides a Virtex 5 FPGA in FFG665 for customer programming and board control Information about the FPGA pin assignment is part of the engineering documentation 8 1 Configuration The FPGA is configured from a Xilinx Platform Flash The flash has the potential to store different FPGA code revisions The Module Management Controller MMC can be programmed to select the code revision that is loaded into the FPGA By default Code Revision 0 is loaded into the FPGA On the TAMC900 the Xilinx Platform Flash is configured to store multiple code revisions The FPGA is configuration Master and loads Revision 0 by default Pay attention to this while generating PROM fil
30. 00D4 Channel DMA Buffer Fill Level 3 R 32 0x00D8 Channel DMA Buffer Fill Level 4 R 32 0x00DC Channel DMA Buffer Fill Level 5 R 32 0Ox00EO Channel DMA Buffer Fill Level 6 R 32 0x00E4 Channel DMA Buffer Fill Level 7 R 32 0x00E8 Revision Control Register R 32 Table 5 4 Register Map 5 3 DMA Descriptor Space Offset to PCI Register Name Access Size Base Address 1 Bit 0x0 Ox1FFF Channel DMA Descriptor Memory R W 32 Table 5 5 DMA Descriptor Space TAMC900 User Manual Issue 2 0 1 Page 27 of 71 6 Register Description 6 1 Module Status and DCM 0 1 Status Register There are several components integrated in the module that need to be configured after power on respectively reset This register summarizes accompany information and has to be checked before the module can be used Bit Symbol Description Access Reset Value 31 17 Reserved R 0 16 STAT3 Core PLL Locked The Core PLL generates the clocks for R 0 the DCMs and the QDR II Memory Controllers 1 PLL is locked 0 PLL is not locked 15 13 Reserved R 12 STAT2 This bit indicates if the DCM 1 has been locked and R operates correctly 1 DCM 1 locked 0 DCM 1 not locked 11 9 Reserved R 8 STAT1 This bit indicates if the DCM 0 has been locked and operates correctly 1 DCM 0 locked 0 DCM 0 not locked 7 5 Reserved R 0 4 STATO QDR II Memory Controllers Ready Flag R 0 3 1 Reserved R 0 0 GST
31. 13 6 SICA OUTPUT REGISTER 2 ADDRESS OXOB aaiiiiiaiaaaaaaaasaasaasaasnansaannasansnnnnannnanansnannnnaannana 54 TAMC900 User Manual Issue 2 0 1 Page 7 of 71 TABLE 13 7 SICA OUTPUT ENABLE REGISTER 1 ADDRESS 0XO0C aaaiaaiaaiaaaaaiassaasansaannasaasnansnannannannana 55 TABLE 13 8 SICA OUTPUT ENABLE REGISTER 2 ADDRESS 0XOD aaiaaiaaaaaaaaaassaasansaasaasananansnannannaannana 55 TABLE 13 9 CROSSPOINT SWITCH CONTROL REGISTER ADDRESS 0X10 ennnen 56 TABLE 13 10 CLOCK MUX CONTROL REGISTER ADDRESS OX 11 aaiaaaaaaaaaaasaaaaasaaanansnannnnnnannnsnannnnnnnnana 57 TABLE 13 11 JITTER ATTENUATOR CONTROL REGISTER ADDRESS 0X12 unnesseernessennsener nenn 58 TABLE 13 12 GENERAL BOARD CONTROL REGISTER ADDRESS 0X18 eneee 59 TABLE 14 1 VO MATING CONNECTORS 1117 7 toe ott 61 777 1 1 62 TABLE 17 1 PIN ASSIGNMENT I O CONNECTOR uersuersnnersnnnsnnnsnnnsnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnenn ern 68 TABLE 17 2 PIN ASSIGNMENT MMC JTAG CONNECTOR FACTORY USE ONLY seen nenn 69 TABLE 17 3 PIN ASSIGNMENT PAYLOAD JTAG CONNECTOR uuuzunnsnnnsnnnnnnnnnnnnnnnennnnnnnnnnnnennnen nenn 69 TABLE 17 4 PIN ASSIGNMENT AMC CONNECTOR aaiaaitaaaaiaaaaaiaaaaasaasaasnanaannansaasnanaannnnnannnanansnannnsnannananana 71 TAMC900 User Manual Issue 2 0 1 Page 8 of 71 List of Figures FIGURE 1 1 BLOCK DIAGRAM TAMC900 WITH
32. 2 0 1 Page 41 of 71 8 3 AMC Interface The Multi Gigabit Transceivers MTGs of the FPGA are connected to Port 4 11 of the AMC Interface Signal Name Virtex 5 Pin AMC Conn Pin TAMC900 10 TX0 B2 44 TX0 C2 45 RX0 C1 47 RXO D1 48 TX1 G2 50 TX1 F2 51 RX1 F1 53 RX1 E1 54 TX2 H2 59 TX2 J2 60 RX2 J1 62 RX2 K1 63 TX3 N2 65 TX3 M2 66 RX3 M1 68 RX3 L1 69 TX4 P2 91 TX4 R2 90 RX4 R1 88 RX4 T1 87 TX5 W2 97 TX5 V2 96 RX5 V1 94 RX5 U1 93 TX6 Y2 103 TX6 AA2 102 RX6 AA1 100 RX6 AB1 99 TX7 AE2 109 TX7 AD2 108 RX7 AD1 106 RX7 AC 1 105 Table 8 2 AMC Fabric Interface connections to the FPGA TAMC900 User Manual Issue 2 0 1 Page 42 of 71 FCLKA of the AMC Interface is multiplied by the factor of 2 5 and then connected to a MGT Clock Input Signal Name Virtex 5 Pin AMC Conn Pin AMC_REFCLK T3 80 AMC_REFCLK V1 81 Table 8 3 AMC FCLKA connection to the FPGA It is free to the customer what kind of interfaces to implement using the FPGA logic recourses If any other interfaces than PCI Express are implemented it is necessary to adapt the Connectivity Records of the MMC Otherwise proper operation of the TAMC900 is not possible 8 4 RAM Interface The RAM interface to access the QDR II SRAM of the TAMC900 has to be implemented in the FPGA TEW
33. A6 R W 0 5 EN_SICAS Sets the corresponding SICA general purpose pins as RW 0 4 EN_SiCA4 input or output R W 0 3 EN SICA3 0 CPLD input R W 0 2 EN Sigag U CPLD output R W 0 1 EN_SiCA1 R W 0 0 EN_SiCAO R W 0 Table 13 8 SiCA Output Enable Register 2 Address 0 00 TAMC900 User Manual Issue 2 0 1 Page 55 of 71 13 2 8 Crosspoint Switch Control Register Address 0x10 Bit Symbol Description Access Reset Value 7 OUT3_ Clock Select for ADC 4 to 7 R W 0 SEL 1 00 Clock input 0 SW_CLKO 100MHz PCIe Ref Clock 01 Clock input 1 EXT_CLK2 10 Clock input 2 EXT CLK1 11 Clock input 3 EXT_CLKO 6 OUT3_ R W 0 SELO 5 OUT2_ Clock Select for ADC 0 to 3 R W 0 SEL1 00 Clock input 0 SW_CLKO 100MHz PCle Ref Clock 01 Clock input 1 EXT_CLK2 10 Clock input 2 EXT_CLK1 11 Clock input 3 EXT_CLKO 4 OUT2_ RW 0 SELO 3 OUT1 Clock Select for FRGA_CLK_IN1 R W 0 SEL1 00 Clock input 0 SW CLKO 100MHz PCIe Ref Clock 01 Clock input 1 EXT CLK2 10 Clock input 2 EXT CLK1 11 Clock input 3 EXT CLKO 2 11 RW 0 SELO 1 OUTO Clock Select for FPGA CLK INO R W 0 SEL1 00 Clock input 0 SW_CLKO 100MHz PCle Ref Clock 01 Clock input 1 EXT_CLK2 10 Clock input 2 EXT_CLK1 11 Clock input 3 EXT_CLKO 0 OUTO_ RW 0 SELO Table 13 9 Crosspoint Switch Control Register Ad
34. AT Whether the module is in working order is shown by this bit R 0 1 Module is operating 0 Module is not operating Table 6 1 Module Status Register Address 0x0 The module should not be used for DMA transmissions if the GSTAT bit is not asserted TAMC900 User Manual Issue 2 0 1 Page 28 of 71 6 2 DCM Multiply Divide 0 1 It is possible to define sample rates for the on board ADCs that are generated by the FPGA For this the module provides two configurable digital clock managers DCMs The sample frequency is adjusted in the way of defining a multiply and division value The resulting fraction is applied on a source clock which has a frequency of 50 MHz The values for multiplication and division are grouped into a single data word This is due to the physical interface of a Virtex 5 DCM Bit Symbol Description Access Reset Value 15 8 MULT The selected multiplier is the assigned value plus one Valid R W 24 range is 1 up to 31 7 0 DIV The selected divider is the assigned value plus one R W 24 Valid range is 0 up to 31 Table 6 2 DCM Multiply Divide Register Address 0x4 0x4 DCM Number The legal value range reflect the Virtex 5 DCM specification Do not use values other than the allowed ones The minimum frequency that can be set is 32 MHz The reset value adjusts a sample frequency of 50 MHz TAMC900 User Manual Issue 2 0 1 Page 29 of 71 6 3 Gl
35. CA12 SiCA on the corresponding SiCA general purpose pins R W 0 3 O SICA11 if the pin is defined as output in the corresponding SICA R W 0 2 O SICA10 Output Enable Register RW 0 1 0 SICA9 R W 0 0 O_SICA8 R W 0 Table 13 5 SICA Output Register 1 Address 0x0A 13 2 5 SICA Output Register 2 Address 0x0B Bit Symbol Description Access Reset Value 7 O_SiCA7 R W 0 6 O_SiCA6 R W 0 2 PE The value written to this register is displayed to the RW 4 0 SICA4 SiCA on the corresponding SiCA general purpose pins R W 0 3 O_SICA3 if the pin is defined as output in the corresponding SICA R W 0 2 O SiCA2 Output Enable Register RW m 1 O_SICA1 R W 0 0 O_SICAO R W 0 Table 13 6 SICA Output Register 2 Address 0x0B TAMC900 User Manual Issue 2 0 1 Page 54 of 71 13 2 6 SiCA Output Enable Register 1 Address 0x0C Bit Symbol Description Access Reset Value 7 EN SICA15 R W 0 6 EN SICA14 R W 0 5 EN_SICA13 Sets the corresponding SiCA general purpose pins as R W 0 4 EN_SiCA12 input or output R W 0 3 EN SICA11 0 CPLD input R W 0 2 EN SiCA10 CPLD output R W 0 1 EN_SICA9 R W 0 0 EN_SiCA8 R W 0 Table 13 7 SiCA Output Enable Register 1 Address 0x0C 13 2 7 SiCA Output Enable Register 2 Address 0x0D Bit Symbol Description Access Reset Value 7 EN_SiCA7 R W 0 6 EN_SiC
36. DC 0 Control Register R W 0x02 0x01 ADC 1 Control Register R W 0x02 0x02 ADC 2 Control Register R W 0x02 0x03 ADC 3 Control Register R W 0x02 0x04 ADC 4 Control Register R W 0x02 0x05 ADC 5 Control Register R W 0x02 0x06 ADC 6 Control Register R W 0x02 0x07 ADC 7 Control Register R W 0x02 0x08 SICA Input Register 1 R depends on SICA 0x09 SICA Input Register 2 R depends on SICA 0x0A SiCA Output Register 1 R W 0x00 0x0B SICA Output Register 2 R W 0x00 0x0C SiCA Output Enable Register 1 R W 0x00 0x0D SiCA Output Enable Register 2 R W 0x00 OxOE OxOF reserved R 0x00 0x10 Crosspoint Switch Control Register R W 0x00 0x11 Clock Mux Control Register R W 0x00 0x12 Jitter Attenuator Control Register R W 0x10 0x13 0x17 reserved R 0x00 0x18 General board Control Register R W 0x00 0x19 0x1 E reserved R 0x00 0x1F Revision Control Register R Code Revision of the CPLD Table 13 1 CPLD Register Overview TAMC900 User Manual Issue 2 0 1 Page 52 of 71 13 2 1 ADC x Control Register Address 0x00 to 0x07 Bit Symbol Description Access Reset Value 7 reserved for future use R 0 6 reserved for future use R 0 5 OF Output Format R W 0 0 offset binary output format 1 2 s complement output format 4 CDCS Clock Duty Cycle Stabilizer R W 0 0 OFF 1 ON 3 reserved for future use R 0 2 reserved for fu
37. DDRESS 0X4 0X4 DCM NUMBER 29 TABLE 6 3 GLOBAL CHANNEL CONFIGURATION REGISTER ADDRESS 0XC uu eerie 30 TABLE 6 4 GLOBAL RESET AND SOFTWARE TRIGGER INPUT REGISTER ADDRESS 0X10 31 TABLE 6 5 SAMPLE CLOCK CONFIGURATION REGISTER aiiaiiaaiaaaaaaaaaaasaasaasaansasaassanaanananansnanaanaannana 32 TABLE 6 6 TRIGGER CONFIGURATION REGISTER ADDRESS 0X1C 0X4 CHANNEL GROUP 33 TABLE 6 7 CHANNEL CONFIGURATION REGISTER ADDRESS 0X24 O0X4 CHANNEL 34 TABLE 6 8 CHANNEL DMA BASE DESCRIPTOR ADDRESS REGISTER eee erent 35 TABLE 6 9 CHANNEL PRE TRIGGER DATA REGISTER ADDRESS 0X64 OX4 CHANNEL 35 TABLE 6 10 CHANNEL DATA REGISTER ADDRESS 0X84 0X4 CHANNEL iiaiiaiiaaaaaaasaassasaassaanananana 36 TABLE 6 11 GLOBAL DMA STATUS REGISTER ADDRESS O0XA4 iiiiiaiaaiaaaasaaaiasaaanansnannasananansnannannaannana 37 TABLE 6 12 CHANNEL DMA STATUS REGISTER ADDRESS 0XA8 OX4 CHANNEL 22 38 TABLE 6 13 CHANNEL DMA BUFFER FILL LEVEL REGISTER ADDRESS OXC8 0X4 CHANNEL 39 TABLE 6 14 REVISION CONTROL REGISTER ADDRESS 0XEB8 aiiaiiaaiaaaaaaasaaaaassaasassaanaanananansnannanaannana 39 TABLE 721 2 INTERRUPT SOURGCES 7 97 1 909 40 TABLE 7 2 INTERRUPT HANDLING eee eee ee eee eee 9 40 TABLE 8 1 FPGA SIGNALS CONNECTED TO THE MMC aaiaaiaaiaaaaaaaaaaasaasnasaasnanna
38. ENT CONTROLLER MMC 222aaaaaaan n nnnnnnnnnnnnnnnnnnnnnnnnnnnn 62 15 1 1HAICATOFS aust 62 15 11 lt Fr nt Panel LEEDS Lukas se 62 15 2 Temperature and Voltage 63 15 3 CONNECT A e eaer a aa e e aaa a e a ae a aaa Ea ae aae aaa raae iaeei aaa 63 15 4 Interfaces 10 Payload 2 un He ee en cites emne denen anne one anna aeg ann nenn 64 TAMC900 User Manual Issue 2 0 1 Page 5 of 71 16 ON BOARD INDICATORS nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 65 0 7 8 8 65 16 2 Power Good LEDs 233 a ar 65 17 PIN ASSIGNMENT 1 1 59 090 66 17 1 OVerview 02 09 6
39. L 3 7 9 4 MP out 3 3V Pin Signal Level Logic Ground 6 RST 3 3V CMOS TTL 10 GND Logic Ground Table 17 2 Pin Assignment MMC JTAG Connector Factory use only 17 4 Payload JTAG Connector Pin Signal Level 7 5 Logic Ground Level mo 3 3V CMOS TTL 1 6 3 3V CMOS TTL TDO 3 3 CMOS TTL TDI 33V CMOS TTL Do Not Connect Table 17 3 Pin Assignment Payload JTAG Connector 17 5 AMC Connector Signals written in talic are not connected on the TAMC900 Pin Signal Function 65 z 83 s2 GND toge Ground 81 FCLKA CT Signaling 80 FCLKA 79 o Logic Ground 78 TCLKB Differential Signaling 77 TCLKB 76 Fu Logic Ground 75 TCLKA Differential Signaling TAMC900 User Manual Issue 2 0 1 Pin Signal Function Logic Ground Differential Signal tial Signaling 89 GND Logic Ground 90 Tx8 Differential Signaling Logic Ground tial Signaling Jen Logic Ground Differential Signaling Page 69 of 71 7 7 7 7 7 6 6 6 6 6 6 6 6 61 60 59 58 57 56 55 54 53 52 5 50 49 48 47 46 45 44 43 42 4 40 39 38 37 36 n NIOQOIRIGO DIN 0D 0 0 INIOTR Signal Function roa PWR 1124 Payload Power G ND i PWR ND i Differential Signaling Differential Signaling ND i ND ND WR G Differential Sign
40. Output Enable Register 1 Address 0x0C aaiaaaaaaaiaasaassaassaassaaasaaassaansaanaaansaanaaannaanaa 55 13 2 7 SiCA Output Enable Register 2 Address 0x0D aaaaaaaaiaasaassaassaassaansaaassaansaanaaannaanaaanaaanaa 55 13 2 8 Crosspoint Switch Control Register Address 0x10 aaaaaaaaaasaaasaaasaaasaaassaansaansaanaaanaaanna 56 13 2 9 Clock Mux Control Register Address Ox11 aaaaaaaiaaaaasaaassaassaassaansaaanaaanaaansaanaaanaaanaaanaaanaa 57 13 2 10 Jitter Attenuator Control Register Address 0x12 aaaaaaaiaaaaaasaassaassaaasaansaannsaansaannaanaaanaaanaa 58 13 2 11 General Board Control Register Address 0x18 iiaaaniaaaaaaaaaasaasaasaanaanaanaannannannannannannanaana 59 14 SIGNAL CONDITIONING ADAPTER SICA nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 60 14 1 Connector and Standoff 50 1 60 14 2 Mating CONNC COM vices cise cecescceeccessecessacccessceceeatezssecstseceed sees su soncencucdsenads sate eszucscoutdeceaeddesecdeensecttecszece 61 14 3 Board and Component Height rnernnnvnnnnnvnnnnnvrnnnvrnnnnvnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnner 61 15 MODULE MANAGEM
41. R 2 MR Reset R W 0 normal operation 1 reset device and disable outputs 1 OEB Output disable for the QBO clock R W 0 0 enable 1 disable 0 OEA Output disable for the QAO and QA1 clocks R W 0 0 enable 1 disable Table 13 11 Jitter Attenuator Control Register Address 0x12 Do not change the frequency of QA0 QA1 TAMC900 User Manual Issue 2 0 1 Page 58 of 71 13 2 11 General Board Control Register Address 0x18 Bit Symbol Description Access Reset Value reserved for future use R 0 6 reserved for future use R 0 RAMDLL1 Disable DLL of RAM 1 R W 0 0 enable 1 disable 4 RAMDLLO Disable DLL of RAM 0 R W 0 0 enable 1 disable 3 reserved for future use R 0 2 reserved for future use R 0 1 reserved for future use R 0 0 LOC_CLK Disable local 250 MHz clock R W 0 0 enable 1 disable Table 13 12 General Board Control Register Address 0x18 TAMC900 User Manual Issue 2 0 1 Page 59 of 71 14 Signal Conditioning Adapter SiCA The SICA holds the connector for the analog inputs the connectors for the clock and trigger inputs and the analog signal conditioning for the TAMC900 Depending on customer needs the form and function of the SICA can vary For more information please refer to the corresponding SiCA User Manual The SiCA is powered from the TAMC900 with 6 Volts from a switched power supply Any other voltages needed must be g
42. S recommends using the Xilinx Memory Interface Generator MIG to build the RAM interface logic Please refer to the QDR II SRAM Data Sheet and the Xilinx documentation for more details 8 5 ADC Interface The ADC data lines and the corresponding sample clocks are routed to the FPGA For accurate and precise sampling of the ADC data TEWS recommends using the ILOGIC FlipFlops of the FPGA Please refer to the sample application for more details Configuration of the ADCs is done via the on board CPLD The on board CPLD is accessible via the FPGA Please refer to the chapter On Board CPLD for more details TAMC900 User Manual Issue 2 0 1 Page 43 of 71 ADCs The TAMC900 provides eight high speed ADCs LTC2254 from Linear Technologies The LTC2254 provides 14 bit resolution Configuration of the ADC Output Enable Shutdown Output Format is done by the on board CPLD It can be controlled via the FPGA The LTC2254 differential inputs are routed to the Signal Conditioning Adapter SICA connector For the pin assignment please refer to chapter I O Connector Any signal conditioning of the analog inputs is not done on the TAMC900 This is done by the SiCA The SICA also carries the I O connectors accessible through the face plate 9 1 AC DC Characteristics 9 1 1 Min Max Sample Rate The minimum sample rate of the LTC2254 is 1 Msps The maximum sample rate is 105 Msps 9 1 2 Input Voltage Range The different
43. T Source amp Order Info QTE 060 02 L D A 8 mm stacking height Pin Count 120 pins Connector Type Q Strip High Speed SMT Source amp Order Info QTE 060 03 L D A 11 mm stacking height Table 14 1 I O mating connectors 14 3 Board and Component Height The height of the SiCA above the AMC depends on the mated stacking height of the connector used When selecting a stacking height care must be taken to ensure enough space for the I O connectors of the SICA Take care not to violate the maximum component height according to AMC 0 The maximum component height on the SiCA depends on the component height of the AMC below the SiCA and the stacking height See figure below for more details Shaded areas are no placement areas 172 70 mm F 169 30 mm i 165 00 mm 128 00 mm m 33 80 mm P 27 10 mm N IN Z Z 7 FA z Z g 3 E E VW 5 3 lt 1450mm 2 E J ST 71 80 mm amp al 64 72 mm Se 68 01 mm 66 06 mm 2 2 a iwi a a VW 7 82 mm 4 86 mm Fu 1 70 mm j H 1 N Nh Z Z A Z Z ZZ bc 23 85 mm l 169 80 mm 172 70 mm 1 EU M 1 Figure 14 2 Maximum Component height for the SICA TAMC900 User Manual Issue 2 0 1 Page 61 of 71 15 Module Management Controller
44. TEWSS The Embedded I O Company TECHNOLOGIES TAMC900 AMC with 8 high Speed ADCs 105MSps 14Bit Version 2 0 User Manual Issue 2 0 1 April 2010 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TAMC900 10R AMC with 8 high speed ADCs 105 MSps 14 bit RoHS compliant Requires Signal Conditioning Adapter TAMC900 User Manual Issue 2 0 1 TEWSS TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 2008 2010 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 71
45. alin vk Differential Signaling Logic Ground Differential Signaling Differential Signaling Logic Ground P ND Differential Signaling 12V Payload Power ENABLE AMC Enable Input Differential Signaling Tx3 Differential Signaling TAMC900 User Manual Issue 2 0 1 Pin Signal Function Logic Ground Rao Differential Signaling Rx10 Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling Differential Signaling 135 TCLKC Differential Signaling Page 70 of 71 Pin Function Logic Ground Differential Signaling Logic Ground Differential Signaling Differential Signaling Logic Ground Differential Signaling Differential Signaling Logic Ground Differential Signaling Logic Ground 12V Payload Power Logic Ground Geogr Address Input PS1 Present detect PWR 12V Payload Power GND Logic Ground Signal RSRVD8 RSRVD6 Pin Signal Function TCLKC Logic Ground TCLKD TCLKD Differential Signaling TCLKD Logic Ground 141 Rx17 Differential Signaling 144 Tx17 144 PI Differential Signaling 147 Rx18 147 Axia Differential Signaling 150 Tx18 150 Tx18 Differential Signaling 153 Rx19 153 R19 Differential Signaling 156 Tx19 156 Tx19
46. annel DMA Status 0 7 rrnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnn 38 6 13 Channel DMA Buffer Fill Level 0 7 rsarnnnnvrnnnvnnnnnvnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 39 6 14 Revision Control 39 TAMC900 User Manual Issue 2 0 1 Page 4 of 71 7 INTERBUPTS sagde 40 FAV IBTEFrUpT SOUFCES 12320222 40 7 2 Interrupt Handling 2 2 tai 40 8 3 1 41 8 1 COMPUTATION 2221
47. annnanannnannnsnnnnannnnnnnnnannnanansnannnnananani 66 TAMC900 User Manual Issue 2 0 1 Page 9 of 71 Product Description The TAMC900 is a high speed high performance analog to digital converter AdvancedMC In addition to the eight high speed ADCs it provides excessive preprocessing power by a Virtex 5 FPGA and high speed on board memory for e g full bandwidth snapshots The up to x8 PCle link of the TAMC900 is used to transmit the ADC data to the CPU To adapt the TAMC900 to different customer requirements the TAMC900 is equipped with a Signal Conditioning Adapter SiCA which holds the connector for the analog inputs the connectors for the clock and trigger inputs and the analog signal conditioning The TAMC900 provides three clock inputs and three trigger inputs The three external clock inputs and the PCle reference clock are routed to a flexible clocking scheme that allows independent clocking of the ADCs in two groups The trigger inputs are routed to the FPGA Eight LTC2254 ADCs provide up to 105 MSps and 14 bit resolution each The minimum sample rate is 1 Msps 4 MByte high speed on board SRAM enables snapshots of all ADCs at full speed and full resolution for 2ms According to AMC 0 the TAMC900 provides an IPMI compliant Module Management Controller MMC with temperature monitoring and hot swap support For First Time Buyers the engineering documentation TAMC900 ED is recommended The engineering documentation includes
48. ate if the channel enable bit CHENx is not set TAMC900 User Manual Issue 2 0 1 Page 30 of 71 6 4 Global Reset and Software Trigger Input Simulating external trigger signals can be performed by the subsequent register Trigger events initiated by using this register are only processed if software trigger input is selected per channel group Moreover the register can be used to reset the internal structure that is channel specific Bit Symbol Description Access Reset Value 15 CRST7 R W 0 14 CRST6 R W 0 13 CRST5 R W 0 12 CRST4 Resetting a channel x is performed by writing 0x1 at the R W 0 11 CRST3 Channel corresponding bit position CRSTx RW 0 10 CRST2 R W 0 9 CRST1 R W 0 8 CRSTO R W 0 7 1 Reserved R 0 0 SWT Writing a value 0x1 at this bit position causes a single cycle R W 0 trigger input Table 6 4 Global Reset and Software Trigger Input Register Address 0x10 The software generated trigger inputs are equivalent to external trigger signals Read Value is always zero TAMC900 User Manual Issue 2 0 1 Page 31 of 71 6 5 Sample Clock Configuration 0 1 The register defines the source for the operating respectively sampling clock This setting is applied due to physical restrictions see chapter Clock Distribution on a group of ADCs 0 3 and 4 7 where the below structure is the same for both groups Choos
49. be damaged if higher voltage levels are used TAMC900 User Manual Issue 2 0 1 Page 50 of 71 13 On Board CPLD The On Board CPLD of the TAMC900 is used for static board configuration and provides the following functions QDR II SRAM DLL enable disable ADC Shutdown ADC Output Enable ADC Mode selection all 4 modes available Control of 16 GP 1 O pins to the SICA Enabling disabling of the local FPGA clock Controlling of the jitter attenuator Control of the local clock distribution Please refer to the following subsections for more information 13 1 Interface to FPGA All functions of the CPLD are accessible by the User FPGA via an easy to use interface The clock is driven by the CPLD Per default this is set to 25 MHz It can be set to 12 5 MHz if necessary Write Read to CPLD from CPLD oe LILI LI LI UL 4 Valid Valid Address 4 0 Address Address Write TR Read XXX ts AAK Figure 13 1 Timing of FPGA CPLD Interface TAMC900 User Manual Issue 2 0 1 Page 51 of 71 13 2 CPLD Register Description The following registers are implemented in the on board CPLD of the TAMC900 They are used for static board configuration For user access the CPLD provides an interface to the FPGA CPLD Description Register Value after Reset Address hex access 0x00 A
50. ccess Reset Value 31 0 CREV Code Revision of the FPGA Firmware R Table 6 14 Revision Control Register Address OxE8 3 The version of the Firmware is not fixed and depends besides others on the hardware version TAMC900 User Manual Issue 2 0 1 Page 39 of 71 Interrupts Legacy interrupt messages and message signaled interrupts MSIs are supported by the firmware In dependency of the chosen mode defined by the PCI header and system driver software one of the two methods is used In legacy interrupt mode INTA interrupts are asserted in case of an interrupt event The MSI mode uses a single vector for interrupt signalize A larger vector would simplify the detection of an interrupt source but increase the implementation and system resource efforts Moreover it is not safe to obtain the resources for a multi vector MSI from the system 7 1 Interrupt Sources IRQ Description IRQCHO IRQCH1 IRQCH2 Every channel can generate an interrupt event if it is enabled appropriately The IROCH3 General DMA Status register can be used to detect which channel caused the IROCHA interrupt The corresponding Channel DMA Status register must be read afterwards to obtain further information about the interrupt 5 6 IRQCH7 Table 7 1 Interrupt Sources 7 2 Interrupt Handling IRQ Description IRQ Enable IRQ Ack IRQCHO Channel
51. current processed DMA transmission is aborted the channel DMA status register is cleared If a channel is reset while others are running this channel cannot be started until the others of the corresponding channel group have finished 4 7 2 Channel Activation The activation is based on the Global Channel Configuration register and the Channel Configuration register Both have to be configured appropriately The significant settings in the Channel Configuration register are the Channel Enable Bit CHEN and the Channel DMA Enable Bit DMAEN Bit CHEN is used to activate physically the concatenated ADC This refers to the LTC2254 Output Enable and the Shutdown steering input Valid ADC samples can only be obtained if the sample frequency is set correctly and this bit is set Stopping a channel should not be done with this steering bit since the DMA operation will not stop TAMC900 User Manual Issue 2 0 1 Page 21 of 71 Bit DMAEN steers the data transport into the Tracking Buffer and to the associated DMA Engine Moreover it controls the DMA transmission Accordingly if the bit is not set no DMA transmission can be started respectively performed This means that e g in the case that the DMA Engine has been started and the DMA enable bit is reset during operation the processing e of the current packet is performed but no further packets are generated e all dynamic DMA information is held Stopping DMA transmission should on
52. dress 0x10 TAMC900 User Manual Issue 2 0 1 Page 56 of 71 13 2 9 Clock Mux Control Register Address 0x11 Bit Symbol Description Access Reset Value reserved for future use R 0 6 reserved for future use R 0 SEL 47 Select Clock for ADC 4 to 7 R W 0 0 route clock from crosspoint switch to ADCs 1 route Clock from FPGA to ADCs 4 EN_47 Enable Clock outputs to ADC 4 to 7 R W 0 0 disable 1 enable 3 reserved for future use R 2 R 1 SEL 03 Select Clock for ADC 0 to 3 R W 0 route clock from crosspoint switch to ADCs 1 route Clock from FPGA to ADCs 0 EN 03 Enable Clock outputs to ADC 0 to 3 R W 0 0 disable 1 enable Table 13 10 Clock Mux Control Register Address 0x11 TAMC900 User Manual Issue 2 0 1 Page 57 of 71 13 2 10 Jitter Attenuator Control Register Address 0x12 Bit Symbol Description Access Reset Value reserved for future use R 0 6 SEL2 Frequency select pins for QAx and QBO outputs R W 0 Inputs Outputs QAO SEL2 SEL1 SELO OA1 QBO 5 SEL1 0 0 0 2 5x fin 2 5x fin R W 0 1 0 0 1X fin 2 5X fin 0 1 0 1 25x fin 2 5x fin 1 1 0 2 5X fin 1 25x fin 0 0 1 2 5X fin 1x fin SELU 1 0 1 1 1 25x fin RON i 0 1 1 1 25x fin 1x fin 1 1 1 1 25x fin 1 25x fin Input frequency fin should be 100 MHz AMC FCLKA 3 reserved for future use
53. e trigger event this register is used The number of samples that are transmitted before the trigger event pre trigger data is defined by the register value Bit Symbol Description Access Reset Value 23 18 Reserved R 0 17 0 NUM Number of samples that is transmitted via DMA as pre R W 0 trigger data Table 6 9 Channel Pre Trigger Data Register Address 0x64 0x4 Channel TAMC900 User Manual Issue 2 0 1 Page 35 of 71 6 10 Channel Data 0 7 Reading the current ADC sample of a channel 0 7 is possible via these registers For this the channel must be enabled in the corresponding Channel Configuration register CHEN since otherwise the read value will always be zero 0x0 The intention of this register interface is more a static evaluation of the input data e g channel calibration The channel data is subdued a sign extension for both ADC operating modes 2 s complement and offset binary output format Bit Symbol Description Access Reset Value 15 13 SEXT Sign Extension R 0 12 0 DAT In dependency of the selected ADC operation mode the R 0 converted data is readable through this register r Converter 5 stage internal pipeline Table 6 10 Channel Data Register Address 0x84 0x4 Channel TAMC900 User Manual Issue 2 0 1 Q The value read from such a register cannot be the last that has been sampled due to the AD Page 36 of 71
54. element is loaded Thus the last element must point to the first if the list should be used again If a DMA channel is stopped before its linked list could have been processed completely it is not clear up to which address the data inside the window is valid Such a case can be handled by controlling the fill level counter This monitors the current position inside a window The information can be obtained through the DMA Buffer Fill Level register There is one dedicated register for every channel The channels are processed in a rotating mechanism that considers possible interrupted PCI Express transactions The channels are selected for transmission in a consecutive manner starting with channel zero After the last channel has been processed the first is taken again If the current selected channel has no packet prepared e g since it is disabled or is offline caused by a transmission error the subsequent channel is selected The engine does not make any restriction to the DMA window size Odd and even sizes are legal If a window has a remaining size less than the static packet size 32 DWORDS a packet is generated that fills the remaining gap of the window Interrupt events have to be acknowledged in the corresponding Channel DMA Status register after occurrence For additional information about interrupts refer chapter Interrupts 4 4 DMA Descriptors The DMA descriptors are used to define target memory regions windows that are
55. enerated on the SICA A 120 pin high speed connector from Samtec QSE 060 01 L D A is used on the TAMC900 to interface with the SiCA The pin assignment of this connector can be found in the chapter I O Connector 14 1 Connector and Standoff Positions Five mounting positions for Standoffs are provided by the TAMC900 to secure the SiCA on the TAMC900 Depending on the size of the SICA all or only a subset of these can be used to secure the SiCA on the TAMC900 See figure below for the exact position we 157 20 mm p 750mm 37 80 mm re CO Or 67 73 mm ele 66 40 mm 46 22 mm 3 5 83 mm dt z S 2780mm I 59 10 mm T 3 157 20 mm Figure 14 1 TAMC900 Connector and Standoff Positions TAMC900 User Manual Issue 2 0 1 Page 60 of 71 14 2 Mating Connector The mating connector connects the SiCA with the TAMC900 The Samtec QSE QTE Series is used and the height of the connector mounted on the SiCA dictates the stacking height of the SiCA above the TAMC900 Possible connectors are e g Pin Count 120 pins Connector Type Q Strip High Speed SM
56. ensors via IPMI VOLT_PAYLOAD monitors the 12V Payload Power Supply VOLT_SICA monitors the 6V Power Supply for the Signal Conditioning Adapter 15 3 Connectivity The on board FPGA of the TAMC900 is connected to AMC Port 4 to 11 AMC FCLKA CLK3 is connected to the FPGA via a Jitter Attenuator that scales the clock from 100 MHz up to 250 MHz and reduces the Clock Jitter TAMC900 User Manual Issue 2 0 1 Page 63 of 71 15 4 Interfaces to Payload The MMC has the following interfaces that allow interaction between the on board FPGA and the MMC Interface Description Payload Reset The MMC controls the Payload RESET signal The RESET signal stays low for app 200ms after Payload Power is turned on and FPGA is configured FUNC_LED2 FUNC_LED2 is an Input to the MMC A rising or falling edge of FUNC LED triggers the MMC to flash the USER LED in the front panel turn off for app 100ms EKEY 4 1 These signals can be used to transmit connectivity data from the MMC to the FPGA This may be necessary in applications that implement different kinds of connections from the FPGA to the AMC interface The implementation in MMC and FPGA has to be done by the customer 12C This 12C Interface can be used by the FPGA to read connectivity data from the MMC This may be necessary in applications that implement different kinds of connections from the FPGA to the AMC interface The implementation in MMC and FPGA has to be done b
57. ers can be accessed with the same data width The size column present in the subsequent table shows the effective width of the implemented registers Registers with a smaller size than 32 bit will align their data to bit zero Accessing registers with a smaller size than their effective one may result in invalid data Offset to PCI Register Name Access Size Base Address 0 Bit 0x0000 Module Status and DCM 0 1 Status R 32 0x0004 DCM Multiply Divide O R W 16 0x0008 DCM Multiply Divide 1 R W 16 0x000C Global Channel Configuration R W 16 0x0010 Global Reset and Software Trigger Input R W 16 0x0014 Sample Clock Configuration 0 R W 8 0x0018 Sample Clock Configuration 1 R W 8 0x001C Trigger Configuration 0 R w 8 0x0020 Trigger Configuration 1 R W 8 0x0024 Channel Configuration 0 R W 8 0x0028 Channel Configuration 1 R W 8 0x002C Channel Configuration 2 R W 8 0x0030 Channel Configuration 3 R W 8 0x0034 Channel Configuration 4 R W 8 0x0038 Channel Configuration 5 R W 8 0x003C Channel Configuration 6 R W 8 0x0040 Channel Configuration 7 R W 8 0x0044 Channel DMA Base Descriptor Addresses 0 R W 32 0x0048 Channel DMA Base Descriptor Addresses 1 R W 32 0x004C Channel DMA Base Descriptor Addresses 2 R W 32 0x0050 Channel DMA Base Descriptor Addresses 3 R W 32 0x0054 Channel DMA Base Descriptor Addresses 4 R W 32 0x0058 Channel DMA Base Descr
58. es The Platform Flash or the FPGA are programmed using the Payload JTAG interface The Payload JTAG interface is accessible via the Payload JTAG connector J4 N 7 The on board CPLD is part of the Payload JTAG Cain TEWS recommends setting the CPLD in Bypass Mode during FPGA or Platform Flash JTAG operations 8 2 MMC Interface The FPGA has the following signals which are connected to the MMC Interface Description FUNC_LED2 This signal can be used to flash the USER LED in the front panel of the TAMC900 A rising or falling edge of FUNC_LED2 triggers the MMC to turn the USER LED off for app 100ms EKEY 4 1 These signals can be used to transmit connectivity data from the MMC to the FPGA The implementation in MMC and FPGA has to be done by the customer Please refer to the chapter Module Management Controller MMC for more information I2C This 12C Interface can be used by the FPGA to read connectivity data from the MMC The implementation in MMC and FPGA has to be done by the customer Please refer to chapter Module Management Controller MMC for more information RXDO TXDO These signals can be used to implement a serial communication between FPGA and MMC By default this is used as debug output of the MMC Any other implementation in MMC and FPGA has to be done by the customer Table 8 1 FPGA Signals connected to the MMC TAMC900 User Manual Issue
59. ial input voltage range of the LTC2254 is 2V and can be set to 1V based on the application The 2V input range will provide the best signal to noise performance while maintaining excellent SFDR The 1V input range will have better SFDR performance but the SNR will degrade by 5 7dB By default the TAMC900 sets the input voltage range of all ADCs to 2V The Common Mode Voltage of the ADC Differential Inputs is 1 5V 9 1 3 Input Frequency Range The LTC2254 provides a full power bandwidth from DC to 640 MHz 9 2 Operational Modes Each ADC may be placed in shutdown or nap mode to conserve power In sleep mode which powers down all circuitry including the reference the ADC typically dissipates 1mW When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize In nap mode the ADC typically dissipates 15mW In nap mode the on chip reference circuit is kept on so that recovery from nap mode is faster than that from sleep mode typically taking 100 clock cycles In both sleep and nap modes all digital outputs are disabled and enter the Hi Z state If the sample clock is stopped during normal ADC operation the output data becomes invalid After the sample clock is turned on it takes app 4000 clock cycles until the output data becomes valid 9 2 1 Data Format The ADCs parallel digital output can be selected for offset binary or 2 s complement format
60. ing a clock source must be done considering the ADCs specification to avoid a physical damage Bit Symbol Description Access Reset Value 7 4 SRSC Sample Rate Source Configuration R W 0 Selection Sample Clock 000x AMC Reference Clock 001x External Clock 2 010x External Clock 1 011x External Clock 0 1xx1 FPGA DCM 1 1xx0 FPGA DCM 0 Others Reserved 3 1 Reserved R 0 SCEN Channel Group Sample Clock Enable R W Table 6 5 Sample Clock Configuration Register Address 0x14 0x4 Channel Group The x inside the embedded table represents a do not care condition TAMC900 User Manual Issue 2 0 1 Page 32 of 71 6 6 Trigger Configuration 0 1 Due to the internal processing all channels in one group refer beginning of chapter Functional Procedures are restricted to have the same trigger configuration In accordance with that there are two trigger configuration registers that allows defining the corresponding settings three external trigger inputs provided by the SiCA TISEL Input Selection Polarity 0000 Disabled 0010 K i Rising Trigger input 0 TRIG 0 0011 Falling 0100 i i Rising Trigger input 1 TRIG 1 0101 Falling 0110 Risin Trigger input 2 TRIG_2 g 0111 Falling 1000 Software Trigger Others Reserved Bit Symbol Description Acce
61. iptor Addresses 5 R W 32 0x005C Channel DMA Base Descriptor Addresses 6 R W 32 0x0060 Channel DMA Base Descriptor Addresses 7 R W 32 0x0064 Channel Pre Trigger Data Size 0 R W 24 0x0068 Channel Pre Trigger Data Size 1 R W 24 0x006C Channel Pre Trigger Data Size 2 R W 24 0x0070 Channel Pre Trigger Data Size 3 R W 24 The read value will always be zero TAMC900 User Manual Issue 2 0 1 Page 26 of 71 Offset to PCI Register Name Access Size Base Address 0 Bit 0x0074 Channel Pre Trigger Data Size 4 R W 24 0x0078 Channel Pre Trigger Data Size 5 R W 24 0x007C Channel Pre Trigger Data Size 6 R W 24 0x0080 Channel Pre Trigger Data Size 7 R W 24 0x0084 AD Channel Data 0 R 16 0x0088 AD Channel Data 1 R 16 0x008C AD Channel Data 2 R 16 0x0090 AD Channel Data 3 R 16 0x0094 AD Channel Data 4 R 16 0x0098 AD Channel Data 5 R 16 0x009C AD Channel Data 6 R 16 Ox00AO AD Channel Data 7 R 16 0x00A4 General DMA Status R 8 0x00A8 Channel DMA Status 0 R w 16 0x00AC Channel DMA Status 1 R W 16 0x00BO Channel DMA Status 2 R W 16 0x00B4 Channel DMA Status 3 R W 16 0x00B8 Channel DMA Status 4 R W 16 0x00BC Channel DMA Status 5 R W 16 0x00C0 Channel DMA Status 6 R W 16 0x00C4 Channel DMA Status 7 R W 16 0x00C8 Channel DMA Buffer Fill Level 0 R 32 0x00CC Channel DMA Buffer Fill Level 1 R 32 0x00D0 Channel DMA Buffer Fill Level 2 R 32 0x
62. is used to realize the different operation modes by using the on board QDR Il memories The modes are described in the following chapters N Q Note that an operation mode is set for entire channel group and cannot be done for every channel in a different way The use of the QDR II memory in the data path has another reason In case of PCI Express transmission gaps the memory can buffer the data so that the data integrity is still held Based on the internal organization structure there are 256k words for a single channel At a sample frequency of 105 MHz a period of approximate 2 4 m sec can be buffered before the loss of data occurs The restriction on channel groups has impacts on the buffer technique The throttle mode is shared by the concatenated channels It is used to stop providing new data to the DMA Engines if one engine signalizes that its dedicated channel FIFO is running full One stalled channel may cause that all channels of the group get into error state due to buffer overflow TAMC900 User Manual Issue 2 0 1 Page 16 of 71 4 2 1 Operation Modes OM One operation mode is provided by the firmware compare chapter Trigger Configuration 0 1 which allows selecting which acquired ADC data should be transmitted via DMA The different settings are explained afterwards There is no absolute sample count that defines the end of transmission This is performed until a descriptor signalizes the end of
63. ly be done by using the DMAEN bit since all information especially the one up to with memory address valid data have been placed is visible The master enable is placed in the Global Channel Configuration register If the channel is not activated there the channel is held in reset This allows configuring the channel completely before activation Thus all changes occur concurrently and not consecutively The master activation of a channel causes assuming that the channel has been configured that e ADC data can be read through the register interface e the channel s DMA Base Descriptor Addresses register content is used to load DMA descriptor information e DMA information e g Channel DMA Buffer Fill Level is set in the register map independence of the trigger mode the QDR II memory starts monitoring the ADC data The asterisk marked aspect is already available after the Enable bit in the Channel Configuration register see below has been set 4 7 3 Descriptor Change As afore mentioned the DMA operation makes use of DMA descriptors There is one base address Descriptor address per channel which is used as entry point to the linked list Several processing flags can be set for a descriptor before the channel has been activated Changes after activation may be destructive Hence only if a channel is not operating a new base address can be set This causes a reload of the selected address A change of an already loaded
64. nnnannnnnnnnnannnanansnannnnnannana 41 TABLE 8 2 AMC FABRIC INTERFACE CONNECTIONS TO THE FPGA aitiiaiaaaaaiaasaasaassaasansaassasaannana 42 TABLE 8 3 AMC FCLKA CONNECTION TO THE FPGA aiiaiaaiaaaaaaaaaaaasassaasaasaasnasaannaananananansnannnsannnananana 43 TABLE 9 1 ADC OUTPUT DATA 5 45 TABLE 11 1 FPGA LOCAL CLOCK LOLK 250 49 TABLE 11 2 FPGA CLOCK OUTPUT Svani 7 71 111 1 11 17 49 TABLE 11 3 ADC FEEDBACK CLOCKS 0 7 nana 49 TABLE 12 1 LVDS LINK PIN ASSIGNMENT 7 777777177 7 50 TABLE 13 14 GPED REGISTER OVERVIEW r iritan iegarena ki nass 52 TABLE 13 2 ADC X CONTROL REGISTER ADDRESS 0X00 TO 0 0 27 0220 53 TABLE 13 3 SICA INPUT REGISTER 1 ADDRESS 0X08 aaiiaiiaaaaaaaaaasaasaansaanaasansnannannnnnannnannansnannnnnnanananani 53 TABLE 13 4 SICA INPUT REGISTER 2 ADDRESS 0X09 aaiiaiaaaaasaaaaasaasaansnanansannnannnnnnnnnannnanansnnnnnnnnanananana 54 TABLE 13 5 SICA OUTPUT REGISTER 1 ADDRESS 0X0A aaiiaiaaiaaaaaaaasaasaasaasnansnannannnnnnnnnannnannnnsnannnnnnnnnna 54 TABLE
65. nterfaces to the Signal Conditioning Adapter See the figure below for pin locating of this connector Pin 2 Pin 40 Pin 120 h 4 CE E IN Pin 1 Pin 39 Pin 119 Figure 17 2 I O Connector Pin Positions TAMC900 User Manual Issue 2 0 1 Page 66 of 71 17 2 NO Connector The I O interface of the TAMC900 is the connector between SICA and the TAMC900 The Samtec QTE QSE Series are used as I O connection between TAMC900 and the SICA The TAMC900 carries a QSE connector and the mating QTE connector is populated on the SICA The stacking height is defined by the QTE connector on the SICA The Samtec QSE 060 01 L D A or compatible is used on the TAMC900 Pin Signal Level Pin Signal Level 17 VDS s VDS 3 VDS 35 AIN 0 LVDS 37 AIN 0 LVDS 45 AN1 LVDS 53 AN 24 2 logic Ground 55 En VDS 57 logic Ground 58 LVDS 6 LVDS TAMC900 User Manual Issue 2 0 1 Page 67 of 71 Pi Signal Level Pin Signal Level 59 _ AIN_3 60 GND logic Ground 61 AIN 3 LVDS_7 LVDS 5 67 ee iVDS a LVDS 85 as TRIG 0 ives 89 oo TRIGH os os mea 97 os mes ives 119 GP_IO_15 2 5 Volt CMOS 120 GND logic Ground Table 17 1 Pin Assignment I O Connector TAMC900 User Manual Issue 2 0 1 Page 68 of 71 17 3 MMC JTAG Connector Factory Use Only Pin Signal Level 3 3V CMOS TTL 3 3V CMOS TTL TDI 3 3V CMOS TT
66. obal Channel Configuration This register controls global high level operation settings This includes top level activation deactivation and trigger activation of certain channels The trigger activation bits have been implemented due to safety consideration This prevents spurious interrupt processing while requiring arming a channel before using Bit Symbol Description Access Reset Value 15 CATE7 R W 0 14 CATE6 13 CATE5 To activation a channel for processing a subsequent trigger event the corresponding bit has to be set The bit is reset 12 CATE4 after an event has processed 1 SATES 0 channel not armed 10 CATE2 1 channel armed 9 CATE1 8 CATEO 7 CHEN7 R W 0 2 ou A channel is enabled CHENx for internal processing if the 5 CHENS accompany bit is set The configuration is done in the way 4 CHEN4 0 disable channel 3 CHEN3 1 enable channel 2 CHEN2 The channel numbers 0 7 matches the ADC numbers 0 7 1 CHEN1 0 CHENO Table 6 3 Global Channel Configuration Register Address 0xC The channel trigger activation bits CATx are reset immediately after processing has started It can be re enabled first if corresponding channel processing has been finished Activation of a channel via the register above should be done after the channel has been configured correctly Internal processing holds the corresponding channel processing logic in reset st
67. on TAMC900 User Manual Issue 2 0 1 Page 14 of 71 4 1 Channel Logic The channel logic is implemented for every channel group It realizes the data synchronization between the internal processing clock and the ADC sample clock domain This is necessary because these clocks can have an arbitrary ratio to each other Only the limits of the ADCs have to be considered The ADCs have an operating frequency of 1 MHz up to 105 MHz Besides this the sign extension is performed in this unit This has been implemented to simplify the data processing out of the target memory by mapping the ADC values into legal data types The sign extension method is described below In 2 th complement the ADC sign bit 13 is mapped onto the additional bits 14 and 15 e In binary offset format the ADC sign bit 13 is mapped onto bit 15 and the bits 13 and 14 are set to zero Ant An OF Data Data 2V Range Offset Bin 2 s Compl gt 1 000000V 1 Ox9FFF Ox1FFF 0 999878V 0 Ox9FFF Ox1FFF 0 999756V 0 Ox9FFE Ox1FFE 0 000122V 0 0x8001 0x0001 0 000000V 0 0x8000 0x0000 0 000122V 0 Ox1FFF OxFFFF 0 000244V 0 Ox1FFE OxFFFE 0 999878V 0 0x0001 OxE001 1 000000V 0 0x0000 OxE000 lt 1 000000V 1 0x0000 OxE000 Table 4 2 ADC Data Format with Sign Extension TAMC900 User Manual Issue 2 0 1 Page 15 of 71 4 2 Tracking Buffer The tracking buffer is the central unit of the module It
68. peration R W INTEN Using this flag allows to enable or disable the interrupt generation 0 disable channel Interrupts 1 enable channel Interrupts R W CHEN Channel enable 0 disable channel 1 enable channel R W zero 0x0 Table 6 7 Channel Configuration Register Address 0x24 0x4 Channel TAMC900 User Manual Issue 2 0 1 QS If a channel is not enabled CHEN the corresponding Channel Data register will always be Page 34 of 71 6 8 Channel DMA Base Descriptor Addresses 0 7 This register has two functions On the one hand it holds an address into tne embedded Block RAM DMA Descriptor Space This defines the first descriptor to load out of the memory for a channel Consequently it selects the first out of the three DMA descriptor instruction words On the other hand it shows the Block RAM address of the current processed descriptor Bit Symbol Description Access Reset Value 31 26 Reserved R 0 25 16 CADDR The pointer reflects the memory address of the current R 0 loaded descriptor 15 10 Reserved R 0 9 0 BADDR This address points into the memory where the channel R W 0 base address descriptor is placed Table 6 8 Channel DMA Base Descriptor Address Register Address 0x44 0x4 Channel 6 9 Channel Pre Trigger Data Size In addition to the trigger mode that allows transmitting data before and after th
69. ss Reset Value Reserved R 0 6 4 TMSEL Selection of the Trigger operation mode R W 0 TMSEL Input Selection 000 Disabled 001 Around Trigger Data Gathering Others Reserved 3 0 TISEL Trigger input Source and polarity selection There are R W 0 Table 6 6 Trigger Configuration Register Address 0x1C 0x4 Channel Group TAMC900 User Manual Issue 2 0 1 Page 33 of 71 6 7 Channel Configuration 0 7 ADC respectively channel specific configuration and steering settings are defined by these registers The settings are made in addition to the general channel activation for internal processing see chapter Global Channel Configuration Bit Symbol Description Access Reset Value Reserved R 0 EFSEL Endian Format Selection steers the endianess of the DMA data in host memory 0 little endian 1 big endian R W 0 OF ADC Output Format 0 offset binary output format 1 2 s complement output format R W CDCS ADC Clock Duty Cycle Stabilizer 0 disabled 1 enabled R W OFSEN Overflow Signalize Enable steers whether an ADC overflow signal is taken into the Channel DMA status register or not 0 suppress ADC overflow 1 consider ADC overflow Activation causes DMA events if an overflow is signalized and interrupt generation is enabled R W DMAEN The bit steers the DMA channel data transmission 0 disable DMA operation 1 enable DMA o
70. ture use R 0 1 SHDN ADC Shutdown R W 1 0 normal operation 1 shutdown corresponding ADC 0 OE ADC output Enable enables the digital outputs of the ADC R W 0 0 output disable 1 output enable Table 13 2 ADC x Control Register Address 0x00 to 0x07 13 2 2 SICA Input Register 1 Address 0x08 Bit Symbol Description Access Reset Value 7 SICA15 R 6 SICA14 R 5 SICA13 R 4 SICA12 Displays the value of the corresponding SiCA general R 3 I SiCA11 purpose pin Value after reset depends on the SICA R 2 I SICA10 R i 1 SICA9 R 0 SICA8 R Table 13 3 SiCA Input Register 1 Address 0x08 TAMC900 User Manual Issue 2 0 1 Page 53 of 71 13 2 3 SICA Input Register 2 Address 0x09 Bit Symbol Description Access Reset Value 7 _SiCA7 R W 6 _SiCA6 R W 5 SICA5 R W 4 SICA4 Displays the value of the corresponding SiCA general R W 3 SiCA3 purpose pin Value after reset depends on the SICA R W T 2 SICA2 R W 1 SICA1 R W 0 SICAO R W Table 13 4 SiCA Input Register 2 Address 0x09 13 2 4 SiCA Output Register 1 Address 0x0A Bit Symbol Description Access Reset Value 7 O SICA15 R W 0 6 O_SICA14 R W 0 OSEN The value written to this register is displayed to the BL 4 0 SI
71. uence Host Interrupt SEQHI is asserted if a Descriptor R W 0 of a Linked List has been processed with the Host Interrupt flag set 7 2 Reserved R 4 DSINF Data sampling has stopped due to the load of an invalid R W descriptor 3 1 Reserved R 0 OVERR Showing that the ADC channel data got corrupt invalid R W due to an internal buffer overrun is the purpose of this bit DMA transmission is stopped in such a case Table 6 12 Channel DMA Status Register Address 0xA8 0x4 Channel The status flags have to be cleared for acknowledgement The errors marked with an asterisk require a channel reset to get into a defined state All flags are cleared automatically after processing start valid trigger input TAMC900 User Manual Issue 2 0 1 Page 38 of 71 6 13 Channel DMA Buffer Fill Level 0 7 These registers offer the possibility to monitor the current DMA window write address of a channel Bit Symbol Description Access Reset Value 31 0 CADDR Current DMA Window Write Position Address R 0 Table 6 13 Channel DMA Buffer Fill Level Register Address 0xC8 0x4 Channel NM 7 The value after channel setup and activation is the one that has been read from the defined k gt DMA base descriptor 6 14 Revision Control Register The register content reflects the firmware revision currently implemented on the module Bit Symbol Description A
72. uisition system implemented on the TAMC900 The structure is abstract in order to show the different functional units and the data flow All physical connections are termed in a bold style The remaining ones are internal connections The functional units are described in the subsequent chapters AMC PCI Express Control Clock Connection i i Distribution Sampling ADC Trigger Logic Clocks Inputs Inputs Sample Rate Logic PCI Express ADC j gt BE Endpoint Synchronisation Sign Extension 4 lt gt Registers FIFO Buffer Channel Logik x2 aa ESS DMA Logic I p FP A Operation Modes Channel FIFO Data QDR II Data DMA Engine x8 i Steering Memory Steering Tracking Buffer x2 Figure 4 1 TAMC900 FPGA System Structure The physical clocking structure of the TAMC900 results in two different ADC channel groups The module contains eight separate 14 bit ADC channels that are structured in the way two times four The ADC to channel group assignment is shown in the subsequent table Channel Group Corresponding ADC s 0 0 3 1 4 7 Table 4 1 ADC Channel Group Assignment Each group has restrictions concerning a common sampling clock and a common trigger configurati
73. until the linked list has been finished by a descriptor Pre and Around Trigger Data Gathering require some time between trigger events to monitor ADC channel data This time depends on the adjusted sample rate If the inter trigger event period is too short it is possible that the transmitted sample data is invalid There are three external physical trigger sources that can be used These are described in chapter Trigger Configuration 0 1 For adaptation purposes the interpretation of a trigger input signal change edge can be defined Currently only edge evaluated trigger have been implemented Level trigger are not considered Besides the external trigger inputs a software trigger input can be selected This make use of an additionally register see chapter Global Reset and Software Trigger Input to initiate processing by writing at a certain bit position All trigger inputs are handled in the same manner There is no difference Additionally the Post Trigger Data gathering can be used in conjunction with the software trigger to realize a free running operation mode if necessary TAMC900 User Manual Issue 2 0 1 Page 17 of 71 4 3 DMA Engine Generating PCI Express Transaction Layer Packets TLPs from the channel data and transmitting these via the PCI Express Interface is the purpose of a DMA Engine Every engine has an internal buffer structure build of a first level FIFO and a second level transmit buffer The
74. used to store the sampled data of a channel inside the host memory For this a descriptor contains on the one hand flags required for its processing and on the other hand information to build a Linked List LL TAMC900 User Manual Issue 2 0 1 Page 18 of 71 A DMA descriptor consists of three instructions words where every word comprises 32 bit These have to be arranged in a consecutive manner in the module s dedicated memory see chapter DMA Descriptor Space Placing the descriptors into embedded Block RAM inside the FPGA will reduce the PCI Express traffic and hence accelerate the internal processing Moreover it simplifies the access onto the descriptor instruction words An embedded Block RAM in Virtex 5 is 36 kb large and thus can contain up to 42 logical DMA regions for one physical ADC if all eight channels are used parallel One single channel alone can have up to 341 different regions The firmware occupies two memory blocks thus having twice the mentioned depth The number of address bit is defined in accordance to that The structure of this block is shown below Bits 31 28 27 24 23 22 21 20 19 11 10 0 OxC Reserved LF Reserved HI CBA Reserved Subsequent Linked List Pointer resident in on board block RAM Pointer Address to DMA Memory Region inside the Host Memory Length of the DMA Memory Region inside the Host Memory in Samples 16 bit words Table 4 3
75. y the customer RXDO TXDO These signals can be used to implement a serial communication between FPGA and MMC By default this is used as debug output of the MMC Any other implementation in MMC and FPGA has to be done by the customer TAMC900 User Manual Issue 2 0 1 Page 64 of 71 16 On Board Indicators For a quick visual inspection the TAMC900 offers 3 LEDs in the front panel Please refer to chapter Front Panel LEDs for more information The TAMC900 provides additional on board LEDs that indicate Power Good of the local power supplies and successful FPGA configuration Figure 16 1 On Board Indicators 16 1 DONE LED The green DONE LED is located on the bottom side of the PCB It indicates that the FPGA is successful configured If the LED is off the FPGA is not configured 16 2 Power Good LEDs There are six green Power Good LEDs on the bottom side of the TAMC900 If one of the LEDs is off this indicates a power failure of the corresponding power supply TAMC900 User Manual Issue 2 0 1 Page 65 of 71 17 Pin Assignment 17 1 Overview Payload JTAG X2 AMC Connector X100 Pin 85 MMC JTAG pg Pn J4 Pin 86 I O Connector X3 Figure 17 1 Connector Overview The TAMC900 interfaces to a Signal Conditioning Adapter that carries the I O connectors accessible through the front panel The TAMC900 has a 120 pin connector Samtec QSE 060 01 L D A that i

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