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USER MANUAL Hardware Part

1. RDS amp MPX BANDPASS DEMODU esal z FILTER LATOR lloras Tats I BIT RDS RBDS DECODER BUFFER RBDS Fig 8 25 RDS RBDS block diagram The RDS RBDS decoder provides block synchronization error detection error correction complex flywheel function and programmable block data output New processed RDS RBDS block information is signalled to the main microcontroller as new data available by use of the DAVN output The block data itself and the corresponding status information can be read out via IIC bus request 8 7 2 RDS bandpass filtering The RDS chain has a separate input FM_RDS This enables RDS updates during tape or other analog source play The RDS chain contains a third order sigma delta AD convertor followed by two decimation filters The first filter passes the multiplex band including the signals around 57 kHz and reduces the sigma delta noise The second filter reduces the RDS bandwidth around 57 kHz The overall filter curve is shown in Fig 8 26 and a more detailed curve of the RDS 57kHz band in Fig 8 27 Philips Semiconductors Usermanual 54 SAA7709H N1B ana i fel Bl A ne AN v ee ee ee T i ee A AA am ETR TOR a ld i pIE I im gQueney Ha Fig 8 26 Overall frequency response curve decimation filters atenuado rid31 a i i i i E I I se Tey I I I I E I i i K a i ALS Jhar a A s A Lg E 5 l 4 toy yt i is wood i Ez i j i
2. e 4 A o A ni te ral ca ers gnd_sel2 2 gt 5 3 CDR_NEG AE C8 R7 Fig 8 19b Full Differential Analogue CD input Philips Semiconductors Usermanual 46 SAA7709H N1B Analogue CD input with floating source In case the signal ground of the CD player is floating e g a battery supplied CD player the input circuit as given in figure 8 20 does not work due to the high input impedance of the circuit This problem can be solved by replacing resistor R10 with two diodes connected in anti parallel see figure 8 21 Recommended diode types are BAS216 or BAW62 CDSP c6 R6 EN ansel_sel1 oL oe NS dif_sw1 T AD 7 AS Cal 1 gt e Ss dr l a CD cable I coeno 0 Qn p Ground bl Tr 1N g Se as 3 Ro ciol ansel_sel2 j 0 con a aN R7 ma c8 2N x dif_sw ae AD2 17 gt a a P E 27 coann Le oa sel2 a ah BAS216 r BAW62 37 4 Vrefad c12 T Fig 8 21 Analogue CD input with floating CD player 8 5 Phone and Navigation inputs The SAA7709H has separate inputs for Phone and Navigation These inputs have their own ground input therefor several different configurations are possible such as Single Ended High Common Mode and Full Differential Mode The basic circuit diagram is given in figure 8 22 As example the Phone input is a differential input and the NAV
3. The External DAC output can be enabled disabled with bit 15 en_dac_out of the Selector registers address 0FF9 by default the external DAC output is disabled To minimise EMC the output has to be disabled default in case the output is not used The UDA1320 or UDA1330 Filter stream DAC can be applied to convert the digital subwoofer and center signal this DAC type is compatible with the 3 3V output levels of the SAA7709H Philips Semiconductors Usermanual 69 SAA7709H N1B 8 13 X tal oscillator circuit OSC_IN and OSC_OUT pin 63 and pin 64 The on chip crystal oscillator is a Pierce oscillator and is described in the data sheet The crystal is running in fundamental mode on 11 2896 MHz Although a multiple of the crystal frequency falls within the FM reception band this will not influence the reception because the crystal is driven in a controlled way The crystal oscillator circuit can operate both in master mode and in slave mode The blockdiagram of the X tal oscillator circuit in master mode is depicted in figure 8 25 The active element Gm compensates for the loss resistance of the crystal The AGC circuit controls the gain of the oscillator and prevents clipping of the generated sine wave and therefor minimises the higher harmonics The blockdiagram of the X tal oscillator circuit in slave mode is depicted in figure 8 26 In order to minimise feedback due to ground bounce the power supply connections of the crys
4. PSRR In the CDSP application we use f gt 1 kHz Vripple 100 mV ripple rejection PSRR typ 39 dB Crerpa 100uF C43 Philips Semiconductors Usermanual 25 SAA7709H N1B 8 1 3 Power on off mute The block diagram of the power on mute POM circuit is depicted in figure 8 4 COMPARATOR lt 500 mV Fig 8 4 Power on mute block diagram Power on Mute pin 7 To avoid any uncontrolled noise at the audio outputs after power on off of the IC the internal reference current source of the D A converter is controlled The capacitor on the POM pin C32 determines the switch on timing of this current See figure 8 5 At power on the the switch S is closed and the current out of the POM pin Ipoy is 16 WA the capacitor Cpom gets charged by Iron and the voltage at the POM pin Vpom increases linearly until Vpoy 0 5 V at this point the comparator is triggered and switch S is opened As a result Ipoy becomes 112 uA and Vpom increases fast until it reaches VDDA As a result of this POM control the Vout AC at the DAC outputs in dB increases almost dB linear from 100 dBFS till 0 dBFS At time tyom the DAC output Vout AC 25 dBFS before this output voltage is reached the chip must be resetted After the reset the chip comes automatically in the idle mode via the DSP program see also chapter 9 This DSP program sets the outputs of the digital upsampling filters to digital silence and therefore the AC output curre
5. SZ gt eure Foe 223225 5 353dadar Sao2Z24 rFrF4 400005 VVVVsV VV VR ag ggggag Ansel_sel1 2 dif_sw1 AD1 a7 em gt 5 E ar gnd_sel1 7 3 ansel_sel2 2 dif_sw2 AD2 a7 oa p 2 gnd sel2 El ansel_sel3 E dif_sw3 AD3 ri a 3 a gnd_sel3 3 A ansel_sel4 2 dif_sw4 ADA 3 ai 5 E dra gnd_sel4 2 3 GND_SEL1 bits 12 and 13 of register 0FFA selects between internal ground midref or an external ground CD_GNDL NAV_GND or PHONE_GND DIF_SW1 bit 1 of register 0FF9 selects a High Common Mode or Fully Differential input mode For ADC2 ANSEL2 bits 3 4 and 5 of register 0FFA selects which input source is connected GND_SEL2 bits 14 and 15 of register 0FFA selects between internal ground midref or an external ground CD_GNDL NAV_GND or PHONE_GND DIF_SW2 bit 2 of register 0FF9 selects a High Common Mode or Fully Differential input mode Philips Semiconductors Usermanual 40 SAA7709H N1B For ADC3 ANSEL3 bits 6 7 and 8 of register 0FFA selects which input source is connected GND_SEL3 bits 16 and 17 of register 0FFA selects between internal ground midref or an external ground CD_GNDL NAV_GND or PHONE_GND DIF_SW3 bit 3 of register 0FF9 selects a High Common Mode or Fully Differential input mode For ADC4 ANSEL4 bits 9 10 and 11 of register 0FFA selects which input source is connected GND_SEL4 bits 18 and 19 of registe
6. sliding stereo etc Dolby B tape noise reduction and the audio controls volume balance fader and tone Some functions have been implemented in hardware stereo decoder RDS decoding and IAC for FM_MPX and are not freely programmable Digital audio signals from external sources with the Philips IS and the LSB 16 18 20 and 24 bit justified format or SPDIF format up to Fs 48 kHz are accepted There are four independent analogue output channels The SAA7709H N103B is the final version All audio and radio software features are in the N103 romcode available The hardware of the IC between the N102B and N103B are the same The DSP contains a basic program which enables a set with AM FM reception compressor function for all audio modes on the primary channel channel 1 and fader balance control A hardware 5 band per channel parametric equalizer is also implemented With some restrictions also 2 different stereo channels can be processed 3 Hardware software features 3 1 Hardware features e 1 Bit stream 1st order Sigma Delta A D converter with anti aliasing broadband input filter e 4 Bit stream 3rd order Sigma Delta A D converters with anti aliasing broadband input filter e 4 Bitstream D A converters with 128 fold oversampling and noise shaping e 4 channel 5 band IC controlled parametric equalizer e Integrated semi digital filter no external post filter required for D A e A stereo I S output with 256 Fs clock for connection to an
7. TAPE R 1 FM MPX 56k 220nF Doo 12 FM i 1 8kQ op 330pF LEVEL 27k Q 220pF 100K 7 77 VREFAD e 18 am RDS demodulator XTAL 7 De OSC_OUT CD DATA 45 Foon 11 2896 MHz BLM21A10 18pF 18pF 10k2 SPDIF 1 5V dig 100nF 100pF 752 3 3V ana P DSP FLAGS 41 DSP 104 SCL 26 21 DSP 105 DSP 106 SDA 16 DSP 107 DSP RESET 14 DSP 108 Digital I O 74 5V ana 9100 T1 4 7kQ VDDA 10 CE 22uF a VSSA VREFDA 12 2247 TI 100pF 15 4 FL TT 10nF pF 1002 FR 1pF 10kQ Pa lora 1pF TLF 10k2 cae RR uF 100 Q Lior 10k Q ws Dac 18 DATA Dadl 9 CLK_DAC 20 Fs_sys 17 34 1IS OUT1 35 1IS OUT2 30 lIS CLK 33 IIS WS 31 IIS IN1 32 11S IN2 MICRO CONTROL MICRO CONTROL TC TC 224 10k2 5V dig
8. TEA6840 allows for a fast RDS update sequence of about 7ms The IC has an RDS update timing sequencer on board which performs the following tasks e Mute of the FM MPX signal with a slope of 1 ms for fade out and fade in of the MPX signal e Tuning to the alternative frequency and back to the main frequency e generating of two timing signals AFHold and AFSample to control the CDSP Figure 8 33 shows the interface diagram between Tuner and CDSP and figure 8 34 the timing diagram The TEA6840 delivers two MPX signals to the CDSP one with Mute the FMMPX and one without Mute the RDSMPX The RDSMPX signal enables the possibility to take also a Noise sample X NOISFLT_U from the alternative frequency This is realised by switching the input of the A D converter from FMMPX to RDSMPX during the RDS update with SEL_FR An internal mute in the CDSP is initiated with AFSample to suppress the modulation from the RDSMPX signal Philips Semiconductors Usermanual 66 SAA7709H N1B AM FM Level SAA7709H TEA6840 RDSMPX no mute _ NS AFHold IIC bus Micro Controller SEL_FR DSP_IN2 DSP_IN1 DSP_OUT2 Figure 8 33 Interface diagram between Tuner TEA6840 and CDSP AFHold FMMPX AFSample 2 11 Te Freeze Sensor signals internal Mute cose iC o yo ns q2ms a 7ms gt Figure 8 34 Timing diagram RDS update with TEA6840 Remark Due to the fast update the all
9. case of switching ON the MPX IAC should not increase significantly adjustment of IAC parameter feed_forward Use no ISN Modulation fmod 1 kHz deviation 75 kHz Choose the RF voltage amplitude so that some trigger pulses occur around the zero crossings of the audio signal Adjust feed_forward to the value at which the number of unwanted trigger pulses around the peaks of the audio signal is about the same as the number around the zero crossings adjustment of IAC parameters Suppression and MPX_delay Use the ISN and create interfering pulses Make the RF voltage so low that the IAC is still sensitive for pulses At lower voltages the IAC will be too sensitive for pulses because of the noise At this RF voltage the suppression time is shortest so the timing of the beginning and the end of the suppression period is most critical Set Suppression and MPX_delay to maximum The beginning of an interference pulse or maybe the whole pulse is suppressed now Reduce MPX_delay to the value at which the beginning of the pulse is still just eliminated Then reduce Suppression so much that the tail of the pulse is just suppressed well The adjustment of Suppression and MPX_delay can be done by listening 2 Optimisation of the Dynamic IAC The Level IAC function should remain switched OFF MPX IAC adjusted and switched ON adjustment of IAC parameter dyn_threshold Use no ISN Set the RF voltage to 200 uV Modulation fmod 10 kHz deviation 22 5 kH
10. data sheet e to create a filter for the FM MPX input with a cut off frequency gt 250 kHz This filter is realised with R19 1 8 kQ 10 and C21 270 pF 10 in combination with the FM_MPX input resistance of gt 48 kQ this results in a cut off frequency of 340 kHz 20 Remarks a The source resistance is not taken into account because this Rsource lt lt 27K otherwise the cut off frequency is affected b The input resistance of the CDSP gt 48 kQ is taken into account for the cut off frequency c Concerning C22 and C23 X7R SMD capacitors are not allowed because they show some voltage dependency which causes extra distortion therefore NPO SMD capacitors are recommended The capacitor C22 is applied to block any DC content of the incoming signal The capacitor C22 forms with the Rin of the CDSP a high pass filter which must fulfil the following requirements maximum leakage current lt 0 5 uA otherwise the specified dynamic range of the A D convertor is limited by an offset voltage lleak RiNmax Vottset 0 5 HA GOK 30 mV offset in case of 200 mV input sensitivity compared to 1 229 Vrms input voltage this results in a loss of dynamic range of 0 2 dB the cut off frequency lt 5 Hz a higher fc limits the maximum channel separation of FM due to phase shift at 19 kHz In the CDSP application we use C22 1 uF MKT during a RDS update the switch is pointed to the FM_RDS pin For a fast update it is nec
11. e RDS_DATA Raw RDS bit stream generated by the demodulator detection of a positive going edge on the RDCL input signal The data output is changing 100 ms 1 8 of the RDS_BCK period after the falling edge of RDS_BCK This allows for external receivers of the RDS data to clock the data on the RDS_BCK signal as well as on its inverse Buffered raw RDS output mode rds_clkin 1 rds_clkout 0 e RDS_CLK Burst clock generated by the mP Bursts of 16 clock cycles are expected The average time between bursts 13 5 ms e RDS_DATA Bursts of 16 raw RDS bits are put out under control of the burst clock input After a data burst this output is high It is pulled low when 16 new bits are available and a new clock burst is awaited The microprocessor has to monitor this line at least every 13 4 ms 8 7 4 Direct RDS Timing of Clock and Data signals in DAVD mode dac0 1 dac1 1 RDS decoder bypass mode The timing of the Clock and Data output is derived from the incoming data signal Under stable conditions the data will remain valid for 400 ms after the clock transition The timing of the data change is 100 ms before a positive clock change This timing is suited for positive as well as negative triggered interrupts on a microprocessor The RDS timing is shown in Fig 8 28 During poor reception it is possible that faults in phase occur then the duty cycle of the clock and data signals will vary from minimum 0 5 times to a maximum of 1 5 times the
12. input is single ended Philips Semiconductors Usermanual 47 SAA7709H N1B PHONE Phone PHONE_GND VREFAD NAV Navigation H H o NAV_GND Fig 8 22 Phone and Navigation inputs The input circuit diagram as given in fig 8 22 shows that both the Phone and Navigation input have a separate ground input pin In this case it is assumed that the ground wire Phone input source is connected with the Phone_GND pin in order to realise a differential input for the Navigation input it is assumed that the NAV_GND pin is not used single ended input and therefor connected via C5 to ground It is of course possible to connect the ground wire of the Navigation input source with the NAV_GND pin similar as for the Phone input if desired The external components of the Phone and Navigation inputs have the following functions e Adapt the source signal amplitude to the maximum input voltage of the CDSP e Input filtering Input sensitivity of the Phone input In the CDSP application we assume that the external phone source delivers a signal of 1 Vrms maximum The full scale input level 0 dB of the A D convertor is 660 mVrms the phone source voltage has to be attenuated accordingly Philips Semiconductors Usermanual 48 SAA7709H N1B This results in the equivalent circuit diagram for determining the overall gain of the Phone input According the diagram below Full scale 0 66 Vrms In the CDSP ap
13. is transmitted by FM radio broadcasting The operational functions of the demodulator and decoder are in accordance with EBU specification EN 50067 The RDS function processes the RDS signal that is frequency multiplexed in the stereo multiplex signal to recover the information transmitted over the RDS data channel This processing consists of band pass filtering RDS demodulation and RDS RBDS decoding Under control of IIC bit rds_clkin an internal buffer can be used to read out the raw RDS stream in bursts of 16 bits With the IIC bit rds_clkout the RDS clock can be enabled or switched off The RDS band signal level in IIC bits RDS_DET of register IIC_RDS_DETection supports fast RDS presence detection The RDS band pass filter discards the audio content from the input signal and reduces the bandwidth The RDS band signal level detector removes a possible ARI signal from the RDS band pass filter output and measures the level of the remaining signal The RDS demodulator regenerates the raw RDS bit stream bit rate 1187 5 Hz from the modulated RDS signal in two steps The first step is the demodulation of the Double Side Band Suppressed Carrier signal around 57 kHz into a baseband signal by carrier extraction and down mixing The second step is the BPSK demodulation of the biphase coded baseband signal by clock extraction and correlation Philips Semiconductors Usermanual 53 SAA7709H N1B RDS_CLK RDS_DATA rds_clkout
14. l F i a Fa 2 a i ei i i Zol IOo E E EN Passe cm a a aa i na a AAA I I I I be O ja a eee AAA A AS A e ae L eee ii L PERNE E ANRE T i i i 21 N EE i i i po al i i i i Sa af Pr I I I I sk zz zH Ez z0 zik Frage amay rllz Fig 8 27 Detailed frequency response curve RDS channel In case of FM stereo reception the clock of the total chip is locked to the stereo pilot 19 kHz multiple In case of FM mono the DCS loop keeps the DCS clock around the same 19 kHz multiple In all other cases like AM reception or tape the DCS circuit has to be set in a preset position by means of the locked_preset bit of the IIC_DCS control register Under these conditions the RDS system is always clocked by the DCS clock in a 38 kHz 4 9 5 kHz based sequence Philips Semiconductors Usermanual 55 SAA7709H N1B 8 7 3 Direct RDS Inputs outputs in DAVD mode dac0 1 dac1 1 RDS decoder bypass mode Apart from control inputs and data outputs via IIC the following inputs and outputs are related to the RDS function see Fig 8 25 e Unbuffered raw RDS output mode rds_clkin 0 rds_clkout 1 RDS_CLK Clock of the raw RDS bit stream extracted from the biphase coded baseband signal by the RDS demodulator Clock period 1 1875 kHz 8192 clock cycles of the DCS system clock 50 duty cycle The positive edge can be used to sample the RDS_DATA output with
15. lt 0 2 30 AM lt 0 1 4 3 Analogue tape input Frequency response 3 dB 20 Hz 18 kHz Typ S N at 1 kHz 0 ref dB 84 dB Typ THD N 1 kHz 0 55 Vrms 85 dB Typ channel separation 1 kHz 65 dB RDS traffic information reception from radio signals in this mode is possible the decoder is still operating 4 4 Analogue CD input Frequency response 3 dB 20 Hz 18 kHz Typ S N at 1 kHz 0 GB ref 84 dB Typ THD N 1 kHz 0 5 Vrms 85 dB Typ channel separation 1 kHz 65 dB RDS traffic information reception from radio signals in this mode is possible the decoder is still operating 4 5 RDS reception Min nearby selectivity 61 dB neighbour ch at 200 kHz Min pilot attenuation 50 dB Philips Semiconductors Usermanual 10 SAA7709H N1B 4 6 CD 125 SPDIF input The performance of these input signals is actually limited by the DAC output as described in chapter 4 7 The digital CD input can be used as an alternative input for the analogue CD RDS traffic information reception from radio signals in this mode is possible the decoder is still operating 4 7 Audio output performance Typ output level Bandwidth fs 44 1 kHz 3dB Typ S N Typ output noise Typ THD N 1 kHz 0 dB Typ Dynamic Range 1 kHz 60 dB 4 8 Audio processing 1 Vrms 20 Hz 22 kHz 105 dBA 3 uV A weighted 90 dB 97 dBA 4 8 1 Volume balance fader tone loudness dynamic bass boost control figures c
16. reaches 90 of its stationary value after less than 14 ms An ARI signal with maximal signal content away from 57 kHz SK DK BK area F and 12 Hz carrier frequency versus filter centre frequency skew and a deviation of 7 5 kHz causes a wiggling detector output with maxima below 0 14 If a threshold of 0 18 is used to detect RDS presence detection takes 12 6 ms for an RDS deviation of 0 8 kHz and 3 4 ms for an RDS deviation of 2 0 kHz Fig 8 32 shows various detector output transients after the selection of the input stereo MPX signals containing RDS or ARI signals AAA pen 00 N ad peA nan par ee eye a 2 Hr ADS pork ack i WHe ROS sth fom top lo bellos all seo condom bagga ard all ons rradulliore ar an rer os SPCR pial de ee a ie ty a ar re et Cw TATA To TET lal hg ge a R A A aT a e nyu BRE AR wilh SH OK ond BE ura EF Fig 8 32 RDS output for various signals The noise in the RDS band adds to the detector output Consider the case of a nominal RDS deviation of 2 0 kHz and white noise measured over the band of the RDS main lobe i e between 54 6 kHz and 59 4 kHz A noise power of 25 dB below the RDS power level adds 0 043 to the detector output Every 6 dB more noise doubles the noise contribution to the detector output A threshold for RDS presence indication can be made dependent on the noise level measured with the wide band or narrow band noise detecto
17. standard clock periods Normally faults in phase do not occur on a cyclic basis ADS_DATA ADS_ELOCK Fig 8 28 RDS timing in the direct output mode Philips Semiconductors Usermanual 56 SAA7709H N1B 8 7 5 Buffering of RDS data The repetition of the RDS data is around the 1187 Hz This results in an interrupt on the microprocessor for every 842 uS In a second mode the RDS interface has a double 16 bit buffer 8 7 6 Buffer interface The RDS interface buffers 16 data bits Every time 16 bits are received the data line in pulled down and the buffer is overwritten The control microprocessor has to monitor the data line in at most every 13 5 msec This mode is selected by setting the rds_clkin IIC bit to 1 and rds_clkout to 0 See IIC_RDS_ConTRol register 6005 In Fig 8 29 the interface signals from the RDS demodulator and the microcomputer in buffer mode are shown When the buffer is filled with 16 bit the data line is pulled down The data line will remain low until reading of the buffer is started by pulling down the clock line The first bit is clocked out After 16 clock pulses the reading of the buffer is ready and the data line is set high until the buffer is filled again The microprocessor stops communication by pulling the line high The data is written out just after the clock high low transition The data is valid when the clock is high When a new 16 bit buffer is filled before the other buffe
18. stereo pilot FM audio filter The purpose of the FM audio filter is to set the audio bandwidth in FM mode independent from the Philips Semiconductors Usermanual 19 SAA7709H N1B other modes Stereo detection The purpose of the stereo detector is to indicate the presence of a pilot tone and that the stereo decoder is in lock Noise filter The noise level is detected in a band from 60 kHz till 120 kHz with an envelope detector see data sheet The noise level is used as adjacent channel information for the controller and for the FM dynamic signal processing RDS updates This function offers the following features Pause detection The purpose of the pause detection is to search for a pause in the FM signal A pause is detected when the FM signal is below a pre defined level for a certain amount of time The output of the pause detector is the DSP_104 pin pin 41 High indicates pause Mute The purpose of the mute is to mute the FM signal that goes to the audio processing block This mute is activated by the external control pin DSP_IO1 pin 38 Low is mute Hold function The purpose of the hold function is to prevent that the information retrieved during an RDS update can disturb the filters in the FM signal processing block The hold function is activated by the external control pin DSP_IO1 pin 38 Low is hold Freeze function The purpose of the freeze function is to freeze the level noise and
19. synchronized and a new block is DACO 0 DAC1 0 received every 26 bits the actual RDS RBDS information of the last two blocks is available with every new received block approx every 21 9ms mode DAVB Fast Pl search mode During synchronization search and if a new A or C DACO 1 DAC1 0 lock is received the actual RDS RBDS information of this or the last two A or C blocks respectively is available with every new received A or C block If he decoder is synchronized the standard output mode is active mode DAVC Reduced data request output mode If the decoder is synchronized and two DACO 0 DAC1 1 new blocks are received every 52 bits the actual RDS RBDS information of he last two blocks is available with every two new received blocks approx every 43 8ms mode DAVD Decoder bypassed mode If this mode is selected then the OutMux output of DACO 1 DAC1 1 the decoder is reset to low OutMux 0 Then the internal row buffer output is active and the decoder is bypassed The decoder provides data output of the block identification of the last and previously processed blocks the RDS RBDS information words and error detection correction status of the last two blocks as well as general decoder status information In addition the decoder output is controlled indirectly by the data request from the external main controller The decoder receives a data overflow DOFL signal controlled by the IIC bus registe
20. to be connected to the main ground plane with sufficient vias Do not use the small ground plane under the chip for the other ground pins these have to be directly connected to the main ground plane Oscillator circuit Mount the oscillator peripheral components XTAL Cx1 and Cx2 see figure 8 25 as close as possible to the CDSP chip The oscillator supply is separately filtered with components a capacitor of 100nF and a choke BLM21A10 see appendix 1 Philips Semiconductors Usermanual 72 SAA7709H N1B 7 filtering DAC outputs On all four analogue outputs the same filtering are used This is described in figure 8 1 first order RC filtering of the analogue output signals will be done with a 100 Ohm resistor and a 10nF capacitor Furthermore it is important to separate the supply of the digital circuitry from the supply of the analogue circuitry In case an analogue 5V supply is used for generating the 3 3V for VDDA2 supply of FSDAC it is recommended to add a 100 uH coil in series with the 5V analogue supply line 8 14 Changing the clock frequency of the DSP By default the DSP in the SAA7709H are running on a frequency of DSP clock frequency 69 854 MHz The EMI behaviour of the SAA7709H is very good and in normal cases there is no interference with FM reception however if desired it is possible to slightly increase the clock frequency of the DSP by changing the divide factor of the PLL that generates the DSP clock s
21. 0 NICE I2C interface Second processor extension function Digital subwoofer and center output External DAC output subwoofer X tal oscillator circuit EMC SAA7709H application Changing the clock frequency of the DSP 8 14 1 Procedure for increasing the clock frequency of the DSP APPENDIX 1 APPLICATION DIAGRAM 66 68 69 69 69 70 72 73 73 74 Philips Semiconductors Usermanual 6 SAA7709H N1B 1 Introduction Digital techniques have been widely accepted in the audio world including in the Car Radio The CD was the first example nowadays the digitisation of the Car Radio is a logical continuation of this trend Furthermore in the Car Radio world there is a growing demand not only for a good radio perception but also for a better sound quality People want the sound of their living room in their vehicle This led not only to the digitisation of analogue designs of the Car Radio but also to the incorporation of a customised DSP on board of a Car Radio I C delivering many possibilities for sound quality improvement Philips Semiconductors Usermanual 7 SAA7709H N1B 2 General description The CDSP chip performs all the signal functions in front of the power amplifiers and behind the AM and FM_MPX demodulation of a car radio or the tape input These functions are interference absorption stereo decoding RDS demodulation and decoding FM and AM weak signal processing soft mute
22. AD would exceed the rail to rail levels far before the 0 dBFS input level is reached at the DSP1 input TUNER OUTPUT VOLTAGE mV Gain dB volfm I2C O dBFS input level mV of Typical at Af 22 5 kHz bits FM MPX and or FM RDS Input 11 6 via stereo decoder to DSP1 impedance Ohms Table 8 1 FM input sensitivity and impedance Philips Semiconductors Usermanual 33 SAA7709H N1B 8 3 3 FM IAC The Interference Absorption Circuit IAC detects and eliminates audible clicks caused by impulsive interference on FM reception The block diagram of the IAC is depicted in figure 8 9 DYNAMIC IAC Deviation IAC on off detector dyn_threshold gt f en_dyn_iac MPX_delay MPX input MPX IAC A a Monostable Multivibrator Threshold Suppression l FM LEVEL 1 High gn Pass Monostable Monostable Multivibrator Multivibrator LEVEL IAC iac_stretch iac_feed_forward Fig 8 9 Block diagram of IAC Philips Semiconductors Usermanual 34 SAA7709H N1B The IAC consists of three circuits MPX IAC e Level IAC e Dynamic IAC The input signal of the MPX IAC circuit is the MPX signal derived from the decimated output signal of the A D convertor The MPX signal is fed to a delay circuit followed a gate switch This gate is activated by the interference detector which consists of a feed forward path an AGC circuit a comparator and a monostable
23. Convertors The Analog to Digital Convertors are supplied via the VDDAAD pin In order to decrease the groundbounce in the chip and to increase the analog performance will increase a choke BLM21A10 must be added in the supply line VDDAAD It s important that no decoupling capacitor is connected to the VDDAAD pin see appendix 1 Supply filtering peripheral supply The peripheral I O circuitry is supplied via VDDQ1 VDDQ2 and VDDQ3 In order to suppress interferences a 10 Ohm series resistor and a decoupling capacitor of 22 nF are added to these pins see appendix 1 Main ground plane The pinning of the CDSP chip has been chosen in such a way that the lay out is possible with a double sided PCB It is recommended to create a ground plane on the non SMD side of the PCB This main ground plane provides a low inductance ground return for the power supply and signal currents This plane act as an equipotential point for the digital as well as for the analogue parts of the CDSP circuitry The EMC critical peripheral components should be above the plane Ground plane under the CDSP chip It is recommended to provide a ground plane under the CDSP chip at the SMD side of the PCB The six ground pins VSSSx of the digital related signals and the oscillator ground pin VSS_OSC have to be connected directly to this plane in order to reduce the loop area of the digital supply this reduces the EMC emission and ground bounce This small ground plane has
24. From the audio characteristics the output level softmute the stereo image sliding stereo to mono and the audio frequency response high cut control are adapted The following functions are implemented e Softmute as a funtion of level and noise fast attack and recovery at level dips with a low repetition rate fast attack with slow recovery at dips with a high repetition rate or with a long duration fast attack and recovery at adjacent channel breakthrough e Stereo control sliding stereo as a function of level noise and multipath fast attack and recovery at level dips noise or multipath bursts with a low repetition rate fast attack with slow recovery at events with a high repetition rate or with a long duration e Audio frequency response control as a function of level noise and multipath fast attack and recovery at level dips noise or multipath bursts with a low repetition rate fast attack with slow recovery at events with a high repetition rate or with a long duration Adjustment of channel separation The purpose of this function is to compensate for the non flat frequency response around 38 kHz of the FM tuner which causes extra cross talk FM De emphasis filter and 19 kHz MPX filter The purpose of the de emphasis filter is to compensate the pre emphasized FM signal with a filter with a time constant of 50 us or 75 us The notch filter at 19 kHz is used to protect tweeters in high power applications from overload by the
25. M_MPX input at fast tuner search on FM_RDS input Must always be defined by application osc 68 crystal oscillator input crystal oscillator sense for gain control or forced input in slave mode CO IN peen IN wee EIN COTE CD_GNDR 71 By 12C switchable common mode reference pin to enable high common mode analogue input for the A CD_R input or a high common mode analogue input for all 2 ADs for right channel processing EN pc reg CD_GNDL 73 By 12C switchable common mode reference pin to enable high common mode analogue input for the a 8 CD_L input or a high common mode analogue input for all 2 ADs for left channel processing pes opema O Philips Semiconductors Usermanual 17 SAA7709H N1B 7 Functional description of the CDSP modes and functions Introduction The CDSP block diagram is depicted in figure 5 1 For a thorough description of the CDSP block diagram see the data sheet of the SAA7709H In this chapter a general overview is given of all modes and functions The CDSP can be set in several operation modes Each mode executes functions which are required for that particular mode furthermore the CDSP can process two independent sources simultaneously dual media modes note that NOT all combinations are possible for example AM mode and FM mode two digital input modes are only possible when the the external digital sources are synchronous and locked to each other The selection of a particular mode is software contro
26. SEL_FR o 11S_CLK El 11s_wS gt 11S_IN1 a 11_1N2 XTAL LEVEL ADC RDS LEVEL 125 SPDIF 12C demodulator osc Y y E SE lt lt Q 5 Z eg i 2 Z 9 z 3 Sp Taro o o 5 E 2 g a 5 2 8838 5 5 g g 82 8 O oc c Fig 5 2 Block diagram CDSP Philips Semiconductors Usermanual 13 SAA7709H N1B 6 Pinning diagram a lt 10 o y pa E E x x E i O S el 8 3 3 2 Z 3 3 6 5 a a 2 8 8 2 Q g e g 2 2 8 8 0 4 5 E 8 8 5 8 3 3 3 E 5 8 a X S amp 2 41 24 DSP_I04 SPDIF2 42 23 DSP_RESET VSSQ1 43 22 RTCB VDDQ1 44 21 SHTCB DSP_IO6 45 20 TSCAN CLK_DAC 46 19 VDDQ3 DATA_DAC 47 18 VSSQ3 WS_DAC 48 17 VDDD1 I FS_SYS 49 16 vsssi O DSP_I07 50 15 VSSS2 FLV 51 14 VDDD2 PM DSP_I08 52 13 VSSS3 PM FRV 53 12 vsss4 lt VREFDA 54 11 VSSS5 VDDDA 55 lt 10 VSSS6 VSSDA 56 9 AO Y RLV 5 8 SCL RRV 58 7 SDA POM 59 6 RDS_CLOCK NRV_GND 60 5 RDS_DATA NAV 61 4 SEL_FR PHONE_GND 62 3 VSS
27. USER MANUAL Hardware Part SAA7709H N1B Car Radio Digital Signal Processor Product Development CarDSP Mainstream Consumer Systems Nijmegen The Netherlands Version nr Author Status Date Report nr 4 0 G Laarhoven Accepted January 8 2002 RNB C 3272 20021 0005 REVISION HISTORY Manual version Date Remarks 1 0 March 31 2000 N101A initial version 2 0 August 11 2000 N102B initial version 3 0 October 30 2000 N103B initial version e Radio features adapted e RDS description adapted 4 0 January 4 2002 N1B final version e Fig 8 15 changed Resistor R16 R18 is added e Fig 8 23 changed Resistor R5 is added e Table 8 2 Timing unit RDS changed e Chapter 8 8 Chapter Interface with tuner TEA6840 is added Philips Semiconductors Usermanual 2 SAA7709H N1B Summary The purpose of this manual is to give all hardware application information of theSAA7709H being a Car Radio Digital Signal Processor CDSP needed to make a hardware application Also the audio and radio features are described The audio and software part of the SAA7709H N103B is decribed in a other document named Software Audio and Radio part SAA7709H N103B Before reading this report it is necessary to read first the data sheet of the SAA7709H In this manual all the pins are described with additional information on the input and output circuits The blockdiagram is given and all functions are explain
28. _OSC PHONE 63 2 OSC_IN CD LEVEL 64 1 OSC_OUT FM_MPX a ES ES E E E E ES E ES o o 0 a 8 a gt A 2 Q a z 2 a 4 8 a z i w W Gi 9 a 9 z 2 2 mj x x ho A A E e e a E Fig 6 1 Pinning diagram Philips Semiconductors Usermanual 14 SAA7709H N1B 6 1 Pin description Table 1 Pin list SAA7709H DEIA IO LEVEL 2 FM AM level input pin Via this pin the level of the FM signal or level of the AM signal is fed to the Es The level information is used in the DSP for signal correction PHONE_GND 4 By 12C switchable common mode reference pin to enable an arbitrary high common mode analogue input 5 pat of common mode navigation signal NAV_GND 6 By 12C switchable common mode reference pin to enable an arbitrary high common mode analogue input 7 Power on Mute of the FSDAC Timing is determined by an external capacitor and the internal current sources fv CTI CONO pavistesoiimeasensnersone Philips Semiconductors Usermanual 15 SAA7709H N1B DSP_IO1 38 Digital in output 1 of the DSP core FO of the status register Input level must always be defined externally in the application DSP_102 39 Digital in output 2 of the DSP core F1 of the status register Input level must always be defined externally in the application DSP_RESET 42 Reset of the DSP core active low Philips Semiconductors Usermanual 16 SAA7709H N1B poo o semen O OOO AD input selection switch to enable high ohmic F
29. al 65 SAA7709H N1B If the decoder is synchronized and in any DAV mode except DAVD mode loss of synchronization is detected flywheel loss of synchronization resulting in restart of synchronization search In any DAV mode except DAVD mode if a reset caused by power on or voltage drop is detected Remark If the decoder is synchronized the DAVN signal is always activated after 21 9ms in DAVA or DAVB mode and after 43 8 ms in DAVC mode independent of valid or unvalid blocks are received The processed RDS RBDS data are available for IIC bus request for at least 20 ms after the DAVN signal was activated The DAVN signal is always automatically de activated high after 10 ms or almost immediately after the main controller has read the RDS RBDS status byte via IIC bus see DAVN timing The decoder ignores new processed RDS RBDS blocks if the DAVN signal is active or if data overflow occurs DOFL 1 The following tables show the block identification number and processed error status outputs of the decoder and how to interpret the output data RPS block See a Be Op lock BB o flock ______ O lock po lock fo lock E RBDS mode Ay invalid block E RDS mode RDS processed error correction EXB EXBO DESCRIPTION op oerorsdetected_ ______ o Hh ursterror of max 2 bits corrected H Pp ursterror of max 5 bits corrected A f uncorrectable block 8 8 Interface with Tuner TEA6840 NICE The tuner IC
30. alance functions are available in the primary and secondary channel Fader This function is only implemented for the primary channel The fader function controls the attenuation of either the front or rear channels while the other channels are kept constant The fader is controlled via the 12C bus Soft audio mute The soft audio mute function enables the user to generate a gradual mute or de mute function without Philips Semiconductors Usermanual 18 SAA7709H N1B undesired clicks The Soft Audio Mute is implemented as a linear ramp There is one SAM function for the primary channel and the subwoofer output the secondary channel has a separate SAM function Parametric Equaliser 2 sections of 2x5 bands each are available they can be used in the primary and or the secondary channel in the main audio program 7 2 FMmode This is the mode for FM reception and runs in the DSP The selected input is FM MPX or FM RDS The program in the FM mode offers the following functions Enhanced FM dynamic signal processing The FM dynamic signal processing adapts the FM audio characteristics depending on the quality of the received station As criterium to judge this quality the following parameters are used the level signal as a measure for the fieldstrength the multipath detector output as a measure for the multipath distortion the noise above 60 kHz of the MPX signal as a measure for the adjacent channel interference
31. and the Dynamic IAC functions are switched on after power on There are in total 9 different coefficients which will be described in short AGC bit 11 of IAC settings register In case the sensitivity and feed forward factor are out of range in a certain application the set point of the AGC can be shifted Threshold sensitivity offset bit 2 1 0 of IAC settings register Sets the threshold sensitivity of the comparator in the interference detector It also influences the amount of unwanted triggering feed_forward bit 5 4 3 of IAC settings register Determines the reduction of the detector sensitivity This mechanism prevents the detector from unwanted triggering at noise with modulation peaks Suppression bit 8 7 6 of IAC settings register Sets the duration of the pulse suppression after the detector has stopped sending trigger pulses MPX_delay bit 10 9 of IAC settings register Sets the delay time between 2 and 5 samples of Fs 304 kHz depending on the used front end of the car radio Philips Semiconductors Usermanual 35 SAA7709H N1B lev_iac_threshold bit 16 15 14 13 of IAC settings register Sets the sensitivity of the comparator in the ignition interference pulse detector It also influences the amount of unwanted triggering With the value 0000 the Level IAC function is switched OFF lev_iac_feed_forward bit 18 17 of IAC settings register This parameter allows to adjust for delay differences in t
32. art sending commands General timing requirements are Tdspres gt Tpower Tpom gt Tdspres TuPcomm gt Tdspres Figure 8 6 gives an overview of the several time constants Philips Semiconductors Usermanual 28 SAA7709H N1B Tpom 690 msec Vdspres Tdspres 68 92 msec uPcomm gt 150 msec Fig 8 6 Power up timing diagram to avoid clicks Philips Semiconductors Usermanual 29 SAA7709H N1B 8 2 AM FM signal quality processing Level pin 2 The basic circuit diagram of the level input is depicted in figure 8 7 Fig 8 7 Level input The level signal from the tuner is divided with resistors R4 and R5 in order to match the conversion range of the Level A D convertor to the tuner properties With R4 R5 and C4 a first order low pass filter is realised at the level input The cut off frequency of this filter is The low pass filter at the input of the FM level pin has two functions to avoid aliasing in the level A D convertor that means that frequency components of f gt 1 2 fSap lt 54 dB below the maximum input of the level A D convertor figure for S N for level A D convertor mentioned in data sheet tocreate a filter for the multipath detector with a cut off frequency of 34 kHz 20 These functions are realised with R4 27 kQ 10 R3 100 kQ 10 and C1 220 pF 10 The capacitor is connected to the ground plane Remarks a The source resistance
33. cks_counter If the counter value of the good_blocks_counter reaches the pre selected Max_Good_Blocks_Lose value MGBL lt 5 0 gt then good_blocks_counter and bad_blocks_counter are reset to zero But if the bad_blocks_counter reaches the pre selected Max_Bad_Blocks_Lose value MBBL lt 5 0 gt then new synchronization search bit by bit is started SYNC 0 and both counters are reset to zero The flywheel function is only activated if the decoder is synchronized The synchronization is held until the bad_blocks_counter reaches the pre selected Max_Bad_Blocks_Lose value loss of synchronization or an external forced start of new synchronization search NWSY 1 is performed The maximum values for the flywheel counters are both adjustable via IIC bus in a range of 0 to 63 8 7 10 Bit slip correction During poor reception situation phase shifts of one bit to the left or right 1 bit slip between the RDS RBDS clock and data may occur depending on the lock conditions of the demodulators clock regeneration If the decoder is synchronized and detects a bit slip BSLP 1 the synchronization is corrected by 1 0 or 1 bit via block detection on the respectively shifted expected new block 8 7 11 Data processing control The decoder provides different operating modes selectable by NWSY SYMO SYM1 DACO and DAC1 inputs via the external IIC bus The data processing control performs the pre selected operating modes and controls the requested output
34. culation starting after the first 26 bits have been received This bit by bit syndrome calculation is carried out until the first valid and error free block has been received Then the next expected block is calculated and syndrome calculation is done after the next 26 bits have been received The block span in which the second valid and expected block can be received is selectable via previously setting of the Max_Bad_Blocks_Gain MBBG lt 4 0 gt If the second received block is an invalid block then the bad_blocks_counter is incremented and again the new next expected block is calculated If the bad_blocks_counter value reaches the pre selected Max_Bad_Blocks_ Gain then the bit by bit search for the first block is started again If synchronization is found the synchronization status flag SYNC is set and available via IIC bus request The synchronization is held until the bad_blocks_counter value reaches the pre selected Max_Bad_Blocks_Lose value used for synchronization hold or an external restart of synchronization is performed NWSY 1 or power on reset 8 7 9 Flywheel for synchronization hold For a fast detection of loss of synchronization an internal flywheel is implemented Therefore one counter bad_blocks_counter checks the number of uncorrectable blocks and a second counter good_blocks_counter checks the number of error free or correctable blocks Error blocks increment the bad_blocks_counter and valid blocks increment the good_blo
35. e bus can be enabled disabled with bit 11 en_host_io of the Selector registers address 0FF9 by default the 125 outputs are disabled To minimise EMC the output has to be disabled default in case the output is not used 12S input outputs IIS_IN1 pin 31 IIS_IN2 pin 32 IIS_OUT1 pin34 IIS_OUT2 pin 35 IIS_CLK pin 30 IIS_WS pin33 8 11 Digital subwoofer and center output The CDSP offers an additional dual channel 18 bit digital output for the use of a subwoofer and center output A choose can be made between Ext DAC outputs IIS OUT1 and IIS OUT2 for the subwoofer and center output Similar as the second processor extension function the digital subwoofer output is capable of generating multiple output formats 12S and LSB justified data formats It is however not possible to select different data formats for the second processor and the subwoofer output As also mentioned for the second processor outputs the hardware of the bus can be enabled disabled with the en_host_io bit in register 0FF9 To minimise EMC the output has to be disabled default in case the output is not used 12S outputs 1IS_OUT1 pin 34 or IIS_OUT2 pin 35 IIS_CLK pin 30 and IIS_WS pin33 8 12 External DAC output subwoofer The SAA7709H consists over 125 outputs that could be connected to an external DAC with a own clock FS_SYS This external DAC could be applied to convert the digital subwoofer center signal to an audible signal
36. e max 2 bit errors increment the good_blocks_counter e mode SYNCC SYMO 0 SYM1 1 error correction of burst error max 5 bits blocks corrected are treated as valid blocks all other errors detected are treated as invalid blocks If synchronized error free and correctable max 5 bit errors increment the good_blocks_counter e mode SYNCD SYMO 1 SYM1 1 no error correction blocks detected as correctable are treated as invalid blocks if in synchronization search mode Internal bad_block_counter is always incremented even if correctable errors detected If synchronized error free blocks and correctable max 5 bit errors increment the good_blocks_counter Only uncorrectable blocks increment the bad_blocks counter 8 7 14 RBDS processing mode The decoder is suitable for receivers intended for the European RDS as well as for the USA RBDS standard If RBDS mode is selected RBDS 1 via the IIC bus the block detection and the error detection and correction are adjusted to RBDS data processing That is also E blocks are treated as valid blocks If RBDS is reset to zero 0 RDS mode is selected Philips Semiconductors Usermanual 64 SAA7709H N1B 8 7 15 Data available control modes The decoder provides three different RDS RBDS data output processing modes plus one decoder bypass mode selectable via the data available control mode inputs DACO and DAC1 Table 8 4 DAV modes mode DAVA Standard output mode If the decoder is
37. ed All necessary coefficient settings and tables for several selections are given The application diagram is explained in detail Philips Semiconductors Usermanual 3 SAA7709H N1B Table of Contents 1 INTRODUCTION 2 GENERAL DESCRIPTION 3 HARDWARE SOFTWARE FEATURES 3 1 Hardware features 3 2 Software features 4 QUICK REFERENCE SPECIFICATION 4 1 FM reception 4 2 AM reception 4 3 Analogue tape input 4 4 Analogue CD input 4 5 RDS reception 4 6 CD 12S SPDIF input 4 7 Audio output performance 4 8 Audio processing 4 8 1 Volume balance fader tone loudness dynamic bass boost control 4 8 2 Equalisation 5 BLOCK DIAGRAMS 5 1 Total block diagram 5 2 CDSP Block diagram 6 PINNING DIAGRAM 6 1 Pin description 7 FUNCTIONAL DESCRIPTION OF THE CDSP MODES AND FUNCTIONS 7 1 Audio processing 7 2 FM mode 7 4 General purpose tone generator 7 5 Tone sequencer 10 10 10 10 11 11 11 11 12 12 13 14 15 18 18 19 21 21 Philips Semiconductors Usermanual 4 SAA7709H N1B 7 6 Noise generator 7 7 MSS function 7 8 Radio Data System RDS function 7 9 Second processor extension function 8 HARDWARE APPLICATION OF THE CDSP 8 1 Audio processing in DSP 8 1 1 Analogue outputs pin 8 9 13 and 15 8 1 2 Internal reference voltage sources VREFDA pin 12 and VREFAD pin 77 8 1 2 3 Ref voltages for the AD convertors VDACP pin 75 and VDACN pin 76 8 1 3 Power on
38. ejection and thus eliminates ground noise it is required to use the external ground CD_GNDL and CD_GNDR pins The ground wire of the CD cable has a separate input at the CDSP in order to realise the required level of Common Mode Rejection Ratio The basic circuit diagram of the analogue CD input with High Common Mode inputs is depicted in figure 8 19a CDSP c6 Re ansel_sel1 col i cot o 1N F 2 gt dif_sw AD1 3 5 gt S sel cal 4 as SE pS 57y Y dseli CD cable __ pen 0 n Ground T a gna_se AS J R9 _ cio g ansel_sel2 co R HEY M i c8 2N o dif_sw 30 Ls a AD2 47 _ gt e F k Esas Vrefad att izj Fig 8 19a High Common Mode Analogue CD input Low pass filter The filtering of the incoming signal is a first order RC low pass filter realised with the resistors R6 R8 and the capacitor C9 for the Left channel input and with R7 R9 and the capacitor C10 for the Right channel input The cut off frequency fc of this filter Left channel is In the CDSP application we use R6 R7 8 2 kQ 10 R8 R9 10 kQ 10 In combination with the capacitor C9 C10 1 nF 10 this results in a cut off frequency fc 35 kHz 20 Philips Semiconductors Usermanual 45 SAA7709H N1B Variable gain The gain of the Left and Right input stages is adjustable and equals R8 R6 R8 and R9 R7 R9 respectiv
39. ely The 0 dB output level of the input stage opamps is 0 55 Vrms In the CDSP application we assume a level of 1 Vrms at the CD L and CD R application input It is recommended to change the resistor values if a different input gain is required such that the equivalent parallel resistance R3 R4 and R5 R6 remains lt 5 kQ for optimal CMRR characteristics Remarks e The capacitors C6 and C8 are applied to block any DC content of the incoming signal The capacitors C6 C8 forms with R6 R8 and R7 R9 a high pass filter The cut off frequency of this filter must be lt 15 Hz With R6 R7 8 2 kQ and R8 R9 10 kQ this means C2 C3 gt 583 nF e Capacitor C7 is applied to block the DC bias voltage at the CD GND pin in the CDSP application we use C7 47 uF 10 FULLY DIFFERENTIAL PLAYER CHANGER The basic circuit diagram of the analogue CD input with fully differential inputs is depicted in figure 8 19b C6 R6 CDL_POS a 0 sea aha 2 dif_sw1 AD1 3 gt O a L TA e e U lL o gnd self roL cto 1 2 ps 3 CDL_NEG cae R7 C12 Vrefad L R10 I C6 R6 CDR_POS L e o o A 2 dif_sw2 AD2 3 e
40. essary to determine the value of C23 much smaller then C22 In the application we use C23 330 pF MKT 8 3 2 FM input sensitivity selection The FM input sensitivity is designed for tuner front ends which deliver an output voltage in the range of 60 mV to 237 mV af 1 kHz 22 5 kHz deviation The input sensitivity can be changed in steps of 1 5 dB by means of the 6 volfm bits bits 7 12 of register 0FF8 The maximum gain of the FM MPX and FM RDS input circuit is 2 26 7 08 dB the switches in fig 8 8 are drawn in the 7 08 dB gain position In this gain position the input sensitivity is 60 mV at 22 5 kHz the full scale input level in this case is 340 mV 0 dBFS at the input of DSP1 corresponding with a deviation of 138 kHz The input impedance of the FM MPX and FM RDS input circuits depends on the setting of bit BO in case BO 0 the input impedance is R in case BO 1 the input impedance 1 189 R The value of the internal resistor R 50kQ typical Philips Semiconductors Usermanual 32 SAA7709H N1B The input sensitivity as function of the setting of the volfm bits is given in table 8 1 The input sensitivity of the FM RDS input can be set independent from the FM MPX input with the 6 volrds bits bits 1 6 of register 0FF8 table 8 1 also applies for the FM RDS input The gain settings 6 4 dB 15 4 dB are not applicable for the MPX inputs because signal levels in the OpAmp input stage in front of the
41. external DA converter e Limited dual media support allowing limited separate front seat and rear seat signal sources and separate control e Digital FM stereo decoder e Digital FM interference Suppression e RDS demodulation decoding via separate ADC with buffered output option on the demodulator and decoder I C accessible e Two mono CMRR or differential input high performance stages for voice signals from Phone and Navigation inputs via 3rd order Sigma Delta A D converter e Four switchable stereo CMRR or differential input stages CD walkman CD changer etc e Analogue single ended tape input e A 5120 X 32 DSP Program ROM a 1024 X 24 Data Ram and a 640 X 12 Coefficient RAM e Separate AM left and AM right inputs in case of use of external AM stereo decoder e One digital input I S or LSB justified format e Two digital inputs SPDIF format at Fs 48 kHz maximum e Audio output short circuit protected e 1C bus controlled including fast mode Philips Semiconductors Usermanual 8 SAA7709H N1B e A Phase Lock Loop derives the internal clock for the DSP from one common fundamental crystal oscillator e A Phase Lock Loop derives the internal clock for the DAC and other parts of the IC from a digital input Word Select e Combined AM FM level input e Relative high pin compatibility with SAA7704 SAA7705 SAA7706 SAA7708 incidental minor replacements needed e Low number of external components required e 40
42. generator The noise generator produces white noise the purpose of this function is automatic car aucoustic measurements The noise generator has an optional octave band filter 7 7 MSS function The purpose of the Music Search MSS function is to search for the next pause on a cassette tape The output of the MSS mode is the DSP_IO5 pin pin 26 This pin is High when the level of the input signals remain below a pre defined level for a certain amount of time 7 8 Radio Data System RDS function The selected input for this function is either FM RDS or FM MPX This function offers the following features Demodulation of the inaudible RDS information which is transmitted by FM broadcasting and is sent it to a suitable external decoder Also a internal RDS decoder is available to decode the demodulated RDS information RDS information is then available via 12 communication two tuners concept There are two different input pins from which the RDS information can be retrieved The demodulated RDS information is available by each bit or buffered by 16 bits 7 9 Second processor extension function This function offers the possibility of the addition of a second DSP which offers special more sophisticated features such as acoustic and room effects Philips Semiconductors Usermanual 22 SAA7709H N1B 8 Hardware application of the CDSP General In this chapter the external components are discussed sometimes in combinat
43. he signal paths from the FM antenna to the MPX mute namely via the FM level ADC and Level IAC detection and via the FM demodulator and MPX conversion and filtering These differences depend on the used frontend tuner in the car radio lev_iac_stretch bit 20 19 of IAC settings register Sets the duration of the pulse suppression after the FM level input has stopped exceeding the threshold level lev_dyn_threshold bit 22 21 of IAC settings register If enabled by the en_dyn_iac bit bit 23 of the IAC settings register this block will disable temporarily all IAC action in case the MPX signal exceeds a threshold deviation for a certain period of time A higher MPX IAC threshold means a lower overall trigger sensitivity a higher deviation feed forward factor causes a lower trigger sensitivity at a non zero FM deviation When the MPX IAC suppression stretch time is increased the suppression of the MPX signal will last longer after the last pulse detection Increasing the MPX delay causes that the suppression of the MPX signal begins and ends earlier relative to the MPX signal itself In case the sensitivity and feed forward factor are out of range in a certain application the set point of the AGC can be shifted with parameter AGC set point this decreases the overall sensitivity of the IAC circuit The more often and the longer the MPX signal is suppressed the more distortion of the audio signal will be the result In practice the best set
44. his method After synchronization has been found the error correction is always active depending on the pre selected error correction mode for synchronization node SYNCA SYNCD but cannot be carried out in every reception situation During synchronization search the error correction is disabled for detection of the first block and is enabled for processing of the second block depending on the pre selected error correction mode for synchronization mode SYNCA SYNCD The processed block data and the status of error correction are available for data request via IIC bus for the last two blocks Table 8 3 RDS processed error correction EXB1 EXBO DESCRIPTION Oo p hoerrorsdetected o pp kbursterrorofmax 2 bits corrected Ap kpursterrorofmax 5bitscorrected Processed blocks are characterized as uncorrectable under the following conditions e During synchronization search if the burst error for the second block is higher than allowed by the pre selected correction mode SYNCA SYNCD Philips Semiconductors Usermanual 62 SAA7709H N1B e After synchronization has been found if the burst error exceeds the correctable max 5 bit burst error or if errors are detected but error correction is not possible 8 7 8 Synchronization The decoder is synchronized if two valid blocks in a valid sequence are detected by the block detection The search for the first block is done by a bit by bit syndrome cal
45. ignal A decrease of the DSP clock frequency is possible but NOT allowed because this decreases the number of DSP program cycles below the number of required program cycles An increase of one of the DSP clock frequencies is of course only applicable if the second harmonic of the DSP clock interferes with the frequency of the selected FM station 8 14 1 Procedure for increasing the clock frequency of the DSP The DSP clock signal is generated by PLL1 the default divide factor of PLL1 is 198 this result in a clock frequency of 69 854 MHz The divide factor is set via bits 1 5 of the IC_DSP_CNTR register address 602F Philips Semiconductors Usermanual 73 SAA7709H N1B Appendix 1 Application diagram 3 3V di 3 3V ana 9 3 3V dig MICRO CONTROLLER 109 100pF 220nF 100 H BLM21A10 nav BLM21A10 H pas 22nF 100pF 100pF I H 220 2202 1004F ls ls Te apo 279 92 ope esa less fs s Jo PHONE_POS 2 a e o 39K 3 o o Q Diff Input 2200F 2 Sd pS 10 inF a a PHONE_NEG 3 9kQ 2 Q eoa 220nF LL Ss CDR_POS IMA 170 220nF 82 1nF 10k2 Differential Input oe 220nF 10k2 8 20 CDR_NEG SS A 72 CDL_POS ANALOG 220nF Y o 1nF O 1wa SOURCE e Differential Input h 5 i did SELECTOR Bo 1 20 CDL_NEG al UU CD_GNDL Do 220nF 8 2K aW 7 am T T gt AM L E o C 220nF 82K T Poo EJ AM R EY ott oo T a 220nF 82K Coop Ch ce TAPE L C 79 220nF 56k 2 Eo A AUX R
46. ignal varies and can even be zero Philips Semiconductors Usermanual 36 SAA7709H N1B 20 dB a RF GEN a INTERFERENCE RECEIVER El A 0 SIMULATING gt aena OS WITH NETWORK CDSP el PULSE IAC TRIGGER GENERATOR PULSE TO OSCILLOSCOPE Fig 8 10 IAC test setup INTERF SIM NETWORK metal box from RF gen to dummy ant from pulse gen Fig 8 11 ISN schematics DUMMY ANTENNA metal box from ISN to receiver Fig 8 12 Dummy antenna schematics Philips Semiconductors Usermanual 37 SAA7709H N1B Optimisation procedure IAC parameters Using the measurement set up in figure 8 10 the parameters of the IAC can be optimised all RF voltages measured at the input of the dummy antenna Signal to noise is relative to 22 5 kHz deviation The IAC characteristics can be adapted by means of the IAC settings registers This register contains the control bits that define the IAC parameters For monitoring the IAC trigger pulse at pin DSP 104 pin 41 bit IAC_trigger of the IAC settings register 0FFC should be set to 1 See also the datasheet of the SAA7709H The complete IAC function can be optimised in three steps 1 Optimise the MPX IAC 2 Optimise the Dynamic IAC 3 Optimise the Level IAC 1 Optimisation of the MPX IAC Figure 8 13 gives a graphical presentation of the effect that the MPX IAC parameters have on the interference
47. ion with the on chip input output circuits How to select specific inputs and operating modes is described in chapter 9 of this manual The external components are depicted in the CDSP application diagram which can be found in appendix 1 It must be stressed here that this application diagram is an example not the ultimate application diagram There is also an application diagram of the application board not in the usermanual and that contains much more components in order to optimise the EMC 8 1 Audio processing in DSP In this chapter the following hardware functions will be covered Analogue outputs D A convertors Voltage and current reference sources Power on off mute DSP reset 8 1 1 Analogue outputs pin 8 9 13 and 15 There are 4 analogue outputs namely those which make the outputs of the 4 bitstream DACs Front Left Right and Rear Left Right The D A convertors contain an internal filter so no external filter is required The basic block diagram of one analogue output is depicted in figure 8 1 Analog out 10 kOhm 10 nF Fig 8 1 Analogue output block diagram Philips Semiconductors Usermanual 23 SAA7709H N1B An analogue output consists mainly of a current to voltage convertor A current to voltage convertor is constructed by using the internal CMOS op amp and resistor as depicted in figure 8 1 The current from the Bistream DAC is converted into a voltage via Rint The full scale output
48. irements The cut off frequency of this filter is 1 c f 2 m Rn Cn with Ri R1 R2 4 oR R3 Rv Cl C2 and Cr C1 C2 For the CDSP application we use Philips Semiconductors Usermanual 50 SAA7709H N1B Input sensitivity of the Navigation input In the CDSP application we assume that the external phone source delivers a signal of 1 Vrms maximum The full scale input level 0 dB of the A D convertor is 660 mVrms the Navigation source voltage has to be attenuated accordingly see figure 8 23 VREFAD CDSP R5 Fig 8 23 Navigation input C13 R11 NAV Philips Semiconductors Usermanual 51 SAA7709H N1B 8 6 CD digital inputs I2S or SPDIF 8 6 1 General The DSP runs at the sample frequency of the selected digital input 12S or SPDIF supported sample frequencies are 44 1 kHz and 48 kHz sample frequency of 32 kHz is not supported The SAA7709H detects when the selected digital source becomes disconnected for some reason and as aresult DSP continues running at 44 1 kHz sampling frequency derived from Xtal oscillator 8 6 2 12S input 12S inputs CD CL pin 29 CD WS pin 27 and CD DATA pin 28 The digital inputs DIGIN is capable of handling multiple input formats 12S and LSB justified If the 12S input pins are not used they must be connected to ground as is indicated in the application diagram If they are used then in every input line a T fil
49. is not taken into account because this Rsource lt lt 127 KQO otherwise the cut off frequency is affected b The input resistance of the CDSP is not taken into account because this Rin is big 1 5 MQ min The conversion range of the A D convertor is from O V to VDDA1 see spec in the data sheet The voltage range of the FM level information has to be within this range The total voltage range of the level information has to be gt 1 2 VDDA1 to meet the minimum resolution Philips Semiconductors Usermanual 30 SAA7709H N1B 8 3 FM mode 8 3 1 FM input pins SEL_FR pin 61 The function of the SEL_FR pin is to select in FM mode between the FM MPX and FM RDS input This pin has an Schmitt trigger input and needs no external components because the applied signal is static OV or 3 3V Note that this pin is not used in the application diagram appendix 1 and therefor connected to ground FM MPX pin 1 and FM RDS pin 80 The basic circuit diagram of the FM MPX and FM RDS inputs is depicted in figure 8 8 MidRef Fig 8 8 FM MPX and FM RDS input Philips Semiconductors Usermanual 31 SAA7709H N1B The 1st order RC filter R19 and C21 at the input of the FM MPX pin has two functions to avoid aliasing in the A D convertor that means that frequency components of f gt 1 2 fsA D lt 83 dB below the maximum input of the A D convertor figure for S N for ADC1 and ADC2 convertors mentioned in
50. k output mode The functions which are realized in the decoder are described in detail within the next sections 8 7 6 RDS RBDS block detection The RDS RBDS block detection is always active For a received sequence of 26 data bits a valid block and corresponding offset are identified via syndrome calculation During synchronization search the syndrome is calculated with every new received data bit bit by bit for a received 26 bit sequence If the decoder is synchronized syndrome calculation is activated only after 26 data bits for each new block received Under RBDS reception situation besides the RDS block sequences with A B C C D offset also block sequences of 4 blocks with offset E may be received If the decoder detects an E block this block is marked in the block identification number BINr lt 2 0 gt and is available via IIC bus request In RBDS processing mode the block is signalled as valid E block and in RDS processing mode where only RDS blocks are expected signalled as invalid E block This information can be used by the main controller to detect E block sequences and identify RDS or RBDS transmitter stations 8 7 7 Error detection and correction The RDS RBDS error detection and correction recognizes and corrects potential transmission errors within a received block via parity check in consideration of the offset word of the expected block Burst errors with a maximum length of 5 bits are corrected with t
51. lled via the 12C bus and described in chapter 9 The required inputs for each mode can be selected by the analogue or digital source selectors which are software controlled via the 12C bus The source selection is also described in chapter 9 7 1 Audio processing All basic audio processing in the CDSP chip is performed by the integrated digital signal processor DSP The signal flow is more or less fixed and the functions are controlled by sending coefficient values to the appropriate places in the DSP processor coefficient memory via the 12C bus The functions of the Audio processing block are always executed independent of the mode The Audio processing block consists of two parts the audio processing functions for the primary channel and the audio processing functions for the secondary channel The following functions have been implemented Volume control The volume control function determines the output voltage of the CDSP The volume control is split into a gain and a attenuation section which acts equal for both channels The volume control contains also a prescaling which ensures that for the various input signals the same sound pressure level for a fixed volume setting can be obtained at the output of the CDSP The primary and secondary channel have independent volume control Balance The balance function controls the attenuation of either the left or the right channel while the other channel is kept constant Separate b
52. ms A safe value for Rbias is 1 Roias gt gt ae wo Rs Cp where is the oscillation frequency Rs is the resonator series resistance and C its parallel capacitance This means Rbias gt gt 8 KQ the value of 100 kQ is sufficiently large Philips Semiconductors Usermanual 71 SAA7709H N1B 8 13 EMC SAA7709H application In order to optimise the EMC behaviour of the SAA7709H device some measures are taken in the SAA7709H design 1 2 On chip decoupling capacitor this reduces the high frequency components of the supply currents Distributed clock the switching moments of the digital circuitry is spread in time Adjustable PLL frequency for the DSP this enables to change core frequency under microprocessor control in case FM reception is interfered by the SAA7709H emission Edge controlled digital outputs controlled rise and fall times this reduces the high frequency components that could interfere with radio reception To further optimise the EMC behaviour of the SAA7709H in a CDSP application some additional measures are required see also the SAA7709H application diagram Supply filtering digital circuitry DSP core The EMC most critical supply pins are VDDD1 and VDDD2 Via these pins the core is supplied so the bulk of the digital current is flowing through these pins To suppress interferences a choke BLM21A10 should be added in the supply line Supply filtering Analog to Digital
53. multipath values measured during an RDS update and to read them out after the update The freeze function is activated by the external control pin DSP_IO2 pin 39 Low is freeze Interference absorption circuit IAC The Interference Absorption Circuit IAC detects and suppresses ignition interference The characteristics of the IAC can be adapted to the properties of different FM tuners by means of the predefined coefficients in the IAC control register The values can be changed via the 12C bus On power on the nominal setting for a good performing IAC is selected all IAC control bits are set to their default value according the 12C hardware register definition Philips Semiconductors Usermanual 20 SAA7709H N1B 7 3 AM mono mode This is the mode for mono MW LW or SW reception the selected input is AM_R The program in the AM mono mode runs in the DSP and offers the following functions AM dynamic signal processing The AM dynamic signal processing adapts the AM audio characteristics depending on the quality of the received station As criterium to judge this quality the level signal as a measure for the fieldstrength is used From the audio characteristics the output level softmute and the audio frequency response high cut control are adapted The following functions are implemented e Soft mute as a function of level e Audio frequency response control as a function of level 6th order Low pass filter The p
54. multivibrator The interference detector analyses the high frequency content of the MPX signal and discriminates between interference pulses and other signals The mute switch interrupts the normal signal flow during mute switch activation the output is held at a constant level which is obtained from a LPF The MPX IAC circuit performs optimally in higher antenna voltage circumstances The input signal of the Level IAC circuit is the FM level signal This detector is added to the IAC circuit in order to further optimise the IAC performance at lower antenna voltage circumstances This detection circuit is complementary to the MPX IAC detection circuit The third IAC function is the Dynamic IAC circuit This function is intended to switch OFF the IAC completely at the moment that the MPX signal has a too high frequency deviation In case the frontend tuner has narrow IF filters a too high frequency deviation will result in AM modulation that could be interpreted by the IAC circuitry as interference caused by the car s engine By enabling the Dynamic IAC function this false triggering will be avoided The characteristics of the IAC can be adapted to the properties of different FM tuners by means of the predefined coefficients in the hardware 12C registers IAC settings The values can be changed via the 12C bus On power on the nominal setting for a good performing IAC is selected all IAC control bits set to there prefix value Note that the Level IAC
55. noise and MPX signal The procedure to optimise the MPX IAC parameters is described below Interference Puls C2 threshold sensitivity detected ee 1 2 m ao high audio modulation C5 MPX_delay C4 suppression stretch time C3 deviation feed_forward factor Fig 8 13 Graphical presentation MPX IAC parameters Switch OFF the Level IAC and Dynamic IAC functions set bits 13 14 15 16 and 12 of the IAC settings register O0FFC to 0 The optimisation of the MPX IAC can be done by listening optimise the parameters in the order as given below Note that the optimisation procedure is iterative in some circumstances it is needed to re adjust an already optimised parameter in order to get the overall optimal results Philips Semiconductors Usermanual 38 SAA7709H N1B adjustment of IAC parameter Threshold sensitivity Use no ISN No modulation Set feed_forward to minimum 0 00000 By decreasing the RF voltage the SNR decreases some sputtering noise can be heard now Changing Threshold causes unwanted trigger pulses After increasing the RF voltage which causes also SNR to increase the unwanted trigger pulses should disappear Increase of SNR due to unwanted trigger pulses has to be less than1 dB this requirement has to be met for any fieldstrength this can be verified by comparing the audible noise in case of MPX IAC switched ON with the audible noise in case of MPX IAC switched OFF The audible noise in
56. nt of the DAC s to 0 uA see also in the next chapter The time tpom as function of Cpom is tbom 0 03125 Coom Cpom in uF The time t during which the output voltage further increases from 25 dBFS to 0 dBFS is ts 0 8 tpom In the CDSP application we use Tpom 690 msec 20 Cpom 22 uF C32 Philips Semiconductors Usermanual 26 SAA7709H N1B DAC Vout AC dBFS Fig 8 5 Switch on timing DAC time sec time sec Philips Semiconductors Usermanual 27 SAA7709H N1B Power off plop suppression To avoid plops in a power amplifier the supply voltage of the analogue part of the D A converter and the op amps are fed by an external voltage regulation circuit R9 R10 and TR2 and an extra capacitor C31 as indicated in the application diagram During power off the output voltage will decrease gradually allowing the power amplifier some extra time to switch off without audible plops In addition the POM should be pulled to zero by the uProcessor before the power supply of the digital circuitry VDDDD1 VDDDD2 is below 2 2V Below this value the digital circuitry is undefined and can therefore cause extra undesirable clicks during power off 8 1 4 DSP Reset pin 42 The reset pin is active low and requires an external pull up resistor of 47 KQ Between the reset pin and the ground a capacitor should be connected to allow a proper switch on of the supply voltage The capacitor
57. of the RDS RBDS information Philips Semiconductors Usermanual 63 SAA7709H N1B 8 7 12 Restart of synchronization mode The restart synchronization NWSY control mode immediately terminates the actual synchronization and restarts a new synchronization search procedure NWSY 1 The NWSY flag is automatically reset after the restart of synchronization by the decoder This mode is required for a fast new synchronization on the RDS RBDS data from a new transmitter station if the tuning frequency is changed by the radio set Restart of synchronization search is furthermore automatically carried out if the internal flywheel signals a loss of synchronization 8 7 13 Error correction control mode for synchronization For error correction and identification of valid blocks during synchronization search as well as synchronization hold four different modes are selectable SYM1 SYMO e mode SYNCA SYMO 0 SYM1 0 no error correction blocks detected as correctable are treated as invalid blocks internal bad_blocks counter still incremented even if correctable errors detected If synchronized only error free blocks increment the good_blocks_counter All blocks except error free blocks increment the bad_blocks_counter e mode SYNCB SYMO 1 SYM1 0 error correction of burst error max 2 bits blocks corrected are treated as valid blocks all other errors detected are treated as invalid blocks If synchronized error free and correctabl
58. off mute 8 1 4 DSP Reset pin 42 8 2 AM FM signal quality processing 8 3 FM mode 8 3 1 FM input pins 8 3 2 FM input sensitivity selection 8 3 3 FM IAC 8 4 AM AUX Tape Phone NAV and CD_A inputs 8 4 1 AM inputs 8 4 1 1 AM inputs for AM mono mode and AM stereo mode with external decoder 8 4 2 Tape AUX input 8 4 3 Analogue CD input 8 5 Phone and Navigation inputs 8 6 CD digital inputs 128 or SPDIF 8 6 1 General 8 6 2 128 input 8 6 3 SPDIF input 8 7 Radio Data System RDS function 8 7 1 General description 8 7 3 Direct RDS Inputs outputs in DA VD mode dac0 1 dacl 1 RDS decoder bypass mode 8 7 4 Direct RDS Timing of Clock and Data signals in DAVD mode dac0 1 dacl 1 RDS decoder bypass mode 8 7 5 Buffering of RDS data 8 7 6 Buffer interface 8 7 3 Fast RDS detection with the rds band signal level detector 8 7 4 Bitslip 8 7 5 RDS RBDS decoder 8 7 6 RDS RBDS block detection 8 7 7 Error detection and correction 8 7 8 Synchronization 8 7 9 Flywheel for synchronization hold 8 7 10 Bit slip correction 8 7 11 Data processing control 8 7 12 Restart of synchronization mode 8 7 13 Error correction control mode for synchronization 8 7 14 RBDS processing mode 8 7 15 Data available control modes 8 7 16 Data output of RDS RBDS information 22 22 22 22 Philips Semiconductors Usermanual 5 SAA7709H N1B 8 8 8 9 8 10 8 11 8 12 8 13 8 13 8 14 Interface with Tuner TEA684
59. ount for default coefficient set Volume control range Balance attenuation range Left Right Fader attenuation range Front Rear 4 8 2 Equalisation Number of bands Filter order Centre frequency Gain control range Quality factor 66 dB gt 24 dB 0 dB gt 66 dB 0 dB gt 66 dB 20 bands 2nd order BP 20 Hz gt 18 kHz 30 dB gt 12 dB 0 01 gt 100 Philips Semiconductors Usermanual 11 SAA7709H N1B 5 Block diagrams 5 1 Total block diagram The total block diagram indicates a possible application in which the CDSP can be used PHONE NAV TAPE CD_A AUX SPDIF 2 External DAC uP RDS 120 Display Fig 5 1 Total block diagram Philips Semiconductors Usermanual 12 SAA7709H N1B 5 2 CDSP Block diagram Q a E Q PHONE SAA7709H FRONT LEFT PHONE_GND NAV NAV_GND STEREO ADC1 o rRichT E or g QUAD al CR_GNDR ul Lt gt DSP N FSDAC CD_L ANALOG w o REAR LEFT ra CD_GNDL SOURCE 2 Mea SELECTOR S a TAPE_L STEREO ADC2 o lt REAR RIGHT AM_R g __ Fs sys CLK_DAC AML J 5 AUX_R 9 WS_DAC AUX_L E DATA_DAC FM_MPX FM_RDS 11s_OUT1 11s_OUT2
60. owed settling time for the sensors is very short about 2ms In this time the sampled sensor values are not fully stabilised Therefor the values taken during an update for X LEVA_U and X NOISFLT can differ slightly 3dB from the real values The multipath value X MLTFLIM_U is not reliable after a jump from a frequency with high fieldstrength to a frequency with low fieldstrength Philips Semiconductors Usermanual 67 SAA7709H N1B 8 9 12C interface SCL pin 57 SDA pin 58 These two pins needs a RC filter in the input output lines for EMC reasons as is indicated in the application diagram The components are not critical so a tolerance of 20 is tolerable Philips Semiconductors Usermanual 68 SAA7709H N1B 8 10 Second processor extension function For communication with external processors delay lines or other 125 controllable devices a complete dual channel 18 bit output bus is implemented The CDSP is acting as the master transmitter and the external device has to be synchronised with the word select line As input for the processed data two data input lines have been implemented which are processed synchronously with the data output to the external processor This enables in total a feedback of two stereo audio channels To the external processor the DSP program should move data to the two Ext IIS DATA output registers and read it back from the two or four Ext IIS DATA 1 2 input registers The hardware of th
61. plication we use Ra 3 9 kQ 1 and Rb 10 KQ 10 Rv 1 MQ Also high impedance inputs are possible Ae E ia Rb Rv 2 Ra The overall input attenuation is The overall gain of the Phone input now matches the 1 Vrms phone source to the full scale input level of the A D convertor 0 66 Vrms CMMR The CMMR of the Phone input depends on the matching of the internal resistors and the external resistors R1 and R2 for this reason the maximum tolerance of these resistors must be 1 in order to achieve typical 50 dB CMMR as specified in the SAA7709H datasheet Input filtering The equivalent electrical diagram for determining the Phone input filtering is given in the figure below Low pass filter PHONE_GND Philips Semiconductors Usermanual 49 SAA7709H N1B With R1 R2 R3 and C3 a first order low pass filter is realised at the Phone input The cut off frequency of this filter is The 1st order filter at the Phone input is to avoid aliasing in the Audio A D convertor The requirements are not critical though Remark Concerning C59 a X7R SMD capacitor is not allowed because it shows some voltage dependency which causes extra distortion therefore NPO SMD capacitors are recommended High pass filter The capacitors C1 and C2 are applied to block any DC content of the incoming signal The capacitors C1 and C2 forms with R1 R2 and R3 a first order high pass filter but there are no critical requ
62. put of the ARI notch is shown in Fig 8 30 compares the detector filter characteristic with the spectra of RDS signals deviation 0 8 kHz with zero random one and toggled messages and the spectrum of an ARI signal deviation 7 5 kHz with worst case subcarriers SK DK BK area F and with a 12 Hz skew between the centre frequency of the filter and the ARI arrier Philips Semiconductors Usermanual 58 SAA7709H N1B aia NO J o o Jo J S5500 Fig 8 31 RDS detector filter versus various signal spectra The remaining signal is rectified and averaged with a first order low pass filter with a time constant of 6 75 ms The output of this filter is a measure for the signal and noise content in the RDS band The RDS band signal level in the IIC_RDS_DETector register is an 8 bit unsigned number between 0 and 0 996 For an RDS deviation below 4 kHz the 8 bit output RDS_DET is approximately detector output RDS_DET value RDS deviation in kHz 4 Philips Semiconductors Usermanual 59 SAA7709H N1B For all zero or all one messages the stationary detector output differs approximately 20 from this value For random messages the detector output varies between 10 bounds So RDS_DET 0 2 0 02 for a deviation of 0 8 kHz 0 5 0 05 for a deviation of 2 0 kHz in case of random messages For RDS deviations above 4 kHz the detector output saturates to the maximum value Simulations show that the detector output
63. r 8 7 4 Bitslip Phase jumps of the extracted RDS clock are detected and accumulated If the accumulated phase shift exceeds a threshold the RDS RBDS decoder is informed by the BSLP signal see Fig page If the RDS RBDS decoder detects a bitslip the RDS demodulator is informed by the BPSA signal This causes the accumulator of RDS clock phase shifts to be cleared Philips Semiconductors Usermanual 60 SAA7709H N1B 8 7 5 RDS RBDS decoder The RDS RBDS decoder handles the complete data processing and decoding of the continuously received serial RDS RBDS demodulator output data stream RDDA RDCL Different data processing modes are software controllable by the external main controller via IIC bus request All control signals are direct inputs to the decoder and are connected to the outputs of the IIC memory map interface Processed RDS RBDS data blocks with corresponding decoder status information are available via IIC bus Also the output signals of the decoder are direct outputs and are connected to the inputs of the IIC bus memory map interface Philips Semiconductors Usermanual 61 SAA7709H N1B As already mentioned the RDS RBDS decoder contains the following functions RDS and RBDS block detection Error detection and correction Fast block synchronization Synchronization control flywheel Mode control for RDS RBDS processing Different RDS RBDS block information output modes e g A C bloc
64. r interface This DOFL is set to high DOFL 1 if the decoder is synchronized and a new RDS RBDS block is received before the previously processed block was completely transmitted via IIC bus After detection of data overflow the interface registers are not updated until reset of the data overflow flag DOFL 0 by reading via the IIC bus or if NWSY 1 which results in start of new synchronization search SYNC 0 8 7 16 Data output of RDS RBDS information The decoded RDS RBDS block information and the current decoder status is available via the IIC bus For synchronization of data request between main controller and decoder the additional data available output DAVN is used If the decoder has processed new information for the main controller the data available signal DAVN is activated low under the following conditions During synchronization search in DAVB mode if a valid A or C block has been detected This mode can be used for fast search tuning detection and comparison of the PI code contained in the A and C blocks During synchronization search in any DAV mode except DAVD mode if two blocks in the correct sequence have been detected synchronization criterion fulfilled If the decoder is synchronized and in mode DAVA and DAVB a new block has been processed This mode is the If the decoder is synchronized If the decoder is synchronized and in DAVC mode two new blocks have been processed Philips Semiconductors Usermanu
65. r 0FFA selects between internal ground midref or an external ground CD_GNDL NAV_GND or PHONE_GND DIF_SW4 bit 4 of register 0FF9 selects a High Common Mode or Fully Differential input mode Notes 1 The input selection related 12C bits are automatically set by the Easy Programming source switching commands as described in chapter 9 0 3 2 The full scale input level of 660 mVrms at the CD_A AUX NAV PHONE Tape and AM inputs corresponds with an input level of 0 dBfs at the input of the DSP Philips Semiconductors Usermanual 41 SAA7709H N1B 8 4 1 AM inputs AM R AM_MONO and AM_L inputs pin 66 and pin 67 The function of the AM inputs can be either 1 Input for AM mono AM mono applied to AM_R AM_MONO input pin 2 Input for AM stereo with external AM stereo decoder AM left applied to AM L pin and AM right applied to AM_R AM_MONO input pin 8 4 1 1 AM inputs for AM mono mode and AM stereo mode with external decoder The basic circuit diagram for the AM L and AM R AM_MONO input for AM mono or AM stereo with external stereo decoder is depicted in figure 8 15 The use of the internal ground connection is required for the AM inputs VREFAD R16 R18 013 015 R11 R13 C14 C16 Ri gt 1 MQ J Fig 8 15 AM Left Right input In case of AM mono mode the AM AF output of the tuner has to be connected to the AM R AM input of the CarDSP this section deals with both the Left and Right inp
66. r D A convertors and buffers of the level A D convertor ADC 1 2 and ADC3 4 As filtering for the internal reference voltages a capacitor is added at the VREFDA pin In the CDSP application we use f gt 1 kHz Vripple 100 mV ripple rejection PSRR typ 60 dB CREFDA 22 uF C42 The VREFAD voltage is also used as a DC bias for the analogue AM Tape and CD inputs via 82 KQ 100 KQ resistors Due to the low output impedance of the buffer the crosstalk between the analogue inputs is lt 74 dB at DC the external 22 uF elco C12 is added to further improve the crosstalk rejection to lt 80 dB at 1 kHz The 47 nF capacitor C11 is added to remove high frequency noise on the midref voltage for the A D convertors Philips Semiconductors Usermanual 24 SAA7709H N1B 8 1 2 3 Ref voltages for the AD convertors VDACP pin 75 and VDACN pin 76 The block diagram of the reference voltages for the AD convertors is depicted in figure 8 3 VDDAAD 3 reference voltage ADC R 40 k reference voltage ADC Fig 8 3 Block diagram reference voltages AD convertors The voltages at the pins VDACP and VDACN1 are the reference voltages for the AD convertors for good performing AD s it is important that these reference voltages are clean The external 10 resistor R34 and 100 uF elco C43 filter the analogue supply voltage VDDAAD and are added to improve the power supply rejection ratio
67. r is read that buffer will be overwritten and the old data is lost ROS_DATA RDS CLOCK Aleck mady eae wading data Fig 8 29 Interface signals RDS demodulator and microcomputer The timing figures can be found in Table 8 2 Philips Semiconductors Usermanual 57 SAA7709H N1B Table 8 2 Timing of the RDS nominal clock frequency 1187 5 Z 8 01 RDS clock Msr Elocksetuptime Ho F F ps BO Mpr Periodictime b Be F ps BO Mhr Clock hightime R F 640 ps B04 Mir Clocklowtime PDFs SS Mdr Dataholdtime ho F F ps Bo Mwb Waittime U F F h BO Mpb Periodictime R F F h kio mb Clockhightime ft F F ks pu O t e s e Fed frequency Extern 8 13 RDS Clock 8 7 3 Fast RDS detection with the rds band signal level detector RDS presence detection after tuning to a new FM station using only the RDS demodulator decoder will take 130 mS The special for fast RDS detection designed RDS band signal level detector supports RDS presence detection in 10 ms after the front end is tuned to the selected frequency The band pass filtered input of the RDS demodulator is first passed through a notch filter to discard a possible ARI signal in the band 57 kHz 54 Hz 57 kHz 54 Hz The designed filter has 2 passbands with 3 dB frequencies at 55 4 kHz and 56 6 kHz and at 57 4 kHz and 58 6 kHz respectively The overall filter characteristic around 57 kHz from the output of the SRC to the out
68. st eliminated Then reduce iac_stretch so much that the tail of the pulse is just suppressed well The adjustment of iac_feed_forward and iac_stretch can be done by listening Philips Semiconductors Usermanual 39 SAA7709H N1B 8 4 AM AUX Tape Phone NAV and CD_A inputs From a hardware point of view the input circuits in front of the AD s are the same for these inputs First the internal input circuit common for the analogue inputs will be discussed here the specific external components for the different analogue inputs will be discussed in the following sections The internal input circuit common for the analogue inputs is given in figure 8 14 Fig 8 14 Input circuit CD_A Tape AM Phone NAV AUX The switches are controlled via hardware 12C registers with the following bits For ADC1 ANSEL1 bits 0 1 and 2 of register 0FFA selects which input source is connected a zZ 9 a W ww FL J MX 8 a
69. tal oscillator circuit are separated from the other power supply lines CLKOUT VDD_OSC vss_osc OSC_OUT VDD_OSC vss_osc Fig 8 26 Block diagram oscillator in slave mode Philips Semiconductors Usermanual 70 SAA7709H N1B X tal calculations It can be shown that in order to start up the transconductance of the active element must have a certain value Oma amp m A 4 RCL Where R is the loss resistance of the crystal and C is the load capacitance C and C 2 are the capacitors connected to either side of the crystal and C is the parasitic shunt capacitance of the crystal In the CDSP the minimum transconductance is 4 mA V In order to ensure start up the following inequality must hold o RCL 8m min 4 Filling in the oscillation frequency of the CDSP fo 11 2896MHZ and Qm min one obtains RCL lt 199e10 For example if C Cy 18pF and C 5pF so that C 14pF the loss resistance R of the crystal must be smaller than 1000 Q However it is wise to take a safety margin of 30 because the above equations are approximations In this example that would mean that the maximum loss resistance of the crystal which is specified by the manufacturer should not exceed 80 Q The internal bias resistor Rpias is chosen high enough 100 kQ in order to prevent start up proble
70. ter can be used see figure below 100 Q 100 Q From S source A ieie To CDSP 100 pF The T filter is used to avoid incoming and outgoing radiation component tolerance of the T filter is 20 In case the I2S signals come from a device with slew rate controlled outputs this T filter might be unnecessary Please note that this filter is optimised for a bitrate of 64 fs the rise and fall times of the I2S signals will be too high when a higher bitrate is used in this case the component values of the filter should be adapted in order to compensate for this If the 12S driver outputs of the external digital source IC s have Tri state outputs they can all be connected on one single 12S input not used outputs must be put in the high impedance mode Philips Semiconductors Usermanual 52 SAA7709H N1B 8 6 3 SPDIF input SPDIF inputs SPDIF1 pin 25 and SPDIF2 pin 24 The SPDIF input can be used as an alternative for the I S input The two SPDIF inputs are connected to the internal SPDIF receiver via an analogue multiplexer switch that selects between SPDIF1 and SPDIF2 The recommended input circuit is given in figure 8 24 see the SAA7709H datasheet for additional information 100nF SPDIF p SPDIF input input pin 24 25 75 Ohm 100pF I Fig 8 24 SPDIF input circuit 8 7 Radio Data System RDS function 8 7 1 General description The RDS function recovers the additional inaudible RDS information which
71. the Tape inputs single ended inputs VREFAD R16 R18 C17 C19 R15 R17 TAPEUR 4 TAPE L R C18 C20 J Fig 8 18 Tape Left Right input With R15 R17 56 kQ 10 R16 R18 100 kQ 10 and C18 C20 100 pF 10 a low pass input filter with cut off frequency fc 44 3 kHz is realised The capacitor C17 C19 is applied to block any DC content of the incoming signal The capacitor C17 C19 forms with R15 R16 R17 R18 a high pass filter but there are no critical requirements For the CDSP application we use C17 C19 100pF 10 and Rin 156 kQ 10 resulting in a fe 10 2 Hz 20 Remarks a The source resistance is not taken into account because this Rgource lt lt 150 KQ otherwise the cut off frequency is affected b The input resistance of the CDSP is not taken into account because this Rin gt 1 MQ c Concerning C18 C20 X7R SMD capacitors are not allowed because they show some voltage dependency which causes extra distortion therefore NPO SMD capacitors are recommended Philips Semiconductors Usermanual 44 SAA7709H N1B 8 4 3 Analogue CD input CD Left Right and CD Ground Left Right pin 70 71 72 and 73 The analogue CD input is for connecting the analogue output signal of a CD player or CD changer The SAA7709H handles fully Differential and or High Common mode CD players changers HIGH COMMON MODE CD PLAYER CHANGER In order to have a high level of common mode r
72. ting of the parameters is obtained when the annoying interference pulses are eliminated and when the IAC reacts only little at noise and audio signals For the TEA6811 6824 tuner the value codes F4CAED for the IAC settings register address 0FFC showed a good performance also on the road IAC testing The internal trigger is visible on DSP 104 pin 41 if the IAC_trigger bit of the IAC settings register is set bit 12 In this mode the parameter settings on the IAC performance can be verified The IAC can be tested with the setup given in figure 8 10 The schematics of the interference simulation network ISN and the dummy antenna are given in figure 8 11 and 8 12 respectively The rise time of the pulse generator has to be faster than 5 nanoseconds The loaded voltage amplitude must be circa 10 Volts Note that the ISN attenuates the FM signal by circa 20 dB so the RF signal output of the generator should be compensated for this Ignition interference of a four cylinder engine running at 6000 rev min can be simulated by setting the frequency of the pulse generator at 100 Hz and the duty cycle at 50 Note that the rising edge as well as the falling edge of the square wave causes a pulse in the RF signal to the receiver When the IAC is switched off each 5 milliseconds a pulse can be expected in the audio signal However because of the random phase relation between the square wave and the FM signal the amplitude of the pulses in the audio s
73. to 85 C operating temperature range e Easy applicable 3 2 Software features e FM de matrixing e AM brick wall filter e Baseband Audio processing balance fader volume e Soft Audio Mute e Large volume jumps e power interpolated for smooth volume steps e General Purpose Tone Generator 4 Quick reference specification Important This overview shows the best specification which can be obtained with an ideal receiver in combination with the SAA7709H However the specification points 4 1 and 4 2 will be limited by the front end receiver and not by the SAA7709H 4 1 FM reception Frequency response 1 dB 20 Hz 17 kHz S N mono 1KHz 22 5 kHz dev gt 69 dB typical 72 dB deemphasis 50 us S N stereo 1 kHz 22 5 kHz dev gt 60 dB typical 63 dB deemphasis 50 us Max deviation at THD lt 1 at 1 kHz gt 120 kHz Mono distortion 1 kHz at 75 kHz deviation lt 0 2 at 22 5 kHz deviation lt 0 1 Stereo distortion 1KHz 1 channel at 22 5 kHz deviation lt 0 2 Stereo channel separation 1 kHz gt 40 dB typical 45 dB Philips Semiconductors Usermanual 9 SAA7709H N1B 4 2 AM reception Frequency response with tuner 20 Hz 2 kHz Frequency response 1 dB with DSP software brickwall 20 Hz 4 5 kHz filter without tuner Frequency response 1 dB without brickwall filter 20 Hz 15 kHz without tuner S N at 1 kHz 30 AM gt 70 dB typical 75 dB Distortion 400 Hz BW 5 kHz 80 AM
74. urpose of the low pass filter is to suppress interference whistles from adjacent channels and noise AM IAC The AM IAC interference absorption circuitry detects and eliminates audible clicks caused by impulsive interference such as caused by engine ignition or fan on AM reception The characteristics of the AM IAC can be adapted to the properties of different AM tuners by means of coefficients in the YRAM of the DSP AM Quality detection The AM Quality feature detects interfering signals caused by adjacent and co channel interference This feature is available only during search mode of the AM tuner The audio output is muted during search mode 7 4 General purpose tone generator The tone generator generates a sinewave signals on the Left and Right audio channel and can be selected as main audio source The tone generator can be used f i to test the speaker outputs in the car radio during production The tone generator function is part of the audio program in the DSP and is therefor always available 7 5 Tone sequencer The tone sequencer generates a wide range of bleeps and chime sounds with selectable frequency and wave form These sounds can be used for audio feedback or for test purposes and can be added to the Primary and or Secundary channel outputs The tone sequencer function is part of the audio program in the DSP and is therefor always available Philips Semiconductors Usermanual 21 SAA7709H N1B 7 6 Noise
75. ut because they are identical from a hardware point of view The resistor combinations R11 and R16 or R13 and R18 attenuates the input signal in order to match the AM output voltage of the tuner to the input range of the A D convertor Biasing is done via the resistor R16 R18 For the CDSP application the AM output voltage of the tuner is assumed to be about 1 Vrms max R11 and R13 are 100 kQ this results in a voltage of 545 mVrms at the AF AM Left Right pins of the CDSP With R11 C14 and R13 C16 a first order low pass filter is realised at the Left and Right inputs respectively The cut off frequency of this filter Left channel example is 1 I Ri R16 R114 R16 Philips Semiconductors Usermanual 42 SAA7709H N1B The 1st order filter at the input of the AM Left Right pins is to avoid aliasing in the Audio A D convertors that means that frequency components of f gt 1 2 fsA D lt 88 dB below the maximum input of the A D convertor figure for S N for AM inputs mentioned in the data sheet The requirements are not critical though If R11 R13 45 KQ 4 10 Ri 1 MQ 20 and C14 C16 100 pF 10 then the cut off frequency fc 36 9 kHz Remarks a The source resistance is not taken into account because this Regource lt lt 220 KQ otherwise the cut off frequency is affected b Concerning C14 C16 X7R SMD capacitors are not allowed because they show some voltage dependency which causes e
76. value is such that the chip is in reset as long as the power supply is not stabilised A more or less fixed relationship between the DSP reset pin 42 time constant and the POM pin 7 time is obligatory The voltage on the POM pin determines the current flowing in the DACs At 0 V at the POM pin the DAC currents are zero and so are the DAC output voltages At 3 3 V the DAC currents are at their nominal value Long before the DAC outputs get to their nominal output voltages the DSP must be in working mode to reset the output register of the digital filter therefore the DSP reset time constant must be shorter than the POM time tpom The dsp reset input is a digital input with hysteresis and that means that the dsp reset circuit is enabled when VCdspres 80 Vdd In the CDSP application we use Tdspres 68 92 msec tolerance is due to tolerance of the external pull up resistor and the capacitor tolerance 10 Cdspres 1 UF In calculating Tdspres it is assumed that VCuspres 80 Vddd and the formula to calculate Tdspres is Vedspres Vddd 1 e The reset has the following functions the bits of the 12C hardware register are set to their preset values the program counter is set to address 0000 DSP_101 DSP_IO7 When the level on the reset pin is at logical high VCuspres 80 Vddd the DSP program in the DSP starts to run from the idle mode resets the output registers of the digital filters and the Processor can st
77. voltage of the DAC is 1 Vrms The DAC outputs require a AC load that may not drop under the 2 kQ In the application 10 kQ resistors are used R26 R28 R30 and R32 The DC output voltage is the same as VREFDA typ 1 65V This DC is removed by the electrolytic capacitors C34 C36 C38 and C40 The cut off frequency and phase non linearity of these high pass filters depends on the DAC load resistance and or input impedance of the equipment behind the CDSP The extra 1st order RC filter is to suppress radiation from the analogue output to the outside world fc 160 kHz R27 R29 R31 R33 C35 C37 C39 C41 The cut off frequency is not critical component tolerance of 20 is tolerable These filters may be omitted if considered not necessary 8 1 2 Internal reference voltage sources VREFDA pin 12 and VREFAD pin 77 The block diagram of the reference voltage sources VREFDA and VREFAD is depicted in figure 8 2 A Re oy he pee etna Seemed 100 k DC bias analog inputs Int VREF 100 k for DAC VREFDA 100 k Crerpa C42 Fig 8 2 Internal reference voltage sources block diagram The supply voltage VDDA2 is divided by two internal 10 kQ resisters and buffered The output of the first buffer is called the internal Vref and is used as the reference voltage for the D A convertors The output of the second buffer is connected to pin VREFAD pin 77 and is internally used as the 1 65 V reference voltage of the switch capacito
78. xtra distortion therefore NPO SMD capacitors are recommended The capacitor C13 C15 is applied to block any DC content of the incoming signal The capacitor C13 C15 forms with R11 Ri R13 Ri a high pass filter but there are no critical requirements For the CDSP application we use C13 C15 220nF 10 and Rin 220 KQ 10 resulting in a fc 3 3 Hz 20 Local oscillator frequency accuracy The CQUAM AM stereo decoder algorithm that runs in the DSP locks and tracks the incoming 9 5 kHz IF signal and allows a maximum tolerance of 250 Hz on the 9 5 kHz IF frequency The North American broadcast specification allows for 20 Hz broadcast frequency error so this leaves a maximum tolerance of 230 Hz for the IF tuner and IF downconvertor in front of the SAA7709H If for example the IF mixer inside the AM stereo tuner has a tolerance of 40 Hz than the maximum tolerance of the local oscillator in fig 8 17 above is 459 5 kHz 190 Hz this means that the overall accuracy of the 7 353 MHz Xtal in fig 8 17 is 400 ppm Philips Semiconductors Usermanual 43 SAA7709H N1B 8 4 2 Tape AUX input The TAPE and AUX input can configured the same Below there is an example given of the TAPE input TAPE Left Right pin 68 and pin 69 The tape input is for connecting a cassette deck The basic circuit diagram of the TAPE L and TAPE R input is depicted in figure 8 18 it is assumed that the internal ground is used for
79. z First switch OFF the Dynamic IAC Increase the deviation until the MPX IAC starts unwanted triggering Now switch ON the dynamic IAC and set dyn_threshold to maximum deviation 65 kHz Adjust decrease dyn_threshold to the value at which the unwanted trigger pulses just disappear now the highest deviation at which no unwanted triggering occurs is achieved 3 Optimisation of the Level IAC Switch OFF the Dynamic IAC MPX IAC adjusted and switched ON adjustment of IAC parameter iac_threshold Use ISN and create interfering pulses NO modulation Set iac_threshold to maximum 0 5 iac_feed_forward to minimum 2 and iac_stretch to maximum 15 Apply a low RF voltage amplitude such that the MPX IAC stops triggering Decrease iac_threshold until the Level IAC starts triggering The sensitivity can be increased by further decreasing iac_threshold but then also false triggering on audio can occur this can be verified by removing the interfering pulses Choose iac_threshold such that there is no false triggering and that the Level IAC sensitivity is sufficient at a lower fieldstrength It is recommended NOT to set the level IAC threshold lower than 0 05 otherwise false triggering can occur at certain FM Level DC values adjustment of IAC parameter iac_feed_forward and iac_stretch Create interfering pulses and verify the audio output signal Increase iac_feed_forward to the value at which the beginning of the interfering pulse is still ju

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