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VHDL Primer - Signals and Systems

1. DECIMAL INPUTS ai OUTPUTS NOTE OR rUNCTION LT RBI D C B aAJ R BO a b c d e g 0 i x 0 0 0o o 1 oN ON ON ON ON ON OFF 1 O ae C 1 OFF ON ON OFF OFF OFF OFF 2 Qj Xie ado c ES Tg 1 ON ON OFF ON ON OFF ON 3 a qvi A OE 1 ON ON ON ON OFF OFF ON 4 rox o wu o f 1 orF ON ON OFF OFF ON ON 5 i x E so 74 1 ON OFF ON ON OFF ON ON 6 d 5Xu d BO SR 28 1 ON OFF ON ON ON ON ON 7 i X 0 i D g 1 ON ON ON OFF OFF OFF OFF 8 i x 1 0 0o 0 1 oN ON ON ON ON ON ON 9 ce ee 5770 ve 1 ON ON ON ON OFF ON ON 10 1 X 1 0 1 0 1 OFF OFF OFF ON ON OFF ON 11 ji X 1 0 1 1 1 OFF OFF ON ON OFF OFF ON 12 I X 1 1 0 0 1 OFF ON OFF OFF OFF ON ON 13 T amp db ORO 0 1 ON OFF OFF ON OFF ON ON 14 I g Ub GEO gt 1 OFF OFF OFF ON ON ON ON 15 i Xe Gb A Ob X OFF OFF OFF OFF OFF OFF OFF BI X X X X X X OFF OFF OFF OFF OFF OFF OFF 2 RBI i Mp7 vue p 0 O 0 OFF OFF OFF OFF OFF OFF OFF LT O X X X X x 1 N ON ON ON ON ON ON Notes 1 The blanking input BI must be open or held at a high logic level when output functions 0 through 15 are desired The ripple blanking input RBI must be open or high if blanking of a decimal zero is not desired 2 When a low logic level is applied to the blanking input BI all segment outputs are off regardless of any other input 3 When ripple blanking input RBI and inputs A B C and D are at a low level with the lamp test input high all segment outputs go off
2. INPUTS OUTPUTS RBI LD B1 Ph D C B A RBO a b c d e f g DISPLAY X X 1 0 X X X X 0 0 0 0 0 0 0 BLANK 1 1 0 0 0 0 0 0 T 0 0 0 0 0 0 0 BLANK 0 I 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 X 1 0 0 0 0 0 Ji 0 0 1 1 0 0 0 0 nl X 0 0 0 0 X 0 0 di 1 0 3M 1 0 1 2 X 1 0 0 0 0 x 1 0 i 1 i aN 0 0 1 3 X 0 0 0 1 0 0 0 0 1 1 0 0 4 1 4 X 0 0 0 1 0 d 0 1 0 d 1 0 1 T 5 X 1 0 0 0 1 1 0 0 1 0 d 1 T 1 1 6 X i 0 0 0 1 1 i 0 1 1 1 0 0 0 0 7 X L 0 0 1 0 0 0 0 1 L 1 1 d 1 T 8 X i 0 0 1 0 0 T 0 1 4 1 1 0 1 d 9 X 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 BLANK X E 0 0 1 0 ak E 0 0 0 0 0 0 0 0 BLANK X a 0 0 1 1 0 0 0 0 0 0 0 0 0 0 BLANK X ah 0 0 1 1 0 E 0 0 0 0 0 0 0 0 BLANK X ab 0 0 1 1 J 0 0 0 0 0 0 0 0 0 BLANK X 1 0 0 1 1 r 1 0 0 0 0 0 0 0 0 BLANK X 0 0 0 X X X X KR KK t i t t t t Inverse of Output Dis Combinations Above play as above X Don t care Above combinations RBO RBI e ABCD O 52 Electronics Workbench 4000 Series ICs O 2 87 4555 Dual 1 of 4 Dec DEMUX The 4555 device is a dual 1 of 4 decoder demultiplexer Each has two pep ADA 00A L ala DIA E mutually exclusive outputs that are active HIGH O0 to O3 address inputs A0 and A1 an active LOW enable input E and four e 6 D2A E EA D3A Decoder demultiplexer truth table INPUTS OUTPUTS E A0 A1 00 01 02 03 lo mb 07x07 10 Occ ngu ue c3 0 0 1 0 0 1 O0 Ox cho o c 0 X TAE SE 0 300 2907 8 O 2 88 4
3. Indicator Description CAP The Caps Lock key is latched down NUM The Num Lock key is latched down SCRL The Scroll Lock key is latched down B 3 8 Electronics Workbench Project Menu B 3 5 Project Menu The Project menu provides the following commands e Project New e Project Open Project Files e Project Save As e Project Close e Project Save Project State Project Restore Project State Project Project Settings Project Filters Project Load Reload Input Files e Project Load and Go B 3 5 1 Project New Opens the Create New Project screen which enables you to specify the name and working directory for a new project Projects provide a useful method for organizing your source files as the files and libraries for the project may be scattered across many directories The new project name can be typed into the File Name box The SSE will automatically append the suffix spj to the project name if you do not add a suffix to the project name Click Save to create the project name and exit the screen Click Cancel to exit the screen without creating a project name After clicking Save the Project Files screen is automatically opened This screen enables you to specify all the source files library files and PLI library files associated with a project To create a new project that is similar to an existing project you may want to use Project Save As see Project Save As B 3
4. liliis eee O 16 4021 8 bit Static Shift Register o ooocoocooccroco o O 16 4023 Tri 3 IN NAND ssssssesses eR II I nenn O 16 4024 7 stage Binary Counter coccccccccc leeren O 17 40240 Octal Inv Buffer 2 2 eee O 18 40244 Octal Non inv Buffer llle O 18 40245 Octal Bus Transceiver 00 sense O 18 4025 Tri3 InNOR ooccccccoc eee O 19 4027 Dual JK FF edge pre clr llli O 19 4028 1 0f 10 Deicide reb Dew es A ne been e EE O 20 4029 4 bit Bin BCD Dec Counter liliis O 21 4030 Quad 2 In XOR sssssssssssessees ee O 21 4032 Triple Serial Adder liliis O 22 4035 4 bit Shift Register liliis O 22 40373 Octal Trans LatcCh ooococccocccoo eee 0 23 40374 Octal D type Flip flop 00 2 eee eee 0 24 4038 Triple Serial Adder llle 0 24 4040 12 stage Binary Counter 00 c eee 0 24 4041 Quad True Complement BUFFER 000000 o 0 25 4042 Quad D latch oooooooocoooocooo en O 25 4043 Quad RS latch w 3 state Out oococcocccoccooo eee O 26 4044 Quad RS latch w 3 state Out 0 2 0 0 0 o O 26 4049 Hex INVERTER 2 000 e es nen O 26 4050 Hex BUFFER 00000 cece tees O 27 4066 Quad Analog Switches 0000 ccc eee eee 0 27 4068 8 IN NAND 200 ea ccc hn 0 28 4069 Hex INVERTER ssssssssse e teens O 28 4070 Quad
5. llli B2 38 B 2 2 12Keeping Simulation Node States llli cece ee B2 39 B 2 2 13Exclude Saving Module Instance Variable Values B2 40 B 2 2 14Keeping Module Instance Simulation Variable Values B2 41 B 2 2 15Nonconvergence Summary 2 222m nennen eere B2 42 B 2 2 16Narrow Storing Outputs nennen nenn B2 43 B 2 2 17Preprocessing Data ooooccocooccc nenn B2 44 B 2 2 18Probing Node States 2 0 2 0 cee B2 45 B 2 2 19Quitting Execution 0 0 res B2 46 B 2 2 20Resetting Selected Data 0oooococcoccoo a B2 47 B 2 2 21Scope For Printing Module Variables llli llle B2 48 B 2 2 22Logic Simulation Specification llle B2 48 B 2 2 23Size Of Data Reprint llle B2 49 B 2 2 24Spike Summary OUtpUt o ooooccocccoco elles B2 50 B 2 2 25Storing Outputs a n ees B2 51 B 2 2 26Strength Specification For Gates 0000 e eee eee B2 52 B 2 2 27Symbol Modification For Output 0 0 000 c eee eee B2 53 B 2 2 28Batch Execution Overview 0 saana aeaea B2 55 B 2 2 28 1Commands in Files 2 000 cece eee B2 55 B 2 2 28 2Command line Options 2 00 ee B2 56 B 2 2 28 3Windows Batch Execution 000 B2 60 B 2 2 28 4Unix Batch Execution 0 0 0 ee B2 61 B 2 3 Verilog Libraries corras 2 P RIPE ea bode ee eben dees B2 63 B 2 9 VOVEIVIOW Lr sate ee So he MI S ee UNI rte te B2 63 B 2 3 2Library Com
6. JK flip flop truth table SD CD CP J K On On T 0 X X X 1 0 0 de X X X 0 1 1 d X X X 1 1 0 0 0 0 Hold 0 0 1 0 1 0 0 0 0 1 0 1 0 0 T 1 Toggle triggers on POSITIVE pulse Multisim User Guide seues 000p suonounJ Functions 4000 Series O 2 35 4028 1 of 10 Dec The 4028 device is a 4 bit BCD to 1 of 10 active HIGH decoder 1 of 10 decoder truth table DECIMAL OUTPUTS Ol 02 03 04 05 06 07 08 09 00 BCD INPUTS A2 Al AO A3 Extraordinary states sanas 000p suonouny Electronics Workbench O 20 4000 Series ICs O 2 36 4029 4 bit Bin BCD Dec Counter The 4029 is a synchronous edge triggered up down 4 bit binary BCD 1 PL 10 7O CE 00 01 02 03 TC HO DEC BIN Y DN UP 15 cP DRE Pile Pa decade gt counter with a clock input CP an active LOW count enable input CE an up down control input UP DN a binary decade control input BIN DEC an overriding asynchronous active HIGH parallel load input PL four parallel data inputs PO to P3 four parallel buffered out puts OO to O3 and an active LOW terminal count output TC 4 bit binary BCD decade counter truth table PL BIN DEC UP DN CE CP 1 X X X 0 X X 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 HIGH state 0 LOW state X state is immaterial mode parallel load Pn gt On no change count down dec
7. 4 line to 10 line decimal decoder truth table DECIMAL OUTPUT BCD INPUT H H H H No GI IVANI P 5 12174xx43 Exc 3 to Decimal Dec This excess 3 to decimal decoder consists of eight inverters and ten four input NAND gates Functions 74XX series P 65 Multisim User Guide Functions 74XX Series Excess 3 to decimal decoder truth table DECIMAL OUTPUT INPUT EXCESS 3 No GI IVANI P 5 12274xx44 Exc 3 Gray to Decimal Dec This excess 3 gray to decimal decoder consists of eight inverters and ten four input NAND gates Electronics Workbench P 66 sanas XXpZ suonounJj 74XX Excess 3 gray to decimal decoder truth table DECIMAL OUTPUT EXCESS 3 GRAY INPUT Hm o 0 No GI IVANI P 5 12374xx445 BCD to Decimal Dec This BCD to decimal decoder consists of eight inverters and ten four input NAND gates Functions 74XX series P 67 Multisim User Guide Functions 74XX Series BCD to decimal truth table OUTPUTS INPUTS No GI IVANI P 5 12474xx45 BCD to Decimal Dec This BCD to decimal decoder consists of eight inverters and ten four input NAND gates Electronics Workbench P 68 seues XXpZ suonouny 74XX BCD to decimal truth table INPUTS OUTPUTS No D C B alo 1 2 3 4 5 6 7 8 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 2 0 0 1 0 1 1 0 1 1 1 1 1 1 3 0 0 1 1 1 1 1
8. Decoded Bargraph Display This display consists of 10 LEDs arranged side by side just like the regular bargraph display The difference is that the decoded bargraph display already has the decoding circuitry built in so that it only requires the voltage to be measured as an input to the display The circuitry inside decodes the voltage and lights up the appropriate number of LEDs depending on the voltage level The decoded bargraph display also offers a very high resistance to the input voltage The minimum voltages required for the lowest LED and the highest LED are set in the Value tab of the Circuit Component Properties dialog box The voltage at which each LED from low est to highest lights up is given by the formula on y v Yat Electronics Workbench Buzzer where n 1 2 10 the number of the LED Other terms in this formula are defined in the table below J 6 2 1 Decoded Bargraph Display Parameters and Defaults Symbol Parameter Name Default Unit VI Minimum turn on voltage required for 1 V the lowest segment Vh Minimum turn on voltage required for 10 V the highest segment J 7 Buzzer ut This component uses the computer s built in speaker to simulate an ideal piezo SEA electric buzzer A piezoelectric buzzer sounds at a specific frequency when the voltage across its terminals exceeds the set voltage 200H Ae a 2 5 The buzzer is simulated as a single resistor whose r
9. ture E 4 D4 LED green E 8 LED Light Emitting Diode This diode emits visible light when forward current through it J exceeds the turn on current The electrical model of the LED is the same as the diode model described previously LEDs are used in the field of optoelectronics Infrared devices are used together with spectrally matched phototransistors in optoisolation couplers hand held remote Electronics Workbench LED Light Emitting Diode E 4 1 E 4 2 controllers and in fiber optic sensing techniques Visible spectrum applications include status indicators and dynamic power level bar graphs on a stereo system or tape deck Background Information LEDs are constructed of gallium arsenide or gallium arsenide phosphide While efficiency can be obtained when conducting as little as 2 milliamperes of current the usual design goal is in the vicinity of 10 mA During conduction there is a voltage drop across the diode of about 2 volts Most early information display devices required power supplies in excess of 100 volts The LED ushered in an era of information display components with sizes and operating voltages compatible with solid state electronics Until the low power liquid crystal display was devel oped LED displays were common despite high current demands in battery powered instru ments calculators and watches They are still commonly used as on board annunciators disp
10. 00 05 9 H Ol to O9 L Counter advances Counter advances No change No change No change No change HIGH state the more positive voltage LOW state the less positive voltage state is immaterial positive going transition negative going transition number of clock pulse transitions O 11 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 18 40174 Hex D type Flip flop The 40174 device is a hex edge triggered D type flip flop with six data inputs DO to D5 a clock input CP an overriding asynchronous master reset input MR and six buffered outputs OO to O5 Hex D type flip flop truth table INPUTS OUTPUT CP D MR o 1 1 1 0 1 0 X 1 no change X X 0 0 1 HIGH state the more positive voltage 0 LOW state the less positive voltage gtate is immaterial positive going transition negative going transition O 2 19 40175 Quad D type Flip flop O 12 This device is a quadruple edge triggered D type flip flop with four data inputs Dp to D3 a clock input CP an overriding asynchronous master rest input MR four buffered outputs Op to O4 and four complementary buff ered outputs Op to Oy Electronics Workbench 4000 Series ICs Quadruple D type flip flop truth table INPUTS OUTPUTS CP D MR o o i X T 0 0 L 0 1 X 1 no change no change X X 0 0 i 1 HIGH state the more positive voltage 0 LOW state
11. EXCLUSIVE OR gate truth table O 2 54 4071 Quad 2 In OR This device contains four independent 2 input OR gates 2 gt Logic function OR gate truth table 0 2 55 4072 Dual 4 In OR The 4072 device provides the positive dual 4 input OR function 7 Logic function pS la Y A B C D Multisim User Guide O 29 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 56 4073 Tri 3 In AND O 30 4 input OR gate truth table 1 2 3 A AND gate truth table INPUTS OUTPUT A B c D Y 0 0 0 0 0 0 0 0 ae 1 0 0 1 0 1 0 0 1 I 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 T 1 1 0 0 0 1 1 0 0 1 1 1 0 T 0 1 1 0 T 1 1 1 1 0 0 1 1 1 0 1 1 1 I T 0 1 1 T 1 1 1 This device contains three independent 3 input AND gates Logic function x Rkorororolb HH poonnosoco lutu PPPRPOOOCO IAa H O G O O O LO O i ABC Electronics Workbench 4000 Series ICs O 2 57 4075 Tri 3 In OR 2 9 This device contains three independent 3 input OR gates Logic function ed A B C OR gate truth table PRrRFRFOoOoOo oO Oo P H poonnosoco tu HDonononrno n Pbrerbppp RO 0 2 58 4076 Quad D type Reg w 3 state Out 4 37 po 00 iz 01 7722 02 31 p 03 EEEE Multisim User Guide The 4076 device is a quadruple edge triggered D type flip flop with four data inputs Dg to D3 two active LOW data e
12. B 3 11 6Help About SSE Opens the About SILOS Simulation Environment screen This screen contains the SILOS III version number copyright notice and the total memory allocated in RAM memory for SILOS III The memory usage for SILOS III is constant for logic simulation If you select the Load Reload Input Files button on the Main toolbar SILOS III will simulate to time 0 You can then use the About SILOS Simulation Environment screen to determine the RAM memory usage for your design during logic simulation B 3 12Pop up Menus SILOS III has pop up menus for the Watch window Explorer window Data Analyzer win dow Output window and the source windows The pop up menus for the Output window and the source windows allow you to Cut Copy and Paste The pop up menus for windows are The right hand side of the Explorer window has a pop up menu for the Add Signals to Analyzer and Name Filter commands To invoke this pop up menu use the right mouse B 3 32 Electronics Workbench Pop up Menus button to click on any part of the right hand side the side with the signal names of the Explorer window The pop up menu will remain open while the left mouse button is used to select a menu item The left hand side of the Explorer window has a pop up menu for the Copy Scope Go To Module Source Go To Scope and Properties command To invoke this pop up menu use the right mouse button to click on any part of the left hand side the side wi
13. Donononsoco Dopooonnoso PLEAPRROOOO OPPRRRR AO 0 2 29 4024 7 stage Binary Counter The 4024 is a 7 stage binary ripple counter A high on MR Master Reset forces all counter stages and outputs low The 4024 counts from 0 to 15 in binary on every negative high to low transition of the clock pulse 7 stage counter truth table INPUTS OUTPUTS MR CP Qg Qf Qe Qd Qe Qb Qa 0 Count 0 Count Multisim User Guide O 17 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 30 40240 Octal Inv Buffer The 40240 device is an octal inverting buffer with 3 state outputs O 2 31 40244 Octal Non inv Buffer The 40244 device is an octal non inverting buffer with 3 state outputs O 2 32 40245 Octal Bus Transceiver The 40245 device an octal bus transmitter receiver with 3 state outputs is A Be designed for 8 line asynchronous 2 way data communication between data buses 2 3 a 5 5 77 8 8 1 s a O 18 Electronics Workbench 4000 Series ICs O 2 33 4025 Tri 3 In NOR This device contains three independent 3 input NOR gates 1 ap 3 Logic function 8 O I 1 gt 13 NOR gate truth table H H H N H w o H Hononnoso HMHPHoOOHOHO HHHHooo6o ooooooon 0 2 34 4027 Dual JK FF edge pre clr This device contains two independent JK flip flops They have separate pre set and clear inputs
14. Time base 3 X position 0 00 gt rrr ust a Channel A Yposition 0 00 Y position 0 00 pej oo em mel ojos Due Multisim User Guide L 15 SJo11u02 Controls Controls Components L 8 1 Characteristic Equation Vour KW Vig for V S Vou S Vmax out T Vour ae for Vour gt Via Vour 2d V nin for Vour lt V nin L 8 2 Voltage Limiter Parameters and Defaults L 9 L 16 Symbol Parameter Name Default Unit Vloff Input offset voltage 0 V K Gain 1 V V VI Output voltage lower limit 0 V Vu Output voltage upper limit 1 V Vs Upper and lower limit smoothing range 1e 06 V Current Limiter Block A1 This component models the behavior of an operational amplifier or compara tor at a high level of abstraction All of its pins act as inputs three of them 1 also act as outputs The component takes as input a voltage value from the in connector It then applies the offset and gain and derives from it an equivalent internal voltage Veq which it limits to fall between the positive and negative power supply inputs If Veq is greater than the output voltage seen on the out connector a sourcing current will flow from the output pin Otherwise if Veq is less than the output voltage a sinking current will flow into the output pin OV 1V v Depending on the polarity of the current flow either a sourcing or a sinking resistance Rsrc or Rsnk value is a
15. is used to match any pattern including null The question mark character is used to match any single character Multisim User Guide B 3 13 snus 111 SOS Silos II Menus Silos III Menus B 3 5 10Project Load Reload Input Files Automatically resets SILOS III and inputs the files specified for the project that is open Logic simulation is then run to time 0 and you can begin debugging your project by setting breakpoints single stepping etc The Data Analyzer can be opened to display the results dur ing simulation Choosing the Go button on the toolbar will run logic simulation until a Sstop or finish is encountered in the design or until you click the STOP button on the toolbar B 3 5 11Project Load and Go B 3 6 B 3 6 1 B 3 14 Automatically resets Hyperfault inputs the files specified for the project and then runs logic simulation until a stop or a finish system task is encountered or until you click the STOP button on the toolbar Reports Menu The Reports menu provides the commands e Reports Activity e Reports Errors e Reports Fault e Reports Iteration e Reports Nonconvergence e Reports Size Reports Activity Can be used to pre grade the test vectors for fault simulation by reporting nodes that have no activity level transitions during a logic simulation The logic simulation is much faster to run than fault simulation An ACTIVITY report can be very useful for
16. 0 end comparel Reading from the top of the source file you can see the following elements Anentity declaration that defines the inputs and outputs the ports of this circuit e An architecture declaration that defines what the circuit actually does using a single con current assignment Every VHDL design description consists of the following 1 At least one entity architecture pair which in VHDL jargon is sometimes referred to as a design entity In a large design you will typically write many entity architecture pairs and connect them together to form a complete circuit An entity declaration describes the circuit as it appears from the outside that is from the perspective of its input and output interfaces If you are familiar with schematics you might think of the entity declaration as being analogous to a block symbol on a schematic 2 The architecture declaration which refers to the fact that every entity in a VHDL design description must be bound with a corresponding architecture The architecture describes the actual function or contents of the entity to which it is bound Entity Declarations An entity declaration provides the complete interface for a circuit Using the information pro vided in an entity declaration the names data types and direction of each port you have all the information you need to connect that portion of a circuit into other higher level circuits or to deve
17. 100 Ohm 1e 0035 The lossless model is an ideal one that simulates only the characteristic impedance and propagation delay properties of the transmission line The characteristic impedance is resistive and is equal to the square root of L C Note Alossy transmission line with zero loss can be used to model the lossless transmission line and may be more accurate K 13 1 Model A lossless transmission line is an LC model as shown The values of L and C are given by m Z lt td Z where ct capacitance per unit length It inductance per unit length td propagation time delay Z nominal impedance The propagation time delay may be calculated from the data books as follows EE m Vp Vp Vf c Multisim User Guide K 17 OSIN Misc Misc Components where length length of the line Vp velocity of propagation Vf velocity factor C speed of light K 13 2 Lossless Transmission Line Model Parameters and Defaults Symbol Parameter Name Default Unit ZO Nominal impedance 100 Q Td Propagation time delay 1e 09 S K 13 3 Lossless Line Type 2 wi This component is similar to lossless line type 1 100 Ohm 1e 006 Hz K 14 Net This is a template for building a model It allows you to input a netlist using from 2 to 20 pins K 18 Electronics Workbench Appendix L Controls Components L 1 L 2 L 3 L 4 L 5 L 6 L 7 L 8 MultipliGt vires 22 ra a Wee EUH PER U
18. B 1 18 The Verilog language provides two types of explicit timing control over when simulation time procedural statements are to occur The first type is a delay control in which an expression specifies the time duration between initially encountering the statement and when the state ment actually executes The second type of timing control is the event expression which allows statement execution The third subsection describes the wait statement which waits for a specific variable to change Electronics Workbench The Verilog Language Verilog is a discrete event time simulator i e events are scheduled for discrete times and placed on an ordered by time wait queue The earliest events are at the front of the wait queue and the later events are behind them The simulator removes all the events for the current sim ulation time and processes them During the processing more events may be created and placed in the proper place in the queue for later processing When all the events of the current time have been processed the simulator advances time and processes the next events at the front of the queue If there is no timing control simulation time does not advance Simulated time can only progress by one of the following 1 gate or wire delay if specified 2 adelay control introduced by the symbol 3 anevent control introduced by the 9 symbol 4 the wait statement The order of execution of events in the same clock t
19. Channel A Channel B Yposition 0 00 Y position 0 00 eejo er inel olfoc ae L 5 2 Characteristic Equation L 10 dV V u K ou 1 K Voor Electronics Workbench Voltage Integrator L 5 3 Voltage Differentiator Parameters and Defaults Symbol Parameter Name Default Unit K Gain 1 VN VOoff Output offset voltage 0 V VI Output voltage lower limit 1e 12 V Vu Output voltage upper limit 1e 12 V Vs Upper and lower smoothing range 1e 06 V L 6 Voltage Integrator This component calculates the integral of the input voltage the transfer func tion 1 s and delivers it to the output It is used in control systems and analog computing applications YN The true integrator function continuously adds the area under a curve for a specified time interval For waveforms that are symmetrical about the zero axis area above and below the axis is zero and the resulting integrator output is zero For waveforms that are not symmetrical about the zero axis the areas will be different If area above the axis is greater integrator output will rise If area is less integrator output will fall L 6 1 Investigations 1 Inthe initial circuit the input signal is symmetrical 5V about the zero axis and the integrator output is zero for sine square and triangle waveforms 2 To make the waveforms unsymmetrical about the zero axis use the OFFSET control on th
20. J 5 2 Decoded Seven Segment Display This display indicates its current state by displaying hexadecimal digits numerals 1 to 9 and letters A to F It is easier to use than the regular seven segment display because it is already decoded Each hexadecimal digit is displayed when its 4 bit binary equivalent is received as input as shown in the truth table below Truth table 0 0 0 0 0 0 0 0 I 0 0 1 0 I 0 0 1 0 0 I 1 0 1 1 1 0 0 T 0 0 i 0 1 1 0 1 1 1 0 1 1 0 1 T 1 1 1 1 Multisim User Guide Digit displayed 0 1 2 a QU FP Oo ra J 5 SJO eoIpu Indicators Indicators Components J 6 J 6 1 J 6 2 J 6 Bargraphs The Component u1 This display is an array of 10 LEDs arranged side by side This com E DCD_BARGRAPH n ES ponent may be used to indicate visually the rise and fall of a voltage The voltage to be measured needs to be decoded into levels using comparators which are used to drive each individual LED The terminals on the left side of the display are anodes and the terminals on the right are cath odes Each LED lights up when the turn on current flows through it You can change the voltage drop in the Value tab of the Circuit Component Properties dialog box J 6 1 1 Bargraph Display Parameters and Defaults Symbol Parameter Name Default Unit Vf Forward voltage drop 2 V If Forward current at which Vf is measured 0 03 A lon Forward current 0 01 A
21. Parallel operation CP INPUTS OUTPUT J K MR O 1 MODE OF OPERATION I 1 0 1 D flip flop 0 0 0 0 D flip flop 1 0 0 Og toggle 0 1 0 Oo no change X X i 0 reset INPUTS OUTPUTS PO P1 P2 P3 00 O1 O2 03 positive going transition HIGH state the more positive voltage LOW state the less positive voltage State is immaterial O 2 40 40373 Octal Trans Latch The 40373 device is an 8 bit transparent latch with 3 state buffered out DO D1 D2 D3 D4 D5 De D7 gt 933933818 EN 00 puts 01 02 03 04 05 06 07 lel al al sl ol of of Multisim User Guide O 23 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 41 40374 Octal D type Flip flop The 40374 device is an octal D type flip flop with 3 state buffered outputs 4 Do 00 with a common clock input CP It used primarily as an 8 bit positive 7 f edge triggered storage register for interfacing with a 3 state bus gi 021 8 3 yea E ra fa mg Sf 9 9s ot 4 aq Eo cr 0 2 42 4038 Triple Serial Adder The 4038 triple serial adder has the clock and carry reset inputs common B3 INVERT_3 cp RESET 24 m st toall three adders The carry is added on the negative going clock transi T tion for this device 48 INVERT 1 i 2 B2 45 INVERT 2 TE AB 3 2 37 6 0 2 43 4040 12 stage Binary Counter The
22. The format for the probe command is STORE probe tl t2 sion STORE probe ITER t1 t2 format expression expres format expression expres sion STORE probe sion STORE probe STEP dt ITER t1 t2 format expression Multisim User Guide STEP dt tl t2 format optional directs the probe output to a disk file Use the DISK command to specify the file name for thestored out put reports the value of variables and expressions in tabular format Default report the on change values optional causes the values to be reported between time t1 to time t2 at intervals of dt optional causes values of variables and expressions to be reported for each iteration at a time point optional represents an optional time point range over which the values will be reported When t1 and t2 are not specified the probe command will use the simulation time values or the time values specified on the last probe command optional specifies the format for reporting the expres sions Any of the format specifications for display and monitor are allowed Default radix h specifies any legal Verilog HDL expression The paren theses around the first specified expression are not required when it is just a single variable Full hierarchical path names can be used otherwise the module instance selected by the SCOPE command will be used A can be used instead of a name to insert a blank
23. secondary current D 6 2 Ideal Transformer Model Parameters and Defaults Symbol Parameter Name Default Unit n Turns ratio 2 Lo Leakage inductance 0 001 H Ln Magnetizing inductance 5 H Rp Primary winding resistance 0 0 WwW Rs Secondary winding resistance 0 0 Ww If n 1 itis a step down transformer if n 1 itis a step up transformer Multisim User Guide oiseg Basic Components Basic D 7 Nonlinear Transformer This component is based on a general model that can be customized for dif 12 ferent applications It is implemented using a conceptual magnetic core and coreless coil building een blocks together with resistors and inductors Using this transformer you can model physical effects such as nonlinear magnetic saturation primary and sec ondary winding losses primary and secondary leakage inductances and core geometric size See the Magnetic Core description for characteristic equations of the magnetic core D 7 1 Customizing The nonlinear transformer can be customized for different applications It is implemented by using a magnetic core and the coreless coil as the basic building blocks The magnetic core takes in an input voltage and converts it to a Magnetomotive Force mmf The Magnetic Field Intensity H is calculated by dividing the mmf by the Length of the core H mmf L H is then used to find the corresponding Flux Density B This is done by using the linea
24. seues 000p suonounJ Functions 4000 series Functions 4000 Series Priority encoder truth table INPUTS OUTPUTS El 0 1 2 3 4 5 6 7 GS 02 01 00 EO 0 X X X X X X X X 0 0 0 0 0 E 0 0 0 0 0 0 0 0 0 0 0 0 1 T 1 X X X X X X X 1 E 1 1 0 1 0 1 X X X X X X 1 b 1 0 0 1 0 0 T X X X X X 1 E 0 1 0 1 0 0 0 1 X X X X 1 T 0 0 0 1 0 0 0 0 1 X X X Ji 0 I 1 0 1 0 0 0 0 0 1 X X Ji 0 ak 0 0 1 0 0 0 0 0 0 1 X Ji 0 0 1 0 L 0 0 0 0 0 0 0 1 1 0 0 0 0 0 2 84 4539 Dual 4 input Multiplexer jaje 305 2 13 d 5 IE mn tass EIN 00 01 02 GS EOUT o Tu Tale The 4539 device is a dual 4 input multiplexer with common select logic Each multiplexer has four multiplexer inputs IO to I3 an active LOW enable input E and a multiplexer output O 0 2 85 4543 BCD to seven segment latch dec driver O 50 DA a E a Ba OB kr oc OD pepa DE OF oG aT ala N The 4543 device is a BCD to 7 segment latch decoder driver for liquid crystal and LED displays It has four address inputs DA to DD an active HIGH latch disable input LD an active HIGH blanking input BI an active HIGH phase input PH and seven buffered segment outputs Oa to Og Electronics Workbench 4000 Series ICs 7 segment latch decoder driver truth table INPUTS OUTPUTS LD BI PH DD DC DB DA Oa Ob Oc Od Oe Of Og DISPLAY X d 0 X X X X 0 0
25. 1ae 1 1 b 1 1a 0 end initial begin Set up monitoring Smonitor Time 0d a b b b outl b out2 b time a b outil out2 end Instances of modules AND and NAND AND gatel a b out2 NAND gate2 a b out1 endmodule Notice that we need to hold the values a and b over time Therefore we had to use 1 bit regis ters reg variables store the last value that was procedurally assigned to them just like vari ables in traditional imperative programming languages wires have no storage capacity They can be continuously driven e g with a continuous assign statement or by the output of a module or if input wires are left unconnected they get the special value of x for unknown Continuous assignments use the keyword assign whereas procedural assignments have the form reg variable expression where the reg variable must be a register or mem ory Procedural assignment may only appear in initial and always constructs The statements in the block of the first initial construct will be executed sequentially some of which are delayed by 1 i e one unit of simulated time The always construct behaves the same as the initial construct except that it loops forever until the simulation stops The initial and always constructs are used to model sequential logic i e finite state automata Verilog makes an important distinction between procedural assignment and the continuous assignment assign Proc
26. 3 To enable spike recording during logic simulation for the SPIKE report use the silos spike command line option Examples ty spikes NSTO SPIKES 4 2K 4 8K STORE B 2 2 25Storing Outputs When a command that generates a report is preceded by the STORE command the report out put will be directed to a disk file To specify the STORE command enter STORE command STORE Directs the output to a 132 column disk file As a default this file is named store out command Represents a command structure which defines the type of data to be output These commands are described within this sec tion of the manual Application Notes 1 If a command that generates a report is not preceded by the STORE command then the default output device is specified by the CONTROL command 2 To respecify the page width for the STORE command use the FORMAT STORE com mand 3 The default file name for the STORE command may be redefined using the DISK com mand or the FILE STO command Examples store output on change Multisim User Guide B 2 51 Ssuoisueix3 JAH Bojan Verilog HDL Extensions Extensions STO NETWORK FDD B 2 2 26Strength Specification For Gates The STRENGTH command allows you to modify the default strength types To respecify default strength types for gate devices use STRENGTH device strg device strg DEFAULT strg STRENGTH Indicates that default strength types are to be assigned to unid
27. D 2 Switch ia The single pole double throw switch can be closed or opened turned on or off by pressing a key on the keyboard You specify the key that controls the switch by typing its name in the Value tab of the Circuit Component Properties dialog box For example if you want the switch to close or open when the spa cebar is pressed type space in the Value tab then click OK A list of possible key names is shown below To use letters a to z Type the letter e g a Enter enter spacebar space Multisim User Guide D 1 oiseg Basic Basic Components D 3 D 2 Resistor Resistors come in a variety of sizes depending on the power they can safely R1 dissipate A resistor s resistance R is measured in ohms It can have any value rn 10kohm from Q to MQ The Resistance R of a resistor instance is calculated using the following equa tion R Ro 1 TC1 T To TC2 T To 2 where Ro To TC1 TC2 The resistance of the resistor The resistance of the resistor at temperature To Normal temperature 27 degrees C CONSTANT First order temperature coefficient Second order temperature coefficient Temperature of the resistor All of the above variables can be modified with the exception of To which is a constant Note that Ro is the resistance specified on the Value tab of the resistor properties dialog not R T can be specified in two w
28. Gy lor dl Ems dV ps PS Multisim User Guide F 13 SJO SISUBJ Transistors Transistors Components F5 6 MOSFET Level 1 Model Parameters and Defaults Symbol Parameter Name Default Unit VTO Threshold voltage 0 V KP Transconductance coefficient 2e 05 AN LAMBDA Channel length modulation 0 1N PHI Surface potential 0 6 V GAMMA Bulk threshold parameter 0 V 0 5 RD Drain ohmic resistance 0 Ww RS Source ohmic resistance 0 Ww IS Bulk junction saturation current 1e 14 A CGBO Gate bulk overlap capacitance per meter 0 F channel length CGDO Gate drain overlap capacitance per meter 0 F channel length CGSO Gate source overlap capacitance per meter 0 F channel width CBD Zero bias bulk drain junction capacitance 0 F CBS Zero bias bulk source junction capacitance 0 F PB Bulk junction potential 0 8 V RSH Drain and source diffusion sheet resistance 0 Ww CJ Zero bias bulk junction bottom capacitance 0 F m per m2 of junction area MJ Bulk junction bottom grading coefficient 0 5 CJSW Zero bias bulk junction sidewall capacitance 0 F m per m of junction perimeter MJSW Bulk junction sidewall grading coefficient 0 5 JS Bulk junction saturation current per m2 of 0 A m junction area F 14 Electronics Workbench JFETs Junction FETs Symbol Parameter Name Default Unit TOX Oxide thickness 1e 07 m NSUB Substrate doping 0 1 cms N
29. Stop at simulation time 1000 oOoOo0D0DRPRoOooOo0oRPpooPpooRrp oo poo Pp ooPRrpooprpoo 1 oHooHocoHocoHoo Hoc Pp ooPrpooPprpoo Electronics Workbench System Tasks and Functions B 1 3 System Tasks and Functions System tasks are not part of the Verilog language but are build in tasks contained in a library A few of the more commonly used one are described below The Verilog Language Reference Manual has many more B 1 3 1 cleartrace The cleartrace system task turns off the trace See B 1 3 6 settrace on page B 1 25 to set the trace Scleartrace B 1 3 2 display Displays text to the screen much like the printf statement from the language C The gen eral form is display parameter parameter parameter where parameter may be a quoted string an expression that returns a value or a null parameter For example the following displays a header display Registers A B em The special character 96 indicates that the next character is a format specification For each character that appears in the string a corresponding expression must be supplied after the string For example the following prints the value of A in binary octal decimal and hex display A b binary o octal d decimal h hex A A A A produces the following output A 00001111 binary 017 octal 15 decimal Of hex The commonly used format specifiers are oe o display in binary format display in ASCII charac
30. _ EA 7 L 9 1 Current Limiter Parameters and Defaults Symbol Parameter Name Default Unit Off Input offset 0 V k Gain 1 VN Rsrc Sourcing resistance 1 WwW Rsink Sinking resistance 1 W ISrcL Current sourcing limit 10 mA ISnkL Current sinking limit 10 mA ULSR Upper and lower power supply smoothing range 1 uv ISrcSR Sourcing current smoothing range 1 nA ISnkSR Sinking current smoothing range 1 nA VDSR Internal external voltage delta smoothing range 1 nQ L 18 Electronics Workbench Voltage Controlled Limiter L 10 Voltage Controlled Limiter A voltage clipper This component is a single input single output function The output is restricted to the range specified by the output lower and upper limits Output smoothing occurs within the specified range The voltage controlled limiter will operate in DC AC and tran sient analysis modes OV 1Viv The component tests the values of the upper and lower limit control inputs to make sure that they are spaced far enough apart to guarantee the existence of a linear range between them The range is calculated as the difference between upper limit control input U VoUD ULSR and lower limit control input L VoLD ULSR and must be greater than or equal to zero The limiting levels may be individually set at fixed values or one or both limiting levels may be controlled by a variable voltage depending on the desired application In the circuit shown below the up
31. drga teta nee een eR OR 3 B 1 2 1A First Verilog PrograM ooooooccrroonrr meh 3 B 1 2 2Lexical Conventions 22 222 nen sense nh 5 B 1 2 3Program Structure o oooooccooco een 6 Bil 2 4Data Types cs e ss ee at ect A eher 9 B 1 2 4 1Physical Data Types 0 0 0 cee ee 9 B 1 2 4 2Abstract Data Types 222m Henne ernennen nen 10 B 1 2 50peralotS rne unb ue osa d bes usd EE aaa dinates E E E 11 B 1 2 5 1Binary Arithmetic OperatorS oocooccoccoccno ee 11 B 1 2 5 2Unary Arithmetic Operators 00 000 cee eee 11 B 1 2 5 3Relational Operators nanasu aaaea 11 B 1 2 5 4Logical Operators 20 eee 11 B 1 2 5 5Bitwise Operators 0 0 eee 12 B 1 2 5 6Unary Reduction Operators sassa aaaea eese 12 B 1 2 5 7Other OperatorS o oocooccococcncc eA 12 B 1 2 5 80perator Precedence o ooccccccocco en nn 13 B 1 2 62 6 Control Constructs 2 22 con een eee 13 B 1 2 6 1Selection if and case Statements 0000 cee eee 14 B 1 2 6 2Repetition for while and repeat Statements 14 B 1 2 7Other Statements o oooccocccoo ens 15 B 1 2 7 1Parameter Statement 22m css een eee 15 B 1 2 7 2Continuous Assignment 0 0000 seen nennen nenn nn 15 B 1 2 7 3Blocking and Non blocking Procedural Assignments 15 B 1 2 8Tasks and Functions 00 0c eee nenn 16 B 1 2 9Timing Control 0 0 0 0 rh 18 B 1 2 9 1Del
32. ential mode DM and common mode CM input characteristics The capacitor C intro duces a second order effect for the slew rate and C1 introduces a second order effect to the phase response Rx Ia SR Cc Be A SR 27t fu Cc Ini ma 2 Ia 1 P In Ia si p In2 i 8 1 B T 2 pi pz 200 Tree Re Assume ls 10 16 Vos ls2 is 1 es C1 Stan AQ The interstage provides the DM and CM gains and consists of voltage controlled current sources Zem Za and g and resistors Ry and R The dominant time constant of the opamp is provided by the internal feed back capacitor c In some opamps the two nodes of c are made available to the outside world for external compensation The output stage models DC and AC output resistance The elements d3 vc d4 and ve provide maximum desired voltage swings Elements d1 d2 rcc and gc provide the current limiting function G 6 Electronics Workbench Opamp Interstage u Ic 8 002585 Ra Bin Ra d Bi PB2 2 gm ES 4 Ra ARc b S 1008 Roz Gem Ga Curr Output stage R Ro gt Ro out 7 Ry I 2 1 8 Lsc Ls I exp Ki lc 0 025 0 025 I cc In 100 Isp 1 Gc Re V V Va V I Ise C CC sw PD _ I Vg V Vow A Note In addition to the base L2 simulation model other models of this complexity or level are supplied by the various manufacturers for their particular opamp
33. ilog HDL Language Reference Manual The default setting for the switch is to check for IEEE compliance To allow all extensions enter control ext all before inputting your model The parameters to allow individual extensions are reported in the syntax error for each Multisim User Guide B 2 19 suoisuejx3 JAH Bojan Verilog HDL Extensions Extensions B 2 20 extension The following sections include a sample list of extensions that will be flagged as Syntax errors B 2 1 7 1Global Variables example wire xx module endmodule SILOS III command to allow this extension Icontrol ext gvar B 2 1 7 2Global tasks and functions example function endfunction module endmodule SILOS III command to allow this extension control ext gft B 2 1 7 3Functions with multiple outputs example function xx in out2 input in output out2 SILOS 111 command to allow this extension Icontrol ext fmout B 2 1 7 4Functions without any inputs example x funct SILOS III command to allow this extension Electronics Workbench Verilog HDL Extensions Icontrol ext fzero For more information see section 9 3 4 of the Verilog HDL Reference on line help file B 2 1 7 5Tasks and functions with ports declared like a module example task foo inl in2 SILOS III command to allow this extension control ext formals B 2 1 7 6Procedural assignment to wires example module foo wire w i
34. lt some procedural code gt end We assume that the event occurs in one thread of control i e concurrently and the controlled code is in another thread Several events may to or ed inside the parentheses B 1 2 9 3 wait Statement The wait statement allows a procedural statement or a block to be delayed until a condition becomes true wait A 3 begin A B amp C end The difference between the behavior of a wait statement and an event is that the wait state ment is level sensitive whereas posedge clock is triggered by a signal transition or is edge sensitive B 1 2 9 4 fork and join Statements By using the fork and join construct Verilog allows more than one thread of control inside an initial or always construct For example to have three threads of control you fork the thread into three and merge the three into one with a join as shown fork three split thread into three one for each begin end begin code for thread 1 end begin code for thread 2 end Electronics Workbench The Verilog Language begin code for thread 3 end join merge the three threads to one Each statement between the fork and join in this case the three begin end blocks is executed concurrently After all the threads complete the next statement after the join is executed You must be careful that there is no interference between the different threads For example you can t change a register in two different thread
35. 1 and Clk event then if Load 1 then Qreg Data else Qreg Qreg 1 to 7 Qreg 0 end 1f end if Q Qreg end process As written the process is dependent on or sensitive to the asynchronous inputs Rst and CIk These are the only signals that can have events directly affecting the operation of the circuit in the absence of any event on either of these signals the circuit described by the process will simply hold its current value that is the process will remain suspended Consider what happens when an event occurs on either one of these asynchronous inputs First look at what happens when the input Rst has an event in which it transitions to a high state represented by the std ulogic value of 1 In this case the process will begin exe cution and the first 1f statement will be evaluated Because the event was a transition to 1 the simulator will see that the specified condition Rst 1 is true and the assignment of variable Qreg to the reset value of 00000000 will be performed The remaining statements of the if then elsif expression those that are dependent on the elsif condition will be ignored The final statement in the process the assignment of output signal Q to the value of Qreg is not subject to the if then elsif expression and is therefore placed on the process queue for execution Signal assignments do not occur until the process actually suspends Finally the process
36. 1 The EXCLUDE command can be used to specify wires to be excluded from the saved simulation results 2 The MKEEP and MEXCLUDE commands will keep and exclude all variables including registers and memory variables within a module or macro instance 3 The effects to the KEEP and EXCLUDE commands are cumulative 4 The KEEP EXCLUDE MKEEP and MEXCLUDE commands can be used with the CONTROL SAVSIM 1 option Examples CONTROL SAVSIM 1 KEEP MAC15 REGO8 MAC1 MEM ADDRO1 keep m1 bitO ml bit1 m1 bit2 m1 bit3 m1 bit4 ml bit5 m1 bit6 m1 bit7 iobuf pin34 Multisim User Guide B 2 39 suoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions B 2 2 13Exclude Saving Module Instance Variable Values The MEXCLUDE command excludes the internal variable values from being saved during logic simulation for module instances and macro expansions and any variable that is hierar chically below the excluded module instance or macro expansion The format for the MEXCLUDE command is MEXCLUDE mname mname e mname MEXCLUDE Specifies module instances and macro expansions that will not have their internal variables and any variable that is hierarchically below the excluded module instance or macro expansion saved during logic simulation mname represents the name of a module instance or macro expansion Application Notes 1 The MKEEP command can be used to specify module instances and macro expansions for wh
37. 74LS648 TRANSCEIVER REGISTERS 74LS649 TRANSCEIVER REGISTERS 74LS651 TRANSCEIVER REGISTERS 74LS652 TRANSCEIVER REGISTERS 74LS653 TRANSCEIVER REGISTERS 74LS668 UP DOWN COUNTER 74LS669 UP DOWN COUNTER 74LS671 SHIFT REG 74LS672 SHIFT REG 74LS673 SHIFT REG 74LS674 SHIFT REG 74LS681 ALU 74LS682 COMPARATOR 74LS684 COMPARATOR 74LS685 COMPARATOR 74LS686 COMPARATOR 74LS687 COMPARATOR Electronics Workbench Verilog Libraries B 2 3 4 TTL BCT Parts List Name Description 74LS688 COMPARATOR 74LS690 COUNTER 74LS691 COUNTER 74LS693 COUNTER 74LS696 COUNTER 74LS697 COUNTER 74LS699 COUNTER Simucad provides many of the popular TTL library models for the 74 BCT series The behav ioral source for these parts is provided as two libraries e SN74BCT series without timing subdirectory library sn74bct e SN74BCT series with timing subdirectory library sn74bctt The list below shows the TTL BCT library parts provided with SILOS III Ref TTL Logic Data book SDLD001A Revised March 1988 Ref BiCMOS Bus Interface Logic Data book SCBDOO1A Revised July 1989 Multisim User Guide Nama Description 74BCT125 Quad Buffer Gates 74BCT126 Quad Buffer Gates 74BCT240 Octal buffers line drivers 74BCT241 Octal buffers line drivers 74BCT244 Octal buffers line drivers 74BCT245 Octal bus transceivers 74BCT373 Octal D type latches 74BCT374 Octal D type FFs B 2 73 s
38. 74xx136 P 13 74xx138 P 13 74xx139 P 14 74xx14 P 14 74xx145 P 15 74xx147 P 16 74xx148 P 16 74xx15 P 17 74xx150 P 17 74xx151 P 18 74xx152 P 18 74xx153 P 19 74xx154 P 19 74xx155 P 20 74xx156 P 21 74xx157 P 21 74xx158 P 21 74xx159 P 22 74xx16 P 23 74xx160 P 23 74xx161 P 24 74xx162 P 25 74xx163 P 25 74xx164 P 26 74xx165 P 27 74xx166 P 27 74xx169 P 28 74xx17 P 28 Multisim User Guide 74xx173 P 29 74xx174 P 29 74xx175 P 30 74xx180 P 30 74xx181 P 31 74xx182 P 31 74xx190 P 33 74xx191 P 33 74xx192 P 34 74xx193 P 34 74xx194 P 35 74xx195 P 35 74xx198 P 36 74xx199 P 37 74xx20 P 38 74xx21 P 38 74xx22 P 38 74xx238 P 39 74xx240 P 39 74xx241 P 40 74xx244 P 40 74xx246 P 41 74xx247 P 42 74xx248 P 43 74xx249 P 44 74xx25 P 45 74xx251 P 45 74xx253 P 46 74xx257 P 46 74xx258 P 47 74xx259 P 47 74xx26 P 47 74xx266 P 48 74xx27 P 48 74xx273 P 49 74xx279 P 49 74xx28 P 50 74xx280 P 50 74xx283 P 50 74xx290 P 51 74xx293 P 51 74xx298 P 51 vii viii 74xx30 P 52 74xx32 P 52 74xx33 P 53 74xx350 P 53 74xx351 P 54 74xx352 P 54 74xx353 P 55 74xx365 P 55 74xx366 P 56 74xx367 P 56 74xx368 P 57 74xx37 P 57 74xx373 P 58 74xx374 P 58 74xx375 P 59 74xx377 P 59 74xx378 P 59 74xx379 P 60 74xx38 P 60 74xx39 P 60 74xx390 P 61 74xx393 P 62 74xx395 P 63 74xx40 P 64 74xx42 P 64 74xx43 P 65 74xx44 P 66 74xx445 P 67 74xx45 P 68 74xx46 P 69 74xx465 P 70 74xx466 P 71 74xx47 P 71 74xx48 P 73 74xx51 P 74 74xx54 P 74
39. C 1 2 The Ground Component This component has 0 voltage and so provides a clear reference point for calculating electrical values You can use as many ground components as you want All terminals connected to ground components represent a common point and are treated as joined together Multisim User Guide C 1 senos Sources Sources Components C 2 C 3 C 3 1 C 2 Not all circuits require grounding for simulation however any circuit that uses an opamp transformer controlled source or oscilloscope must be grounded Also any circuit which con tains both analog and digital components should be grounded If a circuit is ungrounded or improperly grounded even if it does not need grounding in reality it may not be simulated If it is simulated it may produce inconsistent results The linear transformer must be grounded on both sides Digital Ground The digital ground is used to connect ground to the digital components which do not Y have an explicit ground pin The digital ground must be placed on the schematic but should not be connected to any component DC Voltage Source Battery Battery Background Information A battery may be a single electrochemical cell or a number of electrochemical cells wired in series It is used to provide a direct source of voltage and or current A single cell has a voltage of approximately 1 5 volts depending on its construction It con sists of a container of acid in which an el
40. DATA zwaspg DATA OUTPUT CLEAR CLK G1 G2 D Q X x x 0 o x x x Q0 0 1 x x Q0 0 X 1 x Q0 0 0 0 0 0 0 0 0 i 1 P 5 55 74xx174 Hex D type FF clr D type flip flop truth table CLEAR CER D Q Q 0 X X 0 1 1 F 0 1 0 0 1 1 0 x oo 00 Multisim User Guide P 29 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 56 74xx175 Quad D type FF clr D type flip flop truth table CLEAR CLK D Q Q 0 x x o a 1 l 0 1 0 0 1 1 o x oo Qo P 5 57 74xx180 9 bit Odd even Par GEN This 9 bit 8 data bits plus 1 parity bit parity generator checker features odd even outputs and control inputs to facilitate operation in either odd or even parity applications Parity generator checker truth table INPUTS OUTPUTS S OF H s S S AT A THRU H EVEN ODD EVEN ODD Even 1 0 1 0 Odd d 0 0 1 Even 0 1 0 1 Odd 0 1 1 0 x di 1 0 0 X 0 0 1 1 P 30 Electronics Workbench 74XX P 5 58 74xx181 Alu Function Generator ALU function generator truth table ACTIVE LOW DATA SELECTION M H M L ARITHMETIC OPERATIONS 83 2 81 so LOGIC Cn L Cn H FUNCTIONS NO CARRY WITH CARRY 0 0 0 0 F A F A MINUS 1 F A 0 0 0 1 F AB F AB MINUS 1 F AB 0 0 1 0 F A B F AB MINUS 1 F AB 0 0 al 1 EI F MINUS 1 2 s comp F Zero 0 1 0 F A B F A PLUS A B F A PLUS A4B Plus 1 0 1 0 1 F B F AB PLUS A B F AB PLUS A B PLUS 1 0 1 1 O F
41. L 5 1 3 Square waves In an ideal square wave the change takes place only at the rising and falling edges The change is instantaneous This instantaneous rate of change dV dT dV 0 Multisim User Guide L 9 O1U0D Controls Controls Components will produce an infinitely large output from a differentiator Since ideal square or pulse waveforms as produced by the function generator in Multisim have zero rise and fall times the result of differentiation is infinite dV 0 infinity In the example circuit outputs from the differentiator are limited to 5 kilo volts With the ideal square wave input the differentiator output will be seen to be 5kV All real square wave and pulse signals have finite rise times however small To introduce finite rise and fall times into the input to the differentiator in order to investigate realistic situations use an RC network placed in series with the function generator Note Since the rise and fall times are fixed the differentiator output does not change with change of input frequency as for the sine and triangle waveforms Changing the RC time constant and comparing differentiator output will illustrate this point OUTPUT Function Generator PTA ASAS LJ 1 Frequency Hz K Duycyle 50 E x Amplitude v amp Offset 30 30 Expand Ground Time base Trigger s Ede FEI Xposition 0 00 E Level oco Ig ra ans
42. Multiplexer truth table WORD CLK QA QB QC QD SELECT 0 7 al b1 cl al 1 n a2 b2 c2 da X 1 QA0 QBO QCO QDO s transition from high to low al a2 etc the level of steady state input at A1 A2 etc QAO QBO etc the level of QA QB etc entered on the most recent negative transition of the clock input P 5 96 74xx30 8 In NAND Logic function Y ABCDEFGH 8 input NAND gate truth table INPUTS A THROUGH H Y 0 1 All inputs 1 One or more inputs O0 P 5 97 74xx32 Quad 2 In OR This device contains four independent 2 input OR gates Logic function Y A B P 52 Electronics Workbench 74XX OR gate truth table P 5 98 74xx33 Quad 2 In NOR OC This device contains four independent 2 input NOR gates For correct performance the open collector outputs require pull up resistors Logic function Y MB NOR gate truth table P 5 99 74xx350 4 bit Shifter w 3 state Out This device shifts 4 bits of data to 0 1 2 or 3 places under control of two select lines 4 bit shifter truth table INPUTS OUTPUTS OE sl s vo vi v2 v3 1 X X Z Z Z Z 0 0 0 DO Di D2 D3 0 0 1 D 1 DO D1 D2 0 1 0 D 2 D 1 DO D1 0 T 1 D 3 D 2 D 1 DO Z High impedance off Multisim User Guide P 53 seues Xxv4 suonounJj Functions 74XX Series Functions 74XX series P 5 10074xx351 Dual Data Sel MUX w 3 state Out The 74351 device is made up of two 8 line to 1 line data select
43. Pmax 18 measured in watts from mW to kW V nax 18 measured in volts from mV to kV A bulb will burn out if the volt age across it exceeds V At that point the power dissipated in the bulb exceeds Pray u1 120v 100w J 4 4 Time Domain and AC Frequency Models The bulb is modeled by a resistor R V mak if Vab lt Vmax P max R if Vasl gt Vmax Vmax a lt max Teuer where the maximum voltage that can be applied across the bulb Vm ax the maximum power that can be dissipated by the bulb Pmax For AC circuits V ay is the peak value of the applied voltage not its RMS value Multisim User Guide J 3 SJO eolpu Indicators Indicators Components J 5 Hex Display J 5 1 Seven Segment Display The seven segment display actively shows its state while the circuit is running The seven terminals left to right respectively control segments a to g By giving the proper binary digit inputs to segments a to g you can display decimal numbers from 0 to 9 and letters A to F Truth table u1 DCD HEX a b c d e f g Digit displayed 0 0 0 0 0 0 0 none 1 1 1 T 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 1 2 1 1 1 1 0 0 1 3 0 1 1 0 0 1 1 4 1 0 1 l 0 1 1 5 1 0 1 1 1 1 1 6 1 1 1 0 0 0 0 7 1 1 1 1 1 1 1 8 1 1 1 1 0 1 1 9 1 1 1 0 1 1 1 A 0 0 1 1 1 1 1 b 1 0 0 1 1 1 0 C 0 1 1 1 1 0 JT d 1 0 0 1 1 1 1 E 1 0 0 0 1 1 1 F J 4 Electronics Workbench Hex Display
44. Reset and Turn on Saving sssaaa B2 19 B 2 1 7SILOS III Extensions to Verilog HDL 0 000s B2 19 B 2 1 7 1Global Variables 0 0 20 000 cee ee B2 20 B 2 1 7 2Global tasks and functions oococcocccococoo nenn B2 20 B 2 1 7 3Functions with multiple outputs lille B2 20 Multisim User Guide suoisueix3 JAH Bojan B 2 1 7 4Functions without any inputs llis B2 20 B 2 1 7 5Tasks and functions with ports declared like a module B2 21 B 2 1 7 6Procedural assignment to wires llle B2 21 B 2 1 7 7Continuous assignments to register and memory variables B2 21 B 2 1 7 8Continuous assignments using intra assignment non blocking delays oococccooooo B2 21 B 2 1 7 9Default state value for UDP 0 0 00 elles B2 22 B 2 1 7 10UDP additional states for High Z on inputs or output B2 22 B 2 1 7 11UDP edge for High Z illii B2 22 B 2 1 7 12UDP Multiple Edges in a Row llli B2 23 B 2 1 7 13Non Constant Specify Block Delays oooooooo o B2 23 B 2 1 7 14Parameter for Specify Block Delays o o o B2 23 B 2 1 7 15Stimulustable Extension liliis B2 23 B 2 1 7 16 input output inout declarations after the variable s declaration B2 24 B 2 1 7 17Using registers as module inputs llle B2 24 B 2 1 7 18Duplicate variable definitions 2222220 B2 24 B 2 1 7 19Parameter used for sizing
45. STORE BUSCON t1 TO t2 WTYPE NSTORE Electronics Workbench Silos III Command Line Usage Where TYPE optional Directs the bus contention report to standard STORE output or to a disk file BUS Generates a summary table of any contentions that have CON occurred between two time points t TO t2 Represent the minimum and maximum time point values over which contention is to be checked These time val ues must be within the logic simulation time point range If not specified the simulation time points will be used The keyword TO is optional Application Notes 1 Contentions are reported only for nodes where two or more enabled unidirectional devices or tri triand trior trireg tri0 and tril net types form a wired con nection often used to form a bus Bi directional transistors non enabled gates and gates without enable lines are ignored by the BUSCON report 2 Foreach contention the BUSCON command reports the starting and ending time points the starting and ending node states and the names of the enabled unidirectional devices or roh on on tri triand trior trireg tri0 and tril net types connected to the node Examples TYPE BUSCON 2K 100K nst busco B 2 2 4 Encrypting Library Files The CHGLIB command changes files of Verilog HDL modules and SILOS III macro defini tions from sequential access libraries to random access libraries The CHGLIB command can also be used to
46. The diode small signal conductance g and the small signal capacitance Cd are evaluated at the DC oper ating point E 7 4 SCR Parameters and Defaults Symbol Parameter Name Default Unit Irdm Peak off state current 1e 06 A Vdrm Forward breakover voltage 200 V Vtm Peak on state voltage 1 5 V Itm Forward current at which Vtm is measured 1 A Tq Turn off time 1 5e 05 s dv dt Critical rate of off state voltage rise 50 V us Ih Holding current 0 02 A Vgt Gate trigger voltage 1 V Igt Gate trigger current 0 001 A Vd Voltage at which Igt is measured 10 V E 8 DIAC A diac is a two terminal parallel inverse combination of semiconductor layers that allows triggering in either direction It functions like two parallel Shockley diodes 4N5758 aligned back to back The diac restricts current flow in both directions until the voltage across the diac exceeds the switching voltage Then the diac conducts cur rent in the direction of the voltage E 14 Electronics Workbench DIAC E 8 1 DC Model The diac is switched on and the resistance R is set low if in either the positive or negative direction Va gt Vs Vs The diac is switched off current blocking mode and R is set high Irev if in either direc tion Ta lt In where Va 7 voltage across the diac in volts la E current through the diac in amperes Rs blocking resistance l peak off state reverse current ev Other symbols
47. and metal results in very little junction capacitance 1080015 The Schottky diode will have a Vp of approximately 0 3 V and a Vpp of less than 50 V These are lower than the typical pn junction ratings of Vp 0 7 V and Vgg 2 1 50 V With very little junction capacitance the Schottky diode can be operated at much higher fre quencies than the typical pn junction diode and has a much faster switching time The Schottky diode is a relatively high current device that is capable of switching rapidly while providing forward currents of approximately 50 A It can operate at frequencies of 20 GHz and higher in sinosoidal and low current switching circuits Silicon Controlled Rectifier A silicon controlled rectifier SCR is a unidirectional current control device gt like a Shockley diode However the SCR has a third terminal capable of sup Yos porting a digital gate connection which adds another means of controlling the current flow The SCR switches on when the forward bias voltage exceeds the forward breakover voltage or when a current pulse is applied to the gate terminal The SCR is triggered into conduction by applying a gate cathode voltage VGK which causes a specific level of gate current G The gate current triggers the SCR into conduction The device is returned to its nonconducting state by either anode current interruption or forced commutation When the SCR is turned off it stays in a non conducting state until it r
48. clr llli P 77 74xx77 4 bit Bistable Latches 00 0000 c cee eee P 77 74xx78 Dual JK FF pre com clk amp Clr 2 2 0 0 eee P 77 74xx82 2 bit Bin Full Adder llle eee P 78 74xx83 4 bit Bin Full Adder 0 0 0 0 000 cece eee P 79 74xx85 4 bit Mag COMP oooococcccco een P 79 74xx86 Quad 2 InXOR 2 222m seen ens P 80 74xx90 Decade Counter 2 2 22 cee P 80 74xx91 8 bit Shift Reg 2 eee P 80 74xx92 Divide by twelve Counter 2 2 2222 P 81 74xx93 4 bit Binary Counter 2 222 n nennen eee P 82 Electronics Workbench Appendix P Functions 74XX Series P 1 Standard TTL The characteristics of the standard TTL series can be illustrated by the 7400 de er quad NAND gate IC The 74 series uses a nominal supply voltage Voc of 5V and can operate reli ably over the range 4 75 to 5 25 V The voltages applied to any input of a stan dard 74 series IC must never exceed 5 5 V The maximum negative voltage that can be applied to a TTL input is 0 5 V The 74 series IC is designed to operate in ambient temperatures ranging from 0 to 70 C The guaranteed worst case DC noise margins for the 74 series are 400 mV A standard TTL NAND gate requires an average power of 10 mV A standard TTL output can typically drive 10 standard TTL inputs P 2 Schottky TTL The basic circuitry of the standard TTL series forms the central part of several other TTL series
49. data DATA and Data a zA Z0 9 matches any name that has upper and or lower case characters and or digits for example data DATA Data 123 data1 a zA Z0 9_ matches any name that has upper and or lower case characters and or digits and or for example data DATA Data 123 data1 and DATA bus1 Some programming books such as AWK and Perl show regular expressions enclosed with slashes The SILOS III style of searching for regular expressions is a character search and forward slashes have no special meaning For example using the regular expression a to try to find any name that contains an a will find only the name a Regular expressions are not like the Unix style wildcards where matches any single char acter matches any pattern and list matches any character in list including ranges For example using the regular expression a to find any name that contains an a will not find any names TE If you want use regular expressions to find every name that has an a you can enter a For the above expression a means search for zero or more occurrences the first x of any character the first followed by a single character a followed by zero or more occurrences the second of any character the second So with the search a you could find
50. e Options Full Path Title e Options Data Tips B 3 9 1 Options Fonts Opens the Fonts screen for setting the fonts for the Data Analyzer window and the source windows B 3 9 2 Options Tabs Opens the Tabs screen for setting the number of spaces in the Tab Interval for the source win dows B 3 9 3 Options Snap to Edges When setting the T1 and T2 timing markers for the Data Analyzer they will snap to the near est edge if Options Snap to Edges is active When setting a timing marker you can hold down the shift key to temporarily toggle the Snap to Edges selection to its opposite effect Such as if Snap to Edges is not selected you can have the timing marker snap to the nearest edge when you set it by holding down the SHIFT key as you click on the left or right mouse button with the mouse indicator arrow in the Waveform Display window B 3 24 Electronics Workbench Window Menu B 3 9 4 Options Title Tips Enables the title tips for the signal names in the Data Analyzer The title tips show the full hierarchical path name for a signal B 3 9 5 Options Analog Integer Display Integer variables can be displayed as a vector type of waveform or as an analog waveform Options Analog Integer Display sets the method of displaying integers B 3 9 6 Options Full Path Title Turns on and off the full directory path for a source file B 3 9 7 Options Data Tips The Data Tips feature for displaying the value scope radix and si
51. e wobble stick illuminated Push button switches are momentary switches which need to be activated only for the dura tion during which the user manually acts on them Pilot Lights Multisim includes the following pilot lights non push to test e push to test Terminals Multisim includes the following terminals power terminals control terminals N O control terminals N C coil terminals Multisim User Guide N 3 eolueuoeuJ 0J199 3 Electro mechanical Electro Mechanical Components N 4 Electronics Workbench Appendix O Functions 4000 Series OH 3 CMOS karoa zinc ntt dud dunt aera nd dine Uns exe Biete SD E O 1 O 1 Power Supply Voltage oooocoococcccc e O 2 O 1 Logic Voltage Levels oooooooooooorroo eee O 2 O 1 Noise Margins noria bee e BIOS eu EHI e RE E O 2 O 1 Power Dissipation a anak aae E a Rm O 2 Q 2 4000 S rles IC S anna Dann Se RE DUE Seni ene Poeno es O 2 0 2 1 4000 Dual 3 In NOR and INVERTER sssss eese O 3 0 2 2 4001 Quad 2 In NOR coccccccocccoc nennen nennen nn 0 3 0 2 3 4002 Dual 4 InNOR 2 22m cece O 4 O 2 4 4007 Dual Com Pair Inv lisse O 4 O 2 5 4008 4 bit Binary Full Adder liliis eere O 4 0 2 6 4010 Hex BUFFER honen nennen nennen nennen een nn O 5 O 2 7 40106 Hex INVERTER Schimitt 0 0 0 0 0 nennen een nn 0 5 0 2 8 4011 Quad 2 In NAND 0000 0000 cee ee O 6 O 2 9 401
52. g P 0 7 P2 02 03 7 3 J 03 K 3 7 PE CP Multisim User Guide 14 EE sl 11 The 40195 device is a fully synchronous edge triggered 4 bit shift regis ter with a clock input CP four synchronous parallel data inputs PO to P3 two synchronous serial data inputs J K a synchronous parallel enable input PE buffered parallel outputs from all 4 bit positions OO to O3 a buffered inverted output from the last bit position O3 and an overriding asynchronous master reset input MR seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 26 4020 14 stage Bin Counter The 4020 device is a 14 stage binary ripple counter with a clock input CP an overriding asynchronous master reset input MR and twelve fully buffered outputs Op Oz to O13 MR O 2 27 4021 8 bit Static Shift Register The 4021 device is an 8 bit static shift register parallel to serial con verter with a synchronous serial data input Ds a clock input CP an asynchronous active HIGH parallel load input PL eight asynchronous parallel data inputs Pp to P7 and buffered parallel outputs from the last three stages Os to O7 O 2 28 4023 Tri 3 In NAND This device contains three independent 3 input NAND gates gt Logic function O I 1 13 id 7 O 16 Electronics Workbench 4000 Series ICs NAND gate truth table H ja H N H w o H
53. including the Schottky TTL 74S series The Schottky TTL the 74S series reduces the storage time delay by not allowing the transis tor to go as deeply into saturation The 74S series does this by using a Schottky barrier diode connected between the base and the collector of each transistor Circuits in the 74S series also use smaller resistor values to help improve switching times This increases the circuit average power dissipation to about 20 mV These circuits also use a Darlington pair to provide a shorter output rise time when switching from ON to OFF Multisim User Guide P 1 seues XXpyZ suonounJj Functions 74XX series Functions 74XX Series P 3 P 4 P 5 P 5 1 P 2 Low Power Schottky TTL The low power Schottky TTL the 74LS series is lower in power and slower in speed than the 74S series It uses the Schottky clamped transistor but with larger resistor values than the 74S series The larger resistor values reduce the power requirements of the circuit but increase the switching times A NAND gate in the 74LS series typically has an average propagation delay of 9 5 ns and an average power dissipation of 2 mW Tiny Logic Tiny Logic is a line of single function digital CMOS chips from Fairchild u which are intended for application which require only a single gate to com d plete the design as in the form of glue logic NC7 S00 74XX 74xx00 Quad 2 In NAND This device contains four indepe
54. isse Sone ered E ded DE D 15 D 9 1 The Component ces erie aged hh D 15 D 9 2 Characteristic Equation and Model 0 0 00 eee eee eee D 15 D 9 3 Virtual Variable Capacitor llli eese D 15 Variable Inductor 0 e E a E ne D 16 D 10 1The Componente oia a eia a a eh D 16 D 10 2Characteristic Equation and Model nasasa auaa aeaea D 16 D 10 3Virtual Variable Inductor ooooccocooocc eere D 16 Potentiometer aE paa a e AE T E trn D 17 Dalz The Component x 224 44 nie ae a A aR MR ani TRE D 17 D 11 2Characteristic Equation and Model ooococcocccoccoo D 17 D 11 3Virtual Potentiometer oooooccooocccooo re D 18 Pullu ae a a csetera A a e PRA te P ue BR oa D 18 Resistor Packs 3 2 gp a be a Ar IE D 18 Magnetic Core o oooocccco ehh hs D 18 D 14 1Characteristic Equation llli ee D 18 D 14 2Magnetic Core Parameters and Defaults ooooooococcoooo D 20 Coreless Goil 5 a el ee eee D 20 D 15 1Characteristic Equation 0 2 iliis D 21 D 15 2Coreless Coil Parameters and Defaults 00 000 c eee eee D 21 Electronics Workbench Appendix D Basic Components D 1 Connectors Tofofofofl T o or o or o DSUB15F Connectors are mechanical devices used to provide a method of inputting and outputting signals to a design They do not affect the simulation of the circuit but are included in the circuit for the design of the PCB
55. letters a to z the letter e g a Enter enter spacebar space N 2 Line Transformer T1 E AIR_CORE_INDUCTOR Multisim User Guide Line Transformers are simplified transformers intended for power applications where the primary coils is connected to either 120 or 220 VAC They will perform step up or step down functions plus several specialized functions of voltage and current measurement N 1 eo1uey9au 01 99 3 Electro mechanical Electro Mechanical Components N 3 N 4 N 5 N 6 N 2 Coils Relays 1 Multisim includes the following coils and relays cr motor starter coil como 14 forward or fast starter coil reverse starter coil slow starter coil control relay time delay relay Timed Contacts 81 Multisim includes the following timed contacts enormally open timed closed enormally open timed closed Key Space Protection Devices 81 Multisim includes the following protection devices u fuse FUSE overload overload thermal overload magnetic e ladder logic overload Output Devices 1 Multisim includes the following output devices m HEATER light indicator motor DC motor armature e 3 phase motor Electronics Workbench Push Buttons N 7 N 8 N 9 heater LED indicator e solenoid Push Buttons Multisim includes the following push button switches NO NC N O amp N C double circuit mushroom head
56. llle P 8 P 5 16 74xx113 Dual JK MS SLV FF edge pre 000 2 eee eee P 8 P 5 17 74xx114 Dual JK FF edge pre com clk amp Clr o ooooo o P 9 P 5 18 74xx116 Dual 4 bit latches clr 0 0 2 ee P 9 P 5 19 74xx12 Tri 3 In NAND OC 2 222222 essen P 10 P 5 20 74xx125 Quad bus BUFFER w 3 state Out o ooococcoooooo P 11 P 5 21 74xx126 Quad bus BUFFER w 3 state Out o ooccoocoooooo P 11 P 5 22 74xx132 Quad 2 In NAND Schmitt 2222222 P 11 P 5 23 74xx133 13 IN NAND o oooccccccocco eee P 12 P 5 24 74xx134 12 In NAND w 3 state OUb o ooooccooccoccco rc P 12 P 5 25 74xx135 Quad Ex OR NOR Gate coooocccoccccc lesen P 13 Multisim User Guide seues XXpyZ suonounJj Functions 74XX series P 5 26 P 5 27 P 5 28 P 5 29 P 5 30 P 5 31 P 5 32 P 5 33 P 5 34 P 5 35 P 5 36 P 5 37 P 5 38 P 5 39 P 5 40 P 5 41 P 5 42 P 5 43 P 5 44 P 5 45 P 5 46 P 5 47 P 5 48 P 5 49 P 5 50 P 5 51 P 5 52 P 5 53 P 5 54 P 5 55 P 5 56 P 5 57 P 5 58 P 5 59 P 5 60 P 5 61 P 5 62 P 5 63 P 5 64 P 5 65 P 5 66 P 5 67 74xx136 Quad 2 in Exc OR gate ooococcocccocc eee P 13 74xx138 3 t0 8D8C ooooooooccccco ee P 13 74xx139 Dual 2 to 4 Dec DEMUX 0000 eee P 14 74xx14 Hex INVERTER Schmitt 2 222222 eee eee ee P 14 74xx145 BCD to Decimal Dec ooococcccccoo eee P 15 74xx147 10 to 4 Priority Enc saena 0000
57. lo Ir D2 D2 10 m Lu Io Ded in which Izy is governed by 1 et l D V DAv Vo ar where D duty ratio of the switching device For the DCM bye n Vo Vi Vi 0 D D D2 y ILD i 2 Lx Fs For the critical condition between the CCM and the DCM of operations D2 1 D ILD ILcrit Vis Dx 2 Lx Fs For the CCM D 1 D Vi DiVi D3Vo Vi Ir Iterit IL Multisim User Guide OSIN K 9 Misc Misc Components The averaging behavior governed by the above equations is modeled using the built in Elec tronics Workbench analog behavioral modeling components The AC small signal model is automatically computed inside the program K 8 2 Boost Converter Parameters and Defaults Symbol Parameter Name Default Unit L Filter inductance 500 uH R Filter inductor ESR 10 ma Fs Switching frequency 50 kHz K 9 Buck Converter At This component is an averaging circuit model that models the averaging behavior of a step down DC to DC switching converter It is based on a 500H 5O0hm 50Hz unified behavioral model topology The topology models both small signal and large signal characteristics of this converter power stage The model can be used to simulate DC AC and large signal transient responses of switched mode power supplies operating in both the continuous and discontinuous inductor current conduction modes CCM and DCM respectively K 10 Electro
58. lt 1 Data lt 0100 Load 0100 into the counter walt for 50 ns Load lt 0 wait for 500 ns Load lt 1 Data lt 0000 Load 0000 into the counter walt for 50 ns Load lt 0 wait for 11000 ns walt End Process End stimulus Describing a State Machine This example demonstrates how to write a synthesizable state machine description using pro cesses and enumerated types The circuit a video frame grabber controller was first described in Practical Design Using Programmable Logic by David Pellerin and Michael Holley Prentice Hall 1990 A slightly modified form of the circuit also appears in the ATMEL Configurable Logic Design and Application Book 1993 1994 edition The circuit described is a simple freeze frame unit that grabs and holds a single frame of NTSC color video image This design description includes the frame detection and capture logic The complete circuit requires an 8 bit D A A D converter and a 256K X 8 static RAM A 4 2 1 Design Description A Video Frame Grabber Library ieee Use ieee std logic 1164 all Multisim User Guide A 27 JOWUd TAHA VDHL Prrimer VHDL Primer Entity CONTROL Is Port Reset in std ulogic Clk in std ulogic Mode in std ulogic Data in std ulogic vector 7 downto 0 TestLoad in std ulogic Addr out integer range 0 to 253243 RAMWE out std ulogic RAMOE out std ulogic ADOE out std _ulogic End CONTROL Archit
59. respectively before the etc most recent negative transition of the clock P 5 14774xx92 Divide by twelve Counter The 7492 counts from 0 to 11 in binary It contains four master slave flip flops and additional gating to provide a divide by two counter and a three stage binary counter for which the count cycle length is divide by six Counter truth table RESET INPUTS OUTPUT RO1 RO2 Qd Qc Qb Qa 1 1 0 0 0 0 Count X 0 Count Multisim User Guide P 81 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 14874xx93 4 bit Binary Counter P 82 The 7493 counts from 0 to 15 in binary It contains four master slave flip flops and additional gating to provide a divide by two counter and a three stage binary counter for which the count cycle length is divide by eight Binary counter truth table RESET INPUTS OUTPUT RO1 RO2 Qd Qc Qb Qa 1 F 0 0 0 0 0 X Count 0 Count Electronics Workbench Index Numerics 10 to 4 Priority Enc P 16 12 In NAND w 3 state Out P 12 12 stage Binary Counter O 24 13 In NAND P 12 13 input Checker Generator O 48 14 stage Bin Counter O 16 1 of 10 Dec O 20 1 of 16 Data Sel MUX P 17 1 of 16 Dec DEMUX w Input latches 4514 0 43 4515 0 44 1 of 8 Data Sel MUX P 18 2 bit Bin Full Adder P 78 2 wide 4 In AND OR INVERTER P 74 3 3 Input AND P 17 3 to 8 Dec P 13 3 to 8 line Dec DEMUX P 39 4000 series functions See func
60. silos executable on Unix If you are running from a directory other than the installation directory you can set a link to silos on Unix ln s installation path silos options is one or more command line options supported by SILOS III for more information An example of using command line options would be silos v examl udp v examl lib y library libext v examl v examl tst For the above example SILOS III will scan library files exam1 udp and exam1 lib and the v files in directory library and then input files exam1 v and examl tst Then SILOS III will automatically simulate the circuit report any errors and exit when there are no fur ther commands to be executed from the command line or from a file the sim error and exit commands do not have to be specified plusargs is one or more arguments for the testplusargs system task in Verilog HDL filename filename is the name of one or more input files for SILOS III The files can contain Verilog HDL at the behavioral gate and switch levels The files can also contain SILOS III commands Any SILOS III commands in the files will be exe cuted as they are encountered Mcommand command is one or more optional SILOS III com mands For information on how to use SILOS III commands in a file which may be sim pler than from the command line The is required for all SILOS III commands that are on the command line however the has a
61. the less positive voltage X state is immaterial positive going transition negative going transition 0 2 20 4018 5 stage Johnson Counter The 4018 device is a 5 stage Johnson counter with a clock input CP a Po 00 data input D an asynchronous parallel load input PL five parallel 7 r inputs PO to P4 five active LOW buffered outputs OO to O4 and an 2 E Ma E overriding asynchronous master reset input MR z ra 04 4o is Pt Ta MR ee 5 stage Johnson counter truth table Counter Connect D mode E Remarks Giviae By PP PP 10 04 8 03 6 02 no external com 4 OL ponents needed 2 00 9 03004 7 0203 AND gate needed 5 0102 counter skips 3 00e01 all HIGH states Multisim User Guide 0 13 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 21 4019 Quad 2 In MUX 9 L2 SL SL Ua 15 14 DEE al 2 The 4019 device provides four multiplexing circuits with common select inputs Sa Sp each circuit contains two inputs Ap Bp and one output 0 Multiplexer truth table SELECT INPUTS OUTPUTS Sa Sb AO BO 00 0 0 X X 0 T 0 0 X 0 L 0 1 X 1 0 I X 0 0 0 1 X 1 1 T I 1 X 1 L I X 1 1 al 1 0 0 0 0 2 22 40192 4 bit Dec Counter 00 01 02 03 L O 14 The 40192 device is a 4 bit synchronous up down decade counter with a count up clock input CPU a count dow
62. time domain model D 9 instruments ammeter J 2 bargraph J 6 buzzer J 7 hex display J 4 lamp J 3 probe J 3 voltmeter J 1 integrator about L 11 equations L 12 parameters and defaults L 13 J JFET_N F 15 L lamp about J 3 LED about E 8 parameters and defaults E 9 limiter about L 15 equations L 16 parameters and defaults L 16 line transformer N 1 linear transformer about D 10 equations D 11 parameters and defaults D 11 Look ahead Carry GEN P 31 lossless line type 1 K 17 lossless line type 2 K 18 Lossless transmission line parameters and default values K 18 lossy transmission line K 15 magnetic core D 18 magnetic relay D 13 misc digital components line driver H 9 line receiver H 9 line transceiver H 9 VHDL H 6 mode ammeter J 2 voltmeter J 1 model full wave bridge rectifier E 10 relay D 14 SCR E 13 triode vacuum tube K 5 model parameters opamps G 1 mono stable l 3 MOSFET about F 10 AC small signal model F 13 DC model F 12 depletion F 11 enhancement F 11 parameters and defaults F 14 time domain model F 13 motor K 2 multiplier about L 1 equations L 3 parameters and defaults L 3 N net K 18 nonlinear dependent source C 22 nonlinear transformer about D 12 customizing D 12 parameters and defaults D 13 Norton opamps G 8 N P N P N P transistor array F 10 O Octal BUFFER w 3 state Out P 40 74xx240 P 39 74xx244 P 40 74xx465 P 70 74xx466 P 71 Octal Bus Transceiver O 18 Octal D type FF P
63. with and functionally equivalent to TTL devices with the same number Many but not all functions that are available in TTL are also available in the 74C series It is possible then to replace some TTL circuits with an equivalent design The 74HC HCT series is an improved version of the 74C series It has a tenfold increase in switching speed compared to the 74LS devies and a higher output curre t capability than that of the 74C The 74HC HCT ICs are pin compatible with and functionally equivalent to TTL ICs with the same number 74HCT devices are electrically compatible with TTL but devices from the 74C series are not The 74AC ACT series often referred to as ACL for advanced CMOS logic is functionally equivalent to the various TTL series but is not pin compatible with TTL 74AC devices are not electrically compatible with TTL however the 74ACT devices can be connected directly to TTL The 74AC ACT series has advantages over the HC series in the areas of noise immu nity propagation delay and maximum clock speed The device numbering for this series dif fers from TTL 74C and 74HC HCT numbering The 74AHC is the newest series of CMOS devices The devices in this series are three times faster than and can replace the HC series devices Multisim User Guide O 1 seues 0007 suonouny Functions 4000 series Functions 4000 Series Power Supply Voltage The 4000 14000 series and 74C series devices can operate with V pp values r
64. with consideration for operating frequencies and slew rate or with specialized ICs such as the LM339 The comparator compares a reference voltage fixed or variable with an input waveform If the input is applied to the non inverting input and the reference to the inverting input lower circuit the comparator will be operating in the non inverting mode In this case when the input voltage is equal to or slightly less than the reference voltage the output will be at its lowest limit near the negative supply and when the input is equal to or slightly greater than the reference voltage the output will change to its highest value near the positive supply If the inverting and non inverting terminals are reversed upper circuit the comparator will operate in the inverting mode Multisim User Guide G 9 Bojeuy Analog Analog Components G 3 2 Comparator Simulation models The same levels of simulation model as the opamps are provided with several levels of simu lation models of increasing complexity and accuracy The following model levels are used to distinguish between these models e LI this is the simplest model with the opamp modeled as a gain block with a differential input and a single ended output 2 thisis a more complex model in which the supply voltages are included in the simu lation e L3 this is a model of increasing complexity where additional control pins are supported e L 4 this is the most comple
65. 0 0 0 0 0 BLANK Y 0 0 0 0 0 0 aL 1 1 T 1 0 0 1 0 0 0 0 0 1 0 di 1 0 0 0 0 JI 1 0 0 0 0 1 0 1 di 0 T I 0 1 2 1 0 0 0 0 1 i 1 l 1 d 0 0 1 3 1 0 0 0 1 0 0 0 1 al 0 0 1 1 4 1 0 0 0 1 0 i 1 0 al 0 1 1 5 1 0 0 0 1 i 0 1 0 1 i i 1 1 6 1 0 0 0 1 1 i 1 a 1 0 0 0 0 7 1 0 0 ES 0 0 0 1 Eh 1 4 Ed 1 1 8 1 0 0 1 0 0 1 1 d 1 Jd 0 1 1 9 1 0 0 1 0 T 0 0 0 0 0 0 0 0 BLANK 1 0 0 1 0 T 1 0 0 0 0 0 0 0 BLANK 1 0 0 1 1 0 0 0 0 0 0 0 0 0 BLANK 1 0 0 1 1 0 1 0 0 0 0 0 0 0 BLANK I 0 0 1 1 1 0 0 0 0 0 0 0 0 BLANK L 0 0 1 1 1 T 0 0 0 0 0 0 0 BLANK 0 0 0 X X X X as above 1 as above inverse as above as above 1 HIGH state the more positive voltage 0 LOW state the less positive voltage state is immaterial For liquid crystal displays apply a square wave to PH For common cathode LED displays select PH LOW For common anode LED displays select PH HIGH Depends upon the BCD code previously applied when LD HIGH Multisim User Guide O 51 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 86 4544 BCD to seven segment latch dec The 4544 BCD Binary Coded Decimal to seven segment latch decoder driver is designed for use with liquid crystal readouts It is constructed with complementary MOS CMOS enhancement mode devices The circuit provides the functions of a 4 bit storage latch and an 8421 BCD to seven segment decoder and driver 7 segment latch decoder driver truth table
66. 0 X X X 1 T 1 1 0 0 0 1 1 T EB 0 Toggle 1 T 0 1 Hold 1 1 il 1 1 0 1 J 0 X X Hold positive edge triggered P 5 14 74xx11 Tri 3 In AND This device contains three independent 3 input AND gates Logic function Y ABC Multisim User Guide P 7 sanas Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 15 74xx112 Dual JK FF edge pre clr AND gate truth table A B C Y 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 This device contains two independent J K negative edge triggered flip flops JK flip flop truth table PRE CLR CLK 0 HFRHrHHRHROH 1 HHHHHOo 7 X XxX c x xs X 0 1 0 1 x 0 negative edge triggered x Pr OOM mM Kl A OrOF O PrP Fr Oo Ol Toggle Hold 1 0 Hold P 5 16 74xx113 Dual JK MS SLV FF edge pre This device contains two independent J K negative edge triggered flip flops Electronics Workbench 74XX JK flip flop truth table PRE CLK J K o Q 0 X X X 1 0 I F 0 0 Hold J F T 0 d 0 I 0 T 0 i 1 1 1 1 Toggle 1 1 X X Hold negative edge triggered P 5 17 74xx114 Dual JK FF edge pre com clk amp clr This device contains two independent J K negative edge triggered flip flops JK flip flop truth table PRE CLR CLK 0 0 X J X X X X 0 1 0 T X RLRERRROR PREPRRPROO K Q Q X T 0 X 0 1 X al 1 0 Hold 0 Bl 0 1 0 1 1 Toggle X Hold negative edg
67. 0 for Vos Vro lt 0 Ip 2 B V Vro A AV ps for 0 lt Vas Vro lt Vps BW psl2 Vos Vro Vps1 1 AVps for lt Vps V4 Vro where Vas gate source voltage in volts Vos drain source voltage in volts Vap gate drain voltage in volts Ves ff gate source cutoff voltage in volts Ig X saturation current for the gate drain and gate source diode junctions Ip drain to source current in amperes lbss drain to source saturation current in amperes Ipss V 2 p as of transconductance parameter in A V channel length modulation parameter measured in 1 V Other symbols used in these equations are defined in JFET Model Parameters and Defaults Electronics Workbench JFETs Junction FETs Note Pis not to be confused with g the AC small signal gain mentioned later in this chap ter The charge storage occurring in the two gate junctions is modeled by the diode time domain model described in the Diodes Parts Bin chapter The diodes used to model the JFETs are represented by their small signal models dlp gn OP dVas dlp gps op dVps dlcs gas op dVas Qcp OP dVap where Om AC small signal gain gps small signal forward admittance or transconductance ggs and ggp are normally very small because the diode junctions are not forward biased Igs and Igp are the diode current expressions mentioned in the diode modeling section Multisim User Gu
68. 01 02 03 Da 05 06 07 os Ds sl al al 0 al lola m 5 Four of these six non inverting buffers Il through I4 are enabled by a high on ENI and the last two I5 and I6 are enabled by a high on EN2 Buffer gate truth table Z High impedance X Don t care O 2 70 4508 Dual 4 bit latch DATA AD A1 A2 pepe RESET Qo WR_DISABLE 01 Q2 Q3 G4 Qs Qe 97 FEE alo lalalala Multisim User Guide This device contains two independent 4 bit latches O 39 seues 000p suonounJ Functions 4000 series Functions 4000 Series 4 bit latch truth table INPUTS OUTPUTS MR ST EO Dn On 0 1 0 1 1 0 1 0 0 0 0 0 0 X LATCHED J X 0 X 0 X X 1 X Z O 2 71 4510 BCD up down Counter O 40 PO P1 P2 P3 PL i E WD MR 00 01 02 03 Tol al al Y n gll e BCD up down counter truth table MR PL UP DN CE CP MODE 0 1 x X X PARALLEL LOAD 0 0 x 1 x NO CHANGE 0 0 0 0 COUNT DOWN 0 0 1 0 COUNT UP 1 x x x x RESET Electronics Workbench 4000 Series ICs O 2 72 4511 BCD to seven segment latch Dec The 4511 BCD Binary Coded Decimal to seven segment latch decoder um DA OA un translates a 4 bit BCD input into hexadecimal and outputs high on the ze j output pins corresponding to the hexadecimal representation of the BCD E i o input There are provisions
69. 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 Y 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 E 1 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 1 0 1 0 ji j 1 1 1 1 0 1 1 1 1 j P 78 Electronics Workbench 74XX P 5 14274xx83 4 bit Bin Full Adder This device performs the addition of two 4 bit binary numbers It features full internal look ahead across all four bits generating the carry term in ten nanoseconds typically P 5 14374xx85 4 bit Mag COMP This 4 bit magnitude comparator performs comparison of straight binary and straight BCD 8 4 2 1 codes 4 bit magnitude comparator truth table COMPARING CASCADING INPUTS INPUTS OUTPUTS A3 B3 A2 B2 Al B1 A0 BO A gt B A lt B A B A gt B A lt B A B A3 gt B3 X X X X X X 1 0 0 A3 lt B3 X X X X X X 0 1 0 A3 B3 A2 gt B2 X X X X X 1 0 0 A3 B3 A2 B2 X X X X X 0 1 0 A3 B3 A2 B2 A1 gt B1 X X X X 1 0 0 A3 B3 A2 B2 Al lt Bl X X X X 0 1 0 A3 B3 A2 B2 Al1 B1 A0 5BO X X X 1 0 0 A3 B3 A2 B2 A1 B1 AO BO X X X 0 1 0 A3 B3 A2 B2 Al B1 AO BO 1 0 0 1 0 0 A3 B3 A2 B2 Al B1 AO BO 0 1 0 0 1 0 A3 B3 A2 B2 Al B1 AO BO 0 0 1 0 0 1 A3 B3 A2 B2 Al B1 AO BO X X 1 0 0 1 A3 B3 A2 B2 Al B1 AO BO 1 1 0 0 0 0 A3 B3 A2 B2 Al B1 AO BO 0 0 0 1 alt 0 A3 B3 A2 B2 Al B1 AO BO 0 1 1 0 1 1 A3 B3 A2 B2 Al B1 AO BO 1 0 1 1 0 1 A3 B3 A2 B2 Al B1 AO BO 1 1 1 1 1 1 A3 B3 A2 B2 Al B1 AO BO T 1 0 1 1 0 A3 B3 A2 B2 Al B1 AO BO 0 0 0 0 0 0 Mult
70. 100 This will reject any pulse whose width is less than n percent of the module path delay For pulse e n n specifies a number in the range 0 100 This will flag as an error and drive unknown x any path pulse whose width is less than n percent of the module path delay but whose width is greater than pulse r For more information see PATHPULSES in the IEEE 1364 Verilog HDL manual e pulse quiet command ine argument suppresses warning messages generated by pulse e command line argument suppressredef This option will suppress the warning message for redefinition of define macros suppressfloat This option will suppress the warning message for floating nodes which may be caused by a gate input not having a driver or by declaring a variable as a wire and then never assigning a value to it e timing checks This option turns on all timing checks for fault simulation This will slow down the fault simulation and increase the memory used by fault simulation e xl order Specifies a switch so that the order of evaluation for always blocks is the same order as for Verilog XL This switch may be useful for obtaining the same simula tion results as Verilog XL This option must be parsed before any modules are parsed This option automatically enters define xl order 1 An example would be the order of evaluation for always Gposedge clock always Gposedge clock SILOS III also supports the following SI
71. 14 9 If two signs are specified on the table header then the delay values are relative to the time the stimulus table is started very much like delay values in a fork join statement For exam ple 10 time 10 table inl in2 out strobe 122 00 00 ff time 11 2 1 6 Oe Oa f6 time 11 6 2 1 ff ff 00 time 12 1 To have each delay value represent absolute time start the stimulustable at time 0 For example initial begin stimulustable s1 table inl in2 out strobe 1 2 00 00 ff time 1 2 1 6 Oe Oa f6 time 1 6 Qed ff ff 00 time 2 1 Note that mixing of both delay styles in the same stimulus is not allowed B 2 1 3 5Memory Utilization Data specified in tables is not stored in RAM so as to reduce memory used when there is a large pattern Electronics Workbench Verilog HDL Extensions B 2 1 3 6Strobe Expected value information is conditioned by a strobe When the strobe is high the variable must agree with the data in the column as follows mod gt 0 gt don t care gt High impedance strength 0 1 or x NxM OF A AN A A The expected value check is engaged when the stimulustable statement begins execution and persists through one strobe cycle following the conclusion of the stimulustable statement During engagement of the expected value check a high positive strobe is required to check that the variable agrees with the expected value data To prevent possible race condit
72. 2 INXOR ooooocococco e O 28 4071 Quad 2 In OR oococcccccc nes O 29 4072 Dual 4 In OR 2 22m sense ae O 29 4073 Tri 3 InAND o ooococcccoc RR II e O 30 4075 Tri 3 In OR as cis RE ann ERE na O 31 4076 Quad D type Reg w 3 state Out 2 2222er O 31 4077 Quad 2 In XNOR oooccoocccococ seh O 32 4078 8 IN NOR iss 42 4 Susan aan a PRERPE3 O 32 4081 Quad 2 In AND oococcocccco se O 33 4082 Dual 4 In AND 2 22 comes III O 33 4085 Dual 2 Wide 2 In AND OR INVERTER 20 00 O 34 4086 4 Wide 2 In AND OR INVERTER sssseeeesereess O 36 4093 Quad 2 In NAND Schmitt oooococcooccccccooo ee O 36 4094 8 stage Serial Shift Register ooooooooocooocommo O 37 4099 8 bit batch esa ei danae a a eg PUITS O 38 Electronics Workbench O 2 68 O 2 69 O 2 70 O 2 71 O 2 72 O 2 73 O 2 74 O 2 75 O 2 76 O 2 77 O 2 78 O 2 79 O 2 80 O 2 81 O 2 82 O 2 83 O 2 84 O 2 85 O 2 86 O 2 87 O 2 88 O 2 89 4502 Strobed hex INVERTER oooccccccccoc eee O 38 4503 Tri state hex BUFFER w Strobe 000 0c e ee eens O 39 4508 Dual 4 bitlatch ooooococcocccoo ee O 39 4510 BCD up down Counter ooocccoccccoo eee O 40 4511 BCD to seven segment latch Dec o ooooccoccococcconoo O 41 4512 8 In MUX w 3 state OUb o ooooococcoooccno ee O 42 4514 1 of 16 Dec DEMUX w Input latches ooocoo ooooo O 43 4515
73. 21 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series Data selector multiplexer truth table STROBE COO O H al SELECT A B X 0 0 1 1 x M FH Oo p H O b x x w OUTPUT Y ohohrh P 5 43 74xx159 4 to 16 Dec DEMUX OC This 4 line to 16 line decoder uses TTL circuitry to decode four binary coded inputs into one of sixteen mutually exclusive open collector outputs when both the strobe inputs are low P 22 The demultiplexing function is performed by using the 4 input lines to address the output line passing data from one of the strobe inputs with the other strobe input low Decoder demultiplexer truth table INPUTS OUTPUTS Gl G2 D C B AJO 1 a 3 4 5 6 7 8 9 10 11 12 13 14 15 o aaa 704 c0 Ar 2 eho Lak d ECCE d TEE A 9 s coss d e cO xk X Xo do Lob Cd ck Cl dy Lo SE D d Bor de DO Ok Dee d0s We GE do OLD doc de CE CY ode Xe 324 O 9 son Us aes xb d s0y Xe b a do deck Ole do Xe A Ins od r ua OA LOL ho dede us 700 CES o te CE Xo E ES box 6 ua xb UO LEO GER A nb or GLO Ge dee CE O4 CES SEXE Go ul XE O Xs 20 do A 0o A deo X OE OG LE cb OX ga uds E EV cde Lo Wood Gb CO c X CE OX cd E Dei Go uec 00 X 29 de GLO HD Cd mo OI A do ES sb OX Go ux Uu 0 0 EFE o4 4d dno X d 7d do d OE d EA Q QI um QE de Ih dno dn Xo X X X X o9 od ur X a d PES Oe CER A dh b a d d D CX 207 des G0 at gag ECEES IBN vU dee he decode uod E
74. 3 LV V pk Other items are defined in Triode Vacuum Tube Parameters and Defaults K 4 2 Model The dynamic characteristic of the triode vacuum tube is modeled by its DC characteristic with three capacitances Cgk Cpk and Cgp which are associated interelectrodes Multisim User Guide K 5 OSIN Misc Misc Components K 4 3 Triode Vacuum Tube Parameters and Defaults K 5 Symbol Parameter name Default Unit Vpk Plate cathode voltage 250 V Vgk Grid cathode voltage 20 V Ip Plate current 0 01 A m Amplification factor 10 Cgk Grid cathode capacitance 2e 12 F Cpk Plate cathode capacitance 2e 12 F Cgp Grid plate capacitance 2e 12 F Voltage Reference x u The output voltage of the Zener reference diode is set at approximately 6 9 V AD584 JH and requires a high voltage supply The band gap voltage reference diode has a significant advantage over the Zener reference diode in that it is capable of a lower minimum operating current and has a sharper knee The band gap reference relies on matched transistors and is therefore easily integrated along with biasing buffer and amplifier circuitry to give a complete reference diode The LM285 LM385 series are examples of micropower two terminal band gap voltage refer ence diodes These devices are designed to operate over a wide current range of 10 UA to 20 mA The features of these devices include exceptionally low dynamic impedance l
75. 3 state outputs RS latch truth table EO Sn Rn On 0 X X Z 1 0 1 1 1 X 0 0 E 1 1 Latched O 2 48 4049 Hex INVERTER This device contains six independent INVERTER gates De Logic function OQ I INVERTER gate truth table O 26 Electronics Workbench 4000 Series ICs O 2 49 4050 Hex BUFFER This device contains six independent BUFFER non inverting gates 3 Logic function Y cA BUFFER gate truth table A Y 0 0 1 1 0 2 50 4066 Quad Analog Switches The 4066 device has four independent bilateral analogue switches trans mission gates Each switch has two input output terminals Y Z and an active HIGH enable input E When the C input is high the input outputs A and B will pass either dig ital or analog signals in either direction Multisim User Guide O 27 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 51 4068 8 In NAND Logic function 2 3 37 Oy KEBREILIIH 5 13 8 o J 11 12 NAND gate truth table ol 0 INPUTS I0 THROUGH I7 All inputs 1 One or more inputs O 2 52 4069 Hex INVERTER This device contains six independent INVERTER gates po Logic function A Y INVERTER gate truth table A Y 0 r i 0 O 2 53 4070 Quad 2 In XOR This device contains four independent 2 input EXCLUSIVE OR gates 1 p Logic function Y A0B O 28 Electronics Workbench 4000 Series ICs
76. 4001 Quad 2 In NOR This device contains four independent 2 input NOR gates 1 2 Logic function O1 I I NOR gate truth table HH oo o oo oh 0 1 0 1 Multisim User Guide O 3 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 3 4002 Dual 4 In NOR This device contains four independent 4 input NOR gates Logic function y S spes O1 I 1 13 1 On I I 17 1g3 NOR gate truth table om MM FR oO x PM Hn rx O p n x x Oo x M x Hooo6o O 2 4 4007 Dual Com Pair Inv This device is a dual complementary pair and an inverter with access to each device It has three n channel and three p channel enhancement mode MOS transistors O 2 5 4008 4 bit Binary Full Adder This device is capable of adding two 4 bit binary numbers together 13 a S3 Logic function 1 45 3 12 31 s2 ze 1 S CIN GA CB ua EP C AB BCOUT ACOUT 7 10 g so 9 CIN cauT O 4 Electronics Workbench 4000 Series ICs 4 bit binary adder truth table INPUTS OUTPUTS CIN A1 B1 A2 B2 A3 B3 A4 B4 COUT x PM MM OX x MM NM MF x PM MM OX P4 MM P4 H M x PM MM H b4 bd b4 b b M P Do p MP PR B4 bd kt bd bd bd x PM PPR ORPRRR 0 2 6 4010 Hex BUFFER This device contains six independent BUFFER gates pol Logic function Y A BUFFER gate truth table A Y 0 0 1 1 0 2 7 40106 Hex INVERTER Schmitt T
77. 4040 device is a 12 stage binary ripple counter with a clock input 10 3 qi o ce o0 CP an overriding asynchronous master reset input MR and twelve fully si se X buffered outputs Og to O41 11 5 Ms G El 12 stage binary counter truth table 05 Ed 4 ME CP MR o0 011 O8 E i 0 Count os t 1 0 010 KEN 011 O 24 Electronics Workbench 4000 Series ICs O 2 44 4041 Quad True Complement BUFFER This device provides both inverted and non inverted buffered outputs for each 3 2 input I Logic function QE T O I Buffer gate truth table lo o 0 0 1 del 0 0 2 45 4042 Quad D latch This device contains four independent D latches f o 00 D latch truth table 7 700 ha Bf n o1 Le En El On 13 11 92 0 0 0 Dn o2 L 14 0 1 Latched 03 03 rs 5 03 I 1 0 Latched 5750 1 1 Dn Set Multisim User Guide O 25 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 46 4043 Quad RS latch w 3 state Out pop 42 1 14 15 00 0 2 47 4044 This device contains four independent RS latches with 3 state outputs RS latch truth table EO Sn Rn On 0 X X Z 1 0 1 0 1 1 X 1 1 0 O Latched Quad RS latch w 3 state Out AAA 90 R 781 R1 52 R2 53 R3 EQ 00 02 03 9 01 o 1 13 1 This device contains four independent RS latches with
78. 49 FF edge P 58 FF w en P 59 Flip flop O 24 Transparent Latches P 58 Octal Inv Buffer O 18 Octal Non inv Buffer O 18 Octal Trans Latch O 23 opamps 3 terminal about G 3 5 terminal interstage G 7 output stage G 7 about G 1 ideal model G 1 model parameters G 1 optocoupler K 4 oscillator voltage controlled sine wave C 8 voltage controlled square wave C 10 voltage controlled triangle wave C 12 output device types of N 2 Electronics Workbench P Parallel load 8 bit Shift Reg 74xx165 P 27 74xx166 P 27 parameters and defaults bipolar junction transistors F 6 comparator G 10 current limiter block L 18 diac E 16 differentiator L 11 diodes E 5 divider L 5 full wave bridge rectifier E 11 GaAsFET F 21 integrator L 13 LED E 9 limiter L 16 linear transformer D 11 MOSFET F 14 multipliers L 3 nonlinear transformer D 13 opamps G 1 SCR E 14 three way summer L 23 transfer function block L 7 triode vacuum tube K 6 voltage gain block L 8 voltage hysteresis block L 14 voltage slew rate block L 21 voltage controlled limiter L 20 zener diode E 8 passive components capacitors see also capacitors D 4 crystal K 1 inductors see also inductors D 7 linear transformer see also linear transformer D 10 nonlinear transformer see also nonlinear transformer D 12 relay see also relay D 13 resistors see also resistors D 2 Multisim User Guide piecewise linear current source C 18 piecewise
79. 74xx55 P 74 74xx69 P 75 74xx72 P 75 74xx73 P 75 74xx74 P 76 74xx75 P 76 74xx76 P 77 74xx77 P 77 74xx78 P 77 74xx82 P 78 74xx83 P 79 74xx85 P 79 74xx86 P 80 74xx90 P 80 74xx91 P 80 74xx92 P 81 74xx93 P 82 fuse K 14 G GaAsFET about F 19 equations F 19 parameters and defaults F 21 gain See voltage gain block general purpose high current N P N transistor array F 10 general purpose P N P transistor array F 10 generator sine wave C 9 square wave C 7 triangle wave C 13 ground C 1 H Hex BUFFER 4010 O 5 4050 O 27 Hex BUFFER OC 74xx07 P 5 74xx17 P 28 Hex Buffer Driver w 3 state 74xx365 P 55 74xx367 P 56 hex display Electronics Workbench about J 4 Hex D type Flip flop O 12 Hex D type FF clr P 29 w en P 59 Hex INVERTER OC 74xx05 P 4 OC 74xx16 P 23 Schmitt 40106 O 5 Schmitt 74xx14 P 14 4049 O 26 4069 O 28 74xx04 P 3 Buffer Driver w 3 state 74xx366 P 56 Buffer Driver w 3 state 74xx368 P 57 Hex INVERTER OC P 4 hysteresis block about L 13 parameters and defaults L 14 IBEW components coils N 2 output devices N 2 pilot lights N 3 protection devices N 2 relays N 2 switches D 1 timed contacts N 2 IEEE standard 1076 A 1 IEEE standard 1076 3 A 24 IEEE standard 1076 3 numeric standard A 2 IEEE standard 1076 4 VITAL A 2 IEEE standard 1164 A 1 IGBT IGBT F 21 inductor virtual D 10 inductors about D 7 Multisim User Guide AC frequency model D 10 DC model D 8 equations D 8
80. A 3 with a simple 8 bit loadable shift register The shift register will allow a detailed exami nation of how behavior level VHDL can be written for synthesis The two subcircuits the shifter and comparator will be connected using VHDL s hierarchy features and will demonstrate the third level of abstraction structure The complete circuit is shown below This diagram has been intentionally drawn to look like a hierarchical schematic with each of the lower level circuits represented as blocks In fact many of the concepts to be covered dur ing the development of this circuit are familiar to users of schematic hierarchy These con cepts include the ideas of component instantiation mapping of ports and design partitioning In a more structured project environment you would probably enter a circuit such as this by first defining the interface requirements of each block then describing the overall design of the circuit as a collection of blocks connected together through hierarchy at the top level Later after the system interfaces had been designed you would proceed down the hierarchy using a top down approach to design and fill in the details of each subcircuit In this example however each of the lower level blocks will be described and then they will be connected to form the complete circuit A 2 6 2 Comparator Dataflow The comparator portion of the design will be identical to the simple 8 bit comparator already shown The on
81. A transfer function up UY TWV to the third order can be directly modeled This component may be used in DC AC and transient analyses Characteristic Equation This transfer function model is defined in a form of the rational function YG _ a AS As AS A X s B s B s Bis B T s Transfer functions up to the third order may be modeled In the example shown below the transfer function for a simple first order low pass filter is used Only the numerator and denominator constants AO and BO are required in this case These are equal to two pi times the cutoff frequency first pole The cursor on the Bode Plotter may be used to confirm first order performance with 3dB at 10kHz and rolloff of 6dB per octave above 20kHz Al 10kHz Lowpass P vi Qs 1 v1 kHzi Deg Bode Plotter Magnitude Phase Save m Vertical Horizontal em em FL oe E Fio EY fae Hl 1 20 ae iho E 3 010dB EE ES 10 00kHz n Ou Electronics Workbench Voltage Gain Block L 3 2 Transfer Function Block Parameters and Defaults Symbol Parameter Name Default Unit Vloff Input voltage offset 0 V K Gain 1 V V VINT Integrator stage initial conditions 0 V w Denormalized corner frequency 1 A3 Numerator 3rd order coefficient 0 A2 Numerator 2nd order coefficient 0 A1 Numerator 1st order coefficient 0 AO Numerator constant 1 B3 Den
82. Addr out integer range 0 to 253243 RAMWE out std ulogic RAMOE out std ulogic ADOE out std ulogic End Component Constan Top Signal Signal Signal Signal Signal t PERIOD time 100 ns level signals go here Reset std ulogic Clk std ulogic Mode std ulogic Data std ulogic vector 7 downto 0 TestLoad std ulogic Signal Addr integer range 0 to 253243 Signal Signal Signal Signal Begin DUT RAMWE std ulogic RAMOE std ulogioc ADOE std _ulogic done boolean false CONTROL Port Map Reset Reset Clk gt Clk Mode gt Mode Data gt Data TestLoad gt TestLoad Addr gt Addr RAMWE gt RAMWE RAMOE gt RAMOE ADOE gt ADOE Js Clock1 process variable clktmp std ulogic 0 begin wait for PERIOD 2 clktmp not clktmp Clk lt clktmp Attach your clock here Multisim User Guide A 31 dwd TAHA VDHL Prrimer VHDL Primer if done true then wait end if end process Stimulusl Process Begin Sequential stimulus goes here Reset lt L Mode lt 0 Data lt 00000000 TestLoad lt 0 wait for PERIOD Reset lt 0 wait for PERIOD Data lt 00000001 wait for PERIOD Mode lt 1 Check to make sure we detect the vertical sync Data lt 00000000 for i in 0 to 127 loop wait for PERIOD end loop Now sample data to make sure the frame counter works Data l
83. B BUFFER gate truth table A Y 0 0 1 1 P 5 8 74xx08 Quad 2 In AND This device contains four independent 2 input AND gates Logic function AND gate truth table P 5 9 74xx09 Quad 2 In AND OC This device contains four independent 2 input AND gates For correct performance the open collector outputs require pull up resistors Logic function Y AB Multisim User Guide P 5 sanas Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 10 74xx10 Tri 3 In NAND P 5 11 74xx100 8 Bit Bist Latch The 74100 is an 8 bit bistable latch 8 bit bistable latch truth table AND gate truth table This device contains three independent 3 input NAND gates Logic function Y ABC NAND gate truth table A B C Y 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 INPUTS OUTPUTS D ejo o 0 1 0 1 1 1 1 0 X 0 QO 00 Electronics Workbench 74XX P 5 12 74xx107 Dual JK FF clr This device is a positive pulse triggered flip flop It contains two independent J K flip flops with individual J K clock and direct clear inputs JK flip flop truth table CIR cLK J Klo 2 0 X X X 0 1 Ji 0 0 Hold 1 d 0 d 0 1 0 4 0 1 T 1 T Toggle P 5 13 74xx109 Dual JK FF edge pre clr This device contains two independent J K positive edge triggered flip flops JK flip flop truth table PRE CLR CLK 3 Klo Q 0 T X X X 1 0 1 0 X X X 0 1 0
84. B3 32 B 3 12Pop up Menus ix dxsnb Dex Msn Debe un AO B3 32 B 3 12 1Explorer Window llle B3 33 B 3 12 1 1 Add Signals to Analyzer llllsielies elles B3 33 B 3 12 1 2Name Filter lille B3 33 B 3 12 1 3Copy Scope oooooccocccco res B3 35 B 3 12 1 4Go to Module SourCe oooooccoccooccnc nenn B3 35 B 3 12 1 5Go to Scope Menu Selecti0N o ooooooccooccnoo B3 36 B 3 12 1 6Properties cec rp ta a UE E B3 36 B 3 12 2Watch Window ei 2 22 22 202 2 BR ee an ud RE UE Be B3 37 B 3 12 2 1Add Signal Expression liliis en B3 37 B 3 12 2 2Set Value For Watch Window lesse lessen B3 37 B 3 12 2 3Free Forced Wire For Watch Window lusus B3 37 B 3 12 2 4Clear All For Watch Window 0000 0c eee ee B3 37 B 3 12 3Data Analyzer Pop up MenuS 00 0 eee eee B3 37 B 3 12 3 1 Data Analyzer Timeline Area llle B3 37 B 3 12 3 2Data Analyzer Signal List Box 2222er seen B3 39 B 3 12 4Source Window Pop up Menus 2 222m nennen eee B3 43 B 3 12 41UN00 iie RE AR Re dada we B3 43 B 3 12 4 2 Cube eter voee sett ag Ie Er E LIES AD Eg ne B3 43 B 3 12 4 3C0DV zur 2 pee ere a AA B3 43 B 3 12 4 4Paste 2 0 rn B3 44 B 3 12 4 5Add Remove Breakpoint 20 0c cece nenn B3 44 B 3312 4 6Dala Tips s vice are a Eke peeled en B3 44 B 3 12 4 7Data Tip Radix 2 ee B3 44 Multisim User Guide snus 111 SOS Silos II Menus Elec
85. Bo 0 0 0 0 0 0 HIGH state the more positive voltage o Il LOW state the less positive voltage state is immaterial Multisim User Guide O 55 seues 000p SUONDUNY Functions 4000 series Functions 4000 Series O 56 Electronics Workbench Appendix P Functions 74XX Series P 1 P 2 P 3 P 4 P 5 Standard TE cerro ra AA ape P 1 SChOHkKy T TEC Lee ce Md cri dd d P 1 Low Power Schottky TTL oooocccccccoococn nen P 2 Tiny LOGIC uo MEM Iur eure Dr ae E INA be ee ae P 2 TOO AA E bey Bae eT pepe a E sees P 2 P 5 1 74xx00 Quad 2 InNAND 2 2 2 2 nun nennen eee P 2 P 5 2 74xx02 Quad2 In NOR 0000 cee ee P 3 P 5 3 74xx03 Quad 2 In NAND LS OC sslsslssslseresnen P 3 P 5 4 74xx04 Hex INVERTER 00 0000 e rn P 3 P 5 5 74xx05 Hex INVERTER OC 2 0 000 cece eren P 4 P 5 6 74xx06 Hex INVERTER OC ooocccccccccncn eres P 4 P 5 7 74xx07 Hex BUFFER OC ooococcccccccncc rennen nenn P 5 P 5 8 74xx08 Quad 2 In AND raneren a iaaa nennen nn P 5 P 5 9 74xx09 Quad 2 In AND OC oocccccccccncc ee P 5 P 5 10 74xx10 Tri 3 In NAND ooccccccccccc eR m RI rn P 6 P 5 11 74xx100 8 Bit Bist Latch ooocoooocccnccncc ee P 6 P 5 12 74xx107 Dual JK FF clr 0 2 0 0c IR P 7 P 5 13 74xx109 Dual JK FF edge pre clr liliis P 7 P 5 14 74xx11 Tri 3 In AND nene a eee P 7 P 5 15 74xx112 Dual JK FF edge pre clr
86. Current Source llli eee C 8 Current Controlled Current Source se C 8 Voltage Controlled Sine Wave 0000 cece C 8 GC 16 1 The Component iir rele e Oe aia x De ee ale Peas oS C 8 Multisim User Guide senos Sources C 17 C 18 C 19 C 20 C 21 C 22 C 23 C 24 C 25 Cd62Example eo A le SNA C ere LN s C 9 Voltage Controlled Square Wave o ooooocccccccoc ese C 10 C47 rhe Component 1 see Gan eR a A e ana Pee ewe bes C 11 GA 7 2bxample ox Eee ved e ore X m eee EEE C 11 Voltage Controlled Triangle Wave o ooooccccccocccnoc nenn C 12 C 18 1The Component essens e pe ma ia n C 13 O 18 2bxampl i e mE RR Ue bt ee deed ERU ta C 13 Voltage Controlled Piecewise Linear Source lll cece eee eee C 14 Piecewise Linear Source o ooooccoccoccc es C 15 C 20 1The Component ooocco s C 15 2 20 14 Example riim mass A C 16 C 20 1 2Input Text File Specification llli C 16 C 20 1 3Special Considerations 22222222 essen een een C 17 C 20 2Piecewise Linear Voltage Source llli ilie C 18 C 20 3Piecewise Linear Current Source 2 222er een nn C 18 Pulse Souree ix ost br Dia nie EUIS E EHE ERA C 18 C 21 1Pulse Voltage Source 0 0 0 ses C 19 C 21 2Pulse Current Source o ooccococcooococ ese C 20 Polynomial SOurce 44 2 veda tae 2 2 en Pace ra era ie C 20 C 22 1 Output Voltage Characteristic Equati0N o ooooooooo oo C 20 E
87. Multisim User Guide Represents one of the state type codes for the OUTPUT POUTPUT and probe reports and for the CLK and PAT TERN stimulus specifications state default report symbol default stimulus char Supply Low 0 0 Supply Unknown x Supply High 1 1 Supply High Voltage 1 Driving Low 0 Driving Unknown Driving High 1 Driving High Voltage 1 Resistive Low 0 Resistive Unknown Resistive High 1 Resistive High Voltage 1 High Z Low High_Z Unknow High Z High N N N N High Z High Voltage B 2 53 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 54 sc The following symbols are used only in the output reports No symbol can be defined to input these states for CLK or PATTERN stimulus State Symbols State Default Report Symbol Default Stimulus Char 0 Uncertain Low Uncertain Unknown 1 Uncertain High i HV Uncertain High Voltage 0D Decaying Low D D Decaying Unknown D 1D Decaying High D HVD Decaying High Voltage D S Spike S char Represents the single character you want to be used to indicate the state The comment character default a cannot be used as a char symbol Application Notes 1 Enter the SYMBOL command before the PATTERN and CLK specifications are entered to redefine symbols used for stimulus state values 2 The SYMBOL command can redefine node state symbols either before or after simulation forthe t s OUTPUT probe and t s POUT
88. PZT consists of randomly ori ented crystallites of varying size The piezoelectric but not the ferroelectric property of the ceramic materials of the PZT family is made use of in transducer applications such as ultra sonic echo ranging sonar medical diagnostic ultrasound and nondestructive testing system devices Multisim User Guide K 1 OSI Misc Misc Components K 2 K 2 DC Motor T The component is a universal model of an ideal DC motor which can be used to model the behavior of a DC motor excited in parallel in series or separately The excitation type of the component is determined by the interconnection of the terminals between field windings terminals 1 and 2 and armature windings terminals 3 and 4 MOTOR IDEAL To excite the DC motor in parallel connect the positive terminal of a DC source to terminals 2 and 4 then connect the negative terminals of the DC source to terminals 1 and 3 To excite the DC motor in series connect terminal 2 to terminal 3 use a connector then connect the posi tive terminal of a DC source to terminal 4 and connect the negative terminal of the DC source to terminal 1 To excite the DC motor separately connect a DC source to terminals 2 and 1 positive and negative respectively then connect another DC source to terminals 4 and 3 positive and negative respectively Terminal 5 is the DC motor s output The output is the motor s rpm value To display this value e
89. The buffer has an active high enable input If the device is not enabled then the buffer output goes into a high impedance Z state In this state the output pin is effectively disconnected from the rest of the circuit Thus the buffer is useful for circuits where outputs from different digital devices meet at the same node Truth table input nabra output input 1 1 1 0 1 0 X 0 Z where Z is a high impedance state Note When using a tristate buffer use the Models tab of the Circuit Component Properties dialog box Select the LS BUF or LS OC BUF OC Open collector model if the buffer is being used as a TTL device Select HC BUF or HC OD BUF if the tristate buffer is being used as a CMOS device Otherwise by default the tristate buffer will behave as a regular digital device without any high current capabilities Buffer This component is a non inverting buffer It has a greater fan out and offers a A P A high current source and sink capability for driving high current loads Truth table input output d 1 0 0 Multisim User Guide H 5 eubig OSIN Misc Digital Misc Digital Components Note When using a buffer set it up using the Models tab of the Circuit Component Proper ties dialog box Select the LS BUF or LS OC BUF model if the buffer is being used as a TTL device Select HC BUF or HC OD BUF if the buffer is being used as a CMOS device Otherwise by default the buffer will behave as a regular digita
90. V MJS Substrate junction exponential factor 0 0 5 XTB Forward and reverse beta tempera 0 ture exponent EG Energy gap for temperature effect on 1 11 ev XTI Temperature exponent for effect on IS 3 KF Flicker noise coefficient 0 AF Flicker noise exponent 1 FC Coefficient for forward bias depletion 5 capacitance formula TNOM Parameter measurement temperature 27 50 C Multisim User Guide F 7 SJO SISUBJ Transistors Transistors Components F 2 F 3 F 3 1 T Co Resistor Biased BJT NPN amp PNP Resistor biased BJTs are discrete transistors which have had additional resistors added to them within a standard transistor package This is done to reduce the space required on the PCB for the design The gen eral application is for transistor switches for displays such as LED and Hex displays Q3 RN1101 They come in two varieties with a NPN transistor or a PNP transistor Darlington Transistor NPN amp PNP The Darlington connection is a connection of two bipolar junction tran a5 sistors for operation as a composite transistor The composite transistor 2neo38 acts as a single unit with a current gain that is the product of the current gains of each bipolar junction transistor DC Bias Model If a Darlington transistor with a very high current gain Bp is used the base current may be calculated from _ Vcc Var ge RE Rg BpRg This equation is the sam
91. V This property is used in a Schmitt trig ger which sets off an alarm when a signal exceeds a certain value Other properties of the opamp include a high input resistance Ri and a very small output resistance Ro Large input resistance is important so that the opamp does not place a load on the input signal source Due to this characteristic opamps are often used as front end buffers to isolate circuitry from critical signal sources Opamps are also used in feedback circuits comparators integrators differentiators summers oscillators and wave shapers With the correct combination of resistors both inverting and non inverting amplifiers of any desired voltage gain can be constructed G 2 Electronics Workbench Opamp G 1 4 Opamp Simulation Models Opamps are provided with several levels of simulation models of increasing complexity and accuracy The following model levels are used to distinguish between the various models e LI this is the simplest model with the opamp modeled as a gain block with a differential input and a single ended output e L2 this is a more complex model in which the supply voltages are included in the simula tion L3 thisisa model of increasing complexity where additional control pins are supported e 4 this is the most complex and accurate model with a majority of the external control pins modeled G 1 4 1 L1 Simulation Model This is the simplest simulation model and is equivalent to t
92. a NOT OR or an inverted OR gate Its output is high only gt when all the inputs are low Using a NOR gate is the same as having a NOT B gate at the output of an OR gate Electronics Workbench TIL Components Equivalent circuit NOR gate truth table Boolean Expression H 1 5 NAND Gate This component is a NOT AND or inverted AND gate Its output is low only o v when all inputs are high Using a NAND gate is the same as having a NOT gate at the output of an AND gate Equivalent circuit NAND gate truth table Boolean Expression y a b y a b Multisim User Guide H 3 eubiq OSIN Misc Digital Misc Digital Components H 1 6 XOR Gate Exclusive OR This component has a high output when an odd number of inputs 1 3 5 etc gt is high An even number of high inputs generates a low output XOR gate truth table Boolean Expression y a b y ab ab H 1 7 XNOR Gate Exclusive NOR This component has a high output when an even number of inputs 2 4 6 etc gt is high An odd number of high inputs generates a low output B XNOR gate truth table Boolean Expression y a0b y a b ab Electronics Workbench TIL Components H 1 8 Tristate Buffer H 1 9 This component is a non inverting buffer with a three state output It has a a gt greater fan out and offers a high current source and sink capability for driving af high current loads
93. and simulate the netlist and report simulation results Before reading the sections on running as a batch execution you may want to review the sec tion on B 2 2 1 Commands Overview to gain a better understanding of how to use SILOS III commands B 2 2 28 1Commands in Files SILOS III commands can be entered in the Command window for the Main toolbar for more information see B 2 2 1 Commands Overview or from a file Commands entered from a file must be directly preceded without any white space by a ora Preceding a com mand by will cause the command to be echoed to standard output as it is executed Usu ally only the first two characters are required when specifying a command A few commands e g PRE PRO require three letters to prevent ambiguity For more information on the commands available for SILOS III see the B 2 2 Silos III Command Line Usage An is shown below For this example file test v will automatically simulate to the finish on and report any error messages Enclosing SILOS III commands with a ifdef silos compiler on Multisim User Guide B 2 55 suoisuejx3 JAH Bojan Verilog HDL Extensions Extensions B 2 56 directive allows you to maintain Verilog compatibility the keyword silos is defined as true by default in SILOS III File test v title simple circuit module foo reg clock initial begin clock 0 10 clock 1 10 Sfinish end endmodule ifd
94. and the ripple blanking output RBO goes to a low level response condition 4 When the blanking input ripple blanking output BI RBO is open or held high and a low is applied to the lamp test input all segment outputs are on Multisim User Guide P 41 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 76 74xx247 BCD to seven segment dec P 42 The BCD to seven segment decoder driver features active low outputs designed for driving indicators directly It has full ripple blanking input output controls and a lamp test input BCD to seven segment decoder driver truth table DECIMAL INPUTS OUTPUTS NOTE OR BI FUNCTION LT RBI D c B A RBO a b c d e f g 0 1 1 0 0 0 Of i ON ON ON ON ON ON OFF 1 1 X 0 0 0 1 1 OFF ON ON OFF OFF OFF OFF 2 1 X 0 0 1 0 1 ON ON OFF ON ON OFF ON 3 1 X 0 0 1 1 1 ON ON ON ON OFF OFF ON 4 1 X 0 1 0 0 1 OFF ON ON OFF OFF ON ON 5 1 X 0 1 0 1 1 ON OFF ON ON OFF ON ON 6 1 X 0 1 1 0 1 ON OFF ON ON ON ON ON 7 1 X 0 1 1 1 1 ON ON ON OFF OFF OFF OFF 4 8 1 X 1 0 0 0 1i oN ON ON ON ON ON ON 9 1 X 1 0 0 1 1 ON ON ON ON OFF ON ON 10 1 X 1 0 1 0 1 OFF OFF OFF ON ON OFF ON 11 1 X 1 0 1 1 1 OFF OFF ON ON OFF OFF ON 12 1 X 1 1 0 0 1 OFF ON OFF OFF OFF ON ON 13 1 x 1 1 0 1 1 ON OFF OFF ON OFF ON ON 14 1 X 1 1 1 0 1 OFF OFF OFF ON ON ON ON 15 1 X 1 1 1 1 1 OFF OFF OFF OFF OFF OFF OFF BI X X X X X X 0 OF
95. can be made visible to other design units through the use of a use statement as will be shown If the package contains declarations of subprograms functions or procedures or defines one or more deferred constants constants whose value is not immediately given then a package body is required in addition to the package declaration A package body which is specified using the package body keyword combination must have the same name as its corresponding package declaration but it can be located anywhere in the design it does not have to be located immediately after the package declaration The relationship between a package and package body is somewhat akin to the relation ship between an entity and its corresponding architecture There may be only one pack age body written for each package declaration however While the package declaration provides the information needed to use the items defined within it the parameter list for a global procedure or the name of a defined type or subtype the actual behavior of such elements as procedures and functions must be specified within package bodies Examples of global procedures and functions can be found in A 4 Examples Gallery on page A 23 Configurations Electronics Workbench Learning VHDL A 2 6 The final type of design unit available in VHDL is called a configuration declaration A configuration declaration identified with the configuration keyword specifies which
96. changes the file name for sub sequent STORE and NSTORE commands BAT changes the default BATCH FILE command file name MODE specifies whether a report STOREd will either append to the existing STO file or DISK command file or overwrite the STO file Default MODE OVERWRITE filename represents the redefined name of the file A file name can be unlimited in length However the name must conform to the syntax of your operating sys tem Application Notes 1 The FILE SAV command must be entered before using a FSIM command Do not specify a file name extension the program will automatically provide the correct exten sions Default filename S AVE 2 The FILE STO command is equivalent to the DISK command Default file name STORE OUT or STORE OUTPUT Electronics Workbench Silos III Command Line Usage 3 A file name specified on a subsequent BATCHFILE command will override the FILE BAT command Example file sav run5 B 2 2 12Keeping Simulation Node States The KEEP command specifies wires whose state values will be saved during simulation To save state values to registers see B 2 2 14 Keeping Module Instance Simulation Variable Values The format for the KEEP command is KEEP name name TP name KEEP specifies wires whose state values will be saved during simulation name represents the name of a wire whose state changes will be kept during simulation Application Notes
97. cie V a cc de jEO 5 Mz d for Ver gt FC 9 dV F Pr T dn eeu la for V lt FC Q6 C dV 9c dr V ry Bea Col rr for Vj 2 FC Q gt Vic c Vul C io to for Vo 0 Ps sub V C io 1 M Y cs for Vo gt 0 i 9 V mc Coll Xoc E for V lt FCKQ C C Ts c Xoc E Ic for Va 2 FC q E Pc where for the base emitter junction Cpr F 4 Electronics Workbench BJT NPN amp PNP l mg F 1 FC F 21 FC 1 m and for the base collector junction Cgc and Cyx F 1 FG E 1 FC l m The symbols used in these equations are defined in BJT Model Parameters and Defaults F 1 3 AC Small Signal Model The small signal model of a BJT is automatically computed during linearization of the DC and large signal time domain models The circuit shown is the Gummel Poon small signal model of an NPN transistor Is Cz Csr op gr op Vr Ic Cu Csc or gm op Vr Ic Cs Cw op go op Va m Cx Cx OP Bac 8 87 Ic 87Vbe 8uVce where 9p z input conductance 9 reverse feedback conductance Om transductance O E output conductance Multisim User Guide F 5 SJO SISUBJ Transistors Transistors Components F 1 4 BJT Model Parameters and Defaults T o Symbol Parameter Name Default Example Unit IS Saturation current 1e 16 1e 15 A BF Forward current gain coefficient 100 100 gt BR Revers
98. column in the report When an sign is used in front of any expression then values are reported when those expres sions change expression expres B 2 45 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions Examples A typical way the probe command can be used is to declare the scope for a module instance and then list variables in the module that you want to report on Using two commas between variables would leave a blank column between variables Scope main declare module instance main pro a b c blank column between variables The probe command can be used to report the value for any expression such as you could use the following probe command to report the value for the assignment out a b c d for each change of variable clock probe Gclock out a b c d The STORE command can be used to store the probe report to a file store probe a b stores the probe report to a file Some additional examples for the probe command are listed below probe main il a report variable a inside instance main il probe output result 0 out use string and octal radix formats probe 0 100 so a b c report concatenated variables as octal store probe b a 0 2 h a 3 6 vary the radix for reporting val ues B 2 2 19Quitting Execution B 2 46 The QUIT command enables you to terminate an unwanted session without that session affecting any active SAVE files To quit p
99. continue working on it To save a project to a different project name see Project Save As B 3 2 5 File Print Allows you to print the Output window the source windows and the report windows Multisim User Guide B 3 3 snus 111 SOS Silos Ill Menus Silos III Menus The Data Analyzer waveforms use the Analyzer Print Options screen for print Analyzer Print Options xi Fr n Sar T mz rint Sto lt T me Payer CE wus EST Can lr pte R1 avalo mz fe Tir e Fuis The number of pages will automatically adjust Selecting this will print the time val to the print start and stop times ues for the T1 and T2 timing mark ers and the delta time The fonts for the Data Analyzer window can be set using Options Fonts The Analyzer Print Options screen will print multiple pages of the waveform display The number of pages to be printed is specified in the pages box When printing multiple pages the pages are automatically determined based on the Print Start and Print Stop times and the number of pages specified B 3 2 6 File Print Preview Displays a preview of the printout for the Output window the source windows and the report windows B 3 2 7 File Print Setup Allows you to set up the printer for the Output window the source windows and the report windows B 3 4 Electronics Workbench Edit Menu B 3 2 8File Exit B 3 3 B 3 3 1 B 3 3 2 B 3 3 3 Exits the SILOS Simulation Environm
100. decoder demultiplexer truth table OUTPUTS 13 14 15 11 12 10 INPUTS P 5 39 74xx155 Dual 2 to 4 Dec DEMUX This device features a dual 1 line to 4 line demultiplexer with individual strobes and com mon binary address inputs Decoder demultiplexer truth table OUTPUTS Y1 Y2 Y3 YO Electronics Workbench SELECT STROBE DATA P 20 seues XXpyZ suonouny 74XX P 5 40 74xx156 Dual 2 to 4 Dec DEMUX OC This device contains two 2 to 4 decoders demultiplexers Decoder demultiplexer truth table SELECT STROBE DATA OUTPUTS A B G c vo vi v2 v3 X Xx 1 X Pt Ar 0 0 0 1 0s X X 4 0 1 0 1 r 0 x i 1 0 0 1 r c4 4d 1 1 0 1 Y X X X x x 0 i fhe A P 5 41 74xx157 Quad 2 to 1 Data Sel MUX This device contains inverters and drivers to supply full on chip data selection to the four out put gates It presents true data A 4 bit word is selected from one of two sources and is routed to the four outputs Data selector multiplexer truth table STROBE SELECT OUTPUTS G A B A B Y 1 x X X 0 0 0 0 x 0 0 0 1 x 1 0 1 X 0 0 0 1 X 1 1 P 5 42 74xx158 Quad 2 to 1 Data Sel MUX This device contains inverters and drivers to supply full on chip data selection to the four out put gates It presents inverted data to minimize propagation delay time A 4 bit word is selected from one of two sources and is routed to the four outputs Multisim User Guide P
101. encrypt and secure library files CHGLIB ENCRYPT SECURE feature NODEMOLIMIT output file infilel CHGLIB converts or encrypts library files to random access Multisim User Guide B 2 29 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions ENCRYPT the resulting library file is unreadable except by the SILOS III program Readable comments can be added by editing the encrypted library file before the first character Use of this option is con trolled by a security license feature issued by Simucad SECURE fea the resulting library file is unreadable except by the ture SILOS III program When SILOS III attempts to access the resulting library file the user must have the feature listed in the license file silos lic for SILOS Ill The SECURE option does not require the ENCRYPT option to encrypt the file The SECURE option can also be used with the NODEMOLIMIT option NODEMOLIMIT the resulting library file is unreadable except by the SILOS III program This is a special option that allows the demo version of SILOS III to read a library file of more than 200 gates Use of this option is controlled by a security license feature issued by Simucad output file name of the output library file to be created by the CHGLIB command infile1 name s of one or more input files to be converted to random access and encrypted Application Note 1 Using the CHGLIB command will not necessarily resu
102. end The while statement acts in the normal fashion i 0 while i lt 10 begin Sdisplay i 0d i i i 1 end B 1 14 Electronics Workbench The Verilog Language The repeat statement repeats the following block a fixed number of times in this example five times repeat 5 begin display i 0d i i i 1 end B 1 2 7 Other Statements B 1 2 7 1 Parameter Statement The parameter statement allows the designer to give a constant a name Typical uses are to specify width of registers and delays For example the following allows the designer to parameterized the declarations of a model parameter byte size 8 reg byte size 1 0 A B B 1 2 7 2 Continuous Assignment Continuous assignments drive wire variables and are evaluated and updated whenever an input operand changes value The following ands the values on the wires in1 and in2 and drives the wire out The keyword assign is used to distinguish the continuous assignment from the procedural assignment See B 1 2 3 Program Structure on page B 1 6 for more discussion on continuous assignment assign out inl in2 B 1 2 7 3 Blocking and Non blocking Procedural Assign ments The Verilog language has two forms of the procedural assignment statement blocking and non blocking The two are distinguished by the and lt assignment operators The blocking assignment statement operator acts much like in traditional programming
103. exponential Function Generator Dutycycle 50 x Amplitude v 8 Offset 7 3 5 2 au T 30 Xposition 0 00 4 vir Bra anm Channel A z Y position 0 00 acj ooe 8 C 20 1 2Input Text File Specification This file must contain a list of time and voltage current points Each line of the file represents one point The format is Time space s Voltage Or Time space s Current C 16 Electronics Workbench Piecewise Linear Source You can leave any amount of space between the Time and Voltage Current fields Here is an example of an ideally formatted input file 0 0 2 88e 06 0 0181273 5 76e 06 0 0363142 1e 05 0 063185 1 848e 05 0 117198 If the PWL source encounters It will non whitespace at beginning of line ignore line non numeric data following correctly formatted accept data ignore non data numeric data non whitespace between Time and Voltage Cur ignore line rent whitespace preceding correctly formatted data accept data ignore whitespace C 20 1 3Special Considerations If the earliest input point is not at time 0 0 then the PWL source gives the output of the earli est time point from time 0 0 to that earliest time After the latest input point the PWL source gives the output of the latest time point in the file from that latest time until the simulation ends Between input points the PWL source uses linear interpolat
104. for lamp testing and for blanking the outputs TEL OOF Iu 39 en 96 4 T INPUTS OUTPUTS DISPLAY EL BI LT D C B Aa b c d e f g 8 X X 0 0 0 0 0 1 1 1 1 1 1 0 X 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 2 0 1 1 0 0 1 0 1 1 0 1 1 0 1 3 0 1 1 0 0 1 1 1 1 1 1 0 0 1 4 0 1 1 0 1 0 0 0 d 1 0 0 1 1 5 0 1 1 0 1 0 1 1 0 1 1 0 1 1 6 0 1 1 0 1 1 0 0 0 1 1 1 1 0 7 0 1 1 0 1 1 1 1 1 1 0 0 0 0 8 0 1 1 1 0 0 0 1 1 1 1 1 qi 1 9 0 1 1 1 0 0 1 1 1 1 0 0 1 1 0 1 1 1 0 1 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 1 Eo cr 0 0 0 1 0 0 0 1 1 0 1 1 i sf 0 1 1 0 0 1 0 1 1 0 1 1 i X 1 0 0 0 0 1 1 1 1 0 1 1 LA 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 Depends on BCD code applied during 0 to 1 transition of EL active low latch enable input active low ripple blanking input a al El 4 Hl E active low lamp test input Multisim User Guide 0 41 seues 000p SUONDUNY Functions 4000 Series O 2 73 4512 8 In MUX w 3 state Out This device is a 8 input multiplexer with 3 state outputs Multiplexer truth table OUTPUT INPUTS DATA SELECT I1 I2 I3 I4 I5 I6 I7 I0 sanas 000p suonouny Electronics Workbench 0 42 4000 Series ICs Output Enable Active low Enable input Active low N TT High impedance 0 2 74 4514 1 of 16 Dec DEMUX w Input latches 2 37 a j 2 43 4 23 EL d E This device is a 1 of 16
105. function block L 6 voltage gain block voltage hysteresis block L 13 voltage slew rate block L 20 voltage controlled limiter L 19 controlled one shot C 23 coreless coil D 20 crystal K 1 current limiter block about L 16 parameters and defaults L 18 current controlled current source C 8 current controlled voltage source C 7 customizing nonlinear transformer D 12 D Darlington connection about F 8 AC model F 9 DC bias model F 8 Data Sel MUX P 18 Data Sel MUX w 3 state Out P 45 DC bias model F 8 DC current source C 3 DC model capacitors D 5 diac E 15 diodes E 2 inductors D 8 MOSFET F 12 zener diode E 7 DC voltage source C 2 Decade Counter P 51 P 80 depletion MOSFET F 11 diac about E 14 AC small signal model E 15 DC model E 15 parameters and defaults E 16 time domain model E 15 differentiator about L 9 equations L 10 parameters and defaults L 11 sine wave L 9 square wave L 9 triangle waveform L 9 digital ground C 2 diodes E 1 AC small signal model E 4 DC model E 2 parameters and defaults E 5 time domain model E 3 Divide by twelve Counter P 81 divider about L 3 equations L 5 parameters and defaults L 5 DMOS transistor F 19 Dual 1 of 4 Dec DEMUX 4555 O 53 4556 O 53 Dual 2 to 4 Dec DEMUX 74xx139 P 14 74xx155 P 20 Dual 2 to 4 Dec DEMUX OC P 21 Dual 2 Wide 2 In AND OR INVERTER O 34 Dual 3 In NOR and INVERTER O 3 Dual 4 bit Binary Counter 74xx393 P 62 74xx69 P 75 Dual 4 bit latch O 39 Du
106. gt Vdrm Rs le 06 E 16 Electronics Workbench TRIAC Vd 2 0 and Ig gt Igt at Vg gt Vet or or dva dv dt dt of the triac The triac is switched off and the resistance R is set high current blocking mode if Id lt Ih In this case the switching occurs after turn off time T which is implemented by the behav ioral controller Vs maximum forward breakover voltage or switching voltage in volts current through the diac in amperes blocking resistance in ohms peak off state reverse current maximum forward breakover voltage in volts current through the triac in amperes voltage across the diac in volts voltage across the triac in volts turn on time in seconds Other symbols used in these equations are defined in Triac Parameters and Defaults Multisim User Guide sepoig Diodes Diodes Components E 10 Varactor Diode The varactor is a type of pn junction diode with relatively high junction gt capacitance when reverse biased The capacitance of the junction is con dRSASQA trolled by the amount of reverse voltage applied to the device which makes the device function as a voltage controlled capacitor D11 The capacitance of a reverse biased varactor junction is found in the following way where C1 the total junction capacitance CE permittivity of the semiconductor material A the cross sectional area of the junction Wa the width of the depletion laye
107. hand side of the Explorer window to open the pop up menu B 3 12 1 2Name Filter The name filtering in the Explorer window uses regular expressions Explanations for regular expressions can be found in many programming books A short description of regular expres sions is provided in this help file A regular expression is a notation for specifying and matching strings Regular expressions have two basic kinds of characters Multisim User Guide B 3 33 snuoy 111 SOS Silos III Menus Silos III Menus B 3 34 e Special characters These are characters that have special meaning for matching strings The special characters for regular expressions are V where This escapes or quotes other characters such as matches the A useful quoted string is which means or Another useful quoted string is and which allow the parenthesis to be used to group regular expressions For example ac means the character a and zero or more characters of c However ac means zero or more occurrences of the character string ac d This matches the preceding character at the beginning of a string When is the first char acter in a character class it means the compliment of the character class This matches the preceding character at the end of a string This matches any single character Characters enclosed in brackets are a character class This matches zero or more occurrences of the cha
108. ide SiO layer Depletion MOSFETs are used in automatic gain control AGC circuits 3 terminal n channel depletion MOSFET 3 terminal p channel depletion MOSFET 4 terminal n channel depletion MOSFET substrate unconnected 4 terminal p channel depletion MOSFET substrate unconnected Enhancement MOSFETs An enhancement MOSFET has no physical channel between the drain and the source unlike the depletion MOSFET Instead the substrate extends all the way to the silicon dioxide SiO layer An enhancement MOSFET works only with positive gate source voltages Enhance ment MOSFETs are extensively used in digital circuits and large scale integration LSI appli cations 3 terminal n channel enhancement MOSFET 3 terminal p channel enhancement MOSFET 4 terminal n channel enhancement MOSFET substrate unconnected 4 terminal p channel enhancement MOSFET substrate unconnected Multisim provides four MOSFET device models which differ in the formulation of the cur rent voltage characteristic The parameter LEVEL in the model dialog specifies the model to be used LEVEL 1 is a modified Shichman Hodges model LEVEL 2 defines the geometry based analytical model LEVEL 3 defines the semi empirical short channel model LEVEL 4 defines the BS1M1 model LEVEL 5 defines a new BS1M2 model Multisim User Guide F 11 SJO SISUBJ Transistors Transistors Components F5 3 DC Model Due to the complexity of the MOSFET models used only very basic
109. in the Project Settings screen may need to be enabled Project Project Settings This will save the simulation history for every variable The Save simulation data for this entry in the Module Properties screen may need to be enabled Explorer window Tree Properties See Keeping Module Instance Simulation Variable Values for a simpler method of saving instances in the hierarchy EX SILOS ccisilos3 examplesini spj Debug SILOS Explorer Ele View ne Debs window zlip amp Mudu es Sca k glob L ui sim lus stimu us C In 1 vend vendY Mr zc lasiaace stmalas vend Je Type verd Frit Aslp cress H Click with right mouse button on the left side of the Explorer window to open pop up menu Save simulation entry should be checked to save the simulation history B 3 11 Help Menu B 3 11 1Help Contents Opens the contents listing for the SILOS III User s Manual on line help file Multisim User Guide B 3 31 snus 111 SOIS Silos Ill Menus Silos III Menus B 3 11 2Help Using Help Opens a Microsoft help file for an explanation of how to effectively use the Index and on line Help B 3 11 3Help SILOS Ill User s Manual Provides the complete SILOS III User s Manual B 3 11 4Help Verilog LRM Provides the complete OVI Verilog Language Reference Manual version 1 0 B 3 11 5Help SDF Manual Provides the complete OVI Standard Delay Format SDF Manual version 2 0
110. is modeled by a resistor R K 11 1 Characteristic Equations R20 if ia lt Imax R oo if ia gt max where i current through the fuse in amperes Ina maximum current rating of the fuse in amperes For AC circuits Zax is the peak value of the current not its RMS value K 14 Electronics Workbench Lossy Transmission Line K 11 2 Fuse Parameters and Defaults Symbol Parameter Name Default Unit Imax Maximum current 1 A K 12 Lossy Transmission Line wi This component is a 2 port network that represents a medium such as a vn wire or an interconnect through which electrical signals pass 1m 010hm The lossy model also models resistive losses in the line along with the char acteristic impedance and propagation delay properties of the transmission line This is a two part convolution model for single conductor lossy transmission lines The uni form constant parameter distributed transmission line model can be used to model the follow ing types of lines e RLC uniform transmission lines with series loss only RC uniform RC lines LC lossless transmission lines e RG distributed series and parallel conductance K 12 1 Model The characteristic of a lossy transmission line is modeled by the Telegrapher Equations e E Ri ox ot di ov DM gi Gv with the following boundary and initial conditions vo v t v t vt io i it t Multisim User Guide K 15 OSIN Misc
111. line Data Sel MUX P 46 This device is designed to multiplex signals from 4 bit data sources to 4 output data lines in bus organized systems Its 3 state outputs interface directly with the system bus Data selector multiplexer truth table OUTPUT CONTROL SELECT A B Y 1 X X X Z 0 0 0 X 0 0 0 X 1 0 a8 X 0 0 0 a8 X 1 1 Z High impedance off Electronics Workbench 74XX P 5 83 74xx258 Quad 2 to 1 line Data Sel MUX This device is designed to multiplex signals from 4 bit data sources to 4 output data lines in bus organized systems Its 3 state outputs interface directly with the system bus Data selector multiplexer truth table OUTPUT CONTROL SELECT A B Y 1 X X X Z 0 0 0 X 0 0 0 1 X 1 0 I X 0 0 0 T X ah 1 Z High impedance off P 5 84 74xx259 8 bit Latch This 8 bit addressable latch is a 1 of 8 decoder or demultiplexer with active high outputs It stores single line data in eight addressable latches 8 bit addressable latch truth table INPUTS OUTPUT OF EACH ADDRESSED OTHER FUNCTION CLEAR G LATCH OUTPUT 1 0 D Qio Addressable latch 1 1 Qio Qio Memory 0 0 D 0 8 line demultiplexer 0 1 0 0 Clear P 5 85 74xx26 Quad 2 In NAND OC This device contains four independent 2 input NAND gates Logic function Y ABCD Multisim User Guide P 47 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series NAND gate truth table x OM x
112. linear voltage source C 15 pilot light types of N 3 PIN diode E 6 PLL 1 4 polynomial source C 20 potentiometer C 9 D 17 probe about J 3 protection device types of N 2 pullup D 18 pulse current source C 20 pulse voltage source C 18 push button switch N 3 PWL source See piecewise linear source Q Quad 2 In AND OC 74xx09 P 5 4081 O 33 74xx08 P 5 Quad 2 in Exc OR gate P 13 Quad 2 In MUX O 14 P 51 Quad 2 In NAND Ls OC 74xx03 P 3 OC 74xx26 P 47 OC 74xx38 P 60 OC 74xx39 P 60 Schmitt 4093 O 36 Schmitt 74xx132 P 11 4011 O 6 74xx00 P 2 74xx37 P 57 Quad 2 In NOR OC 74xx33 P 53 4001 O 3 74xx02 P 3 74xx28 P 50 xi Quad 2 In OR 4071 O 29 74xx32 P 52 Quad 2 In XNOR OC 74xx266 P 48 4077 O 32 Quad 2 In XOR 4030 O 21 4070 O 28 74xx86 P 80 Quad 2 to 1 Data Sel MUX P 21 Quad 2 to 1 line Data Sel MUX 74xx257 P 46 74xx258 P 47 Quad Analog Switches O 27 Quad bus BUFFER w 8 state Out P 11 Quad D latch O 25 Quad D type FF clr P 30 FF w en P 60 Flip flop O 12 Reg w 3 state Out O 31 Quad Ex OR NOR Gate P 13 Quad Multiplexer O 47 Quad RS latch w 3 state Out O 26 Quad SR latches P 49 Quad True Complement BUFFER O 25 R relay about D 13 equations D 14 model D 14 types of N 2 resistance about D 3 ammeter J 2 voltmeter J 1 resistors xii about D 2 equations D 4 virtual D 4 RF BJT NPN M 2 RF capacitor M 1 RF inductor M 1 RF MOS STDN M 2 rpack D 18 S Schottky diode E 12 SCR about E
113. no delay control no event control O or wait statements allowed A task may contain time controlled statements 2 A Verilog function cannot invoke call enable a task whereas a task may call other tasks and functions The definition of a task is the following task task name Notice no parameter list or s argument ports declarations statements endtask B 1 16 Electronics Workbench The Verilog Language An invocation of a task is of the following form name of task port list where port list is a list of expressions which correspond by position to the argument ports of the definition Port arguments in the definition may be input inout or output Since the argument ports in the task definition look like declarations the programmer must be careful in adding declares at the beginning of a task Testing tasks and functions Dan Hyde Aug 28 1995 module tasks task add task definition input a b two input argument ports output c one output argument port reg R register declaration begin end endtask initial begin initl reg p add 1 0 p invocation of task with 3 arguments display p b p end endmodule input and inout parameters are passed by value to the task and output and inout parameters are passed back to invocation by value on return Call by reference is not avail able Allocation of all variables is static Therefor
114. numbers ocoooccocooo ooo B2 24 B 2 1 7 20Null statements 22222 22m een B2 25 B 2 1 7 21Timing checks without edge specifications for selected variables mussen nennen nennen B2 25 B 2 1 7 22More precision in timeformat than timescale B2 25 B 2 1 7 23Missing port connections are set to ground for VCS compatibility 22er B2 25 B 2 1 7 24VCS compatibility extension for comma at the end of the port list i e module xx a 2 222220 B2 25 B 2 2 Silos Ill Command Line Usage oocooccocccoc ere B2 26 B 2 2 1 Commands Overview ooococccooocc ns B2 26 B 2 2 1 1Command Syntax ees B2 26 B 2 2 1 2Inputting SILOS Commands 000 0c eee eee B2 26 B 2 2 1 3Stopping Processes 0 0 0 c eects B2 26 B 2 2 2Activity Report For Nodes 222m ss seen eae B2 26 B 2 2 3Bus Contention Report 2 2 2 000 eee B2 28 B 2 2 4Encrypting Library Files 0 2 0 0 cece eee B2 29 B 2 2 5Control Parameters For Logic Simulation 0200000 es B2 30 B 2 2 6Default Device Delay Times 0 0 ee nenn B2 34 Multisim User Guide suoisueix3 JAH Bojan B 2 2 7Disk File Name Reassignment llslells elles B2 35 B 2 2 8Error Summary oii gia eaa eee es B2 36 B 2 2 9Exclude Saving Simulation Node StateS o oooooccococoooo B2 36 B 2 2 10Exiting The Program o ococcccoconcc nh B2 37 B 2 2 11File Name Specification
115. of design units in VHDL entities architectures packages pack age bodies and configurations Electronics Workbench Learning VHDL 1 The diagram below illustrates the relationship of these five design units Configuration or default config Package Body Architecture s Entities A VHDL entity is a statement identified by the ent ity keyword that defines the exter nal specification of a circuit or sub circuit The minimum VHDL design description must include at least one entity and one corresponding architecture When you write an entity declaration you must provide a unique name for that entity and a port list defining the input and output ports of the circuit Each port in the port list must be given a name direction or mode in VHDL jargon and a type Optionally you may also include a special type of parameter list called a generic list that allows you to pass additional information into an entity Architectures A VHDL architecture declaration is a statement beginning with the architecture keyword that describes the underlying function and or structure of a circuit Each archi tecture in your design must be associated or bound by name with one entity in the design VHDL allows you to create more than one alternate architecture for each entity This fea ture is particularly useful for simulation and for project team environments in which the design of the system interfaces expressed a
116. of var ious information including the current simulation time the line number the file name mod ule and any results from executing the statement settrace You can turn off the trace using the cleartrace system task B 1 3 7 showscopes The showscopes system task displays a complete lists of all the modules tasks functions and named blocks that are defined at the current scope level showscopes B 1 3 8 showvars The showvars system task produces status information for register and net wires vari ables both scalar and vector When invoked without parameters showvars displays the status of all variables in the current scope When invoked with a list of variables it shows only the status of the specified variables Multisim User Guide B 1 25 Jewud Bowe Verilog Primer Verilog HDL Primer showvars Sshowvars lt list of variables B 1 3 9 stop The stop system task puts the simulator into a halt mode issues an interactive command prompt and passes control to the user stop B 1 3 10 time The time system function returns the current simulation time as a 64 bit integer time must be used in an expression B 1 26 Electronics Workbench Appendix B 2 Extensions B 2 1 Verilog HDL Extensions 0 0 0 E E nenne nn B2 1 B 2 1 1SILOS III PLI Interface llis eese B2 1 B 2 1 1 1SILOS III PLI Interface on the PC llslslsllsssss B2 1 B 2 1 1 2SILOS III PLI In
117. or QH respectively before QHO the indicated steady state input conditions were estab lished QAn QBn etc the level of QA QB etc respectively before the most recent negative transition of the clock Multisim User Guide P 37 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 68 74xx20 Dual 4 In NAND This device contains two independent 4 input NAND gates Logic function X ABCD NAND gate truth table x MM OF y x x o x HF w KkKoxkHrln O x x x HI 8 HFHrHrol x P 5 69 74xx21 Dual 4 In AND This device contains two independent 4 input AND gates Logic function Y ABC AND gate truth table A B C D Y T 1 1 1 T 0 X X xo X 0 X X0 X X 0 x 0 X X X 0 0 P 5 70 74xx22 Dual 4 In NAND OC This device contains two independent 4 input NAND gates For correct performance the open collector outputs require pull up resistors P 38 Electronics Workbench 74XX Logic function Y ABCD NAND gate truth table x OF x OM w ox mM FILO x x XM I Oo PrP PR oO KK P 5 71 74xx238 3 to 8 line Dec DEMUX The logic levels at the C B and A inputs select one of the eight lines G1 is an active high enable input while G2A and G2B are active low enable inputs 3 to 8 decoder demultiplexer truth table SELECT OUTPUTS B YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 COO OLO O O O x xp S Q Ooooc oooo r nn mM HFHHrH PrP Hr ELO x o FHH Ho o o
118. ordinate 1 0 A turns m H2 Magnetic field co ordinate2 1 0 A turns m H3 H15 Magnetic field co ordinates 0 A turns m B1 Flux density co ordinate 1 0 Wb m B2 Flux density co ordinate 2 1 0 Wb m B3 B15 Flux density co ordinates 0 Wb m D 8 Relay K1 L t EDR201A05 The magnetic relay can be used as a normally open or normally closed relay It is activated when the current in the energizing circuit attached to P P exceeds the value of the switch on current Ion During operation the con tact switches from the normally closed terminals Sy 5 to the normally open terminals Sy 5 The relay will remain on as long as the current in the circuit is greater than the holding current 4 The value of Ig must be less than that of J Multisim User Guide oiseg Basic Basic Components The magnetic relay is a coil with a specified inductance Lc in henries that causes a contact to open or close when a specified current Ion in A charges it The contact remains in the same position until the current falls below the holding value Ihd in A at which point it returns to its original position D 8 1 Model The energizing coil of the relay is modeled as an inductor and the relay s switching contact is modeled as resistors R and R3 D 8 2 Characteristic Equation R 0 R2 e Ry e R2 0 where L R4 R2 if ip lt ion if ihd lt ion lt ip inductance of the relay ener gizin
119. parallel inputs PO to P3 a cascade feedback input CF four buffered parallel outputs OO to O3 a terminal count output TC and an overriding asynchronous master reset input MR DEDE O 2 81 4526 4 bit Bin Down Counter The 4526 device is a synchronous programmable 4 bit binary down 5 counter with an active HIGH and an active LOW clock input CPO 7 mo o 5 CP1 an asynchronous parallel load input PL four parallel inputs PO 2 9r to P3 a cascade feedback input CF four buffered parallel outputs OO 3 a M to 03 a terminal count output TC and an overriding asynchronous 7 co re master reset input MR ie OP cP1 O 2 82 4531 13 input Checker Generator The 4531 device is a parity checker generator with 13 parity inputs IO Ho o LL to 112 and a parity output O a 01 z P2 02 4 31 P3 03 LL is Pt 42 ae Tc a are CPO Op cP4 O 48 Electronics Workbench 4000 Series ICs Truth table INPUTS 10 I1 I2 13 I4 15 16 17 18 19 110 I11 112 0 0 0 0 0 0 0 0 0 0 0 0 0 any odd number of inputs HIGH any even number of inputs HIGH x 1 T 1 d a 1 1 1 1 1 1 HIGH state the more positive voltage LOW state the less positive voltage 0 2 83 4532 8 bit Priority Enc This device is an 8 bit priority encoder T Pes Pl es a a Dn NA 0 2 3 4 5 IE 0 7 ie 9 10 11 Multisim User Guide OUTPUTS O Hon o O 49
120. parallel inputs parallel outputs right shift and left shift serial inputs operating mode control inputs and a direct overriding clear line Shift register truth table MODE SERIAL PARALLEL OUTPUTS CLEAR S1 SO CLK LEFT RIGHT A h QA QB QG QH 0 X X X X X X 0 0 0 0 1 X X 0 X X X QAO QBO 0GO QHO 1 1 X X a h a b g h 1 0 1 X 1 X alt QAn QFn QGn 1 0 1 X 0 X 0 QAn QFn QGn d T 0 1 X X OBn QCn QHn 1 d T 0 0 X X OBn QCn QHn 1 1 0 0 X X X X QAO QBO QGO QHO Electronics Workbench 74XX transition from low to high a h the level of steady state input at inputs A through H respectively QAO QB0 QGO the level of QA QB QG or QH respectively before QHO the indicated steady state input conditions were estab lished QAn QBn etc the level of QA QB etc respectively before the most recent negative transition of the clock P 5 67 74xx199 8 bit Shift Reg sh ld ctrl This device contains an 8 bit shift register with shift load control Shift register truth table MODE SERIAL PARALLEL OUTPUTS QB CLEAR S L CLKINH CLK J K A H QA ae QH 0 x X X X X X 0 0 0 1 X 0 0 X X X QAO OBO OHO 1 0 0 X X a exh a b g h 1 1 0 0 1 X QAO QAO QGn I 1 0 0 0 X 0 OAn QGn 1 1 0 1 1 X 1 QCn L 1 1 0 1 0 x Qan QAn QGn 1 x 1 x x x QAO QBO QHO transition from low level to high level a h the level of steady state input at inputs A through H respectively QAO QB0 QGO the level of QA QB QG
121. s resistance to get a more accurate reading However using a voltme ter with very high resistance in a low resistance circuit may result in a mathematical round off error Mode DC or AC The voltmeter can measure DC or AC voltage In DC mode any AC component of the signal is eliminated so that only the DC component of the signal is measured In AC mode any DC component is eliminated so that only the AC component is measured When set to AC the voltmeter displays the root mean square RMS value of the signal Multisim User Guide J 1 S10 291pu Indicators Indicators Components J 1 3 Connecting a Voltmeter J 2 J 2 1 J 2 2 J 2 3 J 2 Connect the voltmeter in parallel with the load attaching the probes to connectors on either side of the load you want to measure When a circuit is activated and its behavior is simulated the voltmeter displays the voltage across the test points The voltmeter may also display interim voltages before the final steady state voltage is reached Note If a voltmeter is moved after the circuit has been simulated activate the circuit again to get a reading Ammeter The ammeter offers advantages over the multimeter for measuring current in a circuit The advantage of using the ammeter is that you can use an unlimited number of ammeters in a circuit and you can rotate their terminals to suit your lay out The side with the heavier border is the negative terminal Resista
122. shown below the VCO parameters are set so that control voltage of 0V pro duces an output frequency of 100Hz and control voltage of 12V produces an output frequency of 20KHz Multisim User Guide C 13 seounos Sources Sources Components A square wave control voltage produces a form of FSK frequency shift keying a sine wave control voltage produces a form of FM frequency modulation 81 SWEEP V S CONTROL V Frequency Adj R1 FT kQ 60 2092 V M1 1 poo Dutyoycle 50 5 Offset i 21 Ground Time base 0 20ms div I Xposition 0 00 Channel A Y position 0 00 Jae oo ERIS C 19 Voltage Controlled Piecewise Linear Source This source voltage controlled piecewise linear source allows you to control the shape of the output waveform by entering up to five input output pairs Qu which are shown in the Properties dialog box as X Y co ordinates The X values are input co ordinate points and the associated Y values represent the outputs of those points If you use only two pairs the output voltage is linear Outside the bounds of the input co ordinates the PWL controlled source extends the slope found between the lowest two co ordinate pairs and the highest two co ordinate pairs A potential effect of this behavior is that it can unrealistically cause the output to reach a very C 14 Electronics Workbench Piecewise Lin
123. special meaning on UNIX and must be escaped as M There must be no whitespace between the and the SILOS III com mand SILOS III commands that contain an embedded space must be enclosed by quotes such as batch examl log In Unix there is an additional method for running SILOS III in the batch mode that is similar to the interactive mode To setup a batch session edit a file and enter the same SILOS HI commands as you would have used for an interactive session Next submit the file as a batch run on your computer The following file would run SILOS III as a batch session on a UNIX operating system using C shell bin csh silos lt lt mark batch examl log redirects standard output to file examl log library examl lib examl udp library v input examl v examl tst sim disk run01 out store probe q 4 1 B 2 62 Electronics Workbench Verilog Libraries exit mark B 2 3 Verilog Libraries B 2 3 1 Overview Simucad provides many of the popular TTL library models for the SN74LS series The behavioral source for these parts is provided as four libraries SN74LS series without timing subdirectory libraryisn741s e SN74LS series with timing subdirectory libraryisn741st e SN74BCT series without timing subdirectory library sn74bct e SN74BCT series with timing subdirectory library sn74bctt B 2 3 2 Library Command SILOS III will search library files when module definitions are not foun
124. state gates the output level will be set to Unknown The output strength will be defined by the gate definition for a tri state gate 4 When the iteration limit is exceeded for CONTROL MXDCI or CONTROL MXITR a nonconvergence error stops execution Nonconvergence may be due either to circuit path length or problems with designs involving feedback To eliminate oscilla tions caused by problems involving feedback the circuit design must be corrected When nonconvergence is due to path length increasing the iteration limit should enable the cir cuit to converge In general each node in the serial path length requires one iteration to propagate a signal Arbitrarily increasing the iteration limits is not recommended as it may dramatically increase the execution time necessary to identify oscillating nodes 5 The NONCONV command can be used to identify which parts of the circuit have caused a logic initialization or logic simulation to stop executing Examples con mxd 200 mxp 200 CON DISK 2M MXOSC 30 EUNK B 2 2 6 Default Device Delay Times B 2 34 Normally if a device has no delay specification the delay times default to zero The DELAY command allows you to globally redefine the default values Default delay times are specified as follows DELAY DEFAULT di d2 DELAY Indicates a default delay time specification DEFAU Indicates that the default times for all LT unspecified delays are to be assigned No
125. the Y numerator terminal the quotient will go to infinity and a large positive or negative spike will be observed on the scope ES Numerator e A1 1 VAIO V Y Denominator Quotier t output V1 120 V 60 Hz 0 Deg Qv Vi60 Hz Deg E 16 97 V Ground Time base Trigger 5 00msidw_ El Edge ll e X position 0 00 E Level n 3 fivet gens ue Auto 18 8 Es Channel A Channel B 100 wow A Yposiion o o0 Ej Yposition o 00__ Eelo oc e Bel ol oc e L 4 Electronics Workbench Divider L 2 1 Characteristic Equation v Yor V k off out V X X where Vx input voltage at x Vy u input voltage at y Other symbols used in these equations are defined in the table below L 2 2 Divider Parameters and Defaults Symbol Parameter Name Default Unit k Output gain 1 VN off Output offset 0 V Yoff Y Numerator offset 0 V Yk Y Numerator gain 1 VN Xoff X Denominator offset 0 V Xk X Denominator gain 1 VN XLowLim X Denominator lower limit 100 pV XSD X Denominator smoothing domain 100 pV Multisim User Guide L 5 S O4 UO Controls Controls Components L 3 L 3 1 L 6 Transfer Function Block A This component models the transfer characteristic of a device circuit or system in the s domain The transfer function block is specified as a frac tion with polynomial numerators and denominators
126. the dialog box See Input Text File Specification below Outside the bounds of the input co ordinates the PWL controlled source extends the slope found between the lowest two co ordinate pairs and the highest two co ordinate pairs A potential effect of this behavior is that it can unrealistically cause the output to reach a very large or very small value especially for large input values Therefore keep in mind that this source does not inherently provide a limiting capability In order to reduce the potential for non convergence of simulations the PWL controlled source provides for smoothing around the co ordinate pairs If input smoothing domain ISD is set to say 10 the simulator assumes a smoothing radius about each co ordinate point equal to 1046 of the length of the smaller of the segments above and below each co ordinate point Multisim User Guide C 15 seoinos Sources Sources Components C 20 1 1 Example In the sample circuit shown below a triangle waveform with uniform rise and fall slopes is modified to a parabolic waveform for which the slope increases at each reference point The co ordinate pairs that perform this conversion are First pair 0 0 no change Second pair 1 1 same Third pair 2 4 slope is increased between this pair and the last Fourth pair 3 9 slope increased again Fifth 4 16 even steeper slope Note In this example the Y output is the square of the input It is therefore an
127. the diode drops When the input cycle is negative diodes D4 and D4 become forward biased and conduct cur rent in the direction shown Hence the current flows in the same direction for both the posi tive and the negative halves of the input wave A full wave rectified voltage appears across the load E 10 Electronics Workbench Full Wave Bridge Rectifier E 5 3 Full Wave Bridge Rectifier Parameters and Defaults Symbol Parameter Name Default Typical Value Unit IS Saturation current 1e 14 1e 9 1e 18 cannot A be 0 RS Ohmic resistance 0 10 WwW CJO Zero bias junction capacitance 0 0 01 10e 12 F VJ Junction potential 1 0 05 0 7 V TT Transit time 0 1 0e 10 S M Grading coefficient 0 5 0 33 0 5 2 BV Reverse bias breakdown volt 1e 30 V age N Emission coefficient 1 1 EG Activation energy 1 11 1 11 eV XTI Temperature exponent for 3 0 3 0 s effect on IS KF Flicker noise coefficient 0 0 AF Flicker noise exponent 1 1 FC Coefficient for forward bias 0 5 0 5 depletion capacitance formula IBV Current at reverse breakdown 0 001 1 0e 03 A voltage TNOM Parameter measurement tem 27 27 50 C perature Multisim User Guide sepoiq Diodes Diodes Components E 6 E 7 E 12 Schottky Diode The Schottky diode is a two terminal device with a junction that uses metal in place of the p type material The formation of a junction with a semiconductor
128. the maximum size on disk for the simulation history save file This prevents SILOS III from crashing when all available disk space is used SILOS III will return to the Ready prompt when the simulation history save file reaches the limit The reset savfile command can be entered in the Command window in the Main toolbar to reset the simulation history save file to a few bytes The simulation can be continued and the simulation results that are after the reset savfile can be reviewed plusargs You can enter command line arguments that are project specific such compare sdf etc For example suppose you wanted to specify the SDF file only if you entered sdf in the plusargs box for the Project Settings screen Then your test bench may look like module test bench Electronics Workbench Project Menu initial if Stest plusargs sdf sdf annotate test sdf only execute if sdf is an argument endmodule e Retain simulation data file This prevents the simulation history save file from being deleted from disk when the SSE is exited The default is to delete the simulation history file when the SSE is exited Checking this option is not recommended as it has no use and may clutter up your disk with large save files e Save all sim data This feature will save the simulation history for every variable If Save all sim data is not enabled then the only variables saved are those spec
129. three characters and are used in expressions see B 1 2 5 Opera tors on page B 1 11 An identifier is specified by a letter or underscore followed by zero or more letters digits dol lar signs and underscores Identifiers can be up to 1024 characters B 1 2 3 Program Structure B 1 6 The Verilog language describes a digital system as a set of modules Each of these modules has an interface to other modules to describe how they are interconnected Usually we place one module per file but that is not a requirement The modules may run concurrently but usu ally we have one top level module which specifies a closed system containing both test data and hardware models The top level module invokes instances of other modules Modules can represent pieces of hardware ranging from simple gates to complete systems e g a microprocessor Modules can either be specified behaviorally or structurally or a com bination of the two A behavioral specification defines the behavior of a digital system module using traditional programming language constructs e g ifs assignment statements A structural specification expresses the behavior of a digital system module as a hierarchi cal interconnection of sub modules At the bottom of the hierarchy the components must be primitives or specified behaviorally Verilog primitives include gates e g nand as well as pass transistors switches The structure of a module is the following modul
130. transition negative going transition either HIGH or LOW number of clock pulse transitions 0 2 13 40160 4 bit Dec Counter The 40160 device is a fully synchronous edge triggered 4 bit decade HE Po 00 counter with a clock input CP an overriding asynchronous master reset sg 01 MR four parallel data inputs PO to P3 three synchronous mode con e 5 trol inputs parallel enable PE count enable parallel CEP and count H CEP enable trickle CET buffered outputs from all four bit positions OO to Ee ed 03 and a terminal count output TC td MR er Multisim User Guide O 9 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 14 40161 4 bit Bin Counter 5 D d el gt e aj al 2 la m 00 01 02 o3 sala a The 40161 device is a fully synchronous edge triggered 4 bit binary counter with a clock input CP an overriding asynchronous master reset MR four parallel data inputs PO to P3 three synchronous mode con trol inputs parallel enable PE count enable parallel CEP and count enable trickle CET buffered outputs from all four bit positions OO to O3 and a terminal count output TC O 2 15 40162 4 bit Dec Counter e al gt gt j ol a i CET PE SR CP z 00 01 02 03 lala a The 40162 device is a fully synchronous edge triggered 4 bit decade counter with a clock input CP
131. unresolved devices and nodes the type of device and node as either a type data keyword NODE for a wired connection with at least one bi directional device or BUS for a wired connection between two or more unidirectional enabled gates the node state values for the nonconvergence time point State values reported are preceded by a to indicate possible previous states B 2 42 Electronics Workbench Silos III Command Line Usage 3 Nonconvergence only occurs when gate delays are zero Zero delays occur during logic initialization which forces delays to be zero or during zero delay logic simulation or when either zero delay or no delay is specified for devices the default delay for Verilog HDL devices is zero 4 When the iteration limit is exceeded while resolving node states at a time point a noncon vergence error stops execution Nonconvergence may be due either to the circuit path length or problems with designs involving feedback The circuit design must be corrected to eliminate oscillations caused by problems involving feedback When nonconvergence is due to path length increasing the iteration limit should enable the circuit to converge In general each node in the serial path length requires one iteration to propagate a signal 5 The maximum iterations per pass for logic initialization can be redefined by the CON TROL MXDCI command The maximum iterations at a time point for logic simulation can be
132. up 11 J Count up 0 1 I X X X X Count down 1 1 Count down transition from low to high i605 TCU CPU at terminal count up HLLH qe TCD CPD at terminal count down LLLL P 5 63 74xx193 Sync 4 bit Bin Up down Counter This device is a synchronous 4 bit binary reversible up down counter P 34 Up down counter truth table INPUTS OUTPUTS OPERATING MR PL CPU CPD DO D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD MODE 1 X X 0 X X X X 0 0 0 0 1 0 Reset 1 X X 1 X X X X 0 0 0 0 1 1 0 0 X 0 0 0 0 0 0 0 0 0 1 0 0 0 X 1 0 0 0 0 0 0 0 0 1 1 Parallel 0 0 0 X 1 1 1 1 1 1 1 1 0 1 load 0 0 1 X 1 1 1 1 1 1 1 1 1 1 0 1 1 X X X X Count up 31 1 Count up 0 1 1 X X X X Count down 1 1 Count down transition from low to high TCU CPU at terminal count up HHHH Electronics Workbench 74XX 12 TCD CPD at terminal count down LLLL P 5 64 74xx194 4 bit Bidirect Univ Shift Reg This bidirectional shift register has parallel inputs parallel outputs right shift and left shift serial inputs operating mode control inputs and a direct overriding clear line Shift register truth table MODE SERIAL PARALLEL OUTPUTS CLEAR S1 so CLK LEFT RIGHT A B C D QA oB oc op 0 X X X X X X X X X 0 0 0 0 1 X X 0 X X X X X X QAO QBO QCO QDO I 1 1 X X a b c d b c d d 0 1 X 1 X X X X 1 OAn QBn QCn E 0 1 X 0 X X X X 0 OAn QBn QCn 1 L 0 1 X X X X X OBn QCn ODn A 1 T 0 0 X X x x X OBn QCn QDn 0 1 0 0 X X X X X X X QAO Q
133. used as the pin to pin delay for the module input to output For examples of path delays see Chapter 13 on specify blocks in the Verilog LRM on line help file delay mode unit Command line argument sets all gate and specify block delays to one delay mode zero Command line argument sets all gate and specify block delays to zero incdir directoryl directory2 If SILOS III can not find a file name that is specified on the user s include in the current directory then SILOS III will search the directories specified by the incdir command line option for the file ignore sdf interconnect delay specifies that SDF INTERCONNECT delays will not be used This can be useful for reducing the runtime and memory usage for fault simulation ignore sdf port delay specifies that SDF PORT delays will not be used This can be useful for reducing the runtime and memory usage for fault simulation mindelays This option selects the minimum delay specification for delays min typ max typdelays This option selects the typical delay specification for delays min typ max Default typdelays maxdelays This option selects the maximum delay specification for delays min typ max nodoldisplay This option suppresses all messages from display write etc sys tem tasks to standard output This can be used to prevent these messages from cluttering the log file during logic simulation nolibfaults Automatically inserts suppress faults and e
134. voltage Conversely when an AC volt age is applied across the quartz crystals they vibrate at the frequency of the applied voltage This is known as the piezoelectric effect and quartz is an example of a piezo electric crystal The piezoelectric characteristics of quartz give the crystal the characteristics of a very high Q tuned circuit The piezoelectric effect of quartz crystal links the mechanical and electrical properties of the resonator Electrode voltage causes mechanical movement Likewise mechanical displacement generates an electrode voltage An equivalent circuit for a crystal shows a large inductor in series with a small resistance and a capacitance When mounted in a holder with connections a shunt capacitance is added to the equivalent circuit The resultant equivalent circuit means that the crystal has both a series and parallel resonant frequency very close together Oscillators that employ crystals typically quartz offer excellent oscillation frequency stabili ties of 0 001 percent Crystal oscillators are used in digital wristwatches and in clocks that do not derive their frequency reference from the AC power line They are also used in color tele vision sets and personal computers In these applications one or more quartz crystals con trol frequency or time Another much more efficient transducer material than quartz is PZT This ceramic material is ferroelectric and is made up of lead and other atoms Ti or Zr
135. voltage level one setup prior to the low to high clock transition 0 Low voltage level 1 Low voltage level one setup prior to the low to high clock transition An Lower case letters indicate the state of the refer enced output prior to the low to high clock transi tion X Don t care Low to high clock transition 2 The TC output is High when CET is High and the counter is at Terminal Count HLLH P 5 48 74xx163 Sync 4 bit Binary Counter This synchronous presettable 4 bit binary counter features an internal carry look ahead for fast counting Multisim User Guide P 25 seues Xxv suonounJj Functions 74XX series Functions 74XX Series 4 bit counter truth table INPUTS OUTPUTS OPERATING SR CP CEP CET PE DN QN TC MODE X X X X 0 0 Reset clear h X X l l 0 0 h X X i h 1 2 Parallel load h h h h X cou 2 Count nt h X 1 X h X aq 2 Hold do h X X 1 h X q O nothing 1 High voltage level h High voltage level one setup prior to the low to high clock transition 0 Low voltage level 1 Low voltage level one setup prior to the low to high clock transition dh Lower case letters indicate the state of the refer enced output prior to the low to high clock transi tion X Don t care Low to high clock transition 2 The TC output is High when CET is High and the counter is at Terminal Count HHHH P 5 49 74xx164 8 bit Parallel Out Serial Shift Reg This
136. 0 Buick Converter vase iwi de ew oleh a K 10 K 9 1 Characteristic Equations 0 00 tee K 11 K 9 2 Buck Converter Parameters and Defaults 20000 eee eee K 12 Buck Boost Convener ar vL org wh pee BAS e LA RA Weel ln K 12 K 10 1Characteristic Equations o oocococooccnccoa eee K 13 K 10 2Buck Boost Converter Parameters and DefaultS oo o o K 14 FUSE obese uses utes Un ee Eel dor deam Ger ace ema dare p unt ema aie K 14 K 11 1Characteristic Equations oococococcorcocoo ee K 14 K 11 2Fuse Parameters and Defaults liliis K 15 Lossy Transmission Line sss riges sedre denni nh K 15 Multisim User Guide OSI Misc K 13 K 14 Ki12 1Model ruri keds taras fixe Ile e eb Dix perpe K 15 K 12 2Lossy Transmission Line Model Parameters and Defaults K 16 Lossless Line Type T oooooooocoorco e K 17 Kd32IModel nift 9E yaaa ae bide al Deu eS A Fee E K 17 K 13 2Lossless Transmission Line Model Parameters and Defaults K 18 K 13 3Lossless Line Type 2 ooooooccoooornrr nee K 18 Net SS A da ped ci K 18 Electronics Workbench Appendix K Misc Components K 1 Crystal XTAL4 This component is made of pure quartz and behaves as a quartz crystal res a E onator a circular piece of quartz with electrodes plated on both sides mounted inside an evacuated enclosure When quartz crystals are mechani Hc49 U 15MHz cally vibrated they produce an AC
137. 0 0 ee ees A 27 A 4 2 2 Test Bench o a ERG ERE ES A 30 A 4 3 Reading and Writing from Files llle A 32 Multisim User Guide JOWUd TAHA VDHL Prrimer A 4 3 1Design Description 00 eee A 4 3 2Test Bench Electronics Workbench Appendix A VHDL Primer A 1 A 1 1 A 1 2 This section provides a solid introduction to programming in VHDL It is not intended to be a fully comprehensive VHDL reference It is made up of an overview of VHDL standards a section on learning VHDL a conclusion and several examples VHDL Standards History This section provides a detailed history of VHDL standards IEEE Standard 1076 In the early 1980s a team of engineers from three companies IBM Texas Instruments and Intermetrics were contracted by the Department of Defense to complete the specification and implementation of a new language based design description method The first publicly available version of VHDL version 7 2 was released in 1985 In 1986 the Institute of Elec trical and Electronics Engineers Inc IEEE was presented with a proposal to standardize the language which it did in 1987 after substantial enhancements and modifications were made by a team of commercial government and academic representatives The resulting standard IEEE 1076 1987 is the basis for virtually every VHDL simulation and synthesis product sold today An enhanced and updated version of the language IEEE 1076 1993 was
138. 0 0 0 0 X 0 0 of 1 0 X l X Z Z 1 X X Z Z 1 High voltage level 0 Low voltage level X Don t care Z Multisim User Guide high impedance off state P 55 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 10474xx366 Hex Inverter Buffer Driver w 3 state This device is a 3 state Hex inverter buffer driver Hex inverter buffer driver truth table INPUTS OUTPUTS OE OE I4 Y Ya 0 0 olo 1 o o l o0 IET d MEE We Su NA NM OF ll High voltage level Low voltage level Don t care High impedance off state P 5 10574xx367 Hex Buffer Driver w 3 state This device features high fan out improved fan in and can be used to drive terminated lines down to 133 ohms Hex buffer driver truth table sl 0 X Z High impedance off state P 56 High voltage level Low voltage level Don t care Electronics Workbench 74XX P 5 10674xx368 Hex Inverter Buffer Driver w 3 state This device is a 3 state hex inverter buffer driver Hex inverter buffer driver truth table INPUTS OUTPUTS OE In Yn Y 0 0 0 1 0 A I 0 1 Z Z 1 High voltage level 0 Low voltage level X Don t care Z High impedance off state P 5 10774xx37 Quad 2 In NAND This device contains four independent 2 input NAND gates Logic function NAND gate truth table Multisim User Guide P 57 seues Xxv4 suonounJj Functio
139. 0 1 0 COUNT UP 1 x X X x RESET O 2 77 4518 Dual BCD Counter O 46 CPOA 34 cP1A T MRA 00A DIA D2A O3A DEEE The 4518 device is a dual 4 bit internally synchronous BCD counter BCD counter truth table CPO CP1 MR MODE 1 0 D ooo o COUNTER ADVANCES COUNTER ADVANCES NO CHANGE NO CHANGE NO CHANGE NO CHANGE 00 TO O3 LOW Electronics Workbench 4000 Series ICs O 2 78 4519 Quad Multiplexer O 2 79 4520 Dual Binary Counter ERRE 10 Bo Ad B1 B2 B3 SA SB 00 01 02 03 4 2 7 CPOA 3Q cP1A OZA T MRA 00A 01A ol al als O3A The 4519 device provides four multiplexing circuits with common select inputs SA SB Each circuit contains two inputs An Bn and one out put On The 4520 device is a dual 4 bit internally synchronous binary counter Binary counter truth table CPO CP1 MR MODE J X Multisim User Guide Ho O OQ OG GOO COUNTER ADVANCI COUNTER ADVANCI NO CHANGE NO CHANGE NO CHANGE NO CHANGE ES ES 00 TO O3 LOW O 47 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 80 4522 4 bit BCD Down Counter The 4522 device is a synchronous programmable 4 bit BCD down counter with an active HIGH and an active LOW clock input CPO CP1 an asynchronous parallel load input PL four
140. 0 1 1 1 1 1 4 0 1 0 0 1 1 1 1 0 1 1 1 1 5 0 1 0 1 1 1 1 1 1 0 1 1 1 6 0 1 ji 0 1 1 1 1 1 1 0 1 1 7 0 1 1 1 1 1 1 1 1 1 1 0 1 8 1 0 0 0 1 1 1 1 1 1 1 1 0 9 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 ep a 0 1 1 1 1 1 1 1 1 1 1 1 nla 1 0 0 1 1 1 1 1 1 1 1 1 E 1 1 0 1 1 1 1 1 1 1 1 1 1 Hla 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P 5 12574xx46 BCD to seven segment dec The 7446 BCD Binary Coded Decimal to seven segment decoder translates a 4 bit BCD input into hexadecimal and outputs high on the output pins corresponding to the hexadecimal representation of the BCD input There are provisions for lamp testing and for blanking the outputs Multisim User Guide P 69 seues Xxv4 suonounJj Functions 74XX Series BCD to seven segment decoder OUTPUTS INPUTS gt GHA al D LT RBI No 10 11 12 13 14 15 BI RBI LT P 5 12674xx465 Octal BUFFER w 3 state Out This device has a two input active low AND enable gate controlling all eight data buffers Octal buffers truth table Electronics Workbench High impedance off Z P 70 seues XXPZ suonounJj 74XX P 5 12774xx466 Octal BUFFER w 3 state Out This device has a two input active low AND enable gate controlling all eight data buffers Octal buffers truth table G1 G2 aly 0 0 0 1 0 0 1 0 L 0 X Z 0 HE X Z L 1 X Z Z High impedance of
141. 1 H A3 NOT Gate cinco Ede aia ata path Gat er ec Rr ss ced ed H 2 H1 4 NOR Gale 2 00 00 8 04 Da keen xu Para eid H 2 HAD NAND Gale usu bte LE IR REESE ee eh wae H 3 H 1 6 XOR Gate Exclusive OR o ococccoccocco ee H 4 H 1 7 XNOR Gate Exclusive NOR 00000 eee eee eae H 4 H 1 8 Tristate Buffer opel Rhe rea debe ween H 5 Fs 129 Bunter tix x ze Ka ans c Bihan E A H 5 H 1 10Schmitt Tigger ossia a nieri e AE A re H 6 VADI de RNA H 6 Line Receiver iii Ss bed ped Oe dede eae xis H 9 ENE DRIVEN mato fateh DE e e Negare males UL igo ted vrbs ater Dee D OMS aes H 9 Line TrAnscelVet fis vA rca E Ek a UR Mr inrer Au Mp ers do es H 9 Multisim User Guide eui OSIN Misc Digital Electronics Workbench Appendix H Misc Digital Components H 1 TIL Components H 1 1 AND Gate n u This component has a high output only when all inputs are high B AND gate truth table Boolean Expression y a b y a amp b H 1 2 OR Gate i This component has a high output when at least one input is high v gt OR gate truth table Multisim User Guide H 1 e16iq OSIN Misc Digital Misc Digital Components Boolean Expression y a b y ajb H 1 3 NOT Gate This component inverts or complements the input signal If the input is high A be the output is low and vice versa NOT gate truth table a 0 1 1 0 Boolean Expression ox Ho og Ms H 1 4 NOR Gate This component is
142. 1 X 0 X X X X 1 1 1 1 JT 1 1 ab 0 1 0 0 0 0 0 1 1 1 1 1 1 I 0 1 0 0 0 2 X 0 1 1 1 1 1 T 0 1 0 0 1 0 El 1 0 1 1 1 de i 0 1 0 0 n 1 I 1 1 0 1 1 i 1 0 1 0 1 0 0 E 1 1 1 0 1 de 1 0 I 0 1 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 1 d 1 1 0 de 0 1 0 d 1 1 I 1 B 1 1 4 1 0 1 1 0 X X X Output corresponding to stored address 0 all others 1 P 5 28 74xx139 Dual 2 to 4 Dec DEMUX This decoder demultiplexer contains two individual two line to four line decoders It features fully buffered inputs each of which represents only one normalized load to its driving circuit 2 to 4 decoder demultiplexer truth table INPUTS OUTPUTS ENABLE SELECT COO OF al e Ho o x u Hhorox RhRROoR DHponnu Donmnnnun O HH HH P 5 29 74xx14 Hex INVERTER Schmitt A key feature of this integrated circuit is its high noise immunity Due the to the Schmitt trig ger action this device is ideal for circuits that are susceptible to unwanted small signals such as noise P 14 Electronics Workbench 74XX INVERTER gate truth table A Y 0 E 1 0 The voltage threshold levels are as follows VT VT P 5 30 74xx145 BCD to Decimal Dec 0 95V 1 8V at 5 Volt test condition at 5 Volt test condition The BCD to decimal decoder driver consists of eight inverters and ten four input NAND gates These decoders feature high performance n p n output transistors designed for use as indicator relay drivers or as open collector logic circui
143. 1 of 16 Dec DEMUX w Input latches ooocoo ooooo O 44 4516 Binary up down Counter 2 2 2222 ernennen eee 0 45 4518 Dual BCD Counter 222m nennen een een nennen O 46 4519 Quad Multiplexer oo ooocoooooocooooa IIIA O 47 4520 Dual Binary Counter coooccccocco eee O 47 4522 4 bit BCD Down Counter o o ooccccccocc ee O 48 4526 4 bit Bin Down Counter sssaaa 0 0000 cee eese O 48 4531 13 input Checker Generator 0 000 cece eee 0 48 4532 8 bit Priority Enc liliis O 49 4539 Dual 4 input Multiplexer llle eee O 50 4543 BCD to seven segment latch dec driver o o ooo o O 50 4544 BCD to seven segment latch dec ooococccoccooo O 52 4555 Dual 1 of 4 Dec DEMUX 02 0000 cece O 53 4556 Dual 1 of 4 Dec DEMUX oooococcccccco eee O 53 4585 4 bit Comparator o ooococcccc se O 54 Multisim User Guide sanas 000p suonounJ Functions 4000 series Electronics Workbench Appendix O Functions 4000 Series O 1 CMOS The complementary MOS CMOS logic family uses both P and N channel MOSFETS in the same circuit CMOS is faster and consumes less power than gt o the other MOS families 400080 U1A CMOS ICs provide not only all of the same logic functions available in TTL but also several special functions not provided by TTL The 74C series is pin compatible pin configuration of the two ICs are the same
144. 11 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series VT 1 8V at 5 Volt test condition VT 0 95V at 5 Volt test condition P 5 23 74xx133 13 In NAND Logic function Y ABCDEFGHIJKLM NAND gate truth table INPUTS A THRU M Y All inputs 1 0 One or more inputs 0 1 P 5 24 74xx134 12 In NAND w 3 state Out 12 Input NAND with 3 state outputs INPUTS A THRU L oc Y All inputs 1 0 0 One or more inputs 0 0 1 Don t care 1 Z Z high impedance off P 12 Electronics Workbench 74XX P 5 25 74xx135 Quad Ex OR NOR Gate This device can operate as Exclusive OR gate C input low or as Exclusive NOR gate C input high Exclusive OR NOR gate truth table PPOOPRPpOoO ol INPUTS OUTPUT B c Y 0 0 0 i 0 1 0 0 1 1 0 0 0 1 1 al 1 0 0 T 0 1 I 1 P 5 26 74xx136 Quad 2 in Exc OR gate This device is a quadruple 2 input exclusive OR gate with open collector outputs Exclusive OR gate truth table OUTPUT Y INPUTS A B 0 0 0 1 1 0 1 i opero P 5 27 74xx138 3 to 8 Dec This device decodes one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs Multisim User Guide P 13 seues Xxv4 suonounJj Functions 74XX Series Functions 74XX series 3 to 8 decoder demultiplexer truth table SELECT GL Gl G2 C B A Y0 Yl Y2 Y3 Y4 Y5 Y6 Y7 X X 1 X X X 1 1 1 1 1 1 1
145. 12 AC small signal model E 14 model E 13 parameters and defaults E 14 time domain model E 13 sensing switches N 1 sine wave L 9 sine wave generator C 9 source AC current C 4 AC voltage C 3 amplitude modulation C 4 current controlled current C 8 current controlled voltage C 7 DC current C 3 DC voltage C 2 exp current C 22 exp voltage C 21 frequency modulated C 5 frequency shift key modulated C 6 nonlinear dependent C 22 piecewise linear current C 18 piecewise linear voltage source C 15 polynomial C 20 pulse current C 20 pulse voltage C 18 Vcc voltage C 3 voltage controlled current C 8 Electronics Workbench voltage controlled piecewise linear C 14 voltage controlled voltage C 7 square wave L 9 square wave generator C 7 strip line M 3 Strobed hex INVERTER O 38 summer three way L 21 switch push button N 3 types of D 1 Sync 4 bit Bin Counter P 24 Sync 4 bit Bin Up down Counter P 34 Sync 4 bit Binary Counter P 25 Sync 4 bit Decade Counter P 25 Sync 4 bit Decade Counter clr P 23 Sync 4 bit up down Binary Counter P 28 Sync 4 bit up down Counter P 33 Sync BCD Up down Counter P 33 P 34 T terminal types of N 3 three way summer about L 21 equations L 23 parameters and defaults L 23 timed contact types of N 2 time domain model bipolar junction transistors F 4 capacitors D 5 diac E 15 diodes E 3 inductors D 9 MOSFET F 13 SCR E 13 timer 1 3 transfer function block about L 6 equations L 6 Multisim User Gu
146. 2 Dual 4 In NAND ssssssse e nh O 6 0 2 10 4013 Dual D type FF edge o0cococoocccccooc nn nn O 7 0 2 11 4014 8 bit Static Shift Reg 00 ee O 7 0 2 12 4015 Dual 4 bit Static Shift Reg 0 00 02 O 8 0 2 13 40160 4 bit Dec Counter ooococcccccoo esee O 9 O 2 14 40161 4 bit Bin Counter ooooooccoccoo ee O 10 0 2 15 40162 4 bit Dec Counter oooococcccccoo ee O 10 0 2 16 40163 4 bit Bin Counter oooooccccccooc ee O 10 O 2 17 4017 5 stage Johnson Counter oococcccccccc nn O 11 0 2 18 40174 Hex D type Flip flop 0 0 00 cee ee O 12 0 2 19 40175 Quad D type Flip flop lisse O 12 0 2 20 4018 5 stage Johnson Counter oococcccccccc O 13 0 2 21 4019 Quad 2 In MUX annaua 0 0 en O 14 0 2 22 40192 4 bit Dec Counter oooccoccccccoo eee O 14 0 2 23 40193 4 bit Bin Counter ooooooccccccooc ee O 15 0 2 24 40194 4 bit Shift Register liiis O 15 0 2 25 40195 4 bit Shift Register liliis O 15 Multisim User Guide seues 0007 suonouny Functions 4000 series O 2 26 O 2 27 O 2 28 O 2 29 O 2 30 O 2 31 O 2 32 O 2 33 O 2 34 O 2 35 O 2 36 O 2 37 O 2 38 O 2 39 O 2 40 O 2 41 O 2 42 O 2 43 O 2 44 O 2 45 O 2 46 O 2 47 O 2 48 O 2 49 O 2 50 O 2 51 O 2 52 O 2 53 O 2 54 O 2 55 O 2 56 O 2 57 O 2 58 O 2 59 O 2 60 O 2 61 O 2 62 O 2 63 O 2 64 O 2 65 O 2 66 O 2 67 4020 14 stage Bin Counter
147. 2 1 3 1 BNF stimulustable id table lt delay expression probe lt lt probe gt gt delay constant lt data gt lt delay constant gt lt data gt Multisim User Guide B 2 5 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 6 endtable endstimulustable probe data format variable lt variable lt strobe gt gt if data format is omitted then h is assumed data format h For replacing an existing stimulus table after prep stimulustable id table lt delay expression lt delay constant gt lt data gt lt delay constant gt lt data gt endtable endstimulustable B 2 1 3 2Stimulustable stimulustable is a behavioral statement and can be located anywhere any statement can be placed e g for i l i lt 8 i 1 1 repeat 8 times the input pattern stimulustable endstimulustable There is no limit to the number of stimulustable statements They are not required to be located in top level modules The syntax for the stimulustable keywords must be lower case Such as the keyword table must be lower case Variable names are upper lower case sensi tive Any number of input or expected value columns may appear in a stimulustable Each input column is identified by a variable which is driven by the data in the column Each expected value column is identified by an sign The variable on the left side of an sign is verifie
148. 3 Strip LING oribus tue oup ls sede a mde EM PME M 3 Multisim User Guide Ju Electronics Workbench Appendix M RF Components M 1 M 2 RF Capacitor c1 RF capacitors at RF frequencies show behaviors different from the regular E capacitors at low frequencies RF capacitors at RF frequencies act as a com samp g bination of a number of transmission lines waveguides discontinuities and dielectrics The dielectric layers are usually very thin typically 0 2 Mum The equations governing these types of capacitors follow those of transmission lines there fore each RF capacitor is described by inductance per unit length resistance per unit length shunt capacitance per unit length and shunt conductance per unit length Depending on the type of the technology used practical capacitance values are in the range between several picofarads and several nanofarads These capacitors are used for coupling or bypassing for frequencies up to approximately 20 GHz One type of RF capacitor is called an interdigital capacitor Both conductors of the capacitor are in the same plane which is the top surface of the dielectric substrate used Each conductor or external node of the capacitor is structured by connecting a number of transmission lines in parallel In other words the planar structure uses N thin parallel conducting strips of length L linked alternately to one or other two strips of length W running perpendicularly alongside the
149. 33 seues 000p suonounJ Functions 4000 series Functions 4000 Series Logic function Y ABCD AND gate truth table A B C D Y 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 al 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 T 1 i 0 2 63 4085 Dual 2 Wide 2 In AND OR INVERTER O 34 elsi en aia 11 12 This device contains a combination of gates AND OR and INVERTER Logic function Oa Ao A Az Az A Op Bg B4 B5 B4 B Electronics Workbench 4000 Series ICs Inverter gate truth table OUTPUT INPUTS Functions 4000 series O 35 Multisim User Guide Functions 4000 series Functions 4000 Series 0 2 64 4086 4 Wide 2 In AND OR INVERTER This device contains a combination of gates AND OR and INVERTER 1 3 p oO Logic function I 1 1 gt 213 1 1I5 1 17 1g 1l9 Inverter gate truth table IO I1 I2 X X X X X X AS 1 X X X T X X X X X X ANY OTH x FM MM X INPUTS I4 I5 X X X X X X X X 1 1 X X Dr P4 o 1 P P4 P4 P4 P 1 x MM 5M ox HD ER COMBINATION OF INPUTS x Me MM OM OUTPUT a m XE e A ano AS 0 2 65 4093 Quad 2 In NAND Schmitt This device contains four independent 2 input NAND gates Due the to the O 36 Logic function NAND gate truth table Schmitt tri
150. 3874xx76 Dual JK FF pre clr This device contains two independent J K flip flops with individual J K clock preset and clear inputs JK flip flop truth table PRE CLR CLK JJ Klo Q 0 1 X X 1 0 1 0 X X X 0 1 0 0 X X X 1 1 1 T 0 0 Hold 1 1 1 0 d 0 1 1 0 1 0 1 1 T 4 1 Toggle P 5 13974xx77 4 bit Bistable Latches pulse triggered level sensitive This 4 bit latch is available in a 14 pin flat package Bistable latch truth table P 5 14074xx78 Dual JK FF pre com clk amp clr D e L H 0 A 1 0 1 1 jd 0 X 0 Hold The 7478 contains two negative edge triggered flip flops with individual JK individual pre set common clock and common clear inputs Multisim User Guide P 77 seues Xxv4 suonounJj Functions 74XX Series Functions 74XX series JK flip flop truth table PRESET CLEAR J K CLOCK Q Q 0 X X X 1 0 1 0 X X X 0 1 0 0 X X X 1 1 unstable 1 1 0 0 no change X 1 0 E 1 L 1 RE 0 n ib 0 T 1 1 T toggle 1 1 X X 1 no change This configuration will not persist when preset and clear are inactive Transition from high to low P 5 14174xx82 2 bit Bin Full Adder This device performs the addition of two 2 bit binary numbers 2 bit binary full adder truth table INPUTS OUTPUTS WHEN CO L WHEN CO H Al B1 A2 B2 S1 S2 C2 Sg1 S2 Cc2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0
151. 4LS373 LATCH 74LS374 FLIP FLOPS 74LS375 LATCH 74LS377 D FLIP FLOPS 74LS378 D FLIP FLOPS 74LS379 D FLIP FLOPS 74LS381A ALU 74LS382A ALU 74LS384 MULTIPLIER 74LS385 ADDER SUBTRACTOR 74LS386A XOR 74LS390 DECADE COUNTER 74LS393 BINARY COUNTER 74LS395A SHIFT REG 74LS396 FLIP FLOPS 74LS399 MUX WITH STORAGE 74LS422 MONOSTABLE MULTIVIBRATOR 74LS440 TRANSCEIVER 74LS441 TRANSCEIVER Electronics Workbench Verilog Libraries Multisim User Guide Name Description 7415442 TRANSCEIVER 7415444 TRANSCEIVER 74LS446 TRANSCEIVER 74LS449 TRANSCEIVER 74LS465 BUFFER 74LS466 BUFFER 74LS467 BUFFER 74LS468 BUFFER 74LS490 DECADE COUNTER 74LS540 BUFFER 74LS541 BUFFER 74LS590 BINARY COUNTER 74LS591 BINARY COUNTER 74LS592 BINARY COUNTER 74LS593 BINARY COUNTER 74LS594 SHIFT REG 74LS595 SHIFT REG 74LS596 SHIFT REG 74LS597 SHIFT REG 74LS598 SHIFT REG 74LS599 SHIFT REG 74LS604 LATCH 74LS606 LATCH 74LS607 LATCH 74LS620 TRANSCEIVER 74LS621 TRANSCEIVER B 2 71 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 72 Name Description 74LS623 TRANSCEIVER 74LS639 TRANSCEIVER 74LS640 TRANSCEIVER 74LS641 TRANSCEIVER 74LS642 TRANSCEIVER 74LS644 TRANSCEIVER 74LS645 TRANSCEIVER 74LS646 TRANSCEIVER REGISTERS 74LS647 TRANSCEIVER REGISTERS
152. 5 2 Project Open Opens the Open Project screen to specify the name for opening an existing project Click Open to open the project Click Cancel to exit the menu Before opening a project the SSE is automatically reset so that the results from any previous project are lost Multisim User Guide B 3 9 snus 111 SOS Silos II Menus Silos III Menus B 3 5 3 Project Files Opens the Project Files screen for specifying the input files and library files for a project To select a project for the Project Files screen use Project New or Project Open The File Group list box allows you to select Verilog HDL Source Files Library Files and PLI Library Files To add source files have the Source Files option selected in the File Group box Next double click on a file name in the list box or highlight a file name in the list box and click Add to add the source file to the Files in Group list box Files can be deleted from the project by highlighting the file name in the Files in Group box and clicking Remove The Move Up and Move Down buttons allow you to rearrange the file names in the Files in Group list box Click Ok to update the project and close the screen and Cancel to exit the screen without affecting the project To specify library files click on the drop down arrow in the File Group list box in the Project Files screen and select Library Files Double click on library file names in the list box to add them to the Fil
153. 55 i Multisim User Gui HIGH state the more positive voltage LOW state the less positive voltage state is immaterial 6 Dual 1 of 4 Dec DEMUX This device contains two independent 1 of 4 decoders demultiplexers de O 53 seues 000p suonounJ Functions 4000 series Functions 4000 Series Decoders demultiplexer truth table INPUTS OUTPUTS E A0 a loo 01 02 03 olo olo 2 1 1 oli 0 1 0 1 1 ollo ali 1 O0 1 oli l 1 1 0 1 xXx X 1 1 1 1 O 2 89 4585 4 bit Comparator O 54 is ct i s Bs i M i og BO B1 AT B2 B3 APB A B ASB lalala The 4585 device is a 4 bit magnitude comparator that compares two 4 bit words A and B whether they are less than equal to or greater than Each word has four parallel inputs A0 to A3 and BO to B3 Electronics Workbench 4000 Series ICs 4 bit comparator truth table COMPARING INPUTS ee OUTPUTS INPUTS A3 B3 A2 B2 Al Bl AO BO IA gt B IA lt B IA B OA gt B OA B OA B A3 gt B X X X 1 X X 1 0 0 A4 B4 X X x x X X 0 1 0 Az B A2 gt B X x 1 X X 1 0 0 A3 B A lt B X x x X x 0 1 0 A3 B A B A gt B X 1 X X 1 0 0 A3 B A B A lt By X x X X 0 1 0 A3 B3 A5 B5 Ai B4 Ao gt Bo z X X 1 0 0 A3 B A B A B Ao lt Bo x X X 0 1 0 A3 B A B A B Ao Bo X 0 1 0 0 1 A3 B3 A5 B5 Ai B4 Ao Bg 1 0 0 1 0 0 A3 B A B A B Ao Bo x 1 0 0 1 0 A3 B A B A B Ao Bo X 1 1 0 1 1 A3 B A B A B Ao
154. 8 bit shift register has gated serial inputs and an asynchronous clear Shift register truth table Clear Clk A B QA QB Q 0 x x xlo oo 1 o x X QA0 QBO QHO 1 i x QAn QGn 1 0 X QAn QGn 1 X 0 QAn QGn P 26 Electronics Workbench 74XX positive edge triggered QAO OBO the level of QA QB QH respectively before the QHO indicated steady state input conditions were established QAn QGn the level of QA or QG before the most recent positive transition of the clock indicates one bit shift P 5 50 74xx165 Parallel load 8 bit Shift Reg This serial shift register shifts the data in the direction of QA toward QH when clocked To load the data at the 8 inputs into the device apply a low level at the shift load input This reg ister is equipped with a complementary output at the eighth bit Shift register truth table INTERNAL INPUTS O P OUTPUTS SHIFT PARALLEL s CLK INH CLK SERIAL QA QB QH LOAD A B Cc D 0 X X X a b p d a b h 1 0 0 X X X X X QAO QBO QHO T 0 1 X X X X 1 QAn QGn 1 0 0 X X X X 0 QAn QGn 1 al X X X X X X QAO QBO OHO transition from low to high a b c d the level of steady state input at A B C or D respectively P 5 51 74xx166 Parallel load 8 bit Shift Reg This shift register is a parallel in or serial in serial out device It shifts the data in the direc tion of QA toward QH when clocked It features an active low clear input To load the data at
155. A B F A MINUS B MINUS 1 F A MINUS 0 1 1 F A B F A B F A B PLUS1 1 0 0 F AB F A PLUS A B F A PLUS A B PLUS 1 1 0 1 F A B F A PLUS B F A PLUS B PLUS 1 0 1 0 F B F AB PLUS A B F AB PLUS A B PLUS 1 1 0 1 1 F A B F A B F A B PLUS 1 1 1 0 0 F 0 F A PLUS A F A PLUS A PLUS 1 1 1 0 1 F AB F AB PLUS A F AB PLUS A PLUS 1 1 1 1 0 F AB F AB PLUS A F AB PLUS A PLUS 1 1 1 1 1 F A F A F A PLUS 1 P 5 59 74xx182 Look ahead Carry GEN The high speed look ahead carry generator can anticipate a carry across four binary adders or groups of adders It is cascadable to perform full look ahead across n bit adders Truth table for G output INPUTS OUTPUT G3 G2 G1 G0 P3 P2 P1 G 0 X X X X X X 0 X 0 X X 0 X X 0 X X 0 X 0 0 X 0 X X X 0 0 0 0 0 All other combinations 1 Multisim User Guide P 31 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series Truth table for P output INPUTS OUTPUT ul P3 P2 Pl PO All other combinations E Truth table for Cn x output INPUTS OUTPUT GO PO Cn Cn x 0 X X 1 X 0 jT 1 All other combinations 0 Truth table for Cn y output INPUTS OUTPUT Gl GO P1 PO Cn Cn y 0 X X X X 1 X 0 0 X X 1 X X 0 0 1 1 All other combinations 0 Truth table for Cn z output INPUTS OUTPUT G2 G1 GO P2 P1 PO Cn Cnez 0 X X X X X X ME X 0 X 0 X X X 1 X X 0 0 0 X X I X X X 0 0 0 1 1 All othe
156. ARATOR 74LS86A 2 INPUT XOR 74LS90 DECADE COUNTER 74LS91 8 BIT SHIFT REGISTER 74LS92 DIVIDE BY 12 COUNTER 74LS93 4 BIT BINARY COUNTER 74LS95 4 BIT SHIFT REG Electronics Workbench Verilog Libraries Multisim User Guide Name Description 74LS96 5 BIT SHIFT REG 74LS107A JK FLIP FLOP 74LS109A JK FLIP FLOP 74LS112A JK FLIP FLOP 7ALS113A JK FLIP FLOP 7ALS114A JK FLIP FLOP 74LS122 MONOSTABLE MULTIVIBRATOR 74LS123 MONOSTABLE MULTIVIBRATOR 74LS125A TRI STATE BUFFERS 74LS126A TRI STATE BUFFERS 74LS132 2 INPUT NAND SCHM TRIG 74LS136 2 INPUT XOR OC 74LS137 3 TO 8 DECODER 74LS138 3 TO 8 DECODER 74LS139A 2 TO 4 DECODER 74LS147 PRIORITY ENCODER 74LS148 PRIORITY ENCODER 74LS151 MUX 8 TO 1 74LS153 MUX 4 TO 1 74LS155A 2 TO 4 DECODER 74LS156 2 TO 4 DECODER OC 74LS157 2 TO 1 MUX 74LS158 2 TO 1 MUX 74LS160A SYNC 4 BIT COUNTER 74LS161A SYNC 4 BIT COUNTER 74LS162A SYNC 4 BIT COUNTER B 2 67 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 68 Name Description 74LS163A SYNC 4 BIT COUNTER 74LS164 8 BIT SHIFT REG 74LS165A PARALLEL LOAD BIT SHIFT REG 74LS166A PARALLEL LOAD BIT SHIFT REG 74LS169B UP DOWN BINARY COUNTER 74LS170 4 4 REGISTER FILE OC 74LS171 D FLIP FLOP 74LS173A D FLIP FLOP WITH 3 STATE 74LS174 D FLIP FLOP 74L
157. Appendix A VHDL Primer A 1 A 2 A 3 A 4 VHDL Standards Histofy 2 rae em nen Reges E AE A 1 A 1 1 IEEE Standard 1076 oooccccccccoc len A 1 A 1 2 IEEE Standard 1164 oococccocooccn eee A 1 A 1 2 1IEEE Standard 1076 3 Numeric Standard 222222200 A 2 A 1 2 2IEEE Standard 1076 4 VITAL ssesselleeeeel lees A 2 Learning VADL ua wessen De ar peg ewe DEP a A 3 AZT A Simple Example lead ue an er Ve EEG E i ded A 3 A 2 2 Entity Declarations llle A 4 A 2 3 Architecture Declarations llis A 5 A 2 4 Data Types osa ERE ae ee A 6 A 2 5 Desigm Unils 2 4 2 00 sme Rex a RE digerere d A 6 A 2 6 Levels of Abstraction oooooocoooccrne eh A 9 A 2 6 1 Sample Circuit sce is ubere ue xe ein A 10 A 2 6 2Comparator Dataflow lille A 11 A 2 6 3Barrel Shifter Entity liliis A 13 A 2 6 4Signals and Variables llli illis A 17 A 2 6 5Using a Procedure ooococoooccco eee A 17 A 2 6 6Structural VHDL 1 eres A 19 A 2 6 7 Design Hierarchy lille A 20 A2 6 8Test Benches s wea ten as A 21 A 2 6 9Sample Test Bench 2 222 css eee A 21 reu A 23 Examples Gallery nr 2 erh A jaw eive rwr xti A 23 A 4 1 Using Type Version Functions A 23 A 4 1 1Design Description ooooccococcocoeoo e A 24 AA 1 2 Test Bench ue REED A 26 A 4 2 Describing a State Machine o oococcoccococcnc nen A 27 A 4 2 1Design Description 0
158. BO is open or held high and a low is applied to the lamp test input all segment outputs are high Electronics Workbench 74Xx P 5 79 74xx25 Dual 4 In NOR w Strobe This device contains two independent 4 input NOR gates with strobe NOR gate with strobe truth table x OM MM E x OM KH MM Uu x OM FP eM MIA x OR MM x U O XPRRPRA hbRooo Oo K P 5 80 74xx251 Data Sel MUX w 3 state Out This device contains full on chip binary decoding to select one of eight data sources and has a strobe controlled three state output Data selector multiplexer truth table INPUTS OUTPUTS SELECT STROBE c BA s Y X X X 1 Z Z 0 0 0 0 DO DO 0 0 1 0 D1 DI 0 1 0 0 D2 D2 0 1 1 0 D3 D3 1 0 0 0 D4 D4 1 0 1 0 D5 D5 1 1 0 0 D6 D6 1 1 1 0 D7 D7 Z high impedance off DO D1 D7 level of the respective D input Multisim User Guide P 45 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 81 74xx253 Dual 4 to 1 Data Sel MUX w 3 state Out This Schottky clamped data selector multiplexer contains inverters and drivers to supply fully complementary on chip binary decoding data selection to the AND OR gates Data selector multiplexer truth table KB A ida Cr c2 c3 mox X X X X X X 1 Z 0 0 0 X X X 0 0 0 0 1 X X X 0 1 0 1 X 0 X X 0 0 0 d X 1 X X 0 1 1 0 X X 0 X 0 0 1 0 X X 1 X 0 1 1 I X X X 0 0 0 1 d X X X L 0 1 Z High impedance off P 5 82 74xx257 Quad 2 to 1
159. BO QCO QDO transition from low to high a b c d the level of steady state input at inputs A B C or D respectively QAO QB0 QC0 the level of QA QB QC or QD respectively before QDO the indicated steady state input conditions were estab lished QAn QBn QCn the level of QA OB QC or QD before the most recent QDn negative transition of the clock P 5 65 74xx195 4 bit Parallel Access Shift Reg This 4 bit register has parallel inputs parallel outputs J K serial inputs shift load control input and a direct overriding clear Multisim User Guide P 35 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series Shift register truth table SERIAL PARALLEL OUTPUTS crear SEFT om g K A B C D QA QB oc QD QD LOAD 0 X X X X X X X X 0 0 0 0 1 1 0 X X a b c d a b c d d 1 1 0 x x X X X X QAO QBO QCO QDO QDO 1 1 0 1 X X X X QAO QAO QBn QCn QCn 1 1 0 0 X x X X 0 QAn QBn QCn QCn 1 1 1 X X X X 1 QAn QBn QCn QCn 1 1 1 0 x X X X QAn QAn QBn QCn QCn transition from low to high a b c d the level of steady state input at inputs A B C or D respectively QAO QBO QCO the level of QA QB QC or QD respectively before QDO the indicated steady state input conditions were estab lished QAn QBn QCn the level of QA QB QC before the most recent negative transition of the clock P 5 66 74xx198 8 bit Shift Reg shl shr ctrl P 36 This bidirectional register has
160. Circuit Component Properties dia log box The final current I allowed to flow through the core is used to obtain a value for the voltage reflected back across the terminals It is calculated as I BA where A cross sectional area Multisim User Guide oiseg Basic Basic Components D 14 2 Magnetic Core Parameters and Defaults Symbol Parameter Name Default Unit A Cross sectional area 1 m L Core length 1 m ISD Input smoothing domain 1 N Number of co ordinates 2 H1 Magnetic field co ordinate 1 0 A turns m H2 Magnetic field co ordinate 2 1 0 A turns m H3 H15 Magnetic field co ordinates 0 A turns m B1 Flux density co ordinate 1 0 Wb m B2 Flux density co ordinate 2 1 0 Wb m B3 B15 Flux density co ordinates 0 Wb m D 15 Coreless Coil This component is a conceptual model that you can use as a building D 20 T2 1 Turns block to create a wide variety of inductive and magnetic circuit models Typically you would use the coreless coil together with the magnetic core to build up systems that mock the behavior of linear and nonlinear magnetic components It takes as input a current and produces a volt age The output voltage behaves like a magnetomotive force in a mag netic circuit that is when the coreless coil is connected to the magnetic core or some other resistive device a current flows Electronics Workbench Coreless Coil D 15 1 Characteristic Equ
161. Components Misc v0 vo i 0 ide where the transmission line stretches from x coordinates 0 to 1 I line length V x t voltage at point x at time t i x t current in the positive x direction at x at time t v 0 t voltage at point 0 at time t i 0 t currentin the positive x direction at O at time t v x 0 voltage at point x at time 0 i x 0 currentin the positive x direction at x at time O The set of equations is first transformed into a pair of coupled ordinary differential equations in x and s using the Laplace transformation The equations are then reformulated for numeri cal convolution Finally inverse Laplace transforms are taken to return them to the time domain form K 12 2 Lossy Transmission Line Model Parameters and Defaults Symbol Parameter Name Default Unit Len Length of the transmission line 100 m Rt Resistance per unit length 0 1 Q Lt Inductance per unit length 1e 06 H Ct Capacitance per unit length 1e 12 F Gt Conductance per unit length 1e 12 mho REL Breakpoint control 1 ABS Breakpoint control 1 Note A lossy transmission line with zero loss can be used to model the lossless transmission line and may be more accurate K 16 Electronics Workbench Lossless Line Type 1 K 13 Lossless Line Type 1 Wi This component is a 2 port network that represents a medium such as a wire or an interconnect through which electrical signals pass
162. D Positive Edge Triggered Flip Flop STD377 VHD Octal D Type Flip Flop with Enable 8 Bit Hold Register STD38 VHD Quadruple 2 input positve NAND buffers STD521 VHD 8 Bit Identity Comparator STD533 VHD D Latch with 3 State Outputs STD541 VHD Driver with 3 state output STD543 VHD Latched Transceiver STD544 VHD Inverting Latched Transceiver STD574 VHD Positive Edge Triggered Flip Flop STD640 VHD Bidirectional Bus Transceiver STD652 VHD Registered Bus Transceiver with 3 State Output STD74 VHD Positive Edge Triggered Flip Flop STD821 VHD Bus Interface Flip Flop with 3 State Output STD823 VHD Bus Interface Flip Flop with 3 State Output STD825 VHD Buffer with 3 state output STD827 VHD Buffer with 3 state output STD832 VHD 2 input positve OR gate STD86 VHD 2 input exclusive OR gate STD869 VHD Synchronous 8 Bit Up Down Counter STD952 VHD Registered Transceiver with 3 State Output STDH244 VHD Line driver with 3 state output and bus hold STDH245 VHD TTL Transceiver with bus hold STDH374 VHD Positive Edge Triggered Flip Flop with bus hold STDH543 VHD Latched Transceiver with bus hold STDH652 VHD Reg Bus Transceiver with 3 State Output and Bus Hold Electronics Workbench Line Receiver H 3 H 4 H 5 STDH952 VHD Registered Transceiver with 3 State Output and bus hold SY69167 VHD 64 X 18 FIFO Line Receiver Line receivers are devices which are used in applications such as a bridge between analog sig na
163. E Us enc a ess aA B3 5 B 3 9 3bEdit CODy u 3 8 ir aa a Be a pn Res B3 5 BS SAEAVR sier ss it Ei aie RE xm LER ORT XE ca T B3 6 B SB5EAVElEaR 2 tau Pda ead hae ere D arx pde de te m den B3 6 B 3 3 6EdiUSelect All u Bi ar ur otn ah ee a P LOT B3 6 BO CEH FING corta N ER E ia d ud B3 6 B 3 3 8EdiUFind Next oda 4A seed Geared wun hast a B3 6 B 3 3 9Edit Replace ooooococcococcn hn B3 6 B 33 10EdIUGOtO LINS iia a ad B3 7 B 3 4 View Menis aee praia ad A Sie et m S Ru DA The RRS lens tg B3 7 B S41View Zoom ou by ev asa a esu mua dub a e Uk dk Pain das B3 7 B 3 4 1 1Zoomtall us ctt ett st ed s D Uy nt ed s Dew ys B3 7 B 3 4 1 2Z200M OUt 3 222 nu 2 E ura ERG Numer gae Dev Rd arg B3 7 B 3 4 1 3ZOOHElIT ne mere ee Y a qc B3 7 B 3 4 1 4Zoom markers 2 ooo B3 7 B 3 4 2View Main Toolbar lees RR RIRRRRRR III B3 7 B 3 4 3View Analyzer Toolbar lsssseeseee ree B3 8 B 3 4 4View Status Bar iacere buo quy heels mua dolre ter ma ede Ra e Ern B3 8 B 3 5 Project Menu cum eme ei SE Mr Eee RE dE B3 9 B 3 5AProject NGW A asses ir a ara uid Here cu Ed mg B3 9 B 3 5 2Projec Open 2 4 20 le an RR e RON Rn B3 9 Multisim User Guide snus 111 SOS Silos II Menus B 3 5 3Project Files llli rr B3 10 B 3 5 4Project Save ASh cipum e iaa aena iaei nne B3 10 B 3 5 5Project ClOSG secet ERREUR n HR cepe a ko B3 10 B 3 5 6Project Save Project State o oo ooooooocooorrrn nee B3 11 B 3 5 7Proje
164. F OFF OFF OFF OFF OFF OFF RBI 1 0 0 0 0 0 0 OFF OFF OFF OFF OFF OFF OFF LT 0 X X X X X 1 N ON ON ON ON ON ON Notes 1 The blanking input BI must be open or held at a high logic level when output functions 0 through 15 are desired The ripple blanking input RBI must be open or high if blanking of a decimal zero is not desired 2 When a low logic level is applied to the blanking input BI all segment outputs are off regardless of any other input 3 When ripple blanking input RBI and inputs A B C and D are at a low level with the lamp test input high all segment outputs go off and the ripple blanking output RBO goes to a low level response condition 4 When the blanking input ripple blanking output BI RBO is open or held high and a low is applied to the lamp test input all segment outputs are on Electronics Workbench 74XX P 5 77 74xx248 BCD to seven segment dec The BCD to seven segment decoder driver features active high outputs for driving lamp buffers It has full ripple blanking input output controls and a lamp test input BCD to seven segment decoder driver truth table DECIMAL INPUTS T OUTPUTS NOTE OR FUNCTION LT RBI D C B A RBEO a b c d e g 0 Et cos ene A As v0 dte a 1 b E X 0o 0o 0o la A 0 0 0 0 i 2 X vx ce cC E eG us ee VER OX 3 d 902 20 are e e A e A cq Doe CT 4 I X IA 2 a A o 0o l 1l 5 O e Al AAA AA 6 Poog 2e sho SX E oe e
165. FILA x x XM OF BP xx Om FY w ox MM HL UO HHRHHHro lx P 5 86 74xx266 Quad 2 In XNOR OC This device contains four independent 2 input EXCLUSIVE NOR gates Logic function Y s AGB Exclusive NOR gate truth table FH o O e OF o w FOOF K P 5 87 74xx27 Tri 3 In NOR This device contains three independent 3 input NOR gates Logic function Y A B C P 48 Electronics Workbench 74Xx NOR gate truth table POPOPOP oO gt P PRrRoOoOFRFH ool wW PPRPROOOO Aa oOoooooodn m P 5 88 74xx273 Octal D type FF D flip flop truth table CLEAR CLK transition from low to high P 5 89 74xx279 Quad SR latches The RS flip flop has an undesired operating condition where 1 levels at both inputs will cause both outputs to go to a O level This undefined condition must be avoided Circuits involving feedback will lead to a race condition where the output will be unpredictable RS flip flop truth table Bode wg 0 0 no change 0 1 0 1 1 0 1 0 1 1 X X undefined Multisim User Guide P 49 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 90 74xx28 Quad 2 In NOR This device contains four independent 2 input NOR gates Logic function A AB NOR gate truth table P 5 91 74xx280 9 bit odd even parity generator checker 9 bit odd even parity generator checker truth table NUMBER OF INPUTS A THROUGH I THAT ARE HIGH an
166. Guide A 35 JOWUd TAHA VDHL Prrimer VHDL Primer signal Clk Clr std ulogic Declare local signals signal Load std ulogic signal Data in std ulogic vector 15 downto 0 signal S std ulogic vector 15 downto 0 signal done std ulogic 0 constant PERIOD time 50 ns for DUT fib use entity work fib behavior Configuration Specification begin DUT fib port map Clk Clk Clr Clr Load Load Creates one Data_in gt Data_in S gt S instance Clock process variable c std ulogic begin while done 0 loop wait for PERIOD 2 Cc sl NOt E Clk lt c end loop end process read input process file vector file text is variable variable S expected variable str stimulus in variable err cnt variable file line line line line buffer begin wait until rising edge Clk while not endfile vector file A 36 is a standard type 0 Background clock process The done flag indicates that we are finished and can stop the clock in testfib vec File declaration stimulus in std ulogic vector 33 downto 0 Temporary storage for inputs std ulogic vector 15 downto 0 Temporary storage for outputs string 34 downto 1 Temporary storage for big string integer 0 Keeps track of how many errors Text textio library Synchronizes with first clock loop Loops through the lines in the file Electronics Workbench Examp
167. I have been implemented The user C programs could be used for modeling a circuit or for creating test vectors Selected acc PLI routines have also been implemented Contact Simucad for the list of implemented PLI routines B 2 1 2 Standard Delay Format SILOS III supports the Standard Delay File SDF format SDF is a text file that contains the instance names and delay values necessary to back annotate delays into a Verilog HDL description SDF is usually generated by another tool such as a place and route tool The sdf annotate system task is used to specify the SDF file do not input the SDF file The format specification for the sdf annotate system task is sdf annotate file name module instance where file name represents any valid file path and file name specification Multisim User Guide B 2 3 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 4 module instance represents the name of the module instance The hierarchy of this instance is used for back annotation The names in the SDF file are relative paths to the module instance or full paths with respect to the entire Verilog HDL description For example if you use the module instance name top dff1 then the instance names in the SDF file are relative to top dff1 If you omit module instance SILOS IIl uses the module containing the call to the sdf annotate system task as the module instance for annotation For examples on using SDF s
168. Il Low to high clock transition The TC output is High when CET is High and the counter is at Terminal Count HLLH P 5 46 74xx161 Sync 4 bit Bin Counter This synchronous presettable binary counter features an internal carry look ahead for fast counting 4 bit bin counter truth table INPUTS OUTPUTS OPERATING MR CP CEP CET PE DN QN TC MODE 0 X X X X X 0 0 Reset clear HE X X T 1 0 0 1 x X 1 h 1 1 Parallel load J h h h X cou 1 Count nt X 1 X h X dn 1 Hold do X X 1 h X q o0 nothing 1 High voltage level h High voltage level one setup prior to the low to high clock transition 0 Low voltage level 1 Low voltage level one setup prior to the low to high clock transition An Lower case letters indicate the state of the refer enced output prior to the low to high clock transi tion X Don t care Low to high clock transition 1 The TC output is High when CET is High and the P 24 counter is at Terminal Count HHHH Electronics Workbench 74XX P 5 47 74xx162 Sync 4 bit Decade Counter This synchronous presettable decade counter features an internal carry look ahead for fast counting Decade counter truth table INPUTS OUTPUTS OPERATING SR CP CEP CET PE DN QN TC MODE X X X X 0 0 Reset clear h X X TH 0 0 h X x 1 h 1 2 Parallel load h h h h X cou 2 Count nt h X h X d amp n 2 Hold do h X d de XS da 9 nothing 1 High voltage level h High
169. LOS command line option e nospec The nospec command line option eliminates all specify blocks Eliminating the specify blocks will reduce the memory used and increase the simulation speed However eliminat ing the specify block delays may cause race conditions and non convergence due to zero delays If this happens the rise and fall delays for all gates whose delays are not explicitly specified can be set to 1 with the following SILOS III command e Idelay default 1 1 Multisim User Guide B 2 59 suoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions B 2 60 SILOS III also allows system commands to be entered from the command line i e system ls It mm For library searching SILOS III also supports the uselib compiler directive The format for uselib is uselib file filename dir directory name where e filename is the full path name for a file containing one or more module definitions that are searched to complete unresolved instantiations e directory name is the full path name for a directory of files whose names are a con catenation of the name of a module definition and a file extension such as dff v Some examples of uselib are The below example uses define to specify macros for the uselib This makes it easier to change the library paths define asicl dir c actel lib vlog libext v define asic2 file d library udp v uselib asicl asic2 The below example uses specifies the s
170. MKEEP and MEXCLUDE commands will keep and exclude all variables including registers and memory variables within a module or macro instance 2 The effects to the KEEP and EXCLUDE commands are cumulative When an identical net name is specified in more than one KEEP or EXCLUDE command the last KEEP or EXCLUDE command will determine if the simulation states for that net are saved 3 The KEEP EXCLUDE MKEEP and MEXCLUDE commands can be used with the CONTROL SAVSIM 1 command option to save simulation state values Examples CONTROL SAVSIM 1 EXCLUDE REG15 OBAR A15 exclude m1 bitO m1 bit1 m1 bit4 m1 bit5 m1 bit6 m1 bit7 driver iobuf pin34 B 2 2 10Exiting The Program The EXIT command is used for normal exit of SILOS III To exit the program enter EXIT EXIT commands the SILOS III program to stop execution and exit normally Example EXI FILE Multisim User Guide B 2 37 suoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions B 2 2 11File Name Specification B 2 38 The FILE command enables you to redefine the default file names used for the SAVE STORE and BATCHFILE commands The format for the FILE command is FILE SAV filename STO filename BAT filename MODE APPEND MODE OVERWRITE FILE redefines the file name defaults SAV changes the file name prefix save to a user specified name for all of the save files including the save dictionary file STO
171. Machine rotational inertia 0 01 N m s rad nn Rated rotational speed 1800 RPM Van Rated armature voltage 115 V lan Rated armature current 8 8 A V n Rated field voltage 115 V TI Load torque 0 0 N m K 3 Optocoupler An optocoupler is a device that uses light to couple a signal from its input u1 X a photoemitter to its output a photodetector A typical optocoupler can be found in a six pin dual in line package DIP 4N25 containing both an LED and a photodetector and a transistor Darlington pair or SCR The wavelength response of each device is structured to be as identical as possible to permit the highest measure of coupling possible K 4 Vacuum Tube v1B This component behaves as a three electrode tube consisting of an anode 1287 cathode and plate electrode It is often used as an amplifier in audio applica tions The vacuum tube is a voltage controlled current device very similar in oper ation to an N channel FET K 4 Electronics Workbench Vacuum Tube As for an FET the gain of the tube is referred to as transconductance and is defined as the change in plate current resulting from a change in grid to cathode voltage gm change in plate current change in grid to cathode voltage K 4 1 Characteristic Equations The DC characteristic of the triode vacuum tube is modeled by a two dimensional voltage controlled current 3 K u V V foru V V 20 0 for U V V lt 0
172. Multisim User Guide B 2 49 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions SIZES Generates memory usage information Application Notes 1 Items reported include the total number of devices network names etc 2 The memory usage may be different after read in preprocessing and simulation 3 The memory usage is also reported in the Help About box Examples NSTO SIZ TY SIZ B 2 2 24Spike Summary Output The t s SPIKES command allows you to view all the nodes on which spikes were made observable during logic simulation see B 2 2 22 Logic Simulation Specification To generate a node spike summary enter TYPE STORE SPIKES tl TO t2 WTYPE NSTORE TYPE optional Directs the spike summary STORE to standard output or to a disk file SPIKES Lists a summary table of all spikes between two time points t1 TO t2 Represent the minimum and maximum time point values over which the spike out put is to be generated This time point range must be within the logic simulation time point range If the time points are not specified the logic simulation times are used The TO keyword is optional B 2 50 Electronics Workbench Silos III Command Line Usage Application Notes 1 A spike occurs when the gate input level changes faster than the gate output can change 2 Setting the criteria for spike conditions is controlled by the pulse e pulse_r and path pulse command line arguments
173. NAND OC o coccccccccc eee P 60 74xx39 Quad 2 In NAND OC ococcccccccc nennen nn P 60 74xx390 Dual Div by 2 Div by 5 Counter a a sasaa aaea P 61 74xx393 Dual 4 bit Binary Counter nasasa saaana P 62 74xx395 4 bit Cascadable Shift Reg w 3 state Out P 63 74xx40 Dual 4 In NAND sssssseee I meh P 64 74xx42 4 BCD to 10 Decimal Dec 2 22 22 P 64 74xx43 Exc 3 to Decimal DeC ooocoocccccoo nn P 65 74xx44 Exc 3 Gray to Decimal Dec 2222er nenn P 66 74xx445 BCD to Decimal Dec seselse ee P 67 74xx45 BCD to Decimal Dec coococcococco lesse P 68 74xx46 BCD to seven segment dec liilslses lesen P 69 74xx465 Octal BUFFER w 3 state Out oooooocoooccooccoo o P 70 74xx466 Octal BUFFER w 3 state Out 0000 0002s P 71 74xx47 BCD to seven segment dec 22222 P 71 74xx48 BCD to seven segment dec 00 0 cece eee eee eee P 73 74xx51 AND OR INVERTER 2000 00 ee eee eee eee P 74 74xx54 4 wide AND OR INVERTER 200000 nennen P 74 74xx55 2 wide 4 In AND OR INVERTER lisse P 74 74xx69 Dual 4 bit Binary Counter liiis P 75 74xx72 AND gated JK MS SLV FF pre clr ooooooocoo o P 75 74xx73 Dual JK FF clr 2 0 0 mh P 75 74xx74 Dual D type FF pre cl llle P 76 74xx75 4 bit Bistable Latches 00 00000 eee eee eee P 76 74xx76 Dual JK FF pre
174. NT 1 0 COUNT 0 0 0 0 0 1 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 P 5 13474xx72 AND gated JK MS SLV FF pre clr This device is equipped with an active low pre and active low clr Therefore the flip flop begins accepting input from the JK input when the preset and clear are both high hence AND gated AND gated JK flip flop truth table PRE CLR c k g K Q Q Oo xx xl 0 1 0 XxXx Xx x o 1 o o x x x UNSTABLE 1 1 0 o oo Qo 1 1 1 of 1 0 1 1i o alo lt 2 1 1 X 1 Toggle triggers on pulse level sensitive P 5 13574xx73 Dual JK FF clr This device contains 2 independent JK flip flops Multisim User Guide P 75 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series JK flip flop truth table CLR CLK 3 ee ne E Qr E 1 0 0 Hold L T 0 dl 0 1 0 1 0 1 1 1 1 Toggle triggers on pulse level sensitive P 5 13674xx74 Dual D type FF pre clr This device is equipped with active low preset and active low clear inputs D type positive edge triggered flip flop truth table PRE CLR CLK D Q Q 0o tam St ND 1 0 X X 0 1 0 0 X X 1 1 1 1 1 1 0 1 1 Of Oe d 1 1 0 x Hold positive edge triggered P 5 13774xx75 4 bit Bistable Latches This device features complementary Q and Q outputs from a 4 bit latch Bistable latch truth table INPUTS OUTPUTS D c Q Q 0 1 0 1 1 1 1 0 X 0 oo Qo P 76 Electronics Workbench 74XX P 5 1
175. Ox Kin HHroolh Ho ok KK For olr or olx W x p oooocooooH o06o0 Cas EU 0 OI QE OO oO xoxo OO iO e I Ie O O O OHO G OO 0O 0O oOoon oooolooo oohojooocojooo oroojoooojooo E o Cx A OOO Ol Oo P 5 72 74xx240 Octal BUFFER w 3 state Out This device has high fan out improved fan in and 400 mV noise margin Multisim User Guide P 39 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series Octal BUFFER gate truth table G A Y 1 X Z 0 0 1 0 I 0 Z High impedance off P 5 73 74xx241 Octal BUFFER w 3 state Out This device has high fan out improved fan in and 400 mV noise margin Octal BUFFER gate truth table INPUTS OUTPUTS G al A2 a3 A4 Yl Y2 y Y4 al 0 Z High impedance off Al AQ as The level of the respective input P 5 74 74xx244 Octal BUFFER w 3 state Out This device has high fan out improved fan in and 400 mV noise margin Octal BUFFER gate truth table INPUTS OUTPUTS G al a2 a3 A4 Yl Y2 y Y4 1 X X X X Z Z Z Z 0 X X X X Al A2 A3 A4 Z High impedance off Alp ADS 2 The level of the respective input P 40 Electronics Workbench 74XX P 5 75 74xx246 BCD to seven segment dec The BCD to seven segment decoder driver features active low outputs designed for driving indicators directly It has full ripple blanking input output controls and a lamp test input BCD to seven segment decoder driver truth table
176. P 52 74xx33 Quad 2 In NOR OC oooccccccccoo eee P 53 74xx350 4 bit Shifter w 3 state Out 20 0 aaaea a P 53 74xx351 Dual Data Sel MUX w 3 state OUt ooooocoooo oo P 54 74xx352 Dual 4 to 1 Data Sel MUX 0 0000 eee P 54 74xx353 Dual 4 to 1 Data Sel MUX w 3 state Out P 55 74xx365 Hex Buffer Driver w 3 state 0 0 2 0 0c ce eee P 55 74xx366 Hex Inverter Buffer Driver w 3 state o o o o oo P 56 74xx367 Hex Buffer Driver w 3 state 2 2 22 000 c cee eee P 56 74xx368 Hex Inverter Buffer Driver w 3 state o oo oo oooo o P 57 74xx37 Quad 2 In NAND 00 0000 cee eee P 57 74xx373 Octal D type Transparent Latches lusus P 58 74xx374 Octal D type FF edge 0 00 ee eee P 58 Multisim User Guide seues Xxv suonounJj Functions 74XX series P 5 110 P 5 111 P 5 112 P 5 113 P 5 114 P 5 115 P 5 116 P 5 117 P 5 118 P 5 119 P 5 120 P 5 121 P 5 122 P 5 123 P 5 124 P 5 125 P 5 126 P 5 127 P 5 128 P 5 129 P 5 130 P 5 131 P 5 132 P 5 133 P 5 134 P 5 135 P 5 136 P 5 137 P 5 138 P 5 139 P 5 140 P 5 141 P 5 142 P 5 143 P 5 144 P 5 145 P 5 146 P 5 147 P 5 148 74xx375 4 bit Bistable Latches lille P 59 74xx377 Octal D type FF w en ooococccocccoo ee P 59 74xx378 Hex D type FF w en ooocccccocccco eee P 59 74xx379 Quad D type FF W en 0000 cee nen P 60 74xx38 Quad 2 In
177. PUT reports 3 When the same symbol is used to represent the different states as in the defaults of 0 1 for the input stimulus for a CLK or PATTERN specification the program resolves the ambiguity in the following order The most recent symbol specified by the most recently entered SYMBOL command is used For the default symbols not specified by a SYMBOL command the higher strength is used and within a strength the higher level is used Electronics Workbench Silos III Command Line Usage For example if SYMBOL D1 RO is entered then the symbol would mean Resistive Low If SYMBOL Di D is entered then the symbol would mean Driving Unknown 4 Note that the Unset state symbol cannot be changed it will always be a question mark Examples SYMBOL Z0 Z Z1 symbol r U z U d U rl H zi H di H d0 L r0 L z0 L SYM OD L D U 1D H S0 0 S X Sl 1 ISYM DO O D X Dl I S B 2 2 28Batch Execution Overview SILOS III can be run on the host computer as Aninteractive session for debugging a design A batch session for running regression tests Running SILOS III as a batch execution may be useful for Running regression tests This section explains how to run SILOS III as a batch execution in the Windows 95 Windows 98 operating system Windows NT operating system or the Unix operating system Examples are provided for common tasks such as using SILOS III commands from a file to input
178. S Ba e AIR RUE L 1 L 1 1 Characteristic Equation llis eh L 3 L 1 2 Multiplier Parameters and Defaults 0 0 0 eee ee L 3 Divider ous be I REX EQ ba ened Boo E amen eel ton E ab ape eee ten bane ane eee L 3 L 2 1 Characteristic Equation 0 000 eee L 5 L 2 2 Divider Parameters and Defaults liliis L 5 Transfer Function Block 0 cee tee eee L 6 L 3 1 Characteristic Equation 0 0000 eee L 6 L 3 2 Transfer Function Block Parameters and DefaultS L 7 Voltage Gain Block t a tairi Eo aiiai a a a a rh L 7 L 4 1 Characteristic Equation sasaaa aaaea L 8 L 4 2 Voltage Gain Block Parameters and Defaults oo ooooooocooo L 8 Voltage Differentiator asrga He ar KAE a Ree ad L 9 L 5 1 Investigations o oiee ea ae o i aa a a RII III L 9 5311 Sine Wave ocu a ua ea Wit oder dee eR L 9 L 5 1 2 Triangle waveforms sllsseeleeee ens L 9 L 5 1 3 Square waves ers L 9 L 5 2 Characteristic Equation liliis L 10 L 5 3 Voltage Differentiator Parameters and Defaults L 11 Voltage Integrator oooooooccoooo nn L 11 L 6 1 Investigations o ooooooooorooo I Iren L 11 L 6 2 Characteristic Equation liliis eren L 12 L 6 3 Voltage Integrator Parameters and Defaults ooo oooooo L 13 Voltage Hysteresis Block 0 oooocoooccooooco nennen L 13 L 7 1 Hysteresis Block Parameters and Default
179. S175 D FLIP FLOP 74LS181 ALU 74LS183 CARRY SAVE ADDER 74LS190 UP DOWN COUNTER 74LS191 UP DOWN COUNTER 74LS192 UP DOWN COUNTER 74LS193 UP DOWN COUNTER 74LS194A 4 BIT SHIFT REGISTER 74LS195 4 BIT SHIFT REGISTER 74LS196 BINARY COUNTER 74LS197 BINARY COUNTER 74LS221 MONOSTABLE MULTIVIBRATOR 74LS240 TRI STATE BUFFERS 74LS241 TRI STATE BUFFERS 74LS242 TRANSCEIVER 74LS243 TRANSCEIVER Electronics Workbench Verilog Libraries Multisim User Guide Name Description 74LS244 TRI STATE BUFFERS 74LS245 TRANSCEIVER 74LS251 3 STATE MUX 74LS253 3 STATE MUX 74LS257B MUX 74LS258B MUX 74LS259B LATCH 74LS261 MULTIPLIER 74LS266 XNOR OC 74LS273 D FLIP FLOPS 74LS279 SR LATCH 74LS279A SR LATCH 74LS280 PARITY GENERATOR CHECKER 74LS283 4 BIT ADDER 74LS290 DECADE COUNTER 74LS292 PROGRAMMABLE COUNTER 74LS293 BINARY COUNTER 74LS294 PROGRAMMABLE COUNTER 74LS295B SHIFT REG 74LS298 MUX WITH STORAGE 74LS299 8 BIT SHIFT REGISTER 74LS322A 8 BIT SHIFT REG 74LS323 8 BIT SHIFT REG 74LS348 PRIORITY ENCODER 74LS352 MUX 74LS353 MUX B 2 69 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 70 Name Description 74LS354 MUX 74LS355 MUX 74LS356 MUX 74LS365A BUS DRIVER 74LS366A BUS DRIVER 74LS367A BUS DRIVER 74LS368A BUS DRIVER 7
180. SS Surface state density 0 1 cm TPG Type of gate material 1 LD Lateral diffusion 0 m UO Surface mobility 600 cm Vs KF Flicker noise coefficient 0 AF Flicker noise exponent 1 FC Coefficient for forward bias depletion capaci 0 5 tance formula TNOM Parameter measurement temperature 27 C Tp rs 10 to 15 of the on state drain source resistance Rps on F6 JFETs Junction FETs The JFET is a unipolar voltage controlled transistor that uses an induced di electrical field to control current The current through the transistor is con 2n3370 trolled by the gate voltage The more negative the voltage the smaller the cur rent A JFET consists of a length of an n type or p type doped semiconductor mate rial called a channel The ends of the channel are called the source and the drain The terminal with the arrowhead represents the gate In an n channel JFET the gate consists of p type material surrounding the n channel In a p channel JFET the gate consists of n type material surrounding the p channel Multisim User Guide F 15 SJO SISUBJ Transistors Transistors Components F 6 1 F 16 DC Model The DC model characteristic is determined by a nonlinear current source Ip Forward characteristics Vps 2 0 0 for Vos V 0 Ip 7 B Vas Vio AV 5 tor O lt Ves Vro E Vos BOU DV V45 Vos 11 AV ps for0 V5 Vos Vro Reverse characteristics Vps lt 0
181. Schottky Diode oooococccocccoo hr E 12 Silicon Controlled Rectifier llle E 12 E 7 1 Model Berni a ee E ee sed Lee Du a E 13 E 7 2 Time Domain Model oocccococccoooo esses E 13 E 7 3 AC Small Signal Model oooccccccccocc eese E 14 E 7 4 SCR Parameters and DefaultS o ooooocoooococcn nor E 14 DAG area bea Brand en ed o ata daa it ds Be Sea E 14 E 8 111 DE Mode liv 2 5 2 rn aan NE I E ANN oy E 15 E 8 2 Time Domain and AC Small Signal ModelS ooocooccoocoo E 15 E 8 3 DIAC Parameters and Defaults o ooooocoooonocnnoncr o E 16 Multisim User Guide sepoiq Diodes E 9 TRAGA A S E geholt iuh e ET E 9 1 MOGel arica pa Dia ez renim DIO ETE olt bene Go BOT deside Be n ds E 16 E 10 Varactor Diode Electronics Workbench Appendix E Diodes Components E 1 E 1 1 Diode Diodes allow current to flow in only one direction and can therefore be used as simple solid state switches in AC circuits being either open not conduct ing or closed conducting Terminal A is called the anode and terminal K is 1N1199C called the cathode D1 Diodes Background Information Diodes exhibit a number of useful characteristics such as predictable capacitance that can be voltage controlled and a region of very stable voltage They can therefore be used as switch ing devices voltage controlled capacitors varactors and voltage references Zener diodes Because diodes
182. State transitions STTRANS process current state Mode VS ENDFR begin case current state is when StateLive Display live video on the RAMWE 1 RAMOE lt 1 ADOE lt 0 INCAD lt 0 Multisim User Guide which output A 29 dwd TAHA VDHL Prrimer VHDL Primer A 30 if Mode 1 then next state StateWait end if when StateWait Wait for vertical sync RAMWE 1 RAMOE lt 1 ADOE lt 0 INCAD lt 0 if VS 1 then next_state lt StateSample end if when StateSample gt Sample one frame of video RAMWE lt 0 RAMOE lt 1 ADOE lt 0 INCAD lt 1 if ENDFR 1 then next_state lt StateDisplay end if when StateDisplay gt Display the stored frame RAMWE lt 1 RAMOE lt 0 ADOE lt 1 INCAD lt 1 if Mode 1 then next state lt StateLive end if end case end process End CONTROL A A 4 2 2 Test Bench The following test bench uses loops to simplify the description of a long test sequence library ieee Use ieee std logic 1164 all Use std textio all library work use work control Entity T CONTROL Is Electronics Workbench Examples Gallery End T CONTROL Archite cture stimulus of T CONTROL Is Component CONTROL Por t Reset in std ulogic Clk in std ulogic Mode in std ulogic Data in std ulogic vector 7 downto 0 TestLoad in std ulogioc
183. TIVITY t1 TO t2 keywrd val keywrd optionally directs the activity report to standard output or to a disk file generates a node activity report represent the minimum and maximum time point values for reporting node activity This time point range must be within the logic simulation time point range If the time points are not specified the logic simulation times are used The TO keyword is optional represents an optional keyword used to define a condition or specify a value The first keyword must be preceded by a slash reports the activity only for nodes that are included within fault blocking specifies the lower limit for reporting node activity Only nodes which have known level transitions greater than or equal to this minimum limit will be reported Default MNTRAN 0 specifies the upper limit for reporting node activity Only nodes which have known level transitions less than or equal to this maximum limit will be printed Default MXT RAN 0 represents the user specified numerical value for MNT RAN or MXTRAN suppresses output of the activity versus time histogram suppresses output of the activity summary suppresses output of the node activity table B 2 27 suoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions Application Notes 1 An ACTIVITY report can be very useful for developing input test patterns to detect circuit faults for fault simulation The number of level transitio
184. Timing checks without edge specifications for selected variables example recovery CLR SILOS III command to allow this extension Icontrol ext neref For more information see section B 9 6 of the Verilog HDL Reference on line help file B 2 1 7 22More precision in timeformat than times cale SILOS III command to allow this extension control ext tfmt For more information see section B 5 2 of the Verilog HDL Reference on line help file B 2 1 7 23Missing port connections are set to ground for VCS compatibility HyperFault command to allow this extension control skip gnd Note Wires which are otherwise floating still remain HiZ regardless of control skip B 2 1 7 24VCS compatibility extension for comma at the end of the port list i e module xx a HyperFault command to allow this extension control ext portcomma Multisim User Guide B 2 25 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 2 Silos Ill Command Line Usage B 2 2 1 Commands Overview The Commands section contains a short overview on command syntax inputting commands from the in the Command window for the Main toolbar and inputting commands from a data file B 2 2 1 1Command Syntax Usually only the first two characters are required when specifying a command A few com mands e g FAN PRE PRO require three letters to prevent ambiguity B 2 2 1 2Inputting SILOS Commands Most commands are a part of
185. Voltage Controlled Voltage Source P KEYING FSK output 200 Hz 5096 Dscilloscope Time base 1 00ms div X position 0 00 v male aur A B E Channel amp Channel B 5vipu E Yposition 1 83 Ej Yposition 0 00 gel mlo s Belal oc This component is a square wave generator You can adjust its voltage amplitude duty cycle and frequency C 12 Voltage Controlled Voltage Source The output voltage of this source depends on the voltage applied to its input terminal The ratio of the output voltage to the input voltage determines its id voltage gain E Voltage gain can have any value from mV V to kV V E VouT VIN C 13 Current Controlled Voltage Source The output voltage of this source depends on the current through the input ter minals The two are related by a parameter called transresistance H which is the ratio of the output voltage to the input current It can have any value from 10hm mW to kW Multisim User Guide C 7 seounos Sources Sources Components C 14 C 15 C 16 C 16 1 C 8 H _ Vout lin Voltage Controlled Current Source The output current of this source depends on the voltage applied at the input terminals The two are related by a parameter called transconductance G which is the ratio of the output current to the input voltage It is measured in mhos also known as seimens and can have any value fro
186. a EVEN ODD 0 2 4 6 8 1 0 1 3 5 7 9 0 1 2 sigma P 5 92 74xx283 4 bit Bin Full Add This device performs the addition of two 4 bit binary numbers It features full internal look ahead across all four bits generating the carry term in ten nanoseconds typically P 50 Electronics Workbench 74XX P 5 93 74xx290 Decade Counter This device contains four master slave flip flops and additional gating to provide a divide by two counter and a three stage binary counter for which the count cycle length is divide by five Decade counter truth table COUNT QD QC QB QA RO 1 RO 2 R9 1 R9 22 QD QC QB QA 0 0 0 0 0 T 1 0 X 0 0 0 0 1 0 0 0 1 1 1 X 0 0 0 0 0 2 0 0 1 0 X X 1 T r 0 o 1 3 0 0 1 1 X 0 X 0 COUNT 4 0 1 0 0 0 X 0 X COUNT 5 0 1 0 elt 0 X X 0 COUNT 6 0 1 1 0 X 0 0 X COUNT 7 0 1 1 1 8 1 0 0 0 9 T 0 0 1 P 5 94 74xx293 4 bit Binary Counter This device contains four master slave flip flops and additional gating to provide a divide by two counter and a three stage binary counter for which the count cycle length is divide by eight Counter truth table RESET IN OUTPUT Rol Ro2 Qd Qc Qb Qa 1 al 0 0 0 0 0 X COUNT X 0 COUNT P 5 95 74xx298 Quad 2 In MUX This quadruple two input multiplexer selects one of two 4 bit data sources and stores data synchronously with system clock Multisim User Guide P 51 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series
187. abs not carriage returns can be used to delineate the values between different variables however white space is not allowed between the values for a vector variable An example for specifying the radix is shown below table 1 2 b inl in2 out strobe 00000000 00 ff 00001110 Oa 6 11111111 ff 00 For single bit wires SILOS state symbols may be used to enter states other than 1 0 x z See B 2 2 27 Symbol Modification For Output B 2 1 3 4Delay Time The delay time for a constant increment of time delta time between application of subse quent table lines can be specified as a single expression table delta Multisim User Guide B 2 7 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 8 When the delta delay is specified on the table header then the first table line is applied imme diately upon execution of the stimulustable statement The delay time can also be specified on each table line When no sign is specified on the table header then the delay values are added to the simulation time as the stimulustable is read The delay is applied prior to the application of the table line The time units for the delay value can be specified by preceding the module containing the stimulustable statement with a timescale statement Below is an example timescale Ins Ins 10 time 10 table inl in2 out strobe 1 2 00 00 ff time 11 2 1 6 0e Oa 6 time 12 8 2 1 ff ff 00 time
188. ace conditions This command displays every signal that has more than one iteration at a timepoint from time 0 to the current time point To view a graphical display for iterations at a timepoint see Reports Iteration B 3 6 5 Reports Nonconvergence B 3 16 Generates a report of any nonconverged nodes and their oscillating states for the time point that nonconvergence occurred Reports Nonconvergence can only be used to debug noncon vergence in gate level designs For behavioral level designs this command will produce a report that states there is no data to report To debug nonconvergence for behavioral designs see Nonconvergence Hanging for Behavioral Designs B 3 6 5 1Nonconvergence For Gate Designs Reports the following information Names of the unresolved devices and nodes The type of device and node as either a type data keyword NODE for a wired con nection with at least one bi directional device or BUS for a wired connection between two or more unidirectional enabled gates The node state values for the nonconvergence time point State values reported are pre e 00 ceded by a to indicate possible previous states Nonconvergence only occurs when gate delays are zero Zero delays can cause the circuit to oscillate at a single timepoint As the circuit oscillates the simulator must iterate over the cir cuit trying to resolve the circuit to a single set of values When the itera
189. ade count up decade count down binary count up binary the more positive voltage the less positive voltage positive going clock pulse edge 0 2 37 4030 Quad 2 In XOR This device contains four independent 2 input EXCLUSIVE OR gates 1 o Multisim User Guide Logic function O 1 01 O 21 seues 000p suonounJ Functions 4000 series Functions 4000 Series EXCLUSIVE OR gate truth table FOr o op ro 0 0 1 1 O 2 38 4032 Triple Serial Adder The 4032 triple serial adder has the clock and carry reset inputs Are sl common to all three adders The carry is added on the positive 11 t 7781 going clock transition for this device 43 NVERT 1 12 Se 5 B2 4g INVERT 2 A da S 31 B3 3 INVERT_3 0 2 39 4035 4 bit Shift Register The 4035 device is a fully synchronous edge triggered 4 bit shift register 5 colt With a clock input CP four synchronous parallel data inputs PO to P3 10 15 Y ale tt two synchronous serial data inputs J K a synchronous parallel enable LN 2 e 5 input PE buffered parallel outputs from all 4 bit positions O0 to O3 a y true complement input T C and an overriding asynchronous master reset Tq input MR 5 PE cm Following are two shift register truth tables 5 cP MR O 22 Electronics Workbench 4000 Series ICs Serial operation first stage CP X
190. al 4 bit latches clr P 9 Dual 4 bit Static Shift Reg O 8 Dual 4 In AND 4082 O 33 74xx21 P 38 Dual 4 In NAND 4012 O 6 74xx20 P 38 74xx40 P 64 Dual 4 In NAND OC P 38 Dual 4 In NOR O 4 Dual 4 In NOR w Strobe P 45 Dual 4 In OR O 29 Electronics Workbench Dual 4 input Multiplexer O 50 Dual 4 to 1 Data Sel MUX 74xx153 P 19 74xx352 P 54 Dual 4 to 1 Data Sel MUX w 3 state Out 74xx253 P 46 74xx353 P 55 Dual BCD Counter O 46 Dual Binary Counter O 47 Dual Com Pair Inv O 4 Dual Data Sel MUX w 3 state Out P 54 Dual Div by 2 Div by 5 Counter P 61 Dual D type FF edge O 7 pre clr P 76 Dual JK FF edge pre clr 4027 O 19 edge pre clr 74xx109 P 7 clr 74xx107 P 7 clr 74xx73 P 75 edge pre clr P 8 edge pre com clk amp clr P 9 pre clr P 77 pre com clk amp clr P 77 Dual JK MS SLV FF edge pre P 8 E enhancement MOSFET F 11 equations bipolar junction transistors F 2 capacitors D 5 differentiator L 10 divider L 5 full wave bridge rectifier E 10 GaAsFET F 19 inductors D 8 integrator L 12 limiter L 16 linear transformer D 11 Multisim User Guide multiplier L 3 relay D 14 resistors D 4 three way summer L 23 transfer function block L 6 triode vacuum tube K 5 voltage gain block L 8 Exc 3 Gray to Decimal Dec P 66 Exc 3 to Decimal Dec P 65 exp current source C 22 exp voltage source C 21 F FM source See frequency modulated source frequency modulated source C 5 frequency sh
191. al BUFFER w 3 state Out 0000 0c e eee P 40 74xx244 Octal BUFFER w 3 state Out 2 000 0c P 40 74xx246 BCD to seven segment dec 0 0c eee eee eee P 41 74xx247 BCD to seven segment dec 2 222220 P 42 74xx248 BCD to seven segment dec 020 0c eee eee eee P 43 74xx249 BCD to seven segment dec 22222 nennen P 44 74xx25 Dual 4 In NOR w Strobe 00000 c eee eee eee P 45 74xx251 Data Sel MUX w 3 state Out aaua anaana P 45 74xx253 Dual 4 to 1 Data Sel MUX w 3 state Out P 46 74xx257 Quad 2 to 1 line Data Sel MUX 00000 2 eee eee P 46 74xx258 Quad 2 to 1 line Data Sel MUX 20 00000 eee P 47 74xx259 8 bit Latch 0 20 0 cee P 47 74xx26 Quad 2 In NAND OC ooocccoccccc eee P 47 74xx266 Quad 2 In XNOR OC 222222 sense rennen nn P 48 74xx27 Tri 3 IN NOR 0 6 eae P 48 74xx273 Octal D type FF ananasa 000 cee eee P 49 74xx279 Quad SR latches 0 0 00 0 cee P 49 74xx28 Quad 2 In NOR 2 2 00 eee P 50 74xx280 9 bit odd even parity generator checker P 50 74xx283 4 bit Bin Full Add 0 2 20 0 0 00 cee eee P 50 74xx290 Decade Counter 2 222 case een P 51 74xx293 4 bit Binary Counter o oococcocccooc eee P 51 74xx298 Quad 2 IN MUX o oooccccccccoc eee P 51 74xx30 8 In NAND 22 ccc eR re P 52 74xx32 Quad 2 In OR 0occocccccccoc ses
192. always will run concurrently initial begin stop at Will stop the execution after 20 simulation units 20 stop end These statements done at simulation time 0 since no Hk initial begin Init Initialize register A Other registers have values of x Multisim User Guide B 1 3 Jewud Boje Verilog Primer Verilog HDL Primer B 1 4 A 0 Display a header Sdisplay Time A B CH ys Prints the values anytime a value of A B or C changes monitor 0d b b b time A B C end main process will loop until simulation is over always begin main process 1 means do after one unit of simulation time 1 A A 1 1 B 0 3 A 4 7 is bitwise not operator 1 C amp A 6 7 bitwise and reduction of last 2 bits of A end endmodule In module simple we declared A and B as 8 bit registers and C a 1 bit register or flip flop Inside of the module the one always and two initial constructs describe three threads of control i e they run at the same time or concurrently Within the initial con struct statements are executed sequentially much like in C or other traditional imperative pro gramming languages The always construct is the same as the initial construct except that it loops forever as long as the simulation runs The notation 1 means to execute the statement after delay of one unit of simulated time Therefore the thread of control caused by the firs
193. ame uselib without using a define Notice that the libext keyword for the library file name extensions is required when specifying a directory dir specification for a directory of library files uselib file test lib udp v dir test lib2 libext v B 2 2 28 3Windows Batch Execution SILOS III can be run as a batch execution from the Windows 95 Windows 98 and Windows NT operating systems The command line syntax for running SILOS III as a batch execution on the Windows 95 Windows 98 and Windows NT operating system is silos exe options plusargs filename filename command command where silos exe is the path to the silos exe executable on Windows options is one or more Verilog HDL style command line options An example of using command line options would be Silos exe v examl udp v examl lib y library libext v examl v examl tst For the above example SILOS III will scan library files exam1 udp and exam1 lib and the v files in directory library and then input files exam1 v and examl tst Then SILOS III Electronics Workbench Silos III Command Line Usage will automatically simulate the circuit report any errors and exit when there are no fur ther commands to be executed from the command line or from a file the sim error and exit commands do not have to be specified The above examples could also have used the f command line option to specify the file that has th
194. an J 2 J 2 3 Connecting an AmMmMmeter o ooccccccoc ees J 2 Probe LED wi 242 Hr FUE penso e dac ee ii J 3 Lamp ss cM J 3 J 4 1 Time Domain and AC Frequency Models 0000 eee else J 3 Hex Display sa cme ass e bh tes ewe Ltd vage qo eae ied J 4 J 5 1 Seven Segment Display oooccooccocco eee J 4 J 5 2 Decoded Seven Segment Display o ooooocccccocco nenn J 5 Bargraphs ace is or ev bete ue ebria ds il qa EQUES J 6 J 6 1 The Component arroa 2222 jg d xA Aere Lenk teste J 6 J 6 1 1 Bargraph Display Parameters and Defaults J 6 J 6 2 Decoded Bargraph Display liliis J 6 J 6 2 1 Decoded Bargraph Display Parameters and Defaults J 7 PUZZ tantas EA UP aae uei viae uet ice gi DUAE J 7 Multisim User Guide s O e91pu Electronics Workbench Appendix J Indicators Components J 1 J 1 1 J 1 2 Voltmeter The voltmeter offers advantages over the multimeter for measuring volt v gi age in a circuit The advantage of using the voltmeter is that you can use an unlimited number of voltmeters in a circuit and you can rotate their termi nals to suit your layout The side with the heavier border is the negative terminal Resistance 1 0 999 99 TQ The voltmeter is preset to a very high resistance 1 MQQ which generally has no effect on a circuit If you are testing a circuit that itself has very high resistance you may want to increase the voltmeter
195. analog_in top 0 000 feedback top 0 000 counter_value top 0 4 gt 4 For Help press F1 T1 T2 Tdelta Time 180 000us E Double click to toggle Stepping function display on Piece wise linear display of ana between stepping analog signal log signal function and piece wise linear Analog signals for real variables are displayed as piece wise linear or step waveforms Dou ble clicking on the signal name will toggle between the two methods of displaying analog sig nals for real variables If you want to change the default setting for displaying analog signals add the following line in the Analyzer section for the sse ini file in the Windows directory AnalogWaveMode Step or AnalogWaveMode Pwl Integer variables can be displayed as a vector type of waveform or as an analog waveform Choose Options Analog Integer Display to set the method of displaying integers Displaying integer variables as analog waveforms can be very useful for designing digital filters etc B 3 10 6 2Notes on using the Data Analyzer Window Viewing More Waveforms To create more space to display waveforms Multisim User Guide B 3 29 snuelA 111 SOS Silos III Menus Silos III Menus Decrease the size of the Name Scope or Value buttons by grabbing and moving the ver tical edge for the buttons Increase the size of the Waveform Display by grabbing the vertical line that separates the Name list from the Waveform Display a
196. anging from 3 to 15 V The 74HC HCT and 74AC ACT series operate over a range of supply voltages between 2 and 6 V Logic Voltage Levels The input and ouput voltage levels are different for each CMOS series The Vo for the CMOS devices is close to O V and the Voy is close to 5 V The required input voltage levels are greater for CMOS than for TTL except for the 74 ACT series These series are designed to be electrically comparable with TTL so they must accept the same input voltage levels as TTL Noise Margins The CMOS devices have greater noise margins than TTL Power Dissipation The power dissipation of a CMOS logic circuit is very low when the circuit is in a static state The pwoer dissipation of a CMOS IC increases in proportion to the frequency at which the circuits are switching states 0 2 4000 Series ICs O 2 The 4000 component in the parts bin is a generic IC or template It has no pins or labels and cannot be wired into a circuit To use an IC drag the template onto the circuit window A list of available ICs for this family appears Select the IC you want to include in your circuit The correct graphic will appear containing labels and pins Electronics Workbench 4000 Series ICs O 2 1 4000 Dual 3 In NOR and INVERTER 3 a 6 Logic function 5 O1 Ij I5 4I4 On I 15 165 1 NOR gate truth table H H H N H w o B HohrohroHho Hpoonnoso FrrHroooo C gt oo o oo H 0 2 2
197. anking input RBI must be open or high if blanking of a decimal zero is not desired 2 When a low logic level is applied to the blanking input BI all segment outputs are low regardless of any other input level 3 To place the device in lamp test mode RBO must be high when LT is low This forces all lamps on Electronics Workbench 74XX P 5 12974xx48 BCD to seven segment dec This device features active high outputs for driving lamp buffers or common cathode VLEDs It also has full ripple blanking input output controls and a lamp test input BCD to seven segment decoder INPUTS OUTPUTS No LT RBI D c B A Bre a b c d e E g RBO 0 1 1 0 0 0 0 1 1 1 1 I 1 1 0 1 1 X 0 0 0 1 dl 0 1 1 0 0 0 0 2 1 X 0 0 1 0 d Al 1 0 il 1 0 1 3 1 X 0 0 1 1 1 1 1 1 1 0 0 1 4 1 X 0 1 0 0 1 0 1 1 0 0 1 1 5 1 X 0 1 0 1 1 1 0 1 1 0 1 1 6 1 X 0 1 1 0 ji 0 0 1 1 1 1 0 7 1 X 0 1 1 1 1 1 1 1 0 0 0 0 8 1 X 1 0 0 0 1 1 1 1 1 1 1 1 9 1 X al 0 0 1 1 1 1 1 0 0 1 1 10 1 X 1 0 1 0 1 0 0 0 1 1 0 1 INV 11 1 X 1 0 1 1 1 0 0 1 1 0 0 1 lt ALI 12 1 X 1 1 0 0 1 0 1 0 0 0 1 1 lt D 13 1 X 1 1 0 1 i 1 0 0 1 0 1 1 lt 14 1 X 1 1 1 0 1 0 0 0 1 1 1 1 15 1 X 1 1 1 1 1 0 0 0 0 0 0 0 BI X X x X X X 0 0 0 0 0 0 0 0 RBI 1 0 0 0 0 0 0 0 0 0 0 0 0 0 LT 6 X x X X X 1 1 1 1 1 1 1 BI active low blanking input RBI active low ripple blanking input LT active low lamp test input Notes 1 The
198. ant clue in solving a nonconvergence is to know which signal started oscillat ing first The probe command can be used to find out which signal started oscillating see Probing Node States Use following steps to debug your circuit 1 Inthe Command window for the Main toolbar enter the disk command to name an out put file such as disk filel 2 In the Command window for the Main toolbar enter the nstore nonconv command to store the nonconvergence report in filel 3 Next edit filel and copy and paste the net names from the nonconvergence report to another file file2 that you have the probe command in for example probe iter timel time end netl1l net2 net3 where timel is the timepoint before the non convergence and time end is the nonconver gence timepoint If the net names use the SILOS style to delimit hierarchy then you ee will have to change the to 4 In the Command window for the Main toolbar prompt input the file that has the probe command input file2 From the probe report determine which net is oscillating first 5 Open the Data Analyzer and the Explorer window In the Explorer window select the sig nal that was first oscillated and drag and drop it to the Data Analyzer Then highlight the signal in the Data Analyzer and use Trace Signal Inputs to trace backwards from the net that started oscillating so that you can draw the circuit for that net and figure out the cau
199. aracter strings librescan Search all the library files again for undefined modules libverbose This option prints information about the opening of files and the resolu tion of module and UDP definitions during the scanning of libraries define text macro name macro text This option allows you to specify define macros from the command line The text macro name is the macro identifier and the macro text is the text substitution Double quotes must be used around the macro text if the macro text contains whitespace For example silos exe define sdf test sdf is equivalent to define sdf test sdf and silos exe define declare reg a is equivalent to define declare reg a delay_mode_distributed Command line argument specifies the distributed delay mode for all modules in the source description This means that the distributed delays for gates connecting the module input to the module output will always be used as the pin to pin delay for the module input to output For examples of distributed delays see Chapter 13 on specify blocks in the Verilog LRM on line help file delay mode path Command line argument specifies the path delay mode for all modules in the source description This means that the path delays specified in the specify Multisim User Guide B 2 57 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 58 blocks for delays from the module input to the module output will always be
200. architectures are to be bound to which entities and allows you to change how com ponents are connected in your design description at the time of simulation or synthesis Configuration declarations are always optional no matter how complex a design descrip tion you create In the absence of a configuration declaration the VHDL standard speci fies a set of rules that provide you with a default configuration For example in the case where you have provided more than one architecture for an entity the last architecture compiled will take precedence and will be bound to the entity Levels of Abstraction VHDL supports many possible styles of design description These styles differ primarily in how closely they relate to the underlying hardware The different styles of VHDL refer to the differing levels of abstraction possible using the language behavior dataflow and structure as shown in the following diagram This figure maps the various points in a top down design process to the three general levels of abstraction Starting at the top suppose the performance specifications for a given project are the compressed data coming out of the DSP chip needs to be analyzed and stored within 70 nanoseconds of the Strobe signal being asserted This human language specification must be refined into a description that can actually be simulated A test bench written in combina tion with a sequential description is one such expression of the desi
201. arge signal transient responses of a variety of switched mode power supplies operating in both the continuous and discontinu ous inductor current condition modes DCM and CCM respectively K 12 Electronics Workbench Buck Boost Converter K 10 1 Characteristic Equations D D I I I er D D Gut La D D D D 2 Uat yop ths D D in which is governed by 1 pr L 7 7 J D V D V at where D duty ratio of the switching devices For the DCM Den V V 20 D V D D Ij a Se 2 L F S For the critical condition between the CCM and the DCM of operation D 1 D D V I I een LD Lerit 2x Lx F For the CCM D 1 D V D V DsV Ii cd yc Multisim User Guide OSIN K 13 Misc Misc Components The averaging behavior governed by these equations is modeled using Electronics Work bench s built in analog behavioral modeling components The AC small signal model is auto matically computed K 10 2 Buck Boost Converter Parameters and Defaults Symbol Parameter Name Default Unit L Filter inductance 500 uH R Filter inductor ESR 5 mW Fs Switching frequency 50 kHz K 11 Fuse ut This is a resistive component that protects against power surges and current X X jo overloads OS5_AMP A fuse will blow open if the current in the circuit goes above Lpa the maxi mum current rating 7 can have any value from mA to kA The fuse
202. arguments x and y Function Name Description sin x sine cos x cosine tan tangent asin x inverse sine acos x inverse cosine atan x inverse tangent sinh x hyperbolic sine cosh x hyperbolic cosine Multisim User Guide B 2 17 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions Function Name Description tanh x hyperbolic tangent sqrt x square root exp x exponentia log10 x common logarithm log x natural logarithm pow x y power xy B 2 1 4 3Examples for Transcendental Math Functions The transcendental functions are used in the same way as any other Verilog function The module below illustrates a simple use of displaying values for the math functions module math03 initial begin real pi pi 3 14159 display sin 0 0 0 display sin 0 5 pi 0 01 0 01 display end endmodule sin 0 cos 0 00234 0 999997 0 0 99995 sin 0 5 pi cos 0 00234 The next example shows how to generate a sine wave using the sin function title example for generating a sine wave The example below generates a sine wave x module sine_wave real x y initial begin x 0 1000 Sfinish end always begin 1 x x 0 1 B 2 18 y based on the value of Electronics Workbench Verilog HDL Extensions y sin x Built in SILOS III sin function end endmodule B 2 1 5 silos and sse k
203. as the opamps are provided with several levels of simu lation models of increasing complexity and accuracy Electronics Workbench Comparator The following model levels are used to distinguish between these models e LI this is the simplest model with the opamp modeled as a gain block with a differential input and a single ended output e L 2 thisis a more complex model in which the supply voltages are included in the simu lation e 3 this is a model of increasing complexity where additional control pins are supported e 4 this is the most complex and accurate model with a majority of the external control pins modeled G 3 Comparator HA17339 S G 3 1 The Component This component models the high level behavior of a comparator A comparator is an IC oper ational amplifier whose halves are well balanced and without hysteresis and is therefore suit able for circuits in which two electrical quantities are compared The comparator component models conversion speed quantization error offset error and output current limitation A comparator is a circuit that compares two input voltages and produces an output in either of two states indicating the greater than or less than relationship of the inputs A comparator switches to one state when the input reaches the upper trigger point It switches back to the other state when the input falls below the lower trigger point A voltage comparator may be implemented with any op amp
204. at you selected from the Explorer window will then appear in the Scope box Next click Add to add the name of the module instance to the list of breakpoints The Break in Module Any Instance selection allows you to select a module instance and then stop logic simulation each time a source line in any instance of the module is to be simu lated To select a breakpoint location use the Explorer window to highlight the module instance you want to select In the Breakpoints screen select Break in Module Any Instance for the Type box The name of the module instance that you selected from the Explorer window will then appear in the Scope box Next click Add to add the name of the module instance to the list of breakpoints Multisim User Guide B 3 23 snus 111 SOS Silos II Menus Silos III Menus The Add button adds the specified breakpoint to the Breakpoints list Active breakpoints are preceded by a plus sign Inactive breakpoints Disable button are preceded by a minus sign Individual breakpoints can be deleted with Delete All breakpoints can be deleted by the Clear All button The OK button closes the Breakpoints screen and saves the changes The Cancel button closes the Breakpoints screen without saving the changes B 3 9 Options Menu The Options menu provides the following commands e Options Fonts e Options Tabs e Options Snap to Edges e Options Title Tips Options Analog Integer Display
205. ation V out N i where Vout Output voltage value magne tomotive force input current D 15 2 Coreless Coil Parameters and Defaults Symbol Parameter Name Default Unit N Number of inductor turns 1 D 21 Multisim User Guide oiseg Basic Basic Components D 22 Electronics Workbench Appendix E Diodes Components E 1 E 2 E 3 E 4 E 5 E 6 E 7 E 8 Bx eem E 1 E 1 1 Diodes Background Information 0 000 eee ee E 1 E 1 2 DEIM del He ette trente eom rte Root tere RR RR te e E E 2 E 1 3 Time Domain Model 0000 cee ees E 3 E 1 4 AC Small Signal Model 0 000 cece E 4 E 1 5 Diode Parameters and Defaults liliis E 5 PIN Diode cue ce a AA dae a eee a AA eee ee Sts E 6 E 2 1 Photo Diode Application llis E 6 zener Diode sis ux cuu ieu Base e Prae T hende i euh nii E 6 ES TDC Model er tica e era Cato dos od E ee x es E 7 E 3 2 Zener Diode Parameters and DefaultS ooocooooooooocco E 8 LED Light Emitting Di0de ooooccoccconccno eh E 8 E 4 1 Background Informati0N ooooccooooccoor ee E 9 E 4 2 LED Parameters and Defaults 222 0 000 E 9 Full Wave Bridge Rectifier unanunua cee eee E 10 E 5 1 Characteristic Equation liliis eee E 10 E 5 2 Model as n esicta tu e E apr RELIER RC ue AE ERR M E 10 E 5 3 Full Wave Bridge Rectifier Parameters and Defaults E 11
206. ation that the market for Verilog HDL related software products would grow more rapidly with broader acceptance of the language Cadence realized that Verilog HDL users wanted other software and service companies to embrace the language and develop Verilog supported design tools Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels i e gate and switch levels leading to Very Large Scale Integration VLSI Integrated Circuits IC layouts and chip fabrication A primary use of HDLs is the simulation of designs before the designer must commit to fabrication This primer does not cover all of Verilog HDL but focuses on the use of Verilog HDL at the architectural or behavioral levels The primer emphasizes design at the Register Transfer Level RTL B 1 1 2 Why Use Verilog HDL B 1 2 Digital systems are highly complex At their most detailed level they may consists of millions of elements i e transistors or logic gates Therefore for large digital systems gate level design is dead For many decades logic schematics served as the lingua franca of logic design but not any more Today hardware complexity has grown to such a degree that a sche matic with logic gates is almost useless as it shows only a web of connectivity and not the functionality of design Since the 1970s Computer engineers and electrical engineers
207. attach a voltmeter to terminal 5 connect the other side of the voltmeter to ground and simulate or attach the oscilloscope to terminal 5 and simulate the rpm value is the voltage that appears or attach a connector to terminal 5 then choose an appropriate analysis from the Analysis menu for example if you choose Analysis DC Operating Point the rpm value is the volt age at the connector This component connects the electrical and mechanical parts of a servo system Input to the motor is electrical while output is mechanical Electronics Workbench DC Motor K 2 1 Characteristic Equations The characteristic equations of an ideal DC motor are given by vor d dt K 1 0 di do de J trB o tT K i i dt where On rotational speed Km EMF constant Va armature voltage V field voltage Other terms are defined in DC Motor Parameters and Defaults The EMF constant K is determined by Yos ER 50 aN a K 27 Ny au s 60 where for separately excited DC motor for parallel excited DC motor for series excited DC motor Multisim User Guide K 3 OSIN Misc Misc Components K 2 2 DC Motor Parameters and Defaults Symbol Parameter Name Default Unit Ha Armature resistance 1 1 Q La Armature inductance 0 001 Rf Field resistance 128 Q Lf Field inductance 0 001 H Bf Shaft friction 0 01 N m s rad J
208. ay Control 8 llli 19 B 1 2 9 2Events dn t pp UR Asa aee x eg 19 B 1 2 9 3wait Statement o ooocccccocco ees 20 B 1 2 9 4fork and join Statements oococcccccccc nennen nn 20 B 1 2 9 5Traffic Light Example 2 22 2nen een ee 21 System Tasks and Functions 22222 en seen eee 23 Bal GA eleantace sese Brehna aan ran E RS 23 B 1 3 295display fa a A A en en ees 23 BES IIA Srta E vated Gn fu ub o dt 24 B 1 3 4 MONIIOR ue tad a Dres Lasten ne le a ru 24 B 13 5 scope os cese wr entera A td 25 B 1 3 6 Seltr ce ut EE etur utes Pei t e ela 25 B 1 3 7 S5hOWSCOD S aos foe a a me ee bd dod eei id 25 B31 3 895ShOWVAIS o woe a M Aa a sci a dese e EA A 25 BA S 9 StOp riii RS Y p ERA x ue beta a EORR epis 26 B 1 3 109time ar aa rl dew aer ve 26 Appendix B 1 Verilog HDL Primer B 1 1 Forward Electronics Workbench would like to thank Dr Daniel C Hyde of the Computer Science Department Bucknell University Lewisburg PA for allowing us to use his Handbook on Verilog HDL Dated August 25 1997 Dr Hydes handbook which has been incorporated into this primer provides an entry level discussion on Verilog HDL and its capabilities Introduction Verilog HDL is a Hardware Description Language HDL A Hardware Description Lan guage is a language used to describe a digital system for example a computer or a component of a computer One may describe a digital system at several levels For exam
209. ays 1 Select the Use global temperature option on the Analysis Setup tab of the resistor prop erties dialog box Specify the Global Simulation temperature TEMP on the Analysis Options dialog box 2 Deselect the Use global temperature option on the Analysis Setup tab of the resistor properties dialog box Specify the local temperature of the resistor instance on the Analy sis Setup tab of the resistor properties dialog The resistor is ideal with the temperature co efficient set to zero To include resistors in the Temperature Analysis set the temperature co efficient TC1 and TC2 in the resistor proper ties dialog box Resistor tolerance is by default set to the global tolerance defined in the Analysis Monte Carlo dialog box To set the tolerance explicitly de select Use global tolerance and enter a value in the tesistance tolerance field Electronics Workbench Resistor D 3 1 D 3 2 Resistor Background Information Resistors come in a variety of sizes related to the power they can safely dissipate Color coded stripes on a real world resistor specify its resistance and tolerance Larger resistors have these specifications printed on them Any electrical wire has resistance depending on its material diameter and length Wires that must conduct very heavy currents ground wires on lightning rods for example have large diameters to reduce resistance The power dissipated by a r
210. battery C 2 Electronics Workbench BCD up down Counter O 40 BCD to Decimal Dec 74xx145 P 15 74xx445 P 67 74xx45 P 68 BCD to seven segment dec 74xx246 P 41 74xx247 P 42 74xx248 P 43 74xx249 P 44 74xx46 P 69 74xx47 P 71 74xx48 P 73 BCD to seven segment latch dec 4511 O 41 4544 0 52 BCD to seven segment latch dec driver O 50 Binary up down Counter O 45 bipolar junction transistors about F 1 AC small signal model F 5 characteristic equations F 2 parameters and defaults F 6 time domain model F 4 BJT arrays about F 9 general purpose high current N P N transistor array F 10 general purpose P N P transistor array F 10 N P N P N P transistor array F 10 BJT See bipolar junction transistors BJT_NRES F 8 boost converter K 8 buck boost converter K 12 buck converter K 10 buzzer about J 7 Multisim User Guide C capacitor virtual D 7 capacitors about D 4 AC frequency model D 7 DC model D 5 equations D 5 RF M 1 time domain model D 5 clock C 7 coil types of N 2 comparator about G 9 parameters and defaults G 10 COMS components TinyLogic 2V P 2 connecting ammeter J 2 voltmeter J 2 connectors D 1 control functions current limiter block see also current limiter block L 16 differentiator see also differentiator L 9 divider see also divider L 3 integrator see also integrator L 11 limiter see also limiter L 15 multiplier see also multiplier L 1 three way summer L 21 transfer function block see also transfer
211. blanking input BI must be open or held at a high logic level when output functions 0 through 15 are desired The ripple blanking input RBI must be open or high if blanking of a decimal zero is not desired 2 When a low logic level is applied to the blanking input BI all segment outputs are low regardless of any other input level 3 To place the device in lamp test mode RBO must be high when LT is low This forces all lamps on Multisim User Guide P 73 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 13074xx51 AND OR INVERTER P 5 13174xx54 4 wide AND OR INVERTER AND OR INVERTER gate truth table Xhe KOKO P KH Oo x oo K W Px MOO KI A Hx OP x O U oorFrFrF P K 4 wide AND OR INVERTER truth table INPUTS OUTPUT A B c D E F G H Y 1 1 X X X X X X 0 X X 1 1 X X X X 0 X X X X 1 1 X X 0 X X X X X X 1 I 0 X X X X X X X X 1 P 5 13274xx55 2 wide 4 In AND OR INVERTER P 74 AND OR INVERTER truth table INPUTS OUTPUT A B C D E F G H Y 1 1 1 1 1 1 L 1 0 1 1 1 1 X X X X 0 X X X X 1 1 ne 1 0 X X X X X X X X 1 Electronics Workbench 74XX P 5 13374xx69 Dual 4 bit Binary Counter Counter number one has two sections counter A divide by 2 section and counter B C D divide by 8 section Counter number two has only divide by sixteen section 4 Bit counter truth table 1CLR 2CLR 19A 10B 1QC 1QD 2QA 208 2QC 20D 1 1 COUNT COU
212. bug BreakpoidtS oooocooccooccno res B3 23 B 3 9 Options Men ss ups EP en en pA RI m de EE DG EET PER B3 24 B 3 9 10ptions Fonts scs bo gto ah Br CERE ER B3 24 B 3 9 20ptions TaDS oobis ue RU PEDAL DD RUP eae d td ric B3 24 B 3 9 3Options Snap to Edges 0 00 eese B3 24 B 3 9 4Options Title Tips 0 0 0 ccs B3 25 B 3 9 50Options Analog Integer Display 0 00 0c e eee eee B3 25 B 3 9 6Options Full Path Title llilsllssell B B3 25 B 3 9 70ptions Data TIps ris sre yee ee ra dine a Deo die har olen B3 25 B 3 10Window Menu a EE nennen B3 25 B 3 10 1Window Cascade 22 222 cette eee B3 26 B 3 10 2Window Tile 0 0 000s B3 26 Electronics Workbench snus 111 SOIS B 3 10 3Window Arrange ICONS ooocccccoco res B3 26 B 3 10 4Window Explorer 2 0 0 0 rn B3 26 B 3 10 5Window Watch 0000 teens B3 26 B 3 10 6Window Data Analyzer 0000s B3 26 B 3 10 6 1 Digital and Analog Signal Display 0ooo ooooo B3 27 B 3 10 6 2Notes on using the Data Analyzer Window B3 29 B 3 11Hlelp MOn vs A a Nd B3 31 B 3 11 1Help Contents oococccocco rns B3 31 B 3 11 2Help Using Help isssssesseeese ren B3 32 B 3 11 3Help SILOS lll User s Manual 02 0000 cee eee B3 32 B 3 11 4Help Verilog LRM 2 22 cause tee B3 32 B 3 11 5Help SDF Manual ss sproken T Ea a tees B3 32 B 3 11 6Help About SSE 0 0coccccccccocn ees
213. c a Multisim User Guide C 21 seoinos Sources Sources Components C 23 1 Exponential Voltage Source This component is an exponential source of which the output is measured in vA voltage Ov 1v C 23 2 Exponential Current Source This component is the same as the Exponential Voltage Source except that b 4 the output is measured in current DA 1A C 24 Nonlinear Dependent Source Use this source for analog behavioral modeling This generic source allows you to create a sophisticated behavioral model by entering a mathematical expression Expressions may contain the following operators A AN unary and these predefined functions abs asin atanh exp sin tan acos asinh cos In sinh u acosh atan cosh log sqrt uramp The functions u unit step function and uramp integral of unit step are useful in synthesiz ing piecewise nonlinear functions 1 forx gt 0 u x 0 forx lt 0 X forx20 uramp x forx lt 0 C 22 Electronics Workbench Controlled One Shot If the argument of log In or sqrt becomes less than zero the absolute value of the argument is used If a divisor becomes zero or the argument of log or In becomes zero an error will result The small signal AC behavior of this source is a linear dependent source with a proportional ity constant equal to the derivative of the source at the DC operating point Mathematical expression examples i cos v 1 sin v 2 v In cos
214. ce can be displayed as a thicker horizontal line The default setting is for the High level to be a thicker line To change this add the fol lowing line in the Analyzer section for the sse ini file in the Windows directory Hilite Low For group names that are inserted into other groups vector names and the name for real or integer variables the value is displayed in the center of the waveform resolution permitting Double clicking on an inserted group or vector name will show or hide the individual bits Color is used to denote the strength for vector signals Purple is used to represent a vector whose bits are at different strengths If the timing markers have been set then the vector value is provided at the top of the display along with the vector strength If the bits for the vector are at different strengths then Mixed Strength is displayed at the top of the display When the timing markers have been set their value is shown in the status bar at the bottom of the Data Analyzer If the bits are at different strengths then Mixed Strength is displayed for the timing marker value Electronics Workbench Window Menu Analog signals H SILOS c silos3 examples analog spi Debug Data Analyzer File View Project Explorer Debug Options Window Help l x Zal fal 88 0 aksa Command Name Scope Value 000us B6 090us 1721 Default clock top sto down_up top sto t
215. ced to the load is less than the rated maximum as determined from rated maximum sink source specifications for a particular opamp operation of the opamp circuit will be as expected If the current to be sinked sourced is greater than the rated maximum as determined by a larger than normal input to the opamp circuit the current limiter will limit current to the spec ified safe maximum value thus protecting the opamp and associated circuitry from damage In the example circuit shown below the sink and source current limits are set to 2 mA and the circuit gain K is set to 1 For this case output current should then be Iload 2 Vin K Rload The switch activated by pressing S applies either a positive or negative input to the op amp circuit These input levels are such that the output current would be in excess of the rated value of 2 0mA The current limit function limits the source or sink output to 2 0 mA If the input levels are reduced to 2V or less then the output current will be as expected at Vin Rload Multisim User Guide L 17 O1U0D Controls Controls Components A sine wave input of 1 4v RMS or less will be passed undistorted through the amplifier while inputs greater than 1 4 v RMS will show limiting clipping at the peaks Positive supply M5 Positive input v6 10v 341 i 81 18 Negative T 1 Rload R1 1ka Negative Supply M8
216. chunks so it requires less memory To change behavioral stimulus to a stimulustable format you can simulate the behavioral stimulus with SILOS III and then store the results from the probe command as a file of tab ular ones and zeros The file can then be edited to remove the title for the probe command n n report Each line of tabular values in the file must end with a semicolon To add a semico man lon at the end of each line put a at the end of the probe state i e store probe inl in2 bil bi2 For example for file stimulus v timescale ins 100ps module foo reg inl in2 reg bil bi2 wire bil bil bi directional inputs wire bi2 bi2 bi directional inputs initial begin inl 0 in2 0 bil 0 bi2 0 10 inl 1 bil 1 10 bi2 1 bz 10 Sfinish end endmodule The following commands would be used from a file to simulate the stimulus include stimulus v control savsim 2 Isim disk stim v scope foo Istore probe inl in2 bil_ bi2_ Next edit file stim v and remove the report header for the probe report and any messages from the probe report Then include file stim v into a stimulustable statement control ext stim timescale ins 100ps module foo Electronics Workbench Verilog HDL Extensions reg inl in2 reg bil bi2 wire bil bil bi directional inputs wire bi2 bi2 bi directional inputs initial be
217. cified by the CONTROL command 2 To respecify the page width for the NSTORE command use the FORMAT NSTORE command 3 The default file name for the NSTORE command may be redefined using the DISK com mand or the FILE STO command Examples nstore output on change NSTO NETWORK FDD PREPROC B 2 2 17Preprocessing Data B 2 44 Normally data preprocessing is automatically performed prior to initialization or simulation i e when the SIMULATE command are entered However you may wish to use the PRE PROC command to check for syntax errors without simulating To preprocess data enter PREPROC Application Notes During data preprocessing the program resolves and checks all gate input connections calculates fan out connections and creates implicit nodes Generally the data is reformat ted for more efficient simulation 2 Once preprocessing has been performed additional topological data cannot be entered 3 Note that at least the first three letters of this command must be specified i e PRE 4 If serious errors occur during a phase of the preprocessing you should correct the errors before proceeding If the errors were corrected interactively enter RESET ERRORS and then reissue the PREPROC command to continue preprocessing probe Electronics Workbench Silos III Command Line Usage B 2 2 18Probing Node States The probe command reports the value of variables and expressions in tabular format
218. cs Workbench Silos III Command Line Usage SAVSIM 3 SYNONYM SKIP TPS XL_ORDER val Application Notes Specifies that all logic type integer type and double type simulation node values are to be saved Output val ues can be retrieved for any network node Causes SILOS III to retain the hierarchical node names synonyms in addition to the real node name for the upper most level that the node is connected to in the hier archy When all synonyms are saved SILOS III will rec ognize the hierarchical name as well as the real name to each node in the design Caution Saving all synonyms may slow down input parsing and memory usage may go up Default SYNONYM 1 SYNONYM 0 Don t save synonyms SSYNONYM 1 Save all synonyms Causes SILOS III to set a skipped port to a level The default level is High Z unknown An allowed level is ground for compatibility with VCS control skip gnd Default SKIP gnd Specifies the default command for redirecting report out puts to standard output or disk file Allowed qualifiers are TYPE WTYPE STORE NSTORE Specifies a switch so that the order of evaluation for always blocks is the same order as for Verilog XL where val is 1 for xl order being on the same as Verilog XL and 0 for xl order being off default This switch may be useful for obtaining the same simulation results as Verilog XL This option must be parsed before any mod ules are par
219. ct Restore Project State 0 0 0 cece B3 11 B 3 5 8Project Project Settings oooococcocccrcoono ee B3 11 B 3 5 9ProjecUFilt rs iius i Sewn ala Petes Mos ea peta hon eG ee eey B3 13 B 3 5 10Project Load Reload Input Files 0 0 00 c eee eee eee B3 14 B 3 5 11Project Load and Go 1 1 tee B3 14 B 3 6 Reports Menu u reres 2 2 220 00 pie ee EAR ete re an aoe toe ge be B3 14 B 3 6 1Reports Activity 2 2 22 220m seen tee B3 14 B 3 6 2Reports Errorsty as os ri Bern UR WEN REP Dres B3 15 B 3 6 3Reports Fault saeide naenda Ee een nn B3 16 B 3 6 4Reports lteration 22222 n nennen ees B3 16 B 3 6 5Reports NONCONVErgenCe oococcocccc nennen nennen B3 16 B 3 6 5 1Nonconvergence For Gate Designs ooo ooocooooo B3 16 B 3 6 5 2Nonconvergence Hanging for Behavioral Designs B3 18 B 3 6 6Reports Size 6 err B3 19 B 3 7 Explorer Men RR eer bb ee B3 19 B 3 7 1Explorer Open Explorer o oooococccocco eh B3 19 B 3 7 2Explorer Go to Module Source 1 6 0 B3 20 B 3 8 Debug Men rr crr ssl dag ER n ARR eed eae en B3 20 B 3 8 TDeb g GO o kao reds PES as re E Sees arro re B3 21 B 3 8 1 1Simulation Suggestions llli eleison B3 21 B 3 8 2Debug Break Simulation llli eee B3 22 B 3 8 3Debug Finish Current Timepoint llle eese B3 22 B 3 8 4Debug Restart Simulation llle B3 22 B 3 8 5Debug Step 2m Hmm rns B3 22 B 3 8 6De
220. cts one of eight data sources and is equipped with one enable input and two complementary outputs Data selector multiplexer truth table SELECT STROBE OUTPUTS C B A G Y w X X X 1 0 1 0 0 0 0 DO DO 0 0 1 0 D1 DI 0 1 0 0 D2 D2 0 1 1 0 D3 D3 1 0 0 0 D4 D4 1 0 1 0 D5 D5 1 1 0 0 D6 D6 Bl 1 1 0 D7 D7 This data selector multiplexer contains full on chip binary decoding to select one of eight data sources Data selector multiplexer truth table SELECT INPUTS ae c B A W 0 0 0 DO 0 0 1 Di 0 1 0 D2 0 1 1 D3 1 0 0 D4 1 0 1 D5 1 1 0 D6 1 1 1 D7 Electronics Workbench 74XX P 5 37 74xx153 Dual 4 to 1 Data Sel MUX This data selector multiplexor contains inverters and drivers to supply fully complementary on chip binary decoding data selection to the AND OR gates Separate strobe inputs are pro vided for each of the two four line sections Data selector multiplexer truth table SELECT DATA INPUTS STROBE OUTPUTS B A co ci c2 c3 E Y X X X X X X 1 0 0 olo X X X 0 0 0 0 1 X X X 0 1 0 lx 0 X x 0 0 0 1 X E X X 0 1 1 ofx X 0 X 0 0 1 O XxX X 1 X 0 1 1 1X X X 0 0 0 1 al X X X al 0 1 P 5 38 74xx154 4 to 16 Dec DEMUX This 4 line to 16 line decoder uses TTL circuitry to decode four binary coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs are low Multisim User Guide P 19 seues Xxv4 suonounJj Functions 74XX Series 4 to 16
221. cture is used to describe a circuit in terms of its compo nents Structure can be used to create a very low level description of a circuit such as a transistor level description or a very high level description such as a block diagram In a gate level description of a circuit for example components such as basic logic gates and flip flops might be connected in some logical structure to create the circuit This is what is often called a netlist For a higher level circuit one in which the components being connected are larger functional blocks structure might simply be used to segment the design description into manageable parts Structure level VHDL features such as components and configurations are very useful for managing complexity The use of components can dramatically improve your ability to reuse elements of your designs and they can make it possible to work using a top down design approach A 2 6 1 Sample Circuit To help demonstrate some of the important concepts covered so far in this section a very sim ple circuit will be presented It will show how the function of this circuit can be described in A 10 Electronics Workbench Learning VHDL VHDL The design descriptions shown are intended for synthesis and therefore do not include timing specifications or other information not directly applicable to today s synthesis tools The circuit combines the comparator circuit presented in A 2 1 A Simple Example on page
222. d The library files will be searched in the order specified to the program Each LIBRARY command will override any previous LIBRARY commands they are not cumulative A LIBRARY command can use more than one line by beginning each new line with a sign in column one see the Examples below If the file name specified by the LIBRARY command cannot be found during the CHECK command a warning mes sage is issued Entering the LIBRARY command after preprocessing PREPROC com mand has no meaning and a warning message is not issued Library files can be encrypted by the CHGLIB program Once a file has been encrypted it cannot be entered with the INPUT command or include compiler directive It is good practice to check the files for errors with the INPUT command before encrypting them Library files can be converted to random access files by the CHGLIB program Once a file has been converted to random access it cannot be entered with the INPUT command or include compiler directive It is good practice to check the files for errors with the INPUT command before converting them to random access Examples LIBRARY d test asic v lib fast lib nmos lib ecl dat TTL LS B 2 3 3 TTL LS Parts List The list below shows the TTL LS library parts provided with SILOS III The behavioral source for these parts is provided with unit delays and with full timing Ref TTL Logic Data book SDLD001A Revised March 1988 B 2 64 Electro
223. d against the data in the column The variable on the right side of the sign is used as a strobe Variables used in the table can be a wire register memory element integer or real variable of any width and they can have any valid Verilog name In the example below for stimulustable s1 register variable inl and memory element in2 are driven by the data in the table Wire outl is verified against the data in the table whenever the variable strobel is high To prevent possible race conditions the rising or the falling edge of the strobe signal strobe1 should not coincide with a change in the expected output for out1 in the stimulustable Electronics Workbench Verilog HDL Extensions control ext stim timescale 1ns 100ps module test reg 7 0 ini in2 1 0 wire 7 0 outi in1 in2 0 reg strobel initial strobel 0 always Goutl begin 480 1 strobel 1 40 1 strobel 0 end initial begin 5 stimulustable s1 table 1 2 inl in2 0 outlestrobel 00 00 ff 0e Oa f6 ff ff 00 endtable endstimulustable end endmodule B 2 1 3 3Radix Data in the table can be in hexadecimal 96h is the default octal 960 or binary 96b for reg ister data types and integer or floating point for integer and real data types There must be one or more blank spaces between the radix symbol and the variable name it refers to such as h in2 Each row of values in the table is terminated by a semicolon Blank spaces and t
224. d transistor control components The internal circuitry of an IC voltage regulator is similar to that of the series feedback regulator K 6 1 Input Output Voltage Differential Rating The input output voltage differential rating shows the maximum difference between V and Vout that can occur without damaging an IC voltage regulator The differential voltage rating can be used to determine the maximum allowable value of V as follows Vintmax Vouttadj T Va where Vin max the maximum allowable unrectified dc input voltage Vout adj the adjusted output voltage of the regulator Va the input output voltage differential rating of the regulator Multisim User Guide K 7 OSIN Misc Misc Components K 6 2 DC Output Voltage K 7 K 8 K 8 The following equation can be used to determine the dc output voltage of the circuit V 125 22 1 1 25 dc Ry where Vac u the regulated dc output voltage of the regulator Voltage Suppressor o The voltage suppressor diode is a Zener diode that is capable of handling PBKE200A high surges It is used as a filtering device to protect voltage sensitive elec tronic devices from high energy voltage transients The voltage suppressor diode is connected across the AC power input line to a DC power sup ply It contains two zener diodes that are connected back to back making the voltage suppres sor diode bi directional This characteristic enables it to
225. d MEXCLUDE commands can be used with the CONTROL SAVSIM 1 option Examples CONTROL SAVSIM 1 MKEEP macl a b mkeep m1 bit0 m1 bit1 m1 bit2 m1 bit3 m1 bit4 m1 bit5 mi bit6 mi bit7 driver iobuf pin34 Multisim User Guide B 2 41 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 2 15Nonconvergence Summary The t s NOCONV command generates a report of any nonconverged nodes and their oscil lating states for the time point that nonconvergence occurred To obtain a nonconvergence summary for nodes and devices enter TYPE STORE NOCONV INPUT ITER val WTYPE NSTORE TYPE TYPE optional directs the nonconver STORE gence table to standard output STOREor to a disk file NOCONM reports the oscillating states for nonconverged nodes INPUT optional reports the states for all inputs of devices which drive the oscillating nodes ITER val optional specifies the iteration number to the 1st of eight states for each node reported for nonconver gence The default iteration for val is computed such that the last of the eight states reported corresponds to the last iteration simulated before no convergence halted the simulation Application Notes 1 The t s NOCONV command can be used to identify which parts of the circuit have caused a logic initialization or logic simulation to nonconverge 2 The t s NOCONV command reports the following information names of the
226. d for the module instances in the design The LIBRARY command can be used to specify library file names and file name extensions for library files To specify the library file names enter LIBRARY filename ext LIBRARY Defines disk file names for external libraries 2 Represents the name of one or more additional library filename ad de disk files ext Represents the file name extension When searching a directory for library files SILOS III searches for a file whose root name is the same as the module name on the module instance and whose exten sion matches the extension specified for the library search Multisim User Guide B 2 63 suoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions Application Notes 1 Library files can contain module definitions and module instances and macro definitions and macro expansions Commands are not allowed in library files other than the BUS and INIT commands for SILOS netlists LIBRARY files are useful for A method of inputting library parts with specific timing Reducing memory by not loading unreferenced netlist data Encrypting data see B 2 2 4 Encrypting Library Files The search order for a module definition or macro definition is e Files entered by the INPUT command or include compiler directive e Library file names or directories that contain library files ending with a specified extension that were specified by the LIBRARY comman
227. d math functions such as sine cosine log power directly in your Verilog HDL code This is an extension to the IEEE standard for Verilog HDL B 2 1 4 2 Utility Transcen dental Functions The project for analog behavioral modeling is already set up To open the project select the Project Open menu selection Then change to the examples subdirectory of the installa tion directory select project analog spj and then click on the OK button to close the dia log box B 2 1 3 14Running the Analog Behavioral Modeling Sim ulation Click on the Go button on the Toolbar to load the input file and run logic simulation The logic simulation will run until it encounters the finish system task in file analog v To display the logic simulation results click on the Open Analyzer button on the Toolbar to open the Analyzer Window You should see both analog and digital waveforms displayed in the Waveform Display Window You can double click on the analog signal names top feedback and top analog in to tog gle between a piece wise linear or analog display see B 3 10 6 1 Digital and Analog Signal Display The integer top counter value can also be displayed as an analog waveform by selecting the Options Analog Integer Display menu selection You can use the timing mark ers to display the analog values This concludes the analog behavioral modeling example To run the other examples for the Tutorial see Desig
228. d the Output window never displays the Ready prompt this is usually due to an error in the behavioral code in an initial or an always block The below example hangs at time 0 due to the incorrect code i 1 which should be i i 1 in the below for loop module hang at O0 reg a integer I initial for i 0 i lt 10 i 1 a a endmodule To debug a design that hangs at time 0 use comments to comment out portions of the design until it no longer hangs at time 0 Then inspect the commented code and fix the problem in the behavioral code When SILOS III hangs during simulation the program will not respond to the STOP button or the Esc key on the keyboard User errors in behavioral code are usually what cause SILOS III to hang These errors are usually caused by a loop with no delay such as in these code seg ments Code Segment 1 for i a b c i i 1 begin if d amp 9 h100 0 begin b b H1 end end Code Segment 2 always a b b always b a a Electronics Workbench Explorer Menu Code segment 1 hangs when the if test is not true causing the for loop to infinitely loop at a time step Code segment 2 hangs because each always block is triggering the other always block and neither always block has delay To debug a hang during simulation run the simulation until it hangs and then note the sim ulation time value on
229. d when the program runs e An end statement The easiest way to think of a VHDL process such as this is to relate it to software as a pro gram that executes in simulation any time there is an event on one of its inputs as specified in the sensitivity list A process describes the sequential execution of statements that are dependent on one or more events occurring A flip flop is a perfect example of such a situa tion it remains idle not changing state until there is a significant event either a rising edge on the clock input or an asynchronous reset event that causes it to operate and potentially change its state Although there is a definite order of operations within a process from top to bottom you can think of a process as executing in zero time This means that a a process can be used to describe circuits functionally without regard to their actual timing and b multiple processes can be executed in parallel with little or no concern for which processes complete their Multisim User Guide A 15 dwd TAHA VDHL Prrimer VHDL Primer A 16 operations first There are certain caveats to this behavior of VHDL processes These caveats are described in detail in most VHDL textbooks For your reference the process of how the barrel shifter operates is shown below reg process Rst Clk variable Oreg std ulogic vector 0 to 7 begin if Rst 1 then Async reset Oreg 00000000 elsif Clk
230. d z values All bits must match for equality Returns TRUE or FALSE Case inequality The bitwise comparison includes comparison of x and z values Any bit difference produces inequality Returns TRUE or FALSE Electronics Workbench The Verilog Language T Concatenation Joins bits together with 2 or more comma separated expressions e g A 0 B 1 7 concatenates the zeroth bit of A to bits 1 to 7 of B lt lt shift left Vacated bit positions are filled with zeros e g A A lt lt 2 shifts A two bits to left with zero fill gt gt shift right Vacated bit positions are filled with zeros Conditional Assigns one of two values depending on the conditional expression e g A C gt D B 3 B 2 means if C greater than D the value of A is B 3 otherwise B 2 B 1 2 5 8 Operator Precedence The precedence of operators is shown below The top of the table is the highest precedence and the bottom is the lowest Operators on the same line have the same precedence and asso ciate left to right in an expression Parentheses can be used to change the precedence or clarify the situation We strongly urge you to use parentheses to improve readability unary operators amp amp highest precedence amp gt gt lt gt gt mt a nm amp ER u amp amp B 1 2 6 2 6 Control Constructs Verilog HDL has a rich collection of control statements which can used in the procedural sec tions
231. data type in VHDL has a defined set of values and a defined set of valid operations Type checking is strict so it is not possi ble for example to directly assign the value of an integer data type toabit vector data type There are ways to get around this restriction using what are called type conversion functions These are not discussed in this manual but examples of their use are provided in A 4 Examples Gallery on page A 23 The following chart summarizes the fundamental data types available in VHDL Data Type Values Example Bit 1 0 Q lt 1 Bit_vector array of bits DataOut lt 00010101 Boolean True False EQ lt True Integer 2 1 0 1 2 3 4 etc Count lt Count 2 Real 1 0 1 0E5 etc V1 V2 5 3 Physical 1 ua 7 ns 100 ps etc Q lt 1 after 6 ns Record various Tvec Clk Inp Result Character a b 2 etc CharData lt X String Array of characters Msg lt MEM amp Addr A 2 5 Design Units One concept unique to VHDL when compared to software programming languages and to Verilog HDL is the concept of a design unit Design units which may also be referred to as library units are segments of VHDL code that can be compiled separately and stored in a library You have been introduced to two design units already the entity and the architecture There are actually five types
232. de B 2 35 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 2 8 Error Summary When the program indicates that errors occurred during read in preprocessing or simulation you should enter the t s ERRORS command to determine their error level and type For input errors the line number and the input file name will also be reported To check the errors enter TYPE STORE ERRORS LEVEL value WTYPE NSTORE TYPE optional Ddirects the error messages to standard outpu STORE tor to a disk file ERRORS Reports any error and warning messages LEVEL optional lindicates that only those errors with a severity level equal to value are to be output If not specified all errors will be output value Represents a value from 1 to 5 Examples STOR ERROR LEVEL 2 ty er B 2 2 9 Exclude Saving Simulation Node States The EXCLUDE command specifies nets whose state values will not be saved during simula tion To exclude registers see B 2 2 13 Exclude Saving Module Instance Variable Values The format for the EXCLUDE command is EXCLUDE name name ga name EXCLUDE Specifies nets whose state values will not be saved during simulation B 2 36 Electronics Workbench Silos III Command Line Usage name Represents the name of a net whose state changes will not be saved during simulation Application Notes 1 The KEEP command can be used to specify nets whose simulation states are to be saved The
233. de is repre sented by a small signal conductance gp The small signal capacitance is also evaluated at the DC operating point ais mo ME dVp ds nVr Y l T 8p Co 1 for V lt FC jo cm dQ 9 DT OP dV C V rite en e 2 for V 2 FC j 2 0 where OP Operating point Qp the charge on Cp Electronics Workbench E 4 Diode E 1 5 Diode Parameters and Defaults Symbol Parameter Name Default Typical Value Unit IS Saturation current 1e 14 1e 9 1e 18 cannot A be 0 RS Ohmic resistance 0 10 WwW CJO Zero bias junction capaci 0 0 01 10e 12 F tance VJ Junction potential 1 0 05 0 7 V TT Transit time 0 1 0e 10 s M Grading coefficient 0 5 0 33 0 5 Symbol Parameter Name Default Typical Value Unit BV Reverse bias breakdown volt 1e 30 V age N Emission coefficient 1 1 EG Activation energy 1 11 1 11 ev XTI Temperature exponent for 3 0 3 0 effect on S KF Flicker noise coefficient 0 0 AF Flicker noise exponent 1 1 FC Coefficient for forward bias 0 5 0 5 depletion capacitance formula IBV Current at reverse breakdown 0 001 1 0e 03 A voltage TNOM Parameter measurement tem 27 27 50 C perature Multisim User Guide E 5 sepoiq Diodes Diodes Components E 2 E 2 1 E 3 E 6 Pin Diode The PIN diode consists of three semiconductor materials The center material is made up of intrinsic pu
234. decoder demultiplexer with input latches The input latches allow for the user to hold a previous input with the enable input while the inputs change FS EF PA ER PSU ES E IPS n e m al al al el al sl al al lo 3 Multisim User Guide 0 43 seues 000p suonounJ Functions 4000 Series 1 of 16 decoder demultiplexer truth table OUTPUTS INPUTS E A3 A2 Al A000 O1 O2 O3 O4 05 O6 O7 O8 09 O10 O11 O12 O13 O14 O15 Electronics Workbench This device is a 1 of 16 decoder demultiplexer with input latches The input latches allow for the user to hold a previous input with the enable input while the inputs change do J do dr do do ds JPL US dP I 4718191 oO ro Y wo 917 0 0O ana oO s wo B6868060580rzrz22z RN S H H 1 1 1 3 WwW amp X g g u a m m ls lo T 0 2 75 4515 1 of 16 Dec DEMUX w Input latches 0 44 sanas 000p suonouny 4000 Series ICs 1 of 16 decoder demultiplexer truth table OUTPUTS INPUTS E A3 A2 Al A0 O0 O1 O2 O3 O4 O5 O6 O7 O8 09 O10 011 O12 013 014 015 O 2 76 4516 Binary up down Counter This binary up down counter counts from 0000 to 1111 in binary 0 to 15 in decimal Functions 4000 series O 45 Multisim User Guide Functions 4000 series Functions 4000 Series Binary up down counter truth table MR PL UP DN CE CP MODE or 3 X X X PARALLEL LOAD 0 0 x 1 x NO CHANGE 0 0 0 0 COUNT DOWN 0
235. ded It encodes eight data lines to three line 4 2 1 binary octal 8 line to 3 line priority encoder truth table INPUTS OUTPUTS EI 0 1 2 3 4 5 6 7 A2 Al A0 GS EO 1 X X X X X X X X 1 1 1 1 1 0 1 1 J 1 ji 1 1 1 1 1 T 1 0 0 X X X X X X X 0 0 0 0 0 l 0 X X X X X X 0 al 0 0 1 0 l 0 X X X X X 0 1 al 0 1 0 0 1 0 X X X X 0 1 1 al 0 d 1 0 l 0 X X x 0 1 1 1 1 1 0 0 0 1 0 X X 0 Y 1 1 1 1 1 0 1 0 1 0 x 0 1 1 1 1 1 1 1 j 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 P 16 Electronics Workbench 74XX P 5 33 74xx15 3 3 Input AND Logic function Y ABC AND gate truth table OF x orn u o x Mm FIO oo O H kK P 5 34 74xx150 1 of 16 Data Sel MUX This device can select one of sixteen data sources when a 4 bit binary number is applied to the inputs It is equipped with one enable input and a complementary output Truth table INPUTS OUTPUTS D C B AG w X X X X 1 1 0 0 0 0 0 EO 0 0 0 1 0 El 0 0 1 0 0 E2 0 0 1 1 0 E3 0 1 0 0 0 E4 0 T 0 1 0 E5 0 1 1 0 0 E6 0 1 1 1 0 E7 1 0 0 0 0 E8 1 0 0 1 0 E9 1 0 1 0 0 E10 1 0 1 1 0 E11 1 1 0 0 0 E12 1 1 0 1 0 E13 1 1 1 0 0 E14 1 1 1 1 1 E15 Multisim User Guide P 17 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 35 74xx151 1 of 8 Data Sel MUX P 5 36 74xx152 Data Sel MUX P 18 This data selector multiplexer contains full on chip binary decoding to select the desired data source It sele
236. developing input test patterns to detect circuit faults for fault simulation The number of level transitions at a node indicates an input test pattern s effectiveness Faults at nodes which make no level transitions can not be detected Reports Activity can be used to generate the following report e An activity table that lists the node names of nodes that do not transition AnHDL Code Coverage table that lists the lines of each file that were not executed This Electronics Workbench Reports Menu can be used to find problems with the HDL code or stimulus that is not exercising all of the HDL code e An activity summary that lists totals for the number of nodes at each level of activity count e An activity histogram that shows known and potential level transitions versus time For the activity table for the Activity report you will see the following legend Legend for TRANSITION COUNT column value Number of definite transitions value Number of possible transitions H No definite transitions node High at Min time specified L No definite transitions node Low at Min time specified The legend is stating that a value is reported to the left of a node name A definite transi tion is defined as a change from a Low to High level or High to Low level even if it goes through an intermediate Unknown level A possible transition is defined as a change from a High or Low level to the Unknown level
237. divided into the forward and reverse char acteristics DC forward characteristic Vp I L e 1 V G for Vp 2 5nV DC reverse characteristic Vo nV Le 1 Vp G nin for 5nV Vp lt 0 I V p Grin for BV lt V lt 5nV D IBV for Vp 2 BV 1 BV4Vp BV H e 2 14 for Vp lt BV V where lp current through the diode in amperes Vo voltage across the diode in volts Vr thermal voltage 0 0258 volts at room tem perature 27 C BV breakdown voltage I is equivalent to the reverse saturation current of a diode In a real diode J doubles for every 10 degree rise in temperature Other symbols used in these equations are defined in the table below Multisim User Guide sepoig Diodes Diodes Components E 3 2 Zener Diode Parameters and Defaults Symbol Parameter name Default Unit Is Saturation current 1e 14 A Rs Ohmic resistance 0 Ww CJO Zero bias junction capacitance 0 F VJ Junction potential 1 V TT Transit time 0 S M Grading coefficient 0 5 VZT Zener test voltage 1e 30 V IZT Zener test current 0 001 A N Emission coefficient 1 EG Activation energy 1 11 ev XTI Temperature exponent for effect 3 0 on Is Symbol Parameter name Default Unit KF Flicker noise coefficient 0 AF Flicker noise exponent 1 FC Coefficient for forward bias deple 0 5 tion capacitance formula TNOM Parameter measurement tempera 27 C
238. dodo db E Suh 70v Eo P X Qr RU ESCXE Uo do ode uh do A CES dn d d CY EEE P I Qu EE XE ESO A da de E Wn doc do d Y udo X VEO oe X de 0 xRS YECTUES dO udh dp de de Wd CES dn do d Eo du do X L 9 0 1 X X X X 1 1 al 1 l 1 1 1 1 T 1 1 1 1 1 lI 1 0 X X X X 1 1 al 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X ab 1 1 1 1 1 TX 1 1 1 1 1 1 1 1 al Electronics Workbench 74XX P 5 44 74xx16 Hex INVERTER OC This device contains six inverters For correct performance the open collector outputs require pull up resistors Logic function Y A INVERTER gate truth table A Y 1 0 0 d P 5 45 74xx160 Sync 4 bit Decade Counter clr This synchronous presettable decade counter features an internal carry look ahead for fast counting Decade counter truth table INPUTS OUTPUTS OPERATING MODE MR CP CEP CET PE DN QN TC 0 X X X X X 0 0 Reset clear 1 X X 1 13 0 0 1 Xx x 1 h 1 1 Parallel load 1 h h h X count 1 Count 1 X 1 X h X dn 1 Hold do nothing 1 X X 1 h Xx An 0 1 High voltage level High voltage level one setup prior to the low to high clock transition Low voltage level Low voltage level one setup prior to the low to high clock transition dn Lower case letters indicate the state of the referenced output prior to the low to high clock transition X Don t care Multisim User Guide P 23 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series Hd
239. e module name port list declares module items endmodule The module name gt is an identifier that uniquely names the module The port list is a list of input inout and output ports which are used to connect to other modules The declares section specifies data objects as registers memories and wires as wells as procedural con structs such as functions and tasks The module items may be initial constructs always constructs continuous assignments or instances of modules The semantics of the module construct in Verilog is very different from subroutines proce dures and functions in other languages A module is never called A module is instantiated at the start of the program and stays around for the life of the program A Verilog module instan tiation is used to model a hardware circuit where we assume no one unsolders or changes the Electronics Workbench The Verilog Language wiring Each time a module is instantiated we give its instantiation a name For example NAND1 and NAND2 are the names of instantiations of our NAND gate in the example below Here is a behavior specification of a module NAND The output out is the not of the and of the inputs inl and in2 Behavioral Model of a Nand gate By Dan Hyde August 9 1995 module NAND inl in2 out input inl in2 output out continuous assign statement assign out inl in2 endmodule The ports in1 in2 and out are
240. e a task may call itself but each invocation of the task uses the same storage i e the local variables are not pushed on a stack Since concurrent threads may invoke the same task the programmer must be aware of the static nature of stor age and avoid unwanted overwriting of shared storage space The purpose of a function is to return a value that is to be used in an expression A function definition must contain at least one input argument The passing of arguments in functions is the same as with tasks see above The definition of a function is the following Multisim User Guide B 1 17 Jewud Boje Verilog Primer Verilog HDL Primer function range or type function name Notice no parameter list or s argument ports declarations statements endfunction where range or type is the type of the results passed back to the expression where the function was called Inside the function one must assign the function name a value Below is a function which is similar to the task above Testing functions Dan Hyde Aug 28 1995 module functions function 1 1 add2 function definition input a b two input argument ports reg R register declaration begin BR uds if a b add2 1 amp R else add2 end endfunction Il o initial begin initl reg p p add2 1 0 invocation of function with 2 arguments display p b p end endmodule B 1 2 9 Timing Control
241. e a so file on Solaris enter the following load command ld o mylib so dy G o The SILOS III pliload command is used to specify the so files for SILOS III at runt ime The pliload command is cumulative so that one or more pliload commands is allowed before starting simulation The pliload command can be entered at the in the Command window for the Main toolbar from the SILOS III command line or from a file pliload mypli so example of entering the pliload command at the in the Command window for the Main toolbar silos exe myfile v pliload mypli so example of entering the pliload command at the command line Electronics Workbench Verilog HDL Extensions pliload mypli so example of entering the pliload command at the in the Command window for the Main toolbar module foo entering the pliload command from a file endmodule ifdef silos pliload mypli so endif For more information see the README TXT file in the PLI subdirectory for the SILOS III installation e For an example of using PLI with SILOS III see file pli01 spj PLI subdirectory for the SILOS III installation or contact Simucad B 2 1 1 3List of Implemented PLI Routines The Silos Simulation Environment uses the IEEE 1364 Standard Hardware Description Lan guage Based on the Verilog Hardware Description Language manual as the specification for the PLI Many of the tf PLIroutines for linking user C programs to SILOS II
242. e body region underneath the gate oxide Current is conducted through the resulting short channel to the substrate and then vertically down the substrate to the drain The DMOS transistor can have a breakdown voltage as high as 600 V and a current capability as high as 50 A is possible Power MOSFETs have threshold voltages in the range of 2 to 4 V In comparison with BJTs power MOSFETS do not suffer second breakdown nor do they require the large base drive currents of power BJTS They also have a higher speed of operation than the power BJTs These advantages make power MOSFETS suited to switching applications such as in motor control circuits N Channel amp P Channel GaAsFET 4 l This component is a high speed field effect transistor that uses gal Gaasret n_ioca lium arsenide GaAs as the semiconductor material rather than silicon It is generally used as a very high frequency amplifier into the giga hertz range A GaAsFET consists of a length of n type or p type doped GaAs called the channel The ends of the channel are called the source and the drain The terminal with the arrowhead represents the gate GaAsFETS are used in microwave appli cations Model and Characteristic Equations The GaAsFET component is based on the Statz model Multisim User Guide F 19 SJO SISUBJ Transistors Transistors Components O for V Vi lt 0 3 Id 11 03 B 1 A Vy HA Vio for V Vo 20 1 B V Vo g is where V
243. e command line options For example silos exe f design vc File design vc would then contain the following commands and file names for the above example v examl udp v examl lib y library libext v examl v examl tst plusargs is one or more arguments for the testplusargs system task in Verilog HDL filename filename is the name of one or more input files for SILOS III The files can contain Verilog HDL at the behavioral gate and switch levels The files can also contain SILOS III commands Any SILOS III commands in the files will be exe cuted as they are encountered lcommand I command is one or more optional SILOS III commands For information on how to use SILOS III commands in a file which may be simpler than from the command line The is required for all SILOS III commands that are on the command line There must be no whitespace between the and the SILOS III com mand SILOS III commands that contain an embedded space must be enclosed by quotes such as Ibat examl log B 2 2 28 4Unix Batch Execution SILOS III can be run as a batch execution from the Unix operating system The command line syntax for running SILOS III as a batch execution on the Unix operating system is silos options plusargs filenamel filenamen command1 commandn where Multisim User Guide B 2 61 suoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions silos is the path to the
244. e current gain coefficient 1 1 rb Base ohmic resistance 0 100 W re Emitter ohmic resistance 0 10 Ww rc Collector ohmic resistance 1 Ww Cs Substrate capacitance 0 1 F Ce Cc Zero bias junction capacitances 0 2e 09 F be dc Junction potentials 0 75 0 75 V tF Forward transit time 0 1e 13 S TR Reverse transit time 0 10e 09 S me mc Junction grading coefficients 0 33 0 5 VA Early voltage 1e 30 200 V Ise Base emitter leakage saturation cur 0 1e 13 A rent Ikf Forward beta high current knee point 1e 30 0 01 A Ne Base emitter leakage emission coeffi 1 5 2 cient NF Forward current emission coefficient 1 1 NR Reverse current emission coefficient 1 1 VAR Reverse early voltage 1e 30 200 V IKR Reverse beta roll off corner current 1e 30 0 01 A ISC B C leakage saturation current 0 0 01 A NC B C leakage emission coefficient 2 1 5 Electronics Workbench BJT NPN amp PNP Symbol Parameter Name Default Example Unit IRB Current for base resistance equal to 1e 30 0 1 A rb RBM 2 RBM Minimum base resistance at high cur 0 10 WwW rents XTF Coefficient for bias dependence of tF 0 0 VTF Voltage describing VBC dependence 1e 30 V of tF ITF High current dependence of tF 0 A PTF Excess phase at frequency equal to 1 0 Deg tF 2Pl Hz XCJC Fraction of B C depletion capacitance 1 connected to internal base node VJS Substrate junction build in potential 75
245. e ee OR 7 EI i toet E a Gs 29 2308 o 208 5 8 13 8 AA ED I I l 1l 9 d en 6 GbR pues CX AES 3s 308 ai 10 b A pecho uo m q emn A A X 11 b X De Fag mb Qa a m xb 12 E VEO 1 1 A A 0 0 21 cR 13 p cC oc a COR pcm pE cdm as ooa b 14 p Ux GEO a eX copo a 0607 3s A idee om 15 g o wo Os E O ie ade Oc A A O BI x TETERA o 0o 0o o 0o o 2 RBI de o cr ww OP o o o a o a oOx o 0 3 LT O NAE S E S Il ae E E XE de Epod Notes 1 The blanking input BI must be open or held at a high logic level when output functions 0 through 15 are desired The ripple blanking input RBI must be open or high if blanking of a decimal zero is not desired 2 When a low logic level is applied to the blanking input BI all segment outputs are low regardless of any other input 3 When ripple blanking input RBI and inputs A B C and D are at a low level with the lamp test input high all segment outputs go low and the ripple blanking output RBO goes to a low level response condition 4 When the blanking input ripple blanking output BI RBO is open or held high and a low is applied to the lamp test input all segment outputs are high Multisim User Guide P 43 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 78 74xx249 BCD to seven segment dec P 44 The BCD to seven segment decoder driver features active high outputs for driving lamp buffers It has full ripple blanking input output controls and a la
246. e for a regular transistor however the value of Bp is much greater and the value of Vp is larger The emitter current is then Ig Bp 1 Bp DC voltages are Vg IpRg Vg Vet Veg Electronics Workbench BJT Array F3 2 AC Model F 4 The AC input signal is applied to the base of the Darlington transistor through capacitor C with the ac output V obtained from the emitter through capacitor C5 The Darlington transis tor is replaced by an ac equivalent circuit made up of an input resistance r and an output cur rent source Bp p F 3 2 1 AC Input Impedance The AC input impedance looking into the transistor base is then V 5 7 BpRe b The AC input impedance looking into the circuit is Z Rell 7 BpRe F 3 2 2 AC Current Gain The AC circuit gain is as follows Rp BpRg AB DEB i POR BoR Rg BpRg BJT Array BJT arrays are collections of discrete transistors on a single die They can Q7A come in many variations based on their intended application The reasons enzorscm for using an array is that the devices are more closely matched than a ran dom group of discrete devices eliminating the need to sort them the noise characteristics are better and the space required on a PCB is smaller There are three types of BJT arrays e PNP transistor array e NPN PNP transistor array e NPN transistor array Multisim User Guide F 9 SJO SISUBJ Transistors Transistors Compon
247. e function generator Setting the OFFSET equal to the AMPLITUDE setting will refer ence the input to ground 0V In this case the output is always positive When output is high area is continually added Output will rise indefinitely Multisim User Guide L 11 O1U0D Controls Controls Components Changing frequency changes the area Therefore in the case of lower frequencies output rises faster Function Generator Frequency Duty cycle Amplitude v E Offset Common s s Dscilloscope Time base 0 05 s div 8 Xposition 0 00 Channel A Ypostion o o0 E Jaci j oc e L 6 2 Characteristic Equation VO Kf Vic V po at va L 12 Electronics Workbench Voltage Hysteresis Block L 6 3 Voltage Integrator Parameters and Defaults Symbol Parameter Name Default Unit Vloff Input offset voltage 0 V K Gain 1 VN VI Output voltage lower limit 1e 12 V Vu Output voltage upper limit 1e 12 V Vs Upper and lower smoothing range 1e 06 V VOic Output initial conditions 0 V L 7 Voltage Hysteresis Block A1 This component is a simple buffer stage that provides hysteresis of the output with respect to the input ViL and ViH specify the center voltage or current inputs about which the hysteresis effect operates The output values are lim ov VIV ited to VoL and VoH The hysteresis value H is added to ViL and ViH in order to specify the
248. e is useful for debugging the design The current time scale T1 time value T2 time value and delta time value can be displayed by holding the mouse cursor over the timeline for a few seconds To modify the time scale open the Time Scale screen and enter a value in the Time Div box You can use any standard time unit such as ns for nano seconds ps for pico seconds etc i e 12000 3ns The OK button closes the screen and causes the Data Analyzer to use the selected time scale The Cancel button closes the screen and does not affect the Data Analyzer To invoke the pop up menu right click on any part of the time point display area the gray area just above the Waveform Display window Snap to Edges When setting the T1 and T2 timing markers for the Data Analyzer they will snap to the near est edge if Analyzer Timepoint Snap to Edges is active When setting a timing marker you can hold down the SHIFT key to temporarily toggle the Snap to Edges selection to its opposite effect Such as if Snap to Edges is not selected you can have the timing marker snap to the nearest edge when you set it by holding down the SHIFT key as you click using the left or right mouse button with the mouse indicator arrow in the Waveform Display window To invoke the pop up menu right click on any part of the time point display area the gray area just above the Waveform Display window Add Bookmark Enables you to place a virtual marker fo
249. e module and single step ping is resumed There are four types of breakpoints Break at Simulation Time Allows you to specify a simulation time and stops the logic simulation before the specified time is simulated To specify a stop time select Break at Simulation Time in the Type box and enter the stop time in the Timepoint box Then click Add Break at Location Stops logic simulation before the selected source line is simulated To select a breakpoint location you can use the Toggle Breakpoint button on the toolbar or you can use the Break points screen To use the Toggle Breakpoint button first open a source file window by sin gle stepping with the SSE or use File Open or the Open button on the toolbar to open the source file window Next put the mouse cursor on an HDL source line you want to stop at Then click the Toggle Breakpoint button on the toolbar to set the breakpoint A red stop sign symbol will be placed to the left of the line next to the line number You can also see that the breakpoint has been set in the Breakpoints screen Break in Module Instance Allows you to select a module instance and then stop logic simulation each time a source line in the selected module instance is to be simulated To select a breakpoint location use the Explorer window to highlight the module instance you want to select In the Breakpoints screen select Break in Module Instance for the Type box The name of the module instance th
250. e selected text onto the Clipboard delete it or perform other editing actions B 3 3 7 Edit Find Searches for characters or words in a document You can match uppercase and lowercase letters and search forward or backward from the insertion point B 3 3 8 Edit Find Next Repeats the last search without opening the Find screen B 3 3 9 Edit Replace Replaces one string with another B 3 6 Electronics Workbench View Menu B 3 3 10Edit Goto Line Goes to the source line number that was specified B 3 4 View Menu The View menu provides the following commands View Zoom e View Main Toolbar e View Status Bar B 3 4 1 View Zoom The View menu has Zoom selections for the Data Analyzer window A check mark appears next to the menu item that is used These zoom selections are also buttons on the toolbar B 3 4 1 1Zoom all Displays the entire simulation time range B 3 4 1 2Zoom out Zooms out by a factor of two B 3 4 1 3Zoom in Zooms in by a factor of two B 3 4 1 4Zoom markers Zooms in between the T1 and T2 timing markers if they are displayed B 3 4 2 View Main Toolbar A check mark appears next to the Main toolbar when it is displayed Multisim User Guide B 3 7 snus 111 SOS Silos II Menus Silos III Menus Many of the selections for pull down menus can also be accessed by clicking on buttons on the Main toolbar To obtain a text message of each button s function place the mouse curso
251. e triggered P 5 18 74xx116 Dual 4 bit latches clr This device contains two independent 4 bit latches Each 4 bit latch has an independent asyn chronous clear input and a gated two input enable circuit Multisim User Guide P 9 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series 4 bit latch truth table INPUTS ENABLE OUTPUT CLR C1 C2 DATA Q lo o 0 1 0 0 1 1 1 X 1 X Hold 1 1 X X Hold 0 X X X 0 P 5 19 74xx12 Tri 3 In NAND OC This device contains three independent 3 input NAND gates For correct performance the open collector outputs require pull up resistors Logic function Y ABC NAND gate truth table Hononono HH Boonnosoco u HD pmnb bn oooo n oO HHHHHrHH K P 10 Electronics Workbench 74XX P 5 20 74xx125 Quad bus BUFFER w 3 state Out This device contains four independent BUFFER non inverting gates with 3 state outputs BUFFER gate truth table x OF PI Ho Oo A NF ol K Z high impedance The output of the bus buffer is disabled when G is high P 5 21 74xx126 Quad bus BUFFER w 3 state Out This device contains four independent BUFFER non inverting gates with 3 state outputs BUFFER gate truth table A G X 1 1 1 0 1 0 X 0 Z Z high impedance The output of the bus buffer is disabled when G is low P 5 22 74xx132 Quad 2 In NAND Schmitt NAND gate truth table A B Y 1 1 0 0 X 1 X 0 1 Multisim User Guide P
252. eError stop from the monitor system task or the SILOS III probe command the vari able prints a terse string indicating the stimulus name and column name violated e g monitor time ExpectedValueError To obtain all violations at a single time point probe iter ExpectedValueError To obtain time points for which there is at least one violation probe ExpectedValueError Note other variables may simultaneously be probed e g probe out ExpectedValueError When the Expected ValueError signal is displayed in the Data Analyzer value for the Expect edValueError signal is none when there is no violation and x when there is a violation The Scan T1 Right and the Scan T1 Left buttons on the Analyzer Toolbar can be used to scan to expected value violations If the Expected ValueError signal shows a series of contig uous none values then the rising and falling edge of the strobe signal may be coincident with the changes for the expected value signal in the stimulustable For example the rising and falling edge of the strobe signal strobe1 does not coincide with expected output signal outl in the next example The below example shows how to use the ExpectedValueError variable with monitor Icon ext stim title example with monitor timescale 1ns 100ps module test reg 7 0 ini in2 1 0 wire 7 0 outi inl in2 0 reg strobel initial strobel 0 always Goutl begin 480 1 strobel 1 440 1 strobel 0 e
253. ear Source C 20 large or very small value especially for large input values Therefore keep in mind that this source does not inherently provide a limiting capability In order to reduce the potential for non convergence of simulations the PWL controlled source provides for smoothing around the co ordinate pairs If input smoothing domain ISD is set to say 10 the simulator assumes a smoothing radius about each co ordinate point equal to 1046 of the length of the smaller of the segments above and below each co ordinate point Piecewise Linear Source C 20 1 The Component The signal output of this component can be either a current source or a voltage source This source allows you to control the shape of the waveform by entering time and voltage cur rent pairs of values Each pair of values specifies the value of the source at the specified time At intermediate values of time the value of the source is determined by linear interpolation The component has two terminals and behaves as a current or voltage source when connected in a circuit It reads a specified file which contains a table of time and current voltage points Using the data in the table the component generates a current voltage waveform specified by the input text file To use the PWL source 1 Drag PWL Source from the Sources toolbar to the circuit window 2 Double click the component 3 Select the file containing the voltage current and time points from
254. eceives another trigger Electronics Workbench Silicon Controlled Rectifier E 7 1 Model The SCR is simulated using a mixed electrical and behavioral model The status of the SCR is handled with a logical variable much like the Shockley diode and diac simulations The resistance R acts as a current block when the SCR is switched off R has two separate values depending on the status of the SCR When the SCR is on the resis tance R is low when the SCR is off the resistance R is high The high resistance value acts as a current block The SCR is switched on and R set low 1e 06 if Vd 2 Vdrm Or Ig 2 Igt at Vg gt Vgt and vd o or dVa dV dt dt ofthe SCR The SCR is switched off and R set high if Id Ih In this case the switching occurs after turn off time T which is implemented by the behav ioral controller la current through the SCR in amperes fs E blocking resistance in ohms Symbols used in these equations are defined in SCR Parameters and Defaults E 7 2 Time Domain Model For the time domain model the charge storage effects of the SCR junction capacitance are considered in the simulation Multisim User Guide E 13 sepoig Diodes Diodes Components The turn off time T is implemented by introducing a behavioral delay in the opening of the controlled switch E 7 3 AC Small Signal Model In the AC model the diode is represented by its linearized small signal model
255. ecting Project Load Reload Input Files or the Go button The simulation history is stored on disk in the file named project name sim and the simula tion state is stored on disk in the file named project name cmm The project name cmm file will be slightly larger than the size of you SILOS III simulation in RAM memory B 3 5 8 Project Project Settings Allows you to set the command line options and other options for SILOS III For these set tings to take effect you must click on the Load Reload Input Files button or choose Project Load Reload Input Files Available options for the Project Settings screen are Analyzer Symbol Table File This specifies a file that substitutes text strings for state val ues for vectors displayed in the Data Analyzer The text strings can be symbols for a state machine making the state machine much easier to debug For an example see Displaying Multisim User Guide B 3 11 snus 111 SOS Silos Ill Menus Silos III Menus B 3 12 Vectors Using Symbolic Names Auto File Save Enabling this feature will cause SILOS III to automatically save any source file you have modified whenever you click on the Load Reload Input Files button on the Main toolbar or choose Project Load Reload Input Files Command Line Arguments You can use Verilog style command line arguments for SILOS III The command line arguments can be entered from the Command Line Argu ments box in the Project Settings screen
256. ectrode is placed Chemical action causes electrons to flow between the electrode and the container and this creates a potential difference between the electrode and the material of the container Batteries can be rechargeable and can be built to deliver extremely high currents for long peri ods The automobile ignition battery is an application of a battery as a current source the voltage may vary considerably under use with no visible battery deterioration Batteries may be used as voltage references their voltage remaining stable and predictable to many figures of accuracy for many years The standard cell is such an application A standard cell is a voltage source and it is important that current is not drawn from the standard cell Electronics Workbench VCC Voltage Source C 3 2 C 4 C 5 C 6 Battery Component This source can be adjusted from uV to kV but the value must be greater than zero Tip The battery in Multisim has no resistance If you want to use a battery in parallel with another battery or a switch insert a 1 mW resistor in series with it Battery tolerance is by default set to the global tolerance defined in the Analysis Monte Carlo dialog box To set the tolerance explicitly de select Use global tolerance and enter a value in the voltage tolerance field VCC Voltage Source VEG The VCC Voltage Source is used to connect power to the digital components T o which do not have an explicit powe
257. ecture CONTROL A of CONTROL Is constant FRAMESIZE integer 253243 constant TESTADDR integer 253000 signal ENDFR std ulogic Signal INCAD std ulogic signal VS std ulogic Signal Sync integer range 0 to 127 type states is StateLive StateWait StateSample StateDisplay Signal current state next state states Begin Address counter This counter increments until we reach the end of the frame address 253243 or until the input INCAD goes low ADDRCTR process Clk variable cnt integer range 0 to FRAMESIZE begin if rising edge Clk then if TestLoad 1 then cnt TESTADDR ENDFR lt 0 else if INCAD 0 or cnt FRAMESIZE then ent ser 0 else cnt 4 ont vy end if if cnt FRAMESIZE then ENDFR lt 1 else ENDFR lt 0 end if A 28 Electronics Workbench Examples Gallery end if end if Addr cnt end process Vertical sync detector Here we look for 128 bits of zero indicates the vertical sync blanking interval SYNCCTR process Reset Clk begin if Reset 1 then Sync 0 elsif rising edge Clk then if Data 00000000 or Sync 127 then Sync 0 else Sync lt Sync 1 end 1f end if end process VS lt 1 when Sync 127 else 0 State register process STREG process Reset Cl1k begin if Reset 1 then current state lt StateLive elsif rising edge Clk then current state next state end if end process
258. ed in a command file by enclosing the command with double quotes silos command i e control sav 2 k file name This option saves the text that has been entered from standard input to a file 1 file name This option writes the standard output from SILOS III to a log file An exit or quit command must be encountered for SILOS III to terminate la This option appends the standard output from SILOS III to a log file instead of over writing the log file and also to standard output This option must appear before the 1 fn option r save file name This option restores SILOS III to the last saved simulation state from a previous SILOS III save command s This option causes SILOS III to enter the interactive mode after executing any com mands that have been input to SILOS III u This option converts every name to upper case v file name This option specifies a library file name w Specifying w means that SILOS III will not display any warning messages y directory path This option specifies a directory of library files libext textensionl extension2 This option names the file name extensions for library files in the directory specified by the y option An example of specifying the library path and extension would be y c silos3 examples library libext v libnonamehide This option causes SILOS III to read in the module and UDP defi nition names as they are written in the file without appending ch
259. edural assignment changes the state of a register i e sequential logic whereas the continuous statement is used to model combinational logic Continuous assignments drive wire variables and are evaluated and updated whenever an input operand changes value It is important to understand and remember the difference Electronics Workbench The Verilog Language We place all three modules in a file and run the simulator to produce the following output Time 0 a 0 b 0 outl 1 out2 0 Time 1 a 1 b 0 outl 1 out2 0 Time 2 a 1 b 1 out1 0 out2 1 Time 3 a 0 b 1 outl 1 out2 0 Since the simulator ran out of events I didn t need to explicitly stop the simulation B 1 2 4 Data Types B 1 2 4 1 Physical Data Types Since the purpose of Verilog HDL is to model digital hardware the primary data types are for modeling registers reg and wires wire The reg variables store the last value that was procedurally assigned to them whereas the wire variables represent physical connections between structural entities such as gates A wire does not store a value A wire variable is really only a label on a wire Note that the wire data type is only one of several net data types in Verilog HDL which include wired and wand wired or wor and tristate bus tri This Primer is restricted to only the wire data type The reg and wire data objects may have the following possible values 0 logical zero or false 1 logical one or true x unkno
260. ee the example on the next page and see project fltsim spj fault simulation example in the examples subdirectory for the installation For the below example and diagram if the SDF file contained the following instance name INSTANCE name2 name4 DELAY ABSOLUTE IOPATH INO OUT 2420 2420 2420 2420 2420 2420 then the sdf annotate system task to specify the SDF file and its relative position in the design s hierarchy would be module testbench initial sdf annotate filename sdf testbench namel When SILOS III reads file filename sdf to update the design the path testbench namel is concatenated with path name2 name4 to form path testbench namel name2 name4 Sig nals INO and OUT are then updated as specified in the above example Electronics Workbench Verilog HDL Extensions Diagram of the Design Hierarchy for the SDF Example module testbench design name1 ports mod1 name2 ports mod2 name3 ports mod2 name4 INO OUT mod1 name5 ports SDF file is updating this instance Top level of design B 2 1 3 Expected Values and Stimulustable The IEEE Verilog specification does not describe any syntax for tabular representation of input data nor expected value information The stimulustable statement is a SILOS III enhancement which provides tabular format for input data The stimulustable statement also can combine expected value information with the tabular format for input data B
261. eee P 16 74xx148 8 to 3 Priority EnC 22222 nennen nn P 16 74xx15 3 3 Input AND 22 22 mie eie ea aga ea ea a eE P 17 74xx150 1 of 16 Data Sel MUX 0 0 00 ce eee P 17 74xx151 1 of 8 Data Sel MUX 2 2 0000 eee P 18 74xx152 Data Sel MUX nananana anaa P 18 74xx153 Dual 4 to 1 Data Sel MUX 00000 c eee eee P 19 74xx154 4 to 16 Dec DEMUX 00000 eee P 19 74xx155 Dual 2 to 4 Dec DEMUX 0000 eee P 20 74xx156 Dual 2 t0 4 Dec DEMUX OC 00 002 eee eee P 21 74xx157 Quad 2 to 1 Data Sel MUX 000000 cee eee P 21 74xx158 Quad 2 to 1 Data Sel MUX 0 0000 onen P 21 74xx159 4 to 16 Dec DEMUX OC 00 0000 eee P 22 74xx16 Hex INVERTER OC ococcocccccc eee P 23 74xx160 Sync 4 bit Decade Counter cIr 2222er san P 23 74xx161 Sync 4 bit Bin Counter 2 000000 P 24 74xx162 Sync 4 bit Decade Counter 00 00 cee eee P 25 74xx163 Sync 4 bit Binary Counter 2222022 P 25 74xx164 8 bit Parallel Out Serial Shift Reg oo oooo P 26 74xx165 Parallel load 8 bit Shift Reg o ooooocooocoommo P 27 74xx166 Parallel load 8 bit Shift Reg o ooocooccoommo P 27 74xx169 Sync 4 bit up down Binary Counter issues P 28 74xx17 Hex BUFFER OC ooccoccocccocc eee P 28 74xx173 4 bit D type Reg w 3 state Out 2222er nennen P 29 74xx174 H
262. ef silos sim lerrors endif Commands are executed immediately upon being encountered in the data Therefore the order in which the commands are placed may be important e g PREP before SIM You should use the include compiler directive when inputting a file from another file In the previous example remove the SILOS III commands from the file test v and put them in file testl v shown below with an include compiler directive to include file test v for addi tional information see include in the Verilog HDL Reference on line help file File testl v include test v ifdef silos sim 200 lerrors endif B 2 2 28 2Command line Options You can use Verilog style command line arguments for SILOS III The command line argu ments can be entered from the Command Line Arguments box in the Project Settings dialog box see B 3 5 8 Project Project Settings or from the command line if you are running a batch simulation Available command line arguments are e c This option compiles the source files and then exits f file name This option instructs SILOS III to get the command line arguments from a file SILOS III has the ability to nest the command files For example command file logicsim silos f logicsim could contain the name of another com mand file logicsim1 that has additional command line arguments Electronics Workbench Silos III Command Line Usage SILOS style commands can be enter
263. efinitions for standard signed and unsigned arithmetic data types along with arithmetic shift and type conversion operations for those types A 1 2 2 IEEE Standard 1076 4 VITAL The annotation of timing information to a simulation model is an important aspect of accurate digital simulation The VHDL 1076 standard describes a variety of language features that can Electronics Workbench Learning VHDL A 2 A 2 1 be used for timing annotation however it does not describe a standard method for expressing timing data outside of the timing model itself The ability to separate the behavioral description of a simulation model from the timing spec ifications is important for many reasons One of the major strengths of Verilog HDL is the fact that it includes a feature specifically intended for timing annotation This feature the Standard Delay Format SDF allows timing data to be expressed in a tabular form and included into the Verilog timing model at the time of simulation The IEEE 1076 4 standard published by the IEEE in late 1995 adds this capability to VHDL as a standard package A primary impetus behind this standard effort which was dubbed VITAL for VHDL Initiative Toward ASIC Libraries was to make it easier for ASIC vendors and others to generate timing models applicable to both VHDL and Verilog HDL For this rea son the underlying data formats of IEEE 1076 4 and Verilog s SDF are quite similar Learning VHDL This
264. ent When the SSE is exited the simulation history is lost unless Project Save Project State is selected before exiting Edit Menu The Edit menu provides the following commands Edit Undo Edit Cut Edit Copy e Edit Paste Edit Clear e Edit Select All Edit Find Edit Find Next Edit Replace e Edit Goto Line Edit Undo Undoes your last editing or formatting action including cut and paste actions If an action cannot be undone Undo appears dimmed on the Edit menu Edit Cut Deletes text from a document and places it onto the Clipboard replacing the previous Clip board contents Edit Copy Copies text from a document onto the Clipboard leaving the original intact and replacing the previous Clipboard contents When the Data Analyzer window has the focus Edit Copy cop ies the Data Analyzer window signal names scope values and waveforms so it can be pasted into Microsoft Word Multisim User Guide B 3 5 snus 111 SOS Silos II Menus Silos III Menus B 3 3 4 Edit Paste Pastes a copy of the Clipboard contents at the insertion point or replaces selected text in a document B 3 3 5 Edit Clear Deletes selected text from a document but does not place the text onto the Clipboard Use Clear when you want to delete text from the current document but you have text on the Clipboard that you want to keep B 3 3 6 Edit Select All Selects all the text in a document at once You can copy th
265. ents F 4 1 F 4 2 F 4 3 F 5 F 10 General purpose PNP Transistor Array This general purpose silicon PNP transistor array incorporates two transistors a Darlington circuit and a current mirror pair with a shared diode The two transistors can be used in circuit applications The total array can be used in applica tions in systems with low power and low frequency requirements NPN PNP Transistor Array This general purpose high voltage silicon transistor array consists of five independent transis tors two PNP and three NPN types on a common substrate which has a separate connection Separate connection for each transistor permits greater flexibility in circuit design This array is useful in applications including differential amplifiers DC amplifiers level shif tors timers thyristor firing circuits and operational amplifiers General purpose High current NPN Transistor Array This array consists of five high current NPN transistors on a common monolithic substrate Two of these transistors are matched at low currents for applications in which offset parame ters are particularly important Independent connections for each transistor and a separate ter minal for the substrate allow for maximum flexibility in circuit design This array is useful in applications such as signal processing and switching systems operating from DC to VHF Other applications include lamp and relay driver differential amplifier thy r
266. erating point The transistors parameters are based on the Gummel Poon tran sistor model BJTs are commonly used in amplification and switching applications They come in two ver sions NPN and PNP The letters refer to the polarities positive or negative of the materials that make up the transistor sandwich For both NPNs and PNPs the terminal with the arrow head represents the emitter An NPN transistor has two n regions collector and emitter separated by a p region base The terminal with the arrowhead is the emitter The ideal NPN in the parts bin has generic val ues suitable for most circuits You can specify a real world transistor by double clicking the icon and choosing another model A PNP transistor has two p regions collector and emitter separated by an n region base The terminal with the arrowhead represents the emitter The ideal PNP model has generic val ues suitable for most circuits You can specify a real world transistor by double clicking the icon and choosing another model Multisim User Guide F 1 SJO SISUBA Transistors Transistors Components F 1 1 F 2 Characteristic Equations Ir Ic Ip I poc hre In AI Bac mE OP Vce hre where Boo hgg DC current gain Bac hj small signal current gain lc collector current lg base current Ale emitter current The model for the PNP transistor is the same as the NPN model except the polarities of the terminal currents a
267. erefore with the proper automated tools one can create a VLSI description of a design in Verilog in a few weeks Verilog also allows the designer to specific designs at the logical gate level using gate constructs and the transistor level using switch constructs B 1 2 The Verilog Language There is no attempt in this primer to describe the complete Verilog language It describes only the portions of the language needed to allow you to explore the architectural aspects of com puters In fact this primer covers only a small fraction of the language For the complete description of the Verilog HDL consult the references in the Multisim help files We begin our study of the Verilog language by looking at a simple Verilog program Looking at the assignment statements we notice that the language is very C like Comments have a C flavor i e they are shown by to the end of the line The Verilog language describes a digital system as a set of modules but here we have only a single module called simple B 1 2 1A First Verilog Program By Dan Hyde August 9 1995 A first digital model in Verilog module simple Simple Register Transfer Level RTL example to demo Verilog Register A is incremented by one Then first four bits of B is set to not of the last four bits of A C is the and reduction of the last two bits of A declare registers and flip flops reg 0 7 A B reg C The two initial s and
268. erentiator A1 This component calculates the derivative of the input voltage the transfer function s and delivers it to the output It is used in control systems and ana log computing applications didt TV Differentiation may be described as a rate of change function and defines the slope of a curve Rate of change dV dT L 5 1 Investigations L 5 1 1 Sine wave The slope of a sine wave changes continuously and smoothly Therefore the differentiator output should follow the sine shape In the example circuit shown below if you change frequency from 10Hz to 100Hz the rate of change of the waveform will increase by a factor of 10 The differentiator output will also increase by the same factor When investigating note also a 90 degree phase shift from input to output L 5 1 2 Triangle waveforms In an ideal triangle waveform the rising and falling slopes are constant with an abrupt change taking place at the peaks Since the rate of change slope during rise and fall are constant the differential result is also constant The reversal of slope at the peaks from rise to fall fall to rise produces a large instantaneous change in the differentiator output resulting in a square wave output In the example circuit as for the sine wave if you change frequency from 10Hz to 100Hz the rate of change of the waveform will increase by a factor of 10 The differentiator output will also increase by the same factor
269. ers 74BCT756 Octal buffers line drivers 74BCT8244 SCAN Test with Octal Buffer 74BCT8245 SCAN Test amp Octal Xscievers 74BCT29821 10bit Bus Interface FF 74BCT29822 10bit Bus Interface FF 74BCT29823 9bit Bus Interface FF 74BCT29824 9bit Bus Interface FF 74BCT29841 10bit Bus D Latches 74BCT29842 10bit Bus D Latches Multisim User Guide B 2 75 suoisuejx3 JAH Bojan Verilog HDL Extensions Extensions B 2 76 Electronics Workbench snus 111 SOIS Appendix B 3 Silos Ill Menus B 3 T Menus OVerVIe WE 3 o v eum c PS nal CR EAS ee Nadine s B3 1 B 3 1H Men Bald edm e en test dor pad ac B3 1 B 3 1 2P0P Up Menus as PER Pea PRE Peeks eh wires B3 2 B 3 1 3Screen Conventions zerr era e a i A A eee an B3 2 B 3 2 Flle Menu fhe e acr Ed bee Ae en ee db Pe X ue Y ed B3 2 B 3 2 MFile New Ar a a ett eie ae ehe toe tt eerie Gr t es B3 2 B 3 2 2File Open ss bu Une PSU a RE GUNT E RAPERE E die B3 3 B 3 2 3File S8VO s ed entes bean tees oat te odd vrai so Nr oa B3 3 B 3 24File Save AS vo 3 pe ta a cR E Ab UA B3 3 B 3 2 5File Prinit ra ass i rece De vr cel ge AE RAE a LU IUS B3 3 B 3 2 6File Print Preview eee RR RIRRRRRRR RII B3 4 B 3 2 7File Print Setup 0 0 eee B3 4 B 3 2 9File EXIE A a e A d Pe xo AE nee B3 5 B 3 3 Edit Menu A ES A RE A EN B3 5 B 3 3 M EdiUUndO ici A EAS adr ae AA aed op B3 5 B 9 3 2EGIUG U
270. es and are used in conjunction with the time system func tion Arrays of integer and time variables but not reals are allowed Multiple dimensional arrays are not allowed in Verilog HDL Some examples integer Count simple signed 32 bit integer integer K 1 64 an array of 64 integers time Start Stop Two 64 bit time variables Electronics Workbench The Verilog Language B 1 2 5 Operators B 1 2 5 1 Binary Arithmetic Operators Binary arithmetic operators operate on two operands Register and net wire operands are treated as unsigned However real and integer operands may be signed If any bit of an oper and is unknown x then the result is unknown Operator Name Comments Addition u Subtraction Multiplication Division Divide by zero produces an x i e unknown Modulus B 1 2 5 2 Unary Arithmetic Operators Operator Name Comments Unary Minus Changes sign of its operand B 1 2 5 3 Relational Operators Relational operators compare two operands and return a logical value i e TRUE 1 or FALSE 0 If any bit is unknown the relation is ambiguous and the result is unknown Operator Name Comments E Greater than gt Greater than or equal lt Less than Less than or equal Logical equality Logical inequality lt B 1 2 5 4 Logical Operators Logical operators operate on logical operands and return a logical value i e TRUE 1 or FALSE 0 Used typically in if and while
271. es in Group list box You can also select more than one library file by clicking on a file name to highlight it and then hold down the SHIFT key or the CTRL key while clicking on additional file names To specify a directory of library files whose file name extensions end in v enter the directory name followed by v in the File Name box and click Add An example for specifying all the files ending with v for directory library would be library v To specify PLI library files click on the drop down arrow in the File Group list box in the Project Files screen and select PLI Library Files Double click on PLI library file names in the list box to add them to the Files in Group list box as PLI library file names To actually input the files for a project use Project Load Reload Input Files or the Load Reload Input Files button on the toolbar B 3 5 4 Project Save As Saves the project to the project name that you specify It does not save the simulation history for the Data Analyzer The Save As feature can be used to easily clone projects for testing pur poses without having to modify the original project B 3 5 5 Project Close Closes a project All child processes such as the Output window and the Data Analyzer win dow are also closed B 3 10 Electronics Workbench Project Menu B 3 5 6 Project Save Project State Saves the simulation results and the current state of the simulator to dis
272. ese conventions will be looked at below Using a Process The first design description to be looked at for this shifter is a description that uses a VHDL process statement to describe the behavior of the entire circuit over time This is the behav ioral level of abstraction It represents the highest level of abstraction practical and synthesiz able for registered circuits such as this one The VHDL source code for the barrel shifter is shown below Multisim User Guide A 13 JOWUd TAHA VDHL Prrimer VHDL Primer Eight bit barrel shifter library ieee use ieee std logic 1164 all entity rotate is port Clk Rst Load in std ulogic Data in std ulogic vector 0 to 7 Q out std ulogic vector 0 to 7 end rotate architecture rotatel of rotate is begin reg process Rst Clk variable Qreg std ulogic vector 0 to 7 begin if Rst 1 then Async reset Oreg 00000000 elsif Clk 1 and Clk event then if Load 1 then Qreg Data else Qreg Qreg 1 to 7 amp Qreg 0 end if end if Q lt Qreg end process end rotatel Reading from the top of the source file you can see the following acomment field as described previously library and use statements allowing us to use the IEEE 1164 standard logic data types anentity declaration defining the interface to the circuit Note that the direction mode of Q is written as out indicating that it will not be used d
273. esented ear lier The same if then elsif structure used in the process is used to describe the behavior of the registers Instead of a sensitivity list however the procedure has a parameter list describing the inputs and outputs of the procedure The parameters defined within a procedure or function definition are called its formal param eters When the procedure or function is executed in simulation the formal parameters are replaced by the values of the actual parameters specified when the procedure or function is used If the actual parameters being passed into the procedure or function are signal objects then the signal keyword can be used as shown above to ensure that all information about the signal object including its value and all of its attributes is passed into the procedure or func tion A 2 6 6 Structural VHDL The structure level of abstraction is used to combine multiple components to form a larger cir cuit or system As such structure can be used to help manage a large and complex design and structure can make it possible to reuse components of a system in other design projects Because structure only defines the interconnections between components it cannot be used to completely describe the function of a circuit at some level all aspects of your circuit must be described using behavioral and or dataflow levels of abstraction To demonstrate how the structure level of abstraction can be used to connect lower level c
274. esistance value is dependent on the buzzer s rated voltage and the current It beeps when the voltage across its terminals exceeds its voltage rating V 4ted V rated Buzzer resistance F irated Beeps when Vab gt Vrated Multisim User Guide J 7 SJO eoIpu Indicators Indicators Components J 8 Electronics Workbench Appendix K Misc Components K 1 K 2 K 3 K 4 K 5 K 6 K 7 K 8 K 9 K 10 K 12 Crystal tte ract rte ed as pap EUNT UM sif deg a cra cosa a due K 1 DEMO ux rete Ya met epe e etri and qoe ce tete eR RENE an x e May K 2 K 2 1 Characteristic Equations llsseelels ee K 3 K 2 2 DC Motor Parameters and Defaults llli liliis K 4 Optoco pler 2 2 22 55 Me nen Lo deo EU o M e eM K 4 Vacuum T be isse hb lxv Av P eeepc ie teu K 4 K 4 1 Characteristic Equations oooooocooccooocrcrr ee K 5 K 4 2 Model uot ER DE ILIA Li ERES E dub tau Ec d RU ERES K 5 K 4 3 Triode Vacuum Tube Parameters and DefaultS oo o o ooo o K 6 Voltage Reference pesisiereispes i ESE eee K 6 Voltage Regulator ooooooococcocro ne K 7 K 6 1 Input Output Voltage Differential Rating liliis K 7 K 6 2 DC Output Voltage 2 rr K 8 Voltage Suppressor coccoccoco rr K 8 Boost Converler it ede eoa date ae aaa stad seed Wat K 8 K 8 1 Characteristic Equations 0 000 tae K 9 K 8 2 Boost Converter Parameters and Defaults oooooccoocoooo K 1
275. esistive circuit carrying electric current is in the form of heat Cir cuits dissipating excessive energy will literally burn up Practical circuits must take power capacity into account About Resistance Ohm s law states that current flow depends on circuit resistance I E R Circuit resistance can be calculated from the current flow and the voltage R El Circuit resistance can be increased by connecting resistors in series Rz RI R2 Rn Circuit resistance can be reduced by placing one resistor in parallel with another RI R2 R3 Multisim User Guide D 3 oiseg Basic Basic Components D 3 3 Characteristic Equation The current through the resistor uses the model i V V2 R where i current V4 voltage at node 1 Vo voltage at node 2 R resistance D 3 4 Resistor Virtual This component functions in the same way as a resistor but has a user settable R2 Ran value 1kOhm D 4 Capacitor gt A capacitor stores electrical energy in the form of an electrostatic field Capacitors He are widely used to filter or remove AC signals from a variety of circuits In a DC cir cuit they can be used to block the flow of direct current while allowing AC signals to pass 1 0F A capacitor s capacity to store energy is called its capacitance C which is measured in far ads It can have any value from pF to mF Capacitor tolerance is by default set to the global tolerance defined i
276. ession specified as parameters to the task The parameters are specified in exactly the same manner as the display system task When you invoke the monitor task the simulator sets up a mechanism whereby each time a variable or an expression in the parameter list changes value with the exception of time the entire parameter list is dis played at the end of the time step as if reported by the display task If two or more param eters change values at the same time however only one display is produced For example the following will display a line anytime one of the registers A B or C changes monitor 0d b b b time A B C B 1 24 Electronics Workbench System Tasks and Functions Only one monitor statement may be active at any one time The monitoring may be turned off and on by the following Smonitoroff lt some code gt Smonitoron B 1 3 5 scope The scope system task lets the user assign a particular level of hierarchy as the interactive scope for identifying objects scope is useful during debugging as the user may change the scope to inspect the values of variables in different modules tasks and functions scope name The lt name gt parameter must be the complete hierarchical name of a module task function or named block See B 1 3 7 showscopes on page B 1 25 to display the names B 1 3 6 settrace The settrace system task enables tracing of simulation activity The trace consists
277. est bench reads lines from an ASCII file and applies the data contained in each line as a test vector to stimulate and test the Fibonacci circuit Test bench for Fibonacci sequence generator library ieee use ieee std logic 1164 all use std textio all Use the text I O features of the standard library Electronics Workbench Examples Gallery use work fib Get the design out of library work entity testfib is Entity once again we have no ports end testfib architecture stimulus of testfib is component fib Create one instance of the fib design unit port Clk Clr in std ulogic Load in std ulogioc Data in in std ulogic vector 15 downto 0 S out std ulogic vector 15 downto 0 end component The following conversion functions are used to process the test data and convert from string data to array data function str2vec str string return std ulogic vector is variable vtmp std ulogic vector str range begin for i in str range loop if str i 1 then vtmp i 1 elsif str i 0 then vtmp 1 0 else vtmp i X end if end loop return vtmp end function vec2str vec std ulogic vector return string is variable stmp string vec left 1 downto 1 begin for i in vec reverse range loop if vec i 1 then stmp i 1 174 elsif vec i 0 then stmp i 1 0 else stmp i 1 X end 1f end loop return stmp end Multisim User
278. ex D type FF cl sls P 29 74xx175 Quad D type FF clr l i P 30 74xx180 9 bit Odd even Par GEN a nn naana aaae P 30 74xx181 Alu Function Generator 0 0000 eee eee P 31 74xx182 Look ahead Carry GEN 0oococccccccoc eee P 31 74xx190 Sync BCD up down Counter 00 nennen P 33 74xx191 Sync 4 bit up down Counter 2 222220 P 33 74xx192 Sync BCD Up down Counter 00 0c eee eee P 34 74xx193 Sync 4 bit Bin Up down Counter 22222222 P 34 74xx194 4 bit Bidirect Univ Shift Reg 00 00 eae P 35 74xx195 4 bit Parallel Access Shift Reg 200 00 0 eu P 35 74xx198 8 bit Shift Reg shl shr ctil llis lesen P 36 74xx199 8 bit Shift Reg sh ld Ctrl ooooooooccocco oo P 37 Electronics Workbench P 5 68 P 5 69 P 5 70 P 5 71 P 5 72 P 5 73 P 5 74 P 5 75 P 5 76 P 5 77 P 5 78 P 5 79 P 5 80 P 5 81 P 5 82 P 5 83 P 5 84 P 5 85 P 5 86 P 5 87 P 5 88 P 5 89 P 5 90 P 5 91 P 5 92 P 5 93 P 5 94 P 5 95 P 5 96 P 5 97 P 5 98 P 5 99 P 5 100 P 5 101 P 5 102 P 5 103 P 5 104 P 5 105 P 5 106 P 5 107 P 5 108 P 5 109 74xx20 Dual 4 In NAND 000 00 c tees P 38 74xx21 Dual 4 In AND 2 0 2 0 00 eee P 38 74xx22 Dual 4 In NAND OC 000 00 cece eee P 38 74xx238 3 to 8 line Dec DEMUX 00000 ee eee P 39 74xx240 Octal BUFFER w 3 state Out 000 0c e eee P 39 74xx241 Oct
279. example if you do a zoom full then every change for the displayed signals is stored in mem ory If you then zoom in or zoom out for these signals the redraw time is much faster If you add additional signals to the Data Analyzer then the simulation data for the new signals has to be read from the simulation history save file on disk assigns the approximate limit of disk storage in bytes that the simulation save file can use When the disk storage limit is exceeded the simulation will terminate see note 1 Default DISK 100M Specifies that the maximum delay value will be used when parsing the netlist see note 2 Specifies that the minimum delay value will be used when parsing the netlist see note 2 B 2 31 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 32 EUMK NONCON MXDCI MXITR SAVCELL SAVSIM SAVISM 0 SAVISM 1 SAVISM 2 Defines the conductance for bi directional transistors and unidirectional transfer gates when there is an Unknown level on the enable on when EUNK 1 off when EUNK O0 or Unknown when EUNK See note 3 Default EUNK When nonconvergence is detected the default is for SILOS III to issue a warning message pick a possible solution if this is possible and continue simulation If the CONTROL NONCON command is entered before logic initialization begins then if nonconvergence is detected SILOS III will issue an error message and
280. eywords SILOS III has a reserved keyword silos that is always true The silos keyword allows the user to enclose Silos specific code or commands within a ifdef else endif compiler direc tive so that it will be available for SILOS III but not other Verilog simulators e g ifdef silos initial stopsave initial 1000000 resetstartsave endif When running the SSE the reserved keyword sse is always true so that the user can enclose code or commands that is specific to the GUI within a ifdef else endif compiler directive B 2 1 6 Extensions to Turn off Reset and Turn on Saving When running a simulation that creates a large save file the stopsave system task can be used to turn off saving to the save file This can be used to keep the save file size fixed during the portion of the simulation that is of no interest for the designer The Sresetstartsave system task can be used to reset the save file and then start saving the sim ulation history After the simulation is complete the simulation history that has been saved after resetting the save file will be available for display with the Data Analyzer The below example stops saving at time 0 and starts saving at time 1000000 ifdef silos initial S stopsave initial 1000000 resetstartsave endif B 2 1 7 SILOS Ill Extensions to Verilog HDL SILOS III has a switch to issue syntax errors for extensions to the IEEE P1364 Standard Ver
281. f P 5 12874xx47 BCD to seven segment dec The 7447 BCD Binary Coded Decimal to seven segment decoder translates a 4 bit BCD input into hexadecimal and outputs high on the output pins corresponding to the hexadecimal representation of the BCD input There are provisions for lamp testing and for blanking the outputs Multisim User Guide P 71 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 72 BCD to seven segment decoder truth table INPUTS OUTPUTS No LT RBI D c B A BEZ a b c d e f g RBO 0 1 1 707 A liebe Mae 2 a 0 1 1 X 0 0 0 1 1 0 1 1 0 0 0 0 2 1 2 2087 06 BS ala Ma A ee ud 3 1 x 0 0 1 i d x 4 1 4 Tai 87170 d ol LA 2 7 5 xlo 1 1 1 1 0 1 1 0 1 1 6 del i cio llo Oe dl Ck ci C 7 ds Dx pepe ANA Wee D 0 220 0 20 8 Tel eh 0 00 equum ES a E uu d 9 1 X 1 0 0 1 1 1 1 ao 0 1 1 10 1 X1 O 1 Of 1 0 0 O 1 1 0 4 I id cde DX Db 0b XS X 00 095 o Uh IX 0300 00 165 A N 12 1 X 1 1 0 0 1 0 1 0 0 0 1 1 lt V ee co Gd D nO a a x A 14 1 X 1 1 1 0 1 0 0 0 1 1 1 1 L 15 1 X1 1 1 lalo 0 O 0 O0 o 0 x BI X Xx x x x xlo o o o o o o o RBI 1 olo o o o ol lo o o o 0 o OQ LT X 1 1 1 1 1 BI active low blanking input RBI active low ripple blanking input LT active low lamp test input Notes 1 The blanking input BI must be open or held at a high logic level when output functions 0 through 15 are desired The ripple bl
282. f Clk was the signal triggering the process execution If the event that triggered the process execution was in fact a rising edge on Clk then the sim ulator will go on to check the remaining if then logic to determine which assignment state ment is to be executed If Load is determined to be 1 then the first assignment statement is executed and the data is loaded from input data to the registers If Load is not 1 then the data in the registers is shifted as specified using the bit slice and concatenation operations available in the language Note Every assignment to a variable or signal you make that is dependent on a Clk 1 and CIk event expression will result in at least one register when synthesized A 2 6 4 Signals and Variables There are two fundamental types of objects used to carry data from place to place in a VHDL design description signals and variables In virtually all cases you will want to use variables to carry data between sequential operations within processes procedures and functions and use signals to carry information between concurrent elements of your design such as between two independent processes Examples of signals and variables and differences between them are shown in more detail in A 4 Examples Gallery on page A 23 For now it is useful to think of signals as wires as in a schematic and variables as temporary storage areas similar to variables in a traditional software programmi
283. fines the operation of the diode taking into account its charge storage effects or capacitance There are two types of capacitances diffusion or storage capacitance and deple tion or junction capacitance The charge storage element Cp takes into account both of these as follows m dl V j T C 1 for Vy lt FC jo J dv Po C C dl 0 mV TT F for V 2 FC j dV F D 2 Po where Cio zero bias junction capacitance typically 0 1 to 10 picofarads Po junction potential typically 0 5 to 0 7 volts T transit time typically 1 nanosecond m junction grading coefficient typically 0 33 to 0 5 and where F and F are constants whose values are F gt 1 FC lem F3 1 FC 1 m Notes 3 The voltage drop across the diode varies depending on the set value of saturation current typically 10 14 amperes Is ohmic resistance typically 0 05 ohms fs 4 The parameter 7 is proportional to the reverse recovery time of the diode That is it affects the turn off or switching speed of the diode It is the time required for the minority carrier to cross the junction Multisim User Guide sepoig Diodes Diodes Components 5 The barrier potential for a diode is approximately 0 7 to 0 8 volts This is not to be con fused with the model parameter given above E 1 4 AC Small Signal Model The figure below shows the linearized small signal diode model in which the dio
284. finish is encountered in the design During simulation the Go button will change into a Stop button which can be clicked on to halt the simulation at any time The Go button can be useful during single stepping to skip across uninteresting source code to the next breakpoint at which point the single stepping can be resumed B 3 8 1 1Simulation Suggestions Libraries To increase the speed of processing your design use the library feature to specify large library files from vendors Any file of Verilog source code can be specified as a library file To spec ify library files see the File Menu SILOS III is very efficient in saving the simulation results to disk In general there is only a 10 to 1596 difference in speed between the saving every variable in the hierarchy and saving nothing However if the save file on disk becomes large enough over a few hundred mega bytes then the time spent writing to disk may be significant To reduce simulation save file size on disk you can select which parts of the hierarchy that you want to save the simulation results for To specify which instances to save information for during simulation choose Properties from the pop up menu for the left hand side of the Explorer window see Properties Restarting Simulation SILOS III has the ability to restart the simulation from any timepoint by using the save and restore feature see Project Save Project State and Project Restore Project State Us
285. for each counter The 74393 is ideal for circuits that require two independent counters The 74393 counts from 0 to 15 in binary on every positive transition low to high of the clock pulse P 62 Electronics Workbench 74XX Count sequence truth table OUTPUT COUNT QD QC QB QA 0 0 0 0 0 du 0 0 0 T 2 0 0 I 0 3 0 0 1 T 4 0 al 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 I3 1 T 0 I 14 1 T 1 0 15 1 1 1 1 P 5 11874xx395 4 bit Cascadable Shift Reg w 3 state Out This device is a 4 bit shift register with 3 state outputs It features parallel in and parallel out registers 4 bit shift register truth table C CLR LD SH CLK SER A B C D QA QB QC QD QD 0 x pe X X X X X X Z Z Z QD 1 0 X X X X X X X 0 0 0 0 0 1 1 1 1 X X X X X NO CHANGE 1 1 1 X A B C D 0A QB oc QD op 1 1 0 1 X X X X X NO CHANGE 1 1 0 1 X X X X 1 QA QB QC QC 1 1 0 0 X X X X 0 QA QB QC QC Multisim User Guide P 63 sanas Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 11974xx40 Dual 4 In NAND This device contains two independent 4 input NAND gate Logic function Y ABCD NAND gate truth table INPUTS OUTPUT A B C D Y 1 1 1 1 0 0 X X X 1 x 0 X X 1 X X 0 X 1 X X X 0 1 P 5 12074xx42 4 BCD to 10 Decimal Dec This BCD to decimal decoder consists of eight inverters and ten four input NAND gates P 64 Electronics Workbench 74XX
286. formulas are provided in the following description The DC characteristics are modeled by a nonlinear current source Ip Forward characteristics Vps gt Vre Vro y Jo Vss Yo fory gt 0 p gt 0 0 for Vas VE lt 0 Ty BW Vrg A AV for 0 lt Vas Vre S Vps BD Vre Vos AV for 0 lt Vps lt Vos Vre Reverse characteristics Vps lt 0 VTE Vro v 4o Vsp Jo 0 for V Vre lt 0 Ip BVs Vr 1 AV for0 lt Von Vre Vos B Vps 2 Vop Vig V5 1 AV5 forO lt Vps Ven Vre where a channel length modulation measured in volts Vie threshold voltage in volts Vio zero bias threshold voltage in volts Y bulk threshold parameter in volts j surface potential at strong inversion in volts Vas bulk to source voltage in volts F 12 Electronics Workbench MOSFET Vep bulk drain voltage in volts Vos drain to source voltage in volts F 5 4 Time Domain Model The time domain model takes into account the charge storage effects of the junction diodes used to model MOSFETs The diodes are modeled using the diode time domain model described in the Diodes Parts Bin chapter F 5 5 AC Small Signal Model In the linearized small signal model the junction diodes used to model the MOSFETs are replaced by their equivalent small signal models Cop Cos Cap are zero bias junction capacitances dl _ dl ys Em dV Lak 8 ps dV lo dl dl ps ay len 800
287. four synchronous parallel data inputs PO to P3 four synchronous mode control inputs parallel enable PB count enable parallel CEP and count enable trickle CET and syn chronous reset SR buffered outputs from all four bit positions OO to O3 and a terminal count output TC O 2 16 40163 4 bit Bin Counter Spe pepe buo i O 10 CET PE SR cP 00 01 02 03 lal al a The 40163 device is a fully synchronous edge triggered 4 bit binary counter with a clock input CP four synchronous parallel data inputs PO to P3 four synchronous mode control inputs parallel enable PB count enable parallel CEP and count enable trickle CET and syn chronous reset SR buffered outputs from all four bit positions OO to O3 and a terminal count output TC Electronics Workbench 4000 Series ICs O 2 17 4017 5 stage Johnson Counter OPCPEN MR Qo a1 Q2 Q3 Q4 35 Qe 97 s Qs COUT sl sl el 0 ol lal l 2 ol o nis The 4017 device is a 5 stage Johnson decade counter with ten spike free decoded active HIGH outputs Oy to O an active LOW output from the most significant flip flop Os 9 active HIGH and active LOW clock inputs CP CP and an overriding asynchronous master reset input MR 5 stage Johnson counter truth table MR CPO CP1 OPERATION y X 0 al 0 0 0 0 X 0 1 0 n Multisim User Guide X PeM oO o
288. frequency A third stage may be introduced by specifying the location of a second pole in hertz Cc compensation capacitance which shifts the dominant pole to the left in the fre quency response Its value is typically 30 40 picofarads SR slew rate which is the rate of change of output voltage in V s in response to a step input G 1 4 2 L2 Simulation Model This is a more complex simulation model and is equivalent to the Five Terminal Opamp model of EWB Version 5 The base L2 model is a differential input single output model based on the Boyle Cohn Pederson macro model which includes the supply voltage connections This model supports second order effects such as common mode rejection output voltage and current limiting characteristics of the opamp in addition to the first order effects The modeled opamp parameters are open loop gain e input resistance Output resistance slew rate unity gain bandwidth common mode rejection CCMR input bias current input offset current input bias current input offset voltage input bias voltage output voltage swing output current limiting The internal components of a 741 opamp are shown below Multisim User Guide G 5 Dojeuy Analog Analog Components The circuit is divided into three stages The input stage consists of ideal transistors Q1 and Q2 and associated sources and passive elements It produces the linear and nonlinear differ
289. g A Brig M5 v16 21100 Hz 0 Deg Time base L 2 Electronics Workbench Divider L 1 1 Characteristic Equation The output voltage is given by V out where lt x ll K X Vi x Y V Yg Off input voltage at x input voltage at y Other symbols used in these equations are defined in Multiplier Parameters and Defaults L 1 2 Multiplier Parameters and Defaults Symbol Parameter Name Default Unit k Output gain 0 1 VN off Output 0 0 V Yoff Y offset 0 0 V Yk Y gain 1 0 VN Xoff X offset 0 0 V Xk X gain 1 0 VN L 2 Divider Y A1 x Aviv OY Multisim User Guide This component divides one voltage the y input or numerator by another the x input or denominator Vo Vy Vx L 3 S O4 UO Controls Controls Components You can limit the value of the denominator input to a value above zero by using the parameter XLowLim This limit is approached through a quadratic smoothing function the domain of which you can specify as an absolute value in XDS In the example shown below the 120v RMS 339 38v peak to peak sine wave at the Y input is divided by a 16 96V DC voltage at the X input The result is 339 38v peak to peak 16 97V 20v peak to peak If Vx is replaced with a 12v RMS voltage in phase with Vy the output will be 10V DC CAUTION If the X denominator voltage crosses Ov when any voltage is present at
290. g Close button will close the screen however options selected for the screen are not canceled Clicking STOP on the toolbar or pressing ESC will stop the current process such as input ting a file or running logic simulation If SILOS III hangs and does not respond see Reports Nonconvergence For the command line version silos exe on the PC and silos on Unix pressing the CTRL and C keys will stop the current process B 3 2 File Menu The File menu provides the following commands File New e File Open e File Save File Save As File Print e File Print Preview File Print Setup File Exit B 3 2 1 File New Opens a new source window for editing B 3 2 Electronics Workbench File Menu B 3 2 2 File Open Opens a source window for an existing file so that you can view or edit the file More that one source window can be open at the same time Use the Window menu to switch among the multiple open documents To simulate a project use Project New to create a new project B 3 2 3 File Save Saves the contents of the source file window that has the focus The document remains open so you can continue working on it To save the simulation results for logic simulation see Project Save Project State B 3 2 4 File Save As Allows you to specify a file name and then save the contents of the source file window that has the focus When you choose Save As the document remains open so you can
291. g coil in henrys resistance of the relay s switching contact in ohms turn on current in amperes holding current in amperes current through the energiz ing coil in amperes Electronics Workbench Variable Capacitor D 9 Variable Capacitor c2 a Key a 100pF D 9 1 The Component This component acts much like a regular capacitor except that its setting can be adjusted D 9 2 Characteristic Equation and Model This component s capacitance C is computed based on the initial settings according to the equation _ Setting 100 Capacitance The variable capacitor is simulated as an open circuit with a current across the capacitor forced to zero by a large impedance value Values are set in the same way as those for the potentiometer D 9 3 Virtual Variable Capacitor This component performs the same functions as a variable capacitor but has a user settable value Multisim User Guide D 15 oiseg Basic Basic Components D 10 Variable Inductor L2 Key a 100mH D 10 1 The Component This component acts much like a regular inductor except that its setting can be adjusted D 10 2 Characteristic Equation and Model This component s inductance L is computed based on the initial settings according to the equation Settin jose 100 Inductance The variable inductor is simulated as an open circuit with a current across the inductor forced to zero by a large impedance
292. gger action this device is ideal for circuits that are susceptible to unwanted small signals such as noise Electronics Workbench 4000 Series ICs O 2 66 4094 8 stage Serial Shift Register The 4094 device is an 8 stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to par iz LA allel buffered 3 state outputs OO to O7 Shift register truth table PARALLEL SERIAL INPUTS OUTPUTS OUTPUTS CP EO STR Oo On Os Os Z Z Os nc Z Z nc 0 0 Opi Os nc D X X X nc nc Os nc 0 1 t 054 1 06 He 1 PRRPRPROO FP Ho X nc nc nc 0 1 HIGH state the more positive voltage 0 LOW state the less positive voltage state is immaterial positive going transition negative going transition Z high impedance off state nc no change O6 the information in the seventh shift register stage Multisim User Guide O 37 seues 000p suonounJ Functions 4000 series Functions 4000 Series O 2 67 4099 8 bit Latch The 4099 device is an 8 bit addressable latch The input for this device is a unidirectional write only port O 2 68 4502 Strobed hex INVERTER This device contains six independent INVERTER gates N INVERTER gate truth table x MH Oo x FH Oo Oo BI rRooo NOOR 0 38 Electronics Workbench 4000 Series ICs O 2 69 4503 Tri state hex BUFFER w Strobe 00
293. gin timescale 100ps 100ps timescale for stimulustable stimulustable s1 table inl in2 bil bi2 include stim v endtable endstimulustable timescale lns 100ps respecify the circuit s timescale 10 Sfinish end endmodule When converting behavioral stimulus to tabular stimulus you need to ensure that timescale for the tabular stimulus is correct The units for the time values from the probe command are equal to the smallest resolution for the simulation This may require a timescale compiler directive before the stimulustable statement so that the delay values are scaled correctly In the above example the resolution of the timescale 1ns 100ps compiler directive for the cir cuit is 100ps so a timescale 100ps 100ps compiler directive must be used before the stimulustable statement Notice that the stimulustable for the above example also uses the delay notation so that the time values are relative to the time that the stimulustable statement is started Notice also that you may need to be careful when applying the stimulus for inout bi direc tional pins in the circuit The inout pins bil and bi2 are defined as the left hand side of continuous assignments For this circuit the stimulustable values should be applied to the registers bil and bi2 Otherwise registers bil and bi2 will remain at an Unknown level and will continue to drive wires bil and bi2 to an Unknown level due
294. gn These are all points in the behavior level of abstraction After this initial simulation the design must be further refined until the description is some thing a VHDL synthesis tool can digest That is the dataflow level of abstraction The structure level of abstraction occurs when smaller segments of circuitry are being con nected together to form a larger circuit The structure level is commonly thought of as a circuit netlist or perhaps a higher level block diagram The three levels of abstraction are as follows Behavior The highest level of abstraction supported in VHDL is called the behavior level of abstrac tion When creating a behavioral description of a circuit you will describe your circuit in terms of its operation over time The concept of time is the critical distinction between behavioral descriptions of circuits and lower level descriptions specifically descriptions created at the dataflow level of abstraction In a behavioral description the concept of time may be expressed precisely with actual delays between related events such as the propagation delays within gates and on wires Multisim User Guide A 9 JOWUd TAHA VDHL Prrimer VHDL Primer or it may simply be an ordering of operations that are expressed sequentially such as in a functional description of a flip flop When you are writing VHDL for input to synthesis tools you may use behavioral statements to imply that there are registers in
295. have moved toward hardware description languages HDLs The most prominent modern HDLs in industry are Verilog and VHDL Verilog is the top HDL used by over 10 000 designers at such hardware vendors as Sun Microsystems Apple Computer and Motorola Industrial designers like Verilog It works The Verilog language provides the digital designer with a means of describing a digital system at a wide range of levels of abstraction and at the same time provides access to computer aided design tools to aid in the design process at these levels Verilog allows hardware designers to express their design with behavioral constructs deter ring the details of implementation to a later stage of design in the design An abstract repre sentation helps the designer explore architectural alternatives through simulations and to detect design bottlenecks before detailed design begins Though the behavioral level of Verilog is a high level description of a digital system it is still a precise notation Computer aided design tools i e programs exist which will compile programs in the Verilog notation to the level of circuits consisting of logic gates and flip flops One could then go to the lab and wire up the logical circuits and have a functioning system Electronics Workbench The Verilog Language And other tools can compile programs in Verilog notation to a description of the integrated circuit masks for very large scale integration VLSI Th
296. he Project must be reloaded by using Project Open or by selecting a project name from the Most Recently Used list of projects at the bottom of the Project menu To invoke this command right click on any part of the left hand side of the Explorer window to open the pop up menu Electronics Workbench Pop up Menus B 3 12 2Watch Window B 3 12 2 1Add Signal Expression Opens the Specify Signal Expression screen To use this command right click on any part of the Watch window to open the pop up menu The Specify Signal Expression screen contains an edit box Scope to specify the scope for the signal The Specify Signal Expression screen also contains an edit box Signal Expres sion to enter a signal or an expression Any valid Verilog HDL expression can be entered If the expression or scope is not valid then the expression will list an Error The OK button closes the screen and displays the specified expression in the Watch window The Cancel button closes the screen and does not display the expression B 3 12 2 2Set Value For Watch Window Can be used to force or set a vector in the Watch window To use this command right click on any part of the Watch window to open the pop up menu B 3 12 2 3Free Forced Wire For Watch Window Frees a wire that has been forced in the Watch window To use this command right click on any part of the Watch window to open the pop up menu B 3 12 2 4Clear All For Watch Window Clea
297. he Three Terminal Opamp model of EWB Version 5 This model is an idealized differential input single output model that models only the first order characteristics of the opamp The modeled opamp parameters are e open loop gain e input resistance Output resistance slew rate unity gain bandwidth input bias current input offset current The opamp is modeled by distributing the open loop voltage gain A across three stages The first and second stages model the first and second poles of the opamp and the third stage models the output impedance The same model is used for DC time domain and AC analyses Is Ibias dox 2 Is2 Inns EE 2 he Are Vivi Ri Ai A Multisim User Guide G 3 Bojeuy Analog Analog Components where A open loop voltage gain of the first stage Rin input resistance in ohm Ig as input bias current in amperes los input offset current in amperes R 1 KQ Su fu A 1 ze 27 R fri The slew rate limits the rate of change of to model the rate of change of output voltage pz A Vm R 2 AlB A A R Roy where Rour output resistance A third stage is introduced by specifying the location of the second pole 1 C 270 Ry fo R 1 KQ R Rour E AV R G 4 Electronics Workbench Opamp where f unity gain bandwidth in hertz i e the fre quency at which the open loop voltage gain equals 1 fpo second pole
298. he output from a PLL that determines a precise frequency Control voltage may be a continuous variable of any desired shape as required in sweep gen erators and spectrum analysers In the example shown below the VCO parameters are set so that control voltage of OV pro duces an output frequency of 100Hz and a control voltage of 12V produces an output fre quency of 20KHz Multisim User Guide C 9 seounos Sources Sources Components A square wave control voltage produces a form of FSK frequency shift keying a sine wave control voltage produces a form of FM frequency modulation 81 MEY Bl cowrROLV Frequency Adj R1 F 1 kQ 60 2060 Vl M1 30 Frequency Duty cycle Offset 30 i i 30 s Dscilloscope Time base 0 20ms div X position 0 00 E Wiper ta ae Channel A Yposition 0 00 E Bel e oc Be Channel B 3 Yposition 0 00 Bel ajjoc 6 C 17 Voltage Controlled Square Wave AV 1V C 10 Electronics Workbench Voltage Controlled Square Wave C 17 1 The Component This oscillator is identical to the voltage controlled sine wave oscillator except that it outputs a square wave This oscillator takes an input AC or DC voltage which it uses as the indepen dent variable in the piecewise linear curve described by the control frequency pairs From the curve a frequency value is determined and the oscillato
299. his device contains six independent INVERTER gates Due the to the 1 Rs s Schmitt trigger action this device is ideal for circuits that are susceptible to unwanted small signals such as noise Logic function Multisim User Guide O 5 seues 000p suonounJ Functions 4000 series Functions 4000 Series INVERTER gate truth table A Y 0 1 T 0 O 2 8 4011 Quad 2 In NAND This device contains four independent 2 input NAND gates i 2 Logic function O1 LI NAND gate truth table 0 0 I 0 0 1 t 1 OH HH 0 2 9 4012 Dual 4 In NAND This device contains four independent 4 input NAND gates Logic function e 5 0 O4 1 12 13 1 NAND gate truth table INPUTS OUTPUTS Il I2 13 I4 ol 1 1 1 1 0 0 X X X 4 X 0 X X a X X 0 X 1 X X X 0 1 O 6 Electronics Workbench 4000 Series ICs O 2 10 4013 Dual D type FF edge The 4013 device is a dual D type flip flop that features independent set i direct Sp clear direct Cp clock inputs CP and outputs 0 0 Dlo o y 9 X AA 70 0 1 X X 0 1 1 1 X X 1 1 0 0 o lo 1 0 0 je lit 0 positive edge triggered 0 2 11 4014 8 bit Static Shift Reg The 4014 device is a fully synchronous edge triggered 8 bit static shift M qu register with eight synchronous parallel inputs Po to P7 a synchronous 6 z de T Sa serial data input Ds a synchronous parallel enable input PE a LOW A P3 an E to HIGH edge
300. ic makeup of a square wave Amplitude and phase of any of the signals may be varied to experiment further CAUTION The switches should not be operated while a solution is in progress This will result in solution error messages Allow the solution to pause or pause it by clicking on the solution switch Operate a switch to add the desired harmonic and then solve the cir cuit again V2 120 V 60 Hz 0 Deg Dscilloscope Time base Xposition 0 00 4 vT ens ven Channel A Y position 0 00 welo oc s Electronics Workbench Three Way Voltage Summer L 12 1 Charactistic Equation Vour Kov Ka Va Vaag Ka Ve Vaagr T Kc Vc Vcog V oor L 12 2 Summer Parameters and Defaults Symbol Parameter Name Default Unit VAoff Input A offset voltage 0 V VBoff Input B offset voltage 0 V VCoff Input C offset voltage 0 V Ka Input A gain 1 VN Kb Input B gain 1 VN Kc Input C gain 1 VN Kout Output gain 1 VN VOoff Output offset voltage 0 V Multisim User Guide L 23 S O04 UO Controls Controls Components L 24 Electronics Workbench Appendix M RF Components M 1 M 2 M 3 M 4 M 5 M 6 RE Capacitor a een RU eus eMe EI o RS M 1 BF Ind ctor z osse Aie eene ih SEE nter nti RR M 1 RF Bipolar Resistors o erennere ee en M 2 REMOS23TDN soccpsbhssibete PESCLRF BORU U ts Een M 2 Tunnel DIode drerit hee n ber ELI Bun daa In le DIETE M
301. ich the simulation state values to all variables are saved 2 The effects to the MKEEP and MEXCLUDE commands are cumulative 3 The KEEP EXCLUDE MKEEP and MEXCLUDE commands can be used with the CONTROL SAVSIM 1 option Examples CONTROL SAVSIM 1 MKEEP macl a MEXCLUDE maci a ca Imexclude m1 bitO mi biti m1 bit2 m1 bit3 m1 bit4 m1 bit5 m1 bit6 mi bit7 driver iobuf pin34 B 2 40 Electronics Workbench Silos III Command Line Usage B 2 2 14Keeping Module Instance Simulation Variable Values The MKEEP command saves the logic simulation state values for all variables in the specified module instances and macro expansions and the state values for all variables hierarchically below each specified module instance and macro expansion The format for the MKEEP command is MKEEP mname mname n mname MKEEP specifies module instances and macro expansions whose logic simulation state values will be saved for all variables in the specified module instance and macro expansion and for all variables hierarchically below each specified module instance and macro expansion mname represents the name of a module instance or macro expansion Application Notes 1 The MEXCLUDE command can be used to specify module instances and macro expan sions whose internal variables will not be saved during logic simulation 2 The effects to the MKEEP and MEXCLUDE commands are cumulative 3 The KEEP EXCLUDE MKEEP an
302. ide SJO SISUBJ Transistors Transistors Components F6 2 JFET Model Parameters and Defaults Symbol Parameter Name Default Example Unit VTO Threshold voltage 2 V BETA Transconductance coeffi 0 0001 1e 03 AN cient LAMBDA Channel length modulation 0 1e 04 1 V RD Drain ohmic resistance 0 WwW RS Source ohmic resistance 0 WwW IS Gate junction saturation cur 1e 14 1e 14 A rent Cgd Zero bias gate drain junction O 1e 12 F capacitance Cgs Zero bias gate source junc 0 5e 12 F tion capacitance PB Gate junction potential 1 V B Doping tail parameter 1 KF Flicker noise coefficient 0 AF Flicker noise exponent 1 FC Coefficient for forward bias 5 depletion capacitance for mula TNOM Parameter measurement 27 C temperature rp rg 10 to 15 of the on state drain to source resistance Rps on F 18 Electronics Workbench Power MOSFET N P F 7 F 8 F 8 1 Power MOSFET N P The double diffused or DMOS transistor is an example of a power MOS DE FET This device is fabricated on a lightly doped n type substrate with a heavily doped region at the bottom for drain contact Two diffusions are used one to create the p type body region and another to create the n type source region The DMOS device is operated by applying a positive gate voltage vgs greater than the threshold voltage V which induces a lateral n channel in the p typ
303. ide parameters and defaults L 7 transformer linear D 10 nonlinear D 12 Tri 3 In AND 4073 O 30 74xx11 P 7 Tri 3 In NAND OC 74xx12 P 10 4023 O 16 74xx10 P 6 Tri 3 In NOR 4025 O 19 74xx27 P 48 Tri 3 In OR O 31 triac E 16 triangle wave generator C 13 triangle waveform L 9 triode vacuum tube about K 4 equations K 5 model K 5 parameters and defaults K 6 Triple Serial Adder 4032 O 22 4038 O 24 Tri state hex BUFFER w Strobe O 39 TTL components P 1 tunnel diode M 3 V varactor diode E 18 variable capacitor D 15 variable inductor D 16 Vcc voltage source C 3 Verilog HDL extensions B 2 1 menus B 3 1 xiii primer B 1 1 resistance J 1 VHDL examples A 23 WwW sample circuits A 3 wide bandwidth amplifiers G 11 standards history A 1 voltage Z gain C 7 voltage differentiator See differentiator zonar diode about E 6 voltage gain block DC model E 7 about L 7 f parameters and defaults E 8 equations L 8 parameters and defaults L 8 voltage hysteresis block about L 13 parameters and defaults L 14 voltage integrator See integrator voltage limiter See limiter voltage reference K 6 voltage regulator K 7 voltage slew rate block about L 20 parameters and defaults L 21 voltage suppressor K 8 voltage controlled analog l 2 voltage controlled current source C 8 voltage controlled limiter about L 19 parameters and defaults L 20 voltage controlled piecewise linear source C 14 vol
304. ied values of a controlling input voltage Note that the input is not internally limited Therefore if the controlling signal exceeds the specified Coff or Con values the resistance may become excessively large or small 2 f NET The voltage controlled switch has a function similar to that per formed by a mechanical On Off switch except that the On Off conditions are selected by a control voltage When the control voltage is below a selected value the switch is off and the input and output signals are disconnected When the control voltage is above the selected value the switch is on and the input and output signals are connected Electronics Workbench Timer 1 3 1 3 The 555 timer is an IC chip that is commonly used as an astable multivi vec brator a monostable multivibrator or a voltage controlled oscillator The g our 555 timer consists basically of two comparators a resistive voltage divider a flip flop and a discharge transistor It is a two state device whose output voltage level can be either high or low The state of the out ols put can be controlled by proper input signals and time delay elements GND connected externally to the 555 timer 1 LMSSSCH Model The internal diagram of a 555 timer is shown below The resistive voltage divider is used to set the voltage comparator levels All three resistors are of equal value The upper comparator has a reference voltage of 2 3 V and the lower co
305. ier 00 eee eee G 11 G 4 1 The Component 0 00 nnn G 11 G 4 2 Wide Band Amplifier Simulation ModelS ooococcoccccocoo G 11 Special FUNCION erreso RE Rx Ex Rue RR RA RR OC RE G 12 G 5 1 The Component oocccccc nen G 12 G 5 2 Special Function Simulation MOdelS o o oooooooococooooooo G 12 Multisim User Guide Bojeuy Electronics Workbench Appendix G Analog Components G 1 Opamp G 1 1 Opamp Model Parameters An ideal operational amplifier Opamp is an amplifier with infinite gain infinite input impedance and zero output impedance With the application of negative feedback Opamps can be used to implement functions such as addition subtraction differentiation integration averaging and amplification An opamp can have a single input and single output a differential input and single output or a differential input and differential output G 1 2 Ideal Opamp Model The ideal opamp model is the fastest to simulate Its characteristics include open loop voltage gain A The open loop gain is the gain of the opamp without any feedback applied which in the ideal opamp is infinite This is not possible in the typical opamp but it will be in the order of 120 dB frequency response Multisim User Guide G 1 Bojeuy Analog Analog Components The frequency response of an opamp is finite and its gain decreases with frequency For stability a dominant pole is intent
306. ifferential Driver Receiver Pair IF75188 VHD RS 232 Quad Line Driver IF75189 VHD RS 232 Line Receiver STD00 VHD 2 input positve NAND gate STD01 VHD 2 input positve NAND gate with open collector output STD02 VHD 2 input positve NOR gate STD03 VHD 2 input positve NAND gate with open collector output STD04 VHD Inverter STDO05 VHD Inverter STD06 VHD Inverter with open collector output STD07 VHD Buffer Driver with Open Collector Outputs STD08 VHD 2 input positve AND gate STD10 VHD 3 input NAND gate STD109 VHD Positive Edge Triggered J K Flip Flop STD11 VHD 3 input positve AND gate STD125 VHD Line driver with 3 state output STD132 VHD 2 input positve NAND gate STD138 VHD 3 to 8 decoder STD139 VHD 2 to 4 decoder STD14 VHD Inverter STD157 VHD 2 1 Mux with enable STD16260 VHD Multiplexed D Latch with 3 State Outputs STD16500 VHD Universal Bus Transceiver STD16501 VHD Universal Bus Transceiver STD16601 VHD Universal Bus Transceiver STD240 VHD Inverting line driver with 3 state output STD244 VHD Line driver with 3 state output Multisim User Guide H 7 eubig OSIN Misc Digital Misc Digital Components STD245 VHD 8 bit TTL Transceiver STD257 VHD 2 1 Mux with 3 state output STD258 VHD 2 1 Mux with 3 state inverting output STD26 VHD 2 input positve NAND gate with open collector output STD273 VHD D Flip Flop with Clear STD32 VHD 2 input positve OR gate STD373 VHD Transparent Latch STD374 VH
307. ified on each instance in the hierarchy by the Properties command in the Explorer pop up menu Simulation Data File Path This specifies the directory where the simulation history file is stored This enables you to use disk drives with more space or that are more convenient e Save celldefine data This feature determines if variables in celldefine endcelldefine boundaries are saved This feature is useful for excluding variables that are inside of library cells from the save file thus reducing the size of the save file on disk When using the Data Analyzer if you see No Saved Data instead of a waveform this may mean that the signal is inside of a celldefine boundary To correct this enable the Save celldefine data option and re simulate Tabs This feature will set the spacing for tabs in the source file windows This can be use ful for customizing the tab spacing Use Alternate Behavioral Evaluation Order This instructs the simulator to evaluate selected behavioral code in a similar order of execution as used by other Verilog HDL simulators B 3 5 9 Project Filters Opens the File Filters screen for specifying file name filters for the Project Files screen Project Files If you specify a file filter then the default filters are hidden for the Project Files screen The name filtering for the Project Files screen uses the standard Windows style wildcard char acters for file name expansion The asterisk character
308. ift key modulated source C 6 FSK source See frequency shift key modulated source full wave bridge rectifier about E 10 characteristic equation E 10 model E 10 parameters and defaults E 11 functions 4000 O 3 4001 O 3 4002 O 4 4007 O 4 4008 O 4 4010 O 5 40106 O 5 4011 O 6 4012 O 6 4013 O 7 4014 O 7 4015 O 8 40160 O 9 40161 O 10 40162 O 10 40163 O 10 4017 O 11 4077 O 32 40174 O 12 4078 O 32 40175 O 12 4081 O 33 4018 O 13 4082 O 33 4019 O 14 4085 O 34 40192 O 14 4086 O 36 40193 O 15 4093 O 36 40194 O 15 4094 O 37 40195 O 15 4099 O 38 4020 O 16 4502 O 38 4021 O 16 4503 O 39 4023 O 16 4508 O 39 4024 O 17 4510 O 40 40240 O 18 4511 O 41 40244 O 18 4512 O 42 40245 O 18 4514 O 43 4025 O 19 4515 O 44 4027 O 19 4516 O 45 4028 O 20 4518 O 46 4029 O 21 4519 O 47 4030 O 21 4520 O 47 4032 O 22 4522 O 48 4035 O 22 4526 O 48 40373 O 23 4531 O 48 40374 O 24 4532 O 49 4038 O 24 4539 O 50 4040 O 24 4543 O 50 4041 O 25 4544 O 52 4042 O 25 4555 O 53 4043 O 26 4556 O 53 4044 O 26 4585 O 54 4049 O 26 74xx00 P 2 4050 O 27 74xx02 P 3 4066 O 27 74xx03 P 3 4068 O 28 74xx04 P 3 4069 O 28 74xx05 P 4 4070 O 28 74xx06 P 4 4071 O 29 74xx07 P 5 4072 O 29 74xx08 P 5 4073 O 30 74xx09 P 5 4075 O 31 74xx10 P 6 4076 O 31 74xx100 P 6 Electronics Workbench 74xx107 P 7 74xx109 P 7 74xx11 P 7 74xx112 P 8 74xx113 P 8 74xx114 P 9 74xx116 P 9 74xx12 P 10 74xx125 P 11 74xx126 P 11 74xx132 P 11 74xx133 P 12 74xx134 P 12 74xx135 P 13
309. iled for the type of platform you are using For example object code from the Sun will not work on the PC The SILOS III pliload command is used to specify the dll files for SILOS III at runt ime The pliload command is cumulative so that one or more pliload commands is allowed before starting simulation The pliload command can be entered in the Com Multisim User Guide B 2 1 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 2 mand window for the Main toolbar from the SILOS III command line or from a file pliloadmypli dll Example for entering the pliload command in the Command window for the Main toolbar silos exe myfile v pliloadmypli dil Example for entering the pliload command at the command line module foo Entering the pliload command from a file endmodule ifdef silos pliload endif For more information see the README TXT file in the PLI subdirectory for the SILOS III installation For an example of using PLI with SILOS III see file pli01 spj in the PLI subdirectory for the SILOS III installation or contact Simucad B 2 1 1 2SILOS III PLI Interface on the Workstation The PLI can be used with SILOS III on the Sun and HP workstations supported by SILOS III Contact Simucad for an updated list of supported platforms To use PLI on the workstation e Create one or more so files that contain the object code for the PLI For example to creat
310. im User Guide POXIIN Electronics Workbench Appendix Mixed Components 1 1 ADC DAC At An ADC is a special type of encoder that converts the input analog voltage to an equivalent output digital word There are five inputs and nine outputs 1 1 1 Characteristic Equation The V input is the analog voltage input The voltage at V and V pins set up the full scale voltage The full scale voltage is given by Vs Vref Vref To start the conversion the SOC pin should be driven high This pulls the EOC pin low signi fying that a conversion is taking place The conversion takes 1 uS to complete and the EOC pin is pulled high when it is completed The output digital data is now available at pins DO through D7 These are tri stated outputs pins which may be enabled by pulling the OE pin high Multisim User Guide POXIIN Mixed Mixed Components The output at the end of the conversion process is the digital equivalent of the analog input voltage The discrete value corresponding to the quantized level of input voltage is given by input voltage 256 Vis Note that the output described by this formula is not a continuous function of input voltage The discrete value is then encoded into the binary digital form at pins DO through D7 The binary output is thus given by BIN input voltage 256 Vs 1 2 Analog Switch A This switch is a resistor that varies logarithmically between spec i if
311. ime may not be predictable B 1 2 9 1 Delay Control A delay control expression specifies the time duration between initially encountering the statement and when the statement actually executes For example 10 A A 1 specifies to delay 10 time units before executing the procedural assignment statement The may be followed by an expression with variables B 1 2 9 2 Events The execution of a procedural statement can be triggered with a value change on a wire or register or the occurrence of a named event Some examples er begin controlled by any value change in A B C the register r end e posedge clock2 A B amp C controlled by positive edge of clock2 negedge clock3 A B amp C controlled by negative edge of clock3 forever negedge clock controlled by negative edge begin A B amp C end Multisim User Guide B 1 19 Jewud Boje Verilog Primer Verilog HDL Primer B 1 20 In the forms using posedge and negedge they must be followed by a 1 bit expression typically a clock A negedge is detected on the transition from 1 to 0 or unknown A posedge is detected on the transition from 0 to 1 or unknown Verilog also provides features to name an event and then to trigger the occurrence of that event We must first declare the event event evento To trigger the event we use the gt symbol event6 To control a block of code we usethe symbol as shown event6 begin
312. ing selections for groups IB SILOS c silos3 examples rtl spj Debug Dala Analyzer File View Project Explorer Debug Options Window Help tal s ol 9 alwe Command Name S Value P 000us f070us E Default Trace Signal Inputs clock E __ e New Group clk nex Delete Group rx 12 10210121012 0 2 Insert Group newspi Show Groups nno reset Se Bad EXT MEME Ex TVs 7 mus SN ST ets N Reverse Bit Wrder info g6 84d ional O WNA 3 Add Blank Line DN YVYYYYYYYYY 4 Clear Signal List 4 gt For Help press F1 T1 T2 Tdelta Time 1 540us mm Y Signal list box Selections for groups New Group This selection can be used to add a new group to the Name list box Delete Group This selection can be used to delete a group Insert Group This selection opens the Add Group screen This screen will insert a group within a group The inserted group is displayed as a bus which can be expanded and hid den by double clicking on it e Show Groups This selection opens the Select Signal Groups screen This screen can be used to select which groups are displayed in the Data Analyzer To invoke the pop up menu right click on any part of the Name list box The pop up menu will remain open while the mouse is used to select the group menu item of interest When the Data Analyzer window is opened the Default group is displayed To save any signals tha
313. ing this feature eliminates the time required to re input and re simulate the design A debugging strat egy may be to simulate to a timepoint and then use Project Save Project State to save the state of the simulation You can then set variables to a value and continue simulation To restart the simulation exit SILOS III then restart SILOS III and choose Project Restore Project State to return the simulation to the timepoint the simulation was saved at To restart the simulation from time 0 you do not need to exit SILOS III Instead use Debug Restart Simulation This is useful for re starting single stepping without having to re input the design Multisim User Guide B 3 21 snus 111 SOS Silos II Menus Silos III Menus Loss of Simulation Data To prevent the loss of the simulation results due to unexpected interruptions you can save the state of SILOS III after logic simulation When simulation has completed save the simulation results by choosing Project Save Project State Then open the Data Analyzer review your simulation results and debug your design If you need to re enter SILOS III you can select Project Restore Project State open the Data Analyzer and view the waveforms without re simulating B 3 8 2 Debug Break Simulation Stops the SILOS III program from simulating logic simulation The ESC key or the STOP but ton on the toolbar performs the same function B 3 8 3 Debug Finish Current Timepoint Used to con
314. ion to generate output The PWL source can handle unsorted data It sorts the points by time before the simulation starts If you do not specify a file name the PWL source behaves as a short circuit An easy way to generate an input file for the PWL source is to capture data using the Write Data component described in the Miscellaneous Parts Bin chapter If you capture more than one node with Write Data and then use the resulting file for the PWL source only the wave form V1 will be used Multisim User Guide C 17 seounos Sources Sources Components C 20 2 Piecewise Linear Voltage Source This component is a piecewise linear source of which the output is measured in A w voltage C 20 3 Piecewise Linear Current Source This component is the same as the Piecewise Linear Voltage Source except that EN 1 the output is measured in current C 21 Pulse Source This source includes pulse voltage source and pulse current source The Pulse sources are con figurable sources whose output can be set to produce periodic pulses The following parameters can be modified Initial Value e Pulsed Value Delay time Rise Time Falltime e Pulse Width Period C 18 Electronics Workbench Pulse Source Pulse Voltage C 21 1 Pulse Voltage Source This component is a pulse source of which the the output is measured in volt v2 age Multisim User Guide C 19 Sources Sources Components C 21 2 P
315. ionally added to the opamp to control this decreasing gain with frequency In an internally compensated opamp the response typically is set for 6dB octive roll off with a 3dB frequency in range of 10 Hz With an externally compen sated Opamps the 3 dB corner frequency can be changed by adding an external capacitor unity gain bandwidth This is the frequency at which the gain of the opamp is equal to 1 This is the highest fre quency at which the opamp can be used typically as a unity gain buffer common mode rejection ratio CCMR This is the ability of an opamp to reject or to not amplify a signal that is applied to both its input pins expressed as a ratio in dBs of its common mode gain to its open loop gain slew rate This is the rate of change of output voltage expressed in volts per microsecond G 1 3 Opamp Background Information The operational amplifier is a high gain block based upon the principle of a differential ampli fier It is common to applications dealing with very small input signals The open loop voltage gain A is typically very large 10e 5 to 10e 6 If a differential input is applied across the and terminals the output voltage will be V A V V The differential input must be kept small since the opamp saturates for larger signals The output voltage will not exceed the value of the positive and negative power supplies Vp also called the rails which vary typically from 5 V to 15
316. ions the rising or the falling edge of the strobe signal should not coincide with a change in the expected output signal in the stimulustable For example in stimulustable s1 shown below variable strobel strobes outl every 0 2 nano seconds This is faster than the input values change every 1 2 nano seconds for variables inl and in2 When the second entry in the table is executed the calculated value for out1 f6 does not equal its expected value The violation is recorded at the next high pulse for variable strobel and then is not recorded again until after the next entry in the table occurs control ext stim timescale 1ns 100ps module test reg 7 0 inl in2 1 0 wire 7 0 outl inl in2 0 reg strobel initial strobel 0 always Goutl begin 480 1 strobel 1 40 1 strobel 0 end initial begin 5 stimulustable s1 table 1 2 inl in2 0 outlestrobel 00 00 ff 0e Oa 6 ff ff 00 endtable endstimulustable end endmodule Using the disable statement to disable the block containing the stimulustable statement imme diately terminates expected value checking Multisim User Guide B 2 9 suoisuejx3 JAH Bojan Verilog HDL Extensions Extensions B 2 10 Each expected value column has one strobe however multiple columns may each have differ ent strobes B 2 1 3 7 I O Pad The stimulustable can be used to model a bi directional I O pad In the example below for stimulustable s1 variable enable con
317. ir cuit elements into a larger circuit the comparator and shift register circuits will be connected into a larger circuit as shown below Multisim User Guide A 19 JOWUd TAHA VDHL Prrimer VHDL Primer Note This diagram was drawn in much the same way you might enter it into Multisim Structural VHDL has many similarities with schematic based design A 2 6 7 Design Hierarchy When you write structural VHDL you are in essence writing a textual description of a sche matic netlist a description of how the components on the schematic are connected by wires or nets In the world of schematic entry tools such netlists are usually created for you auto matically by the schematic editor as Multisim does When writing VHDL you enter the same sort of information by hand When you use components and wires signals in VHDL to connect multiple circuit elements together it is useful to think of your new larger circuit in terms of a hierarchy of components In this view the top level drawing or top level VHDL entity and architecture can be seen as the highest level in a hierarchy tree as shown below library ieee use ieee std logic 1164 all entity rotcomp is port Clk Rst Load in std ulogic Init in std ulogic vector 0 to 7 Test in std ulogic vector 0 to 7 Limit out std ulogic end rotcomp architecture structure of rotcomp is component compare port A B in std ulogic vector 0 to 7 EQ out std ulogic end co
318. irectional gate devices device Represents a device keyword see note 1 below If no device P or device strg is specified for an individual gate device the program defaults to a CMOS strength type DEFAULT Sets the strength for all devices that do not have the strength explicitly specified The default is CMOS strength type strg Represents any combination of D R or Z The first character indicates the strength of the Low level The sec ond character indicates the strength of the Unknown level The third character indicates the strength of the High level D represents Strong strength R repre sents Pull strength and Z represents High Z strength Alternatively the characters N P or C can be used by themselves to indicate NMOS type DRR PMOS type RRD or CMOS type DRD defaults Application Notes 1 The device keyword can be any of the combinatorial gate devices 2 Supply strength cannot be defined Examples Istrength nor n nand n not c Istrength default ddd B 2 52 Electronics Workbench Silos III Command Line Usage B 2 2 27Symbol Modification For Output The SYMBOL command allows you to use a unique symbol for each possible logic state To modify the output state symbols use SYMBOL sc char sc char sc char SYMBOL Specifies that the state code symbols are to be redefined SC state symobols so S 1 SHV DO D D1 DHV RO R R1 RHV ZO z Z1 ZHV
319. irectly as the lower level storage object Q will not be fed back directly anarchitecture declaration consisting of a single process statement that defines the opera tion of the shifter over time in response to events appearing on the clock Clk and asyn chronous reset Rst Process Statement The process statement in VHDL is the primary means by which sequential operations such as registered circuits can be described When describing registered circuits the most common form of a process statement is Electronics Workbench Learning VHDL architecture arch name of ent name is begin process name process sensitivity list local declaration local declaration begin Sequential statement Sequential statement Sequential statement end process end arch name A process statement consists of the following items e An optional process name an identifier followed by a colon e The process keyword e An optional sensitivity list indicating which signals result in the process executing when there is some event detected The sensitivity list is required if the process does not include one or more wait statements to suspend its execution at certain points An exam ple that does not use a sensitivity list is discussed in A 2 6 5 Using a Procedure on page A 17 e An optional declarations section allowing local objects and subprograms to be defined Abegin keyword Asequence of statements to be execute
320. isa more complex model in which the supply voltages are included in the simu lation e 3 this is a model of increasing complexity where additional control pins are supported e L4 this is the most complex and accurate model with a majority of the external control pins modeled Multisim User Guide G 11 Dojpeuy Analog Analog Components G 5 Special Function G 5 1 The Component These are a group of analog devices that are used for the following applications instrumentation amplifier video amplifier multiplier divider preamplifier active filter G 5 2 Special Function Simulation models G 12 The same levels of simulation model as the opamps are provided with several levels of simu lation models of increasing complexity and accuracy The following model levels are used to distinguish between these models L1 this is the simplest model with the opamp modeled as a gain block with a differential input and a single ended output L2 this is a more complex model in which the supply voltages are included in the simu lation L3 this is a model of increasing complexity where additional control pins are supported L4 this is the most complex and accurate model with a majority of the external control pins modeled Electronics Workbench Appendix H Misc Digital Components H 1 H 2 H 3 H 4 H 5 TIE COMPONEMIS vicios o o ai an A wed H 1 Het AND Gate 2 nr A bo Rd H 1 Hi2 OR Gale ii A a A ise Reis H
321. isim User Guide P 79 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 14474xx86 Quad 2 In XOR Logic function X x A B EXCLUSIVE OR gate truth table P 5 14574xx90 Decade Counter The 7490 counts from 0 to 9 in binary It contains four master slave flip flops and additional gating to provide a divide by two counter and a three stage binary counter for which the count cycle length is divide by five Decade counter truth table RESET INPUTS OUTPUT RO 1 RO 2 R9 1 R9 2 QA Qc Qb Qa 1 1 0 X 0 0 0 0 0 0 1 0 0 COUNT COUNT COUNT COUNT x CO x_M MF O M XM OM FH O P OM HP x x OM OF O P 5 14674xx91 8 bit Shift Reg 0 0 1 This 8 bit shift register contains eight R S master slave flip flops input gating and a clock driver P 80 Electronics Workbench 74XX Shift register truth table A B Qh Qh 1 1 1 0 0 X 0 1 X 0 0 T PRESET PRESET SERIAL OUTPUTS CLR ENABLE A B c D CLK QA QB QC QD QE 0 0 X X X X X X 0 0 0 0 0 0 X 0 0 0 0 X X 0 0 0 0 0 1 i 1 I 1 1 X X 1 E de 1 1 1 I 0 0 0 0 0 X QAO QBO QCO ODO QEO 1 E 1 0 1 0 0 X 1 OBO 1 ODO EE 1 0 X X X X 0 X QAO QBO QCO ODO QEO 1 0 X X X X 1 1 QAn QBn QCn QDn 1 0 X X X X 0 0 QAn QBn QCn QDn transition from low to high level QAO QBO the level of QA QB etc respectively before the etc indicated steady state input conditions were estab lished QAn QBn the level of QA QB etc
322. istor firing and temperature compensated amplifier MOSFET A MOSFET is a Metal Oxide Semiconductor FET This transistor is a EJ type of FET that uses an induced electrical field to control current through ersoswe the device Either negative or positive gate voltages can be applied to con trol the current The substrate is usually connected to the most negatively biased part of the MOSFET usually the source lead In the three terminal MOSFETS the substrate is internally connected to the source N channel MOSFETs have an inward pointing substrate arrow and Electronics Workbench MOSFET F 5 1 F 5 2 p channel MOSFETs have an outward pointing arrow N channel and p channel MOSFETs are identical except that their voltage polarities are opposite The 4 Terminal Enhanced N MOSFET is an n channel enhancement MOSFET Because the substrate lead is not connected to the source lead it has four terminals The 4 Terminal Enhanced P MOSFET is a p channel enhancement MOSFET Because the substrate and source leads are not connected it has four terminals Eight MOSFETS both depletion type and enhancement type are included in the parts bin Depletion MOSFETs Like a JFET a depletion MOSFET consists of a length of p type for a p channel MOSFET or n type for an n channel MOSFET semiconductor material called the channel formed on a substrate of the opposite type The gate is insulated from the channel by a thin silicon diox
323. k This feature is very useful for preventing simulation data loss so that you do not have to re simulate your design if you exit SILOS III or if SILOS III crashes Project Save Project State can be selected at any time after simulation has halted When SILOS III is restarted the Project Restore Project State can be used to reload the sim ulation up to the last time point that was saved The Data Analyzer can then be used to view the simulation results and the simulation can be continued The Project Restore Project State must be selected immediately after SILOS III is reopened or a project is opened The Project Restore Project State menu can not be selected after selecting the Project Load Reload Input Files menu or the Go button The simulation history is stored on disk in the file named project name sim and the simula tion state is stored on disk in the file named project name cmm The project name cmm file will be slightly larger than the size of you SILOS III simulation in RAM memory B 3 5 7 Project Restore Project State When SILOS III is restarted Project Restore Project State can be used to reload the simula tion up to the last time point that was saved by Project Save Project State The Data Ana lyzer can then be used to view the simulation results and the simulation can be continued Project Restore Project State must be selected immediately after SILOS III is reopened or a project is opened It can not be selected after sel
324. keywords is found the actual functional description of our comparator There are many ways to describe combinational logic functions in VHDL the method used in this simple design description is a type of concurrent statement known as a conditional assignment This assignment specifies that the value of the output EQ will be assigned a value of 1 when A and B are equal and a value of 0 when they dif fer This single concurrent assignment demonstrates the simplest form of a VHDL architecture There are many different types of concurrent statements available in VHDL allowing you to describe very complex architectures Hierarchy and subprogram features of the language allow you to include lower level components subroutines and functions in your architectures and a powerful statement known as a process allows you to describe complex sequential logic as well Multisim User Guide A 5 dwd TAHA VDHL Prrimer VHDL Primer A 2 4 Data Types Like a high level software programming language VHDL allows data to be represented in terms of high level data types These data types can represent individual wires in a circuit or they can represent collections of wires using a concept called an array The preceding description of the comparator circuit used the data types bit and bit vector for its inputs and outputs The bit data type has only two possible values 1 or 0 Abit vector is simply an array of bits Every
325. l and digital signals such as RS232 interfaces or long signal runs over cables The line receivers are placed at the receiving end of the application before the digital circuits Line Driver Line drivers are devices which are used in applications such as a bridge between analog signal and digital signals such as RS232 interfaces or long signal runs over cables The line drivers are placed at the transmitting end of the application after the digital circuits Line Transceiver Line transceivers are devices which are used in applications such as a bridge between analog signal and digital signals such as RS232 interfaces or long signal runs over cables The line transceivers are placed between the digital circuits Multisim User Guide H 9 eubig OSIN Misc Digital Misc Digital Components Electronics Workbench Appendix Mixed Components 1 1 1 2 1 3 ADG DAG xd rater iecur A A baat aie ele oa need ees l 1 1 1 1 Characteristic Equation sssaaa aaaea l 1 Analog Switch 2 22 ee ie eed a to en acne eee 1 2 Timer us ot wx dde A tented red tese dt re cas l 3 1 3 1 Model 5 226 a aE a n DLE MM tL n Mt a a sd l 3 Mono Stable sai veu eet a AOE l 3 4 1 Models i bu du fae el doe BELL DES td A S S be ty hk e eed ar l 4 Phase Locked Loop E EEEE EE nennen men l 4 1 5 1 Characteristic Equation s a a aaaea eea l 5 1 5 2 Phase Locked Loop Parameters and Defaults liliis l 6 Multis
326. l device without any high current capabilities H 1 10 Schmitt Trigger H 2 This component is a type of comparator with hystereses that produces uniform A Dor amplitude output pulses from a random amplitude input signal It has applica tions in pulse systems for example converting a sine wave into a square wave Characteristic Operation The Schmitt trigger outputs O ifthe voltage is rising and Vp gt Vig 1 ifthe voltage is falling and Vj lt Vig where Vh 16V Vin Vig 0 9V Vj 9 VHDL The components in the VHDL family are digital components in VHDL The models were obtained from the Free Model Foundation http www fmf org The source for these compo nents is installed by default in the vhdl fmfparts subdirectory of the Multisim directory In that sudirectory the VHDL description files named with the form STDxx for example model the equivalent component in the TTL 74xx series e g STDOO vhd is the VHDL description for the 7400 ECL10016 VHD 4 Bit Synchronous Binary Up Counter ECL10102 VHD 2 input NOR and 2 input OR NOR ECL10104 VHD 2 input AND and 2 input AND NAND ECL10124 VHD TTL to ECL Translator Electronics Workbench VHDL ECL10131 VHD Dual D Flip Flop with Set Reset and Clock Enable ECL10141 VHD 4 Bit Universal Shift Register IF75155 VHD RS 232 Driver Receiver IF75172 VHD Quad Differential Line Drivers IF75173 VHD Quad Differential Line Receivers IF75179 VHD D
327. labels on wires The continuous assignment assign continu ously watches for changes to variables in its right hand side and whenever that happens the right hand side is re evaluated and the result immediately propagated to the left hand side out The continuous assignment statement is used to model combinational circuits where the out puts change when one wiggles the input Here is a structural specification of a module AND obtained by connecting the output of one NAND to both inputs of another one module AND inl1 in2 out Structural model of AND gate from two NANDS input inl in2 output out wire w1 two instantiations of the module NAND NAND NAND1 inl in2 wl NAND NAND2 w1 wl out endmodule This module has two instances of the NAND module called NAND1 and NAND2 connected together by an internal wire wl The general form to invoke an instance of a module is module name gt parameter list instance name gt port list where parameter list gt are values of parameters passed to the instance An example parame ter passed would be the delay for a gate Multisim User Guide B 1 7 Jewud Boje Verilog Primer Verilog HDL Primer B 1 8 The following module is a high level module which sets some test data and sets up the moni toring of variables module test AND High level module to test the two other modules reg a b wire outil out2 initial begin Test data a 0 b 20
328. languages The whole statement is done before control passes on to the next statement The non blocking lt operator evaluates all the right hand sides for the current time unit and assigns the left hand sides at the end of the time unit For example the following Verilog program Multisim User Guide B 1 15 Jewud Boje Verilog Primer Verilog HDL Primer testing blocking and non blocking assignment module blocking reg 0 7 A B initial begin initl A 3 1 A As 1 blocking procedural assignment B A 1 display Blocking A b B b A B A 3 1 A lt A 1 non blocking procedural assignment B lt A 1 1 display Non blocking A b B b A B end endmodule produces the following output Blocking A 00000100 B 00000101 Non blocking A 00000100 B 00000100 The effect is for all the non blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the cur rent time unit This reflects how register transfers occur in some hardware systems B 1 2 8 Tasks and Functions Tasks are like procedures in other programming languages e g tasks may have zero or more arguments and do not return a value Functions act like function subprograms in other lan guages Except 1 A Verilog function must execute during one simulation time unit That is no time control ling statements i e
329. lays and solid state indicator lamps LED Parameters and Defaults Symbol Parameter Name Default Unit IS Saturation current 1e 14 A RS Ohmic resistance 0 Ww CJO Zero bias junction capacitance 0 F VJ Junction potential 1 V TT Transit time 0 S M Grading coefficient 0 5 Multisim User Guide E 9 sepoiq Diodes Diodes Components E 5 Full Wave Bridge Rectifier The full wave bridge rectifier uses four diodes to perform full wave rec Ds tification of an input AC voltage Two diodes conduct during each half cycle giving a full wave rectified output voltage The top and bottom ter minals can be used as the input terminals for the AC voltage The left and right terminals can be used as the output DC terminals 3N246 E 5 1 Characteristic Equation The average output DC voltage at no load condition is approximately given by VDC 0636 Vp 1 4 where V the peak value of the input AC voltage E 5 2 Model A full wave bridge rectifier consists of four diodes as shown in its icon Terminals 1 and 2 are the input terminals so the input AC source is connected across 1 and 2 Terminals 3 and 4 are the output terminals so the load is connected across 3 and 4 When the input cycle is positive diodes D and D are forward biased and D3 and D are reverse biased D and D thus conduct current in the direction shown The voltage developed is identical to the positive half of the input sine wave minus
330. lb F 12 F 5 4 Time Domain Model cooccccccoc eh F 13 F 5 5 AC Small Signal Model ooccocccocccccc eese F 13 F 5 6 MOSFET Level 1 Model Parameters and Defaults F 14 JFETs Junction FETS ioe naaa i a rn F 15 EA DEMO E A E e T A EEE AEAEE F 16 F 6 2 JFET Model Parameters and DefaultS oooooccooccocoo ooo F 18 Power MOSFET N P ooocccccccc RR mm ru F 19 N Channel amp P Channel GaAsFET 0000 cece sees F 19 F 8 1 Model and Characteristic Equations 0000 cece eee F 19 F 8 2 GaAsFET Parameters and Defaults 00 00 e eee eee eee F 21 Multisim User Guide SJO SISUBA Transistors Electronics Workbench Appendix F Transistors Components F1 BJT NPN amp PNP A bipolar junction transistor or BJT is a current based valve used for con 41324 trolling electronic current BJTs are operated in three different modes depending on which element is common to input and output common base common emitter or common collector The three modes have different input and output impedances and different current gains offering individual advantages to a designer A transistor can be operated in its nonlinear region as a current voltage amplifier or as an elec tronic switch in cutoff and saturation modes In its linear region it must be biased appropri ately i e subjected to external voltages to produce a desired collector current to establish a proper DC op
331. le Source B 3 7 1 Explorer Open Explorer Opens a hierarchical Explorer window The Explorer displays the name of every module instance and variable in the design in a tree structure similar to the directory structure for the Windows Explorer The shift and control keys can be used to select variable names in a simi lar manner to the Windows Explorer Names can then be dragged and dropped to the other windows such as the Data Analyzer window and the Watch window The Explorer window Multisim User Guide B 3 19 snus 111 SOS Silos Ill Menus Silos III Menus also has pop up menus that can be accessed by using the right mouse button see Explorer Window The Explorer is multi threaded This enables you to use the Explorer or even simu late while the Explorer is working The hierarchical Explorer window is divided into two vertical windows with the hierarchy of module instances and gates listed in the left window and the variable names listed in the right window To traverse the hierarchy of the design in the left window click on the plus sign to the left of the instance or double click on module instances As each module instance or gate is selected in the left window the names of the variables in that instance are displayed in the right window Symbols to the left of the variables distinguish port variables the symbol is a pad from variables local to the instance the symbol is a box with an X for logic variables R for
332. le bit may be referenced by a variable For example reg 0 7 A B B 3 A 0 B 3 b111 ILLEGAL indices MUST be constant A B 1 b1 A single bit reference is LEGAL Why such a strict requirement of constant indices in register references Since we are describ ing hardware we want only expressions which are realizable Memories are specified as vectors of registers For example Mem is 1K words each 32 bits reg 31 0 Mem 0 1023 The notation Mem 0 references the zeroth word of memory The array index for memory register vector may be a register Notice that one can not reference a memory at the bit level in Verilog HDL If you want a specific range of bits in a word of memory you must first trans fer the data in the word to a temporary register B 1 2 4 2 Abstract Data Types In addition to modeling hardware there are other uses for variables in a hardware model For example the designer might want to use an integer variable to count the number of times an event occurs For the convenience of the designer Verilog HDL has several data types which do not have a corresponding hardware realization These data types include integer real and time The data types integer and real behave pretty much as in other languages e g C Be warned that a reg variable is unsigned and that an integer variable is a signed 32 bit integer This has important consequences when you subtract time variables hold 64 bit quantiti
333. le rail outputs D type flip flop truth table INPUTS OUTPUTS G CLK DATA Q 9 1 X X 00 Qo 0 1 1 0 0 A 0 0 1 X 0 X Qo 00 P 5 11474xx38 Quad 2 In NAND OC This device contains four independent 2 input NAND gates For correct performance the open collector outputs require pull up resistors Logic function NAND gate truth table P 5 11574xx39 Quad 2 In NAND OC This device contains four independent 2 input NAND gates For correct performance the open collector outputs require pull up resistors Logic function Y AB P 60 Electronics Workbench 74XX NAND gate truth table P 5 11674xx390 Dual Div by 2 Div by 5 Counter The 74390 device incorporates dual divide by two and divide by five counters BCD count sequence truth table OUTPUT COUNT QD QC QB QA 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 Notes Output QA is connected to input B for BCD count Multisim User Guide P 61 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series Bi quinary truth table OUTPUT COUNT QA QD QC QB 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 1 0 0 0 6 1 0 0 ab 7 1 0 1 0 8 1 0 1 1 9 1 1 0 0 Notes Output QD is connected to input A for bi quinary P 5 11774xx393 Dual 4 bit Binary Counter This device features an independent active high clear and clock input
334. les Gallery readline vector file file line Reads one complete line into file line read file line str stimulus in Extracts the first field from file line stimulus in str2vec str stimulus in Converts the input string to a vector wait for 1 ns Delays for a nanosecond Clr stimulus in 33 Gets each input s Load stimulus in 32 value from the test Data in stimulus in 31 downto 16 vector array and assigns the values S expected stimulus in 15 downto 0 wait until falling edge Clk Waits until the clock goes back to 0 midway through the clock cycle if S S expected then err cnt err cnt 1 assert false Increments the error counter and reports an error if different report Vector failure amp lf amp Expected S to be amp vec2str S expected amp lf amp but its value was amp vec2str S amp lf severity note end if end loop Continues looping through the file done lt 1 Sets a flag when we are finished this will stop the clock wait Suspends the simulation end process end stimulus Multisim User Guide A 37 JOWUd TAHA VDHL Prrimer VHDL Primer A 38 Electronics Workbench Appendix B 1 Verilog HDL Primer B 1 1 B 1 2 B 1 3 Introduction 432 erbe re A d ONE E Xu 1 B 1 1 1Whatis Verilog csse cd e Feds 1 B 1 1 2Why Use Verilog HDL 2 2222 222er ernennen nh 2 The Verilog Language
335. lexical conventions are close to the programming language C Comments are desig nated by to the end of a line or by to across several lines Keywords e g module are reserved and in all lower case letters The language is case sensitive meaning upper and lower case letters are different Spaces are important in that they delimit tokens in the language Numbers are specified in the traditional form of a series of digits with or without a sign but also in the following form lt size gt lt base format gt lt number gt where lt size gt contains decimal digits that specify the size of the constant in the number of bits The lt size gt is optional The lt base format gt is the single character followed by one of the following characters b d o and h which stand for binary decimal octal and hex respec tively The lt number gt part contains digits which are legal for the lt base format gt Some examples 549 decimal number h 8FF hex number 10765 octal number 4 b11 4 bit binary number 0011 3 b10x 3 bit binary number with least significant bit unknown 5 d3 5 bit decimal number 4 b11 4 bit two s complement of 0011 or 1101 Multisim User Guide B 1 5 Jewud Boje Verilog Primer Verilog HDL Primer The lt number gt part may not contain a sign Any sign must go on the front A string is a sequence of characters enclosed in double quotes this is a string Operators are one two or
336. lloscope 2 B Xposition 0 00 E Hy ve a ABl Channel A 1 Y position 0 00 acj ol 0c DIE C 18 Voltage Controlled Triangle Wave hd Ay 1v a C 12 Electronics Workbench Voltage Controlled Triangle Wave C 18 1 The Component This oscillator is identical to the voltage controlled sine wave oscillator except that it outputs a triangle wave This oscillator takes an input AC or DC voltage which it uses as the indepen dent variable in the piecewise linear curve described by the control frequency pairs From the curve a frequency value is determined and the oscillator outputs a triangle wave at that frequency When two co ordinate pairs are used the oscillator outputs a linear variation of the frequency with respect to the control input When the number of co ordinate pairs is greater than two the output is piecewise linear You can change the rise time duty cycle and the peak and valley values of the output triangle wave by resetting the Output peak high value and Out put peak low value on the model parameter dialog box C 18 2 Example The example shows a triangle wave generator with output frequency determined by a control voltage Control voltage may be DC controlled by a potentiometer as is the case for many signal gen erators and function generators Control voltage may be a continuous variable of any desired shape as required in sweep gen erators and spectrum analysers In the example
337. log v 1 2 2 v 3 4 v 2 v 1 i 17 gt To use the nonlinear dependent source 1 Double click the component 2 Type the algebraic expression Note Tf the dependent variable is V the output is in volts if the dependent variable is T the output is current C 25 Controlled One Shot This oscillator takes an AC or DC input voltage which it uses as the independent variable in the piecewise linear curve described by 95Y0Y1Y the control pulse width pairs From the curve a pulse width value is determined and the oscillator outputs a pulse of that width You can change clock trigger value output delay from trigger output delay from pulse width output rise and fall times and output high and low values When only two co ordinate pairs are used the oscillator outputs a linear variation of the pulse with respect to the control input When the number of co ordinate pairs is greater than two the output is piecewise linear Multisim User Guide C 23 seounos Sources Sources Components C 24 Electronics Workbench Appendix D Basic Components Dich SGonneclorS TA D 1 DZ Mile aci ar Reue a E aaa studs D 1 D 3 RESISTOR Dr D 2 D 3 1 Resistor Background Information 0 0000 eee ee D 3 D3 2 About Biesistance sv DUE elek D 3 D 3 3 Characteristic Equation oocoocoocccoocrcrr nen D 4 D 3 4 Resistor Virtual lille D 4 D 4 Capacitan Rs A pu ee D 4 D 4 1 Capaci
338. lop input stimulus in the form of a test bench for testing purposes The actual oper ation of the circuit however is not included in the entity declaration The following entity declaration contains a simple design description entity compare is port A B in bit vector 0 to 7 EQ out bit end compare The entity declaration includes a name compare and port declaration statement defining all the inputs and outputs of the entity The port list includes definitions of three ports A B and EQ Each of these three ports is given a direction in out or inout and a type in this case Electronics Workbench Learning VHDL either bit vector 0 to 7 which specifies an 8 bit array or bit which represents a single bit value There are many different data types available in VHDL To keep this introductory circuit sim ple the simplest data types in VHDL bit andbit vector will be used A 2 3 Architecture Declarations Every entity declaration you write must be accompanied by at least one corresponding archi tecture The architecture declaration for the comparator circuit is as follows architecture comparel of compare is begin EQ lt 1 when A B else 0 end comparel The architecture declaration begins with a unique name comparel followed by the name of the entity to which the architecture is bound in this case compare Within the architec ture declaration between the begin and end
339. lorer Open Explorer B 3 10 5Window Watch Opens the Watch window that can be used to display the state value for specified variables and expressions as you single step through the design Variables or expressions can be dragged and dropped into the Watch window from any source file window from the Explorer window and from the Data Analyzer window The Watch window also has a pop up menu for setting and forcing variables to a value The pop up menu can be accessed by using the right mouse button B 3 10 6Window Data Analyzer Opens the Data Analyzer window that can be used to display the waveforms for specified variables and expressions as you single step through the design Variables or expressions can be dragged and dropped into the Signal window for the Data Analyzer from any source file window and from the Explorer window B 3 26 Electronics Workbench Window Menu The Data Analyzer window displays the logic simulation results as waveforms The list box to the left of the waveforms shows the signal s Name its Scope and the Value of the sig nal at either the left axis of the waveform window or the T1 timing marker The Scope rep resents the hierarchical path for the signal name To copy the waveform display to Microsoft Word choose Edit Copy when the Data Analyzer window has the focus and then paste it into Word For pop up menu click in the gray area above Zoom Buttons Scan Buttons Pan Buttons the ti
340. lt in a increase in speed as SILOS III automatically indexes a library file that is sequential access the first time it is used Examples chglib cmos12 lib cmos12 dat cmosi3 dat cmosi4 dat chglib encode chip library chip dat B 2 2 5 Control Parameters For Logic Simulation B 2 30 The CONTROL command enables you to modify the parameters that con trol logic simulation The general format of the CONTROL command is CONTROL COMMENT c CUSTREPORT DISK val DISABLECACHE DMIN DMAX EUNK val MXITR val MXDCI val Electronics Workbench Silos III Command Line Usage NONCON SYNONYM val SKIP val val C string control COMMENT CUSTREPORT DISABLECACHE DISK DMAX DMIN Multisim User Guide SAVCELL val SAVSIM val TPS qual XL ORDER val represents the numerical value assigned to the control parameter represents a single character represents the prompt string indicates that the default simulation control parameters are to be modified specifies the comment character Default COM MENT specifies that the save file will be used in a Custom Report Default not specified turns off the caching mechanism for the Data Analyzer Turning off the caching may reduce the RAM memory used by SILOS Ill however it may make the Data Ana lyzer slower The cache is used to remember in RAM memory the simulation data that you have viewed with the Data Analyzer For
341. ly difference is that the IEEE 1164 standard logic data types std ulogic and std_ulogic_vector will be used rather than the bit andbit vector data types used previously Using standard logic data types for all system interfaces is highly recom mended as it allows circuit elements from different sources to be easily combined It also pro vides you the opportunity to perform more detailed and precise simulation than would otherwise be possible The updated comparator design using the IEEE 1164 standard logic data types is shown below Eight bit comparator library ieee use ieee std logic 1164 all entity compare is port A B in std ulogic vector 0 to 7 EQ out std ulogic Multisim User Guide A 11 JOWUd TAHA VDHL Prrimer VHDL Primer end compare architecture comparel of compare is begin EQ lt 1 when A B else 0 end comparel Reading from the top of the source file you can see the following e a comment field indicated by the leading double dash symbol VHDL allows com ments to be embedded anywhere in your source file provided they are prefaced by the two hyphen characters as shown Comments in VHDL extend from the double hyphen symbol to the end of the current line There is no block comment facility in VHDL alibrary statement that causes the named library IEEE to be loaded into the current compile session When you use VHDL libraries it is recommended that you include you
342. lysis the inductor is modeled by an impedance with its imaginary component equal to 27fL where f frequency of operation of the circuit L inductance value D 5 6 Inductor Virtual L3 rn 1mHz This component performs in the same way as an inductor but has a user settable value D 6 Transformer The transformer is one of the most common and useful applications of u inductance It can step up or step down an input primary voltage V1 to Dur a secondary voltage V2 The relationship is given by V1 V2 n 4 E where n is the ratio of the primary turns to the secondary turns The Tts auoio 4p ro 4 Parameter n can be adjusted by editing the transformer s model To properly simulate the transformer both sides must have a common reference point which may be ground The transformer can also be used in a center tapped configuration A center tap is provided which may be used for this purpose The voltage across the tap is half of the total secondary voltage This transformer is suitable for getting quick results To simulate realistic devices that include a transformer you should use the nonlinear transformer Note Both sides of a transformer must be grounded D 10 Electronics Workbench Transformer D 6 1 Characteristic Equation The characteristic equation of an ideal transformer is given by V nV T i i n where V primary voltage secondary voltage turns ratio primary current
343. m and the whole structure is deposited on a substrate often of alumina Capacitors of this type capacitors appear to be lumped up to 3 GHz and values from 0 1 to 10 pF can be achieved However because of their structure they require a relatively large area RF Inductor ET From many types of RF inductors spiral inductors provide higher induc tance values and higher Qs The spiral inductor is a technique of forming a planar inductor in a small place The shape is described by an increasing SAMPLE radius with angle i e R 7 I k0 Multisim User Guide M 1 Ju RF RF Components M 3 M 4 M 2 The equivalent circuit is a combination of series resistor due to skin effect and inductor and shunt capacitors due to the distance between the surface which embraces the conductor and the ground plane The quality of the inductor usually noted as Q is higher for spiral induc tors than those of other types of inductors such as the rectangular spiral RF Bipolar Resistors erg sa designed for low frequencies RF transistors however have a higher maxi di Basic operation of an RF bipolar transistor is identical to that of transistors mum operating frequency W depending on base and collector transit and charging times To achieve this the physical size of emitter base collector areas at the layout level are minimized However reduction in the base area is limited by the technology used to fabricate the transistor Red
344. m mmhos to kmhos 1Mho G louT VIN Current Controlled Current Source The magnitude of the current output of a current controlled current source depends on the current through the input terminals The two are related by a 1wA parameter called current gain F which is the ratio of the output current to the input current The current gain can have any value from mA A to kA A 12 _ lout lin F Voltage Controlled Sine Wave v4 t LAD ovv The Component This oscillator takes an input AC or DC voltage which it uses as the independent variable in the piecewise linear curve described by the control frequency pairs From the curve a fre quency value is determined and the oscillator outputs a sine wave at that frequency When Electronics Workbench Voltage Controlled Sine Wave only two co ordinate pairs are used the oscillator outputs a linear variation of the frequency with respect to the control input When the number of co ordinate pairs is greater than two the output is plecewise linear You can change the peak and valley values of the output sine wave by resetting the Output peak high value and Output peak low value on the model param eter dialog box C 16 2 Example The example shows a sine wave generator with output frequency determined by a control voltage Control voltage may be DC controlled by a potentiometer as is the case for many signal gen erators and function generators or may be t
345. mand coocccc res B2 63 B 2 9 3 TTE ES Parts Eist in 22 E eu nS dente dns ls kiss B2 64 B 2 3 4TTL BCT Pans List eisir aia a aaa eee B2 73 Multisim User Guide SUOISUSIXF JAH BOMA Verilog HDL Extensions Electronics Workbench Appendix B 2 Extensions B 2 1 Verilog HDL Extensions B 2 1 1 SILOS III PLI Interface SILOS III dynamically interfaces the user written or vendor supplied Programming Language Interface PLI routines with the SILOS III executable at runtime Interfacing the PLI rou tines at run time has the following advantages The user does not have to create a new SILOS III executable or have a different executable for each set of vendor supplied PLI routines Dynamically linking the PLI routines at runtime is faster than having to recompile and create a new executable each time Upgrading to new versions of SILOS III is simple because there is no need to recompile and create a new executable B 2 1 1 1SILOS Ill PLI Interface on the PC The PLI can be used with SILOS III on Windows NT version 4 0 and greater and on Win dows 95 and Windows 98 Contact Simucad for an updated list of supported platforms You may also need a C compiler such as the MS Visual C compiler to compile any user writ ten PLI routines and to create a dll file to link with SILOS III To use PLI on the PC plat form Create one or more dll files that contain the object code for the PLI The object code must have been comp
346. meline with the right mouse button IB SILOS c silos3Xekamples il spi Debug iD eta Analyzer Of x FT Ble View Project Axslorer Debug Opli hs Window Help 18 x ajajaja ul HA gt 1 13 Name Scope value 73us P8035 283 E Default clock stimulus St cain 1 0 stimulus none Hime none newspaper stimulus su po EE resel slimulus S0 NEXT STATE 0 stimulus vendY 0 cents 0 cents PRES STATE I stimulus vendY 15 cents q Cents D cents into 3b 1 stimulus adding adding coins clock amp amp coin 1 stimulus S10 clk news gt Fat Han press Fl T1 7870s T2 fihus Tdeta f ria Time 1 Rf 7 N Default DisplayFor pop up menu click in Timing information shownin T1 and T2 Timing Group the Name list box with the Status Bar Holding cursor Markers right mouse button above the timeline also shows timing B 3 10 6 1 Digital and Analog Signal Display Digital Signals For digital signals simulation results are displayed with waveforms denoting signal levels and colors denoting signal strength on color monitors e Supply strength black Multisim User Guide B 3 27 snu III SOS Silos III Menus Silos III Menus B 3 28 e Strong strength blue e Pull strength green High Z Unset and Uncertain strength red mixed strength for inserted groups and vectors purple Either the High level or Low level for the signal tra
347. module and the variable names can not be put on the table line The name of the stimulustable is used to determine which stimulustable is updated The file below test v shows the top level module with a stimulustable that is simulated until the finish is encountered Electronics Workbench Verilog HDL Extensions File test v Icon ext stim timescale 1ns 100ps module main reg 8 0 r9 reg 17 initial begin stimulustable s1 table 10 b r9 fd 000000000 T 000010000 0 111111111 Xx 100000001 0 endtable endstimulustable 10 Sfinish end endmodule Isim include testl v The next file testl v shows the new stimulustable values To simulate the new values use include to input file test1 v Notice that the delta delay value was changed from 10 for the first version of stimulustable s1 to 20 for the second version of stimulustable s1 The command sim 0 2100m will restart the simulation at time 0 and simulate until the Sfinish in file test v File testl v stimulustable s1 table 20 001100000 0 011010000 x IITITLIITI Xx 100010001 T endtable endstimulustable sim 0 2100m Multisim User Guide B 2 13 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 14 B 2 1 3 11Changing Behavioral Stimulus to a stimulust able Format Using a stimulustable statement instead of behavioral stimulus has the following advantage e The stimulustable is input in
348. mp test input BCD to seven segment decoder driver truth table DECIMAL INPUTS OUTPUTS NOTE OR BI RBO FUNCTION LT RBI D c B A a b c d e f g 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 X 0 0 0 1 1 0 S ao Or OR 1 2 i X 0 0 1 0 1 f E 0 de 1 0 1 3 1 X 0 0 1 1 1 Bl Br N 000 4 1 X 0 d 0 0 1 Q p T 0 50 E d 5 1 X 0 1 0 1 1 1 0 1 1 0 1 1 6 1 X 0 1 1 0 1 1 0 1 1 1 1 1 7 1 X 0 1 1 1 1 1 1 1 0 0 0 0 1 8 Ac x 74 0 0 0 1 LAO A he AL 9 d x 7d 0 0 1 1 io GO 3d bo 0 1 1 10 io Xo 7d 0 1 0 1 0 00 v sE S 586 4 11 U Xd 0 1 1 1 Qs d db cu o0 4 12 1 o UX Oi X 0 0 1 0 1 7 0 0 0 1 TA 13 io Xs b 4 0 1 1 Te 200 S0 EO 00 ER 14 qo X ood d 1 0 1 Q 20 50 vde i DE 15 w X ale ecd 1 1 1 o 0 0 0 0 0 0 BI X X X X X X 0 0 0 0 0 0 0 0 2 RBI 1 0 0 0 0 0 0 0 0 0 0 0 O0 O0 3 LT E XC Xe 2X 7X 1 d 1 82 A XE d 4 Notes 1 The blanking input BI must be open or held at a high logic level when output functions 0 through 15 are desired The ripple blanking input RBI must be open or high if blanking of a decimal zero is not desired When a low logic level is applied to the blanking input BI all segment outputs are low regardless of any other input When ripple blanking input RBI and inputs A B C and D are at a low level with the lamp test input high all segment outputs go low and the ripple blanking output RBO goes to a low level response condition When the blanking input ripple blanking output BI R
349. mparator has a reference of 1 3 V The comparator s output controls the state of the flip flop and hence the output When the trigger voltage goes below 1 3 Vec the output of the lower comparator goes high and the flip flop sets The output thus jumps to a high level The threshold input is normally connected to an external RC timing network When the external voltage exceeds 2 3 V the upper comparator s output goes high and resets the flip flop which in turn switches the output back to the low level When the device output is low the discharge transistor Q is turned on and provides a path for the discharge of the external tim ing capacitor This basic operation allows the timer to be configured with external components as an oscilla tor a monoshot or a time delay element Mono Stable u1 O MONO_STABLE tivibrator This component produces an output pulse of a fixed duration in response to an edge trigger at its input The length of the output pulse is controlled by the timing RC circuit connected to the monostable mul Multisim User Guide 1 3 pexiN Mixed Mixed Components 1 4 1 1 5 Model A monostable multivibrator has two digital inputs Al and A2 The multivibrator can be trig gered by a positive edge of digital signal at Al or a negative edge at A2 Once triggered it ignores further inputs An RC combination connected to RT CT and CT pins controls the duration of the pulse pro duced by the m
350. mponent component rotate port Clk Rst Load in std ulogic Data in std ulogic vector 0 to 7 Q out std ulogic vector 0 to 7 end component signal Q std ulogic vector 0 to 7 begin COMP1 compare port map A gt Q B gt Test EQ gt Limit A 20 Electronics Workbench Learning VHDL ROT1 rotate port map Clk gt Clk Rst gt Rst Load gt Load Data gt Init Q gt Q end structure A 2 6 8 Test Benches At this point the sample circuit is complete and ready to be processed by synthesis tools Before processing the design however you should take the time to verify that it actually does what it is intended to do You should run a simulation Simulating a circuit such as this one requires that you provide more than just the design description itself To verify the proper operation of the circuit over time in response to input stimulus you will need to write a test bench The easiest way to understand the concept of a test bench is to think of it as a virtual tester cir cuit This tester circuit which you will describe in VHDL applies stimulus to your design description and optionally verifies that the simulated circuit does what it is intended to do The diagram below graphically illustrates the relationship between the test bench and your design description which is called the unit under test or UUT To apply stimulus to your design your test bench will probably be written using one or more sequential
351. mulation time point for a variable or expression in the source window can be toggled on or off with Options Data Tips Any variable or expression in a source window can be viewed by opening the source window and holding the mouse cursor over a variable or by highlighting an expression and holding the mouse cursor over the expression This feature enables you to trace the cause of problems directly in a Verilog HDL source code window Open Module Source can be used to quickly display the module definition for any instance in the hierarchy This saves time opening the source window for displaying the value for variables and expressions when there are numerous files in the design B 3 10Window Menu The Window menu provides the following commands e Window Cascade e Window Tile e Window Arrange Icons e Window Explorer e Window Watch e Window Data Analyzer Multisim User Guide B 3 25 snus 111 SOS Silos II Menus Silos III Menus B 3 10 1Window Cascade Arranges multiple opened windows in an overlapped fashion B 3 10 2Window Tile Arranges multiple opened windows in a non overlapped fashion B 3 10 3Window Arrange Icons Arranges icons for the minimized windows B 3 10 4Window Explorer Opens the hierarchical Explorer window that displays the name of every module instance and variable in the design in a tree structure similar to the directory structure for the Windows Explorer for more information see Exp
352. n f t dt The low pass filter is modeled by a simple passive RC low pass filter that is a resistor and a capacitor where R is 100 kW and 1 2m f R The voltage controlled oscillator VCO is modeled by fO fe ae EV po 21 f dt where fi input frequency fp low pass filter pole location fo VCO output frequency fc VCO free running frequency Va phase detector output DC voltage Vo VCO output voltage Ko VCO conversion gain Kg phase detector conversion gain Qj input signal phase Po VCO output phase Multisim User Guide 1 5 pexiN Mixed Mixed Components 1 5 2 Phase Locked Loop Parameters and Defaults Symbol Parameter name Default Unit Kd Phase detector conversion gain 1 0 V rad Ko VCO conversion gain 1 0 Hz V fc VCO free running frequency 10 kHz fp Low pass filter pole location 100 kHz Vom VCO output amplitude 5 0 V Rconv Convergence aid resistance 100 MQ Electronics Workbench Appendix J Indicators Components J 1 J 2 J 3 J 4 J 5 J 6 J 7 Voltimeter rb dee a o dba AMA US PP ERN ER J 1 J 1 1 Resistance 1 0 W 999 99 TW lsssessese eee J 1 3 1 2 Mode DC or AC an uie re labra J 1 J 1 8 Connecting a Voltmeter 0 2 00 eee J 2 AMME 2x ee o eared epee ea de had toute dalek ad touts J 2 J 2 1 Resistance 1 0 pW 999 99 W 2 2 con nennen ee J 2 4 2 2 Mode DG Or AQ iis Tieri aide RR Sewanee re
353. n Sel 00 else B when Sel 01 else C when Sel 10 else D when Sel 11 t Electronics Workbench Learning VHDL end muxl Selected Signal Assignment This form of signal assignment can be used as an alternative to the conditional signal assign ment The selected signal assignment has the following general form again using a multi plexer as an example architecture mux2 of mux is begin with Sel select Y wm A when 00 B when O1 C when 10 D when 11 end mux2 Choosing between a conditional or selected signal assignment for circuits such as this is largely a matter of taste For most designs there is no difference in the results obtained with either type of assignment statement A 2 6 3 Barrel Shifter Entity The second and most complex part of this design is the barrel shifter circuit This circuit dia grammed below accepts 8 bit input data loads this data into a register and when the load input signal is low rotates this data by one bit with each rising edge clock signal The circuit is provided with an asynchronous reset and the data stored in the register is accessible via the output signal Q They are many ways to describe a circuit such as this in VHDL If you are going to use syn thesis tools to process the design description into an actual device technology however you must restrict yourself to well established synthesis conventions when entering the circuit Two of th
354. n Simulation and Debug with Multisim s Verilog HDL Electronics Workbench Verilog HDL Extensions B 2 1 4 Analog Extensions Simucad has added extensions to the Verilog Hardware Description Language HDL that allow SILOS III to model analog circuits at the behavioral level B 2 1 4 1Real and Integer Data Types SILOS III supports real and integer data types as defined by the IEEE P1364 Standard Verilog HDL Language Reference Manual To facilitate analog behavioral modeling SILOS III also supports the following unique extension to the Verilog language Real floating point and integer variables can be passed between module ports The advantages of directly passing real and integer variables between modules are ease of programming style e no loss of information as occurs with other Verilog simulators Passing numerical values between behavioral modules is particularly useful when modeling analog behavior for circuits such as analog to digital converters phase lock loops charge pumps etc For an example of an analog to digital converter see file analog v in the exam ples subdirectory of the installation directory B 2 1 4 2Utility Transcendental Functions To simplify the implementation of analog models SILOS III supports a full range of transcen dental math functions The following functions accept a single floating point argument x and return a floating point value except for pow which has two floating point
355. n clock input CPD an asyn chronous parallel load input PL four parallel data inputs PO to P3 an asynchronous master reset input MR four counter outputs OO to O3 an active LOW terminal count up carry output TCU and an active LOW terminal count down borrow output TCD Electronics Workbench 4000 Series ICs 0 2 23 40193 4 bit Bin Counter 45 3 Se oo 4 Po 2 gt 01 L 10 6 s 7 ls o3 11 O PL 12 5 TCU D cru 13 4 Teo p sa P cro MR The 40193 device is a 4 bit synchronous up down binary counter with a count up clock input CPU a count down clock input CPD an asyn chronous parallel load input PL four parallel data inputs PO to P3 an asynchronous master reset input MR four counter outputs O0 to O3 an active LOW terminal count up carry output TCU and an active LOW terminal count down borrow output TCD 0 2 24 40194 4 bit Shift Register 2 3 OSR 3 P o0 z7r 01 g P2 02 T 03 DSL 3 40 0 711 1 TP CP sal ela The 40194 device is a 4 bit bidirectional shift register with two mode control inputs SO and S1 a clock input CP a serial data shift left input DSL a serial data shift right input DSR four parallel data inputs PO to P3 an overriding asynchronous master reset input MR and four buffered parallel outputs OO to O3 0 2 25 40195 4 bit Shift Register 4 Po 00 1
356. n the Analysis Monte Carlo dialog box To set the tolerance explicitly de select Use global tolerance and enter a value in the capacitance tolerance field The variable capacitor is simulated as an open circuit with a current across the capacitor forced to zero by a large impedance value The polarized capacitor must be connected with the right polarity Otherwise an error mes sage will appear Its capacitance measured in farads can be any value from pF to F D 4 Electronics Workbench Capacitor D 4 1 D 4 2 D 4 3 Capacitor Background Information Capacitors in an AC circuit behave as short circuits to AC signals They are widely used to filter or remove AC signals from a variety of circuits AC ripple in DC power supplies AC noise from computer circuits etc Capacitors prevent the flow of direct current in a DC circuit They can be used to block the flow of DC while allowing AC signals to pass Using capacitors to couple one circuit to another is a common practice Capacitors take a predictable time to charge and discharge and can be used in a variety of time delay circuits They are similar to inductors and are often used with them for this pur pose The basic construction of all capacitors involves two metal plates separated by an insulator Electric current cannot flow through the insulator so more electrons pile up on one plate than the other The result is a difference in voltage level from one plate t
357. nable inputs ED and ED a common clock input CP four 3 state outputs Oo to O4 two active LOW output enable inputs EO and EO and an overriding asyn chronous master reset input MR O 31 seues 000p suonounJ Functions 4000 series Functions 4000 Series D type register truth table INPUTS OUTPUTS MR CP EDO ED1 Dn On X X X X 0 0 al X X NO CHANGE 0 X X NO CHANGE 0 0 0 4 I 0 0 0 0 0 0 i X X X NO CHANGE O 2 59 4077 Quad 2 In XNOR This device contains four independent 2 input EXCLUSIVE NOR gates Logic function O AGB EXCLUSIVE NOR gate truth table O 2 60 4078 8 In NOR Logic function O 32 Ipg 1 12 13 1 15 1g 17 Electronics Workbench 4000 Series ICs 8 input NOR gate simplified truth table If one or more inputs are high the output is low INPUTS OUTPUT IO I1 I2 I3 I4 I5 I6 I7 ol 0 0 0 0 0 0 0 0 B 1 X X X X X X X 0 X T X X X X X X 0 X X 1 X X X X X 0 X X X 1 X X X X 0 X X X X 1 X X X 0 X X X X X 1 X X 0 X X X X X X 1 X 0 X X X X X X X 1 0 O 2 61 4081 Quad 2 In AND 3 a This device contains four independent 2 input AND gates Logic function Y AB AND gate truth table Fr oo w A 0 l 0 1 O 2 62 4082 Dual 4 In AND Multisim User Guide FOO O K This device contains two independent 4 input AND gates All 4 inputs on each 4 input gate must be high to obtain a high at the output 0
358. nable portfaults and nosuppress faults and disable portfaults around every module in a library file The library file can be specified using the y and v command line options the library com mand or the Project Files dialog box no pulse msg The command line option no pulse msg turns off the pulse messages This does the same thing as the pulse quiet command line option notimingchecks This option disables all timing checks improving speed and reducing memory used no_tchk msg This option suppresses timing check violation messages Timing checks are still processed but no messages are printed to standard output if there is a tim ing check violation nowarntfmpc This option suppresses the warning message for a mismatch in the number of port connections plusargs You can enter command line arguments that are project specific such compare sdf etc For example suppose you wanted to specify the SDF file only when you entered sdf in the plusargs box for the Project Settings dialog box Then your test bench may look like Electronics Workbench Silos III Command Line Usage module test bench initial if Stest plusargs sdf sdf annotate test sdf only execute if sdf is an argument endmodule e pulse r n and pulse e n command line arguments specify a range of pulse widths that will propagate to the path destination For pulse r n n specifies a number in the range 0
359. nal and registered portions of the circuit The following VHDL design description uses this method to describe the same barrel shifter circuit previously described architecture rotate3 of rotate is signal D Qreg std logic vector 0 to 7 begin D lt Data when Load 1 else Qreg 1 to 7 amp Qreg 0 dff Rst Clk D Qreg Q lt Qreg end rotate3 In this version of the design description the behavior of the D type flip flop has been placed in an external procedure dff and intermediate signals have been introduced to more clearly describe the separation between the combinational and registered parts of the circuit The fol lowing diagram helps illustrate this separation Inputs Logic Registers Outputs A 18 Electronics Workbench Learning VHDL In this example the combinational logic of the counter has been written in the form of a single concurrent signal assignment while the registered operation of the counter s output has been described using a call to a procedure named df f What does the d f procedure look like The following is one possible procedure for a D type flip flop procedure dff signal Rst Clk in std ulogic signal D in std ulogic vector 0 to 7 signal Q out std ulogic vector 0 to 7 is begin if Rst 1 then Q 00000000 elsif Clk 1 and Clk event then Q lt D end if end dff Notice that this procedure has a striking resemblance to the process statement pr
360. names such as a data read etc B 3 12 1 3Copy Scope Located in the pop up menu in the left hand Tree side of the Explorer window When you select a hierarchical instance in the Explorer window the Copy Scope command or simulta neously holding down the CTRL and C keys will copy the hierarchical instance name to the Windows Clipboard This enables you paste the hierarchical name simultaneously holding down the CTRL and C keys To use this command right click on any part of the left hand side of the Explorer window to open the pop up menu B 3 12 1 4Go to Module Source Located in the pop up menu in the left hand Tree side of the Explorer window When you select a hierarchical instance in the Explorer window the Go to Module Source command Multisim User Guide B 3 35 snus 111 SOS Silos Ill Menus Silos III Menus B 3 36 opens a source window that displays the source code for the hierarchical instance This enables you to quickly find the source code for any instance in your design To use this command right click on any part of the left hand side of the Explorer window to open the pop up menu B 3 12 1 5Go to Scope Menu Selection Located in the pop up menu in the left hand Tree side of the Explorer window This feature enables you to quickly find an instance in the Explorer window The Go to Scope command opens the Enter Scope screen where you specify the scope for the instance that yo
361. nce 1 0 pQ 999 99 2 The ammeter s resistance is preset to 1 mQ which presents little resistance to a circuit If you are testing a circuit that has low resistance you can lower the ammeter s resistance even fur ther to get a more precise measurement However using an ammeter with very low resistance in a high resistance circuit may result in a mathematical round off error Mode DC or AC The ammeter is preset to DC mode which measures only the DC component of a signal If you want to measure the current from an AC source change the mode to AC When set to AC the ammeter displays the root mean square RMS value of the alternating signal Connecting an Ammeter Like a real ammeter the simulated ammeter must be connected in series at nodes you want to measure The negative terminal is on the side with the heavy border If an ammeter is moved after the circuit has been simulated activate the circuit again to get a reading Electronics Workbench Probe LED J 3 Probe LED u1 The probe indicates high on or low off levels at any point in a digital circuit It O I lights up or turns off as the circuit is running You can change the color of the probe from the Choose Probe tab of the Circuit Component Properties dialog box J 4 Lamp The lightbulb is an ideal nonlinear resistive component that dissipates A energy in the form of light It has two rated values maximum power P nax and maximum voltage Vinax
362. nce is by default set to the global tolerance defined in the Analysis Monte Carlo dialog box To set the tolerance explicitly de select Use global tolerance and enter a value in the current tolerance field C 8 Clock Source This component is a square wave generator You can adjust its voltage vA amplitude duty cycle and frequency CLOCK_SOURCE C 9 Amplitude Modulation AM Source The AM source single frequency amplitude modulation source gen v2 erates an amplitude modulated wave It can be used to build and ana 1v 1000H2 100Hz yze communications circuits C 9 1 Characteristic Equation The behavior of the AM source is described by Vour ve sin 2 2 fc TIME 1 m sin 2 2 fm TIME C 4 Electronics Workbench FM Source C 10 C 10 1 C 10 2 where vc carrier amplitude in volts fc carrier frequency in hertz m modulation index fm modulation frequency in hertz FM Source The FM source single frequency frequency modulation source generates a frequency modu lated wave It can be used to build and analyze communications circuits The signal output can be either a current source or a voltage source FM Voltage Source v3 5v 1000Hz 100Hz Characteristic Equation This is an FM source of which the output is measured in voltage The behavior of the FM voltage source is described by Vour va sin 2 for TIME m sin 2 z fm TIME where va peak amplitude in
363. nd initial begin Multisim User Guide B 2 11 SUOISUSIXF JAH Bojan Verilog HDL Extensions Extensions B 2 12 Stimeformat 9 3 ns 15 monitor t realtime ExpectedValueError 5 stimulustable s1 table 1 2 inl in2 0 outlestrobel 00 00 Et 0e 0a f6 ff ff 00 endtable endstimulustable H10 Sfinish end endmodule The output from the monitor is shown below 6 300ns s1 outl fb f6 6 400ns 7 500ns s1 outl ff 00 7 600ns For the first line 6 300ns s1 outl fb f6 The 6 300ns is the time the difference occurred the s1 is the instance name for the stimu lustable the fb is the simulation value for variable out1 and the f6 is the expected value for out1 B 2 1 3 9Expected Value Error Storage The expected values are stored in variables that use the root name of the variable whose value is checked with an lt expected gt lt number gt appended to the name These variables can be accessed with the probe or print commands or viewed in the Data Analyzer B 2 1 3 10Incremental Update stimulustable data can be incrementally replaced without having to re input all the files in the design This allows quick iteration of different stimulus expected value patterns The incremental stimulustables can be specified at any time after preprocessing the prep com mand When specifying the incremental stimulustables each incremental stimulustable must be specified outside of any
364. nd moving the vertical line to the left or right Use the View menu to hide the Status Bar or Tool bars Grab the toolbars and move them to any part of your monitor display even outside of the SILOS III program Multiple Data Analyzers To open one or more Data Analyzer windows you can use the Open Analyzer button on the toolbar Each time the Analyzer is started it can be used to simultaneously display another copy of the simulation results No Saved Data Project Settings Lx plusargs define s DK Cancel Ensure these items are checked if you see No Saved Data in Data Analyzer Delay Selection Iv i v Save all sim data Typ Functional simulation Enable log file Max Sim File Size Enable Silos extensions Auto File Save 1000 Retain simulation data file Tabs la Disable floating node warnings Use Alternate Behavorial E valuation Order Command Line Arguments Simulation Data File Path Analyzer Symbol T able File C silos3 EXAMPLES R tl sym Browse If the Data Analyzer reports No Saved Data for a waveform check the following B 3 30 The Save celldefine data option in the Project Settings screen may need to be enabled Project Project Settings This will save the local variables for modules in library cells Electronics Workbench Help Menu that are bounded by celldefine and endcelldefine The Save all sim data option
365. nd voltages are reversed The DC characteristic of a BJT in Multisim is modeled by a simplified Gummel Poon model The base collector and base emitter junctions are described by their ideal diode equations The diode capacitors are treated as open circuits Electronics Workbench BJT NPN amp PNP The beta variation with current is modeled by two extra non ideal diodes The diode capaci tors are treated as open circuits The various equations are B Ise2 t exo NcVT Isc Hex 1 Vac 1 VA Ka VBE NeVT al E Is Kj exp 1 Z Koc Le 1 4Ko Ice RN on K e DE Hi VBC Vr lec AA exp i Kab IcT Ice Icc VBE IBE1 1 ex E VT lBc1 PES where Vr V V V J thermal voltage 0 0258 forward early voltage The model parameter is equivalent to Bpc in the DC case and Bac in the AC case Other symbols used in these equations are defined in BJT Model Parameters and Defaults Multisim User Guide F 3 SJO SISUBJ Transistors Transistors Components F1 2 Time Domain Model The BJT time domain model takes into account the parasitic emitter base and collector resis tances and also the junction diffusion and substrate capacitances The capacitors in the model are represented by their energy storage model derived using the appropriate numerical integration rule N ra eeu Ya ae eH C WV pp 9r SI afe
366. ndent 2 input NAND gates Logic function NAND gate truth table Electronics Workbench 74Xx P 5 2 74xx02 Quad 2 In NOR This device contains four independent 2 input NOR gates Logic function Y AGB NOR gate truth table P 5 3 74xx03 Quad 2 In NAND Ls OC This device contains four independent 2 input NAND gates For correct performance the open collector outputs require pull up resistors Logic function NAND gate truth table P 5 4 74xx04 Hex INVERTER This device contains six independent INVERTER gates Logic function Y A Multisim User Guide P 3 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series INVERTER gate truth table A Y 1 0 0 1 P 5 5 74xx05 Hex INVERTER OC This device contains six independent INVERTER gates For correct performance the open collector outputs require pull up resistors Logic function Y A INVERTER gate truth table A Y T 0 0 1 P 5 6 74xx06 Hex INVERTER OC This device contains six independent INVERTER gates For correct performance the open collector outputs require pull up resistors Logic function Y A INVERTER gate truth table A Y 1 0 0 al P 4 Electronics Workbench 74XX P 5 7 74xx07 Hex BUFFER OC This device contains six independent BUFFER non inverting gates For correct performance the open collector outputs require pull up resistors Logic function Y
367. ng induced voltage and current The transfer is proportional to the ratio of the winding turns Radio antennae are inductors that operate like transformers in generating and detecting elec tromagnetic fields Their efficiency is proportional to their size The ignition coil in an automobile develops a very high induced voltage when the current through it suddenly becomes very great This is the voltage that fires spark plugs Characteristic Equation The voltage across the inductor is equal to the inductance L multiplied by the change in cur rent through the inductor that is di dt v L DC Model In the DC model the inductor is represented by a short circuit Electronics Workbench Inductor D 5 4 Time Domain Model R is an equivalent resistance and i is an equivalent current source The expression for the Ry and ij depends on the numerical integration method used For trapezoid method Re h h lin Vi tin 2L For Gear method first order L Rin h h lin V L where Var present unknown voltage across the inductor ina present unknown current through the inductor Vh in previous solution values h time step n time interval These expressions are derived by applying appropriate numerical integration to the character istic equation of the inductor Multisim User Guide D 9 oiseg Basic Basic Components D 5 5 AC Frequency Model For the small signal ana
368. ng language In many cases you can choose whether to use signals or variables to perform the same task As a general rule you should use variables whenever possible and use signals only when you must access data across different concurrent parts of your design A 2 6 5 Using a Procedure Describing registered logic using processes requires that you follow some established conven tions if you intend to synthesize the design and to consider the behavior of the entire circuit In the barrel shifter design description shown in Process Statement on page A 14 the regis ters were implied by the placement and use of statements such as if Clk 1 and Clk event Assignment statements subject to that clause resulted in D type flip flops being implied for the signals Multisim User Guide A 17 JOWUd TAHA VDHL Prrimer VHDL Primer For smaller circuits this mixing of combinational logic functions and registers is fine and not difficult to understand For larger circuits however the complexity of the system being described can make such descriptions hard to manage and the results of synthesis can often be confusing For these circuits it often makes more sense to retreat to a dataflow level of abstraction and to clearly define the boundaries between registered and combinational logic One easy way to do this is to remove the process from your design and replace it with a series of concurrent statements representing the combinatio
369. nics Workbench Buck Converter K 9 1 Characteristic Equations The averaging DC and large signal characteristics of a Buck converter are given by the fol lowing sets of equations D D D L 1 p D D I U 1 I in which is governed by lr I zh D V V DV dt where D duty ratio of the switching device For the DCM pepe Vo Vi 0 Ip D Vi xp ee 2 Lx Fs For the critical condition between the CCM and DCM of operation D 1 D _ V Vo Iip l iori x ox Lx F S For the CCM D 1 D V DWV CV D V DA Ea Multisim User Guide OSIN K 11 Misc Misc Components The averaging behavior governed by the above equations is modeled using the built in Elec tronics Workbench analog behavioral modeling components The AC small signal model is automatically computed inside the program K 9 2 Buck Converter Parameters and Defaults Symbol Parameter Name Default Unit L Filter inductance 500 uH R Filter inductor ESR 5 ma Fs Switching frequency 50 kHz K 10 Buck Boost Converter A1 This component is an averaging circuit model that models the averag ing behavior of a DC to DC switching converter It is based on a uni soon 100hmsHe fied behavioral model topology The topology models both small signal and large signal characteristics of this converter power stage This behavioral model can be used to simulate DC AC and l
370. nics Workbench Verilog Libraries Ref BiCMOS Bus Interface Logic Data book SCBD0014A Revised July 1989 Multisim User Guide Name Description 74LS00 2 INPUT NAND 74LS01 2 INPUT NAND OC 74LS02 2INPUT NOR 74LS03 2 INPUT NAND OC 74LS04 HEX INVERTER 74LS05 HEX INVERTER 74LS08 2 INPUT AND 74LS09 2 INPUT AND OC 74LS10 SINPUT NAND 74LS11 3 INPUT AND 74LS12 3 INPUT HAND OC 74LS13 4 INPUT NAND SCHM TRIG 7ALS14 HEX SCHM TRIG INVERTER 74LS15 3 INPUT AND OC 74LS19A HEX SCHM TRIG INVERTER 74LS20 4 INPUT NAND 74SL21 4 INPUT AND 74LS22 4 INPUT NAND OC 74LS24A 2 INPUT NAND SCHM TRIG 74LS26 2 INPUT NAND OC 74LS27 3 INPUT NOR 74LS28 2 INPUT NOR 74LS30 8 INPUT NAND 74LS31 DELAY LINE 74LS32 2 INPUT OR B 2 65 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 66 Name Description 74LS33 2 INPUT NOR OC 74LS37 2 INPUT NAND 74LS38 2 INPUT NAND OC 74LS40 4 INPUT NAND 74LS42 BCD TO DECIMAL DECODER 74LS51 3 WIDE AND OR INV 74LS54 4 WIDE AND OR INV 74LS55 2 WIDE AND OR INV 74LS56 FERQUENCY DIVIDER 50 1 74LS57 FREQUENCY DIVIDER 60 1 74LS68 DECADE BINARY COUNTER 74LS69 DECADE BINARY COUNTER 74LS73A JK FLIP FLOP 74LS74A D FLIP FLOP 74LS75 LATCH 74LS76A JK FLIP FLOP 74LS77 LATCH 74LS78A JK FLIP FLOP 74LS83A ADDER 74LS85 COMP
371. nitial w 1 SILOS III command to allow this extension Icontrol ext paw 4 7 7 B 2 1 7 7Continuous assignments to register and mem ory variables example reg r assign r in SILOS III command to allow this extension control ext aar For more information see sections 5 1 and 11 1 of the Verilog HDL Reference on line help file B 2 1 7 8Continuous assignments using intra assign ment non blocking delays example module foo wire o o1 assign o 4 i Multisim User Guide B 2 21 Ssuoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 22 assign ol lt H4 i SILOS III command to allow this extension control ext assign For more information see section 5 1 of the Verilog HDL Reference on line help file B 2 1 7 9Default state value for UDP The default keyword for the UDP specifies the state value for the UDP s output when UDP input levels and transitions do not match any of the entries in the UDP table When the default keyword is not used the UDP default output state is x example primitive udp1 out in output out input in table in out 0 T default 0 endtable endprimitive SILOS III command to allow this extension control ext udpdefault For more information see section 7 1 of the Verilog HDL Reference on line help file B 2 1 7 10UDP additional states for High Z on inputs or output example for row states other than 0 x 1 such as Ze xd ETHW
372. ns 74XX series Functions 74XX Series P 5 10874xx373 Octal D type Transparent Latches This 8 bit register features three state bus driving outputs and transparent D type latches D latch and flip flop truth table OUTPUT ENABLE ENABLE LATCH D OUTPUT 0 d 1 1 0 1 0 0 0 0 X Qo AE X X Z Z High impedance off P 5 10974xx374 Octal D type FF edge This 8 bit register features three state bus driving outputs and transparent D type flip flops D latch and flip flop truth table OUTPUT ENABLE ENABLE LATCH D OUTPUT 0 1 A 0 0 0 0 0 X Qo 1 X Z Z High impedance off Transition from low to high P 58 Electronics Workbench 74XX P 5 11074xx375 4 bit Bistable Latches This device features outputs from a 4 bit latch Bistable latch truth table x FH ojl o onnu n ROJO Q o ol P 5 111 74xx377 Octal D type FF w en This device contains eight flip flops with single rail outputs D type flip flop truth table G CLK DATA Q Q 1 X X 00 00 0 1 1 0 0 0 0 1 X 0 X Qo 00 P 5 11274xx378 Hex D type FF w en This device contains six flip flops with single rail outputs D type flip flop truth table G CLK DATA Q Q 1 X X 00 Qo 0 1 1 0 0 0 0 1 X 0 X Qo Qo Multisim User Guide P 59 seues Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 11374xx379 Quad D type FF w en This device contains four flip flops with doub
373. ns at a node indicates an input test pattern s effectiveness Faults at nodes which make no level transitions cannot be detected 2 The t s ACTIVITY command can be used to generate the following reports e An activity table that lists the node names and their number of level transitions Either single output nodes or wired nodes are listed whose level transition count falls between the ACTIVITY report MNTRAN and MXTRAN values e An activity summary that lists totals for the number of nodes at each level of activity count e An activity histogram that shows known and potential level transitions versus time 3 A known transition is defined as a change from a Low to High level or High to Low level even if it goes through an intermediate Unknown level A possible transition is defined as a change from a High or Low level to the Unknown level or from the Unknown level back to a High or Low level Examples ST ACT ST ACTIV 400 TO 2000 store act 0 to 10000 MXT 1 STO AC 5K 2 5K NOTAB ty ac nos mxtran 10 mntran 3 B 2 2 3 Bus Contention Report B 2 28 The BUSCON command reports the logic simulation time points at which more than one tri triand trior trireg tri0 or tril net types or an enabled unidirectional device bufif1 bufif0 notifl notif0 nmos pmos rnmos and rpmos devices are simultaneously driving a node a bus contention To obtain a bus contention report enter TYPE
374. o the other Characteristic Equation The current through the capacitor is equal to C multiplied by the rate of change in voltage across the capacitor that is ENS at DC Model In the DC model the capacitor is represented by an open circuit D 4 3 1 Time Domain Model R is an equivalent resistance and i is an equivalent current source The expression for the R and i depends on the numerical integration method used Multisim User Guide D 5 oiseg Basic Basic Components For trapezoid method Ren RR 2C Len e T ln h For the first order Gear method Backward Euler h Roa C C len Vn h where Var present unknown voltage across the capacitor inet present unknown current through the capacitor Vh in previous solution values h time step n time interval These expressions are derived by applying appropriate numerical integration to the character istic equation of the capacitor D 6 Electronics Workbench Inductor D 4 4 AC Frequency Model For the small signal analysis the capacitor is modeled by an impedance whose imaginary component is equal to 1 22fC where f frequency of operation C apacitance value D 4 5 Capacitor Virtual c3 This component performs the same functions as a capacitor but has a user settable H value tuF D 5 Inductor An inductor stores energy in an electromagnetic field created by changes in cur mm rent through it It
375. o vr 15 SILOS III command to allow this extension control ext udpstate For more information see section 7 1 of the Verilog HDL Reference on line help file B 2 1 7 11UDP edge for High Z example for edges to High Z such as 02 1 SILOS III command to allow this extension Electronics Workbench Verilog HDL Extensions Icontrol ext udpstate For more information see section 7 1 of the Verilog HDL Reference on line help file B 2 1 7 12UDP Multiple Edges in a Row example 01 01 1 SILOS III command to allow this extension Icontrol ext udpstate For more information see section 7 5 of the Verilog HDL Reference on line help file B 2 1 7 13Non Constant Specify Block Delays example for non constant specify block delay such as in gt out delay var SILOS III command to allow this extension control ext ncsd For more information see section 13 1 of the Verilog HDL Reference on line help file B 2 1 7 14Parameter for Specify Block Delays example for parameter used for specify block delay such as parameter dly 8 in gt out dly SILOS III command to allow this extension Icontrol ext psd For more information see section 13 1 of the Verilog HDL Reference on line help file B 2 1 7 15Stimulustable Extension example for using the stimulustable statement such as stimulustable endstimulustable statement SILOS III command to allow this extension Icon
376. of code i e within an initial or always block Most of them will be familiar to the programmer of traditional programming languages like C The main difference is instead of C s brackets Verilog HDL uses begin and end In Verilog the brackets are used for concatenation of bit strings Since most users are familiar with C the following subsections typically show only an example of each construct Multisim User Guide B 1 13 Jewud Boje Verilog Primer Verilog HDL Primer B 1 2 6 1 Selection if and case Statements The i statement is easy to use if A 4 begin B 2 end else begin B 4 end Unlike the case statement in C the first lt value gt that matches the value of the lt expression gt is selected and the associated statement is executed then control is transferred to after the endcase i e no break statements are needed as in C case expression valuel statement value2 statement default statement endcase The following example checks a 1 bit signal for its value case sig l bz display Signal is floating l bx display Signal is unknown default display Signal is b sig endcase B 1 2 6 2 Repetition for while and repeat Statements The for statement is very close to C s or statement except that the and operators do not exist in Verilog Therefore we need to use i i 1 for i 0 i lt 10 i i 1 begin display i 0d i
377. ominator 3rd order coefficient 0 s B2 Denominator 2nd order coefficient 0 B1 Denominator 1st order coefficient 0 BO Denominator constant 1 L 4 Voltage Gain Block A1 1vi OV OV sine wave and the gain factor K is set at 5 The output then is K times the input 707 5 3 535v RMS or 10 v peak to peak This component multiplies the input voltage by the gain and delivers it to the output This represents a voltage amplifier function with the gain factor K selectable with the Value tab of Circuit Component Properties The voltage gain block is used in control systems and analog computing applications In the example shown below the input is a 0 707v RMS 2v peak to peak CAUTION Using the default model as in this example sine wave inputs may be any value Multisim User Guide S O04 UO Controls Controls Components Suitable settings of model parameters will allow for virtually unlimited flexibility for practi cal applications 0 707 V 1 kHz 0 Deg s Oscilloscope 0 50msi div M Xposition o co Channela Y position 0 00 welo oc FE L 4 1 Characteristic Equation Vs K Vin Vor Voor L 4 2 Voltage Gain Block Parameters and Defaults Symbol Parameter Name Default Unit K Gain 1 VN Vloff Input offset voltage 0 V VOoff Output offset voltage 0 V L 8 Electronics Workbench Voltage Differentiator L 5 Voltage Diff
378. ommonly used coding styles for synthesizable circuits and test benches These examples and more can be found in the EXAMPLES folder of your VHDL installation You are encouraged to copy these examples and modify them for your own use Using Type Version Functions This example an 8 bit counter demonstrates one possible approach to type conversion Type conversions are often required in VHDL due to the languages strict type checking features In this example a type conversion is required to convert the array data types used in the design s interface to integer data types used internally for arithmetic operations For demon stration purposes we are using a custom type conversion function that is defined in the design description In most cases you will want to use a standard type conversion function from the IEEE library or use a type conversion function provided by your synthesis vendor Multisim User Guide A 23 Jeuiug TAHA VDHL Prrimer VHDL Primer Note Another option when numeric values are required is to make use of the IEEE 1076 3 numeric std package This package is provided in the library IEEE supplied with the Multisim VHDL simulator A 4 1 1 Design Description library ieee use ieee std logic 1164 all package conversions is function to unsigned a std ulogic vector returninteger function to vector size integer num integer return std ulogic vector end conversions package body conversions is Con
379. on or scope is not valid then the waveform will be blank The OK button closes the screen and displays the specified expression in the Data Analyzer The Cancel button closes the screen and does not display the expression Add Blank Line Inserts a blank line in the Data Analyzer just above the signal name that is highlighted Clear Signal List Deletes all of the signal names in the Name list box Reload Groups Causes the Data Analyzer to clear the list box and reload the group information from the project file This is useful when a user written program is used to modify the groups while the SSE is running B 3 12 4Source Window Pop up Menus B 3 12 4 1Undo Undoes your last editing or formatting action including cut and paste actions If an action cannot be undone Undo appears dimmed on the pop up menu To invoke the pop up menu right click on any part of the source window B 3 12 4 2Cut Deletes text from a document and places it onto the Clipboard replacing the previous Clip board contents To invoke the pop up menu right click on any part of the source window B 3 12 4 3Copy Copies text from a document onto the Clipboard leaving the original intact and replacing the previous Clipboard contents To invoke the pop up menu right click on any part of the source window Multisim User Guide B 3 43 snus 111 SOS Silos Ill Menus Silos III Menus B 3 12 4 4Paste Pastes a copy of the Clipboard contents a
380. onostable at Q A complementary output is produced at W To operate the monostable the following connections may be used e Connect a series resistor R and capacitor C to the CT input Connect the junction of the R and C to the RT CT e Connect Vec to a voltage source The output Q will give a pulse of duration 0 0693 R C when either a positive clock edge is given to Al or a negative edge is given to A2 The threshold voltage at which triggering starts can be changed by modifying the model Phase Locked Loop This component models the behavior of a phase locked loop circuit Fin Phase In which is a circuit that contains an oscillator whose output phase and fre ia quency are steered to keep it synchronized with an input reference signal F Out v Out A phase locked loop circuit is composed of three functional blocks a oviza Overy Phase detector a low pass filter and a voltage controlled oscillator VCO The phase detector behaves as an analog multiplier It outputs a DC voltage which is a function of the phase difference between the input reference signal and the VCO output signal The output of the phase detector is input to the low pass filter which removes the high frequency noise and outputs a DC voltage The VCO converts the DC volt age into its corresponding frequency signal Electronics Workbench Phase Locked Loop 1 5 1 Characteristic Equation The phase detector is modeled by V K sin 9 9 2
381. operate in either direction to monitor under voltage dips and over voltage spikes of the AC input It protects the power supply from surges by shorting out any voltages greater than the V Zener voltage ratings of the diodes The voltage suppressor diode must also have extremely high power dissipation ratings because most AC power line surges contain a relatively high amount of power in the hun dreds of watts or higher It must also be able to turn on rapidly to prevent damage to the power supply In DC applications a single unidirectional voltage suppressor can be used instead of a bi directional voltage suppressor It is connected in shunt with the DC input and reverse biased cathode to positive DC Boost Converter M This component is an averaging circuit model that models the averag ing behavior of a step up DC to DC switching converter It is based on prc a unified behavioral model topology The topology models both small 500H 100hm 50Hz siena and large signal characteristics of this converter power stage The model can be used to simulate DC AC and large signal transient Electronics Workbench Boost Converter responses of switched mode power supplies operating in both the continuous and discontinu ous inductor current conduction modes CCM and DCM respectively K 8 1 Characteristic Equations The averaging DC and large signal characteristics of a Boost converter are given by the fol lowing sets of equations I I
382. or from the Unknown level back to a High or Low level A H reported to the left of the node name means the node never had a definite transi tion and the node was High at the time specified as the minimum time for the time range for the report The default minimum time is time 0 A L reported to the left of the node name means the node never had a definite transition and the node was Low at the time specified as the minimum time for the time range for the report For the Summary for the Activity report the percentages are based on the nodes listed that are within the range specified for the Activity report The default range is zero transitions for the maximum and minimum number of transitions The default is zero because the purpose of the Activity report is to report nodes that did not toggle for fault simulation If you want to set the maximum number of transitions to greater than zero so you can see how many times the nodes are toggling see the Activity Report For Nodes B 3 6 2 Reports Errors Reports the errors that occurred during read in preprocessing or simulation An error level of 1 indicates a warning Error levels 2 through 5 will prevent simulation until the error has been corrected Multisim User Guide B 3 15 snus 111 SOS Silos II Menus Silos III Menus B 3 6 3 Reports Fault Reports the fault simulation results B 3 6 4 Reports Iteration Useful for finding order of evaluation problems and r
383. or from the command line if you are running a batch simulation define s You can enter define statements that are project specific These define compiler directives will be used in addition to any define compiler directives in the design When entering the define use just the text macro name MACRO TEXT part of the define syntax For example for the Verilog compiler directive define wordsize 8 you would enter in the Project Settings screen wordsize 8 Delay Selection You can select the min typ max delay setting for all delays in the project Disable floating node warnings This feature disables the warning message that informs you that a wire is not driven by anything i e a floating node Enable Silos extensions This feature enables extensions to the Verilog HDL language such as assigning to wires in procedural code and global variables see Verilog HDL Extensions Enable log file This feature causes standard output to be written to a log file when the SSE program is exited The default log file name is the project name with the log file extension When this option is selected the SSE will write to both standard output and the log file Functional simulation This feature reduces the memory used and increases simulation speed by eliminating the specify blocks from logic simulation To prevent nonconver gence problems the unit delay mode is used for all modules Max Sim File Size You can select
384. ors multiplexors with full decoding on one monolithic chip Dual data selector multiplexor truth table INPUTS OUTPUTS ENABLE SELECT 3 c B A 1Y 2Y 1 X X X Z Z 0 0 0 0 1Do 2DO 0 0 0 1 IDI 2D1 0 0 1 O 1D2 2D2 0 0 1 1 1D3 2D3 0 X 0 o D4 Da 0 X 0 1 D5 D5 0 X 1 0 D6 D6 0 X 1 1 D7 D7 P 5 10174xx352 Dual 4 to 1 Data Sel MUX This device contains inverters and drivers to supply fully complementary on chip binary decoding data selection to the AND OR invert gates Data selector multiplexer truth table SELECT DATA INPUTS B A co a C2 c3 G x X X X X X X 1 1 0 0 0 x x x 0 1 0 0 x x x 0 0 0 1 x 0 x x 0 1 0 j x 1 x x 0 0 1 0 x x 0 x 0 1 d 0 X X L X 0 0 1 1 x X x 0 0 1 1 1 X X X 1 0 0 P 54 Electronics Workbench 74XX P 5 10274xx353 Dual 4 to 1 Data Sel MUX w 3 state Out This device contains inverters and drivers to supply fully complementary on chip binary decoding data selection to the AND OR invert gates Data selector multiplexer truth table SELECT DATA INPUTS B A co C1 C2 X X X X X 0 0 0 X X 0 0 1 X X 0 d X 0 X 0 d X 1 X 3 0 X X 0 I 0 X X 1 I de X X X I 1 X X X c3 E O P4 P4 b P MM ox CP OOOO OO oO HF Ql OorFOrFOF OF PK P 5 10374xx365 Hex Buffer Driver w 3 state This device features high fan out improved fan in and can be used to drive terminated lines down to 133 ohms Hex buffer driver truth table INPUTS OUTPUTS OE OF I YQ Ya
385. os gate source voltage Vas drain source voltage Vio threshold voltage equivalent to the gate source cutoff voltage a saturation voltage b transconductance I channel length modulation Id drain to source current F 20 Electronics Workbench IGBT F8 2 GaAsFET Parameters and Defaults F 9 Symbol Parameter name Default Unit VTO Pinch off voltage 2 V BETA Transconductance 0 0001 ANN B Doping tail extending parameter 0 3 1N ALPHA Saturation voltage 2 1N LAMBDA Channel length modulation 0 1N RD Drain ohmic resistance 0 Ww RS Source ohmic resistance 0 WwW CGS Zero bias G S junction capacitance 0 F CGD Zero bias G D junction capacitance 0 F PB Gate junction potential 1 V KF Flicker noise coefficient 0 AF Flicker noise exponent 1 FC Coefficient for forward bias depletion 0 5 capacitance formula IGBT 01 2N6375 The IGBT is an MOS gate controlled power switch with a very low on resistance It is similar in structure to the MOS gated thyristor but main tains gate control of the anode current over a wide range of operating condi tions The low on resistance feature of the IGBT is due to conductivity modulation of the n epitaxial layer grown on a p substrate The on resistance values have been reduced by a factor of about 10 compared with those of conventional n channel power MOSFETs of similar size and voltage capability Changes to the epitaxial structu
386. ow noise and stable operation over time and temperature The low operating current make these devices suitable for micropower circuitry such as portable instrumentation regulators and other ana log circuitry that requires extended battery life Note Many types of two terminal 1 2 V voltage reference diodes offer the same performance but are not all directly interchangeable Minor differences in regulation voltage and in allow able or required capacitive loading may affect a circuit Electronics Workbench Voltage Regulator K 6 Voltage Regulator d The linear IC voltage regulator is a device used to hold the output volt Pr age from a dc power supply relatively constant over a wide range of UT I DN line and load variations Most commonly used IC voltage regulators are LMmM109H E three terminal devices There are four types of IC voltage regulators fixed positive fixed neg ative adjustable and dual tracking The fixed positive and fixed negative IC voltage regula tors are designed to provide specific output voltages The adjustable regulator can be adjusted to provide any dc output voltage within two specified limits The dual tracking regulator pro vides equal positive and negative output voltages The regulator input voltage polarity must match the device s rated output polarity regardless of the type of regulator used IC voltage regulators are series regulators that is they contain internal pass transistors an
387. parity generator checker P 50 A AC current source C 4 AC frequency model capacitors D 7 inductors D 10 AC model F 9 AC small signal model bipolar junction transistors F 5 diac E 15 diodes E 4 MOSFET F 13 SCR E 14 AC voltage source C 3 ADC DAC 1 1 Alu Function Generator P 31 AM source See amplitude modulation source ammeter about J 2 connecting J 2 mode J 2 resistance J 2 amplifiers wide bandwidth G 11 amplitude modulation source C 4 analog components bipolar junction transistors see also bipolar junction transistors F 1 BJT arrays see also BJT arrays F 9 comparator G 9 Darlington connection see also Darlington connection F 8 diac see also diac E 14 diodes see also diodes E 1 DMOS transistor F 19 full wave bridge rectifier see alsofull wave bridge rectifier E 10 GaAsFET see also GaAsFET F 19 IGBT IGBT F 21 LED Light Emitting Diode see a so LED E 8 MOSFET see also MOSFET F 10 Norton opamps G 8 opamps see also opamps G 1 optocoupler K 4 PIN diode E 6 Schottky diode E 12 SCR Silicon Controlled Rectifier see also SCR E 12 triac E 16 triode vacuum tube see alsotriode vacuum tube K 4 varactor diode E 18 voltage reference K 6 voltage regulator K 7 voltage suppressor K 8 voltage controlled analog l 2 wide bandwith amplifiers G 11 zener diode see also zener diode E 6 analog switch 1 2 AND gated JK MS SLV FF pre clr P 75 AND OR INVERTER P 74 arrays BJT F 9 B bargraph about J 6
388. per voltage limit is set by adjusting the potentiometer sup plying the Upper terminal on the VCL The lower voltage limit is set by adjusting the potenti ometer supplying the Lower terminal on the VCL The potentiometers are adjusted by pressing U or SHIFT U for the upper limit and L or SHIFT L for the lower limit These settings may be adjusted to provide symmetrical or unsymmetrical clipping on the pos itive and negative peak excursions of the input waveform when these peaks exceed the set limit clipping values N Input L 1 kcy 50 Lower Lim Upper Lim R2 UJ 1 Ka 50 6 Output 4 so vyjoo Hao dey are M2 S00 V wi ov v4 7 Oscilloscope Ground Time base Trigger Edge me 6 X position 0 00 E Level Aver aa ve Auto a B Est Channel A Channel B Y position 0 00 Y position o oo Bel el oc FE gelol oc FE Multisim User Guide L 19 04 U0D Controls Controls Components L 10 1 Voltage Controlled Limiter Parameters and L 11 L 20 Defaults Symbol Parameter Name Default Unit ViOff Input offset 0 V k Gain 1 VN VoUD Output upper delta 0 V VoLD Output lower delta 0 V ULSR Upper and lower smoothing range 1 uv Voltage Slew Rate Block A This component limits the absolute slope of the output with respect to iA time to some maximum or value You can accurately model actual slew dE rate effects of ove
389. ple an HDL might describe the layout of the wires resistors and transistors on an Integrated Circuit IC chip i e the switch level Or it might describe the logical gates and flip flops in a digital sys tem i e the gate level An even higher level describes the registers and the transfers of vec tors of information between registers This is called the Register Transfer Level RTL Verilog supports all of these levels However this primer focuses on only the portions of Ver ilog which support the RTL level B 1 1 1 What is Verilog Verilog is one of the two major Hardware Description Languages HDL used by hardware designers in industry and academia VHDL is the other one The industry is currently split on which is better Many feel that Verilog is easier to learn and use than VHDL VHDL was made an IEEE Standard in 1987 and Verilog in 1995 Verilog is very C like and liked by elec trical and computer engineers as most learn the C language in college VHDL is very Ada like and most engineers have no experience with Ada Verilog was introduced in 1985 by Gateway Design System Corporation now a part of Cadence Design Systems Inc s Systems Division Until May 1990 with the formation of Multisim User Guide B 1 1 JEW Boje Verilog Primer Verilog HDL Primer Open Verilog International OVI Verilog HDL was a proprietary language of Cadence Cadence was motivated to open the language to the Public Domain with the expect
390. point Examples RES ERR res savfile Multisim User Guide B 2 47 suoisuejx3 JAH Bojan Verilog HDL Extensions Extensions B 2 2 21Scope For Printing Module Variables The SCOPE command declares the module instance used when the PRINT or probe com mands reports the values for variables and expressions in a module The format for the SCOPE command is SCOPE instance_name SCOPE Declares the module instance used by the PRINT or probe command instance name Represents the instance name for the module whose vari ables will be reported by the PRINT or probe commands Example SCOPE main cpu cache B 2 2 22Logic Simulation Specification Logic simulation can be performed by entering the SIMULATE command To initiate the logic simulation enter SIMULATE t1 TO t2 SIMULATE Performs time response logic simulation that can use both finite and zero delay specifications Preprocessing PREPROC and logic initialization will be automatically performed if they have not been previously t1 TO t2 Represent the values of the first and last simulation time points see note 1 below The keyword TO is optional Application Notes 1 When specifying the simulation time point range the following items apply B 2 48 Electronics Workbench Silos III Command Line Usage e Specifying neither tl nor t2 or setting t2 to an arbitrary large number will cause SILOS III to simulate until stop or finish is encoun
391. points at which the slope of the hysteresis function would normally change abruptly as the input transitions from low to high values The slope of the hysteresis function is smoothly varied whenever ISD is set greater than zero This component can be used to simulate a non inverting comparator in which the comparison threshold is changed each time the input crosses the threshold in effect at that instant As the output changes state high to low or low to high the threshold voltage is changed internally in such a manner that the input must continue to change until it reaches the new threshold In the example circuit shown below the hysteresis value is set to 5V This means that the two comparison thresholds at which the output changes are 5V and 5V As shown the input triangle waveform rises from OV and the output is at its lowest value OV in this case as the input crosses 5V the upper threshold in comparator terms the output changes to its highest value 2V in this case Internally in the hysteresis block the threshold is now changed to 5V the lower threshold The output continues to rise to a peak and then starts to decrease Multisim User Guide L 13 O1U0D Controls Controls Components Note The output changes only when the input crosses 5V Internally the threshold is changed again to the upper threshold and the process repeats Function Generator L 7 1 Oscilloscope Ground Time ba
392. pplied to govern the output voltage output current relationship The chosen resistance will continue to control the output current until it reaches a maximum value speci fied by either ISrcL or ISnkL The latter mimics the current limiting behavior of many opera tional amplifier output stages Electronics Workbench Current Limiter Block During operation the output current is reflected either in the positive or the negative power supply inputs depending on the polarity of the output current Thus realistic power consump tion as seen in the supply rails is modeled ULSR controls the voltage below positive input power and above negative input power beyond which Veq k input voltage Off is smoothed ISrcSR specifies the current below ISrcL at which smoothing begins and specifies the current increment above zero input current at which positive power begins to transition to zero ISnkSR serves the same purpose with respect to ISnkL and negative power VDSR specifies the incremental value above and below Veq output voltage 0 at which output resistance will be set to Rsrc and Rsnk respectively For values of Veg output voltage less than VDSR and greater than VDSR output resis tance is interpolated smoothly between Rsrc and Rsnk The current limiter block is also a representation of an operational amplifier with respect to the sourcing and sinking of current at the output and supply terminals If the current being sinked sour
393. processes and it will use a series of signal assignments and wait statements to describe the actual stimulus You will probably use VHDU s looping features to simplify the description of repetitive stimulus such as the system clock and you may also use VHDL s file and record features to apply stimulus in the form of test vectors To check the results of simulation you will probably make use of VHDL s assert feature and you may also use the file features to write the simulation results to a disk file for later analy sis For complex design descriptions developing a comprehensive test bench can be a large scale project in itself In fact it is not unusual for the test bench to be larger and more complex than the design description For this reason you should plan your project so that you have the time required to develop the function test in addition to developing the circuit being tested You should also plan to create test benches that are re usable perhaps by developing a master test bench that reads test data from a file When you create a test bench for your design you use the structural level of abstraction to connect your lower level previously top level design description to the other parts of the test bench A 2 6 9 Sample Test Bench The following VHDL source statements describe a simple test bench for the shift and com pare circuit This test bench uses two processes that operate concurrently One process clock Multi
394. r The value of Cris inversely proportional to the width of the depletion layer The depletion layer acts as an insulator called the dielectric between the p type and n type materials Varactor diodes are used in place of variable capacitors in many applications E 18 Electronics Workbench Appendix F Transistors Components F 1 F 2 F 3 F 4 F 5 F 6 F 7 F 8 BJ NBN SBNP eo rob o ae ar a edo F 1 F 1 1 Characteristic Equations 22 22m sense nennen eh F 2 F 1 2 Time Domain Models crenis reipi at trde nai eene F 4 F 1 3 AC Small Signal Model aaaea F 5 F 1 4 BJT Model Parameters and Defaults llle F 6 Resistor Biased BJT NPN amp PNP ooococcccccccc eren F 8 Darlington Transistor NPN amp PNP 0 0000 eee eee RII F 8 F 3 1 DC Bias Modeli meda aiu ea a a A a tees F 8 F 3 2vAC Model 2 2 02 3 2 tr edu a de A a e nee F 9 F 3 2 1 AC Input Impedance nunana naaa F 9 F 3 2 2AC Current Gain llis ee F 9 BJT Atray nda Die ni ate Seem Eh ad Sec F 9 F 4 1 General purpose PNP Transistor Array llli elles F 10 F 4 2 NPN PNP Transistor ArTay ooocooccoccooc e F 10 F 4 3 General purpose High current NPN Transistor Array 2 2 2202 F 10 MOSFET 228 xr UST oder Ed pps tp EE Wt E e F 10 F 5 1 Depletion MOSFETS sssssseeee nennen nennen F 11 F 5 2 Enhancement MOSFETS 00 0 cece rns F 11 F 5 3 DG MOGel ex esseri eme Muse ha ead ae Ue ERIS
395. r library statements once at the beginning of the source file before any use clauses or other VHDL statements ause clause specifying which items from the IEEE library are to be made visible for the subsequent design unit the entity and its corresponding architecture The general form of a use statement includes three fields delimited by a period the library name in this case ieee a design unit within the library normally a package in this case named std logic 1164 and the specific item within that design unit or as in this case the special keyword all which means everything to be made visible e an entity declaration describing the interface to the comparator Note that std ulogic and std ulogic vector which are standard data types provided in the IEEE 1164 standard and in the associated IEEE library were specified e an architecture declaration describing the actual function of the comparator circuit Conditional Signal Assignment The function of the comparator is defined using a simple concurrent assignment to port EQ The type of statement used in the assignment to EQ is called a conditional signal assign ment Conditional signal assignments make use of the when else language feature and allow complex conditional logic to be described The following description of a multiplexer circuit makes the use of the conditional signal assignment more clear architecture mux1 of mux is begin Y lt A whe
396. r over the button for a few seconds and an explanatory text message will appear The location of the Main toolbar can be changed by using the mouse to grab an edge of either toolbar and dragging the toolbar to the desired location B 3 4 3 View Analyzer Toolbar A check mark appears next to the Analyzer toolbar when it is displayed Many of the selections for pull down menus and can also be accessed by clicking on buttons on the Analyzer toolbar To obtain a text message of each button s function place the mouse cursor over the button for a few seconds and an explanatory text message will appear The location of the Analyzer toolbar can be changed by using the mouse to grab an edge of either toolbar and dragging the toolbar to the desired location B 3 4 4 View Status Bar Displays or hides the Status Bar at the bottom of the SSE The left area of the Status Bar describes actions of menu items as you use the arrow keys to navigate through menus This area similarly shows messages that describe the actions of tool bar buttons as you depress them before releasing them If you wish not to execute the toolbar button after viewing the description of the toolbar button then release the mouse button while the pointer is off the toolbar button The right area of the Status Bar displays the time values for the T1 T2 the delta time and the current time The farthest right area of the status bar displays which of the following keys are latched down
397. r relationship described in the H B array of coordinate pairs This H B array can be taken from the averaging H B curve which may be obtained from a technical manual that specifies the magnetic characteristics of different cores The slope of the B H function is never allowed to change abruptly but is smoothly varied whenever the Input Smoothing domain parameter is set to a number greater than zero The Flux Density B is multiplied by the cross sectional area to obtain a Flux Value The Flux Value is used by the coreless coil to obtain a value for the voltage reflected back across the terminals The core is modeled to be lossless No core losses are considered In the transformer model the only losses taken into account are the ones modeled by the winding resistances To obtain the H B points of the curve e Contact a manufacturing company They many be able to provide the technical data required to model a core Obtain experimental data D 12 Electronics Workbench Relay D 7 2 Nonlinear Transformer Parameters and Defaults Symbol Parameter Name Default Unit N1 Primary turns 1 R1 Primary resistance 1e 06 Ww L1 Primary leakage inductance 0 0 H N2 Secondary turns 1 R2 Secondary resistance 1e 06 Ww L2 Secondary leakage inductance 0 0 H A Cross sectional area 1 0 m L Core length 1 0 m ISD Input smoothing domain 1 0 N Number of co ordinates 2 H1 Magnetic field co
398. r combinations 0 1 High level 0 Low level X Don t care P 32 Electronics Workbench 74XX P 5 60 74xx190 Sync BCD up down Counter This device is a synchronous BCD reversible up down counter Counter TC and RC truth table TERMINAL COUNT OUTPUTS INPUTS STATE U D CE CP Q0 Q1 Q2 Qs 1 1 X 1 X X 1 0 1 X ak X X 1 0 0 1 X X d 0 1 X 0 0 0 0 1 1 X 0 0 0 0 1 0 0 0 0 0 1 High voltage level 0 Low voltage level X Don t care P 5 61 74xx191 Sync 4 bit up down Counter This device is a synchronous 4 bit binary reversible up down counter Low pulse Counter TC and RC truth table TERMINAL COUNT Hrorro INPUTS OUTPUTS STATE U D CE CP QO0 Q1 Q2 93 TC 1 A X 1 al 1 al 0 0 1 X 1 T 1 1 1 0 0 1 al 1 yl RE 0 J X 0 0 0 0 0 1 T X 0 0 0 0 L J 0 0 0 0 0 1 1 High voltage level 0 Low voltage level X Don t care Multisim User Guide Low pulse P 33 sanas Xxv4 suonounJj Functions 74XX series Functions 74XX Series P 5 62 74xx192 Sync BCD Up down Counter This device is a synchronous BCD reversible up down counter Up down counter truth table INPUTS OUTPUTS OPERATING MR PL CPU CPD DO D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD MODE 1 X X 0 X X X X 0 0 0 0 1 0 Reset 1 X X 1 X X X X 0 0 0 0 i 1 0 0 X 0 0 0 0 0 0 0 0 0 1 0 Parallel 0 0 X 1 0 0 0 0 0 0 0 0 1 1 load 0 0 0 X 1 X X 1 On Dn 0 1 0 0 1 X d X X 1 On Dn 1 1 0 1 1 X X X X Count
399. r driving an amplifier circuit by cascading the amplifier with this component Maximum rising and falling slope values are expressed in volts per second 1G6GV sec 1GV The slew rate block will continue to raise or lower its output until the difference between input and output values is zero After it will resume following the input signal unless the slope again exceeds its rise or fall slope limits This component provides for introduction of selectable rising and falling slew rates rise and fall times on a pulse waveform for analysis of pulse and analog circuits With an ideal pulse or analog input to block the effect of slew rate on a logic circuit or analog amplifier discrete component or op amp output may be investigated In the example shown below the function generator may be set for either square wave or sine wave output A slew rate of 8000V sec for rising slope and 6000V sec for falling slope shows as rise and fall time on an ideal 80Hz square wave input Signal degradation as a result of slew rate occurs when frequency is increased Switching the function generator to sine wave output 60 Hz does not result in distortion However as frequency is increased slew rate distortion on a sine wave will become evident at 200 Hz and above As frequency is increased the sine wave deteriorates to a triangle shape Electronics Workbench Three Way Voltage Summer A more serious degradation of output as a result of slew rate occ
400. r outputs a square wave at that frequency When two co ordinate pairs are used the oscillator outputs a linear variation of the frequency with respect to the control input When the number of co ordinate pairs is greater than two the output is piecewise linear You can change duty cycle rise and fall times and the peak and valley values of the output square wave by resetting the Output peak high value and Output peak low value on the model parameter dialog box C 17 2 Example The example shows a square wave generator with output frequency determined by a control voltage Control voltage may be DC controlled by a potentiometer as is the case for many signal gen erators and function generators Control voltage may be a continuous variable of any desired shape as required in sweep gen erators and spectrum analysers In the example shown below the VCO parameters are set so that control voltage of OV pro duces an output frequency of 100Hz and control voltage of 12V produces an output frequency of 20KHz Multisim User Guide C 11 seoinos Sources Sources Components A square wave control voltage produces a form of FSK frequency shift keying a sine wave control voltage produces a form of FM frequency modulation 81 El cowtroLv SWEEP Y OUTPUT Frequency Adj JR1 FJT kQ160 M1 Function Generator rr Frequency 500 HE Dutyoyele to El Amplitude 55 El Offset Common s Osci
401. r pin The VCC Voltage Source must be placed on the schematic and can be used as a DC voltage source The value of VCC can be set by using the Digital Power dialog box which appears when you right click on the VCC symbol Multiple VCC symbols may be placed on a schematic but there is only one VCC net in the schematic Only one value of VCC voltage is possible in the design with both positive and negative values being supported DC Current Source i The current generated by this source can be adjusted from uA to kA 1a DC current source tolerance is by default set to the global tolerance defined in the Analysis Monte Carlo dialog box To set the tolerance explicitly de select Use global tolerance and enter a value in the current tolerance field AC Voltage Source v2 The root mean square RMS voltage of this source can be adjusted from c soHz WV to kV You can also control its frequency and phase angle V peak 42 AC voltage source tolerance is by default set to the global tolerance defined in the Monte Carlo Analysis screen To set the tolerance explicitly de select Use global tolerance and enter a value in the voltage tolerance field VRMS Multisim User Guide C 3 seounos Sources Sources Components C 7 AC Current Source The RMS current of this source can be adjusted from u A to kA You can also dy E control its frequency and phase angle peak IRMS 72 AC current source tolera
402. r the time and the timescale resolution of the center of the Waveform Display window When debugging your design the bookmakers you set enable you to jump back and forth between waveform views with the same or different timescale Electronics Workbench Pop up Menus After opening the Add Bookmark screen you will see the default bookmarks i e Bookmark1 Bookmark2 etc You can specify any string of characters for the bookmark name and then click on OK to set the bookmark The bookmarks you have set are listed at the bottom of the pop up menu To go to a bookmarker select it with the left mouse button To invoke the pop up menu right click on any part of the time point display area the gray area just above the Waveform Display window Delete Bookmark Enables you to delete a bookmarker After opening the Delete Bookmark screen you will see the bookmarkers i e Bookmark1 Bookmark2 listed in the Bookmarks list box You can delete a bookmark by selecting it with the mouse and clicking Delete Click OK to close the screen To invoke the pop up menu right click on any part of the time point display area the gray area just above the Waveform Display window B 3 12 3 2Data Analyzer Signal List Box Trace Signal Inputs Menu Selection Opens a Trace Signal Inputs window The Trace Signal Inputs window allows you to interac tively trace an incorrect value at a net to its cause by displaying the waveforms of all
403. racter that precedes the t This matches one or more occurrences of the character that precedes the This matches zero or one occurrence of the character that precedes the e Ordinary characters These are all the other available characters These characters match themselves such as a would match the letter a The character class has special rules Inside a character class all characters have their lit eral meaning except for the quoting character V at the beginning and between two char acters Each of the characters in a character class are treated as an or search For example ab will find any single character name a or b The character class a z will match any single character lower case name The character class a zA Z will match any single charac ter name that is not an alpha Some examples of using regular expressions are listed below a matches only the name lowercase a a matches any name that begins with a a matches any name that ends with a and the name a ar matches any name that has an a anywhere in the name abc matches only the names a or b or o Electronics Workbench Pop up Menus a z matches any name that is a single lower case character such as b a z matches any name that is only lower case characters for example data a zA Z matches any name that is upper and or lower case characters for example
404. re silicon The p and n type mate eom rials are heavily doped and as a result have very low resistances When reverse biased the PIN diode acts as a capacitor The intrinsic material can be seen as the dielectric of a capacitor The heavily doped p and n type materials can be viewed as the two conductors Photo Diode Application The intrinsic layer which is a pure semiconductor with no impurities makes the PIN diode respond better to infrared photons that penetrate deeper into the diode s regions The intrinsic layer creates a larger depletion region which causes the diode to produce a more linear change in current in response to changes in light intensity Zener Diode A zener diode is designed to operate in the reverse breakdown or Zener x Ds region beyond the peak inverse voltage rating of normal diodes This reverse U breakdown voltage is called the Zener test voltage Vzt which can range between 2 4 V and 200 V In the forward region it starts conducting around 0 7 V just like an ordinary silicon diode In the leakage region between zero and breakdown it has only a small reverse current The breakdown has a sharp knee followed by an almost vertical increase in current Zener diodes are used primarily for voltage regulation because they maintain constant output voltage despite changes in current Electronics Workbench Zener Diode E 3 1 DC Model The DC characteristic of a real diode in Multisim is
405. re and the addition of recombination centers are responsible for the reduction in the fall time and an increase in the latching current level of the IGBT Fall Multisim User Guide F 21 SJO SISUBJ Transistors Transistors Components times as low as 0 1 ts and latching currents as high as 50A can be achieved while retaining on resistance values 0 2Q for a 0 09cm chip area F 22 Electronics Workbench Appendix G Analog Components G 1 G 2 G 3 G 4 G 5 ODamp iiris grane LO tbe a pated Per P Pea aceti road G 1 G 1 1 Opamp Model Parameters 0 000 cee een G 1 G 1 2 Ideal Opamp Model oococcccccco rn G 1 G 1 3 Opamp Background Information 0 0000 eee ees G 2 G 1 4 Opamp Simulation Models 2 222 sans rennen nenn nn G 3 G 1 4 1L1 Simulation Model 2 22 22nssen nennen eee G 3 G 1 4 2L2 Simulation Model 2 22 22 c nennen eese G 5 G 1 4 3L3 Simulation Model isses nennen een nn G 8 G 1 4 4L4 Simulation Model oooooccccccccoc G 8 Norton Opamp Ar eR eee A G 8 Gi2 1 The Component seie e ara E EX eek a a x G 8 G 2 2 Norton Opamp Simulation models 0000 00 eee eee eee G 8 Comparator sess eR ROREM RAV ab ERR a ee Dates G 9 G 3 1 The Component occcccccc hs G 9 G 3 2 Comparator Simulation MOAeIS ooococccccoco eee G 10 G 3 3 Comparator Parameters and Defaults 0000 e eee eee G 10 Wide Band Amplif
406. real variables and T for integer variables Input ports have the pad symbol pointing to the right output ports have the pad symbol pointing to the left and inout ports have the pad symbol pointing in both directions When you open the Explorer window the first hierarchical name listed is the global mod ule The global module contains the names of any global variables Verilog HDL Extensions SILOS III also has global variables called ExpectedValueError for checking the results of expected values for more information see Expected Values and Stimulustable B 3 7 2 Explorer Go to Module Source B 3 8 B 3 20 Opens a source window that displays the source code for the hierarchical instance you selected in the left hand Tree side of the Explorer window This enables you to quickly find the source code for a module instance when you have a large design that spans many files scattered across many directories Debug Menu The Debug menu provides the following commands e Debug Go e Debug Break Simulation Debug Finish Current Timepoint Debug Restart Simulation e Debug Step e Debug Breakpoints Electronics Workbench Debug Menu B 3 8 1 Debug Go Performs logic simulation The Go button is also available on the toolbar When Go is selected the files specified for the project are automatically input into SILOS III unless they have already been input Logic simulation is then run until a stop or
407. redefined by the CONTROL MXITR command Arbitrarily increasing these parameters is not recommended as it may dramatically increase the execution time neces sary to identify oscillating nodes 6 The maximum number of passes for logic initialization is defined by the CONTROL MXPAS command When this limit is exceeded the error message specifies the required number of passes to complete logic initialization To reduce the number of passes and exe cution time use INIT to preset the state for critical nodes Although arbitrarily setting CONTROL MXPAS to a large value will very likely converge a circuit that is theoreti cally solvable this is not recommended as the problem is usually due to incorrect circuit design Examples ty noc nocon iter 43 B 2 2 16Narrow Storing Outputs When a command that generates a report is preceded by the NSTORE command the report output will be directed to a disk file To specify the NSTORE command enter NSTOREcommand NSTORE directs the output to a 79 column disk file As a default this file is named store out Multisim User Guide B 2 43 Suoisueix3 JAH Bojan Verilog HDL Extensions Extensions command represents a command structure which defines the type of data to be output These commands are described within this section of the manual Application Notes 1 If a command that generates a report is not preceded by the NSTORE command then the default output device is spe
408. released in 1994 and VHDL tool vendors have been responding by adding these new language features to their products IEEE Standard 1164 Although IEEE Standard 1076 defines the complete VHDL language there are aspects of the language that make it difficult to write completely portable design descriptions descriptions that can be simulated identically using different vendors tools The problem stems from the Multisim User Guide A 1 Jeuiug TAHA VDHL Prrimer VHDL Primer A 2 fact that VHDL supports many abstract data types but it does not address the simple problem of characterizing different signal strengths or commonly used simulation conditions such as unknowns and high impedance Soon after IEEE 1076 1987 was adopted simulator companies began enhancing VHDL with new signal types typically through the use of syntactically legal but nonstandard enumer ated types to allow their customers to accurately simulate complex electronic circuits This caused problems because design descriptions entered using one simulator were often incom patible with other simulation environments VHDL was quickly becoming nonstandard To get around the problem of nonstandard data types another standard numbered 1164 was created by an IEEE committee It defines a standard package a VHDL feature that allows commonly used declarations to be collected into an external library containing definitions for a standard nine valued data type This
409. rmally the default delays are d1 d2 0 di Represents the nominal rise delay time where d1 must be an integer between O and 10000 Electronics Workbench Silos III Command Line Usage d2 represents the nominal fall delay where d2 must be an integer between 0 and 10000 Examples IDEL DEF 16 5 del default 0 0 DISK B 2 2 7 Disk File Name Reassignment The DISK command enables you to change the default file name for the STORE NSTORE commands To change the STORE NSTORE disk file name enter DISK filename DISK Changes the STORE NSTORE disk file name If no file name is specified the program will tell you the name of the present default disk file name filename Represents the name of the disk file to which STOREd output will be written filename store out Application Notes 1 Whenever a DISK command is specified any STOREd data will be written to that disk file until another file name is specified 2 Each time a STORE or NSTORE command is specified any existing data on the DISK file in effect may be overwritten default appended or a new cycle will be created 3 The file name can be unlimited in length but must conform to the file name syntax of your operating system For the UNIX operating system the file name is case sensitive 4 The FILE STO command can also be used to change the default file name Examples DISK sim results DI PATTERN INP ERRORS Multisim User Gui
410. rogram execution enter QUIT Application Notes 1 The QUIT command aborts execution of the program and all program results since the last SAVE command are lost Electronics Workbench Silos III Command Line Usage B 2 2 20Resetting Selected Data The RESET command can be used to reset i e delete selected data information for the com mand line version of SILOS III For the graphical interface version the Silos Simulation Environment use the Load Reload Files button The form of the command is ALL ERRORS RESET OUTPUTS PATTERN SAVFILE RESET ALL ERRORS SAVFILE Application Notes Resets selected program counters and or flags as speci fied by the below options Resets everything as if you just began execution The program will not issue a warning Deletes data error flags and messages up through level 4 This can be used to continue a simulation after errors have been corrected and to clear unnecessary warning and error messages Resets the logic simulation save file data to eliminate disk storage 1 For RESET OUTPUTS new output commands can be entered from the menu selections or input from a file 2 Before using RESET SAVFILE reports should be generated and or the SAVE files should be copied to tape After RESET SAVFILE logic simulation can be continued from the last simulation time point but output reports are not available for simulation results prior to the last simulation time
411. rs all of the expressions from the Watch window To use this command right click on any part of the Watch window to open the pop up menu B 3 12 3Data Analyzer Pop up Menus B 3 12 3 1 Data Analyzer Timeline Area Goto Timepoint Opens the Goto Timepoint screen for specifying the time point for the left axis or the center of the Waveform Display window The Goto Timepoint screen enables you to precisely position the Waveform Display window for debugging and printing The time value for the Time Point box can be specified in any standard time unit such as ns for nano seconds ps for pico seconds etc i e 12000 3ns Multisim User Guide B 3 37 snus 111 SOS Silos Ill Menus Silos III Menus B 3 38 To use this command right click on any part of the timeline display area the gray area just above the Waveform Display window Pan to T1 Pan to T2 and Pan to Last View Analyzer Timepoint Pan to T1 and Pan to T2 will center the Waveform Display window around the T1 or T2 timing marker Pan to Last View will return the Waveform Display win dow to the preceding view These commands are useful during debugging for jumping between views of the simulation results To invoke the pop up menu right click on any part of the timeline display area the gray area just above the Waveform Display window Timescale Opens the Time Scale screen for setting the number of time units per division of display Set ting the timescal
412. s o ooooo oo oooo L 14 Voltage Limiter 1a ese e ne eek es een ees ed L 15 L 8 1 Characteristic Equation 0 0 000 ee L 16 L 8 2 Voltage Limiter Parameters and Defaults 0000s eee L 16 Multisim User Guide S O1 JUOD Controls L 9 L 10 L 11 L 12 Current Limiter Block eee RR RR Ras L 16 L 9 1 Current Limiter Parameters and Defaults ooococccooccooooo L 18 Voltage Controlled Limiter o ooooooococcoooocn IIIA L 19 L 10 1 Voltage Controlled Limiter Parameters and DefaultS L 20 Voltage Slew Rate Block ooococcoccocooccoo es L 20 L 11 1 Voltage Slew Rate Block Parameters and DefaultS L 21 Three Way Voltage Summer occccccc lese L 21 L 12 1 Charactistic Equation liliis L 23 L 12 2 Summer Parameters and Defaults liliis eese L 23 Electronics Workbench Appendix L Controls Components L 1 Multiplier Y as This component multiplies two input voltages X X The basic function multiplies the X and Y inputs TYE ov Vo z Vx Vy Gain factors may be applied to the X and Y inputs and to the output Examples shown below a Two DC voltages are multiplied 4V 2V 8V b Two volts DC multiplied by 2v RMS 2V 2v RMS 4v RMS c Two AC signals 2sinx and 4 cosx Multisim User Guide S O1 JUOD Controls Controls Components E09 M1 vg 2 41100 Hz 0 De
413. s Multisim User Guide Bojyeuy Analog Analog Components G 2 G 2 1 G 2 2 G 8 G 1 4 3 L3 Simulation Model This is a more complex simulation model that is equivalent to the Seven Terminal Opamp models of EWB Version 5 This model is supplied by the various manufacturers for the more complex Opamps that have additional pins to support functions such as external compensa tion and output offset balance controls Each model is unique as it was developed by the individual companies to support their prod ucts Therefore a general description of each model is not possible G 1 4 4 L4 Simulation Model This is generally the most complex opamp simulation model and is equivalent to the Nine Terminal Opamp model of EWB Version 5 Models are supplied by the various manufacturers for the more complex Opamps that have additional pins to support functions such as external compensation and output offset balance controls Each model is unique as it was developed by the individual companies to support their prod ucts Therefore a general description of each model is not possible Norton Opamp amp LM13600AN The Component The Norton amplifier or the current differencing amplifier CDA is a current based device Its behavior is similar to an opamp but it acts as a transresistance amplifier where the output voltage is proportional to the input current Norton Opamp Simulation models The same levels of simulation model
414. s ability to oppose a change in current flow is called inductance a L and is measured in henrys An inductor can have any value from uH to H Inductor tolerance is by default set to the global tolerance defined in the Analysis Monte Carlo dialog box To set the tolerance explicitly de select Use global tolerance and enter a value in the inductance tolerance field The variable inductor acts exactly like a regular inductor except that its setting can be adjusted It is simulated as an open circuit with a current across the inductor forced to zero by a large impedance value Values are set in the same way as for the potentiometer Note This model is ideal To model a real world inductor attach a capacitor and a resistor in parallel with the inductor Multisim User Guide D 7 oiseg Basic Basic Components D 5 1 D 5 2 D 5 3 D 8 Inductor Background Information An inductor is a coil of wire of one turn or more It reacts to being placed in a changing magnetic field by developing an induced voltage across the turns of the inductance and will provide current to a load across the inductance Voltages can be very large Inductors like capacitors store energy in magnetic fields Their charge and discharge times make them useful in time delay circuits Electric transformers take advantage of the transfer of energy in a magnetic field from the pri mary winding to the secondary winding usi
415. s during the same clock period B 1 2 9 5 Traffic Light Example To demonstrate tasks as well as events we will show a hardware model of a traffic light Digital model of a traffic light By Dan Hyde August 10 1995 module traffic parameter on 1 off 0 red tics 35 amber tics 3 green tics 20 reg clock red amber green will stop the simulation after 1000 time units initial begin stop at 1000 stop end initialize the lights and set up monitoring of registers initial begin Init red off amber off green off display Time green amber red Smonitor 3d Sb Sb b Stime green amber red end task to wait for tics positive edge clocks before turning light off task light output color input 31 0 tics begin repeat tics wait to detect tics positive edges on clock posedge clock color off end endtask Multisim User Guide B 1 21 Jewud Boje Verilog Primer Verilog HDL Primer B 1 22 waveform for clock period always begin H1 clock 1 clock end always begin red on light red clock wave 0 1 main process red tics green on light green green tics amber on light amber amber tics end endmodule of 2 time units call task to wait The output of the traffic light simulator is the following Time green amber red 998 0 ooHhocoHocoHo0oHo oh ooHho oh 1 Oo OF
416. s entities is done by a different engineer than the lower level architectural description of each component circuit An architecture declaration consists of zero or more declarations of items such as inter mediate signals components that will be referenced in the architecture local functions Multisim User Guide A 7 dwd TAHA VDHL Prrimer VHDL Primer and procedures and constants followed by a begin statement a series of concurrent statements and an end statement Packages and Package Bodies A VHDL package declaration is identified by the package keyword and is used to col lect commonly used declarations for use globally among different design units You can think of a package as a common storage area one used to store such things as type decla rations constants and global subprograms Items defined within a package can be made visible to any other design unit in the complete VHDL design and they can be compiled into libraries for later re use A package can consist of two basic parts a package declaration and an optional package body Package declarations can contain the following types of statements e type and subtype declarations constant declarations e global signal declarations e function and procedure declarations e attribute specifications e file declarations e component declarations e alias declarations e disconnect specifications e use clauses Items appearing within a package declaration
417. se Xposition 0 00 Trigger Edge 3 Level Channel A Yposition 0 00 Ac e oc Channel B Yposiion o o0 Bello ae Hysteresis Block Parameters and Defaults Symbol Parameter Name Default Unit ViL Input low value 0 V ViH Input high value 1 V H Hysteresis 0 1 VoL Output lower limit 0 V VoH Output upper limit 1 V ISD Input smoothing domain 96 1 L 14 Electronics Workbench Voltage Limiter L 8 Voltage Limiter Ai This is a voltage clipper The output voltage excursions are limited or clipped at predetermined upper and lower voltage levels while input signal amplitude varies widely DV AVI In the example shown below the upper voltage limit is set to 5V and the lower limit is set to 5 volts These settings provide symmetrical clipping on the positive and negative peak excursions of the input waveform when these peaks exceed the set limit clipping values The 10 v RMS 14 14v peak input is limited at 5V Note Tf the input peak voltages are within the set limiting voltages the input signal is passed through the limiter circuit undistorted Unsymmetrical clipping is selected by setting the limit voltages to different values i e 5V and 2V This technique may be used to produce non standard waveshapes starting with sine triangle sawtooth and other symmetrical waveforms INPUT OUTPUT E 10 v1 kHz Deg Oscilloscope
418. se of the nonconvergence Reports Nonconvergence only reports the basic options for the nonconvergence report For additional options such as the INPUT option that reports the states for all inputs of devices which drive the oscillating nodes and the ITER val option that specifies the iteration number to the Ist of eight states for each node reported for nonconvergence see the Reports Noncon vergence Multisim User Guide B 3 17 snus 111 SOS Silos Ill Menus Silos III Menus B 3 18 B 3 6 5 2Nonconvergence Hanging for Behavioral Designs When nonconvergence occurs in behavioral designs SILOS III may be able to stop the simu lation and report an error stating that there has been nonconvergence For nonconvergence during behavioral simulation Reports Nonconvergence may produce a report that states there is no data to report When this happens you can click on the Step button on the Main toolbar and immediately begin to single step in the nonconverged source code Infinite loops in the user s behavioral code can cause SILOS III to hang and not respond When the infinite loop occurs at time 0 SILOS III will hang and never get to the Ready prompt When the infinite loop occurs during simulation SILOS III will hang and does not respond to the STOP button or the ESC key on the keyboard Different techniques are used to debug hangs at time 0 and hangs during simulation When SILOS III hangs at time 0 an
419. section presents several sample circuits and shows how they can be described for synthe sis and testing These small examples are not intended to represent real applications but will help you to understand the relationships between various types of VHDL statements and the actual hardware being described In addition to the quick introduction to VHDL presented in this section very important con cepts such as concurrency and hierarchy will be introduced Before explaining these more complex topics a very simple example will be presented so you can see what constitutes the minimum VHDL source file A Simple Example The following is a look at a very simple combinational circuit an 8 bit comparator This com parator will accept two 8 bit inputs compare them and produce a 1 bit result either 1 indi cating a match or 0 indicating a difference between the two input values A comparator such as this is a combinational function constructed in circuitry from an arrangement of exclusive OR gates or from some other lower level structure depending on the capabilities of the target technology It is the job of logic synthesis to determine exactly what hardware representation is most appropriate for a given device entity compare is port A B in bit EQ out bit end compare architecture comparel of compare is Multisim User Guide A 3 dwd TAHA VDHL Prrimer VHDL Primer A 2 2 A 4 begin EQ lt 1 when A B else
420. sed An example would be the order of evalu ation for always Oposedge clock always Oposedge clock 1 When the disk storage limit set by CONTROL DISK is exceeded during logic the simulation will stop A message will be displayed showing the last simulation time point To continue the simulation you can increase the disk limit and re enter the SIMULATE command Another method would be to report the simulation results enter RESET SAVFILE to clear the disk file save sim saves the simulation history and then con tinue from the last simulation time point RESET ERRORS must be entered before con tinuing the simulation 2 DMAX and DMIN will not both affect the same simulation The one that is specified last will remain in effect for all netlist parsing and subsequent SIMULATE commands Multisim User Guide B 2 33 Ssuoisuejx3 JAH Bojan Verilog HDL Extensions Extensions The DMAX or DMIN scaling factor should be specified before inputting the netlist so that the netlist is parsed correctly 3 If CONTROL EUNK has been defined and there is an Unknown level on the gate s enable MOS transistors will have an uncertain conductance and interval logic will be used to resolve their source and drain see Interval Logic Resolving Uncertain Strength at a Node in the Logic Simulation chapter Transfer gates also have an uncertain conductance and their output will be resolved using intervallogic For tri
421. sim User Guide A 21 JOWUd TAHA VDHL Prrimer VHDL Primer A 22 describes a background clock with a 100 ns period while the second process stimulus describes a sequence of inputs to be applied to the circuit over time Note This sample test bench does not include any checking of output values More complex test benches that include output value checking are presented in A 4 Examples Gal lery on page A 23 library ieee use ieee std logic 1164 all entity testbnch is No ports needed in a end testbnch testbench architecture behavior of testbnch is component rotcomp is Declares the lower level port Clk Rst Load in std ulogic component and its ports Init in std ulogic vector 0 to 7 Test in std ulogic vector 0 to 7 Limit out std ulogic end component Signal Clk Rst Load std ulogic Introduces top level signals Signal Init std ulogic vector 0 to 7 to use when signal Test std ulogic vector 0 to 7 testing the lower level circuit Signal Limit std ulogic begin DUT rotcomp port map Creates an instance of the Clk Rst Load Init Test Limit lower level circuit the design under test clock process variable clktmp std ulogic 0 This process sets up a begin background clock of 100 ns clktmp not clktmp period Clk clktmp wait for 50 ns end process Stimulus process This process applies begin stimulus to the design Rst 0 inp
422. source file shown below describes this Fibonnaci sequence generator A 4 3 1 Design Description Fibonacci sequence generator Copyright 1996 Accolade Design Automation Inc library ieee use ieee std logic 1164 all entity fib is port Clk Clr in std ulogic Load in std ulogic Data in in std ulogic vector 15 downto 0 S out std ulogic vector 15 downto 0 end fib architecture behavior of fib is Signal Restart Cout std ulogic signal Stmp std ulogic vector 15 downto 0 Signal A B C std ulogic vector 15 downto 0 signal Zero std ulogic signal CarryIn CarryOut std ulogic vector 15 downto 0 begin Pl process Clk begin Multisim User Guide A 33 JOWUd TAHA VDHL Prrimer VHDL Primer A 34 if rising edge Clk then Restart Cout end if end process Stmp A xor B xor CarryIn Zero lt 1 when Stmp 0000000000000000 else 0 CarryIn lt C 15 downto 1 amp 0 CarryOut lt B and A or B or A and CarryIn C 15 downto 1 lt CarryOut 14 downto 0 Cout CarryOut 15 P2 process Clk Clr Restart begin if Clr 1 or Restart 1 then A 0000000000000000 B lt 0000000000000000 elsif rising edge Clk then if Load 1 then A lt Data_in elsif Zero 1 then A lt 0000000000000001 else A lt B end 1f B lt Stmp end if end process S Stmp end behavior A 4 3 2 Test Bench The following t
423. ssary when using different type conversion routines variable Q integer range 0 to 15 begin if Rst 1 then Asynchronous reset Q 0 elsif rising edge Clk then if Load 1 then Q to unsigned Data Convert vector to integer elsif Q 15 then Q 0 else Multisim User Guide A 25 dwd TAHA VDHL Prrimer VHDL Primer Q Q 1 end if end if Count lt to_vector 4 Q Convert integer to vector for use outside the process end process End COUNT16 A A 4 1 2 Test Bench library ieee Use ieee std logic 1164 all Entity T COUNT16 Is End T COUNT16 use work counti6 Architecture stimulus of T COUNT16 Is Component COUNT16 Port Clk Rst Load in std ulogic Data in std ulogic vector 3 downto 0 Count out std ulogic vector 3 downto 0 End Component Signal Clk Rst Load std ulogic Top level signals Signal Data std ulogic vector 3 downto 0 Signal Count std ulogic vector 3 downto 0 Signal Clock cycle natural 0 Begin DUT COUNT16 Port Map Clk Rst Load Data Count The first process sets up a 20Mhz background clock CLOCK process begin Clock cycle lt Clock cycle 1 Clk ez Vit wait for 25 ns CIk mrt wait for 25 ns A 26 Electronics Workbench Examples Gallery A 4 2 end process This process applies stimulus to reset and load the counter Stimulusl Process Begin RsSt lt I wait for 40 ns RSt lt 05 Load
424. standard data type is called std_logic and the IEEE 1164 package is often referred to as the standard logic package or MVL9 for multi valued logic nine values The IEEE 1076 1987 and IEEE 1164 standards together form the VHDL standard in widest use today IEEE 1076 1993 is slowly working its way into the VHDL mainstream but it does not add significant new features for synthesis users A 1 2 1 IEEE Standard 1076 3 Numeric Standard Standard 1076 3 often called the Numeric Standard or Synthesis Standard defines standard packages and interpretations for VHDL data types as they relate to actual hardware This stan dard is intended to replace the many custom nonstandard packages that vendors of synthesis tools have created and distributed with their products IEEE Standard 1076 3 does for synthesis users what IEEE 1164 did for simulation users increase the power of Standard 1076 while at the same time ensuring compatibility between different vendors tools The 1076 3 standard includes among other things A documented hardware interpretation of values belonging to the bit and boolean types defined by IEEE Standard 1076 as well as interpretations of the std ulogic type defined by IEEE Standard 1164 e A function that provides don t care or wild card testing of values based on the std ulogic type This is of particular use for synthesis since it is often helpful to express logic in terms of don t care values D
425. statements Do not confuse logical operators with the bitwise Boolean operators For example is a logical NOT and is a bitwise NOT The first negates e g 5 6 is TRUE The second complements the bits e g 1 0 1 1 is 0100 Multisim User Guide B 1 11 Jewud Boje Verilog Primer Verilog HDL Primer B 1 12 Operator Name Comments Logical negation amp amp Logical AND Logical OR B 1 2 5 5 Bitwise Operators Bitwise operators operate on the bits of the operand or operands For example the result of A amp B is the AND of each corresponding bit of A with B Operating on an unknown x bit results in the expected value For example the AND of an x with a FALSE is an x The OR of an x with a TRUE is a TRUE Operator Name Comments Bitwise negation Bitwise AND Bitwise OR Bitwise XOR amp Bitwise NAND Bitwise NOR A or EquivalenceBitwise NOT XOR gt m B 1 2 5 6 Unary Reduction Operators Unary reduction operators produce a single bit result from applying the operator to all of the bits of the operand For example amp A will AND all the bits of A Operator Name Comments amp AND reduction OR reduction XOR reduction amp NAND reduction NOR reduction A XNOR reduction B 1 2 5 7 Other Operators The conditional operator operates much like in the language C Operator Name Comments mE Case equality The bitwise comparison includes comparison of x an
426. stop the logic simulation Assigns the maximum allowed iterations for each pass during LINIT See note 4 Maximum MXDCI 9999 Default MXDCI 100 Assigns the iteration limit to reach convergence for each logic simulation time point See note 4 Maximum MXITR 999 Default MXITR 300 Causes SILOS III to not save SAVCELL 0 or to save SAVCELL 1 the simulation history for variables listed between the celldefine and endcelldefine compiler direc tives Caution Saving all variables between celldefine and endcelldefine compiler directives may slow down simulation and create larger save files on disk Default SAVCELL 0 Sets the logic simulation save option to determine which simulation node state changes are saved on the SAVE disk file The savsim option must be specified before simulation begins Default SAVSIM 0 Specifies that no simulation node values are to be saved This has limited use as no data is available Specifies that node simulation values logic type integer type and double type are to be saved only for nodes named in the TABLE PLOT GNAME TESTER KEEP MKEEP HEX and OCT commands Output results can be obtained only for the saved nodes This option decreases simulation disk file size and reduces execution time Specifies that all logic type simulation node states are to be saved for all nodes in the circuit This option prevents saving integer and floating point values Electroni
427. suspends all signals that were assigned values in the process in this case Q are updated and the process waits for another event on Clk or Rst What about the case in which there is an event on Clk In this case the process will again exe cute and the if then elsif expressions will be evaluated in turn until a valid condition is encountered If the Rst input continues to have a high value a value of 1 then the simulator will evaluate the first if test as true and the reset condition will take priority If however the Rst input is not a value of 1 then the next expression Clk 1 and Clk event will be evaluated This expression is the most commonly used convention for detecting clock edges Electronics Workbench Learning VHDL in VHDL To detect a rising edge clock write the expression Clk 1 in the conditional expression For this circuit however the expression Clk 1 would not be specific enough since the process may have begun execution as the result of an event on Rst that did not result in Rst transitioning to a 1 For example a falling edge event on Rst that is a transition from 1 to 0 would trigger the process but cause it to skip to the elsif statement even though there was no event on Clk since the Rst 2 1 condition would evaluate as false To ensure that the event we are responding to is in fact an event on Clk we use the built in VHDL attribute event to check i
428. t 01010101 for i in 0 to 100000 loop wait for PERIOD end loop Load in the test value to check the end of frame detection TestLoad lt 1 wait for PERIOD TestLoad lt 0 for i in 0 to 300 loop wait for PERIOD end loop done true End Process End stimulus A 32 Electronics Workbench Examples Gallery A 4 3 Reading and Writing from Files More complex test benches often make use of VHDL s file read and write capabilities These features make it easy to create test benches that operate on data stored in files such as test vectors The following example demonstrates how you can use the text I O features of VHDL to read test data from an ASCII file Consider a Fibonacci sequence generator A Fibonnaci sequence is a series of numbers begin ning with 1 1 2 3 5 in which every number in the sequence is the sum of the previous two numbers To construct a circuit that generates an n bit Fibonacci sequence two n bit registers A and B are required to store the last two values of the sequence and add them to pro duce the next value To initialize the circuit the A and B registers must be loaded with values of 0 and 1 respec tively Subsequent cycles of the circuit must move the calculated next value into the B register while moving the value stored in the B register to the A register In this implementation the A and B registers form a 2 deep first in first out FIFO stack The VHDL
429. t Another example is the Zero Thickness stripline which is a very good approximation for striplines in which the thickness of the conductor is negligible compared to the distance it has from the ground planes Multisim User Guide M 3 Ju RF RF Components Electronics Workbench Appendix N Electro Mechanical Components MT Switches lbs ue A erai e mE tea Ni2 Line Transformer iuuenis 2 4 22 2 u o A RE NI PUIW S ed gx gue PEE N 3 Coils Relays 5 orto tex ee nete bu tao da a cerni d N 4 lt Timed Contacts etico cw EE RARE RR eee texere edd as exte eda N 5 Protection Devices oooooooooccccon enn N 6 Output Devices gt cn a Gad a pets Giese C EEEUPER OEC EE Ges Nie Push Buttons zs dE ec adel ec Roda Babee REUS E NR DA Rn N 8 Pilot LIGAS oe a A WE ELE Ben E WR Ep N 9 Terminals ats aee anne Nee ten dead a e tes Multisim User Guide jes Ley99W 019913 Electro mechanical Electronics Workbench Appendix N Electro Mechanical Components N 1 Switches 1 Switches can be closed or opened turned on or off by pressing a key on the keyboard You specify the key that controls the switch by typing its name in the Value tab of the component s Properties screen For example if you want the Key Space tab then click OK switch to close or open when the spacebar is pressed type space in the Value A list of possible key names is shown below To use Type
430. t are added to the Default group click on the minus sign just to the left of the Default group in the Name list box SILOS III will ask you if you want to save the changes to the Default group Multisim User Guide B 3 41 snuey III SOS Silos Ill Menus Silos III Menus B 3 42 Set Radix Located in the pop up menu for the Name list box Setting the radix for a vector can assist with debugging the design The radix can be set to binary octal or hexadecimal to conve niently display the vector Symbolic names can be used to represent the values for a state machine ASCII vectors can be displayed to create a timeline of events for the Data Analyzer display To invoke the pop up menu right click on any part of the Name list box To set the radix for a vector 1 Right click on the vector to open the pop up menu 2 Choose Set Radix from the pop up menu 3 The Set Radix screen will then be opened and you can select the Radix 4 If you select the Symbol Table radix then select the correct symbol table in the Symbol Table box 5 To close the screen and set the vector to the selected radix click OK Clicking Cancel closes the screen and does not affect the vector s radix Bit Commands The pop up menu for the Name list box for the Data Analyzer has the following commands Add One Bit Adds a single bit signal at a high level just ahead of the selected signal name e Add Zero Bit Adds a single bi
431. t drivers BCD to decimal decoder driver truth table INPUTS OUTPUTS No D C B A 0 1 2 3 4 5 6 7 8 9 O 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 1 1 at 1 1 1 1 2 0 0 1 0 1 1 0 1 1 1 1 1 1 1 3 0 0 1 1 1 1 1 0 1 al 1 1 1 1 4 0 1 0 0 1 1 1 1 0 1 1 1 1 1 5 0 1 0 1 1 1 1 1 1 0 1 1 1 1 6 0 1 1 0 1 1 1 1 1 1 0 1 1 1 7 0 1 1 1 1 1 1 1 i 1 1 0 1 1 8 1 0 0 0 1 al 1 1 i 1 1 1 0 1 9 1 0 0 1 1 1 1 1 i 1 1 1 1 0 1 0 1 0 y 1 1 1 1 1 1 1 i 1 al SE 0 1 1 1 1 1 1 1 d 1 1 1 1 nla 1 0 0 1 1 1 1 al 1 1 1 1 1 E 1 T 0 1 Y 1 1 1 1 1 1 1 1 1 Ala 1 1 0 1 1 1 i 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Multisim User Guide P 15 seues Xxv4 suonounJj Functions 74XX Series Functions 74XX series P 5 31 74xx147 10 to 4 Priority Enc This TTL encoder features priority decoding of the inputs to ensure that only the highest order data line is encoded It encodes nine data lines to four line 8 4 2 1 BCD 101 line to 4 line priority encoder truth table INPUTS OUTPUTS 1 2 3 4 5 6 7 8 9 D c B A 1 1 1 i 1 d 1 1 1 I 1 4 al X X X X X X X X 0 0 d 1 0 X X X X X X X 0 1 0 1 1 1 X X X X X X 0 1 1 1 0 0 0 X X X X X 0 1 1 1 d 0 0 1 X X X X 0 5 1 1 al 1 0 I 0 X X X 0 1 Ai L 1 al d 0 d 1 X X 0 1 1 d 1 1 al d 1 0 0 X 0 1 1 L 1 1 a 1 1 Y 0 1 0 A 1 1 di 1 1 d 1 1 Y 1 0 P 5 32 74xx148 8 to 3 Priority Enc This TTL encoder features priority decoding of the inputs to ensure that only the highest order data line is enco
432. t initial construct will delay for 20 time units before calling the system task stop and stop the simulation The display system task allows the designer to print a message much like printf does in the language C Every time unit that one of the listed variable s value changes the mon itor system task prints a message The system function time returns the current value of simulated time Below is the output Time A B 0 00000000 XXXXXXXX 00000001 XXXXXXXX 00000001 1110xxxx 00000001 1110xxxx 00000010 1110xxxx 00000010 1101xxxx UR WNP oOooonx X x NM Electronics Workbench The Verilog Language 7 00000011 1101xxxx 0 8 00000011 1100xxxx 0 9 00000011 1100xxxx 1 10 00000100 1100xxxx 11 00000100 1011xxxx 12 00000100 1011xxxx 13 00000101 1011xxxx 14 00000101 1010xxxx 16 00000110 1010xxxx 17 00000110 1001xxxx 19 00000111 1001xxxx Stop at simulation time 20 Ooooo0o 0nnmin You should carefully study the program and its output before going on The structure of the program is typical of the Verilog programs you will write for this course i e an initial construct to specify the length of the simulation another initial construct to initialize reg isters and specify which registers to monitor and an always construct for the digital system you are modeling Notice that all the statements in the second initial are done at time 0 since there are no delay statements i e lt integer gt B 1 2 2Lexical Conventions The
433. t signal at a low level just ahead of the selected signal name Reverse Bit Order Reverses the signal order for the highlighted signals in the Name list box This is useful for reversing the bit order for a group To invoke the pop up menu right click on any part of the Name list box Add Signal Opens the Specify Signal Expression screen Adding a signal can be very useful for performing conditional searches The added waveform can be any expression whether the expression exists in your HDL source code or not For a conditional search you can then use the scan to change feature and the States List Box to review the signal values for the conditional search The Add Signal feature can also be useful for adding expressions that exist in your source code such as for an if test and then viewing then the expression is true high The Specify Signal Expression screen contains an edit box Scope to specify the scope for the signal The Specify Signal Expression screen also contains a Signal or Expression edit box to enter a signal or an expression Any valid Verilog HDL expression can be entered Electronics Workbench Pop up Menus however the expression must be enclosed by parentheses You can copy and paste an expres sion that is in your source code window by highlighting the expression and using the CTRL C keys to copy and the CTRL V keys to paste the expression into the Signal or Expression list box If the expressi
434. t the insertion point or replaces selected text in a document To invoke the pop up menu right click on any part of the source window B 3 12 4 5Add Remove Breakpoint Places or removes a simulation breakpoint at the location of the cursor in the source window To invoke the pop up menu right click on any part of the source window B 3 12 4 6Data Tips Toggles the Data Tips capability on or off The Data Tips capability displays the value scope radix and simulation time point for a variable or expression in the source window Any variable or expression in a source window can be viewed by opening the source window and holding the mouse cursor over a variable or by highlighting an expression and holding the mouse cursor over the expression This feature enables you to trace the cause of problems directly in a Verilog HDL source code window To invoke the pop up menu right click on any part of the source window B 3 12 4 7Data Tip Radix Sets the radix for the Data Tips capability The allowed radixes are binary octal hexadecimal decimal and string The Data Tips capability displays the value scope radix and simulation time point for a vari able or expression in the source window Any variable or expression in a source window can be viewed by opening the source window and holding the mouse cursor over a variable or by highlighting an expression and holding the mouse cursor over the expression This feature enables yo
435. t4 dff2 Nq specify You can continue to double click on device inputs and trace your way back through the topol ogy To undo your signal tracing double click on the signal name that was traced If you see No Saved Data instead of a waveform this may mean that the signal is inside of a celldefine boundary To save data within celldefine boundaries see the Save celldefine data option in Project Project Settings Display Iteration Data Useful for finding order of evaluation problems and race conditions To invoke the pop up menu right click on any part of the Name list box When the Display Iteration Data command is chosen it opens an Iteration Data window that displays all of the iterations at a single timepoint for each signal in the Name list box The timepoint to display the iterations is specified by the T1 timing marker To display a text report for iterations at a timepoint see Reports Iteration Groups of Signals Using groups provides a convenient method for organizing your signals in the Data Analyzer window Not only does this help organize the display of your signals it also prevents you from losing your list of signals if the default group gets inadvertently changed or lost Display groups are also useful for assisting engineers who are unfamiliar with the design and for record keeping if the design is reused Electronics Workbench Pop up Menus The pop up menu for the Name list box provides the follow
436. tage controlled sine wave oscillator C 8 voltage controlled square wave oscillator C 10 voltage controlled triangle wave oscillator C 12 voltage controlled voltage source C 7 voltmeter about J 1 connecting J 2 mode J 1 xiv Electronics Workbench
437. ter format display in decimal format display in hex format display in octal format display in string format oo o9 o9 o9 oe noraa A 0 between the and format specifier allocates the exact number of characters required to display the expression result instead of the expression s largest possible value the default For example this is useful for displaying the time as shown by the difference between the fol lowing two display statements Multisim User Guide B 1 23 Jewud Boe Verilog Primer Verilog HDL Primer display Time d time display Time 0d time produces the following output Time 1 Time 1 Escape sequences may be included in a string The commonly used escape sequences are the following An the newline character Nt the tab character the character the character the percent sign A null parameter produces a single space character in the display A null parameter is charac terized by two adjacent commas in the parameter list Note that display automatically adds a newline character to the end of its output See write in Verilog Language Reference Manual if you don t want a newline B 1 3 3 Sfinish The inish system task exits the simulator to the host operating system Don t forget to type the semicolon while in interactive mode Sfinish B 1 3 4 monitor The moni tor system task provides the ability to monitor and display the values of any variable or expr
438. tered in the netlist You can stop the simulation by clicking on the STOP button or pushing the Escape key Esc on the keyboard for the PC and Ctrl C on Unix e Specifying a single time point indicates that simulation will be incrementally contin ued for that amount of time At time 0 this will start the simulation from time 0 for the specified amount of time e Y Specifying tl and t2 with t1 0 runs the simulation from time 0 to time t2 e Specifying tl and t2 with tl greater than zero continues the simulation from the last specified time point e Specifying TO t2 will continue the simulation until time t2 This can be useful to continue a simulation that was halted due to a breakpoint 2 The SIMULATE command will automatically invoke the PREPROC command if PRE PROC has not already been performed and no further topological data can be entered 3 Simulation can either be continued from the last time point or restarted from time 0 4 The SIMULATE command uses inertial delays which do not propagate level changes that occur faster than the gate output can change spike condition Examples simul 0 to 22k SIM 5KGG 10K SIM 5K sim 0 15k SI TO 5K B 2 2 23Size Of Data Reprint The SIZES command reports the memory usage for SILOS III To report the network size information enter TYPE STORESIZES WTYPE NSTORE TYPE optional directs the size informa STORE tion to standard output STOREor to a disk file
439. terface on the Workstation B2 2 B 2 1 1 3List of Implemented PLI Routines o o cooooccoooo o B2 3 B 2 1 2Standard Delay Format llis B2 3 B 2 1 3Expected Values and Stimulustable 000 000 eee eee B2 5 B 2 1 9 BNE sins ea nr de ea para Priore bar d ES We pes ud a ie E B2 5 B 2 1 3 2Stimulustable 1 0 0 0 00 eres B2 6 B21 3 SRAGIKG tec tan See a DEPO Ua Marge e ead ed B2 7 B 2 1 3 4Delay Time Locos AS ae el a Pa a oe B2 7 B 2 1 3 5Memory Utilization llle B2 8 B 2 1 3 6S9trobe oL nU VILLE Baal B2 9 B 2 1 3 7 l O Pad sus rv ee eee u gt B2 10 B 2 1 3 8Expected Value Error 2 22 elis B2 10 B 2 1 3 9Expected Value Error Storage 0 eee B2 12 B 2 1 3 10Incremental Update ocoocccccooccc een nn B2 12 B 2 1 3 11Changing Behavioral Stimulus to a stimulustable Format B2 14 B 2 1 3 12Analog Behavioral Modeling AHDL ooooo co oo B2 15 B 2 1 3 13Specifying the Analog Behavioral Modeling Project B2 16 B 2 1 3 14Running the Analog Behavioral Modeling Simulation B2 16 B 2 1 4Analog EXtensiOnS oooooccooeoorr enne B2 17 B 2 1 4 1Real and Integer Data Types 0 0 0 B2 17 B 2 1 4 2Utility Transcendental Functions 00 02 00 eee eee B2 17 B 2 1 4 3Examples for Transcendental Math Functions B2 18 B 2 1 5 silos and sse keywords llis B2 19 B 2 1 6Extensions to Turn off
440. th the hier archical tree of the Explorer window The pop up menu will remain open while the left mouse button is used to select a menu item The Watch window has a pop up menu for the Add Signal Expression Set Value Free Forced Wire and Clear All commands To invoke this pop up menu use the right mouse button to click on any part of the Watch window The pop up menu will remain open while the left mouse button is used to select a menu item The Data Analyzer has a pop up menu for the Goto Timepoint Pan to T1 Pan to T2 Pan to Last View Timescale Snap to Edges Add Bookmark and Delete Bookmark commands To invoke this pop up menu use the right mouse button to click on any part of the time point display area the gray area just above the Waveform Display window The pop up menu will remain open while the mouse is used to select a menu item The Data Analyzer has a pop up menu for the Trace Signal Inputs Display Iteration Data New Group Delete Group Insert Group Show Groups Set Radix Add One Bit Add Zero Bit Reverse Bit Order Add Signal Add Blank Line and Clear Signal List commands To invoke this pop up menu use the right mouse button to click on any part of the Signal list box B 3 12 1Explorer Window B 3 12 1 1 Add Signals to Analyzer Useful for adding signals to the Data Analyzer when it is difficult to drag and drop the signals due the screen size To use this command right click on any part of the right
441. the devices that are driving the net To invoke the pop up menu right click on any part of the Name list box When you wish to trace a net highlight a signal name in the Name list box of the Data Ana lyzer With the mouse cursor still in the Name list box right click to open the pop up menu Next choose Trace Signal Inputs from the pop up menu A Trace Signal Inputs window will then be opened and it will display the signals that are driving the net you selected To continue the fan in tracing double click on any input and the waveform for that node will be displayed along with the waveforms for the devices driving it To undo your signal trac ing double click on the node name that is being traced When the waveforms for the Trace Signal Inputs window are displayed the name of the node being traced is listed first in the Name box Blank lines delineate each device listed in the Name box The format for each device is similar to the format for a module instance when passing ports by name in Verilog HDL For example the name not top bit4 dff2 n6 out top bit4 dff2 Nq specify in top bit4 dff2 gbar specify Multisim User Guide B 3 39 snus 111 SOS Silos Ill Menus Silos III Menus B 3 40 The device isa not gate and the instance name is top bit4 dff2 n6 The output port name out has the instance name top bit4 dff2 Nq specify The input port name in has the instance name top bi
442. the 8 inputs into the device apply a low level at the shift load input Multisim User Guide P 27 seues XXpZ suonounJj Functions 74XX series Functions 74XX Series Shift register truth table INPUTS INTERNAL OUTPUTS O P cur SHIFT OLK INH CLK SERIAL EORUM QA OB QH LOAD A through H 0 X X X X X X X X 0 0 0 1 X 0 0 X X X X X QAO QBO OHO 1 0 0 X A TO H b 1 1 1 0 1 X X X X 1 QAn QGn E 1 0 0 X X X X 0 QAn QGn 1 X HE x x X X X QAO QBO OHO transition from low to high a b c d the level of steady state input at A B C or D respectively P 5 52 74xx169 Sync 4 bit up down Binary Counter This synchronous presettable 4 bit binary counter has an internal carry look ahead for cascad ing in high speed counting applications Up down counter truth table ENP ENT D U CLK LOAD A B C D QA QB QC QD RCO 0 0 X X 0 X X X X A B c D dex 0 0 1 1 X X X X Count Down L 0 0 0 1 X X X X Count Up l al X X X X X X X X Qa0 QbO QcO OQdO 1 X 1 X X X X X X X Qa0 QbO QcO Qdo 1 1 during the UP count RCO goes LOW at count 15 during the DOWN count RCO goes LOW at count 0 P 5 53 74xx17 Hex BUFFER OC This device contains six independent BUFFER Drivers For correct performance the open collector outputs require pull up resistors P 28 Electronics Workbench 74XX BUFFER gate truth table Y 0 i oj gt P 5 54 74xx173 4 bit D type Reg w 3 state Out D type register truth table
443. the menu structure However a Command window has been provided in the Main Toolbar for SILOS III to enter any command On Unix an additional SILOS III executable silos is also provided that run SILOS III from the Ready prompt B 2 2 1 3Stopping Processes To discontinue or stop an interactive process when running SILOS III such as during a large report that is output to the terminal enter e Ctrl C simultaneously hold down the Ctrl key and the C key on the keyboard for the Unix command line version of HyperFault Esc key on the keyboard for all Windows versions STOP button on Toolbar for all Windows versions B 2 2 2 Activity Report For Nodes B 2 26 The ACTIVITY command pre grades the test vectors for fault simulation by reporting nodes that have no activity level transitions during a logic simulation for the test vectors The logic simulation is much faster to run than fault simulation The ACTIVITY command can also be used as an HDL code coverage report This section of the Activity report lists the number of times that each line of HDL code was executed as spec ified by the MXTRAN and MNTRAN keywords To obtain a node activity report enter Electronics Workbench Silos III Command Line Usage TYPE STORE WTYPE NSTORE where Allowed keywords are Multisim User Guide TYPE STORE ACTIVITY t1 TO t2 keywrd BLOCK MNTRAN val MXTRAN val val NOHIST NOSUM NOTAB AC
444. the same functions as a potentiometer but has a user settable value Pullup sy This component is used to raise the voltage of a circuit to which it is connected ps One end is connected to Vcc The other end is connected to a point in a logic cir PULLUF cuit that needs to be raised to a voltage level closer to Vcc Resistor Packs s R2 Resistor packs are collections of resistors within a single package The configuration of the resistors can be varied based on the intended usage 1x4siP_ of the package Resistor packs are used to minimize the amount of space d required on the PCB for the design In some applications noise can be a 313 1a consideration for the use of resistor packs Magnetic Core Ti This component is a conceptual model that you can use as a building block to iff create a wide variety of inductive and magnetic circuit models Typically you would use the magnetic core together with the coreless coil to build up sys 4sqm 1m tems that mock the behavior of linear and nonlinear magnetic components It takes as input a voltage which it treats as a magnetomotive force mmf value Characteristic Equation Magnetic field intensity H is H mmf l where mmf magnetomotive force the input voltage Electronics Workbench Magnetic Core I core length Flux density B is derived from a piecewise linear transfer function described to the model by the magnetic field flux density pairs that you input in the
445. the status bar in the lower right hand corner of SILOS III Next kill SILOS III restart SILOS III and click the Load Reload Files When SILOS III stops at time 0 enter a simulation time to one less then when the simulation hangs in the Command window for the Main toolbar Such as if the simulation hangs at time 11251ns enter sim 11250ns so that SILOS III stops just before it hangs Then click the Step button Keep sin gle stepping until you find the problem code If you single step past the time point where the simulation was hanging then the time value for the status bar had not yet been updated when SILOS III hung To find the true time value that SILOS III hangs at keep entering short simulation times at the Ready prompt until the simulation hangs such as enter sim 10ns or sim Ins until the simulation hangs Then restart SILOS III re simulate to just before the simulation hangs and single step until you find the problem B 3 6 6 Reports Size B 3 7 Reports the memory usage for SILOS III A simpler method of obtaining the memory usage is to choose Help About SSE to open the About SSE screen which has the memory usage for SILOS III The memory usage will increase during circuit read in and preprocessing until simulation starts at time 0 After simulation starts the memory usage remains constant Explorer Menu The Explorer menu provides the following commands e Explorer Open Explorer e Explorer Go to Modu
446. tinue the simulation until the end of the current timepoint This is useful to com plete the time step during single stepping so that the Data Analyzer waveforms are updated B 3 8 4 Debug Restart Simulation Restarts the SILOS III program from time zero This is useful if you have reviewed the simu lation results and want to rerun the simulation to set breakpoints or to force signals to a value B 3 8 5 Debug Step Single steps through the HDL source code for the project As SILOS III single steps it places a yellow arrow to the left of the line Single stepping can be very useful when combined with breakpoints and the Watch window for debugging behavioral code As you step through the HDL source code you can highlight variables and expressions and drag and drop them into the Data Analyzer window and the Watch window The toolbar also has a Step button B 3 22 Electronics Workbench Debug Menu B 3 8 6 Debug Breakpoints Opens the Breakpoints screen for setting breakpoints A typical method to debug a design using breakpoints would be to set a breakpoint in a module instance then click on the Go but ton on the toolbar and simulate until the simulation stops in the module with the breakpoint Next single step through the module to review how the source code is executing and watch variables change value in the Watch window and the Data Analyzer window The Go button could then be used again to simulate until the simulation stops in th
447. tion limit is exceeded the circuit nonconverges A simple example of a circuit that would cause nonconvergence is a ring of three inverters whose delays are set to zero Zero delays occur during logic simulation when either a zero delay or no delay is specified for devices the default delay for Verilog HDL gate devices is zero Zero delays also occur during logic initialization LINIT com mand which forces delays to be zero so that SILOS III can perform a steady state DC solu tion of the circuit at time 0 Nonconvergence may be due either to circuit path length or problems with designs involving feedback To eliminate oscillations caused by problems involving feedback the circuit design Electronics Workbench Reports Menu must be corrected When nonconvergence is due to path length increasing the iteration limit should enable the circuit to converge In general each node in a serial path length requires one iteration to propagate a signal The iteration limit during simulation is specified by the CONTROL MXITR command The iteration limit at time 0 is specified by the CON TROL MXDCT command Arbitrarily increasing the iteration limits is not recommended as it may dramatically increase the execution time necessary to reach nonconvergence To debug a non convergence due to a problem in the circuit design you will need to use the NONCONV command to store the nonconvergence report Reports Nonconvergence Many times an import
448. tions 4000 series ICs O 2 4 BCD to 10 Decimal Dec P 64 4 bit BCD Down Counter O 48 4 bit Bidirect Univ Shift Reg P 35 4 bit Bin Counter O 10 40161 O 10 40193 O 15 4 bit Bin Down Counter O 48 4 bit Bin Full Add P 50 4 bit Bin Full Adder P 79 4 bit Bin BCD Dec Counter O 21 4 bit Binary Counter 74xx293 P 51 74xx93 P 82 4 bit Binary Full Adder O 4 Multisim User Guide 4 bit Bistable Latches 74xx375 P 59 74xx75 P 76 74xx77 P 77 4 bit Cascadable Shift Reg w 3 state Out P 63 4 bit Comparator O 54 4 bit Dec Counter 40160 O 9 40162 O 10 40192 O 14 4 bit D type Reg w 3 state Out P 29 4 bit Mag COMP P 79 4 bit Parallel Access Shift Reg P 35 4 bit Shift Register 40194 O 15 40195 O 15 4035 O 22 4 bit Shifter w 3 state Out P 53 4 to 16 Dec DEMUX P 19 4 to 16 Dec DEMUX OC P 22 4 Wide 2 In AND OR INVERTER O 36 4 wide AND OR INVERTER P 74 5 stage Johnson Counter 4017 O 11 4018 O 13 74xx series functions See functions 7 stage Binary Counter O 17 8 Bit Bist Latch P 6 8 bit Latch 4099 O 38 74xx259 P 47 8 bit Parallel Out Serial Shift Reg P 26 8 bit Priority Enc O 49 8 bit Shift Reg P 80 8 bit Shift Reg sh ld ctrl P 37 8 bit Shift Reg shl shr ctrl P 36 8 bit Static Shift Reg O 7 8 bit Static Shift Register O 16 8 In MUX w 3 state Out O 42 8 In NAND 4068 O 28 74xx30 P 52 8 In NOR O 32 8 stage Serial Shift Register O 37 8 to 3 Priority Enc P 16 9 bit Odd even Par GEN P 30 9 bit odd even
449. to the continuous assignments B 2 1 3 12Analog Behavioral Modeling AHDL This example demonstrates analog behavioral modeling using the SILOS Simulation Envi ronment SSE for more information see B 2 1 4 Analog Extensions Skills presented in this section are Setting up a project for analog simulation Using analog behavioral modeling in a gate level simulation Viewing analog and digital waveforms in the Data Analyzer Window The file used for this example is listed below Multisim User Guide B 2 15 SUOISUSIXF JAH POMA Verilog HDL Extensions Extensions B 2 16 analog v Shows a simple example of an A D converter modeled with analog behavioral modeling and gate level logic B 2 1 3 13Specifying the Analog Behavioral Modeling Project For this example file analog v shows an A D converter with comments For additional information see B 2 1 4 Analog Extensions The essential ideas for analog behavioral modeling are Y SILOS III has the ability to pass real variables and integer variables in module ports There is no need to convert reals or integers to bit vectors This is an extension to the IEEE standard for Verilog HDL If you need the real or integer variables to behave as wires you can use the wire real or wire integer declaration For more information see B 2 1 4 1 Real and Integer Data Types Y SILOS III supports analog extensions that allow you to put most of the standar
450. tor Background Information 0 0 0c eee eee D 5 D 4 2 Characteristic Equation oooooooocccoooncrre rennen D 5 D4 3 DC Modeli u 2 52 sre user P a Sadia seals eae nc Beats Aud D 5 D 4 3 1Time Domain Model 0 0000 cee eee D 5 D 4 4 AC Frequency Model 0 000 ccc eee tte D 7 D 4 5 Capacitor Virtual 0 0 0 0 0 eee D 7 D 5 Induclor ans as en RD uen ea Sih aa rs e whiten ERA nea oy D 7 D 5 1 Inductor Background Information 0 0 0 0 eee es D 8 D 5 2 Characteristic Equation sassa aaaeeeaa D 8 D 5 3 DE Model 2 onere a Hare x tn ee nr ae D 8 D 5 4 Time Domain Model 00 000 cee eee D 9 D 5 5 AC Frequency Model 00000 e eee ns D 10 D 5 6 Inductor Virtual tai ia aie Y vb epe al Em Wh aie X ERIS D 10 D 6 Transformer oci ug hx DES DRE RUPEE ERI RUNE RE ABO Ine EUR E Red D 10 D 6 1 Characteristic Equation llli eee D 11 D 6 2 Ideal Transformer Model Parameters and DefaultS D 11 D 7 Nonlinear Transformer seai aei okak unka n ete D 12 D 7 1 GUSTOMIZING cir RI OD mt uem t tete a med D 12 D 7 2 Nonlinear Transformer Parameters and DefaultS o D 13 DIS Rel Yi EUR eR D TNR ERATIS ET A DP quac eer ae eR A D 13 8 1 Models nagaire 3202 rss arta D 14 Multisim User Guide oiseg Basic D 9 D 10 D 12 D 13 D 14 D 15 D 8 2 Characteristic Equation iliis D 14 Variable Capacitor
451. tors and 183712 demodulators The unique operating curve of the tunnel diode is a result of the heavy doping used in the manufacturing of the diode The tunnel diode is doped about one thousand times as heavily as standard pn junction diode The tunnel diode is different from any other diode because of its negative resistance region In this area forward voltage and current are inversely proportional For example an increase in forward voltage would result in a reduction in diode current A tunnel diode can also be used to generate a sinusoidal voltage using a DC supply and a few passive elements M 6 Strip Line B Stripline is one of the most commonly used transmission lines at micro N wave frequencies Stripline is coined for ground conductor ground trans saMPLE Beno Mission line with a dielectric normally air in between Due to the multiplicity of the circuit functions substrate technologies and fre quency bands there is a wide range of stripline conductors For example microstrip lines are a special type of stripline where the upper ground is placed at infinity Depending on the posi tion of the stripline conductors the shape of the conductor and the thickness of the conductor the equations governing the behavior of one stripline to another differ For example the cen tered stripline often called Tri Plate line is a stripline where the conductance is placed sym metrically in each position from top bottom left and righ
452. triggered clock input CP and buffered parallel outputs ar from the last three stages Os to Oy P5 Z PE Following are two 8 bit static shift register truth tables LR dd g JDS s PE TEC Multisim User Guide O 7 seues 000p suonounJ Functions 4000 series Functions 4000 Series Serial Operation INPUTS OUTPUTS n PE DS gt CLK PO Pl P2 P3 P4 P5 P6 P705 06 07 1 0 DI XO X X 0X X X 0X XD VE GE X 2 0 D2 X X 0X KR XE ok XV x 3 0 D3 X X X X X X X X X X X 4 0 D4 X X X X X X X X X X X 5 0 D5 X X X X X X X X X X X 6 0 D6 X X X X X X X xX D1 x x 7 0 D7 X X X X X X X x D2 D x 9 0 D8 X X X X X X X X D3 D2 DI 10 0 D9 X X X X X X X X D4 D3 D2 X X X 5 X X X X X X X X no change Parallel Operation INPUTS OUTPUTS PE DS gt CLK PO P1 P2 P3 P4 P5 P6 P7 05 06 07 HE X x X X X X X X X X A X T X X X X X X X X P5 P6 P7 no change O 2 12 4015 Dual 4 bit Static Shift Reg The 4015 device is a dual edge triggered 4 bit static shift register serial cll a E to parallel converter Each shift register has a serial data input D a 4 018 le clock input CP four fully buffered parallel outputs Og to O5 and an w Me s 2 overriding asynchronous master reset input MR O 8 Electronics Workbench 4000 Series ICs Shift register truth table no change 0 0 0 0 HIGH state the more positive voltage LOW state the less positive voltage state is immaterial positive going
453. trol ext stim Multisim User Guide B 2 23 suoisueix3 JAH Bojan Verilog HDL Extensions Extensions B 2 24 B 2 1 7 16 input output inout declarations after the variable s declaration example module foo in wire in input in SILOS III command to allow this extension Icontrol ext inout For more information see section 12 1 of the Verilog HDL Reference on line help file B 2 1 7 17Using registers as module inputs example module xx in input in reg in SILOS III command to allow this extension Icontrol ext rsink For more information see section 12 4 6 of the Verilog HDL Reference on line help file B 2 1 7 18Duplicate variable definitions example module foo wire a wire a SILOS III command to allow this extension Icontrol ext dvd For more information see section 3 1 of the Verilog HDL Reference on line help file B 2 1 7 19Parameter used for sizing numbers example module foo reg 7 0 xx parameter size 8 initial XX size b010 SILOS III command to allow this extension control ext psize For more information see section 2 3 of the Verilog HDL Reference on line help file Electronics Workbench Verilog HDL Extensions B 2 1 7 20Null statements example module foo initial begin SILOS III command to allow this extension Icontrol ext nstmt For more information see sections 8 7 1 of the Verilog HDL Reference on line help file B 2 1 7 21
454. trols the bi directional I O pin bi pad When enable is high 1 pin bi pad acts as an output pin and expected value checking is performed every time strobel goes high The stimulustable also ignores any values in the table for pin bi pad when enable is high When enable is low o pin bi pad acts as an input pin and the stimulustable applies the values in the table for pin bi pad as input stimulus Expected value checking is ignored for pin bi pad when enable is low control ext stim timescale 1ns 100ps module test wire chipside bi pad enable out buf chipside bi pad buf out in bufifl bi pad chipside enable bufifl out in enable buf out chipside reg strobel initial strobel 0 always bi pad begin 8 strobel 1 1 strobel 0 1 end initial begin 5 stimulustable s1 table 10 chipside enable out strobel bi pad enable Gstrobel To CL 1 1 output cycle 0 1 0 0 output cycle K 30 1 1 input cycle 0 0 0 0 input cycle endtable endstimulustable end endmodule B 2 1 3 8Expected Value Error Expected value errors trigger a global register named ExpectedValueError This register is simultaneously set with specific information about the expected value violated The Expected ValueError variable can be accessed either Electronics Workbench Verilog HDL Extensions from the data file to cause immediate interaction with the simulation e g always GExpectedValu
455. tronics Workbench Appendix B 3 Silos Ill Menus B 3 1 Menus Overview B 3 1 1 Menu Bar The SILOS Simulation Environment SSE provides the following top level menus File menu Edit menu e View menu Project menu e Explorer menu Reports menu Debug menu Options menu Window menu Help menu The pull down menus for the SSE change depending on which window has the focus the window that is in focus has its title bar highlighted For example when the Data Analyzer window has the focus the available top level menus are different from the SILOS III window Many of the menu selections can be accessed by clicking on buttons on the toolbar To see a label for each button on the toolbar place the mouse cursor over the button for a few seconds and an explanatory text message will appear Multisim User Guide B 3 1 snuelA 111 SOS Silos II Menus Silos III Menus B 3 1 2 Pop up Menus Many of the windows in SILOS III have a pop up menu that can be accessed by right clicking for more information seePop up Menus For example if you left click in the left hand side of the Explorer window you will see the pop up menu for the Explorer B 3 1 3Screen Conventions The following conventions should be noted for the screens Clicking OK will close the screen and any active options or specifications will be used Clicking Cancel will close the screen and not affect any options or specifications Clickin
456. u to trace the cause of problems directly in a Verilog HDL source code window To invoke the pop up menu right click on any part of the source window B 3 44 Electronics Workbench Appendix C Sources Components C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 GOUNA A EMI C 1 C 1 1 About Grounding lisse C 1 C 1 2 The Ground Component ooococcccc es C 1 Digital Ground ociosas iaa a toe urs vade ruri C 2 DC Voltage Source Battery liliis ele C 2 C 3 1 Battery Background Information llis C 2 C 3 2 Battery COMpoONeMt ooccccccco rn C 3 VCC Voltage Source niii eser C 3 DG Current Source ea eb eee a Seed ER Ese Kn C 3 AC Voltage Source i 4 2 0 Selec yeas deen eee ead dd epi pe eri C 3 AC Current Source 0 0 el hh C 4 COCK SOUE ena ia rn hea are aren wae be C EORR e a ee wey C 4 Amplitude Modulation AM Source 0 0600 eee eee C 4 C 9 1 Characteristic Equation 0 000 C 4 EMESQUICO s etiara ute et teca bt a Pret Pein P e Shaklee fuia E C 5 C 10 1FM Voltage Source 2 222 sense s C 5 C 10 2Characteristic Equation liliis nes C 5 C TO SEM C rtelh E SOURCE e ann d REP rato a ebat i Rae ebd e ua C 6 C 10 4Characteristic Equation llle C 6 ESIKCSOUICO x Seba ND GRE NC etr ete C 6 Voltage Controlled Voltage Source liliis C 7 Current Controlled Voltage Source esee C 7 Voltage Controlled
457. u want to find Then click Ok and the Explorer window will highlight the instance you selected To invoke this menu selection right click on any part of the left hand side of the Explorer window to open the pop up menu B 3 12 1 6Properties Located in the pop up menu in the left hand Tree side of the Explorer window The Proper ties command opens the Module Properties screen The Module Properties screen enables you to specify which module instances you want to save the simulation data for during simu lation See Keeping Module Instance Simulation Variable Values for a simpler method of sav ing instances in the hierarchy If the Save simulation data for this entry is selected then SILOS III saves the simulation data for the following items during simulation All local variables for the module instance All port variables for the module instance even if the ports connect to module instances that are not saved below it in the hierarchy e Any instance below it in the hierarchy of the design unless the instance below it is specif ically not saved If the Save simulation data for this entry is not selected then SILOS III does not save the simulation data for following items during simulation All local variables for the module instance not selected e The simulation data for any instance below it in the hierarchy of the design Before the Save simulation data for this entry specifications can take effect t
458. uction in the collector area is limited by the maximum tolerable voltage at the collector terminal To achieve maximum power output the emitter periphery area should be as large as possible Because of these limitations a special structure for bipolar transistors is used This structure is commonly referred to as an interdigi tal bipolar transistor RF MOS STDN a1 RF FETS have a different type of carrier than bipolar transistors Only the F1007 majority carriers selected for FET should have better transport properties such as high mobility velocity diffusion coefficient For this reason RF FETs are fabricated on n type materials since electrons have better properties The two most important parameters are the gate length and width A reduction in the gate length will improve the gain noise figure and frequency of operation Increasing the gate width will increase the RF power capability That is why typical power FETs have multiple gate fingers interconnected via air bridges with a total width of about 400 to 1000 um The model parameters for RF FET transistors can be obtained using measured data for DC and RF S parameters The equivalent circuit model should have almost identical DC and RF S parameters Electronics Workbench Tunnel Diode M 5 Tunnel Diode D1 A tunnel diode is a heavily doped diode that is used in high frequency communi P H cations circuits for applications such as amplifiers oscillators modula
459. ulse Current Source e put is measured in current OA 1A This component is the same as the Pulse Voltage Source except that the out C 22 Polynomial Source aa This source is a voltage controlled voltage source defined by a polynomial transfer function It is a specific case of the more general nonlinear dependent source Use it for analog behavioral modeling In Multisim the polynomial source has three controlling voltage inputs namely V V2 and V4 C 22 1 Output Voltage Characteristic Equation The output voltage is given by Vour A B V1 C Vo4 D V3 E V F Vi V2 G V i Va H V 1 V 2 xVs J V gt Ke Vi VoxrV 3 where A constant B coefficient of V C coefficient of Vo D coefficient of V3 E coefficient of V42 F coefficient of V Vo G coefficient of V Vz H coefficient of V2 I coefficient of Va Vz C 20 Electronics Workbench Exponential Source J coefficient of Va K coefficient of V V Vz C 23 Exponential Source The exponential sources are configurable sources whose output can be set to produce an expo nential signal The following parameters can be modified Initial Value e Pulsed Value Rise Delay time Rise Time Fall Delay time Fall Time Label Display Value Analysis Setup Fault Initial Value p v 3 Pulsed Value hn lv 3 Iv Rise Delay Time fo sc 3 IV Rise Time Constant i msec Fall Delay Time ls msec 3 e Constant 1 mse
460. uoIsua1X3 JAH Bojan Verilog HDL Extensions Extensions B 2 74 Mam Description 74BCT540 Octal buffers line drivers 74BCT541 Octal buffers line drivers 74BCT543 Octal registered transceiv ers 74BCT534 Octal D type FFs 74BCT620A Octal bus transceivers 74BCT623 Octal bus transceivers 74BCT640 Octal bus transceivers 74BCT652 Octal bus transceivers 74BCT760 Octal buffers line drivers 74BCT2240 Octal buffers line drivers 74BCT2241 Octal buffers 74BCT2244 Octal buffers 74BCT2827A 10 bit bus memory drivers 74BCT2828A 10 bit bus memory drivers 74BCT29827A 10 bit buffers 74BCT29828A 10 bit buffers 74BCT29833 8 to 9bit Parity Transceiver 74BCT29834 8 to 9bit Parity Transceiver 74BCT29843 9bit Bus Interface Xsciever 74BCT29844 9bit Bus Interface Xsciever 74BCT29845 8bit Bus Interface DLatches 74BCT29846 8bit Bus Interface DLatches 74BCT29853 8 to 9bit Parity Transceiver 74BCT29854 8 to 9bit Parity Transceiver 74BCT29861A 10bit bus transceivers Electronics Workbench Verilog Libraries Name Description 74BCT29862A 10bit bus transceivers 74BCT29863A 9bit bus transceivers 74BCT29864A 9bit bus transceivers The following are from Preliminary Data sheets There is a total of 10 parts in 74BCT series which are not released products in the TI 1989 data book Name Description 74BCT544 Octal registered transceiv
461. urs when the input frequency is doubled to 200Hz Function Generator TENIS AG Li eoo E He E Dutycycle so f x ET E e 3 2 Hy BE Offset o Common e s s s gt 3 Z Oscilloscope Ground Time base Trigger Edge 7 e Xposition 0 00 Level fet vor BHA am Auto 5318 ess Channel amp Channel B Y position 0 00 E Ypesiion o oo Bel j oc s Belo oc L 11 1 Voltage Slew Rate Block Parameters and Defaults Symbol Parameter Name Default Unit RSMax Maximum rising slope value 1 GV s FSMax Maximum falling slope value 1 GV s L 12 Three Way Voltage Summer m This component is a math functional block that receives up to three voltage B inputs and delivers an output equal to their arithmetic sum Gain for all three ov inputs as well as the summed output may be set to match any three input sum B ming application In the example shown below all gains are set to unity Multisim User Guide L 21 04 U0D Controls Controls Components L 22 The summer may be used to illustrate the result of adding harmonically related sine wave components which make up a complex waveform the first three terms in the Fourier expres sion defining the waveform In the example a fundamental frequency of 60 Hz and the third and fifth harmonics in phase may be progressively added to illustrate the bas
462. used in these equations are defined in Diac Parameters and Defaults E 8 2 Time Domain and AC Small Signal Models Each of the Shockley diodes is simulated with the mixed electrical behavioral model described in the DC model above Multisim User Guide E 15 sepolg Diodes Diodes Components E 8 3 DIAC Parameters and Defaults Symbol Parameter Name Default Unit IS Saturation current 1e 06 A Vs Switching voltage 100 V Vtm Peak on state voltage 1 5 V Itm Forward current at which Vtm is measured 1 A Tq Turn off time 1e 06 s Ih Holding current 0 02 A CJO Zero bias junction capacitance 1e 12 F E 9 TRIAC A triac is a three terminal five layer switch capable of conducting current in D10 both directions The triac model consists of two SCRs each of which is mod ya 2N5444 eled as described earlier in this chapter The triac remains off restricting cur rent in both directions until the voltage across the triac exceeds the breakover voltage or until a positive pulse of current is applied to the gate terminal E 9 1 Model The simulation is a combined electrical behavioral model The status of the triac either on or off is treated as a logical variable The resistance R is a function of the triac status E drm When the triac is off the resistance R is set high to act as a current block When the triac is on R is low e 06 The triac is switched on in either direction if Vd
463. uts then waits for some Load lt 1 amount of time so we can Init 00001111 observe the results during Test 11110000 simulation Electronics Workbench Conclusion A 3 A 4 A 4 1 wait for 100 ns Load lt 0 walt for 600 ns end process end behavior Conclusion In this section the most important concepts and features of VHDL were explored We hope this introduction was a useful refresher for experienced VHDL users and a good introduction to the language for the novice VHDL is a rich and powerful language however and there is much more to learn before you become a master user To continue your learning it is strongly recommended that you acquire at least one textbook on VHDL and also obtain a copy of the IEEE 1076 VHDL Language Reference Manual There are also many good qual ity VHDL training courses and multimedia training products available Contact Electronics Workbench or visit their Web page at www interactiv com for more information You will also find it useful to study copy and modify existing VHDL design examples A 4 Examples Gallery on page A 23 includes listings and descriptions of sample designs and additional examples are provided on your Multisim s VHDL installation CD ROM Examples Gallery The examples in this section are intended to help you get started with VHDL Each example demonstrates one or more important features of the language and demonstrates c
464. value Values are set in the same way as for the potentiometer D 10 3 Virtual Variable Inductor This component performs the same functions as a variable inductor but has a user settable value D 16 Electronics Workbench Potentiometer D 11 Potentiometer R4 Key a Por D 11 1 The Component This component acts much like a regular resistor except that you can with a single keystroke adjust its setting In the Value tab of the Circuit Component Properties dialog box you set the potentiometer s resistance initial setting as a percentage and increment as a percentage You also identify the key A to Z that you will use to control the setting To decrease the potentiometer s setting press the identified key gt To increase the setting press and hold SHIFT and press the identified key For example say the potentiometer is set to 45 the increment is 596 and the key is R You press R and the setting drops to 40 You press R again and it drops to 35 You press SHIFT and R and the setting rises to 40 D 11 2 Characteristic Equation and Model The potentiometer is simulated using two resistors R and R whose values are computed using the potentiometer s initial settings _ Setting 100 Resistance where R r Ro Resistance r Multisim User Guide oiseg Basic Basic Components D 11 3 Virtual Potentiometer D 12 D 13 D 14 D 14 1 This component performs
465. vert a std ulogic vector to an unsigned integer function to unsigned a std ulogic vector return integer is alias av std ulogic vector 1 to a length is a variable ret d integer begin d 1 ret 07 for i in a length downto 1 loop if av i 1 then ret ret d end 1f d d 2 end loop return ret end to unsigned Convert an integer to a std ulogic vector function to vector size integer num integer return std ulogic vector is variable ret std ulogic vector 1 to size variable a integer begin a num for i in size downto 1 loop if a mod 2 1 then ret i s 1 A 24 Electronics Workbench Examples Gallery else ret i 0 end if a a 2 end loop return ret end to_vector end conversions COUNT16 4 bit counter Library ieee Use ieee std logic 1164 all use work conversions all Entity COUNT16 Is Port Clk Rst Load in std ulogic Data in std ulogic vector 3 downto 0 Count out std ulogic vector 3 downto 0 Jg End COUNT16 Architecture COUNT16 A of COUNT16 Is Begin process Rst Clk Note the use of a variable to localize the feedback behavior of the counter registers This is good general design practice in VHDL as it helps to cut down on unwanted side effects In this example the use of a variable of type integer also localizes the use of a numeric data type to within the process itself This makes it easier to modify the design as nece
466. volts fc carrier frequency in Hz m modulation index fm modulation frequency in Hz Multisim User Guide C 5 seoinos Sources Sources Components C 10 3 FM Current Source This component is the same as the the FM voltage source except that M the output is measured in current 1A 1000Hz 100Hz l C 10 4 Characteristic Equation C 11 C 6 The behavior of the FM current source is described by the same equation as in C 10 2 with Vout replaced by Iout FSK Source This source is used for keying a transmitter for telegraph or teletype va communications by shifting the carrier frequency over a range of a lt gt 120v 10Hz 5Hz few hundred hertz The frequency shift key FSK modulated source generates the mark transmission frequency f1 when a binary 1 is sensed at the input and the space transmission frequency f2 when a 0 is sensed FSK is used in digital communications systems such as in low speed modems for example a Bell 202 type modem 1200 baud or less In this system a digital high level is referred to as a MARK and is reproduced as a frequency of 1200 Hz A digital low level is referred to as a SPACE and is represented by a frequency of 2200 Hz In the example shown below the frequency shift keying signal is a 5v TTL square wave When the keying input is 5V a MARK frequency of 1200 Hz is output When keying voltage is OV a SPACE frequency of 2200 Hz is output Electronics Workbench
467. will conduct current easily in only one direction they are used extensively as power rectifiers converting AC signals to pulsating DC signals for both power applications and radio receivers Diodes behave as voltage controlled switches and have replaced mechanical switches and relays in many applications requiring remote signal switching Even indicator lamps are now replaced with diodes LEDs that emit light in a variety of col ors when conducting A special form of diode called a Zener diode is useful for voltage regulation Multisim User Guide E 1 sopo q Diodes Diodes Components E 1 2 DC Model The DC characteristic of a real diode in Multisim is divided into the forward and reverse char acteristics DC forward characteristic Vp geile 1 Bv DC reverse characteristic Vp for Vp 2 5nV n ler V s for 5nV lt V lt 0 Ls V G min IBV where for BV V lt 5nV for V BV for V BV T current through the diode in amperes voltage across the diode in volts thermal voltage 0 0258 volts at room temperature 27 C breakdown voltage I is equivalent to the reverse saturation current of a diode In a real diode J doubles for every 10 degree rise in temperature Other symbols used in these equations are defined in Diode Parameters and Defaults E 2 Electronics Workbench Diode E 1 3 Time Domain Model This model de
468. wn logical value z high impedance of tristate gate The reg variables are initialized to x at the start of the simulation Any wire variable not connected to something has the x value You may specify the size of a register or wire in the declaration For example the declarations reg 0 7 A B wire 0 3 Dataout reg 7 0 C specify registers A and B to be 8 bit wide with the most significant bit the zeroth bit whereas the most significant bit of register C is bit seven The wire Dataout is 4 bits wide The bits in a register or wire can be referenced by the notation lt start bit gt lt end bit gt For example in the second procedural assignment statement initial begin intl A 8 b01011010 B A 0 3 A 4 7 4 b0000 end Multisim User Guide B 1 9 Jewud Boje Verilog Primer Verilog HDL Primer B 1 10 B is set to the first four bits of A bitwise or ed with the last four bits of A and then concate nated with 0000 B now holds a value of 11110000 The brackets means the bits of the two or more arguments separated by commas are concatenated together An argument may be replicated by specifying a repetition number of the form repetition number expl exp2 expn Here are some examples C 2 4 b1011 C assigned the bit vector 8 b10111011 C 4 A 4 Al4 7 first 4 bits are sign extension The range referencing in an expression must have constant expression indices However a sing
469. x and accurate model with a majority of the external control pins modeled G 3 3 Comparator Parameters and Defaults Symbol Parameter name Default Unit Voffset Input voltage offset 0 7 V A Gain 200000 VN Voh Output high level 3 5 V Vol Output low level 0 23 V Trr Low to high response time 1e 07 S Trf High to low response time 1 5e 07 S Tr Rise time 1e 07 S Tf Fall time 6e 08 S Icc Positive supply current 0 0051 A Icc Negative supply current 0 0041 A Imax Maximum positive supply current 0 006 A Imax Maximum negative supply current 0 005 A Electronics Workbench Wide Band Amplifier G 4 Wide Band Amplifier u1 AD624AD G 4 1 The Component The typical opamp such as a general purpose 741 type opamp has been internally compen sated for a unity gain bandwidth of about MHz Wide band amplifiers are opamps that have been designed with a unity gain bandwidth of greater than 10 MHz and typically in the 100 MHz range These devices are used for application such as video amplifiers G 4 2 Wide Band Amplifier Simulation models The same levels of simulation model as the opamps are provided with several levels of simu lation models of increasing complexity and accuracy The following model levels are used to distinguish between these models e LI this is the simplest model with the opamp modeled as a gain block with a differential input and a single ended output e I2 this
470. xponential SOUFCe rox rn a ER ERR TEES C 21 C 23 1Exponential Voltage Source 00 0 eee C 22 C 23 2Exponential Current Source oooooccccconcc rennen nn C 22 Nonlinear Dependent SourcCe oococcoccccccc ess C 22 Controlled One Shot si e penre pae gy eda Heed Pot ead PRE o e C 23 Electronics Workbench Appendix C Sources Components C 1 Ground l C 1 1 About Grounding A voltage measurement is always referenced to some point since a voltage is actually a potential difference between two points in a circuit The concept of ground is a way of defining a point common to all voltages It represents 0 volts All voltage levels around the circuit are positive or negative when compared to ground In power systems the planet Earth itself is used for this reference point most home power cir cuits are ultimately grounded to the Earth s surface for lightning protection This is how the expression earthing or grounding a circuit originated Most modern power supplies have floating positive and negative outputs and either output point can be defined as ground These types of supplies can be used as positive with respect to ground or negative power supplies In floating power supply circuits the positive output is often used as the voltage reference for all parts of the circuit Note Multisim supports a multipoint grounding system Each ground connected is made directly to the ground plane
471. your circuit It is unlikely however that your synthesis tool will be capable of creating precisely the same behavior in actual circuitry as you have defined in the language Synthesis tools today ignore detailed timing specifications leaving the actual timing results to the target device technology If you are familiar with event driven software programming writing behavior level VHDL will not seem like anything new Just like with a programming language you will be writing one or more small programs that operate sequentially and communicate with one another through their interfaces The only difference between behavior level VHDL and a software programming language is the underlying execution platform in the case of software it is some operating system running on a CPU in the case of VHDL it is the simulator Dataflow In the dataflow level of abstraction you describe your circuit in terms of how data moves through the system At the heart of most digital systems today are registers so in the data flow level of abstraction you describe how information is passed between registers in the circuit You will probably describe the combinational logic portion of your circuit at a rel atively high level and let a synthesis tool figure out the detailed implementation in logic gates but you will likely be quite specific about the placement and operation of registers in the complete circuit Structure The third level of abstraction stru

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