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Renesas R5F1026AASP#V0 datasheet: pdf

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1. TI00 TOOO TI01 TOO1 TI02 TOO2 TI03 TOO3 rns KD ie RxDO n 3 joci TxDO Code flash 16 KB gt Port 13 P aco Data flash 2 KN H SIO0 S000 Buzzer clock PCLBUZO SCKO1 output control gt S001 Key return 1I m ee eters SCLOO Ne SDAOO DMA RL78 CPU core Interrupt control INTPO to INTP3 scLo1 TY 4ch SDA01 Window watchdog timer TOOL TOOL TOOLO TxD RxD On chip debugger Clock Generator adjustment 1 to 20 MHz k ANI2 ANI3 ANI16 to ANI22 Multiplier amp X 10 bit fr onene ANIO AVacre divider X1 X2 EXCLK ANIV AVeerm multiply accumulator Power on Low speed reset low on chip on chip SCLAO voltage oscillator oscillator SDAAO ICAO detector 15 kHz 1 to 24 MHz Voo Vss Note Provided for the R5F102 products R01DS0193EJ0100 Rev 1 00 Page 11 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 1 OUTLINE 1 6 3 30 pin products TAU 8ch T100 TO00 T101 T001 roe Ae foan T103 TOO3 PORT 1 K8_ gt P10 to P17 em omes T105 T005 A e foen mo6 TO06 f e j 1107 TOO7 gt PORT5 lt 2 gt P50 P51 CODEFLASH 16KB RxDO TxDO re P120 2_ P121 P122 RxD1 TxD1 PORT 13 P137 s00 7 m jr SCK11 911 D BUZZER CLOCK 3011 OUTPUT CONTROL 2_ gt POLBUZO PCLBUZ1 scLoo SDAOO INTERRUPT soit oe C6 INTPO to INTPS SDA11 WINDOW WATCHDOG TIMER Clock Generator TxD2 Reset Generator 12 bit INTERVAL SK20
2. Notes 1 2 Zero scale error Notes 1 2 Full scale error Note 1 Integral linearity error Note 1 Differential linearity error Analog input voltage Internal reference voltage is selected 2 4 V lt VDD lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 4 When AVrer Internal reference voltage ADREFP1 1 ADREFPO 0 AVrer AVrerm ADREFM 1 target ANI pin ANIO ANI2 ANI3 ANI16 to ANI22 Ta 40 to 85 C 2 4 V lt Von lt 5 5 V Vss 0 V Reference voltage Vacr Reference voltage AVrerm 0 V HS high speed main mode Parameter Conditions Resolution Conversion time 8 bit resolution Zero scale error AVREFM 0 V 2 4 V lt VDD lt 5 5 V Note 1 Integral linearity error Note 1 Differential linearity error Reference voltage Analog input voltage Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value RO1DS0193EJ0100 Rev 1 00 Page 53 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 6 2 Temperature sensor internal reference voltage characteristics Ta 40 to 85 C 2 4 V lt Von lt 5 5 V Vss 0 V HS high speed main mode Param
3. _ 11 O P16 TI01 TOO1 INTP5 RxDO Voo O 12 O P17 T102 TOO2 TxD0 P60 SCLAO O O P51 INTP2 SO11 P61 SDAAO O O Ps50 INTP1 SI11 SDA11 O P30 INTP3 SCK11 SCL11 Note Provided in the R5F102 products Caution Connect the REGC pin to Vss via capacitor 0 47 to 1 WF Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR RO1DS0193EJ0100 Rev 1 00 Page 8 of 61 Dec 10 2012 Eoin ee RENESAS RL78 G12 CHAPTER 1 OUTLINE 1 5 Pin Identification ANIO to ANI3 ANI16 to ANI22 AVREFM AVREFP EXCLK INTPO to INTP5 KRPO to KR9 POO to POS P10 to P17 P20 to P23 P30 to P31 P40 to P42 P50 P51 P60 P61 P120 to P122 P125 P137 P147 PCLBUZO PCLBUZ1 Analog input Analog Reference Voltage Minus Analog reference voltage plus External Clock Input Main System Clock Interrupt Request From Peripheral Key Return Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 12 Port 13 Port 14 Programmable Clock Output Buzzer Output REGC RESET RxDO to RxD2 SCKOO SCK01 SCK11 SCK20 SCLOO SCLO1 SCL11 SCL20 SCLAO SDAOO SDA01 SDA11 SDA20 SDAAO S100 S101 SI11 S120 000 S001 S011 S020 TI00 to T107 TOOO to TO07 TOOLO TOOLRxD TOOLTxD TxDO to TxD2 Regulator Capacitance Reset Receive Data S
4. 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 5 Cis the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Sip pin and the normal output mode for the SOp and SCKp pins by using port input mode registers 0 1 PIMO PIM1 and port output mode registers 0 1 POMO POM1 Remarks 1 p CSI number p 00 01 11 20 m Unito number m 0 1 n Channel number n 0 1 3 1 3 is for the R5F102 products 2 fmck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number n 0 1 3 1 3 is for the R5F102 products RO1DS0193EJ0100 Rev 1 00 Page 31 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 4 During communication at same potential CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions SCKp cycle time Normal operation 4 0 V lt Voo lt 5 5 V 20 MHz lt fuck 8 fmck fuck lt 20 MHz 6 fuck 2 7 V lt Voo lt 4 0 V 16 MHz lt fuck 8 fuck fuck lt 16 MHz 6 fuck 1 8 V lt Voo lt 2 7 V 16
5. 1 and CKPmn 0 tkcy2 tkL2 tkH2 SCKp SOp Output data RO1DS0193EJ0100 Rev 1 00 Page 47 of 61 Dec 10 2012 Eoin ee RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 10 Communication at different potential 1 8 V 2 5 V 3 V simplified C mode Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions SCLr clock frequency fscL 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V 400 kHz Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 400 kHz Co 100 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 300 kHz Co 100 pF Rb 5 5 KQ Hold time when SCLr L tLow 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 1150 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 1150 ns Co 100 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 1550 ns Co 100 pF Rb 5 5 KQ Hold time when SCLr H tHiGH 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V 675 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V 600 ns Co 100 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 610 ns Co 100 pF Rb 5 5 KQ Data setup time reception tsupat 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 1 fmok 190 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V
6. 22 bps Cb x Rb x In 1 Vb yx 3 1 2 2 Transfer rate x 2 Co x Ro x In 1 4 Baud rate error theoretical value 7 x 100 Transfer rate x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 2 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer R01DS0193EJ0100 Rev 1 00 Page 36 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 3 The smaller maximum transfer rate derived by using fmck 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt Voo lt 4 0 V and 2 3 V lt Vo lt 2 7 V 1 Maximum transfer rate bps Cb x Rb x In 1 lt 0 x3 1 2 0 Transfer rate x 2 ees Rex In 1 V Baud rate error theoretical value n Mn oa 00 Trantor rate x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 4 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer 5 The smaller maximum transfer rate derived by using fmck 6 or
7. 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V __ sew set ets Tn Tove Te Tot Instruction cycle minimum Tey HS High speed main mode lo7v lt Vvoo lt ssv ooe7 1 us instruction execution time l24v lt Vo lt 27v 0085 1 us Tatrama reysvesssy ove 1 ws External main system clock 2 7 V lt Voo lt 5 5 V EE frequency 1 8 V lt Voo lt 2 7 V a MH N External main system clock tex text 2 7 V lt Voo lt 5 5 V input high level width low 1 8 V lt Voo lt 2 7 V level width TIOO to TIO7 input high level tmn tn Ea 10 width low level width TOOO to TOO7 output 4 40V lt Vo lt 55V S V lt Vo lt 5 5 V frequency 2 7 V lt Voo lt 4 0 V 18V lt Vo0 lt 2 7 al PCLBUZO or PCLBUZ1 4 0 V lt Voo lt 5 5 V output frequency 27V lt Vo lt 4 0V 1 8 V lt Voo lt 2 7 V INTPO to INTP5 input high tintH NTL level width low level width KPO to KR9 input available width o a O O O O O Remark fmck Timer array unit operation clock frequency Operation clock to be set by the CKSOn bit of timer mode register On TMROn n Channel number n 0 to 7 20 0 t t e es e 8 EN G a RO1DS0193EJ0100 Rev 1 00 Page 27 of 61 Dec 10 2012 si RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS AC Timing Test Point Vin Vin Test points Vit P a Vit External main system clock timing 0 8Vpp MIN 0 2Vpp
8. Voo 5 0 V fux 20 MHZ Voo 3 0 V fux 10 MHz Voo 5 0 V fux 10 MHz2 Voo 3 0 V LS Low speed fux 8 MHz main mode Voo 3 0 V fux 8 MHz Voo 2 0 V Versov _ W fas e wzo __ a fso Voo 5 0 V Voo 5 0 V Voo 3 0 V Voo 3 0 V Voo 2 0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection CHAPTER 2 ELECTRICAL SPECIFICATIONS 1 2 Pas ml mA mA Notes 1 Total current flowing into Voo including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current except for background operation BGO However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors 2 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vpop 2 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vpop 1 8 V to 5 5 V 1 MHz to 8 MHz 3 When high speed system clock is stopped 4 When high speed on chip osicllator clock is stopped Remarks 1 fmx High speed system clock frequency X1 clock os
9. malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or
10. tENESAS Datasheet RL78 G12 RENESAS MCU RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 True Low Power Platform as low as 63 UA MHz 1 8V to 5 5V operation 2 to 16 Kbyte Flash 31 DMIPS at 24MHz for General Purpose Applications 1 OUTLINE 1 1 Features Ultra Low Power Technology e 1 8V to 5 5V operation from a single supply e Stop RAM retained 0 23pA LVD enabled 0 31uA e Snooze 0 7mA UART 1 20mA ADC e Operating 63 pA MHz 16 bit RL78 CPU Core e Delivers 31 DMIPS at maximum operating frequency of 24MHz e Instruction Execution 86 of instructions can be executed in 1 to 2 clock cycles e CISC Architecture Harvard with 3 stage pipeline e Multiply Signed amp Unsigned 16 x 16 to 32 bit result in 1 clock cycle e MAC 16 x 16 to 32 bit result in 2 clock cycles e 16 bit barrel shifter for shift amp rotate in 1 clock cycle e 1 wire on chip debug function Main Flash Memory e Density 2 KB to 16 KB e Block size 1KB e On chip single voltage flash memory with protection from block erase writing Data Flash Memory e Data Flash with background operation e Data flash size 2 KB size options e Erase Cycles 1 Million typ e Erase programming voltage 1 8 V to 5 5 V RAM e 256 B to 1 5 KB size options e Supports operands or instructions e Back up retention in all modes High speed Oscillator Oscillator e 24MHz with 1 accuracy over voltage 1 8 V to 5 5 V and temperature 40 C to
11. z Q o l QY N pa Q is 3 U N is N 2D a l Y Qa Ke exposed die pad P22 ANI2 O P21 ANI1 AVreem O P20 ANIO AVrerp O P42 ANI21 SCK01 SCL01 T103 TO03 O O Oo O P61 KR5 SDAA00 RxDO O P60 KR4 SCLAO TxDO O P03 KR9 O P02 KR8 SCKO1 SCLO1 O P01 KR7 SO01 SDA01 O P00 KR6 SI01 N P41 ANI22 SO01N SDA01 T102 TOO2 INTP1 P40 KRO TOOLO OOO0O00 o 2 8 a o gt BERA AZAaE WwREZ e RZze go SS S a Aam i No is SE a ES z 3x un L x 2 oe a ga Na lt lt N N a Note Provided in the R5F102 products Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR RO1DS0193EJ0100 Rev 1 00 Page 7 of 61 Dec 10 2012 GETAN RENESAS RL78 G12 CHAPTER 1 OUTLINE 1 4 3 30 pin products e 30 pin plastic SSOP 7 62 mm 300 O O X Z P20 ANI0 AV P O 1 P01 ANI16 TO00 RxD1 O 2 O P22 ANI2 P00 ANI17 TI00 TxD1 O 3 O P23 ANI3 P120 ANI19 O 4 O P147 ANI18 P40 TOOLO O 5 O P10 SCK00 SCL00 T107 TO07 RESET O 6 O P11 900 RxD0 TOOLRxD SDA00 T106 TO06 P137 INTPO 7 O P12 S000 TxD0 TOOLTxD T105 TO05 P122 X2 EXCLK O 8 O P13 TxD2 S020 SDAAO T104 TO04 O P14 RxD2 S120 e SDA20 SCLAO T103 TOO3 R amp C O10 O P15 PCLBUZ1 SCK20 SCL20 TI02 TO02 Vs O
12. 11 RO1DS0193EJ0100 Rev 1 00 Page 29 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 During communication at same potential CSI00 master mode fmck 2 SCKOO internal clock output Ta 40 to 85 C 2 7 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions SCKO0 cycle time 2 7 V lt Voo lt 5 5 V 83 3 SCKOO0 high low level width 4 0 V lt Vio lt 5 5 V tkcy1 2 7 2 7V lt Vo0 lt 5 5V tkcy1 2 10 S100 setup time to SCKOOT 4 0 V lt Voo lt 5 5 V 23 2 7 V lt Voo lt 5 5 V 33 S100 hold time to SCKOOT 2 7 V lt Voo lt 5 5 V 10 Delay time from SCKO0J to SOOO output C 20 pF Notes 1 The value must also be 2 fcLk or more 2 When DAPOO 0 and CKPOO 0 or DAPOO 1 and CKPOO 1 The SIOO setup time becomes to SCKOO when DAPOO 0 and CKP00 1 or DAPOO 1 and CKPO0 0 3 When DAPOO 0 and CKPOO 0 or DAPOO 1 and CKP00O 1 The SIOO hold time becomes from SCKOO when DAPOO 0 and CKP00 1 or DAPOO 1 and CKPO0 0 4 When DAPOO 0 and CKPOO 0 or DAPOO 1 and CKPO00 1 The delay time to SOOO output becomes from SCKOOT when DAPOO 0 and CKPO0 1 or DAPOO 1 and CKPOO 0 5 Cis the load capacitance of the SCKOO and SOO output lines Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCKOO pins by using port inp
13. 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS User s device Simplified IC mode serial transfer timing during communication at different potential 1 fscL tLow THIGH SCLr SDAr RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 tHD DAT tsu DAT Page 49 of 61 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 5 2 Serial interface IICA Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions Standard Mode Fast Mode MIN MAX MIN MAX SCLAO clock frequency Fast mode fcix gt 3 5 MHz Normal mode fck gt 1 MHz Note 1 Setup time of restart condition tsu sTa Hold time tHD STA Hold time when SCLAO L tLow Hold time when SCLAO H tHiGH Data setup time reception tsu DAT Data hold time transmission tap pat Setup time of stop condition tsu sto Bus free time tBUF Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of tHp pat is during normal transfer and a wait state is inserted in the ACK acknowledge timing Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Normal mode Cb 400 pF Rb 2 7 kQ Fast mode Cb 320 pF Rb 1 1 KQ IICA serial tr
14. Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2012 Renesas Electronics Corporation All rights reserved Colophon 2 2
15. KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 1150 Cb 30 pF Rb 5 5 KQ SCKp high level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V tkcy1 2 75 Cb 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V tkcy1 2 170 Cb 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V tkcy1 2 458 Co 30 pF Rb 5 5 KQ SCKp low level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V tkcy1 2 12 C 30 pF Po 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V tkcy1 2 18 Cb 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V tkcy1 2 50 Cb 30 pF Rb 5 5 KQ Note The value must also be 4 fc k or more Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register 0 1 PIMO PIM1 and port output mode register 0 1 POMO POM1 Redirect to PO is not supported in 24 pin products Communication at different potential is not allowed in CSI01 CSI11 Remarks 1 Rb Q Communication line SCKp SOp pull up resistance Cb F Communication line SCKp SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 RO1DS0193EJ0100 Rev 1 00 Page 41 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHA
16. MAX EXCLK TI timing trit tH TIO0 to T107 Interrupt Request Input Timing INTPO to INTP5 Key Interrupt Input Timing I tkr gt KRO to KR9 trsL RESET RO1DS0193EJ0100 Rev 1 00 Page 28 of 61 Dec 10 2012 PEMAN RENESAS RESET input timing RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 5 Serial Communication Characteristics 2 5 1 Serial array unit 1 During communication at same potential UART mode dedicated baud rate generator output Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions Transfer rate Normal operation Theoretical value of the maximum transfer rate fck fuck 24 MHz SNOOZE mode UART mode connection diagram during communication at same potential RL78 G12 User s device UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 q UART number q 0 to 2 g PIM POM number g 0 1 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10
17. MHz lt fuck 8 fmck fuck lt 16 MHz 6 fuck SNOOZE mode SCKp high low level width 1 8 V lt Voo lt 5 5 V tkcy2 2 Slp setup time to SCKp7 2 7 V lt Vo lt 5 5 V 1 fmck 20 1 8 V lt Voo lt 2 7 V 1 fuck 30 Slp hold time from SCKpT 1 fuck 31 Delay time from SCKpJ to SOp C 30 pF 2 7 V lt Von lt 5 5V 2 fmck 44 Note 3 output 2 4 V lt Voo lt 2 7 V 2 fmck 75 1 8 V lt Voo lt 2 4 V 2 fuck 110 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp71 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 Cis the load capacitance of the SOp output lines Caution Select the normal input buffer for the Sip pin and the normal output mode for the SOp and SCKp pins by using port input mode registers 0 1 PIMO PIM1 and port output mode registers 0 1 POMO POM1 Remarks 1 p CSI number p 00 01 11 20 m Unit number m 0 1 n Channel number n 0 1 3 1 3 is for the R5F102 products 2 fmck Serial array unit operation clock
18. Peripheral Functions R5F102 R5F103 RL78 G12 20 24 pin 30 pin product 20 24 pin 30 pin product product product 2 channels 3 channels 1 channel Simplified 1 C 2 channels 3 channels None DMA function 2 channels None Safety function CRC operation None RO1DS0193EJ0100 Rev 1 00 Page 5 of 61 Dec 10 2012 si RENESAS RL78 G12 CHAPTER 1 OUTLINE 1 4 Pin Configuration Top View 1 4 1 20 pin products e 20 pin plastic SSOP 4 4 x 6 5 P20 ANIO AVreFP P42 ANI21 SCK01 SCLO1 T103 TO03 O P41 ANI22 SO01N SDA01N T102 TOO2 INTP1 O P40 KRO TOOLO O P125 KR1 SI01 RESET O P137 INTPO O P122 KR2 X2 EXCLK T102 INTP2 O P121 KR3 X1 T103 INTP3 O Vss O Voo O O P21 ANI1 AVree O P10 ANI16 PCLBUZ0 SCKO00 SCLOON O P11 ANI17 S100 RxD0 SDA00 TOOLRxD O P12 ANI18 SO00 TxD0 TOOLTxD O P13 ANI19 T100 TOOO INTP2 O P14 ANI20 T101 TOO1 INTP3 O P61 KR5 SDAA0 RxD0 O P60 KR4 SCLAO TxD0 Note Provided in the R5F102 products Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR RO1DS0193EJ0100 Rev 1 00 Page 6 of 61 Dec 10 2012 Eoin ee RENESAS RL78 G12 CHAPTER 1 OUTLINE 1 4 2 24 pin products e 24 pin plastic WQFN 4 x 4 17 S100 RxD0 SDA00 TOOLRxD 18 SO00 TxD0 TOOLTxD 19 T100 TOOO INTP2 20 T101 TOO1 INTP3 g 6
19. TIMER 920 s020 sc120 SDA20 Ce ANI2 ANI ANI16 to ANI19 TOOLO TxD RD Mo VS ANIO AVeere __ ANI1 AVreru ON CHIPDEBUG KC gt ae BCD ADJUSTMENT a SCLAD SDAAO IICA0 KS Note Provided for the R5F102 products Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR RO1DS0193EJ0100 Rev 1 00 Page 12 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 1 OUTLINE 1 7 Outline of Functions This outline describes the function at the time when Peripheral I O redirection register PIOR is set to OOH except timer output of R5F102Ax 1 2 R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax Note 1 Code flash memory 2 to 16 KB 4to 16 KB 256 B to 1 5 KB 512 B to 1 5 KB 512 B to 2KB Address space 1 MB Main High speed system clock X1 X2 crystal ceramic oscillation external main system clock input EXCLK system 1 to 20 MHz Vm 2 7 to 5 5 V 1 to 8 MHz Voo 1 8 to 5 5 V clock High speed on chip HS High speed main mode 1 to 24 MHz Voo 2 7 to 5 5 V 1 to 16 MHz Von 2 4 to 5 5 V oscillator clock LS Low speed main mode 1 to 8 MHz Voo 1 8 to 5 5 V Minimum instruction execution time Instruction set e Data transfer 8 16 bits e Adder and subtractor logical operation 8 16 bits e Multiplication 8 bits x 8 bits e Rotate barrel shift and bit manipulation set reset test and Boolean operation etc 6 V toler
20. current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 3 24 pin products only Caution P10 to P12 P41 for 20 pin products P01 P10 to P12 P41 for 24 pin products and P00 P10 to P15 P17 P50 for 30 pin products do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0100 Rev 1 00 Page 18 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V 2 4 Output current low Per pin 20 24 pin products 20 0 mA POO to PO3 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 SS E E A Total of all 20 24 pin products f40v lt Voo lt 55v 600 ma pins P40 to P42 SNEU AIN E a POO P01 P40 P120 20 24 pin products 4 0 V lt Voo lt 5 5 V f40v lt Voo lt 5sv 800 ma Poot Posie per 27V s Vw lt 4ov jervewecsov ff are ma P10 to P14 P60 P61 1 8 V lt Voo lt 2 7 V 5 4 30 pin products P10 to P17 P30 P31 P50 P51 P60 au ae P147 All All the terminais o terminals Perpin pin P20 to P23 Total of all pins 2 Notes 1 Value of current at which the device operation is guaranteed even if the current fl
21. e T e bocce y wt lt 1 gt The low level is input to the TOOLO pin lt 2 gt The external reset ends POR and LVD reset must end before the pin reset ends lt 3 gt The TOOLO pin is set to the high level lt 4 gt Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark tsuinit The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end tsu How long from when the TOOLO pin is placed at the low level until an external reset ends tHo How long to keep the TOOLO pin at the low level from when the external and internal resets end except soft processing time RO1DS0193EJ0100 Rev 1 00 Page 58 of 61 Dec 10 2012 Pau RENESAS RL78 G12 CHAPTER 3 PACKAGE DRAWINGS 3 PACKAGE DRAWINGS 3 1 20 pin products R5F1026AASP R5F10269ASP R5F10268ASP R5F10267ASP R5F10266ASP R5F1036AASP R5F10369ASP R5F10368ASP R5F10367ASP R5F10366ASP R5F1026ADSP R5F10269DSP R5F10268DSP R5F10267DSP R5F10266DSP R5F1036ADSP R5F10369DSP R5F10368DSP R5F10367DSP R5F10366DSP JEITA Package Code RENESAS Code MASS TYP g P LSSOP20 4 4x6 5 0 65 PLSP0020JB A P20MA 65 NAA 1 detail of lead end M ph be L a HE UNIT mm _ITEM __DIMENSIONS_ D 6 50 0 10 E 4 40 0 10 NOTE HE 6 40 0 20 1 Dimensions lt 1
22. main mode Vo 3 0 V Resonator connection fux 8 MH2 Square wave input Voo 2 0 V Voo 5 0 V Resonator connection o Jao 2 7 Resonator connection Notes 1 Total current flowing into Vop including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current except for background operation BGO However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors 2 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vpop 2 7 V to 5 5 V 1 MHz to 24 MHz Vo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vpop 1 8 V to 5 5 V 1 MHz to 8 MHz 3 When high speed system clock is stopped 4 When high speed on chip osicllator clock is stopped Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fik high speed on chip oscillator clock frequency 3 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0100 Rev 1 00 Page 24 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 2 2 Supply HALT HS High speed fin 24 MHz lvoo 5 0v so 1280 current mode main mode Hvoo 30v
23. the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 1 Maximum transfer rate j5 bps Cb x Rb x In 1 V x3 b 1 1 5 Transfer rate x2 CPx Rb x In 1 7 Baud rate error theoretical value n ee ee a ees 100 CTransforrate x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 6 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg In 20 or 24 pin products redirect to P6 is not supported Remarks 1 Rb Q Communication line TxDq pull up resistance Cb F Communication line TxDq load capacitance Vo V Communication line voltage 2 q UART number q 0 to 2 g PIM POM number g 0 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 11 RO1DS0193EJ0100 Rev 1 00 Page 37 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12
24. 1 and CKPOO0 1 3 When DAPOO 0 and CKPOO 1 or DAPOO 1 and CKPO0 0 R01DS0193EJ0100 Rev 1 00 Dec 10 2012 Page 39 of 61 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Caution Select the TTL input buffer for the SI00 pin and the N ch open drain output Voo tolerance mode for the SO00 pin and SCKOO pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 Redirect to PO is not supported in 24 pin products Remarks 1 Rb Q Communication line GCKOO SOp pull up resistance Cb F Communication line SCK00 SOOO load capacitance Vb V Communication line voltage 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSO0 bit of serial mode register SMROO CSI mode connection diagram during communication at different potential lt Master gt SCKOO SO User s device RL78 G12 SIO0 S000 SI RO1DS0193EJ0100 Rev 1 00 Page 40 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 8 Communication at different potential 1 8 V 2 5 V 3 V fuck 4 CSI00 mode master mode SCKp internal clock output 1 2 Ta 40 to 85 C 1 8 V lt Voo lt Vono lt 5 5 V Vss 0 V Parameter Conditions SCKp cycle time 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 300 Cb 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 500 Cb 30 pF Rb 2 7
25. 4 pin products P10 P11 laav lt vo lt 4ov o o5 V 30 pin products P01 P10 1 8 V lt Voo lt 3 3 V 0 32 V P11 P13 to P17 Vis P60 P61 Vits P121 P122 P125 P137 EXCLK RESET Output voltage high Von 20 24 pin products 4 0 V lt Voo lt 5 5 V POO to PO3 P10 to P14 lom 10 0 mA P40 to P42 4 0 V lt Vo lt 5 5V Voo 0 7 30 pin products lon 3 0 MA POO P01 P10 to P17 P30 37y lt vm lt 5 5V Voo0 6 V P31 P40 P50 P51 P120 loni 2 0 mA P147 1 8 V lt Voo lt 5 5 V Vopp 0 5 V lon1 1 5 MA Notes 1 20 24 pin products only 2 24 pin products only Caution The maximum value of Vin of pins P01 P10 to P12 P41 for 20 24 pin products and P00 P10 to P15 P17 P50 for 30 pin products is Voo even in N ch open drain mode High level is not output in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0100 Rev 1 00 Page 20 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Output voltage low 20 24 pin products POO to PO3 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 Other than P121 P122 P121 P122 X1 X2 EXCLK Input leakage current 1 VoD high luin lLiH2 luvs Other than P121 Vi
26. 5F102AAASP R5F102A9ASP R5F102A8ASP R5F102A7ASP R5F103AAASP R5F103A9ASP R5F103A8ASP R5F103A7ASP R5F102AADSP R5F102A9DSP R5F102A8DSP R5F102A7DSP R5F103AADSP R5F103A9DSP R5F103A8DSP R5F103A7DSP JEITA Package Code RENESAS Code Previous Code MASS TYP g P LSSOP30 0300 0 65 PLSP0030JB B S30MC 65 5A4 3 0 18 detail of lead end F mG LA 1 T Z Y A 4 p LE a lt U ITEM MILLIMETERS Lk A 9 85 40 15 0 45 MAX 0 65 T P 0 08 0 24 9 07 0 1 0 05 1 340 1 1 2 8 1 0 2 6 1 0 2 1 040 2 0 17 40 03 0 5 0 13 0 10 NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition 2 5 aoto 0 25 0 60 15 C A o Z r Aje I O am o O w 2012 Renesas Electronics Corporation All rights reserved R01DS0193EJ0100 Rev 1 00 Page 61 of 61 Dec 10 2012 E RENESAS Revision History RL78 G12 Data Sheet Description Date Page Summary 1 00 Dec 10 2012 First Edition issued All trademarks and registered trademarks are the property of their respective owners SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technology licensed from Silic
27. 7 V lt Vb lt 4 0 V Cb 30 pF Ro 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 KQ Delay time from SCKp to SOp output Note 2 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cp 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 KQ Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register 0 1 PIMO PIM1 and port output mode register 0 1 POMO POM1 Redirect to PO is not supported in 24 pin products Communication at different potential is not allowed in CSI01 CSI11 RO1DS0193EJ0100 Rev 1 00 Page 42 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Remarks 1 Rb Q Communication line SCKp SOp pull up resistance Cp F Communication line SCKp SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 CSI mode connection diagram during communication at different potential lt Mast
28. 8 1 000 000 Notes 1 2 3 Retained for 5 years T 85 C 100 000 Retained for 20 years T 85 C 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self program library 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation Caution This specifications show target values which may change after device evaluation Remark When updating data multiple times use the flash memory as one for updating data RO1DS0193EJ0100 Rev 1 00 Page 57 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 9 Timing Specs for Flash Memory Programming Switching Modes Parameter Conditions How long from when an external reset ends until tsuinit POR and LVD reset are the initial communication settings are specified released before external reset release How long from when the TOOLO pin is placed at the low level until an external reset ends How long the TOOLO pin must be kept at the low level after a reset ends except soft processing time lt 1 gt lt 2 gt lt 3 gt a RESET S 2 2 rn a l tHD i l software processing OOH reception time i m gt TOOLRxD TOOLTxD mode TOOLO tsuiniT
29. 85 C e Pre configured settings 24MHz 16MHz 12MHz 8MHz 4MHz amp 1MHz Reset and Supply Management e Power on reset POR monitor generator e Low voltage detection LVD with 12 setting options Interrupt and or reset function Data Memory Access DMA Coniroller e Up to 2 fully programmable channels e Transfer unit 8 or 16 bit Multiple Communication Interfaces Up to 3 x C master Up to 1 x IC multi master Up to 3 x CSI SPI 7 8 bit Up to 3 x UART 7 8 9 bit Extended Function Timers e Multi function 16 bit timers Up to 8 channels e Interval Timer 12 bit 1 channel e 15 kHz watchdog timer 1 channel window function Rich Analog e ADC Up to 11 channels 10 bit resolution 2 1ys conversion time e Supports 1 8V e Internal voltage reference 1 45V e On chip temperature sensor Safety Features IEC or UL 60730 compliance Flash memory CRC calculation RAM parity error check RAM write protection SFR write protection Illegal memory access detection Clock stop frequency detection ADC self test General Purpose I O e 5V tolerant high current up to 20mA per pin e Open Drain Internal Pull up support Operating Ambient Temperature e Standard 40 C to 85 C Package Type and Pin Count e QFN 24 e SSOP 20 30 There is difference in specifications between every product RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 Please refer to specification for details Page 1 of 61 2tENESA
30. CHAPTER 2 ELECTRICAL SPECIFICATIONS UART mode connection diagram during communication at different potential Vb RL78 G12 User s device UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance pi ES ee ye eS TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remarks 1 Rb Q Communication line TxDO pull up resistance Vo V Communication line voltage 2 q UART number q 0 to 2 g PIM POM number g 0 1 RO1DS0193EJ0100 Rev 1 00 Page 38 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 7 Communication at different potential 2 5 V 3 V CSI00 mode CSI0OO master mode fmck 2 SCKOO internal clock output Ta 40 to 85 C 2 7 V lt Voo lt 5 5 V Vss 0 V Parameter SCKO0O0 cycle time Conditions 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 20 pF Rb 1 4 KQ 200 1 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V Cb 20 pF Rb 2 7 KQ 300 Note 1 SCKO0O0 high level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 20 pF Rb 1 4 KQ tkcy1 2 50 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 KQ tkcy1 2 120 SCKOO low level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V
31. Co 20 pF Rb 1 4 KQ tkcy1 2 7 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 KQ tkcy1 2 10 S100 setup time to SCKOOT 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Co 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V Cb 20 pF Rb 2 7 KQ S100 hold time from SCKOOT 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Co 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 KQ Delay time from SCKO0J to SO00 output 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Co 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V Cb 20 pF Rb 2 7 KQ S100 setup time to SCKOOL 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Co 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V Cb 20 pF Rb 2 7 KQ S100 hold time from SCKOOL 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 20 pF Rb 2 7 KQ Delay time from SCKOOT to SO00 output 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 20 pF Rb 2 7 KQ Notes 1 The value must also be 2 fc k or more 2 When DAPOO 0 and CKPOO 0 or DAPOO
32. EFP1 0 ADREFPO 1 AVrer AVrerM ANI1 ADREFM 1 target ANI pin ANI16 to ANI22 Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Conditions Resolution Overall error 10 bit resolution Conversion time AVrere Voo 3 6 V lt VoD lt 5 5 V 2 7 V lt VDD lt 5 5 V 1 8 V lt VoD lt 5 5 V Notes 1 2 Zero scale error Notes 1 2 Full scale error Note 1 Integral linearity error Note 1 Differential linearity error Reference voltage Analog input voltage AVREFP and Vop Internal reference voltage is selected F 1 5 2 4 V lt VDD lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value RO1DS0193EJ0100 Rev 1 00 Page 52 of 61 Dec 10 2012 Pau RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 3 When AVre Voo ADREFP1 0 ADREFPO 0 AVrer Vss ADREFM 0 target ANI pin ANIO to ANI3 ANI16 to ANI22 Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Reference voltage Voo Reference voltage Vss Parameter Conditions Resolution Overall error 10 bit resolution Conversion time 3 6 V lt VoD lt 5 5 V 2 7 V lt VDD lt 5 5 V 1 8 V lt VoD lt 5 5 V
33. EJ0100 Rev 1 00 Page 35 of 61 Dec 10 2012 SS ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode dedicated baud rate generator output Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Transfer rate Note 1 Conditions Normal operation Reception 4 0 V lt Voo lt 5 5 V Theoretical maximum 2 7 V lt V lt 4 0V transfer rate fcLk fuck 24 MHz 2 7 V lt Voo lt 4 0 V Theoretical maximum 2 3 V lt V lt 2 7 V transfer rate fcLk fuck 24 MHz 1 8 V lt Voo lt 3 3 V Theoretical maximum 1 6 V lt Vo lt 2 0 V transfer rate fck fuck 8 MHz Transmissio 4 0 V lt Voo lt 5 5 V Note 1 n 2 7 V lt V lt 4 0V Theoretical maximum 2 8 transfer rate C 50 pF Rb 1 4 kQ Vb 2 7 V 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V Theoretical maximum iaia transfer rate C 50 pF Rb 2 7 kQ Vb 2 3 V 1 8 V lt Voo lt 3 3 V Note 5 1 6 V lt Vo lt 2 0 V Theoretical maximum 0 43 transfer rate Co 50 pF Ro 5 5 KQ Vo 1 6 V SNOOZE mode Notes 1 The smaller maximum transfer rate derived by using fmck 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt Voo lt 5 5 V and 2 7 V lt Vb lt 4 0 V 1 Maximum transfer rate
34. F Ro 3 KQ 1 8 V lt Voo lt 2 7 V Cb 100 pF Re 5 KQ Data setup time reception tsu DAT 1 8 V lt Voo lt 5 5 V 1 fuck 145 Cb 100 pF Re 3 KQ 1 8 V lt Voo lt 2 7 V 1 fuck 230 C 100 pF Rb 5 KQ Data hold time transmission 1 8V lt Vp0 lt 5 5 V C 100 pF Rb 3 KQ 1 8 V lt Voio lt 2 7 V C 100 pF Rb 5 KQ Note Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the N ch open drain output Voo tolerance mode for SDAr by using port output mode register h POMh Remarks 1 Rb Q Communication line SDAr pull up resistance Cb F Communication line SCLr SDAr load capacitance 2 r IIC number r 00 01 11 20 h POM number h 0 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number 0 1 3 4 Simplified C mode is supported by the R5F102 products RO1DS0193EJ0100 Rev 1 00 Page 34 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Simplified IC mode connection diagram during communication at same potential Voo Rb SDA SCL RL78 G12 User s device Simplified IC mode serial transfer timing during communication at same potential SCLr SDAr HD DAT tsu DAT RO1DS0193
35. FFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario LY 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation
36. Hz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vop 1 8 V to 5 5 V 1 MHz to 8 MHz 4 When high speed system clock is stopped a When high speed on chip oscillator clock is stopped 6 When high speed on chip oscillator clock high speed system clock and watchdog timer are stopped Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fik high speed on chip oscillator clock frequency 3 Except temperature condition of the TYP value is Ta 25 C other than STOP mode RO1DS0193EJ0100 Rev 1 00 Page 23 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 30 pin products Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V 1 2 Parameter Conditions Supply Ipp1 Operating HS High speed fin 24 MHz a mA current main mode operation lvoo 3ov las Normal Voo s 0v a7_ 55 peratonlvoo sov az 55 sa ar ao LS Low speed fin 8 MHz Voo 3 0 V Jaz as mA main mode Voo 2 0V 7 4 6 mA mA HS High speed fux 20 MH2 Square wave input i Note2 main mode Voo 5 0 V Resonator connection fux 20 MHz2 Square wave input Voo 3 0 V Resonator connection fux 10 MH2 Square wave input fux 10 MH2 Square wave input Voo 3 0 V Resonator connection LS Low speed_ fmx 8 MHz Square wave input mA r Note2
37. PTER 2 ELECTRICAL SPECIFICATIONS 8 Communication at different potential 1 8 V 2 5 V 3 V fuck 4 CSI mode master mode SCKp internal clock output 2 2 Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Slp setup time to SCKpT Conditions 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 30 pF Ro 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cp 30 pF Rb 5 5 KQ Slp hold time from SCKp 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cp 30 pF Ro 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cp 30 pF Rb 5 5 KQ Delay time from SCKp to SOp output Note 1 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cp 30 pF Ro 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 KQ Slp setup time to SCKp4 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V C 30 pF Ro 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V C 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 KQ Slp hold time from SCKpJ 4 0 V lt Von lt 5 5 V 2
38. R5F103 Product Data Flash R5F102 R5F1026A R5F1027A R5F102AA R5F10269 R5F10279 R5F102A9 R5F10268 R5F10278 R5F102A8 R5F10267 R5F10277 R5F102A7 R5F10266 R5F103 Not mounted R5F1036A R5F1037A R5F103AA R5F10369 R5F10379 R5F103A9 R5F10368 R5F10378 R5F103A8 R5F10367 R5F10377 R5F103A7 R5F 10366 Note The RAM in the R5F10266 has capacity as small as 256 bytes Depending on the customer s program specification the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory Caution When the flash memory is rewritten via a user program the flash ROM area and RAM area are used because each library is used When using the library refer to RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual RO1DS0193EJ0100 Rev 1 00 Page 4 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 1 OUTLINE 1 3 2 On chip oscillator characteristics 1 High speed on chip oscillator oscillation frequency of the R5F102 Ossie __ _Goneton __ wan fax f unt High speed on chip Ta 20 to 85 C oscillator oscillation Ta 40 to 20 C frequency accuracy 2 High speed on chip oscillator oscillation frequency of the R5F103 Oscillator Condition mn MAX Unit High speed on chip Ta 40 to 85 C 5 5 oscillator oscillation frequency accuracy 1 3 3
39. S RL78 G12 CHAPTER 1 OUTLINE O ROM RAM capacities Flash ROM Data flash RAM 20 pins 24 pins 30 pins R5F102AA R5F103AA R5F1026A R5F1027A R5F1036A R5F1037A R5F10269 R5F10279 R5F102A9 R5F10369 R5F10379 R5F103A9 R5F10268 R5F10278 R5F102A8 R5F10368 R5F10378 R5F103A8 R5F10267 R5F10277 R5F102A7 R5F10367 R5F10377 R5F103A7 R5F10266 a 2 R5F10366 z Note This is about 639 byte when the self programing function and data flash function are used For detail see CHAPTER 3 CPU ARCHITECTURE in the RL78 G12 User s Manual 1 2 Ordering Information Pin Package Data flash Fields Part Number count of Applica tion 20 pins 20 pin plastic Mounted R5F1026AASP R5F10269ASP R5F10268ASP R5F10267ASP R5F10266ASP SSOP R5F1026ADSP R5F10269DSP RSF 10268DSP R5F10267DSP R5F10266DSP 4 4 6 5 Not mounted R5F1036AASP R5F10369ASP R5F10368ASP R5F10367ASP R5F10366ASP R5F1036ADSP R5F10369DSP R5F10368DSP R5F10367DSP R5F10366DSP R5F1037AANA R5F10379ANA R5F10378ANA R5F10377ANA R5F1037ADNA R5F10379DNA R5F10378DNA R5F10377DNA 30 pin plastic Mounted R5F102AAASP R5F102A9ASP R5F102A8ASP R5F102A7ASP SSOP R5F102AADSP R5F102A9DSP R5F102A8DSP R5F102A7DSP eamm Not mounted R5F103AAASP R5F103A9ASP R5F103A8ASP R5F103A7ASP 300 R5F103AADSP R5F103A9DSP R5F103A8DSP R5F103A7DSP Note For fields of application see Figure 1 1 Part Number Memory Size and Package o
40. Vss P122 P121 P122 Vi Vss X1 X2 EXCLK Vi VoD Input leakage current low On chip pull up resistance 20 24 pin products POO to P03 P10 to P14 P40 to P42 P125 RESET 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 RESET Note 24 pin products only 4 0V lt Vp0 lt 5 5V lors 15 0 mA 4 0V lt Vp0 lt 5 5V lot1 20 0 mA 4 0V lt Vp0 lt 5 5V lott 8 5 MA 2 7V lt Vo0 lt 5 5 V IOL1 3 0 mA 2 7 V lt Voo lt 5 5 V lor1 1 5 mA 1 8 V lt Voo lt 5 5 V lot1 0 6 mA i maka TEE me Laka TEE B 4 0 V lt Voo lt 5 5 V lors 5 0 mA 2 7 V lt Voo lt 5 5 V lors 3 0 mA 1 8 V lt Voo lt 5 5 V lors 2 0 mA Input port or external clock input When resonator connected Input port or external clock input When resonator connected Vi Vss input port Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 Page 21 of 61 ztENESAS RL78 G12 2 3 2 Supply current characteristics 1 20 24 pin products Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Symbol Conditions Supply Ipp1 Operating HS High speed fin 24 MHz current main mode Note 3 fH 16 MHz LS Low speed fin 8 MHz main mode HS High speed fux 20 MHz main mode
41. ance Timer 16 bit timer 4 channels 8 channels Watchdog timer 1 channel 12 bit Interval timer 1 channel Notes 1 The self programming function cannot be used in the R5F10266 and R5F 10366 2 When PIORO is set to 1 in R5F102Az 3 The number of PWM outputs varies depending on the setting of channels in use the number of masters and slaves see 6 8 3 Operation as multiple PWM output function in the RL78 G12 User s Manual Caution When the flash memory is rewritten via a user program the flash ROM area and RAM area are used because each library is used When using the library refer to RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual RO1DS0193EJ0100 Rev 1 00 Page 13 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 1 OUTLINE 2 2 R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax 1 2 44 kHz to 10 MHz Peripheral hardware clock fwain 20 MHz operation 8 10 bit resolution A D converter 11 channels Serial interface CSI UART Simplified IC CSI Simplified C Clock output buzzer output Product with data flash memory 30 pin CSI UART Simplified I C x 3 CSI UART Multiplier and divider multiply e 16 bits x 16 bits 32 bits unsigned or signed accumulator e 32 bits 32 bits 32 bits unsigned e 16 bits x 16 bits 32 bits 32 bits unsigned or signed Sources External a i e o e Reset by RESET pin e Internal reset by
42. and 32 do not include mold flash A ee A1 0 10 0 10 2 Dimension X3 does not include trim offset A2 1 15 e 0 65 0 12 0 10 bp 0 227 6 95 0 05 c 0 152002 L 0 50 0 20 y 0 10 0 0 to 10 2012 Renesas Electronics Corporation All rights reserved R01DS0193EJ0100 Rev 1 00 Page 59 of 61 Dec 10 2012 2tENESAS RL78 G12 CHAPTER 3 PACKAGE DRAWINGS 3 2 24 pin products R5F1027AANA R5F10279ANA R5F10278ANA R5F10277ANA R5F1037AANA R5F10379ANA R5F10378ANA R5F10377ANA R5F1027ADNA R5F10279DNA R5F10278DNA R5F10277DNA R5F1037ADNA R5F10379DNA R5F10378DNA R5F10377DNA JEITA Package Code RENESAS Code Previous Code MASS TYP g P HWQFN24 4x4 0 50 PWQN0024KE A P24K8 50 CAB 1 0 04 DETAIL OF A PART E A I LE i UNIT mm ITEM DIMENSIONS D 4 00 0 05 E 4 00 0 05 A 0 75 0 05 EXPOSED DIE PAD 0 05 b 0 2575 0 07 e 0 50 Lp 0 40 0 10 x 0 05 B y 0 05 ITEM D2 E2 MIN NOM MAX MIN NOM MAX EXPOSED DIE PAD A 2 45 2 50 2 55 2 45 2 50 2 55 A 18 13 VARIATIONS E Lp e bix SAB 2012 Renesas Electronics Corporation All rights reserved R01DS0193EJ0100 Rev 1 00 Page 60 of 61 Dec 10 2012 E RENESAS RL78 G12 CHAPTER 3 PACKAGE DRAWINGS 3 3 30 pin products R
43. ansfer timing tHD STA tsu sTO Stop Start Restart Stop condition condition condition condition 2 5 3 On chip debug UART Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V RO1DS0193EJ0100 Rev 1 00 Page 50 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 6 Analog Characteristics 2 6 1 A D converter characteristics 1 When AVrer AVrerP ANIO ADREFP1 0 ADREFPO 1 AVrer AVrermM ANI1 ADREFM 1 target ANI pin ANI2 ANI3 Ta 40 to 85 C 1 8 V lt Vpp lt 5 5 V Vss 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Conditions Resolution Note 1 Overall error 10 bit resolution Conversion time AVrerr Voo 3 6V lt Vpp lt 5 5V 2 7V lt Vpp lt 5 5V 1 8 V lt VDD lt 5 5 V Notes 1 2 Zero scale error Notes 1 2 Full scale error Note 1 Integral linearity error Note 1 Differential linearity error Reference voltage Analog input voltage Internal reference voltage is selected 2 4 V lt VoD lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value RO1DS0193EJ0100 Rev 1 00 Page 51 of 61 Dec 10 2012 Pau RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 When AVrer AVrerP ANIO ADR
44. cillation frequency or external main system clock frequency 2 fik high speed on chip oscillator clock frequency 3 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 Page 22 of 61 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 2 2 Supply HS High speed fin 24 MHz Voo 5 0 V Jao 1210 HA Note 1 Note 2 Note3 current main mode Von 3 0 V o 1210 a ole LS Low speed fin 8 MHz Voo 3 0 V 20 542 HA Note 3 desl Voo 2 0 V 270 saa Note 3 fwe 10 MHz Square wave input 190 soo sa LS Low speed_ fmx 8 MHz Square wave input f 110 360 uA main mode Voo 3 0 V Resonator connection 150 me Yer 20V Resonatorconnecion 150 416 Notes 1 Total current flowing into Vop including the input leakage current flowing when the level of the input pin is fixed to Vop or Vss The values below the MAX column include the peripheral operation current except for background operation BGO However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors 2 During HALT instruction execution by flash memory 3 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vpop 2 7 V to 5 5 V 1 M
45. emarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fik high speed on chip oscillator clock frequency 3 Except STOP mode temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0100 Rev 1 00 Page 25 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 3 Common to RL78 G12 all products CHAPTER 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter 12 bit interval timer operating current ItwKa Notes 1 2 fi 15 kHz Conditions Watchdog timer operating current Notes 1 3 WDT fi 15 kHz A D converter operating current ADC Note 4 When conversion at maximum speed Normal mode AVrere Voo 5 0 V Low voltage mode AVrerr Voo 3 0 V A D converter reference voltage current Note 5 IADREF Temperature Imps 5 sensor operating current LVD operating current ILvp Note 6 BGO operating current leco Note 7 SNOOZE operating current Notes 1 Remarks 1 f 2 fck CPU peripheral hardware clock frequency 3 Temperature condition of the TYP value is Ta 25 C Note 5 Note 8 Isnoz ADC operation The mode is performed The A D conversion operations are performed Low voltage mode AVrerr Voo 3 0 V CSI UART operation When high speed on chip oscillator and high speed syste
46. er gt SCKp SO User s device RL78 G12 Slp SOp SI CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy2 tkL2 tkH2 SCKp SOp Output data RO1DS0193EJ0100 Rev 1 00 Page 43 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 SCKp SOp Output data RO1DS0193EJ0100 Rev 1 00 Page 44 of 61 Dec 10 2012 Eoin ee RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions SCKp cycle time Noromal operation 4 0 V lt Vo lt 5 5 V 20 MHz lt fuck lt 24 MHz 12 fuck 2 7V lt VWo lt 4 0V 8 MHz lt fuck lt 20 MHz 10 fuck 4 MHz lt fuck lt 8 MHz 8 fuck fuck lt 4 MHz 6 fuck 2 7 V lt Vo lt 4 0 V 20 MHz lt fuck lt 24 MHz 16 fuck 2 3 V lt V lt 2 7 V 16 MHz lt fuck lt 20 MHz 14 fuck 8 MHz lt fuck lt 16 MHz 12 fmck 4 MHz lt fuck lt 8 MHz 8 fuck fuck lt 4 MHz 6 fuck 1 8 V lt Voo lt 3 3 V 20 MHz lt fuc
47. erial Clock Input Output Serial Clock Input Output Serial Data Input Output Serial Data Input Serial Data Output Timer Input Timer Output Data Input Output for Tool Data Input Output for External Device Transmit Data Power supply Ground Crystal Oscillator Main System Clock RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 ztENESAS Page 9 of 61 RL78 G12 CHAPTER 1 OUTLINE 1 6 Block Diagram 1 6 1 20 pin products TAUO 4 ch TI00 TOOO T101 TOO1 TI02 TOO2 T103 T003 TOOL TOOL TOOLO TxD RxD Multiplier amp divider multiply accumulator SCLAO i SDAAO IICAO Code flash 16 KB Data flash 2KB Note DMA Note 2ch RL78 CPU core a K one n K 3_ P121 P122 P125 Buzzer clock output control yy eyrun 6 KRO to KR5 6ch Interrupt control Ach PCLBUZO INTPO to INTP3 Window watchdog timer Clock Generator Reset Generator Main OSC 1 to 20 MHz X1 X2 EXCLK Power on Low speed High Speed reset low on chip on chip oscillator 1 to 24 MHz voltage oscillator detector 15 kHz Voo Vss Note Provided for the R5F102 products CRC Note K 9 ANI2 ANI3 ANI16 to ANI22 ANIO AVrere ANI1 AVrerm gt 10 bit A D converter 11ch RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 ztENESAS Page 10 of 61 RL78 G12 CHAPTER 1 OUTLINE 1 6 2 24 pin products
48. eter Conditions Temperature sensor output voltage Vimps2s Setting ADS register 80H TA 25 C Internal reference voltage Vconst Setting ADS register 81H Temperature coefficient Fvtmes Temperature sensor that depends on the temperature Operation stabilization wait time 2 6 3 POR circuit characteristics Ta 40 to 85 C Vss 0 V Parameter Conditions Detection voltage Power supply rise time Power supply fall time Minimum pulse width Detection delay time RO1DS0193EJ0100 Rev 1 00 Page 54 of 61 Dec 10 2012 Pau RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 85 C Vror lt Voo lt 5 5 V Vss 0 V Parameter Conditions Detection supply voltage Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Vivp10 Power supply rise ti
49. f so 120 fm 16 MHz vw 50v_ 40 1000 LS Low speed fin 8 MHz peo a Te HS High speed fmx 20 MHZz 5 Square wave input 2 main mode Voo 5 0 V pararmos e Tay ee fmx 10 MHZ 5 Square wave input 190 600 w Nee S0V Resonator connecion 260 67o LS Low speed fux 8 MHZ2 5 Square wave input 95 330 main mode Voo 3 0 V Resonator connection 145 380 fm 8MHZ Square wave input 95 330 ia Besaran es on STOP mode Note 6 Notes 1 Total current flowing into Vop including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors 2 During HALT instruction execution by flash memory 3 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vpop 2 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vbo 1 8 V to 5 5 V 1 MHz to 8 MHz 4 When high speed system clock is stopped a When high speed on chip oscillator clock is stopped 6 When high speed on chip oscillator clock high speed system clock and watchdog timer are stopped The values below the MAX column include the leakage current R
50. f RL78 G12 24 pins 24 pin plastic Mounted A R5F1027AANA R5F10279ANA R5F10278ANA R5F10277ANA WQFN R5F1027ADNA R5F10279DNA R5F10278DNA R5F10277DNA RO1DS0193EJ0100 Rev 1 00 Page 2 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 1 OUTLINE Figure 1 1 Part Number Memory Size and Package of RL78 G12 Package type SP SSOP 0 65 mm pitch NA WQFN 0 50 mm pitch ROM number Omitted with blank products Classification A Consumer applications operating ambient temperature 40 C to 85 C D Industrial applications operating ambient temperature 40 C to 85 C ROM capacity 6 2KB 7 4KB 8 8KB 9 12 KB A 16KB Pin count 6 20 pin 7 24 pin A 30 pin RL78 G12 group 102 Data flash is povided 103 Data flash is not provided Memory type F Flash memory Renesas MCU Renesas semiconductor product RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 Page 3 of 61 ztENESAS RL78 G12 CHAPTER 1 OUTLINE 1 3 Differences between R5F102 and R5F103 The following are differences between the R5F102 and R5F103 O Whether the data flash memory is mounted or not O High speed on chip oscillator oscillation frequency accuracy O Number of channels in serial interface O Whether the DMA function is mounted or not O Whether the safety function is mounted or not 1 3 1 Data Flash The data flash memory of 2 KB is mounted on the R5F102 but not on the
51. for instruction execution time RO1DS0193EJ0100 Rev 1 00 Page 17 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 3 DC Characteristics 2 3 1 Pin characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 1 4 eme om o e a e e Output current high Per pin 20 24 pin products 10 0 POO to P03 P10 to P14 P40 to P42 30 pin products POO PO1 P10 to P17 P30 P31 P40 P50 P51 P120 P147 Total of all 20 24 pin products 4 0 V lt Voo lt 5 5 V erves eo a Note 2 30 pin products POO 1 8V lt Vo lt 2 7V P01 P40 P120 20 24 pin products 4 0 V lt Voo lt 5 5 V sent t Note 3 Poo to POs 2 7 Vs Voo lt 4 0V Fs Pa P10 to P14 1 8 V lt Voo lt 2 7 V 10 0 30 pin products P10 to P17 P30 P31 fa P51 P147 All All the terminais 0 terminals oo f o Perpin P20 to P23 a Total of all 0 4 pins Notes 1 value of current at which the device operation is guaranteed even if the current flows from the Vop pin to an output pin 2 Specification under conditions where the duty factor is 70 The output current value that has changed the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins loH x 0 7 n x 0 01 lt Example gt Where n 50 and loH 10 0 mA Total output current of pins 10 0 x 0 7 50 x 0 01 14 0 mA However the
52. frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number n 0 1 3 1 3 is for the R5F102 products RO1DS0193EJ0100 Rev 1 00 Page 32 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS CSI mode connection diagram during communication at same potential SCKp SCK RL78 G12 Sip SO User s device SOp SI CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKcy1 2 tks01 2 SOp Output data CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkev1 2 tks01 2 Remarks 1 p CSI number p 00 01 11 20 2 n Channel number 0 1 3 RO1DS0193EJ0100 Rev 1 00 Page 33 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 5 During communication at same potential simplified C mode Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions SCLr clock frequency 1 8 V lt Voio lt 5 5 V C 100 pF Re 3 KQ 1 8 V lt Voo lt 2 7 V C 100 pF Re 5 KQ Hold time when SCLr L 1 8 V lt Voio lt 5 5 V C 100 pF Ro 3 KQ 1 8 V lt Voio lt 2 7 V C 100 pF Re 5 KQ Hold time when SCLr H 1 8 V lt Voio lt 5 5 V C 100 p
53. interrupt voltage 3 60 3 67 3 74 v Vivos Veoce Veoci1 Veoci 0 1 1 falling reset voltage 2 7 V 2 70 2 75 2 81 V VLvD4 LVIS1 LVISO 1 O Rising reset release voltage 2 86 2 92 2 97 V 0 1 V Falling interrupt voltage 2 80 2 86 2 91 vV Vivps LVIS1 LVISO 0 1 Rising reset release voltage 2 96 3 02 3 08 V 0 2 V Falling interrupt voltage 2 90 2 96 3 02 V Vivpo LVIS1 LVISO 0 0 Rising reset release voltage 3 98 4 06 4 14 V 1 2 V Falling interrupt voltage 3 90 3 98 4 06 vV R01DS0193EJ0100 Rev 1 00 Dec 10 2012 ztENESAS Page 56 of 61 RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is affected but data is not retained when a POR reset is affected STOP mode lt Operation mode Data retention mode _ gt Voo 4 STOP instruction execution Standby release signal interrupt request 2 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions System clock frequency 1 8 V lt Voo lt 5 5 V Code flash memory rewritable times Retained for 20 years T 85 C Notes 1 2 3 Data flash memory rewritable times Retained for 1 year T 25 C
54. k lt 24 MHz 36 fuck 1 6 V lt Vb lt 2 0 V 16 MHz lt fuck lt 20 MHz 32 fuck 8 MHz lt fuck lt 16 MHz 26 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 10 fmck SNOOZE mode SCKp high low level 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V tkcy2 2 12 width 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V tkcy2 2 18 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V tkcy2 2 50 Slp setup time 2 7 V lt Voo lt 5 5 V 1 fmck 20 Note 1 to SCKp 1 8 V lt Voo lt 3 3 V 4 fvox 30 Slp hold time T ivck 31 from SCKp7 Delay time from 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V 2 fuck 120 SCKpl to SOp output Co 30 pF Rb 1 4 KQ Note 3 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 2 fuck 214 C 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 2 fmck 573 Co 30 pF Rb 5 5 KQ Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPm
55. l RO1DS0193EJ0100 Rev 1 00 Page 15 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C 0510 03 eT SSS REGC terminal input ViRecc REGC 0 3 to 2 8 v voltage and 0 3 to Voo 0 3 Input Voltage Other than P60 P61 0 3 to Voo 0 3 ov P60 P61 N ch open drain 0 3 to 6 5 ov Analog input voltage Val ANIO to ANI22 0 3 to Von 0 3 and 0 3 to AVREF 0 3 Output current high Other than P20 to P23 40 Total of All the terminals other than P20 to P23 all pins 20 24 pin products P40 to P42 30 pin products POO P01 P40 P120 20 24 pin products POO to P03 4 P10 to P14 lt lt 3 3 gt l gt l gt 3 gt 30 pin products P10 to P17 P30 P31 P50 P51 P147 P20 to P23 Total of all pins Output current low Other than P20 to P23 Total of All the terminals other than P20 to P23 all pins 20 24 pin products P40 to P42 30 pin products POO P01 P40 P120 3 gt 3 3 3 gt gt gt 20 24 pin products POO to P03 P10 to P14 P60 P61 30 pin products P10 to P17 P30 P31 P50 P51 P60 P61 P147 P20 to P23 i Total of 5 all pins Operating ambient Ta 40 to 85 C temperature Notes 1 30 pin product only 2 Connect the REGC pin to Vss via a capacitor 0 47 to 1 uF This value determines the absolute maximum rating of the REGC pi
56. lt Vo lt 2 7 V 1 fmcek 190 ns Co 100 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 1 fmck 190 ns Co 100 pF Rb 5 5 KQ Data hold time transmission tHo nat 4 0 V lt Voo lt 5 5 V 2 7 V lt V lt 4 0 V 0 355 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V 0 355 ns Co 100 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 0 405 ns Co 100 pF Rb 5 5 KQ Note Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the TTL input buffer and the N ch open drain output Voo tolerance mode for the SDAr pin and the N ch open drain output Voo tolerance mode for the SCLr pin by using port input mode register 0 1 PIMO PIM1 and port output mode register 0 1 POMO POM1 Communication at different potential is not allowed in IIC01 IIC11 Remarks 1 Rb Q Communication line SDAr SCLr pull up resistance C F Communication line SDAr SCLr load capacitance Vb V Communication line voltage 2 r IIC Number r 00 20 3 fmck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 4 Simplified IC mode is supported by the R5F102 products Simplified IC mode connection diagram during communication at different potential RO1DS0193EJ0100 Rev 1 00 Page 48 of
57. m clock are stopped Current flowing only to the 12 bit interval timer including the operating current of the low speed on chip oscillator The current value of the RL78 G12 microcontrollers is the sum of Ipp1 Ipp2 or Ibos and Iwot when fck fsus when the watchdog timer operates in STOP mode Current flowing only to the watchdog timer including the operating current of the 15 KHz low speed on chip oscillator The current value of the RL78 G12 microcontrollers is the sum of Ipp1 Ipp2 or Ibos and Iwot when fck fsus when the watchdog timer operates in STOP mode Current flowing only to the A D converter The current value of the RL78 G12 microcontrollers is the sum of Ipp1 or Ipp2 and lanc when the A D converter operates in an operation mode or the HALT mode Current flowing to the Vpp Current flowing only to the LVD circuit The current value of the RL78 G12 microcontrollers is the sum of Ipp1 Ipp2 or Ibos and Iv_p when the LVD circuit operates in the Operating HALT or STOP mode Current flowing only to the BGO The current value of the RL78 G12 microcontrollers is the sum of Ipp1 or Ipp2 and Ineo when the BGO operates in an operation mode Refer to shift time to the SNOOZE mode see 17 2 3 SNOOZE mode in the RL78 G12 User s Manual Low speed on chip oscillator clock frequency RO1DS0193EJ0100 Rev 1 00 Dec 10 2012 Page 26 of 61 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 4 AC Characteristics Ta 40 to
58. me Power supply fall time Vivo11 Power supply rise time LILIS SISSI SSIS SISIKII KISIS SISKS Power supply fall time Minimum pulse width Detection delay time R01DS0193EJ0100 Rev 1 00 Page 55 of 61 Dec 10 2012 RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS LVD detection voltage of interrupt amp reset mode Ta 40 to 85 C Vepr lt Voo lt 5 5 V Vss 0 V Parameter LVD detection voltage Conditions Vivo11 Vrocz2 Veoc1 Vroco 0 O 1 falling reset voltage 1 8 V 1 80 1 84 1 87 V Vivo10 LVIS1 LVISO 1 0 Rising reset release voltage 1 94 1 98 2 02 V 0 1 V Falling interrupt voltage 1 90 1 94 1 98 v VLvo9 LVIS1 LVISO 0 1 Rising reset release voltage 2 05 2 09 2 13 V 0 2 V Falling interrupt voltage 2 00 2 04 2 08 V VLvo2 LVIS1 LVISO 0 0 Rising reset release voltage 3 07 3 13 3 19 V 1 2 V Falling interrupt voltage 3 00 3 06 3 12 vV Vivps Vpoce Veoci1 Vroco 0 1 0 falling reset voltage 2 4 V 2 40 2 45 2 50 V VLvo7 LVIS1 LVISO 1 O Rising reset release voltage 2 56 2 61 2 66 V 0 1 V Falling interrupt voltage 2 50 2 55 2 60 vV Vivpe LVIS1 LVISO 0 1 Rising reset release voltage 2 66 2 71 2 76 V 0 2 V Falling interrupt voltage 2 60 2 65 2 70 V Vivo1 LVIS1 LVISO 0 0 Rising reset release voltage 3 68 3 75 3 82 V 1 2 V Falling
59. me systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
60. n 0 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance mode for the SOp and SCKp pins by using port input mode register 0 1 PIMO PIM1 and port output mode register 0 1 POMO POM1 Redirect to PO is not supported in 24 pin products Communication at different potential is not allowed in CSI01 CSI11 RO1DS0193EJ0100 Rev 1 00 Page 45 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Remarks 1 Rb Q Communication line SOp pull up resistance C F Communication line SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn CSI mode connection diagram during communication at different potential lt Slave gt Vb SCKp RL78 G12 Slip SO User s device SOp sI CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy1 SCKp SOp Output data RO1DS0193EJ0100 Rev 1 00 Page 46 of 61 Dec 10 2012 ztENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn
61. n Do not use it with voltage applied 3 Must be 6 5 V or lower 4 24 pin product only Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 AVREF Side reference voltage of the A D converter 3 gt 3 3 gt gt 3 3 RO1DS0193EJ0100 Rev 1 00 Page 16 of 61 Dec 10 2012 ss RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 2 Oscillator Characteristics 2 2 1 X1 clock oscillator characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V X1 clock oscillation Ceramic resonator 2 7V lt Vo0 lt 5 5V T Note frequency fx crystal oscillator 18V lt Vo lt 2 7V Py fe Note Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Cautions 1 When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible e Do not cross the wiring with the other signal lines e Do not ro
62. o the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability what
63. on Storage Technology Inc C 1 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Envir
64. onmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage t
65. ows from an output pin to the Vss pin 2 Specification under conditions where the duty factor is 70 The output current value that has changed the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lot x 0 7 n x 0 01 lt Example gt Where n 50 and lot 10 0 mA Total output current of pins 10 0 x 0 7 50 x 0 01 14 0 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 3 24 pin products only Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0100 Rev 1 00 Page 19 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 3 4 Input voltage high Normal input buffer 0 8Vpp Vpop V 20 24 pin products POO to P03 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 20 24 pin products P10 P11 lasv lt Vo lt 4ov 20 vo v P11 P13 to P17 Vins P121 P122 P125 P137 EXCLK RESET Input voltage low Vi Normal input buffer 20 24 pin products POO to P03 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 20 2
66. soever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti cri
67. technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics RENESAS SALES O
68. ut mode register 1 PIM1 and port output mode register 1 POM1 Remarks 1 This specification is valid only when CSI00 s peripheral I O redirect function is not used 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSO0O bit of serial mode register SMROO RO1DS0193EJ0100 Rev 1 00 Page 30 of 61 Dec 10 2012 Pau RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 3 During communication at same potential CSI mode master mode fmck 4 SCKp internal clock output Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions SCKp cycle time 2 7V lt Vo0 lt 5 5V 167 2 4V lt Vo0 lt 5 5V 250 1 8V lt Vo lt 5 5V 500 SCKp high low level width 40V lt Vo0 lt 5 5V tkcy1 2 12 2 7 V lt Voo lt 5 5 V tkcy1 2 18 2 4 V lt Voo lt 5 5 V tkcy1 2 38 1 8 V lt Voo lt 5 5 V tkcy1 2 50 Slp setup time to SCKpT tsik1 4 0 V lt Voo lt 5 5 V 44 ns 2 7 V lt Voo lt 5 5 V 44 ns 2 4 V lt V lt 5 5V 75 ns 1 8 V lt Voo lt 5 5 V 110 ns Slp hold time from SCKpT tksi1 19 ns Delay time from SCKp1 to tkso1 C 30 pF 25 ns SOp output Notes 1 The value must also be 4 fc k or more 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip setup time becomes to SCKp4 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn
69. ute the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator 2 Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used 2 2 2 On chip oscillator characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Oscillators Parameters Conditions High speed on chip oscillator Note 1 oscillation frequency High speed on chip oscillator R5F102 TA 20 to 85 C oscillation frequency Ta 40 to 20 C Note 2 accuracy R5F103 Low speed on chip oscillator oscillation frequency Low speed on chip oscillator oscillation frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This only indicates the oscillator characteristics Refer to AC Characteristics
70. watchdog timer e Internal reset by power on reset e Internal reset by voltage detector e Internal reset by illegal instruction execution e Internal reset by RAM parity error e Internal reset by illegal memory access Power on reset circuit e Power on reset 1 51 0 03 V e Power down reset 1 50 0 03 V Voltage detector e Rising edge 1 88 to 4 06 V 12 stages e Falling edge 1 84 to 3 98 V 12 stages Power supply voltage Voo 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C Note The illegal instruction is generated when instruction code FFH is executed Note Reset by the illegal instruction execution not issued by emulation with the in circuit emulator or on chip debug emulator RO1DS0193EJ0100 Rev 1 00 Page 14 of 61 Dec 10 2012 PEMAN RENESAS RL78 G12 CHAPTER 2 ELECTRICAL SPECIFICATIONS 2 ELECTRICAL SPECIFICATIONS Cautions 1 The RL78 G12 has an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 The pins mounted depend on the product Refer to 2 1 Port Function to 2 2 1 Functions for each product in the RL78 G12 User s Manua

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