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M5272C3 User`s Manual

1. d 4 3 2 1 DEFAULT SETTING FOR JUMPERS 1 2 amp 3 IS RPS 4x 50 JUMPER FITTED BETWEEN PINS 1 amp 2 Pd ETXERR SL 2E AUTO NEGOTIATION 10 100 FULL DUPLEX a ETXCLK 3 4 D1 u6 ETXEN ETXEN 515 gL8 A Lie voci ETXDO 2 Spa RP6 4x 22 4 RED RP7 4x 50 1 2 ECRS Di JP1 RE ECRS A ETXD1 ERXERR akp SS 3a reen ERXERR Sid hi 2 Oo GND ETXDS 513 40 5 6 ERXDV ERXCLK 25MHz ECOL lt ECOL Si 7 at ERXDY GREEN K ETXD 0 3 7 ETHERNET OSC DUAL 43 3V Bicolour LED LAYOUT FOOTPRINT FOR 8 AND 14 PIN DIL OSC S NOTE minimise track lengths between U7 and RP5 RP6 RP7 amp RP8 RED LED Ethernet Int D3 3 3V Ww A D 43 3V 43 3V ail r4 A RED LEVEL ONE 10 100 4 _JP2 ETHERNET 4 NOTE Pins 36 37 amp 38 on U7 provide dual functionality 2 d d 1 2 CFG2 TRANSCEIVER initially as configuration inputs on power up and then LED e ae e drivers as selected by the LED configuration
2. Table 1 3 JP19 JP18 CS0 Databus width OFF OFF 32 bit OFF ON 8 bit ON OFF 16bit ON ON Reserved Table 1 4 Ethernet Controller Slew Rate Jumper Settings Using The BDM Port JP12 JP10 Ethernet Controller Slew Rate 1 2 1 2 0 2 5nS 1 2 0 2 3 1 3 1nS 2 3 1 1 2 0 3 7nS 2 3 1 2 3 1 4 3nS Table 1 5 Ethernet Controller Operation Modes AutoNegotiation Speed MBPS Duplex JP1 JP2 JP3 Disabled 10 Half L L L Disabled 10 Full L L H Disabled 100 Half L H L Disabled 100 Full L H H Enabled 100 ONLY Half H L L Enabled 100 ONLY Full H L H Enabled 10 100 Half H H L Enabled 10 100 Full Half H H H 1 12 Using The BDM Port The MCF5272 has a built in debug mechanism referred to as BDM background debug module The M5272C3 has the Motorola defined debug module connector J4 to facilitate this connection In order to use the BDM simply connect the 26 pin connector at the end of the BDM wiggler cable provided by Motorola from P amp E Microcomputer Systems to the J4 connector No special setting is needed Refer to the ColdFire User s Manual BDM Section for additional instructions Chapter 1 M5272C3 Board PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Using The BDM Port NOTE BDM functionality and use is supported via third party developer softw
3. y Y QSPI A Expansion Connector 1 Expansion Connector 2 Burst Flash 16 bit 3 3v m LevelOne LXT971L T4 Y 2M 25MHz 10 100 Mb sec Oscillator USB Xcvr 48MHz OSC RJ45 Connector JR1 Connector Figure 1 1 M5272C3 Block Diagram Chapter 1 M5272C3 Board 1 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com System Memory 1 2 System Memory One on board Flash ROM U8 is used to store the M5272C3 dBUG debugger monitor firmware in the lower 256 KBytes The AM29PL160C XX device contains 16Mbits of non volatile storage 16 bits by 1 MByte giving a total of 2MBytes of Flash memory The MCF5272 has 4KBytes of internal SRAM organized as 1KBx32bits The SRAM can be used for either data or instruction space There are two SDRAM devices on the PCB The system ships with 2 x IM x 16 of SDRAM totalling 4MBytes of volatile memory Various SDRAM manufacturers devices as detailed on the schematics are supported The internal cache of the MCF5272 is non blocking The instruction cache is 1 KByte with a 16 byte line size The ROM Monitor currently does not utilize the cache but programs downloaded with the ROM Monitor can initialise and use the cache The M5272C3 evaluation board
4. 3 rc L oru mola 3584 YS gin sa LOS G Id Figure 1 4 Jumper Locations M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 1 10 For More Information On This Product www freescale com Go to System Power up and Initial Operation 1 10 System Power up and Initial Operation When all of the cables are connected to the board power may be applied The dBUG ROM Monitor initialises the board and then displays a power up message on the terminal which includes the amount of memory present on the board Hard Reset DRAM Size 4M Copyright 1995 2000 Motorola Inc All Rights Reserved ColdFire MCF5272 EVS Firmware v2e la xx Build XXX on XXX XX 20XX XX XX XX Enter help for help dBUG The board is now ready for operation under the control of the debugger as described in Chapter 2 If you do not get the above response perform the following checks 1 Make sure that the power supply is properly configured for polarity voltage level and current capability 1A and is connected to the board 2 Check that the terminal and board are set for the same character format and baud 3 Press the RESET button to insure that the board has been initialized properly If you still are not receiving the proper response your board may have been damaged in shipping Contact Matrix Design for further instructions please see the beg
5. int board in char void asm move 140x0010 d0 select the function asm trap 15 make the call asm move ld1 d0 put the character in dO 2 5 3 CHAR PRESENT This function function code 0x0014 checks if an input character is present to receive A value of zero is returned in DO when no character is present A non zero value in DO means a character is present Assembly example move l 0014 d0 Select the function trap 15 Make the call dO contains the response yes no C example int board_char_present void asm move l 0x0014 d0 select the function asm trap 15 make the call 2 5 4 EXIT TO dBUG This function function code 0x0000 transfers the control back to the dBUG by terminating the user code The register context are preserved Assembly example move l 0000 d0 Select the function trap 15 Make the call exit to dBUG C example void board_exit_to_dbug void asm move l 0x0000 d0 select the function 2 40 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com TRAP 15 Functions asm trap 15 exit and transfer to dBUG Chapier 2 Using the Monitor Debug Firmware 2 41 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Chapter 3 Hardware Desc
6. CS6 amp OI Di ll H oO E used adi Q E used E used E used El read from PLI 0 co write write to PLI 0 con read from PLI 1 co write to PLI 1 con For More Information On This Product Go to www freescale com nnector nector nnector nector Sheet 5 Expans Sheet 14 USB PAG USBRXD PA1 USB_R PA2IUSB_RN PAO USB TP PA3 USB_TN PA4 USB_SUSI PAS USB_TXEN USBLineH USBLineL USBEXTCLI ion Connectors PAG USBRXD PAT USB RI PA2 USB_RN PAO USB TI PAS USB_TN Sheet 13 OUTO USRT2TXD USRT2RTS INTS USRTIRXD USRTICTS USRTITXD USRTIRTS Serial Ports SRT2CTS SPI CS2 INO USRT2RXD_ Sheet 8 JTAG BDM Port amp Reset Contig x x amp s MOD x E 7 Ge sg Oo Ho se S it a EX oe 7 of iuo S 959 B p POL Sk sae S22 OZonH 5 Geo ba okQuoe aos POOO O FSF QA S60cc Sheet 12 A10 PRECHG SDWE CASO RASO SDBAO SDCLK SDCKE BS3 B2 rz OW si 8 ZS BSO a x SDRAM Sheet 10 DGNT1 INT6 PSU Reset amp Clocks CS7 box FSRAM BCLK CPU RESET BCLK PAL PA4 USB Sep PAS USB TXE USBEXTCLK CPU Ext CLK DINO USRT2RXD A10 PRECH WSEL BUSWO USRTIRTS USRTITXD USRTICTS USRT1RXD DSO BKPT DSCLK DSI DTEA CPU CLK DRESETEN MTMOD
7. TEST PST 0 3 DDATA 0 3 RESET ISRT2CTS SPI CS2 ISRT2RTS INTS SPI CS3 DOUT3 DCLO USRT2CLK PWMOUTS TIN2 PWM FSC1 DCL1 GEN_DCL_OUT GNT1 INTG DCLI GEN DCL OUT OUTO USRT2TXD USBLineH USBLineL SDBA1 DFSC3 PB6 TINI TOUTI DFSC2 USRTICLK QSPI DIN DIN1 IOUT2 TOUT2 SPI CS1 DGNTO FSCO FSRO PWMOUT1 DREQO FSR1 DFCS1 DREQ1 Dour DACK HIZ TO BYPASS DIN3 INT4 ERXD 0 3 ETXD 0 3 ECRS ECOL EMDC EMDIO ERXCLK ERXDV ETXCLK ETXEN ETXERR ERXERR INT 3 DE CS 0 7 9zzxo FETTEN EECH BaN Eto9z9ogtoOzi lhzDUoOSSggo aa ER PER moos tzabro O DORNAN g Te 5g ER Soe Belt D Pan c bi Sg 22 3 gore Zap Ge ss E SE S i Zz ER SE EOS fe S SS K 38 99 i 9 880 Z5 d Sheet 9 PLI Connectors PAS USB TXEN PA4 USB SUSP PAS USB TN PAO USB TP c p o E USBLineL ISDBA1 DFSCS PB6 TINI TOUTI DFSC2 USRTICLK PAT USB RP PAG USBRXD USBEXTCLK PA2 USB_RN DOUTO USRT2TXD SPI CS3 DOUT3 QSPI_DIN DIN1 DCLO USRT2CLK PWMOUTS TIN2 PWMOUT2 TOUT2 SPI CS1 DGNTO FSCO FSRO PWMOUT1 DREQO FSC1 FSR1 DFSC1 DREQ1 Dour DCL1 GEN_DCL_OUT Sheet 6 USRT2CTS SPI CS2 DINO USRT2RXD B_A 0 22 PU FLASH BYTE PU FLASH A19 an ron x zo or X 2ogxu SRE SSE fon 88 d S239805 Ska ror gos bey se 9 D s oan EES am 2B s oe
8. ETXCLK 87 88 90 ECOL 89 89 oo Q DERXDV Enxpo 92 ERXCLK 91 91 gp H2 SS ETXEN i 93 94 E ETXD2 95 96 98 als og 28 ERxp3 Cep pp 99 100 CR CS5 RD eps 10i 101 102 H0 mE 108 109 104 a 105 106 ERXERR C86 WR 107 107 108 108 C85 WR EMDC ri 110 EMDIO ETXERR ECRS D 0 31 AMP 177983 5 120way SMT Receptacle 0 22 AMP 177983 5 120way SMT Receptacle NOTE 5V is solely supplied via connector J7 on sheet 9 of the schematics PST 0 3 ETXD 0 3 M SPS SESG HESD ColdFire Group C39 C40 C41 C42 C43 C44 1nF 1nF 1nF 1nF is 1nF Title i M5272C3 Evaluation Board 1 Bize Document Number Rev B MCF5272 Expansion Connectors 1 4 Date Monday March 19 2001 Bheet 5 of 14 1 For More Information On This Product Go to www freescale com B A 0 22 B D 0 31 lt gt B A 0 22 DEFAULT SETTING JUMPER 13 SHOULD BE INSTALLED ACROSS PINS 1 amp 2 JP13 16MBit Flash Boot PU FLASH A19 PU FLASH BYTE m 3 DQ15 A 1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc E ie CS AMD Am29PL160C 16 BIT WIDE BURST FLASH MEMORY BOTTOM BOOT SECTOR B D 0 31 M SPS SESG HESD ColdFire Group itle M5272C3 Evaluation Board ize Document Number A MCF5272 Flash Memory
9. PB13 ERXD1 A10 ERXD3 Bg PBIZ ERXD2 A11 PB11 ERXD3 A12 ECOL ECOL A13 ERXD 0 3 EMDC PB15 EMDC A14 EMDIO EMDIO A15 ECRS ECRS A16 A17 A A18 A19 5a uU az A20 oz x ou EE xazazox9 g A21 as arrears Bo S SEL geo 9 58298983 BE 28 gi SZ 8 ggg 2 52555525 55 gt gt IE E egaquys A 0 22 Zee bie mss5zasoo DH am oooo0000 0000 o o GOA 23392322 z E A 0 22 222 ELE Ozxxzxizg 95 QQ 000000000000 0 B 030 700330800 aaa zaz Saoaooooca 55 55 2222222252222 gt FOS xXo0o0rOooo 3 d d da d RP3 5 3823 za8uau a San 8 MCF5272ZP66 MAPBGA196 H2 SDCLKE 3 4H SDCLK 5 ere SDWE Gh 7 8 CASO 4x22 RP4 TOUF TANT a BE 4 3 3VP NOTE capacitors C19 C20 amp ZC Se C21 should be as close as 7 2 A10 PRECHG PWMOUT1 possible to pins USB VDD and Y p T USB VSS on the MCF5272 ee Ax 22 PWMOUT2TOUT2 USBLineL NOTE minimise track lengths between US and RP3 RP4 PWMOUTS TIN2 USBLineH ANTI 2 PAG USBRXD 3 aa PAS USB TXEN INT 1 3 ZI PA4 USB SUSP DACKHIZ PA2 USB RN TC BYPASS PA1 USB RP PBS TA PAS USB_TN PAO USB TP USBEXTCLK For More Information On This Preduct alor Monday March 19 2001 heat 3 o 14 T Go to www freescale com
10. This switch is used to force an interrupt level 6 priority 3 if the user s program execution should be aborted without issuing a RESET refer to Chapter 2 for more information on ABORT Since the ABORT switch is not capable of generating a vector in Chapter 3 Hardware Description and Reconfiguration 3 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com The Processor and Support Logic response to level six interrupt acknowledge from the processor the dBUG programs this interrupt request for autovector mode The INT1 line of the MCF5272 processor is connected to PLI connector pin B33 J6 The INT3 line of the MCF5272 processor is connected to PLI connector pin A34 J5 Refer to MCF5272 User s Manual for more information about the interrupt controller 3 1 7 Internal SRAM The MCF5272 processor has 4 KBtyes of internal memory which may be programmed as data or instruction memory This memory is mapped to 0x20000000 and configured as data space but is not used by the dBUG monitor except during system initialisation After system initialisation is complete the internal memory is available to the user The memory is relocatable to any 4 KByte boundary 3 1 8 The MCF5272 Registers and Memory Map The memory and I O resources of the M5272C3 hardware are divided into two groups MCF5272 internal and external resources All the I O registers are memory mapped The MCF
11. C because its pins are configured by the WSEL signal during device reset An additional port Port D has only a control register which is used to configure the pins that are not multiplexed with any GPIO signals Please see the MCF5272 User s manual for more detail All of these signals are brought out to expansion connectors J2 amp J3 3 2 5 Ethernet Module The MCF5272 device performs the full set of IEEE 802 3 Ethernet CSMA CD media access control and channel interface functions The MCF5272 Ethernet Controller requires an external interface adaptor and transceiver function to complete the interface to the ethernet media The MCF5272 Ethernet module also features an integrated fast 100baseT Ethernet media access controller MAC The Fast Ethernet controller FEC incorporates the following features Chapter 3 Hardware Description and Reconfiguration 3 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Serial Communication Channels Full compliance with the IEEE 802 3 standard Support for three different physical interfaces 100 Mbps 802 3 media independent interface MIT 10 Mbps 802 3 MII 10 Mbps seven wire interface Half duplex 100 Mbps operation at system clock frequency S 50 MHz 448 bytes total on chip transmit and receive FIFO memory to support a range of bus latencies Note the total FIFO size is 448 bytes It is not intended to hold entir
12. More Information On This Product Go to www freescale com ILLUSTRATIONS Figure Page Number ute Number 1 1 MCF5272C3 Block Daer ic e n NENNEN See eta ee eed etas Rees e HE POETE SOEN 1 3 1 2 Minimum System Configuration EE 1 6 1 3 Pin assignment for female P4 Terminal connector eee 1 9 1 4 Jumper LOC AONS lp S 1 10 2 1 Flow Diagram of dBUG Operational Mode 2 4 3 1 The J4 Connector pin assigriment eieiei 3 15 Illustrations ix For More Information On This Product Go to www freescale com Chapter 1 M5272C3 Board The M5272C3 is a versatile single board computer based on the MCF5272 ColdFire Processor It may be used as a powerful microprocessor based controller in a variety of applications With the addition of a terminal it serves as a complete microcomputer system for reference design development evaluation training and educational use The user need only connect an RS 232 compatible terminal or a personal computer with terminal emulation software and power supply to have a fully functional system Provisions have been made to connect this board to additional user supplied peripherals via the Microprocessor Expansion Bus connectors J2 amp J3 on the schematic diagram to expand memory and I O capabilities Additional peripherals may require bus buffers to minimize additional bus loading The board has been designed to be configured specifically for a user s application The user may upgrade t
13. UJ OO UJ OO UJ SE bo b EE EE ES EE 16 UJ UJ UJ UJ UJ UJ 3 a sw Gees m m E Eos ADDRESS BUS BUFFERS MC74LCX245DT M SPS SESG HESD ColdFire Group itle MC74LCX16245DT M5272C3 Evaluation Board ize Document Number DATA BUS TRANSCEIVERS A MCF5272 Buffers Date Monday March 19 2001 Go to www freescale com DTEA M SPS SESG HESD ColdFire Group Title M5272C3 Evaluation Board ize Document Number Rev Cc MCF5272 CPU 14 BS 0 3 CS 0 7 BS 0 3 G t DDATA 0 3 NOTE Rev 1 2 to Rev 1 3 design revision as a result of BS3 DDATAO EMCICE testing C130 to C133 were added to filter high E frequency clock harmonic noise around the MCF5272 ceu cue 3 3VP Dugem A BKPT BUSWI Peres RSTO DSI C8 ce C10 ci C13 C14 C15 C16 C130 C131 C132 C133 QSPI DI Geo 0 tuF 0 1uF 0 tuF 0 1uF 1nF 1nF 1nF 1nF 680pF 680pF 680pF 680pF RESET WSEIN 4 4 4 4 4 4 4 4 4 4 4 DRESETEN MCF5272 Supply
14. as follows 1 Data Carrier Detect Output shorted to pins 4 and 6 Receive Data Output from board receive refers to terminal side Transmit Data Input to board transmit refers to terminal side Data Terminal Ready Input shorted to pin 1 and 6 Signal Ground Data Set Ready Output shorted to pins 1 and 4 Request to Send Input se oo occa ee E e Clear to send Output 9 Not connected Figure 1 4 shows jumper locations Chapter 1 M5272C3 Board 1 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Installation And Setup m SYOLIJSNNOD I d 9823 sr Kaes 9r lZdf Zdr gt 2823 a E Zeg grg ER org Zeg grg im G O AS 0Z D wag vzd u3dd4ng8 49019 ldi IN e OS S dP vzat 2HW99 E 8z13 GEM vv vin EEN 6vU M D o T4 DI e Zdu SZdy TEST Di a gasta 6
15. decouplin RR IE CPU Ex CLK 3 3VP NOTE the MCF5272 is in a 196 pin MAPBGA package EES g d 33 d E us EBEN Bas 3 qa S3aaal aaa gg aj a9090090000000000 lite E D v Op xx oer ygoer mpar HD Be a sg EXXG2x22PL RPO BSSS8888888888 ZE 2 835 3855 S EES Me spe B 2222 G EE E EE fid S 5599 jaa angare acaa D 0 31 E gas dd FS a p Zo SPI CS3 DOUT3 PA7 SPI_CS3 DOUT3 amp OE 5 DO PCO FSCO FSRO PAB FSCO FSRO go D1 PC1 DGNTO PAS DGNTO D2 PC2 DREQO PA10 DREQO D3 PC3 SPI CS1 PATI SPI Ce DA PCA DFSC2 PATZ DFSC2 D5 PC5 DFSC3 PA13 DFSC3 D6 PC6 DREQ PA14 DREQ1 D7 PC7 DGNT1 INT6 PA15 DGNT1 INTG D8 PCB D9 PCO DCLO USRT2CLK DCLO USRT2CLK D10 PC10 DINO USRT2RXD DINO USRT2RXD___ D11 PC11 USRT2CTSISPI CS2 USRT2CTS SPI CS2 D12 PC12 USRT2RTS INTS KG USRT2RTS INTS D13 PC13 DOUTO USRT2TXD DOUTO USRT2TXD D14 PC14 FSC1 FSR1 DFSC1 FSC1 FSR1 DFSC1 D15 PC15 DCLI GEN DCL OUT DCLI GEN DCL OUT D16 DO Doum Gomm D17 D1 DINI D D18 D2 DIN3 INT4 Dain D19 D3 1 D20 D4 USRTITXD PBO USRTITXD Cold Fire amp MCF5272 Processor D21 D5 USRTIRXD PBI USRTIRXD D22 D6 USRTICTS PBZ USRTICTS D23 D7 USRTIRTS PBS USRTIRTS D24 D8 USRTICLK PB4 USRTICLK D25 D9 D26 D10 PBS CM Pee 27 011 D28 D12 TOUTI PB7 TOUTI D29 D13 TINI TINI D30 D14 D31 D15 ETXCLK L7H ETXCLK ETXEN whe ETXEN Ao ETXERR Er ETXERR Ai N6 ETxDo A2 ETXD2 Me PB10 ETXD1 A3 ETXD3 HE PBe ETXD2 M PBB ETXD3 A5 ERXCLK ERXCLK AG ETXD 0 3 ERXERR PBIA ERXERR A7 ERXDV S Mz ERXDV 8 ERXDT ERXDO A9 ERXDZ M9
16. its information displayed The a option adds a symbol name and its value into the symbol table The r option removes a symbol name from the table The c option clears the entire symbol table the 1 option lists the contents of the symbol table and the s option displays usage information for the symbol table Symbol names contained in the symbol table are truncated to 31 characters Any symbol table lookups either by the SYMBOL command or by the disassembler will only use the first 31 characters Symbol names are case sensitive Symbols can also be added to the symbol table via in line assembly labels and ethernet downloads of ELF formatted files Examples To define the symbol main to have the value 0x00040000 the command is symbol a main 40000 To remove the symbol junk from the table the command is symbol r junk To see how full the symbol table is the command is symbol s To display the symbol table the command is symbol l 2 34 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands TRACE Trace Into Usage TRACE lt num gt The TRACE command allows single instruction execution If num is provided then num instructions are executed before control is handed back to dBUG The value for num is a decimal number The TRACE command sets bits in the processors supervisor registers to achieve single inst
17. lt width gt begin end Memory Display MM mm lt width gt addr data Memory Modify MMAP mmap Memory Map Display RD rd lt reg gt Register Display RM rm reg data Register Modify RESET reset Reset SD sd Stack Dump SET set lt option value gt Set Configurations SHOW show lt option gt Show Configurations STEP step Step Over SYMBOL symbol lt symb gt lt a symb value r symb gt lt C I s gt Symbol Management TRACE trace lt num gt Trace Into UPDBUG updbug Update dBUG UPUSER upuser lt bytes gt Update User Flash VERSION version Show Version Chapier 2 Using the Monitor Debug Firmware PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands ASM Assembler Usage ASM lt lt addr gt stmt The ASM command is a primitive assembler The lt stmt gt is assembled and the resulting code placed at lt addr gt This command has an interactive and non interactive mode of operation The value for address lt addr gt may be an absolute address specified as a hexadecimal value or a symbol name The value for stmt must be valid assembler mnemonics for the CPU For the interactive mode the user enters the command and the optional lt addr gt If the address is not specified then the last address is used The memory contents at the address are disassembled and the user prompted for the new assembly If valid the new assembly is placed into
18. memory and the address incremented accordingly If the assembly is not valid then memory is not modified and an error message produced In either case memory is disassembled and the process repeats The user may press the lt Enter gt or lt Return gt key to accept the current memory contents and skip to the next instruction or a enter period to quit the interactive mode In the non interactive mode the user specifies the address and the assembly statement on the command line The statement is the assembled and if valid placed into memory otherwise an error message is produced Examples To place a NOP instruction at address 0x00010000 the command is asm 10000 nop To interactively assembly memory at address 0x00400000 the command is asm 400000 2 8 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands BC Block Compare Usage BC addr1 addr2 length The BC command compares two contiguous blocks of memory on a byte by byte basis The first block starts at address addrl and the second starts at address addr2 both of length bytes If the blocks are not identical the address of the first mismatch is displayed The value for addresses addr1 and addr2 may be an absolute address specified as a hexadecimal value or a symbol name The value for length may be a symbol name or a number converted according to the user defined radix hexade
19. register in U7 GREEN d bl U7 daada dadada dadd oe 7 Bicolour LED wre lt d EE ERR O S ng ee BES Ke ERXD0 3 Ex EE x SCC 48 A 2 ERXDO REFCLK XI RXDO 2 ij 2H Gast 43 3V By xo RXD1 it H3 aji ERXDZ D4 A 1 MDDIS RXD2 ye 5 ot ERXD3 RSTO z RESET RXD3 7 8 RED 4 5 TXSLEWO N C His Di des 2 TXSLEW MDC 25 EMDC 2 1 2 cras 43 3V amp GND MDIO 7 A EMDIO E d A 43 3V DEFAULT SETTING FOR JUMPERS 5 uM d vena Lan 4 1 THRU 9 IS NOT FITTED 19 39 R2 180 GREEN o N C PWRDWN 5 R3 180 A jpa des 4 anD LED CFG1 MDDIS to p OF 12 ADDRO LED CFG2 L Bicolour LED ale 2 Lope o 13 ADDR1 LED CFG3 LZ ri H ADDR2 TEST 1oJP8 o2 181 ADDRS TESTO 244 P 7380 43 3V icJP9 16 33 43 3V OFS o2 ADDR4 PAUSE Sipe 433 A 22968332Z GD A RP9 ej SO OO Ot og xou ei M2Zo0 0000 Z0O0050C 2 1 JP10 e xr ed EOFFSSFFOOFFFFIFOD 3 1 2 d JP11 3 4 TXSLEWO RP10 R5 J J R6 5 2 PAUSE awas Ae 2S von d esdsd4ssuss323 100K SI EE 4x 4 7K DEFAULT SETTING FOR JUMPER 11 IS JUMPER AM bb ard 4 4 4x 4 7K mM FITTED BETWEEN PINS 1 amp 2 PAUSE DISABLED A 1 4 d EDI i 2 i 3 NOTFITTED IN JP12 4 3 3V 4 4 PRODUCTION TXSLEW1 e 2 A i a a i E RJ45 ETHERNET JTAG L1 c22 16 1 TX Hp 270pF TX 215 Ferrite Bead a an NE 2 RX 3 3 4 DEFAULT SETTINGS FOR JUMPERS 4 10 amp 12 50 1 Ferrite Bead_ 44 3 5 IS JUMPER FITTED BETWEEN PINS 1 amp 2 A 3 RX 6 8 7 8 Ile 8 NOTE PLACE COMPONENT
20. 13 0223 D SE 89 vidy 91dM STdy LIZLZGW Jgd VT Aen ZLZSIIOW or Ey H e H T 1 D I zd BIAN OZzdu 0823 30 ang Oldl mai lz gli C s 91H etu ain ano 38SM3 34 33S di S9NI113S MN3dWnP S03 Diet SdN Il H SC H ol 18 i ovo OZI g Cia eso Tdf Zdf Ede Tide ta ra DZ DZ vu Se EQ ee M ve T g An T ow 5 IT Uu a Di H Sa 60 ozi3 SEI ig WNIWYSL Ot LANYSHLA AWUITIXDU pa STi 8z md ezn SE 22 o 9T 1 n ME ths 8 2 11 sso tar SY 9dr Bdr 6c 6dr tdt Ztde sar olde Ody ZHWSZ n n
21. 16 baud 19200 server 192 0 0 1 client 192 0 0 2 gateway 0 0 0 0 netmask 255 255 255 0 filename test srec filetype S Record mac 00 CF 54 07 C3 01 2 32 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands STEP Step Over Usage STEP The STEP command can be used to step over a subroutine call rather than tracing every instruction in the subroutine The ST command sets a temporary breakpoint one instruction beyond the current program counter and then executes the target code The STEP command can be used to step over BSR and JSR instructions The STEP command will work for other instructions as well but note that if the STEP command is used with an instruction that will not return i e BRA then the temporary breakpoint may never be encountered and dBUG may never regain control Examples To pass over a subroutine call the command is step Chapter 2 Using the Monitor Debug Firmware 2 33 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands SYMBOL Symbol Name Management Usage SYMBOL lt symb gt lt a symb value gt lt r symb gt lt cllls gt The SYMBOL command adds or removes symbol names from the symbol table If only a symbol name is provided to the SYMBOL command then the symbol table is searched for a match on the symbol name and
22. 2C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Programmable Timer Counter Port C bits 15 0 are multiplexed with data bus signal D15 DO and are only available when the device is configured for 16 bit data bus mode using the WSEL signal at power up 1 5 Programmable Timer Counter The MCF5272 has four built in general purpose timers counters and a software watchdog timer All four timers are available to the user The signals for each timer are available on the 120 pin expansion connector J3 1 6 USB Controller The MCF5272 connects to the USB transceiver U26 or directly via JR1 using the on chip USB transceiver interface The MCF5272 functions as a device on the USB bus 1 7 On Board Ethernet The M5272C3 has an on board Ethernet controller Level One LXT971L operating at 10M bits sec or 100M bits sec The on board dBUG ROM monitor is programmed to allow a user to download files from a network to memory in different formats The current compiler formats supported are S Record COFF ELF or Image raw binary Refer to Appenix A for details on how to configure the board for network download 1 8 System Configuration The M5272C3 board requires only the following items for minimum system configuration The M5272C3 board provided Power supply 5V to 14V DC with minimum of 1 0 Amp e RS232C compatible terminal or a PC with terminal emulation softwa
23. 3 P24 RP25 RP26 RP27 RP28 3 1 RP3 RP4 RP6 RP8 RP19 Philips SMT 22x4 resistor packs RP5 RP7 Philips R2 R3 R4 180R R5 R27 R28 4K7 R7 R9 R10 R11 R12 R13 R14 R 50R1 15 D 2 M5272 User Manual SMT 50x4 resistor packs SMT 220 0805 resistor SMT 180 0805 resistors SMT 4K7 0805 resistors SMT 100K 0805 resistor 3 3 3 3 3 3 SMT 50 0805 resistors 2 3 4 5 6 7 8 3 SMT 22K1 0805 resistors For More Information On This Product Go to www freescale com Table D 1 MCF5272EVM_BOM Continued ID Lom Lm w p Reman mm Nveemesssaues blemer on Jemen SSC pe s mem m semen E e Ieren rares ton eh TP1 TP2 TP3 TP4 TP5 TP6 TP7 Hughes 100 103 Test Points TP8 TP9 TP10 U1 U2 U3 MC74LCX16245DT Maxim MAX708TCSA System reset amp voltage sense controller C wemsme msmrvaeser irae ES ES e pr Iaeneeng Teen Alternate Parts Samsung K7B403625M GalvantechGVT71128E36 ISSI IS61SF 12836 Micron MT58L128L36F1 GSI GS84036A IDT 71V3577 Cypress CY7C1345 Eer cat s CIE ES ES ES ES ES ES ES ES E T Appendix D Evaluation Board BOM D 3 For More Information On This Product Go to www freescale com D 4 M5272 User Manual For More Information On This Product Go to www freescale com
24. 3 Download to SDRAM If using serial or ethernet start the ROM Monitor first If using BDM viaa wiggler cable download first then start ROM Monitor by pointing the PC to 0x7FE00400 and run 4 In the ROM Monitor execute the upuser command 5 Move jumper JP13 to pin 2 connected to pin 3 and push the reset button S1 User code should now be running 3 2 Serial Communication Channels The M5272C3 offers a number of serial communications They are discussed in this section 3 2 1 MCF5272 UARTS The MCF5272 device has two built in UARTS each with its own software programmable baud rate generators One channel is the ROM Monitor to Terminal output and the other is available to the user The ROM Monitor programs the interrupt level for UARTO to Level 3 priority 2 and autovector mode of operation The interrupt level for UARTI is programmed to Level 3 priority 1 and autovector mode of operation The signals from these channels are available on expansion connector J3 The signals of UARTO and UART are also passed through the RS 232 driver receivers U23 amp U24 and are available on DB 9 connectors P3 and P4 Refer to the MCF5272 User s Manual for programming the UART s and their register maps 3 2 2 QSPI Module The QSPI Queued Serial Peripheral Interface module provides a serial peripheral interface with queued transfer capability It will support up to 16 stacked transfers at one Chapter 3 Hardware Description and Recon
25. 3 2 8 PLI Physical Layer Interface Module The physical layer interface PLI allows the MCF5272 device to connect at a physical level with external CODECs TDM controllers and other peripheral devices which utilize either the general circuit interface GCI or interchip digital link IDL physical layer protocols These PLI slots are unpopulated on the M5272C3 board and have been built on to the PCB to allow customers to add their own POTs Plain Old Telephone System and ISDN Integrated Digital Subscriber Network hardware The MCF5272 PLI has four ports port 3 0 connected through three physical interfaces numbered 0 1 2 and 3 A port can service read or write any 2B D channel Port 0 connects through interface 0 and Ports 1 and 2 both connect through interface 1 Port 3 can use either interface 1 or 3 In the case of interface 1 which connects multiple ports delayed frame sync generators are provided for each port These generators delay the active slots within a port with respect to a reference clock For more details on the PLI port configurations and programming these ports please refer to the MCF5272 User s manual All these siganls appear on expansion connector J3 as well Chapter 3 Hardware Description and Reconfiguration 3 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Connectors and Expansion Bus as PLI connectors J5 amp J6 3 3 Connectors and Ex
26. 30 C31 C32 0 001uF 2KV SMT Capacitors Rubycon 1000uF 35V SMT Capacitor C95 C96 AVX TPSE220M10RLM SMT Capacitors C112 C113 C114 C115 C116 C1 Size B 1uF TANT SMT Capacitors 17 C118 C119 C120 C121 C122 C123 11 D2 D5 D6 LST670 Red LED s 7 wo wo Appendix D Evaluation Board BOM D 1 For More Information On This Product Go to www freescale com Table D 1 MCF5272EVM_BOM Continued Qty Reference Function 1 F1 MULTICOMP MCHTE 15M 1 F1 Littelfuse F920 ND 5A 250V JP1 JP2 JP3 JP4 JP10 JP11 JP Harwin M22 2010305 3 way Jumpers 14 Fuse PSU Fast Acting Fuse 12 JP13 JP14 JP15 JP16 JP20 J P21 JP22 JP23 JP24 JP25 6 Ka JP5 JP6 JP7 JP8 JP9 JP17 JP1 Harwin M22 2010205 8 JP19 Berg 0 1 SIL Ethernet JTAG connector J2 3 AMP177983 5 120 way SMT Receptacle expansion connectors Thomas amp Betts 609 2627 Molex 89177A PCI socket Molex 89177A PCI socket J7 AMP 350211 1 CTCB1210 600 HC Molex DB9 connector 21 RP1 RP2 RP9 RP10 RP11 RP12 Philips SMT 4K7x4 resistor packs RP18 RP14 RP15 RP16 RP17 2 way Jumpers 1 USB PortB connector 1 1 BDM 26 way header PLI SOCKET 0 PLI SOCKET 1 5V amp HIGH VOLTAGE CONNECTOR Central Technology Ferrite Bead Siemens B82111 B C24 25uH INDUCTOR Switchcraft RAPC712 PSU barrel connector Augat 25V 02 2 way bare wire power connector r RS232 9way DType thru board 0 2 3 4 5 6 7 8 9 0 RP18 RP20 RP21 RP22 RP23 R 2 2 2 2 2 2 2 2 2 2
27. 5272 processor has built in logic and up to eight chip select pins CS 7 0 which are used to enable external memory and I O devices In addition there are RAS and CAS lines available for controlling DRAMs There are registers to specify the address range type of access and the method of TA generation for each chip select and the RAS pin These registers are programmed by the dBUG monitor to map the external memory and I O devices The M5272C3 uses the following signals to select external peripherals CS0 to enable the Flash ROM refer to Section 3 1 13 RASO CASO and CS7 to enable the SDRAM refer to Section 3 1 12 CS2 for the FSRAM not populated CS5 amp CS6 for the PLI I O space refer to section 3 2 8 The chip select mechanism of the MCF5272 processor allows the memory mapping to be defined based on the required memory space User Supervisor Program Data spaces All of the MCF5272 internal registers configuration registers parallel I O port registers UART registers and system control registers are mapped by the MBAR register at any 1 KByte boundary The MBAR register is mapped to 0x10000000 by the dBUG monitor For a complete map of these registers refer to the MCF5272 User s Manual The M5272C3 board has 4 MBytes of SDRAM installed Refer to Section 3 1 12 for a discussion of the SDRAM on the board The dBUG ROM monitor is programmed in one 3 4 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTI
28. 7V to 14V DC 2 Ground 1 9 4 Selecting Terminal Baud Rate The serial channel UARTO of MCF5272 is used for serial communication and has a built in timer This timer is used by the dBUG ROM monitor to generate the baud rate used to communicate with a serial terminal A number of baud rates can be programmed On power up or manual RESET the dBUG ROM monitor firmware configures the channel for 19200 baud Once the dBUG ROM monitor is running a SET command may be issued to select any baud rate supported by the ROM monitor Refer to Chapter 2 for the discussion of this command 1 9 5 The Terminal Character Format The character format of the communication channel is fixed at power up or RESET The default character format is 8 bits per character no parity and one stop bit It is neccessary to ensure that the terminal or PC is set to this format 1 9 6 Connecting the Terminal The board is now ready to be connected to a terminal Use the RS232 male female DB 9 serial cable to connect the PC to the M5272C3 The cable has a 9 pin female D sub terminal connector at one end and a 9 pin male D sub connector at the other end Connect the 9 pin male connector to P3 connector on M5272C3 Connect the 9 pin female connector to one of the available serial communication channels normally referred to as COMI COM2 etc on the IBM PC or compatible Depending on the kind of serial connector on the back of your PC the connector on the PC may be a
29. Board ize Document Number Rev 14 ale Monday March 19 2001 heat 9 of 14 Go to www freescale com CPU OSCILLATOR LAYOUT FOOTPRINT FOR 8 amp 14 PIN DIL OSC PACKAGES 3 3 8 3V 3 3V U15 ug 3 3V Clock Driver 14 vcc wei U16 470 il 16 8 XTAL_OUT XTAL_IN CLK t Enable2 Enablei GND A 3 1 GND1 BCLK5 43 3V HARD RESET A VOLTAGE D5 BCLK CPU lt alt 2E n BOLD Ds 3o OSC66MHZ SENSE CONTROLLER r BCLK FSRAM C sl sls 8 Aere CNDA BET 48 3V SOCKETED x 7 Bre t H GND2 BCLK3 re EN Utz RED RESET LED BCLK_PAL 7 RP19 4x 22 BCLK2 VDD2 2 WR e o O MR RESET oh VCC RESET ES e RESET Motorola MPC905D GND NC KS11R23CQD 4 SN BS Ls RESET NOTE minimise track lengths between U16 amp RP19 MAX708TCSA DC Voltage Input range 5V to 14V P1 Power Jack Connector 2 1mm dia 43 3V gv Switchcraft RAPC712 i U18 LM2596S 3 3 R17 2 way Bare Wire 0 R28 R18 P2 power Connector 3 3V Regulator 47K 270 F1 L3 1 2 Le eee 3 3V G a K K gt 3 3V adi p 2 25 25uH ys 2 34 Bet blow 5 oworr6 re 4
30. Board Computer e M5272C3 User s Manual this document One RS232 communication cable One BDM Background Debug Mode wiggler cable e ColdFire Programmers Reference Manual e A selection of Third Party Developer Tools and Literature NOTE Avoid touching the MOS devices Static discharge can and will damage these devices Once you have verified that all the items are present remove the board from its protective jacket and anti static bag Check the board for any visible damage Ensure that there are no broken damaged or missing parts If you have not received all the items listed above or they are damaged please contact Matrix Design immediately for contact details please see the front of this manual 1 9 2 Preparing the Board for Use The board as shipped is ready to be connected to a terminal and power supply without any need for modification Figurel 4 Jumper Locations shows the position of the jumpers and connectors 1 9 3 Providing Power to the Board The board accepts two means of power supply connection either P1 or P2 Connector P1 Chapter 1 M5272C3 Board 1 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Installation And Setup is a 2 1mm power jack and P2 a lever actuated connector The board accepts 7V to 14V DC at 1 5 Amp via either one of the connectors Table 1 1 Power Supply Connections on P2 Contact Number Voltage 1
31. CE For More Information On This Product Go to www freescale com The Processor and Support Logic AMD Am29PL160BC XX Flash ROM which occupies 2 MBytes of the address space The first 256 KBytes i e the first sector are used by ROM Monitor and the remainder is left for the user Refer to section 3 1 13 Table 3 1 shows the M5272C3 memory map Table 3 1 The M5272C3 Memory Map System Integration Module SIM registers 20000000 20000FFF SRAM internal access 1 clock 30000000 3007FFFF CS2 External FSRAM not fitted 2 1 1 1 50000000 5001 FFFF CS5 PLI Connector I O J5 max number of wait states is 30 60000000 6001 FFFF CS6 PLI Connector I O J6 max number of wait states is 30 FFE00000 FFFFFFFF CS0 2M Flash ROM 8 7 7 7 Not installed SRAM footprint accepts Motorola s MCM69F737TQ chip and any other SRAM with the same electrical specifications and package alternatives are shown on the schematics Appendix dBUG Monitor does not program the CS5 CS6 chip selects addresses shown are for illustrative purposes only Connectors J5 and J6 are not populated on the evaluation board All of the unused area of the memory map is available to the user 3 1 9 Reset Vector Mapping After reset the processor attempts to read the initial stack pointer and program counter values from locations 00000000 amp 00000007 the first eight bytes of memory space This requires the board to have a non volatile memory devi
32. CIO SPI CS1 PCH SPI CS1 FSCO FSRO FSC1 FSR1 DFSC1 DOUTO USRT2TXD Doum DINO USRT2RXD Din DCLO USRT2CLK DCL1 GEN_DCL_OUT DEFAULT SETTING FOR JUMPER 23 IS BETWEEN PINS 1 amp 2 DEFAULT SETTING FOR JUMPER 24 IS BETWEEN PINS 1 amp 2 SPI CS1 SPI CS3 DOUT3 PCIO SPI Ce Po SPI CS2 U13 Ut4 TR voc A0 OE A1 Bo A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 gt MC74LCX24DT TR voc A0 OE A1 Bo A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 gt MC7ALOX24EDT Ax 4 7K PLI Socket 0 Ax 4 7K PLI Socket 1 css RD CS6_RD B_D 0 31 4x 47K 4x 4 7K 45V 43 3V 35V A ov NOTE Rev 1 2 to Rev 1 3 design revision as a C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 Can C91 C134 result of EMC CE testing C134 was added to filter 5V amp HIGH VOLTAGE CONN inF inF 1nF inF 1nF inF inF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 680pF high frequency clock harmonic noise near U16 See schematic sheet 10 NOTE all volatge supplies on J5 must be T A y 2 x i x y bd d regulated and stable 5V for the whole board is solely suppled via connector J7 For More Information On This Proeduct B oa C MCF5272 PLI Connectors M SPS SESG HESD ColdFire Group Title M5272C3 Evaluation
33. DBAO A10_PRECHG 3 3V U21 VDD DQO DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQML WE CAS RAS CS BA A10 AO Al A2 E VDD A m II fe fe fs P MT48LC1M16A1TG S 0 22 SDRAM Upper 16 bit Word 0 22 SDRAM Lower 16 bit Word M SPS SESG HESD ColdFire Group itle M5272C3 Evaluation Board ize Document Number A MCF5272 SDRAM Date Monday March 19 2001 heet or More Information On This Go to www freescale com RS232 Transceiver 113 1uF TANT C114 1uF TANT C115 1uF TANT C116 1uF TANT USRT1TXD 40 USRT1RXD lt USRTIRTS gt USRT1CTS C117 1uF TANT Motorola MC145583VF TERMINAL PORT 9 WAY D TYPE Female RS232 Transceiver 119 1uF TANT C120 1uF TANT C122 1uF TANT DOUTO USRT2TXD DINO USRT2RXD USRT2RTS INT5 USRT2CTS SPI CS2 C123 1uF TANT Motorola MC145583VF AUXILARY PORT 9 WAY D TYPE Female M SPS SESG HESD ColdFire Group itle M5272C3 Evaluation Board ize Document Number A MCF5272 Serial Ports Date Monday March 19 2001 Go to www freescale com USB OSCILLATOR LAYOUT FOOTPRINT FOR 8 amp 14 PIN DIL OSC PACKAGES 3 3V JP25 gt USBEXTCLK ii USB MODE DEFAULT JUMPER 25 SETTING BETWEEN PINS 1 amp 2 DEFAULT JUMPER 26 SETTING IS NOT FITTED 5V WILL ONLY BE SUPPLIED VIA J7 ON SCHEMATIC SHEET 9 FOR OPERATION AS A USB HUB NORMAL OPERATION IS AS A USB DE
34. Date Monday March 19 2001 Go to www freescale com wo pare 0 olo ive NOTE Alternative FSRAM s with the same PCB footprint and functionality are Samsung K7B403625M Cypress CY7C1345 IDT 71V3577 amp Micron MT58L128L36F1 ggggggg B A o 22 erh BCLK FSRAM B D 0 31 lt B D n C72 1nF M SPS SESG HESD ColdFire Group itle M5272C3 Evalution Board ize Document Number A MCF5272 FSRAM Date Monday March 19 2001 Go to www freescale com DRESETEN lt _ gt gt _2 e e BCLK CPU CPU Ex CLK C e USBEXTCLK JP14 SDRAM RESET DEFAULT JUMPER POSITION BETWEEN PINS 1 amp 2 SDRAM RESET JP15 MCF5272 TEST MODE DEFAULT JUMPER POSITION BETWEEN PINS 1 amp 2 NORMAL OPERATION JP16 DEBUG MODE DEFAULT BDM DEFAULT JUMPER POSITION BETWEEN PINS 1 amp 2 BDM MODE JP20 CPU CLOCK SELECTOR DEFAULT JUMPER POSITION BETWEEN PINS 1 amp 2 CPU OSC MODE or More Information On This PST o 3 O debugging cable can be used with the MCF5272 processor NOTE Rev 1 2 to Rev 1 3 design revision as a result of EMC CE testing C129 was added to filter BDM clock noise DDATA 0 3 DEFAULT FOR JP17 WSEL IS FITTED 0 DEFAULT FOR JP18 BUSWO IS FITTED 0 DEFAULT FOR JP19 BUSW1 IS NOT FITTED 1 BUSW1 BUSWO DATA BUS WIDTH 32 BITS 8 BITS 16 BITS RESERVED DO NOT USE CS0 BUS WIDTH 32 BITS 16 BITS Go to www freescale
35. HANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands RM Register Modify Usage RM reg data The RM command modifies the contents of the register reg to data The value for reg is the name of the register and the value for data may be a symbol name or it is converted according to the user defined radix normally hexadecimal dBUG preserves the registers by storing a copy of the register set in a buffer The RM command updates the copy of the register in the buffer The actual value will not be written to the register until target code is executed Examples To change register DO on MC68000 and ColdFire to contain the value 0x1234 the command is rm DO 1234 Chapter 2 Using the Monitor Debug Firmware 2 29 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands RESET Reset the Board and dBUG Usage RESET The RESET command resets the board and dBUG to their initial power on states The RESET command executes the same sequence of code that occurs at power on If the RESET command fails to reset the board adequately cycle the power or press the reset button Examples To reset the board and clear the dBUG data structures the command is reset 2 30 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands SET Set Configu
36. M5272C3 User s Manual M5272C3UM D Rev 1 4 08 2001 For More Information On This Product o to www freescale com LIMITED WARRANTY Matrix Design warrants this product against defects in material and workmanship for a period of sixty 60 days from the original date of purchase This warranty extends to the original customer only and is in lieu of all other warrants including implied warranties of merchantability and fitness In no event will the seller be liable for any incidental or consequential damages During the warranty period Matrix Design will replace at no charge components that fail provided the product is returned properly packed and shipped prepaid to Matrix Design at address below Dated proof of purchase such as a copy of the invoice must be enclosed with the shipment We will return the shipment prepaid via UPS This warranty does not apply if in the opinion of Matrix Design the product has been damaged by accident misuse neglect misapplication or as a result of service or modification other than specified in the manual by others Please send the board and cables with a complete description of the problem to Matrix Design amp Manufacturing Inc 2914 Montopolis Drive 290 Austin TX 78741 Phone 512 385 9210 Fax 512 385 9224 http www cadreiii com For More Information On This Product Go to www freescale com CE The M5272C3 Evaluation Board is CE certified For More Information On Th
37. P stack pointer actually refers to general purpose address register seven A7 2 2 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Operational Procedure 2 2 Operational Procedure System power up and initial operation are described in detail in Chapter 1 This information is repeated here for convenience and to prevent possible damage 2 2 1 System Power up e Be sure the power supply is connected properly prior to power up Make sure the terminal is connected to TERMINAL P4 connector Turn power on to the board Chapter 2 Using the Monitor Debug Firmware 2 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Operational Procedure Figur 2 1shows the dUBG operational mode INITIALIZE COMMAND LINE INPUT FROM TERMINAL NO EXECUTE YES COMMAND FUNCTION DOES COMMAND LINE CAUSE USER PROGRAM EXECUTION YES v JUMP TO USER PROGRAM AND BEGIN EXECUTION Figure 2 1 Flow Diagram of dBUG Operational Mode 2 2 2 System Initialization The act of powering up the board will initialize the system The processor is reset and dBUG is invoked dBUG performs the following configurations of internal resources during the initialization 2 4 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Inform
38. R m D6 Mis D8 270 2 U19 wv Augat 25V 02 C92 c93 D7 Z C94 o d SS MBRS340T3 T C95 T C96 C97 UNO 2 RESIN x 0 1uF in H OOOUF 35V 220u 10V 220u 10V 0 1uF 8 MBRS340T3 KS11R22CQD vee r7 RED INT6 LED al SENSE E ABORT INT6 RESET 5 4 gt DGNT1 INT6 SS a E x CT M 8 RESET S GREEN POWER LED SEA Ss CONTROL H 4 onp TLC7733ID Debounced INT6 Signal M SPS SESG HESD ColdFire Group Title M5272C3 Evaluation Board Size Document Number Rev B MCF5272 PSU Reset amp Clocks 1 4 Date Monday March 19 2001 Bheet 10 of 14 1 For More Information On This Product Go to www freescale com USRT2RTS INT5 RSTO DSO DTEA DIN3 INT4 DACK HIZ CS4 DGNT1 INT6 CS5 TC BYPASS CS6 CS7 NOTE U20 is socketed to allow c di 0E C gt d BCLK PAL gt UR gray ee TRANSFER ERROR ACK OUTPUT ENABLE Re TP3 TP4 CS0 WE 1 WRITE ENABLE CHIP SELECT 0 TP5 TP6 C87 C82 CHIP SELECT 2 CHIP SELECT 7 TP7 TP8 CPU Ext CLK SDCLK lt BD CS CPU CLOCK SDRAM CLOCK TP9 TP10 NOTE Place TP9 amp TP10 at the corners of the PCB to allow easy connection of scope probe ground leads d 1 oi GROUND GROUND M SPS SESG HESD ColdFire Group itle M5272C3 Evaluation Board ize Document Number A MCF5272 Pull ups Test points and PAL Date Monday March 19 2001 heet or More Information On This Go to www freescale com BS2 SDWE CASO RASO CS7 S
39. RR DFSC3 FSC1 FSR1 DF 107 ces WR CS5 WR CS1 DGNT1 INT6 OUT1 112 op DIN1 um CS3 DOUT 113 LO E NNNM DCL1 GEN DC DREQ1 EMDC 110 EMDIO L_OUT ES 3 3 2 The Debug Connector J4 The MCF5272 processor has a Background Debug Mode BDM port which supports Real Time Trace Support and Real Time Debug The signals which are neccessary for debug are available at connector J4 Figure 3 1 shows the J4 Connector pin assignment 3 14 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com DEVELOPER RESERVED GND GND RESET 3 3V GND PST2 PSTO DDATA2 DDATAO MOTOROLA RESERVED GND 3 3V N ow o ob DY gt 13 ua gt j5 ie kan 7 ig a J 19 20 I 4 gt 21 22 lt gt 23 o4 ba 25 o6 Connectors and Expansion Bus BKPT DSCLK DEVELOPER RESERVED DSI DSO PST3 PST1 DDATA3 DDATA1 GND MOTOROLA RESERVED CPU_CLK DTEA Figure 3 1 The J4 Connector pin assignment Chapter 3 Hardware Description and Reconfiguration 3 15 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Appendix A Configuring dBUG for Network Downloads The dBUG module has the ability to perform downloads over an Ethernet network using the Trivial File Transfer Protocol TFTP Prior to using this feature sev
40. S L1 C23 thru C26 C24 C25 R8 10nF AS CLOSE AS POSSIBLE TO THE VCCA PINS 0 1uF inF 22 1K 1 R9 l 11 6 R10 R11 JS1 ON U7 50 1 50 1 50 1 R12 R13 10 H 50 1 50 1 ETHERNET CONNECTOR SIM Ge JC 9 8 gt 270pF Bis RIS 50 1 50 1 SE HALO TG110 S050N5 C29 C30 C31 T T t T t T t 10nF 0 001uF 2KV 0 001uF 2KV C32 M SPS SESG HESD ColdFire Group C23 C26 C33 C34 C35 C36 C37 C38 0 001uF 2KV 0 1uF 1nF 0 1uF 0 1uF 0 1uF 1nF 1nF 1nF NOTE each VCC IO amp D to have 0 1uF and 1nF capacitors Title placed close to each power pin on U7 E lL m M5272C3 Evaluation Board 1 S S j x 7 i 7 Bize Document Number Rev B MCF5272 Ethernet 100 10BaseT 1 4 ate riday Apri 00 eet o 4 b Friday April 27 2001 Bhi 4 fu cH 5 4 3 2 1 For More Information On This Product Go to www freescale com CS 0 7 BS 0 3 DDATA 0 3 TH ET z
41. VICE MODE VCC PA5 USB_TXEN OE VMO FSEO X PAS USB TN Po x PA6 USBRXD VPO C jPAO USB TP n dv ER JP26 PA1 USB RP D PA2 USB_RN D SY USB POW PA4 USB SUSP SUSPND SPEED GND NC Default setting for the USBLineH PDIUSBP11APW signal is R21 fitted R24 removed 1 5K USB PORT B USB TRANSCEIVER R22 33 4 1 2 3 4 C124 JR1 10nF Default setting for the USBLineL signal is R25 fitted R26 removed I USBLineL gt USBLineH gt C125 C126 C127 C128 SPS SESG HESD ColdFire Group 0 1uF 0 1uF 1nF 1nF itle M5272C3 Evaluation Board ize Document Number Rev A MCF5272 USB Interface 1 4 Date Monday March 19 2001 heet 14 of 14 1 25 For More Information On This Product 2 Go to www freescale com Appendix D Evaluation Board BOM Table D 1 MCF5272EVM_BOM ID x9 RE 29 C1 C2 C3 C8 C9 C10 C11 C12 SMT Decoupling Capacitors C23 C24 C33 034 C35 C55 C56 C57 C69 C70 C71 C92 C97 C9 75 1 9 C107 C108 C109 C110 C111 C 125 C126 2 C4 C5 C6 C7 C13 C14 C15 C16 SMT Decoupling Capacitors C17 C18 C19 C25 C26 C36 C37 038 039 C40 C41 042 C43 C4 4 C45 C46 C47 C48 C49 C50 C 51 C52 C53 C54 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C72 C73 C74 C75 C76 C7 7 C78 C79 C80 C81 C82 C83 C 84 C85 C86 C87 C88 C89 C90 C91 C93 C98 C100 C101 C102 C103 C104 C105 C106 C127 C1 28 C129 C20 C27 C29 C124 10nF SMT Capacitors C22 C28 270pF COG or NPO only SMT Capacitors AR NI o NI ine C
42. a USB 48MHz oscillator U25 which feeds the USBEXTCLK signal on MCF5272 to clock the USB module therein 3 1 5 Watchdog Timer The duration of the Watchdog is selected by the REF 15 1 bits in the Watchdog Reset Reference Register WRRR The dBUG monitor initialises this register with the value OxFFFE which provides the maximum time out period but dBUG does NOT enable the watchdog timer 3 1 6 Interrupt Sources The ColdFire family of processors can receive seven levels of interrupt priorities When 3 2 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com The Processor and Support Logic the processor receives an interrupt which has a higher priority than the current interrupt mask in the status register it will perform an interrupt acknowledge cycle at the end of the current instruction cycle This interrupt acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the device should provide the proper vector number to indicate where the service routine for this interrupt level is located If the source of interrupt is not capable of providing a vector it s interrupt should be set up as an autovector interrupt which directs the processor to a predefined entry in the exception table refer to the MCF5272 User s Manual The processor goes to an exception routine via the exception table This table is store
43. a prp 2 2 3 4 3 4 CPU_Ext_CLK 3 4 RESET DSO 3 4 DSI BSO t 3 5 er DRESETEN ze is 6 8 BKPT e 7 8 H es CPU_CLK 7 He DSCLK ie mi ide 1HE DTEA cen OE Hi 12 ce TEST fa it 12 m MTMOD CS2 15 19 14 18 Bees DDATAO 15 13 1446 DDATA1 3 3V C54 12115 16 18 CS5 DDATA2 17115 6 1g DDATA3 CS6 19 17 18 20 PSTO 19 17 18 20 19 20 PSTD 19 20 2121 22 22 DACK HIZ 21 21 22 22 TC BYPASS 23153 24 4 23153 24 H4 A10 PRECHG 25 125 26 26 WE PAO USB TP 25 25 26 H PA1 USB RP SDBAO 27 127 28 8 SDBA1 PA3 USB TN 227 27 93 2B PA2 USB RN RASO 29 29 30 H2 Caen PA4 USB_SUSP 29129 30 H32 PA5 USB_TXEN SDCLK 31 31 32 32 SDWE gg PAG USBRXD 31231 32 32 RSTO SDCLKE 33 38 34 34 Do 33 733 w i 25 36 FSCO FSRO 35135 36 3 DGNTO 3 38 DCLO USRT2CLK 32137 38 38 DINO USRT2RXD i2 42 USRT2CTS SPI CS2 32139 40 42 USRT2RTS INT5 4l 42 DOUTO USRT2TXD 4l 41 42 42 DREQO 44 SPI CS1 43143 44 H4 46 451 45 46 46 DFSC2 48 DFSC3 47147 4g 48 FSC1 FSR1 DFCS1 50 DCL1 GEN_DCL_OUT 49 49 50 Q DREQ1 52 DGNT1 INT6 Sits 52 82 DOUT 54 DIN1 53453 54 34 SPI CS3 DOUT3 56 DIN3 INT4 55 55 56 36 USRT1TXD 58 USRT1RXD 52157 58 38 USRTICTS 60 USRTIRTS 59 59 60 82 USRT1CLK i Hie e oe USBEXTCLK 63 64 PB5 TA E i 65 e e PB6 67 e USBLineH i TINI Sie 70 a USBLineL TOUTI 7 72 ANTI INT2 7 INT3 S 73 74 a 75 e WSEL A 7 77 78 2 QSPI_DIN ER BUSW1 2 79 80 22 BUSWO a2 8181 go 82 PWMOUT1 84 PWMOUT2 TOUT2 83 85 gq H4 PWMOUTS TIN2 i i 85 86 BE
44. ained by dBUG To change the default filename use the command set filename filename When using the Ethernet network for download either S record COFF ELF or Image files may be downloaded A default filetype for network downloads is maintained by dBUG as well To change the default filetype use the command set filetype lt srecordlcofflelflimage gt Continuing with the above example the compiler produces an executable COFF file a out This file is copied to the tftp boot directory on the server with the command rcp a out santafe tftp boot a out Change the default filename and filetype with the commands A 2 M5272 User Manual For More Information On This Product Go to www freescale com Troubleshooting Network Problems set filename a out set filetype coff Finally perform the network download with the dn command The network download process uses the configured IP addresses and the default filename and filetype for initiating a TFTP download from the TFTP server A 3 Troubleshooting Network Problems Most problems related to network downloads are a direct result of improper configuration Verify that all IP addresses configured into dBUG are correct This is accomplished via the show command Using an IP address already assigned to another machine will cause dBUG network download to fail and probably other severe network problems Make certain the client IP address is unique for the board Ch
45. al which is fed to the MCF5272 reset RSTI The RSTI signal is an open collector signal and so can be wire OR ed with other reset signals from additional peripherals dBUG configures the MCF5272 microprocessor internal resources during initialization The instruction cache is invalidated and disabled The Vector Base Register VBR contains an address which initially points to the Flash memory The contents of the exception table are written to address 00000000 in the SDRAM The Software Watchdog Timer is disabled Bus Monitor enabled and internal timers are placed in a stop condition The interrupt controller registers are initialised with unique interrupt level priority pairs A memory map for the entire board can be seen in Table 3 1 3 1 3 HIZ Signal The assertion of the HIZ signal during reset forces all output drivers to a high impedance state On the M5272C3 board the high impedance signal is pulled to 3 3V via a 4 7K pull up resistor ensuring that the output drivers will not be in a high impedance state during reset HIZ is also available to the user on connector J2 3 1 4 Clock Circuitry The M5272C3 board uses a 66MHz oscillator U15 on schematics to provide the clock to the clock driver chip U16 The clock driver provides buffered clocks for the MCF5272 processor U5 the FSRAM U9 not fitted and the PAL U20 In addition to the 66MHz oscillator there is also a 25MHz oscillator U6 which feeds the Ethernet chip U7 and
46. ample of the output from this command Type Start End Port Size SDRAM 0x00000000 0x003FFFFF 32 bit Vector Table 0x00000000 0x000003FF 32 bit USER SPACE 0x00020000 0x003FFFFF 32 bit BAR 0x10000000 0x100003FF 32 bit Internal SRAM 0x20000000 0x20000FFF 32 bit External SRAM 0x30000000 0x3007FFFF 32 bit Flash OxFFEOO0000 OxFFFFFFFF 16 bit Chip Selects CSO Flash CS1 not in use CS2 Ext SRAM CS3 not in use CS4 not in use CS5 not in use CS6 not in use CS7 SDRAM Chapier 2 Using the Monitor Debug Firmware 2 27 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands RD Register Display Usage RD reg The RD command displays the register set of the target If no argument for reg is provided then all registers are displayed Otherwise the value for reg is displayed dBUG preserves the registers by storing a copy of the register set in a buffer The RD command displays register values from the register buffer Examples To display all the registers and their values the command is rd To display only the program counter rd pe Here is an example of the output from this command PC 00000000 SR 2000 t Sm 000 xnzvc An 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01000000 Dn 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 2 28 M5272C3 User s Manual PRELIMINARY SUBJECT TO C
47. are and hardware tools details for some of which may be found in this kit on CD ROM 1 14 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Chapter 2 Using the Monitor Debug Firmware The M5272C3 single board computer has a resident firmware package that provides a self contained programming and operating environment The firmware named dBUG provides the user with monitor debug interface inline assembler and disassembly program download register and memory manipulation and I O control functions This Chapter is a how to use description of the dBUG package including the user interface and command structure 2 1 What Is dBUG dBUG is a traditional ROM monitor debugger that offers a comfortable and intuitive command line interface that can be used to download and execute code It contains all the primary features needed in a debugger to create a useful debugging environment dBUG is a resident firmware package for the ColdFire family single board computers The firmware stored in one 1Mx16 Flash ROM device provides a self contained programming and operating environment dBUG interacts with the user through pre defined commands that are entered via the terminal These commands are defined in Section 2 4 Commands The user interface to dBUG is the command line A number of features have been implemented to achieve an easy and intuitive command l
48. ask This is the network address mask to determine if use of a gateway is required This field must be properly set Your local network administrator will have this information filename This is the default filename to be used for network download if no name is provided to the DN command filetype This is the default file type to be used for network download if no type is provided to the DN command Valid values are srecord coff and elf mac This is the ethernet Media Access Control MAC address a k a hardware address for the evaluation board This should be set to a unique value and the most significant nibble should always be even Examples To set the baud rate of the board to be 19200 the command is set baud 19200 NOTE See the SHOW command for a display containing the correct formatting of these options Chapter 2 Using the Monitor Debug Firmware 2 31 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands SHOW Show Configurations Usage SHOW lt option gt The SHOW command displays the settings of the user configurable options within dBUG When no option is provided SHOW displays all options and values Examples To display all options and settings the command is show To display the current baud rate of the board the command is show baud Here is an example of the output from a show command dBUG gt show base
49. ation On This Product Go to www freescale com Operational Procedure The instruction cache is invalidated and disabled The Vector Base Register VBR points to the Flash However a copy of the exception table is made at address 00000000 in SDRAM To take over an exception vector the user places the address of the exception handler in the appropriate vector in the vector table located at 0x00000000 and then points the VBR to 0x00000000 The Software Watchdog Timer is disabled and internal timers are placed in a stop condition Interrupt controller registers initialized with unique interrupt level priority pairs Please refer to the dBUG source files on theColdFire website www motorola com coldfire for the complete initialization code sequence After initialization the terminal will display Hard Reset DRAM Size 4M Copyright 1995 2001 Motorola Inc All Rights Reserved ColdFire MCF5272 EVS Firmware v2e 1a 1a Build XXX on XXX Enter help for help dBUG gt If you did not get this response check the setup refer to Section 1 10 System Power Up and Initial Operation Other means can be used to re initialize the M5272C3 Computer Board firmware These means are discussed in the following paragraphs 2 2 2 1 Hard RESET Button Hard RESET S1 is the button Depressing this button causes all processes to terminate resets the MCF5272 processor and board logic and restarts the dBUG firmware Pressing the RESET button wou
50. ayed If no lt width gt is specified the default of word sized data is used Memory display starts at the address begin If no beginning address is provided the MD command uses the last address that was displayed If no ending address is provided then MD will display memory up to an address that is 128 beyond the starting address This command first aligns the starting address for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To display memory at address 0x00400000 the command is md 400000 To display memory in the data section defined by the symbols data_start and data_end the command is md data_start To display a range of bytes from 0x00040000 to 0x00050000 the command is md b 40000 50000 To display a range of 32 bit values starting at 0x00040000 and ending at 0x00050000 md 1 40000 50000 Chapter 2 Using the Monitor Debug Firmware 2 25 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands MM Memory Modify Usage _MM lt width gt addr data The MM command modifies memory at the address addr The value for addr may be an absolute address specified as a hexadecimal value or a symbol name Width specifies the size of the data that is modified If no lt width gt is specified the default of word siz
51. ce in this range with the correct information stored in it In some systems however it is preferred to have RAM starting at address 00000000 The MCF5272 processor chip select zero CSO responds to any accesses after reset until the CSMRO is written Since CSO the global chip select is connected to the Flash ROM U8 the Flash ROM initially appears at address 00000000 which provides the initial stack pointer and program counter the first 8 bytes of the Flash ROM The initialisation routine then programs the chip select logic locates the Flash ROM to start at SFFE00000 and configures the rest of the internal and external peripherals 3 1 10 TA Generation The processor starts a bus cycle by asserting CSx with other control signals The processor then waits for a transfer acknowledgment TA either from within Auto acknowledge Chapter 3 Hardware Description and Reconfiguration 3 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com The Processor and Support Logic AA mode or from the externally addressed device before it can complete the bus cycle TA is used to indicate the completion of the bus cycle It also allows devices with different access times to communicate with the processor properly i e asynchronously The MCF5272 processor as part of the chip select logic has a built in mechanism to generate TA for all external devices which do not have the capabilit
52. cified as a hexadecimal value or a symbol name When the GT command is executed all breakpoints are inserted into the target code and the context is switched to the target program Control is only regained when the target code encounters a breakpoint illegal instruction or other exception which causes control to be handed back to dBUG Examples To execute code up to the C function bench the command is gt bench Chapter 2 Using the Monitor Debug Firmware 2 19 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands IRD Internal Register Display Usage IRD lt module register gt This command displays the internal registers of different modules inside the MCF5272 In the command line module refers to the module name where the register is located and register refers to the specific register to display The registers are organized according to the module to which they belong The available modules on the MCF5272 are CS DMAO DMA1 DMA2 DMA3 DRAMC PP MBUS SIM TIMERI TIMER2 UARTO and UARTI Refer to the MCF5272 user s manual for more information on these modules and the registers they contain Example ird sim rsr 2 20 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands IRM Internal Register Modify Usage IRM module register data This command modif
53. cimal by default Example To verify that the data starting at 0x20000 and ending at 0x30000 is identical to the data starting at Ox80000 the command is be 20000 80000 10000 Chapier 2 Using the Monitor Debug Firmware 2 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands BF Block Fill Usage BF lt width gt begin end data inc The BF command fills a contiguous block of memory starting at address begin stopping at address end with the value data lt Width gt modifies the size of the data that is written If no lt width gt is specified the default of word sized data is used The value for addresses begin and end may be an absolute address specified as a hexadecimal value or a symbol name The value for data may be a symbol name or a number converted according to the user defined radix normally hexadecimal The optional value lt inc gt can be used to increment or decrement the data value during the fill This command first aligns the starting address for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To fill a memory block starting at 0x00020000 and ending at 0x00040000 with the value 0x1234 the command is bf 20000 40000 1234 To fill a block of memory starting at 0x00020000 and ending a
54. com M SPS SESG HESD ColdFire Group D itle ize A ate 23 25 BDM Header C129 47pF DDATA 0 3 NOTE 4 7K pull up resistors are used on signals BKPT DSCLK DSI DSO RESET amp DTEA See page 11 of the schematics IMPORTANT NOTE THE RSTO SIGNAL MUST BE USED TO DRIVE THE OUTPUT ENABLE PINS OF U10 TO ALLOW THE WSEL BUSWO amp BUSW1 SIGNALS TO BE LATCHED CORRECTLY BY THE MCF5272 U5 MC74LCX541DT M5272C3 Evaluation Board Document Number MCF5272 Background Debug Mode BDM Port amp Reset Config Monday March 19 2001 heet 8 of 14 NOTE PLI Sockets 0 amp 1 are not populated during assembly B D 9 31 PWMOUT2TOUT2 35V 70V 5V 3 3V 70V 35V Utt 35V 70V45V 3 3V 483V 5V 70V 35V u12 vec OE o0 Do O1 D1 02 D2 O3 D3 04 D4 O5 D5 O6 D6 O7 D7 CP GND vec OE O0 DO ot D1 o2 D2 03 D3 O4 D4 O5 D5 O6 D6 07 D7 CP GND MC74LCX574DT MC74LCX574DT PWMOUTS TIN2 CS5_WR PWMOUTS TIN2 Cp WR PWMOUT1 PWMOUT1 PWMOUT2TOUT2 USRT2CTS SPI CS2 SPI CS1 DEFAULT SETTING FOR JUMPER 21 IS BETWEEN PINS 1 amp 2 DEFAULT SETTING FOR JUMPER 22 IS BETWEEN PINS 1 amp 2 USRT2RTS INTS HO INT3 INT3 WSEL QSPI_DIN BUSW1 USRT2CTS SPI CS2 DGNTO DGNT1 INT6 DREQO DREQ1 P
55. d g Oat HES 65009 og a 23 1 A 0 22 3225 B a CS 0 7 o x CS 0 7 PB5 TA DTEA DSI DSCLK BKPT RSTO RESET DACKHI DSO M ANT 1 3 OE WE DIN3 INT4 Cold Fire amp MCF5272 OTN INTE O l re DGNT1 INT6 E ti B d TC BYPASS Seg EE CSL B_D 0 31 CS 0 7 CS0 CS2 BSO BS1 BS2 BS3 B oa B DJ031 B A 0 22 BCLK FSRAM Flash FSRAM BS 0 3 penal Sheet 2 Buffers BS3 Sheet 11 CPU Ext CLK SDCLK BS3 BS2 BS1 PB5 TA DTEA DSI DSCLK BKPT RSTO RESET DACK HIZ DSO ANTI INT2 INT3 DIN3 INT4 USRT2RTS INT5 DGNT1 INT6 TC BYPASS OE WE BD_CS PU_FLASH BYTE PU FLASH A19 ERXD 0 3 ETXD 0 3 ECRS ECOL EMDC EMDIO ERXCLK ERXDV ETXCLK ETXEN ETXERR ERXERR RSTO INT2 2 1 0 BSO BCLK PAL Cen RD CS5 WR CS6_RD CS6 WR Pull ups Test Points amp PAL Ethernet M SPS SESG HESD ColdFire Group Title M5272C3 Evaluation Board ize Document Number Rev Cc Hierarchical Overview 14 ate Monday March 19 2001 beet 1 of 14 H Go to www freescale com D 0 31 lt gt C gt B Dina 23 od w e 0 22 2 LB A 0 22 OQ AIOUuJuauagdgagdguguauuduuodoc o
56. d in the Flash EEPROM The address of the table location is stored in the VBR The dBUG ROM monitor writes a copy of the exception table into the RAM starting at 00000000 To set an exception vector the user places the address of the exception handler in the appropriate vector in the vector table located at 00000000 and then points the VBR to 00000000 The MCF5272 microprocessor has six external interrupt request lines INT 6 1 three of which INT 6 4 are multiplexed with other functions The interrupt controller is capable of providing up to 32 interrupt sources These sources are e External interrupt signals INT 6 1 Software watchdog timer Four general purpose timers Two UART s Ethernet controller PLI Physical Layer Interface time division multiplexer interface controller e Memory to memory DMA e QSPI module USB module All external interrupt inputs are edge sensitive The active edge is programmable An interrupt request must be held valid for at least three consecutive CPU clock cycles to be considered a valid input Each interrupt input can have it s priority programmed by setting the xIPL 2 0 bits in the Interrupt Control Registers NOTE No interrupt sources should have the same level and priority as another Programming two interrupt sources with the same level and priority can result in undefined operation The M5272C3 hardware uses INT6 to support the ABORT function using the ABORT switch S2
57. e Reset eur EE ET 2 6 Command Line RE 2 6 Commands ER 2 6 Contents V For More Information On This Product Go to www freescale com Paragraph Number 2 5 2 5 1 jie 2 5 3 2 5 4 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 1 5 3 1 6 3 1 7 3 1 8 3 1 9 3 1 10 3 1 11 3 1 12 3 1 13 3 1 14 3 2 3 2 1 3 2 2 3 3 3 4 3 5 3 6 3 6 1 3 6 2 vi CONTENTS Page me Number TRAPA US BTS UES ssa ics edo Guo s tete Du ve a tuae aed ta Sued ket i cq t a dde 2 30 OUT e EE 2 39 Ri 2 39 CHAR PRESEN Tie aen aiaa atin eaaa NUS PANURISATQUA TENE FUSE NETUS EOS ERES 2 40 EXUECIO OBE GO toas ere oe ee ee a a added M NUT NOD aiU epe 2 40 Chapter 3 Hardware Description and Reconfiguration The Processor and Support Logic cise asec rendi tena i eb em dun dd 3 1 EE 3 1 Ign R 3 1 MZ Signal esa eet a at aig Sacks ae tsa Ee ee costa t iari 3 2 Sid qe ici 3 2 Watchdog Ke 3 2 Interript SOURCES REIN Eege 3 2 Internal SRAM EE 3 3 The MCF5407 Registers and Memory Map 3 4 Reset Vector Mapping eee ei eiae e Ue ets ced RU STR TUNER Re Ape sedata rds 3 5 EEN Sic scenes e rti red at D ecc sep Mou ni 3 5 Wait State Generators octo edu ie raduno 3 6 SDRAM DIMM eodd tiende NM pepe s e E OU a 3 6 leet ROM pee c 3 7 JP15 Jumper and User s Program eee ient tienne eint ion na ca 3 7 Serial Communication Channels Ls i ope peteret euis
58. e connected to the MCF5272 to provide 1Mx32 of memory 3 1 13 Flash ROM There is one 2 MByte Flash ROM on the M5272C3 U8 The board is shipped with one AMD Am29PL160C 2 MByte Flash ROM The first 256 Kbytes of the Flash contains the ROM Monitor firmware dBUG The remaining Flash memory is available to the user via use of jumper 13 The MCF5272 chip select logic can be programmed to generate the TA for CSO signal after a certain number of wait states i e auto acknowledge mode The dBUG monitor programs this parameter to be six wait states 3 6 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Serial Communication Channels 3 1 14 JP13 Jumper and the User s Program Jumper 13 allows users to test code from boot POR without having to overwrite the ROM Monitor When the jumper is set between pins 1 and 2 the behavior of the system is normal dBUG boots and then runs from OxFFE00000 When the jumper is set between pins 2 and 3 the board boots from the second half of the Flash OxFFF00000 Procedure 1 Compile and link as though the code was to be placed at the base of the flash but setup so that it will download to the SDRAM starting at address OXEO000 The user should refer to their compiler documentation for this since it will depend upon the compiler used 2 Set up the jumper JP13 for Normal operation pinl connected to pin 2
59. e frames but only to compensate for external bus latency The FIFO can be partitioned on any 32 bit boundary between receive and transmit for example 32 x 56 receive and 32 x 56 transmit Retransmission from transmit FIFO following a collision no processor bus used Automatic internal flushing of the receive FIFO for runts and collisions with no processor bus use For more details see the MCF5272 Users manual this module s signals are also brought to expansion connector J3 The on board ROM MONITOR is programmed to allow a user to download files from a network to memory in different formats The current compiler formats supported are S Record COFF ELF or Image 3 2 6 USB Universal Serial Bus Module The MCF5272 processor includes the following features 3 10 Supports full speed 12 Mbps USB devices and low speed 1 5 Mbps devices Full compliance with the Universal Serial Bus Specification Revision 1 1 with the addition of an external USB transceiver Automatic processing of USB standard device requests CLEAR_FEATURE GET_CONFIGURATION GET_DESCRIPTOR GET_INTERFACE GET_STATUS SET_ADDRESS SET_CONFIGURATION SET_FEATURE and SET_INTERFACE Supports either internal or external USB transceiver Programmable 512 byte receive and 512 byte transmit FIFO buffers USB device controller with protocol control and administration for up to eight endpoints 16 interfaces and 16 configurations Programmable endpoint types with support f
60. e prescaler Three independent PWM modules Byte wide width register provides programmable control of duty cycle The PWM is a simple free running counter implemented along with a width register and a comparator such that the output is cleared when the counter value exceeds the value of the width register When the counter wraps around the counter value is less than or equal to the value of the width register and the output is set high The width register is double buffered so that a new value can be loaded for the next cycle without disturbing the current cycle At the beginning of each period the contents of the width buffer register are loaded into the width register The width register feeds the comparator for the purpose of comparison during the next cycle The prescaler contains a variable divider that can divide the incoming clock by certain values between 1 and 32768 The PWM signals are brought to expansion connector J3 please see the MCF5272 User manual for more detail 3 8 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Serial Communication Channels 3 2 4 Parallel UO Port The MCF5272 device provides up to 48 general purpose I O signals depending on device configuration Eight general purpose I O GPIO pins will be available at all times The functions of all I O pins are individually programmable since they are multiplexed with oth
61. eck for proper insertion or connection of the network cable Is the status LED lit indicating that network traffic is present Check for proper configuration and operation of the TFTP server Most Unix workstations can execute a command named tftp which can be used to connect to the TFTP server as well Is the default TFTP root directory present and readable If ICMP DESTINATION UNREACHABLE or similar ICMP message appears then a serious error has occurred Reset the board and wait one minute for the TFTP server to time out and terminate any open connections Verify that the IP addresses for the server and gateway are correct Also verify that a TFTP server is running on the server Appendix A Configuring dBUG for Network Downloads A 3 For More Information On This Product Go to www freescale com Appendix B PAL Equations The PAL equations listed below provide some simple decode logic for the address and data buffers sheet 2 of the schematics and some memory mapped I O sheet 9 of the schematics The first equation which defines generation of the BD_CS signal is a simple OR ing of chip select signals CSO Flash CS2 FSRAM and CS5 amp CS6 PLI connectors This signal is then used to control the output enable OE signal of buffers Ul and U3 that drive the 32 bit wide data bus The next four equations define read and write access to some memory mapped I O octal D type flip flops These equations generate 8 extra input a
62. ed data is used The value for data may be a symbol name or a number converted according to the user defined radix normally hexadecimal If a value for data is provided then the MM command immediately sets the contents of addr to data If no value for data is provided then the MM command enters into a loop The loop obtains a value for data sets the contents of the current address to data increments the address according to the data size and repeats The loop terminates when an invalid entry for the data value is entered i e a period This command first aligns the starting address for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To set the byte at location 0x00010000 to be OxFF the command is mm b 10000 FF To interactively modify memory beginning at 0x00010000 the command is mm 10000 2 26 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands MMAP Memory Map Display Usage mmap This command displays the memory map information for the M5272C3 evaluation board The information displayed includes the type of memory the start and end address of the memory and the port size of the memory The display also includes information on how the Chip selects are used on the board Here is an ex
63. er pin functions All general purpose I O pins can be individually selected as input or output pins After reset all software configurable multi function GPIO pins default to general purpose input pins At the same time all multifunction pins that are not shared with a GPIO pin default to high impedance Internal pullup resistors avoid unknown read values in order to reduce power consumption They remain active until the corresponding port direction registers are programmed The general purpose I O signals are configured as three ports each having up to sixteen signals These three general purpose I O ports are shared with other signals as follows e Port A bits 6 0 are multiplexed with the signals required to interface to an external USB transceiver e PA7 is multiplexed with SPI_CS3 and DOUT3 e Port A bits 15 8 are multiplexed with the pins of PLI TDM Ports 0 and 1 and UARTI e Port B bits 7 0 are multiplexed with the UARTO signals and the bus control signal TA Port B bits 15 8 are multiplexed with the Ethernet controller signals e Port C bits 15 0 are multiplexed with data bus signals D15 D0 and are only available when the device is configured for 16 bit data bus mode using the WSEL signal Control registers are provided for each port to select the function GPIO or peripheral pin assigned to each pin individually Pins can have from 1 to 4 functions including GPIO There is no configuration register for GPIO port
64. eral parameters are required for network downloads to occur The information that is required and the steps for configuring dBUG are described below A 1 Required Network Parameters For performing network downloads dBUG needs 6 parameters 4 are network related and 2 are download related The parameters are listed below with the dBUG designation following in parenthesis All computers connected to an Ethernet network running the IP protocol need 3 network specific parameters These parameters are Internet Protocol IP address for the computer client IP IP address of the Gateway for non local traffic gateway IP and Network netmask for flagging traffic as local or non local netmask In addition the dBUG network download command requires the following three parameters IP address of the TFTP server server IP Name of the file to download filename Type of the file to download filetype of S record COFF ELF or Image Your local system administrator can assign a unique IP address for the board and also provide you the IP addresses of the gateway netmask and TFTP server Fill out the lines below with this information Client IP IP address of the board Server IP IP address of the TFTP server Gateway IP address of the gateway Netmask Network netmask Appendix A Configuring dBUG for Network Downloads A 1 For More Information On This Product Go to www freescale com Co
65. figuration 3 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Serial Communication Channels time minimising CPU intervention between transfers Transfer RAMs in the QSPI are indirectly accessible using address and data registers Functionality it is very similar but not identical to the QSPI portion of the QSM Queued Serial Module implemented in the MC68332 Programmable queue to support up to 16 transfers without user intervention Supports transfer sizes of 8 to 16 bits in 1 bit increments Four peripheral chip select lines for control of up to 15 devices Baudrates from 129 4 Kbps to 33 Mbps at 66MHz Programmable delays before and after transfers Programmable clock phase and polarity Supports wrap around mode for continuous transfers Please see the MCF5272 Users Manual for more detail The QSPI signals from the MCF5272 device are brought out to expansion connector J3 Some of these signals are multiplexed with other functions 3 2 3 PWM Pulse Width Modulation Module This section describes the Pulse Width Modulation unit for use in control applications With a suitable low pass filter the PWM can be used as a simple digital to analog converter This module generates a synchronous series of pulses The duty cycle of the pulses is under software control A summary of the main features include e Double buffered width register e Variable divid
66. has a foot print for a 512 KByte FSRAM but it is unpopulated 1 3 Serial Communication Channels The MCF5272 has 2 built in UARTs UARTO and UART1 with independent baud rate generators The signals of both channels pass through external Driver Receivers to make the channels RS232 compatible An RS232 serial cable with DB9 connectors is included with the board UARTO which is connected to P3 is used by the ROM monitor debugger dBUG for the user to access with a terminal In addition the signals of both channels are available on the 120 pin expansion connector J3 UARTO channel is the TERMINAL channel used by the debugger for communication with external terminal PC The TERMINAL baud rate defaults to 19200 1 4 Parallel I O Ports The MCF5272 offers 48 bits of general purpose parallel I O of which eight GPIO lines will be available at all times Each pin can be individually programmed as input or output The GPIO signals are configured as three ports each having up to 16 signals These three GPIO ports are shared with other signals as follows Port A bits 6 0 are multiplexed with the signals required to interface to an external USB transceiver PA7 is multiplexed with SPI CS3 and DOUT3 Port A bits 15 8 are multiplexed with the pins of PLI TDM Ports 0 amp 1 and USART2 Port B bits 7 0 are multiplexed with the USARTI signals and the bus control signal TA Port B bits 15 8 are multiplexed with the Ethernet controller signals 1 4 M527
67. he memory to 512K FSRAM via the U9 footprint or connect to a PC via the JR1 USB connector as a device 1 1 General Hardware Description The M5272C3 board provides SDRAM Flash ROM an Ethernet interface 10 100M bit sec RS232 and all the built in I O functions of the MCF5272 device for programming and evaluating the attributes of the microprocessor The MCF5272 device is a member of the ColdFire family of processors It is a 32 bit processor with a 23 bit address bus and 32 lines of data The processor has eight 32 bit data registers eight 32 bit address registers a 32 bit program counter and a 16 bit status register The MCF5272 has a System Integration Module referred to as the SIM This module incorporates many of the functions needed for system design These include programmable chip select logic system protection logic general purpose I O and interrupt controller logic The chip select logic can select up to eight memory banks and peripherals in addition to two banks of DRAMs The chip select logic also allows the insertion of a programmable number of wait states to allow slower memory or memory mapped peripherals to be used refer to MCF5272 User s Manual by Motorola for detailed information about the SIM The M5272C3 uses five of the eight chip selects to access the Flash ROMs CS0 FFRAM CS2 which is not populated on the board but may be added by the user and SDRAM CS7 CS5 is used to generate control signals for PLI soc
68. icates an Image download and the s indicates an S record download The o option works only in conjunction with the s option to indicate an optional offset for S record download The filename is passed directly to the TFTP server and therefore must be a valid filename on the server If neither of the c e i s or filename options are specified then a default filename and filetype will be used Default filename and filetype parameters are manipulated using the SET and SHOW commands The DN command checks the destination download address for validity If the destination is an address outside the defined user space then an error message is displayed and downloading aborted For ELF and COFF files which contain symbolic debug information the symbol tables are extracted from the file during download and used by dBUG Only global symbols are kept in dBUG The dBUG symbol table is not cleared prior to downloading so it is the user s responsibility to clear the symbol table as necessary prior to downloading If an entry point address is specified in the S record COFF or ELF file the program counter is set accordingly Examples To download an S record file with the name srec out the command is dn s srec out To download a COFF file with the name coff out the command is dn c coff out To download a file using the default filetype with the name bench out the command is dn bench out To download a file using the defaul
69. ies the contents of the internal registers of different modules inside the MCF5272 In the command line module refers to the module name where the register is located and register refers to the specific register to modify The data parameter specifies the new value to be written into the register The registers are organized according to the module to which they belong The available modules on the MCF5272 are CS DMAO DMA1 DMA2 DMA3 DRAMC PP MBUS SIM TIMERI TIMER2 UARTO and UARTI Refer to the MCF5272 user s manual for more information on these modules and the registers they contain Example To modify the TMR register of the first Timer module to the value 0x0021 the command is irm timerl tmr 0021 Chapter 2 Using the Monitor Debug Firmware 2 21 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands HELP Help Usage HELP command The HELP command displays a brief syntax of the commands available within dBUG In addition the address of where user code may start is given If command is provided then a brief listing of the syntax of the specified command is displayed Examples To obtain a listing of all the commands available within dBUG the command is help To obtain help on the breakpoint command the command is help br 2 22 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go
70. ine interface dBUG assumes that an 80x24 character dumb terminal is utilized to connect to the debugger For serial communications dBUG requires eight data bits no parity and one stop bit 8N1 The default baud rate is 19200 but can be changed after the power up The command line prompt is dBUG gt Any dBUG command may be entered from this prompt dBUG does not allow command lines to exceed 80 characters Wherever possible dBUG displays data in 80 columns or less dBUG echoes each character as it is typed eliminating the need for any local echo on the terminal side In general dBUG is not case sensitive Commands may be entered either in upper or lower case depending upon the user s equipment and preference Only symbol names require that the exact case be used Chapter 2 Using the Monitor Debug Firmware 2 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com What Is dBUG Most commands can be recognized by using an abbreviated name For instance entering h is the same as entering help Thus it is not necessary to type the entire command name The commands DI GO MD STEP and TRACE are used repeatedly when debugging dBUG recognizes this and allows for repeated execution of these commands with minimal typing After a command is entered simply press RETURN or lt ENTER gt to invoke the command again The command is executed as if no command line
71. ined radix normally hexadecimal Please reference the ColdFire Microprocessor Family Programmer s Reference Manual for details on the S Record format If offset is provided then the destination address of each S record is adjusted by offset The DL command checks the destination download address for validity If the destination is an address outside the defined user space then an error message is displayed and downloading aborted If the S record file contains the entry point address then the program counter is set to reflect this address Examples To download an S record file through the serial port the command is di To download an S record file through the serial port and add an offset to the destination address of 0x40 the command is di 0x40 2 16 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands DN Download Network Usage DN c lt e gt lt i gt lt s gt o offset filename The DN command downloads code from the network The DN command handle files which are either S record COFF ELF or Image formats The DN command uses Trivial File Transfer Protocol TFTP to transfer files from a network host In general the type of file to be downloaded and the name of the file must be specified to the DN command The c option indicates a COFF download the e option indicates an ELF download the i option ind
72. inning of this manual for contact details 1 11 M5272C3 Jumper Setup Jumper settings are as follows Note is used to indicate that default setting is used to indicate mandatory setting for proper operation Table 1 2 Jumper Settings Jumper Setting Function JP1 1 2 Ethernet controller U7 autonegotiate enabled 2 3 Ethernet controller U7 autonegotiate disabled JP2 1 2 Ethernet controller U7 handles BOTH 10 and 100 Base T operation 2 3 Ethernet controller U7 handles EITHER 10 OR 100 Base T Ethernet connection JP3 1 2 Ethernet controller U7 Full Duplex operation 2 3 Ethernet controller U7 HalfDuplex operation JP4 1 2 Ethernet controller U7 Management Data Enabled Chapter 1 M5272C3 Board 1 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com M5272C3 Jumper Setup Table 1 2 Jumper Settings Continued Jumper Setting Function 2 3 Ethernet controller U7 Management Data Disabled JP5 9 Not applicable Ethernet controller Device Address Default 0 JP10 1 2 Set slew rate in conjunction with JP12 see Table 1 4 JP11 1 2 Ethernet Pause capability Disabled JP12 1 2 Set slew rate in conjunction with JP10 see Table 1 4 JP13 1 2 Flash EEPROM U8 boot into dBUG ROM monitor 2 3 Flash EEPROM U8 boot i
73. is Product Go to www freescale com Paragraph Number 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 9 1 1 9 2 1 9 3 1 9 4 1 9 5 1 9 6 1 9 7 1 10 1 11 1 12 2 1 2 221 2 32 2 2 2 1 2 2 2 2 22 2 3 2 3 2 4 CONTENTS Page file Number Chapter 1 M5407C3 Board General Hardware Description a aues ot rn Rep e sed e 1 1 System Memory EE 1 4 Serial Communication TEE 1 4 Parallel TO POE seee ieie orisni HE fubit ia Eee eoe 1 4 Programmable Timer Counter EE 1 5 IS Ee 1 5 CI Arh SENG Lato handed psit alse evelyn di a o ien te d 1 5 EE 1 5 uerteelen eege 1 7 Bid xD RE 1 7 Preparing the Board for US ier rales desi Men ee sese ups e sender quoa dee E 1 7 Providing Power to the Board ie rettet a ee lile paco uad 1 8 Selecting Terminal Baud Rate 2 32 2 ele denied ate eb ptt eegen 1 8 The Terminal Character Pormat s ee 1 8 Connecting the Terminal oaa i E eth RAT ERU ex Rae Ee De eda ca TRUE 1 8 Using a Personal Computer as a Termnal eene 1 8 System Power up and Initial Operapon esee 1 11 M5407C3 Jumper Setlps sosta RM ARE Ina Ned ue eae rait ic Ld Lem UT EE 1 11 Usine The EE Eed 1 13 Chapter 2 Using the Monitor Debug Firmware Wea Ts EI DLE ovo en e t e ME 2 1 Operational Procedure ee dei sees dA CASU a E R Esai 2 3 System Power EE 2 3 System napiweute C 2 4 EEGUERESETJIBUUODS gud atiis doe pad uv E a Fete d 2 5 ABORT B tton o ure nre nessun ir enu ue cut eae duse 2 5 Softwar
74. ket 0 J5 and CS6 is used to Chapter 1 M5272C3 Board 1 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com General Hardware Description generate control signals for PLI socket 1 J6 The PLI sockets J5 amp J6 allow ISDN or POTs daughter cards to be connected to the system If the user chooses not to populate either of the PLI connectors CS5 and CS6 become available to the user The DRAM controller is used to control two SDRAM devices providing 4MB of SDRAM memory configured as 1MBx32 longwords All other functions of the SIM are available to the user 1 2 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com General Hardware Description Figure 1 1 shows the M5272C3 block diagram 1 DB 9 Deb t d i 26 pin debug connector ColdFire MCF5272 ere 1 RS232 drivers A jen QSPI re 66MHz a 5 Ethernet d 1 RS232 A OSC Interface USB drivers Ho Lk ignals Bus Clk Drv PWM 1 DB 9 addr data 0 23 0 Leo gt SDRAM gt Y y g Y Y Y Buffers PLI Connectors not populated ra 32bit 3 3V UI 512KB Sync FSRAM 32 bit 3 3V not populated
75. ld be the appropriate action if all else fails 2 2 2 2 ABORT Button ABORT S2 is the button located next to RESET button The abort function causes an interrupt of the present processing a level 7 interrupt on MCF5272 and gives control to the dBUG firmware This action differs from RESET in that no processor register or memory contents are changed the processor and peripherals are not reset and dBUG is not restarted Also in response to depressing the ABORT button the contents of the MCF5272 core internal registers are displayed The abort function is most appropriate when software is being debugged The user can interrupt the processor without destroying the present state of the system This is accomplished by forcing a non maskable interrupt that will call a dBUG routine that will save the current state of the registers to shadow registers in the monitor for display to the user The user will be returned to the ROM monitor prompt after exception handling Chapter 2 Using the Monitor Debug Firmware 2 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Command Line Usage 2 2 2 3 Software Reset Command dBUG does have a command that causes the dBUG to restart as if a hardware reset was invoked The command is RESET 2 3 Command Line Usage The user interface to dBUG is the command line A number of features have been implemented to achieve an easy and intuitive com
76. male 25 pin or 9 pin It may be neccessary to obtain a 25pin to Opin adapter to make the connection If an adapter is required refer to Figure 1 3 which shows the pin assignment for the 9 pin connector on the board 1 9 7 Using a Personal Computer as a Terminal A personal computer may be used as a terminal provided a terminal emulation software package is available Examples of this software are PROCOMM KERMIT QMODEM Windows 95 98 2000 Hyper Terminal or similar packages The board should then be connected as described in section 1 9 6 Connecting the Terminal 1 8 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Installation And Setup Once the connection to the PC is made power may be applied to the PC and the terminal emulation software can be run In the terminal mode it is neccessary to select the baud rate and character format for the channel Most terminal emulation software packages provide a command known as Alt p press the p key while pressing the Alt key to choose the baud rate and character format The character format should be 8 bits no parity one stop bit see section 1 9 5 The Terminal Character Format The baud rate should be set to 19200 Power can now be applied to the board Figure 1 3 shows pin assignments for a female terminal connector Figure 1 3 Pin assignment for female Terminal connector Pin assignments are
77. mand line interface dBUG assumes that an 80x24 ASCII character dumb terminal is used to connect to the debugger For serial communications dBUG requires eight data bits no parity and one stop bit 8N1 The baud rate default 1819200 bps a speed commonly available from workstations personal computers and dedicated terminals The command line prompt is dBUG gt Any dBUG command may be entered from this prompt dBUG does not allow command lines to exceed 80 characters Wherever possible dBUG displays data in 80 columns or less dBUG echoes each character as it is typed eliminating the need for any local echo on the terminal side The Backspace and Delete keys are recognized as rub out keys for correcting typographical mistakes Command lines may be recalled using the Control U Control D and Control R key sequences Control U and Control D cycle up and down through previous command lines Control R recalls and executes the last command line In general dBUG is not case sensitive Commands may be entered either in uppercase or lowercase depending upon the user s equipment and preference Only symbol names require that the exact case be used Most commands can be recognized by using an abbreviated name For instance entering h is the same as entering help Thus it is not necessary to type the entire command name The commands DI GO MD STEP and TRACE are used repeatedly when debugging dBUG recog
78. nal chip select logic All the processor s signals are available through the expansion connectors J2 and J3 Refer to section 3 3 1 for their pin assignments The MCF5272 processor has the capabiliy to support both an IEEE JTAG compatible port and a BDM port These ports are multiplexed on to the same pins and can be used with third party tools to allow the user to download code to the board The board is configured to boot up in the normal BDM mode of operation The BDM signals are available at port J4 The processor also has the logic to generate up to eight 8 chip selects CSO to CS7 and support for 1 bank of ADRAM not included on the evaluation board or 1 bank of SDRAM included on the evaluation board 4 Mbytes in total configured as 1Mx32 The CS7 signal is used to provide selection and control of this bank of SDRAM Chapter 3 Hardware Description and Reconfiguration 3 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com The Processor and Support Logic 3 1 2 Reset Logic The reset logic provides system initialisation Reset occurs during power on or via assertion of the signal RSTI which causes the MCF5272 to reset Reset is also triggered by the reset switch S1 which resets the entire processor system A hard reset and voltage sense controller U17 is used to produce an active low power on RESET signal The reset switch S1 is fed into U17 which generates the sign
79. nd 8 extra output lines for each PLI connector This extra I O is a backup to the I O already available on the MCF5272 which may be used by some customers for alternate functions as many of the pins on the MCF5272 have 2 or 3 multiplexed functions Each I O equation uses a chip select signal CS5 amp CS6 and the OE signal from the MCF5272 to define the control signal to the D types TITLE U20 PATTERN P00001 REVISION 1 DATE 3rd November 2000 AUTHOR Pete Highton COMPANY Motorola SPS c 2000 CHIP U20 PALCE16V8 PIN 1 CLK COMBINATORIAL I P PIN 2 CSO COMBINATORIAL I P PIN 3 CS2 COMBINATORIAL I P PIN 4 CS5 COMBINATORIAL I P PIN 5 CS6 COMBINATORIAL I P PIN 6 OE COMBINATORIAL I P PIN 7 NC PIN 8 NC PIN 9 NC PIN 10 GND Appendix B PAL Equations B 1 For More Information On This Product Go to www freescale com PIN 11 NC PIN 12 BD CS PIN 13 CS5 RD PIN 14 CS5 WR PIN 15 CS6 RD PIN 16 CS6 WR PIN 17 NC PIN 18 NC PIN 19 NC PIN 20 VCC EQUATIONS BD_CS cso CS2 CS5 CS5 RD CS5 OE CS5 WR CS5 OE CS6 RD CS6 OE CS6 WR CS6 OE B 2 CO CO CO CO CO M5272C3 User s Manual BINATO BINATO BINATO BINATO BINATO RIAL RIAL RIAL RIAL RIAL O P O P O P O P Generic CS derived for data buffers CS5 amp OI Ol CS5 amp OI CS6 amp OI
80. nfiguring dBUG Network Parameters A 2 Configuring dBUG Network Parameters Once the network parameters have been obtained the dBUG Rom Monitor must be configured The following commands are used to configure the network parameters set client client IP gt set server server IP set gateway gateway IP set netmask lt netmask gt set mac lt addr gt For example the TFTP server is named santafe and has IP address 123 45 67 1 The board is assigned the IP address of 123 45 68 15 The gateway IP address is 123 45 68 250 and the netmask is 255 255 255 0 The MAC address is chosen arbitrarily and is unique The commands to dBUG are set client 123 45 68 15 set server 123 45 67 1 set gateway 123 45 68 250 set netmask 255 255 255 0 set mac 00 CF 52 72 C3 01 The last step is to inform dBUG of the name and type of the file to download Prior to giving the name of the file keep in mind the following Most if not all TFTP servers will only permit access to files starting at a particular sub directory This is a security feature which prevents reading of arbitrary files by unknown persons For example SunOS uses the directory tftp boot as the default TFTP directory When specifying a filename to a SunOS TFTP server all filenames are relative to tftp boot As a result you normally will be required to copy the file to download into the directory used by the TFTP server A default filename for network downloads is maint
81. nizes this and allows for repeated execution of these commands with minimal typing After a command is entered press the Return or Enter key to invoke the command again The command is executed as if no command line parameters were provided 2 4 Commands This section lists the commands that are available with all versions of dBUG Some board or CPU combinations may use additional commands not listed below 2 6 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands Table 2 1 dBUG Command Summary MNEMONIC SYNTAX DESCRIPTION ASM asm lt lt addr gt stmt gt Assemble BC bc addr1 addr2 length Block Compare BF bf width begin end data inc Block Fill BM bm begin end dest Block Move BR br addr r c count t trigger Breakpoint BS bs width begin end data Block Search DC dc value Data Convert DI di lt addr gt Disassemble DL dl lt offset gt Download Serial DN dn c e lt i gt s o offset gt gt filename Download Network GO go lt addr gt Execute GT gt addr Execute To HELP help lt command gt Help IRD ird lt module register gt Internal Register Display IRM irm module register data Internal Register Modify LR Ir lt width gt addr Loop Read LW Iw width addr data Loop Write MD md
82. ns These are OUT CHAR IN CHAR CHAR PRESENT and EXIT TO dBUG 2 5 1 OUT CHAR This function function code 0x0013 sends a character which is in lower 8 bits of D1 to terminal Assembly example assume d1 contains the character move l 0013 d0 Selects the function TRAP 15 The character in d1 is sent to terminal C example void board_out_char int ch Tf your C compiler produces a LINK UNLK pair for this routine then use the following code which takes this into account Tif 1 LINK a6 0 produced by C compiler asm move 18 a6 d1 put ch into d1 asm move 140x0013 d0 select the function asm trap 15 make the call UNLK a6 produced by C compiler else If C compiler does not produce a LINK UNLK pair the use the following code asm move l4 sp d1 put ch into d1 asm move l 0x0013 d0 select the function asm trap 15 make the call endif 2 5 2 IN CHAR This function function code 0x0010 returns an input character from terminal to the caller The returned character is in D1 Chapter 2 Using the Monitor Debug Firmware 2 39 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com TRAP 15 Functions Assembly example move l 0010 d0 Select the function trap 15 Make the call the input character is in d1 C example
83. nto Flash user space ignoring first 256K JP14 1 2 MCF5272 SDRAM controller U5 enable RESET 2 3 MCF5272 SDRAM controller U5 disable RESET JP15 1 2 MCF5272 U5 Normal Operation 2 3 MCF5272 U5 Test Mode JP16 1 2 MCF5272 U5 BDM mode 2 3 MCF5272 U5 JTAG mode JP17 ON Databus width 32 bits OFF Databus width 16 bits JP18 ON Set CS0 databus width see Table 1 3 JP19 OFF Set CS0 databus width see Table 1 3 JP20 1 2 CPU Clock 66MHz 2 3 CPU Clock 48MHz JP21 1 2 Routes BD27 onto PLI 0 connector J5 2 3 Routes Mux d signal UART2CTS SPI CS2 5272 pin K2 onto PLI 0 connector J5 JP22 1 2 Routes BD27 onto PLI 1 connector J6 2 3 Routes Mux d signal BUSWO SPI CSO0 5272 pin M5 onto PLI 1 connector J6 JP23 1 2 Routes BD30 onto PLI 0 connector J5 2 3 Routes Mux d signal PA11 SPI CS1 5272 pin L1 onto PLI 0 connector J5 JP24 1 2 Routes BD30 onto PLI 1 connector J6 2 3 Routes Mux d signal DOUTS SPI CS3 5272 pin P1 onto PLI 1 connector J6 JP25 1 2 USB tranceiver U26 non forced SEO USB operation 2 3 USB tranceiver U26 forced SEO USB operation JP26 Not fitted USB interface JR1 supplies either 3 3V or 5 0V if fitted 1 2 USB interface JR1 board supplies 3 3V 2 3 USB interface JR1 board supplies 5 0V via J7 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com CS0 Databus width Jumper Setting
84. or up to eight control interrupt bulk or isochronous endpoints Independent interrupts for each endpoint M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Serial Communication Channels e Supports remote wakeup Detects start of frame and missed start of frame for isochronous endpoint synchronization Notification of start of frame reset suspend and resume events e Operates in Device mode only All the USB signals are brought out to USB connector JR1 and expansion connector J3 For further details please refer to the MCF5272 User s manual 3 2 7 ROM Module e 16 Kbyte ROM organized as 4K x 32 bits Contains tabular data for soft HDLC DTMF detection amp tone generation e Single cycle access e Physically located on ColdFire core s high speed local bus Byte word longword address capabilities Programmable memory mapping The ROM module contains tabular data that the ColdFire core can access in a single cycle The ROM can be located on any 16 Kbyte address boundary in the 4 Gbyte address space Depending on configuration information instruction fetches can be sent simultaneously to the instruction cache and the ROM block If the fetch address is mapped into the region defined by the ROM the ROM provides the data back to the processor and any instruction cache data is discarded Accesses from the on chip ROM are not cached
85. pansion Bus There are 2 expansion connectors on the M5272C3 J2 and J3 which are used to connect the board to external I O devices and or expansion boards 3 3 1 Expansion Connectors J2 and J3 Table 3 2 shows pin assignments for the J2 connector Table 3 2 J2 Connector Pin Assignment 3 12 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Connectors and Expansion Bus Table 3 2 J2 Connector Pin Assignment Continued m oe a w Bm TEE EE eo eo foe fre sw else Table 3 3 shows the pin assignments of the J3 connector Table 3 3 J3 Connector pin assignment UXBEXTCLK PB5 TA ESCHER P pes e e for om o pos pe wem je mm s asst Deme m en qm eee m m9 GND 83 PWMOUT2 TO PWMOUT3 TIN UT2 2 PA3 USB_TN PAZ USB RN 87 EXTCLK ETXDO PA4 USB SUS PAS USB TXE lag ECOL m ERXDV P N PA6 USBRXD RSTO 91 ERXCLK ERXDO DCLO USRT2C DINO USRT2R 97 ETXD2 KE ETXD1 LK XD Chapter 3 Hardware Description and Reconfiguration 3 13 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Connectors and Expansion Bus Table 3 3 J3 Connector pin assignment Continued meee m mm Tm em ml s USRT2CTS SP USRTERTSI IN CS6 RD 100 ces RD cs2 a DOUTO USRT2 z DREQO ERXD3 tal ERXD2 TXD GND DFSC2 105 ERXD1 ERXE
86. parameters were provided An additional function called the TRAP 15 handler allows the user program to utilize various routines within dBUG The TRAP 15 handler is discussed at the end of this chapter The operational mode of dBUG is demonstrated in Figure 2 1 After the system initialization the board waits for a command line input from the user terminal When a proper command is entered the operation continues in one of the two basic modes If the command causes execution of the user program the dBUG firmware may or may not be re entered depending on the discretion of the user For the alternate case the command will be executed under control of the dBUG firmware and after command completion the system returns to command entry mode During command execution additional user input may be required depending on the command function For commands that accept an optional width to modify the memory access size the valid values are e B8 bit byte access e W16 bit word access e 32 bit long access When no width option is provided the default width is W 16 bit The core ColdFire register set is maintained by dBUG These are listed below e A0 A7 e D0 D7 e PC e SR All control registers on ColdFire are not readable by the supervisor programming model and thus not accessible via dBUG User code may change these registers but caution must be exercised as changes may render dBUG inoperable A reference to S
87. points are initialized to the values specified by the c or t option Examples To set a breakpoint at the C function main symbol main see symbol command the command is br main When the target code is executed and the processor reaches main control will be returned to dBUG To set a breakpoint at the C function bench and set its trigger value to 3 the command is br bench t 3 When the target code is executed the processor must attempt to execute the function bench a third time before returning control back to dBUG To remove all breakpoints the command is br r 2 12 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands BS Block Search Usage BS width begin end data The BS command searches a contiguous block of memory starting at address begin stopping at address end for the value data lt Width gt modifies the size of the data that is compared during the search If no lt width gt is specified the default of word sized data is used The values for addresses begin and end may be absolute addresses specified as hexadecimal values or symbol names The value for data may be a symbol name or a number converted according to the user defined radix normally hexadecimal This command first aligns the starting address for the data access size and then increments the address accordingly during the ope
88. ration Thus for the duration of the operation this command performs properly aligned memory accesses Examples To search for the 16 bit value 0x1234 in the memory block starting at 0x00040000 and ending at 0x00080000 bs40000 80000 1234 This reads the 16 bit word located at 0x00040000 and compares it against the 16 bit value 0x1234 If no match is found then the address is incremented to 0x00040002 and the next 16 bit value is read and compared To search for the 32 bit value OXABCD in the memory block starting at 0x00040000 and ending at 0x00080000 bs 140000 80000 ABCD This reads the 32 bit word located at 0x00040000 and compares it against the 32 bit value 0x0000A BCD If no match is found then the address is incremented to 0x00040004 and the next 32 bit value is read and compared Chapter 2 Using the Monitor Debug Firmware 2 13 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands DC Data Conversion Usage DC data The DC command displays the hexadecimal or decimal value data in hexadecimal binary and decimal notation The value for data may be a symbol name or an absolute value If an absolute value passed into the DC command is prefixed by Ox then data is interpreted as a hexadecimal value Otherwise data is interpreted as a decimal value All values are treated as 32 bit quantities Examples To display the decimal and binary equi
89. rations Usage SET lt option value gt The SET command allows the setting of user configurable options within dBUG With no arguments SET displays the options and values available The SHOW command displays the settings in the appropriate format The standard set of options is listed below baud This is the baud rate for the first serial port on the board All communications between dBUG and the user occur using either 9600 or 19200 bps eight data bits no parity and one stop bit 8N1 base This is the default radix for use in converting a number from its ASCII text representation to the internal quantity used by dBUG The default is hexadecimal base 16 and other choices are binary base 2 octal base 8 and decimal base 10 client This is the network Internet Protocol IP address of the board For network communications the client IP is required to be set to a unique value usually assigned by your local network administrator server This is the network IP address of the machine which contains files accessible via TFTP Your local network administrator will have this information and can assist in properly configuring a TFTP server if one does not exist gateway This is the network IP address of the gateway for your local subnetwork If the client IP address and server IP address are not on the same subnetwork then this option must be properly set Your local network administrator will have this information netm
90. re e RS232 Communication cable provided Refer to Section 2 2 2 System Initialization for initial system setup Figure 1 2 displays minimum system configuration Chapter 1 M5272C3 Board 1 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com System Configuration SE 45 0 to 14VDC Input Power RS 232 Terminal SE Or PC EE Se Figure 1 2 Minimum System Configuration M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Installation And Setup 1 9 Installation And Setup The following sections describe all the steps needed to prepare the board for operation Please read the following sections carefully before using the board When you are preparing the board for the first time be sure to check that all jumpers are in the default locations Default jumper markings are on the board next to the individual jumpers and a master jumper table is provided on the underside of the board After the board is functional in its default mode you may use the Ethernet by following the instructions provided in Appendix A 1 9 1 Unpacking Unpack the computer board from its shipping box Save the box for storing or reshipping Refer to the following list and verify that all the items are present You should have received e M5272C3 Single
91. ription and Reconfiguration This chapter provides a functional description of the M5272C3 board hardware With the description given here and the schematic diagram in Appendix C the user can gain a good understanding of the board s design In this manual an active low signal is indicated by a preceeding the signal name in the text and a bar over the signal name in the schematics 3 1 The Processor and Support Logic This part of the chapter discusses the CPU and general support logic on the M5272C3 board 3 1 1 Processor The microprocessor used on the M5272C3 is the highly integrated Motorola ColdFire MCF5272 32 bit processor The MCF5272 implements a ColdFire Version 2 core with 1 KByte instruction cache two UART channels four timers 4 KBytes of SRAM a QSPI Queued Serial Peripheral Interface module three 16 bit wide parallel I O ports which are multiplexed with other signals and the system integration module SIM All of the core processor registers are 32 bits wide except for the Status Register SR which is 16 bits wide This processor communicates with external devices over a 32 bit wide data bus D 31 0 with support for 8 and 16 bit ports The width of this data bus is configurable for 16 or 32 bits at Power on Reset POR using the WSEL pin When programmed for a 16 bit external databus width the signals D 15 0 become GPIO Port C The chip can address 16 MBytes of memory space using a 23 bit wide address bus and inter
92. rmware 2 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands BR Breakpoints Usage BR addr lt r gt lt c count gt lt t trigger gt The BR command inserts or removes breakpoints at address addr The value for addr may be an absolute address specified as a hexadecimal value or a symbol name Count and trigger are numbers converted according to the user defined radix normally hexadecimal If no argument is provided to the BR command a listing of all defined breakpoints is displayed The r option to the BR command removes a breakpoint defined at address addr If no address is specified in conjunction with the r option then all breakpoints are removed Each time a breakpoint is encountered during the execution of target code its count value is incremented by one By default the initial count value for a breakpoint is zero but the c option allows setting the initial count for the breakpoint Each time a breakpoint is encountered during the execution of target code the count value is compared against the trigger value If the count value is equal to or greater than the trigger value a breakpoint is encountered and control returned to dBUG By default the initial trigger value for a breakpoint is one but the t option allows setting the initial trigger for the breakpoint If no address is specified in conjunction with the c or t options then all break
93. ruction execution and the target code executed Control returns to dBUG after a single instruction execution of the target code This command is repeatable Examples To trace one instruction at the program counter the command is tr To trace 20 instructions from the program counter the command is tr 20 Chapter 2 Using the Monitor Debug Firmware 2 35 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands UPDBUG Update dBUG Usage updbug The updbug command is used to update the dBUG image in Flash When updates to the M5272C3 dBUG are available the updated image is downloaded to address 0x00020000 The new image is placed into Flash using the UPDBUG command The user is prompted for verification before performing the operation Use this command with extreme caution as any error can render dBUG useless 2 36 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands UPUSER Update User Flash Usage UPUSER bytes The UPUSER command places user code and data into space allocated for the user in Flash The optional parameter bytes specifies the number of bytes to copy into the user portion of Flash If the bytes parameter is omitted then this command writes to the entire user space There are seven sectors of 256K each available as user space Users access this memory
94. sente od hel ascent 3 7 MCP5407 UARTS 5 5 ets et ti yai Rete RU e RE Sed UA 3 7 LR EE 3 8 Real Time Clocks ee n dq eue 3 8 Parallel Eege ab uer edu dg a sch en EE 3 8 Ori Board Bthernet Logics see eri erit to rai RAE egener 3 8 Connectors and Expansion BUS 5 orat ete teeth eere tte NEE tee Eee eae ga 3 11 Expansion Connectors J1 and J A 3 11 The Debus Connector JI ss aine ee eet eb bm prebende 3 13 Appendix A Configuring dBUG for Network Downloads Appendix B ColdFire to ISA IRQ7 and Reset Logic Abel Code Appendix C M5407C3 User s Manual For More Information On This Product Go to www freescale com CONTENTS Paragraph Page Number ie Number SDRAM MUX PAL Equation Appendix D Evaluation Board BOM Appendix E Schematics Appendix F Errata Contents vii For More Information On This Product Go to www freescale com Table Number 1 1 1 2 1 3 1 4 1 5 2 1 3 1 3 2 3 3 D 1 TABLES Page SR Number Power Supply el E 1 8 Vire 1 11 Jumper Settings CS Databus Width AAA 1 13 Jumper Settings Ethernet Controller Slew Rates eee 1 13 Jumper Settings Ethernet Controller Operation Modes see 1 13 dBUG Command Summary osse base pr tod ates edu ere 2 7 The M32 726 3 Memory Map EE 3 5 J2 Connector Pin Assignment ccacesssosien reta eene HE OY REI E ENG e sede Evae ESOS iai 3 12 J3 Connector pin rano Pr 3 13 MCF VE VNE TB ON EE D 1 Tables xi For
95. starting at address OxFFE40000 Examples To program all 7 sectors of user Flash the command is upuser To program only 1000 bytes into user Flash the command is upuser 1000 Chapter 2 Using the Monitor Debug Firmware 2 37 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands VERSION Display dBUG Version Usage VERSION The VERSION command displays the version information for dBUG The dBUG version build number and build date are all given The version number is separated by a decimal for example v 2b 1c 1a In this example v 2b Ic la dBUG common P PU major board major major and minor and minor and minor revision revision revision The version date is the day and time at which the entire dBUG monitor was compiled and built Examples To display the version of the dBUG monitor the command is version 2 38 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com TRAP 15 Functions 2 5 TRAP 15 Functions An additional utility within the dBUG firmware is a function called the TRAP 15 handler This function can be called by the user program to utilize various routines within the dBUG to perform a special task and to return control to the dBUG This section describes the TRAP 15 handler and how it is used There are four TRAP 15 functio
96. t 0x0004000 with a byte value of OxAB the command is bf b 20000 40000 AB To zero out the BSS section of the target code defined by the symbols bss start and bas end the command is bf bas start bss end 0 To fill a block of memory starting at 0x00020000 and ending at 0x00040000 with data that increments by 2 for each width the command is bf 20000 40000 0 2 2 10 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands BM Block Move Usage BM begin end dest The BM command moves a contiguous block of memory starting at address begin and stopping at address end to the new address dest The BM command copies memory as a series of bytes and does not alter the original block The values for addresses begin end and dest may be absolute addresses specified as hexadecimal values or symbol names If the destination address overlaps the block defined by begin and end an error message is produced and the command exits Examples To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to the location 0x00200000 the command is bm 40000 80000 200000 To copy the target code s data section defined by the symbols data_start and data_end to 0x00200000 the command is bm data_start data_end 200000 NOTE Refer to upuser command for copying code data into Flash memory Chapter 2 Using the Monitor Debug Fi
97. t filename and filetype the command is dn Chapter 2 Using the Monitor Debug Firmware 2 17 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands GO Execute Usage GO lt addr gt The GO command executes target code starting at address addr The value for addr may be an absolute address specified as a hexadecimal value or a symbol name If no argument is provided the GO command begins executing instructions at the current program counter When the GO command is executed all user defined breakpoints are inserted into the target code and the context is switched to the target program Control is only regained when the target code encounters a breakpoint illegal instruction trap 15 exception or other exception which causes control to be handed back to dBUG The GO command is repeatable Examples To execute code at the current program counter the command is go To execute code at the C function main the command is go main To execute code at the address 0x00040000 the command is go 40000 2 18 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands GT Execute To Usage GT addr The GT command inserts a temporary breakpoint at addr and then executes target code starting at the current program counter The value for addr may be an absolute address spe
98. to www freescale com Commands LR Loop Read Usage LR lt width gt addr The LR command continually reads the data at addr until a key is pressed The optional lt width gt specifies the size of the data to be read If no lt width gt is specified the command defaults to reading word sized data Example To continually read the longword data from address 0x20000 the command is Ir 20000 Chapier 2 Using the Monitor Debug Firmware 2 23 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands LW Loop Write Usage LW lt width gt addr data The LW command continually writes data to addr The optional width specifies the size of the access to memory The default access size is a word Examples To continually write the longword data 0x12345678 to address 0x20000 the command is lw 20000 12345678 Note that the following command writes 0x78 into memory lw b 20000 12345678 2 24 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands MD Memory Display Usage MD lt width gt begin end The MD command displays a contiguous block of memory starting at address begin and stopping at address end The values for addresses begin and end may be absolute addresses specified as hexadecimal values or symbol names Width modifies the size of the data that is displ
99. valent of 0x1234 the command is de 0x1234 To display the hexadecimal and binary equivalent of 1234 the command is de 1234 2 14 M5272C3 User s Manual PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands DI Disassemble Usage DI lt addr gt The DI command disassembles target code pointed to by addr The value for addr may be an absolute address specified as a hexadecimal value or a symbol name Wherever possible the disassembler will use information from the symbol table to produce a more meaningful disassembly This is especially useful for branch target addresses and subroutine calls The DI command attempts to track the address of the last disassembled opcode If no address is provided to the DI command then the DI command uses the address of the last opcode that was disassembled The DI command is repeatable Examples To disassemble code that starts at 0x00040000 the command is di 40000 To disassemble code of the C function main the command is di _main Chapter 2 Using the Monitor Debug Firmware 2 15 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Commands DL Download Console Usage DL lt offset gt The DL command performs an S record download of data obtained from the console typically a serial port The value for offset is converted according to the user def
100. y to generate this signal The Flash ROM and FSRAM can not generate TA The chip select logic is programmed by the dBUG ROM Monitor to generate TA internally after a pre programmed number of wait states In order to support future expansion of the M5272C3 board the TA input of the processor is also connected to the Processor Expansion Bus J3 pin 64 This allows the expansion boards to assert this line to indicate their TA signal to the processor On the expansion boards this signal should be generated through an open collector buffer with no pull up resistor a pull up resistor is included on this board All TA signals from expansion boards should be connected to this line 3 1 11 Wait State Generator The Flash ROM and SDRAM on the board may require some adjustments to the cycle time of the processor to make them compatible with the processor s external bus speed To extend the CPU bus cycles for the slower devices the chip select logic of the MCF5272 processor can be programmed to generate an internal TA after a given number of wait states Refer to Table 3 1 for information about the address space of the memory and refer to the manufacturers specification for wait state requirements of the SDRAM and Flash ROM 3 1 12 SDRAM The M5272C3 has two 16 MBit devices on the board in a 32 bit wide data bus configuration The MCF5272 processor supports one bank of SDRAM which on this board is represented by SDRAM devices U21 amp U22 These ar

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