Home

User Manual

Contents

1. 141 D pa N N 45 VAR SOM AM43 SYSTEM ON MODULE ctsn Ox1 spi sdk 2 0 spi sdk 2 0 gpmc a20 prO pruO gpo8 0x5 gpio2_26 Od primo won gpme_a20 208 143 144 uararm denm 040 Ox eaEP1 ind oo 06 145 146 23 Ox1 147 uart3 txd 0 3 46 VAR SOM AM43 SYSTEM ON MODULE PM swan oo EE dss datas od CEI DIE gpio1 13 OT UIT 151 B3 Og oo timers 9 wo CT st 169 B8 47 VAR SOM AM43 SYSTEM ON MODULE _ eventm oa AD24 prul oo 1 0 0 0 date oo 181 A7 182 Y22 183 C8 0 7 184 24 eCAP2 in PWM2 out 186 AC18 48 VAR SOM AM43 SYSTEM ON MODULE oo AE20 p cre A 38 020 49 VAR SOM AM43 SYSTEM ON MODULE 50 VAR SOM AM43 SYSTEM ON MODULE 4 Interface Details
2. UART2 RTSn UART Request to Send 62 VAR SOM AM43 SYSTEM ON MODULE 4 8 4 Interface UARTS signals NAME 7 i UART3 RISR UARTRequesttoSend 129 40 145 5 129 40 6 UART Transmit Data 68 68 68 147 147 M7 2 4 8 5 UART5 Interface UARTS signals AM437X SIGNAL Valid configuration PINS UARTS TAD UARTTransmit Data 126 126 126 40 40 40 Notes 1 UARTO Signals are used by default as a low level debug port 2 Refer to PinMux Table 3 2 for RTS CTS Options 3 UART3 and SOM pins 2 4 6 and 8 are used for on SOM Bluetooth if enabled 63 VAR SOM AM43 SYSTEM ON MODULE 4 9 SPI The general features of the SPI controller are Buffered receive transmit data register per channel 1 word deep e Multiple SPI word access with one channel using a FIFO Two DMA requests per channel one interrupt line e Single interrupt line for multiple interrupt source events Serial link interface supports Full duplex Half duplex Multi channel master or single channel slave operations Programmable 1 32 bit transmit receive shift operations Wide selection of SPI word lengths continuous from 4 to 32 bits e Up to four SPI channels e SPI word Transmit Receive slot assignment based on round robin arbitration e SPI configuration per channel clock definition enable polarity and word width e Clock gene
3. 32b LPDDR2 DDR3 DDR3L GPIO Simplified Power ADC 1 8 inputs NAND NOR Async Sequencing 12 bit SAR 16 bit ECC 17 VAR SOM AM43 SYSTEM ON MODULE 2 2 MEMORY 2 2 1 RAM The VAR SOM AM43 is available with up to 8Gbit of DDR3 memory 2 2 2 Non volatile Storage Memory 2 2 3 NAND Flash VAR SOM AM43 is available with up to 512MB 4Gbit of SLC FLASH memory The NAND flash is used for flash disk purposes O S run time image and the bootloader boot from First block block address 00h of the memory device is guaranteed to be valid without ECC up to 1 000 PROGRAM ERASE cycles 2 2 4 eMMC The VAR SOM AM43 is available with up to Up to 32GB of storage 2 2 5 EEPROM The VAR SOM AM43 is available with 4KB I2C EEPROM 2 0 for future revisions 2 3 Ethernet PHY AR8033 AL1A R On board Atheros AR8033 AL1A R is a single 10 100 1000 BASE T IEEE 802 3 compliant Ethernet physical layer transceiver Features 10 100 1000 BASE T IEEE 802 3 compliant e Supports 1000 BASE T PCS and auto negotiation with next page support e Supports RGMII and or SGMII interfaces to MAC devices e Supports Fiber and Copper combo mode when MAC interface works in RGMII mode e Supports additional IEEE 1000 BASE X and 100 BASE FX with Integrated SerDes RGMII timing modes support internal delay and external delay on Rx path e Supports Atheros Green ETHOS power saving modes with internal automatic DS
4. 24 25 24 23 24 23 K23 M25 L24 1 2 ZDN N24 N22 C2 Ci D1 D2 AC20 AB19 19 24 25 54 92 139 147 141 145 187 198 188 179 125 58 117 122 62 60 143 140 54 92 139 147 141 145 187 198 188 179 187 PRO PRUO GPO19 PRO PRUO GPO2 PRO PRUO GPO3 PRO PRUO 4 PRO PRUO GPO5 PRO PRUO GPO6 PRO PRUO GPO7 PRO PRUO PRO PRUO 9 SYSTEM ON MODULE PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRU1 General Purpose Inputs Signals SIGNAL NAME PRO PRU1 GPIO PRO 4 GPI1 PRO 4 GPI10 PRO PRU1 GPI11 PRO 1 GPI12 PRO PRU1 GPI13 PRO PRU1 GPI14 PRO PRU1 GPI15 PRO PRU1 GPI16 PRO 4 GPI17 PRO PRU1 GPI18 PRO PRU1 GPI19 PRO PRU1 GPI2 PRO PRU1 GPI3 PRO PRU1 14 PRO PRU1 GPI5 PRO PRU1 GPI6 PRO 1 GPI7 PRO PRU1 GPI8 PRO PRU1 GPI9 DESCRIPTION PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO P
5. 66 VAR SOM AM43 SYSTEM ON MODULE 4 12 CAN The general features of the DCAN controller are Supports CAN protocol version 2 0 part A ISO 11898 1 e Bit rates up to 1 MBit s Dual clock source 16 32 64 128 message objects instantiated as 64 on this device e Individual identifier mask for each message object e Programmable FIFO mode for message objects e Programmable loop back modes for self test operation e Suspend mode for debug support e Software module reset e Automatic bus on after Bus Off state by a programmable 32 bit timer e Message RAM parity check mechanism e Direct access to Message RAM during test mode CAN Rx Tx pins configurable as general purpose pins e Two interrupt lines plus additional parity error interrupt line e RAM initialization e DMA suppor The SOM includes two CAN 1 F 4 signals are routed to the edge connector CANO signals AM437X SIGNAL Valid PINs Jocanrecevebes DM o DCANTransmitbata 67 CANT signals 437 SIGNAL Valid configuration PINs DCAN1 TX DCAN Receive Data DCAN1_RX DCANTransmitData 145 64 119 67 VAR SOM AM43 SYSTEM ON MODULE 4 13 Analog to Digital Convertor ADCO The touchscreen controller and analog to digital converter subsystem TSC_ADC_SS or ADCO contains a single channel ADC connected to an 8 to 1 analog multiplexer which operates as a general purpose analog to digital c
6. ee 68 69 PU RTT 70 WO 71 General System COMO m ETE 72 BOO COPIO Emm 72 O I 72 73 Pu Sonic NEN m D UU UU MM 73 ES 75 pcc ates 79 NIG BIC LOG Ci T e 79 E 80 POY SF SUPPI de balia 80 VAR SOM AM43 SYSTEM ON MODULE 202 80 5 Absolute Maximum Characteristics pe 80 5 Operating Characteristics sm 81 6 1 Normal Operational Conditions OT 81 6 2 EN 81 0 3 DC Electrical CharacteristiCS RITTER 81 7 Environmental Specifications ccscsccccscscscsccscscsccccccscsceccccscnceccccscscsceccecscsceceecscscesess 83 8 Mechanical Specifications ee 84 8 1 Deanna e 84 8 2 SO 85 9 E Clim 85 10 cielo cem e 85 11 Ordering Information E Tec 86 l Warranty TELNIS Ran 86 12 1 Disclaimer of Warranty Ne 86 122 It union A E 86 AoE 87 Bid 87 VAR SOM AM43 SYSTEM ON MODULE 1 About this Document 1 1 Overview VAR SOM AM43 is a highly integrated cost effective System on Module that perfectly fits various embedded and industrial products and segment It is based on AM437x 1GHz ARM Cortex A9 multipurpose process
7. General Purpose Input output see note 14 A9 26 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 SYSTEM ON AM437X AIN1 437 6 MICDET AM437X_AIN3 MICBIAS 437 MIC IN R 437 437 ADCO_VREFP GND ADCO_VREFN GPIO2 44 LINEIN_RP 1 741 LOWPWR_RSTN LINEIN_LP GPIO4 8 LINEOUT_RP AM437X_PORZN LINEOUT_LP GPIO1_4 DMIC_CLK AM437X_LCD_DATA16 DMIC_DATA 1 519 2 0 SCL GPIO1 64 I2CO_SDA GND AM437X_LCD_DATA21 AM437X_LCD_DATA19 AM437X_LCD_DATA17 GPIO1 34 GPIO4 28 1 2141 4 29 1 14 MODULE A Touch screen X minus analog A Analog input Microphone detect A Touch screen Y minus analog O Microphone bias voltage output A Touch screen X plus analog Al MIC3 input A Analog input A Analog input Al Analog Positive Reference Input Power Digital GND Al Analog Negative Reference Input I O General Purpose Input output see note 14 Al AUDIO Line Input Right I O General Purpose Input output see note 14 Power Audio Ground O RESET OUTPUT build by pins Y23 amp H20 Al AUDIO Line Input Left I O Digital Input Output AO AUDIO Line Output Right I O Power On Reset AO AUDIO Line Output Left I O General Purpose Input output see note 14 O Digita
8. mcaspo fsx pri 0 00000 miiO pri 0 00000 gpio2 15 15 07 96 CEE RE 09 ehrpwm5_tripzone_input Ox6 E gpioO 20 Ox9 gomc_a4 00 eQEP2A_in Ox3 00 ehrpwm0A _ XT ehrpumi tripzone input 06 sno 0 prO pruO gpo1 0x5 gpio3 15 Ox7 40 VAR SOM AM43 SYSTEM ON MODULE USED DRWBUS oo 08 pe mmes o N20 T miiO_ pri mil co Ox5 41 VAR SOM AM43 SYSTEM ON MODULE 119 120 122 123 124 t 0 13 0x7 pri uano ka os OO OD pri vento rin 05 0 _ 000 oo mio nai OKT 1202 DA _SDA Ox3 VAR SOM AM43 SYSTEM ON MODULE prO pruO gpo2 0 7 MES 127 C20 0 1 Xa 0 7 129 B18 43 VAR SOM AM43 SYSTEM ON MODULE 135 B11 955 datal3 OxO gpmc_ad15 44 VAR SOM AM43 SYSTEM ON MODULE mio dink 05 138 10 139 140
9. 0x4 oo E 35 VAR SOM AM43 SYSTEM ON MODULE 56 P25 0x7 124 61 125 62 25 63 24 36 VAR SOM AM43 SYSTEM ON MODULE USBLDRWWBUS OKO sponse spiel o ee oa Ic pri edio data 06 37 VAR SOM AM43 SYSTEM ON MODULE 100 4 0x7 gpioo4 oz OX2 es 50 ehpwmB puarorsen os oo 70 prO_prulgpo7 o5 qme edio data n os woz 000 mca 74 75 ehrowm2A 0x3 pri pruO gpiO 0x6 38 VAR SOM AM43 SYSTEM ON MODULE 2 meee dss ac bias en gpmc a4 pro pru epis 06 pri pruO gpo2 000 pri data n os dss dera 000 pri pruO gpol 0x5 ehrpwm0_synco 0 76 N NI N gpmc a13 VAR SOM AM43 SYSTEM ON MODULE mcaspo fsx
10. 18 2 4 Audio codec via the TLV320AIC3106 4 19 2 9 IU LOO Une 19 2 0 Te 20 5 22 S0M Connector PIKA QUT jan aga ricarica 23 Ss SO DIMM ZOT PINI ini 29 SN 51 4 1 Ne 51 4 2 PSP IRIST Ce e cri 51 4 3 EU 53 54 4 3 2 Optional ROUTE OUT interface 55 4 4 13121 20 m 56 56 4 4 2 On T 56 4 5 57 VAR SOM AM43 SYSTEM ON MODULE tod 4 5 2 4 5 5 4 6 4 6 1 4 6 2 4 7 4 7 1 4 7 2 4 8 4 8 1 4 8 2 428 5 4 8 4 4 8 5 4 9 4 10 4 11 4 12 4 13 4 13 1 4 13 2 4 14 4 15 4 16 4 16 1 4 16 2 4 17 4 17 1 4 17 2 4 18 4 19 4 20 4 20 1 MIICO ISA mmn 57 57 INI 58 M E 59 T VAZUAIC 3 AudiO COC CG usted desi mop hune ete poo hama 59 MCASPO Multichannel Audio Serial Port 59 C again 60 CPI Camera interface 0 iii 60 audience lara ii 61 MVE en E E E 61 UARTO INTET CE ti ieri 62 ICE 62 UART MNES IOE e E E m 62 UART nere 63 UARTS INE C eca ER 63 SS 64 SR 65 66 DAN ian 67 Analog to Digital Convertor ADCO Ne 68
11. and Slave Peripherals Communication IPC Integrates Hardware Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex A9 PRCM and PRU ICSS e Boot Modes Boot Mode is Selected via Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin e Camera Dual Port 8 and 10 Bit BT656 Interface Dual Port 8 and 10 Bit Including External Syncs Single Port 12 Bit YUV422 RGB422 and BT656 Input Format RAW Format Pixel Clock Rate Up to 75 MHz e Package 491 BGA Package 17x17 mm ZDN Suffix 0 65 mm Ball Pitch with Via Channel Array Technology to Enable Low Cost Routing 16 VAR SOM AM43 SYSTEM ON MODULE 2 1 2 Functional Block Diagram ARM Graphics Display 9 PowerVR ani Up to 1000 MHz SGX 24 bit LCDCtrl WXGA Touchscreen Controller TSC 20 MTri s Processing Overlay Quad Core Resizing Color Space PRU ICSS Conversion and more 32K 32K L1 EtherCAT PROFINET 256K L2 RAM EtherNet IP 64K RAM EnDat and more L3 and L4 Interconnect System Interface UART x6 Camera Interface EMAC x5 2x Parallel 2 port switch 10 100 1G QSPI MMC SD with 1588 2 SDIO x3 RMII x3 RGMII CAN x2 eHRPWM x6 USB 2 0 Dual Role and MDIO HDQ 1 Wire eQEP eCAP x3 PHY x2 LL Memory Interface 4ch ADCO 8 inputs 12 bit
12. 1 8V rail 28 VAR SOM AM43 SYSTEM ON MODULE 3 2 SO DIMM 204 Pin Mux The table below summarizes the additional available functionality for each pin in the SO DIMM 200 connector BALL NDS NUMBER 2 NAME gpmca ab H25 RE mm 29 VAR SOM AM43 SYSTEM ON MODULE 7 C6 rO prul 018 Ox4 H22 pru prul gp 11 C3 12 F6 30 VAR SOM AM43 SYSTEM ON MODULE 13 AE21 AE24 oo C 5 16 7 AD25 gt B 31 VAR SOM AM43 SYSTEM ON MODULE 18 rgmii2_rd2 gpmc_a25 1 AD23 20 1 24 0 7 3 AE23 prO 1 gpil3 0x5 4 19 0x7 N N N VAR SOM AM43 SYSTEM ON MODULE AB25 25 cam1_field OxO 28 AD22 prO 1 gpi12 pro pru 33 VAR SOM AM43 SYSTEM ON MODULE eS pr1 edc 0 latcho in Ox6 oo RE 2 AE18 pm prul CO Og o 100 1 Ox7 Bpiool 07 42 A17 34 WW UJ 02 17 VAR SOM AM43 SYSTEM ON MODULE 18 50 18 eCAP1_in_PWM1_out fa event
13. 2 12C0 1 VAR SOM AM43 SYSTEM ON MODULE 2 Main Hardware Components This section summarizes the main hardware building blocks of the VAR SOM AM43 2 1 TEXAS INSTRUMENTS AM437x ARM Cortex A9 2 1 1 Overview The AM437x microprocessors based on the ARM Cortex A9 are enhanced with image graphics processing peripherals and industrial interface options The AM437x microprocessor contains the following subsystems controller and interfaces TEXAS INSTRUMENTS AM437x ARM Cortex A9 e Highlights Upto 1000 MHz ARM Cortex A9 32 Bit RISC Microprocessor e NEON SIMD Coprocessor and Vector Floating Point VFPv3 Coprocessor 32KB of Both L1 Instruction and Data Cache 256KB of L2 Cache or RAM 32 Bit LPDDR2 DDR3 and DDR3L Support General Purpose Memory Support NAND NOR SRAM Supporting Up to 16 bit ECC SGX530 Graphics Engine Display Subsystem Programmable Real Time Unit Subsystem and Industrial Communication Subsystem PRU ICSS Real Time Clock RTC Up to Two USB 2 0 High Speed Dual Role Host or OTG Ports with integrated PHY 10 100 and 1000 Ethernet Switch Supporting Up to Two Ports Serial Interfaces e Two Controller Area Network CAN Ports Six UARTs Two McASPs Five McSPI Three Ports One QSPI and One HDQ or 1 Wire Security e Crypto Hardware Accelerators AES SHA RNG DES and 3DES e Secure Boot Two 12 Bit Successive Approximation Register SAR ADCs Upto T
14. GPIO5 8 GPIO5 13 MODULE O LCD data O LCD pixel clock O LCD data O LCD data O LCD data O LCD data I O SPI Chip Select I O SPI Data Power Digital GND UART Receive Data 005 USB DIFF USBO OTG ID 005 USB DIFF I O SPI Data Power USB1 VBUS I O McASPO Transmit Frame Sync Power Digital GND I O SPI Clock I ODS 0580 OTG Data Pair Power Digital GND I ODS 0580 OTG Data Pair O USBO OTG DRIVER ENABLE Power USBO OTG VBUS Power SOM Power Supply Input Power Digital GND Power SOM Power Supply Input Power SOM Power Supply Input Power SOM Power Supply Input Power SOM Power Supply Input Power Digital GND Power SOM Power Supply Input Power Digital GND I O General Purpose Input output see note 14 Power ADCO Power supply Output 1 8V I O CAN1 Transmit Power ADCO Analog Ground I O General Purpose Input output I O General Purpose Input output 25 B21 A22 B20 A21 B19 A20 T23 P22 P23 V24 U24 V25 P20 T25 N22 N20 W25 W24 G21 U23 C10 AB12 K21 AC15 D25 E24 SYSTEM ON MODULE 116 GPIO1 1217 I O General Purpose Input output E25 117 MCASPO ACLKR I O McASPO Receive Bit Clock L23 118 GND Power Digital GND GND 119 AM437X_DCAN1 RX I O CAN1 Receive L21 120 437 DCANO RX I O CANO Receive L22 121 GND Power Digital GND 122 MCASPO FSR I O McASPO Receive Frame Sync K23 123 437 LCD DATA105 O LCD data A18 124 437 DCANO TX I O CANO Transmit
15. Remote Frame Buffer embedded in the LCD panel support through the RFBI module e Partial refresh of the remote frame buffer through the RFBI module 51 VAR SOM AM43 SYSTEM ON MODULE e Partial display e Multiple cycles output format on 8 9 12 16bit interface TDM Signal Processing e Overlay and Windowing support for one Graphics layer RGB or CLUT and two Video layers YUV 4 2 2 RGB16 and RGB24 RGB 24 bit support on the display interface optionally dithered to RGB 18 bit pixel output 6 Bit Frame rate Control spatial and temporal Transparency color key source and destination Synchronized buffer update e Gamma Curve Support e Multiple buffer support e Cropping Support e Merge capability of the DMA FIFO for use by a single pipeline in case of DVFS e Color Phase rotation Interrupt line and DMA line trigger signals e The LCD DMA is a secure transaction initiator on the L3 interconnect e Remote Frame Buffer Interface Access to RFB s direct MPU interface e Sending commands to the RFB panel e Sending data to the RFB panel received from the Display controller or from the MPU through the L4 OCP slave port e Reading data status from the RFB to the OCP slave port RFBinterface 8 9 12 16 bit parallel interface up to QVGA 30fps at nominal voltage Two programmable configurations for two devices connected to the RFBI module e Tearing Effect control logic Horizontal Synchronization HSync and
16. a73 a73 46 173 173 46 camldatat Camera data 1s6 48 186 48 4 8 UART Interfaces The general features of the UART IrDA module when operating in UART mode are 16C750 compatibility e Baud rate from 300 bps up to 3 6864 Mbps e Auto baud between 1200 bps and 115 2 Kbps e Software Hardware flow control Programmable Xon Xoff characters Programmable Auto RTS and Auto CTS e Programmable serial interface characteristics 5 6 7 or 8 bit characters Even odd mark always 1 space always 0 or no parity non parity bit frame bit generation and detection 1 1 5 or 2 stop bit generation e False start bit detection e Line break generation and detection Modem control functions CTS RTS DSR and DCD e Fully prioritized interrupt system controls e Internal test and loopback capabilities 61 VAR SOM AM43 SYSTEM ON MODULE The SOM includes five UART I F routed out 4 8 1 UARTO Interface UARTO signals AM437X i SIGNAL NAME DESCRIPTION Valid configuration PINs UARTO CTSn UART Clear to Send UARTO_RXD UART Receive Data 66 668 UARTO DCDn UART Data Carrier Detect 4 8 2 UART1 Interface UART1 signals Valid configuration PINs AM437X SIGNAL DESCRIPTION g UART 1 RTSn UART Request to Send UART1 TXDP UART Transmit Data UART1 full modem Interface signals AM437X SIGNAL 4 8 3 UART2 Interface UART2 signals
17. to Enable the Power Management IC to Restore Non RTC Power Domains Peripherals Up to Two USB 2 0 High Speed OTG Ports with Integrated PHY Up to Two Industrial Gigabit Ethernet MACs 10 100 and 1000 Mbps e Integrated Switch Each MAC Supports RMII and RGMII and MDIO Interfaces e Ethernet MACs and Switch Can Operate Independent of Other Functions e IEEE 1588v2 Precision Time Protocol PTP Up to Two Controller Area Network CAN Ports e Supports CAN Version 2 Parts A and B Up to Two Multichannel Audio Serial Ports McASP e Transmit and Receive Clocks Up to 50 MHz e Up to Four Serial Data Pins Per McASP Port with Independent TX and RX Clocks Supports Time Division Multiplexing TDM Inter IC Sound 125 and Similar Formats Supports Digital Audio Interface Transmission SPDIF IEC60958 1 and AES 3 Formats e FIFO Buffers for Transmit and Receive 256 Bytes Up to Six UARTs e All UARTs Support IrDA and CIR Modes e All UARTs Support RTS and CTS Flow Control UART1 Supports Full Modem Control Up to Five Master and Slave McSPI Serial Interfaces McSPIO McSPI2 Supports Up to Four Chip Selects McSPI3 McSPI4 Supports Up to Two Chip Selects Up to 48 MHz One 5 e Supports eXecute In Place XIP from Serial NOR FLASH One Dallas 1 Wiree HDQ Serial Interface Up to Three MMC SD and SDIO Ports 1 4 and 8 Bit MMC SD and SDIO Modes 1 8 or 3 3 V Operation on All Ports Up to 48 MHz Clock e Support
18. 3 72 GND Ground Power Power 85 93 96 101 106 108 118 121 130 165 185 200 202 203 204 GNDA ADC 112 Ground 5 Absolute Maximum Characteristics 80 VAR SOM AM43 SYSTEM ON MODULE 6 Operating Characteristics 6 1 Normal Operational Conditions Unless otherwise specified all DC and AC specifications in this data sheet are valid for the following voltages and temperature ranges 6 2 Power Consumption wem 6 3 DC Electrical Characteristics LVCMOS pins VDDSHVx 3 3 V x 1 11 wo Ls el L Analog 105 AIN 0 7 81 VAR SOM AM43 SYSTEM ON MODULE PWRONRSTn VDDSHV3 1 8 V or 3 3 V 1 Aaa itl Typ SUPPLY NAME DESCRIPTION USB1 VBUS 0 000 5 000 5 250 comparator input 0581 ID Voltage range for the USB ID input 1 This terminal is connected to analog circuits in the respective USB PHY The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 or greater than 100 k Q The terminal should be connected to ground for USB host operation or open circuit for USB peripheral operation and should never be connected to any external voltage source 82 VAR SOM AM43 SYSTEM ON MODULE 7 Environmental Specifications Commercial Operating temperature Industrial Operating tempera
19. 3 SYSTEM ON MODULE 11 Ordering Information Please refer to www variscite com 12 Warranty Terms Variscite guarantees hardware products against defects in workmanship and material for a period of one 1 year from the date of shipment Your sole remedy and Variscite s sole liability shall be for Variscite at its sole discretion to either repair or replace the defective hardware product at no charge or to refund the purchase price Shipment costs in both directions are the responsibility of the customer This warranty is void if the hardware product has been altered or damaged by accident misuse or abuse 12 1 Disclaimer of Warranty THIS WARRANTY IS MADE IN LIEU OF ANY OTHER WARRANTY WHETHER EXPRESSED OR IMPLIED OF MERCHANTABILITY FITNESS FOR A SPECIFIC PURPOSE NON INFRINGEMENT OR THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION EXCEPT THE WARRANTY EXPRESSLY STATED HEREIN THE REMEDIES SET FORTH HEREIN SHALL BE THE SOLE AND EXCLUSIVE REMEDIES OF ANY PURCHASER WITH RESPECT TO ANY DEFECTIVE PRODUCT 12 2 Limitation on Liability UNDER NO CIRCUMSTANCES SHALL VARISCITE BE LIABLE FOR ANY LOSS DAMAGE OR EXPENSE SUFFERED OR INCURRED WITH RESPECT TO ANY DEFECTIVE PRODUCT IN NO EVENT SHALL VARISCITE BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES THAT YOU MAY SUFFER DIRECTLY OR INDIRECTLY FROM USE OF ANY PRODUCT 86 VAR SOM AM43 SYSTEM ON MODULE 13 About Variscite For over a decade Variscite has developed produce
20. 4 1 Overview This chapter describes in detail the VAR SOM AM43 interfaces referring to the default SoM pin names However many additional interfaces are available when different pin modes are selected by the user PinMux Table 3 2 details the additional possible options for each pin on the VAR SOM AM43 connectors The following list describes this chapter s column header tables Signal VAR SOM AM43 original pin name Pin Pin Number on the SO DIMM204 connector Iype Pin Type amp Direction n O Out DS Differential Signal A Analog P Power Pin Description Short Pin functionality description 4 2 Display Interfaces The general features of the DSS module include Display Controller Display Modes e Programmable pixel memory formats Palletized 1 2 4 8 bit per pixel RGB 16 and 24 bit per pixel and YUV 4 2 2 Programmable display size up to 2048 x 2048 e 256 x 24 bit entries palette in RGB e Programmable pixel rate up to 80 MHz Display Support Four types of displays are supported Passive and Active colors Passive and Active monochromes e 4 8 bit Monochrome Passive panel interface support 15 grayscale levels supported using dithering block RGB 8 bit Color Passive panel interface support 3 375 colors supported for color panel using dithering block RGB 12 16 18 24 bit Active panel interface support replicated or dithered encoded pixel values e
21. 4 24 48 18 GPIOO 23 83 1723 GPIO2 22 74 B23 GPIO4 25 50 18 GPIOO 25 65 F25 GPIO2 23 73 23 26 194 AE19 GPIOO 30 131 A2 GPIO2 24 78 A22 GPIO4 27 196 AD19 GPIOO 31 151 GPIO2 25 76 A24 GPIO4 28 190 AE20 GPIO1 011 195 B5 GPIO2 26 143 B1 4 29 192 AD20 1 1 193 GPIO2 27 140 B2 GPIO5 0 8 H22 GPIO1 211 191 B6 GPIO2 28 139 C2 GPIO5 1 K24 1 31 189 GPIO2 29 147 C1 GPIO5 2 4 H25 1 40 177 B7 GPIO2 30 141 D1 5 3 2 H24 GPIO1 51 181 7 GPIO2 31 145 D2 GPIO5 4 56 25 GPIO1 61 183 GPIO3 5 184 AB24 GPIOS 5 148 R24 GPIO1 7 169 B8 GPIO3 6 182 Y22 GPIOS 6 149 P24 GPIO1 8 61 L25 GPIO3 13 65 F25 GPIOS 8 114 D25 GPIO1 9 64 125 GPIO3 14 54 N24 5 9 63 F24 GPIO1 10 66 K25 GPIO3 15 92 N22 5 13 115 E24 GPIO1 11 67 124 GPIO3 16 125 H23 5 19 32 AE18 GPIO1 12 116 E11 GPIO3 17 58 M24 5 20 46 18 70 VAR SOM AM43 SYSTEM ON MODULE GPIO1 16 11 21 60 14 GPIO5 30 131 2 0118 7 23 90 120 07 6 25 83 723 J 6 10121 1 1 Note The following pins GPMC Bus signal internally used and routed to the external connector They can be configured and used as GPIOs only when NAND is not in use 4 15 PWMO The SOM uses PWMO output for control the LCD backlight PWM
22. 5 MMC SD SDIO The general features of the MMCSD host controller IP are Built in 1024 byte buffer for read or write Two DMA channels one interrupt line Clock support 96 MHz functional clock source input upto 384Mbit sec 48MByte sec in MMC mode 8 bit data transfer upto 192Mbit sec 24MByte sec in High Speed SD mode 4 bit data transfer up to 24Mbit sec 3MByte sec in Default SD mode 1 bit data transfer Support for SDA 3 0 Part A2 programming model e Serial link supports full compliance with MMC command response sets as defined in the MMC standard specification v4 3 5 command response sets as defined in the SD Physical Layer specification v2 00 _ 500 command response sets and interrupt read wait suspend resume operations as defined in the SD part E1 specification v 2 00 50 Host Controller Standard Specification sets as defined in the SD card specification Part A2 v2 00 4 5 1 MMCO Signals SDMMCO Interface signals AM437X SIGNAL NAME DESCRIPTION Valid configuration PINs T SOWP SD Card Write Protect 40 40 40 20 MIMCO POW SD Card Power Switch Control 52 117 68 52 17 4 5 2 1 Signals SDMMC1 Interface signals AM437X SIGNAL NAME DESCRIPTION Valid configuration PINs MMC1_CLK MMC SD SDIO Clock MMC1_CMD MMC SD SDIO Command 1 DATO MMC SD SDIO Data Bus 194 MMC1_DAT1 MMC SD SDIO Data Bus 196 1 DAT2 MMC SD SDI
23. Byte Block Error Location Based on BCH Algorithms Programmable Real Time Unit Subsystem and Industrial Communication Subsystem PRU ICSS Supports Protocols such as EtherCATe PROFIBUS PROFINET and EtherNet IP EnDat 2 2 and More Two Programmable Real Time Units PRUs Subsystems Each core is a 32 Bit Load and Store RISC Processor Capable of Running at 200 MHz 11 VAR SOM AM43 SYSTEM ON MODULE 12KB PRU ICSS1 4KB PRU ICSSO of Instruction RAM with Single Error Detection Parity 8KB PRU ICSS1 4KB PRU ICSSO of Data RAM with Single Error Detection Parity Single Cycle 32 Bit Multiplier with 64 Bit Accumulator e Enhanced GPIO Module Provides Shift In and Shift Out Support and Parallel Latch on External Signal 12KB PRU ICSS1 only of Shared RAM with Single Error Detection Parity Three 120 Byte Register Banks Accessible by Each PRU Interrupt Controller Module INTC for Handling System Input Events Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU ICSS Peripherals Inside the PRU ICSS e One UART Port with Flow Control Pins Supports Up to 12 Mbps e One Enhanced Capture eCAP Module Two Ethernet Ports that Support Industrial Ethernet such as EtherCAT e One MDIO Port Industrial Communication is Supported by Two PRU ICSS Subsystems Power Reset and Clock Management PRCM Module Controls the Entry and Exit of Deep Sleep Modes Responsible for Sleep Sequ
24. CAMERA1 data bus Media dependent interface 1 Plus 23 Ball E7 H24 D7 H25 A4 K24 C6 H22 E8 C3 F6 AE21 C5 AE24 D8 AD25 G8 B4 AD23 23 25 23 25 AD22 AE22 11 AE18 12 AD21 AC21 14 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 SYSTEM ON MODULE 1 MDI B M ETH MDIO GND ETH MDIO C P GND MDI C M 1 GND CAM1_DATA10 MDI D P 1 DATA11 MDI D M AM437X_MMCO_SDCD GND MCASPO ACLKX SPI1 SCLK LED ACT GPIOS 4 LED LINK 1000 MCASPO AHCLKR 5 1 CSO LED LINK 10 100 MCASPO AHCLKX UARTO CTSN MCASPO AXR1 437 USBO VBUS DET UARTO RTSN AM437X_USB1_DRVVBUS UARTO_RXD UARTO_TXD AM437X_LCD_BACKLIGHT 2 1 SDA 2 1 SCL UART2 TXD GPIOO 3 GND AM437X LCD 437 LCD VSYNCSI 437 LCD DATAOSI 437 LCD AC BIAS I ODS Power I O I ODS Power I ODS Power I ODS I ODS Power I O I O I O I O I O I O I O Power data bus Media dependent interface 1 Minus MII Management CLK Digital GND Mil Management DATA Media dependent interface 2 Plus Digital GND Media dependent interface 2 Minus data bus Digital GND CAMERA1 data bus Media dependent interface 3 Plus data bus Media dependen
25. D tiva Negative Reference 69 SYSTEM ON MODULE 4 14 General Purpose I O The SOM provides IO pins which can be used as GPIOs GPIO signals SIGNAL SIGNAL SIGNAL NAME PIN BALL NAME PIN BALL NAME PIN BALL GPIOO 2 62 M25 1 22 9 E8 GPIO4 1 197 AD18 GPIOO 2 86 P23 GPIO1 23 12 F6 4 2 186 AC18 GPIOO 3 22 GPIO1 24 22 F7 GPIO4 3 201 AD17 GPIOO 3 60 L24 GPIO1 25 20 B4 GPIO4 4 187 AC20 GPIOO 4 69 721 GPIO1 26 18 G8 GPIO4 5 198 AB19 GPIOO_5 70 720 GPIO1 27 16 D8 GPIOA 6 188 AA19 GPIOO 6 52 R25 GPIO2 21 154 A9 GPIO4 7 179 AC24 GPIOO 7 68 624 2 34 138 E10 GPIOA 8 173 AD24 GPIOO 8 142 C19 GPIO2 4 167 010 GPIO4 9 17 AD25 GPIOO 9 133 019 2 5 109 C10 GPIO4 10 26 23 GPIOO 10 146 C17 GPIO2 6 75 B22 11 13 21 11 144 017 GPIO2 7 80 21 4 12 27 25 GPIOO 12 124 K22 GPIO2 8 77 B21 GPIO4 13 25 25 GPIOO 13 120 122 GPIO2 9 132 C21 14 38 20 GPIOO 14 111 K21 GPIO2 10 82 20 15 36 21 GPIOO 15 119 121 GPIO2 11 79 20 GPIO4 16 34 021 18 98 621 2 12 127 C20 17 30 22 GPIOO 18 117 123 GPIO2 13 128 E19 4 18 28 AD22 GPIOO 19 122 K23 GPIO2 14 126 A19 GPIO4 19 23 GPIOO 20 84 P22 GPIO2 15 81 B19 4 20 21 AD23 GPIOO 21 90 P20 GPIO2 16 123 A18 GPIO4 21 15 AE24 GPIOO 22 94 N20 2 17 129 B18 GPIO
26. E Includes Concurrent Operation and Built In Coexisting and Prioritization Handling of Bluetooth BLE and WLAN Dedicated Audio Processor Supporting SBC Encoding A2DP Up to 100 Mbps Throughput and Up to 1 4X the Range Versus a Single Antenna Configuration With 2X2 MIMO 40 MHz Channel Bandwidth and MRC Lowest Wi Fi Power Consumption in Connected Idle lt 800 uA 2 6 TPS65218 PMIC The Texas Instrument s TPS65218 is an integrated power management IC dedicated to applications processors as the 437 The device provides BATTERY BACKUP SUPPLIES e Two low quiescent current high efficiency step down converters for battery backup domain DCDC5 1 0V output DCDCo 1 8V output VIN range from 2 2V to 5 5V e be 7supplied from system power or coin cell backup battery BUCK CONVERTERS DCDC1 2 3 e Three adjustable step down converter with integrated switching FETs DCDC1 1 1V default up to 1 8A Core DCDC2 1 1V default up to 1 8A MPU DCDC3 1 2V default up to 1 8A DDR e VIN range from 2 7V to 5 5V e Adjustable output voltage range 0 85V 3 5V 100 Duty Cycle for Lowest Dropout LOW VOLTAGE LOAD SWITCH LS1 VIN range from 1 2V to 3 3V e 350mA current limit 110mBl max switch impedance 1 35 HIGH VOLTAGE LOAD SWITCH LS3 e VIN range from 1 8V to 10 0V 100mA 500mA selectable current limit e 500mBl max switch impedance SUPERVISOR e Built in supervisor function monit
27. EIVE DATA VALID ese PRI RXLINK MII RECEIVE LINK 10 624 109 115 PRI TXD1 MII TRANSMIT DATA 1 OS _PRL_MIL TXD3 MITRANSMITDATABIT3 O 6 7 PRI MRLCIK MII RECEIVE CLOCK 10 6 192 PRU ICSS1 UARTO Signals SIGNAL NAME DESCRIPTION TYPE ZDN PIN 0 PRI UARTO CTS UART CLEAR TO SEND K22 P23 124 86 UART RECEIVE DATA ao QT 78 VAR SOM AM43 SYSTEM ON MODULE 4 18 The SoM includes JTAG interface to provide a debug and test control Seven signals are routed from the APQ directly to 1 27 pitch 5x2 pin header Sullins P N GRPBOS2VWVN RC or compatible JTAG Signals AM437x SIGNAL NAME ZDN BALL DESCRIPTION aes Ground Power 1 NDC round Power 15 JTAG MUI MISCEMULAMONPIN 7 system Reset 9 4 19 Wi Fi and Bluetooth The VAR SOM AM43 contains a certified high performance WL183xMOD 2 4 5 GHz IEEE 802 11 a b g n Bluetooth 4 0 BLE module The module has two antennas connections through U FL JACK connectors Antenna cable connected to module must have 50 Q impedance 79 VAR SOM AM43 SYSTEM ON MODULE 4 20 Power 4 20 1 Power Supply pins Power Signals TPS65218 and EDGE SIGNAL NAME AM437x pins DESCRIPTION CONNECTOR VBAT Power input for PMIC VIN and 100 102 103 V3 3SW voltage 104 105 107 VDDA ADC AB12 ADCO Power supply Output 4 20 2 GND pins GND Pins EDGE 10 19 24 29 35 41 44 47 5
28. IFO based packet buffer structure Four priority level QOS support 802 1p e CPPI 3 1 compliant DMA controllers e Support for IEEE 1588v2 Clock Synchronization 2008 Annex D E and F Timing FIFO and time stamping logic inside the SS e Device Level Ring DLR Support e Address Lookup Engine 1024 addresses plus VLANs Wire rate lookup VLAN support Host controlled time based aging Spanning tree support 53 VAR SOM AM43 SYSTEM ON MODULE 12 address lock and L2 filtering support MAC authentication 802 1x Receive or destination based Multicast and Broadcast limits MAC address blocking Source port locking QUI host accept deny feature e Flow Control Support 802 3x e EtherStats and 802 3Stats RMON statistics gathering shared e Support for external packet dropping engine e CPGMAC SL transmit to CPGMAC SL receive Loopback mode digital loopback supported e CPGMAC SL receive to CPGMAC SL transmit Loobback mode FIFO loopback supported e Maximum frame size 2016 bytes 2020 with VLAN e 8k 2048 x 32 internal CPPI buffer descriptor memory e MDIO module for PHY Management e Programmable interrupt control with selected interrupt pacing e Emulation Support e Programmable transmit Inter Packet Gap IPG e Reset isolation 4 3 1 On board 1G PHY The onboard Ethernet PHY AR8033 exports the differential pairs to the edge connector 11 pins for signals 5 pins for GND between the differential pai
29. IN AE23 23 PR1 EDIO OUTVALID DATA OUT VALID O AD18 197 1 EDIO SOF START OF FRAME O AB25 254159 PRU ICSS1 MDIO Signal SIGNAL NAME DESCRIPTION TYPE ZDN PIN PRI MDIO DATA MDIO DATA lO 17 42 PRI MDCLK MDIO CLK O B17 40 PRU ICSS1 MIIO Signals SIGNAL NAME DESCRIPTION TYPE ZDN PIN PRI COL MII COLLISION DETECT D25 114 PRI CRS MII CARRIER SENSE B12 G20 NO PRI RXDO MII RECEIVE DATA BIT O B18 129 PRI RXD1 MII RECEIVE DATA BIT 1 18 123 RXD2 RECEIVE DATA 2 B19 81 PRI RXD3 MII RECEIVE DATA BIT 3 A19 126 PRI RXDV MII RECEIVE DATA VALID D17 144 PRI RXER MII RECEIVE DATA ERROR D19 133 RXLINK RECEIVE LINK C19 142 PR1 MIIO TXDO MII TRANSMIT DATA BIT O O B11 B20 135 79 PR1 MIIO TXD1 MII TRANSMIT DATA BIT 1 O A20 C11 82 150 PRI TXD2 MII TRANSMIT DATA BIT 2 O C21 E11 32 PRI TXD3 MII TRANSMIT DATA BIT 3 O B21 D11 77 PRI TXEN MII TRANSMIT ENABLE O A21 Fil 80 MII RECEIVE CLOCK 146 MII TRANSMIT CLOCK B10 B22 75 PR1 MII MRO CLK PR1 MII MTO CLK PRU ICSS1 MII1 Signals SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1 MII1 COL MII COLLISION DETECT F24 63 PR1 MII1 CRS MII CARRIER SENSE A2 131 PR1 MII1 RXDO MII RECEIVE DATA BIT O D8 16 PR1 MII1 RXD1 MII RECEIVE DATA BIT 1 G8 18 77 VAR SOM AM43 SYSTEM ON MODULE RECEIVE DATA 2 PRI RXDV MII REC
30. K22 125 MCASPO AXRO SPI1 D1 I O McASPO Serial Data IN OUT H23 126 437 LCD DATAS I O LCD data A19 127 AM437X LCD DATAG O LCD data C20 128 AM437X LCD DATA7P O LCD data E19 129 AM437X LCD DATA115 O LCD data B18 130 GND Power Digital GND 131 GPIOO 304117 I O General Purpose Input output see notes HI A2 132 AM437X LCD O LCD data C21 133 AM437X LCD DATA135 O LCD data D19 134 VDDSHV11 Power Power Domain VDDSHV9 and VDDSHV11 135 GPIO1 147 VO General Purpose Input output B11 136 AM437X AIN5 A Analog input AC13 137 GPIO1 15 VO General Purpose Input output A11 138 GPIO2 3 I O General Purpose Input output see note 11 E10 139 AM437X MMCO DAT1 MMC SD SDIO data bus C2 140 AMA37X MMCO DAT2 I O MMC SD SDIO data bus B2 141 AM437X_MMCO_CLK O MMC SD SDIO clock D1 142 AM437X LCD DATA12P O LCD data C19 143 AMA37X MMCO DAT3 I O MMC SD SDIO data bus B1 144 AM437X LCD 15 O LCD data D17 145 437 MMCO I O MMC SD SDIO command D2 146 AM437X_LCD_DATA14 O LCD data C17 147 437 MMCO DATO I O MMC SD SDIO data bus C1 148 GPIO5 517 I O General Purpose Input output R24 149 GPIO5 6 VO General Purpose Input output P24 150 GPIO1 1317 I O General Purpose Input output C11 151 GPIOO 314117 I O General Purpose Input output see notes HI B3 152 AM437X AIN2 A Touch screen Y plus analog Y13 153 MIC IN L Al MIC3 input 11 154 GPIO2 2 I O
31. M43 SYSTEM ON MODULE LCD Display Up to 1400x1050 Parallel 24 Bit RGB interface Capacitive touch panel and 4 5 wire resistive touch panel interface On board 10 100 1000 Mbps Ethernet PHY Second 10 100 1000 Mbps Ethernet RGMII Interface Certified WLAN 802 11 a b g n module with optional MIMO Bluetooth 4 0 BLE USB 1x USB 2 0 host with integrated PHY 1x USB 2 0 OTG with integrated PHY 2 x CAN bus Serial interfaces 4xSPI 2 5xUART HDQ 1 Wire QSPI Camera input 12bit Audio 1 stereo line in 1 stereo line out 1x stereo Digital Microphone in 1 stereo Analog Microphone in Multichannel Audio Serial Port McASP 8 x ADC inputs Backlight PWM Single 3 3 V power supply 67 6 mm x 38 6 mm x 3 mm DDR3 SODIMM 204pins footprint VAR SOM AM43 SYSTEM ON MODULE 1 3 VAR SOM AM43 Block Diagram SO DIMM VAR SOM AM43 204 Pin POWER In 24 bit LCD 24 bit LCD 4 wire Touch ADCO 8ch Backlight eCAPO BUNT Parallel Cam 1 FEE I2CO HOST USB HOST OTG JTAG EMAC1 USB OTG G Ethemet RGMII2 SD MMC2 MCASPO McASPO UART3 DMIC Analog Mi Linel Line Ou D Audio 1 1 1 Audio CANO 1 2x CAN BU GPIO GPIO Up to 3x MMC Up to 5xSPI Up to 5x UART Up to 2 5 10 1 2 3 4 POWER VIO Out UARTO 1 2 3 5 SD MMC0 1
32. MII2 101 UART3 RXD RGMII2 1021 UART3 RTS RGMII2 31 UART3 CTS RGMII2 GND RGMII2 TCTLU 7 RGMII2 7 1 PCLK RGMII2_RCTL M 1 DATA7 RGMII2 RDOH 7 1 HSYNC RGMII2 RD1E U GND RGMII2_RD2 P 1 RGMII2 CAMI 5 GND CAM1_WEN_GPIO4_13 CAM1_VSYNC CAM1_FIELD_GPIO4_12 CAM1_DATA4 GND CAM1_DATA3 MDI A P CAMI DATA9 MDI A M 1 DATA2 GND 1 DATA1 MDI B P 3 1 SoM Connector Pin out Type O O O Power Power Power 005 005 Power 005 Pin Group Function RGMII Transmit Data bit 0 UART Transmit Data RGMII Transmit Data bit 1 UART Receive Data RGMII Transmit Data bit 2 UART Request to Send RGMII Transmit Data bit 3 UART Clear to Send RGMII Transmit Clock Digital GND RGMII Transmit Control RGMII Receive Clock CAMERA1 Data Pixel Clock RGMII Receive Control CAMERA1 data bus RGMII Receive Data bit O Data Horizontal Detect RGMII Receive Data bit 1 Digital GND RGMII Receive Data bit 2 data bus RGMII Receive Data bit 3 CAMERA1 data bus Digital GND Data Write Enable Data Vertical Detect Data Field Indicator data bus Digital GND CAMERA1 data bus Media dependent interface 0 Plus data bus Media dependent interface 0 Minus CAMERA1 data bus Digital GND
33. O Data Bus 190 57 VAR SOM AM43 SYSTEM ON MODULE 4 5 3 MMC Signals SDMMC2 Interface signals AM437X MMC2_CLK MMC SD SDIO Clock MMC2 DATO MMC SD SDIO Data Bus 58 VAR SOM AM43 SYSTEM ON MODULE 4 6 Audio 4 6 1 TLV320AIC3106 Audio codec Audio interfaces are featured by an on board Texas Instrument s feature rich TLV320AIC3106 audio codec device Please refer to the TLV320AIC3106 data sheet for detailed electrical characteristics of relevant interfaces Main supported features are e Stereo line in e Stereo line out e Stereo headphones driver e Digital microphone Analog microphone Audio interface Signals SIGNAL NAME CODEC PIN amp DESCRIPTION O PINE LINEOUT_RP RIGHT LINE OUTPUT MIC_IN_R MIC3 INPUT RIGHT MICROPHONE BIAS MICBIAS VOLTAGE OUTPUT LINE1 ANALOG LEFT LINEIN1 LP INPUT DIGITAL MICROPHONE 178 4 6 2 MCASPO Multichannel Audio Serial Port The interface is shared with the on board Wi Fi module MCASPO Signals AM437X SIGNAL NAME ZDN BALL DESCRIPTION PINE MCASPO_ACLKX McASPO Transmit Bit Clock McASPO Serial Data 2 12 IN OUT 59 VAR SOM AM43 SYSTEM ON MODULE 4 7 Camera 4 7 1 Camera interface 0 The general features of the VPFE module include e A buffer memory for interfacing to the DMA at the chip level and preventing the CCDC module from overflowing Support for conventional Baye
34. O as qdin1 as in e Programmable transfer or frame size No of words from 1 to 4096 e Optional interrupt generation on word or frame completion e Programmable CS to DOUT delay from 0 to DCLKs e Programmable signal polarities e Programmable active clock edge e Software controllable interface allowing for any type of SPI transfer e Control through OCP configuration port access 65 VAR SOM AM43 SYSTEM ON MODULE QSPI signals AM437X SIGNAL asme QSPI DO SPI Data 194 QSPI 02 SPI Data 190 4 11 2 The general features of the I2C controller are e Compliant with Philips I2C specification version 2 1 e Supports standard mode up to 100K bits s and fast mode up to 400K bits s e Multimaster transmitter slave receiver mode e Multimaster receiver slave transmitter mode Combined master transmit receive and receive transmit modes e 7 bit and 10 bit device addressing modes Built in 32 byte FIFO for buffered read or writes in each module e Programmable clock generation e Two DMA channels one interrupt line The SOM includes three I2C I F 2 0 is used for on SOM devices and also routed to the external connector 2 signals SIGNAL NAME DESCRIPTION PIN PERIPHERAL ADDRESS 2 0 SCL I2C Clock PMIC 0X00100100 CODEC 0 0011011 I2C1 signals oo TE 2 2 signals AM437X SIGNAL NAME DESCRIPTION ESENSSE NEN
35. O signals AM437X SIGNAL NAME ZDN BALL DESCRIPTION PINE AM437X_LCD_BACKLIGHT Auxiliary PWMO output 68 71 VAR SOM AM43 SYSTEM ON MODULE 4 16 General System Control 4 16 1 Boot Options Boot Mode is selected via Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin DSS DATA 15 0 terminals are respectively SYSBOOT 15 0 inputs 055 VSYNC terminal is SYSBOOT 16 input DSS HSYNC terminal is SYSBOOT 17 input DSS AC BIAS EN is SYSBOOT 18 input All the pins routed out for SYSTEM BOOT configuration on the rising edge of PWRONRSTn Boot Sequence configuration signals Configuration PINS Value Description BOOT SEQUENCE NAND USB1 MMCO USBO BOOT_SEQUENCE MMC1 MMCO USB1 USBO SYSBOOT 4 0 SYSBOOT 6 E Ob ECC DONE BY ROM 1b ECC DONE BY SYSBOOT 8 _ Ob FOR NAND WAIT MUX OPTION 0 SYSBOOT 11 1B MUXED DEVICE SYSBOOT 15 14 01b 24MHZ CLOCK SYSBOOT 18 5 4 16 2 System Control The signal AM437X_PORZn reset input of the SOM The signal SYS_RESETn produce reset to all internal SOM and external devices in case program reset or manual reset from AM437X_PORZn Power Control signals TPS65218 SIGNAL NAME and DESCRIPTION AM437x pins CONNECTOR AMA37X PORZN 23 8 Power on Reset Output of PMIC and Input of 175 SOM from External Reset 72 4 17 PRU ICSS SYSTEM ON MODULE 4 17 1 PRU ICSSO Interface PRU ICSSO PRUO Ge
36. P power saving scheme e Supports IEEE 802 3az Energy Efficient Ethernet e Supports SmartEEE which allows MAC SoC devices without 802 3az support to function as the complete 802 3az system e Supports Wake on LAN WoL to detect magic packet and notify the sleeping system to wake up e Fully integrated digital adaptive equalizers echo cancellers and Near End Crosstalk NEXT cancellers e Supports Synchronous Ethernet with selectable recovered clock output e Robust Cable Discharge Event CDE protection of 6 kV n Error free operation over up to 140 meters of CAT5 cable e Automatic channel swap ACS e Automatic MDI MDIX crossover e Automatic polarity correction e EEE 802 3u compliant Auto Negotiation 18 VAR SOM AM43 SYSTEM ON MODULE e Jumbo Frame support up to 10KB full duplex e Multiple loopback modes for diagnostics n Robust Surge Protection with 750 V differential mode and 4 kV common mode Cable Diagnostic Test CDT e Single power supply 3 3V optional for external regulator for core voltage n 6mm x 6mm 48 pin QFN package e Industry temperature I temp option available 2 4 Audio codec via the TLV320AIC3106 The Texas Instrument s TLV320AIC3106 is low power highly integrated stereo audio codec Extensive register based power control is included enabling stereo 48 kHz DAC playback as low as 15mW VAR SOM AM43 exposes most of the audio interfaces of the TLV320AIC3106 e Stereo Audio DAC 102 dBA S
37. RU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 DATA IN PRU ICSSO PRU1 General Purpose Outputs Signals SIGNAL NAME PRO PRU1 GPOO PRO PRU1 GPO1 PRO PRU1 GPO10 DESCRIPTION PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT 74 O O O H24 H23 M24 L23 K23 M25 L24 B1 B2 ZDN AD24 AD25 AD21 AE22 AD22 AE23 AD23 AE24 AE18 AB18 H22 K24 AC23 AE21 K25 J24 B23 A23 A22 A24 ZDN AD24 AD25 AD21 125 58 117 122 62 60 143 140 PIN 173 17 34 30 28 23 21 15 32 46 26 13 66 67 74 73 78 76 SYSTEM ON MODULE PRO PRU1 GPO11 PRO PRU1 GPO12 PRO PRU1 13 PRO PRU1 GPO14 PRO PRU1 15 PRO PRU1 GPO16 PRO PRU1 GPO17 PRO PRU1 GPO18 PRO PRU1 GPO19 PRO PRU1 GPO2 PRO PRU1 GPO3 PRO PRU1 4 PRO PRU1 GPO5 PRO PRU1 GPO6 PRO PRU1 GPO7 PRO PRU1 PRO PRU1 GPO9 PRU ICSSO UARTO Signals SIGNAL NAME PRO UARTO CTS N PRO UARTO RTS N PRO UARTO RXD PRO UARTO TXD PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO PRU1 DATA OUT PRU ICSSO P
38. RU1 DATA OUT DESCRIPTION UART CLEAR TO SEND UART REQUEST TO SEND UART RECEIVE DATA UART TRANSMIT DATA 4 17 2 PRU ICSS1 Interface PRU ICSS1 PRUO General Purpose Inputs Signals SIGNAL NAME PR1 PRUO GPIO PR1 PRUO GPI1 PR1 PRUO GPI10 PRI PRUO GPI11 PR1 PRUO GPI16 PR1 PRUO GPI2 PRI PRUO GPI3 PRI PRUO 14 PRI PRUO 5 DESCRIPTION PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN CAPTURE ENABLE PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN PRU ICSS1 PRUO DATA IN 75 AE22 AD22 AE23 AD23 AE24 AE18 AB18 H22 K24 AC23 AE21 K25 J24 B23 A23 A22 A24 ZDN P23 122 T21 T20 ZDN B22 A21 E11 C11 30 28 23 21 15 32 46 26 13 66 67 74 73 78 76 PIN 86 y 69 70 B11 C24 D24 K21 L21 B21 C21 A20 B20 PIN 75 80 116 150 e 119 135 77 132 82 79 SYSTEM ON MODULE 76 PRI PRUO GPI6 PRU ICSS1 PRUO DATA IN C20 127 PRI PRUO PRU ICSS1 PRUO DATA IN E19 128 PR1 PRUO GPI8 PRU ICSS1 PRUO DATA IN B9 NO PR1 PRUO GPI9 PRU ICSS1 PRUO DATA IN F10 NO PRU ICSS1 PRUO General Purpose Outputs Signals SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1 PRUO GPOO PRU ICSS1 PRUO DATA OUT O B22 15 PRI PRUO GPO1 PRU ICSS1 PRUO DATA OUT O A21 80 PRI PRUO PRU ICSS1 PRUO DATA O
39. UT O E11 116 PR1 PRUO GPO11 PRU ICSS1 PRUO DATA OUT O C11 150 PR1 PRUO GPO2 PRU ICSS1 PRUO DATA OUT O B21 77 PRI PRUO GPO3 PRU ICSS1 PRUO DATA OUT O 21 132 1 PRUO GPO4 PRU ICSS1 PRUO DATA OUT O A20 82 PR1 PRUO GPO5 PRU ICSS1 PRUO DATA OUT O B20 79 PR1 PRUO GPO6 PRU ICSS1 PRUO DATA OUT O C20 127 PRI PRUO GPO7 PRU ICSS1 PRUO DATA OUT O ES 128 PRI PRUO 8 PRU ICSS1 PRUO DATA OUT O B9 NO PR1 PRUO GPO9 PRU ICSS1 PRUO DATA OUT O F10 NO PRU ICSS1 eCAP Signal SIGNAL NAME DESCRIPTION TYPE ZDN 1 ECAP CAP ENHANCED CAPTURE INPUT OR lO 11 G24 137 68 PRU ICSS1 ECAT Signal SIGNAL NAME DESCRIPTION TYPE ZDN PIN PR1 LATCHO IN DATA IN AE22 K22 30 124 PRI EDC 1 1 DATA IN AD22 L22 28 120 PRI EDC SYNCO OUT DATA OUT O L25 61 PRI EDC SYNCI OUT DATA OUT O J25 64 PRI EDIO DATA INO DATA IN AD23 21 PR1 EDIO DATA IN1 DATA IN AE24 15 PR1 EDIO DATA IN2 DATA IN B23 74 PR1 EDIO DATA IN3 DATA IN A23 73 PRI EDIO DATA INA DATA IN A22 78 PR1 EDIO DATA 5 DATA IN A24 76 1 EDIO DATA IN6 DATA IN B9 C20 120 PR1 EDIO DATA IN7 DATA IN E19 128 PRI EDIO DATA OUT DATA OUT O mi 69 PRI EDIO DATA OUT DATA OUT O T20 70 SYSTEM ON MODULE 1 EDIO DATA OUT DATA OUT O B23 74 PRI EDIO DATA OUT DATA OUT O A23 73 1 EDIO DATA OUT DATA OUT O A22 78 PRI EDIO DATA OUT DATA OUT O A24 76 PRI EDIO DATA OUT DATA OUT O B9 C20 120 PRI EDIO DATA OUT DATA OUT O ES 128 PR1 EDIO LATCH IN LATCH
40. VAR SOM AM43 SYSTEM ON MODULE Mariscite VARISCITE LTD VAR SOM AMA43 v1 1 Datasheet Texas Instruments Sitara AM437x based System on Module T MEN SOM lt AM43 Vi T 4 T ABCDEFGHIJKLMNPRT d 9 18SBMOD 264 0 WLTIBSBMOD m 2 24510 768751800 31 ECC ID iC ariscite gt Modal 1 18 MODGS e t E i gt 1 mba I me jes j LI 156 d Fa i ar wot das 29193113927 a ra Sun i 12727 icc sis RR T r T 4 1 3 a e 5 VAR SOM AM43 SYSTEM ON MODULE VARISCITE LTD VAR SOM AM43 Datasheet 2015 Variscite Ltd All Rights Reserved No part of this document may be photocopied reproduced stored in a retrieval system or transmitted in any form or by any means whether electronic mechanical or otherwise without the prior written permission of Variscite Ltd No warranty of accuracy is given concerning the contents of the information contained in this publication To the extent permitted by law no liability including liability to any person by reason of negligence will be accepted by Variscite Ltd its subsidiari
41. Vertical Synchronization VSync embedded in a single signal TE or using two signals HS VS Data formats e Programmable pixel memory formats 12 16 18 and 24 bit per pixel modes in RGB format e Programmable output formats on one multiple cycles per pixel data from Display controller and from L4 TDM The VAR SOM AM43 provides the logic to display a video frame from the memory frame buffer on a LCD panel using an up to 24 bit parallel RGB bus DSI signals SIGNALNAME Description type des date0 7 o des date2 o 12 82 o dss deres 79 0 dare 6 o 52 VAR SOM AM43 SYSTEM ON MODULE 1 dos datal0 123 142 dos datal 148 o 179 o _ 201 o dos data22 197 tc dataR6 o 78 LCD pinelclock hsyne 73 LCD horizontalsyne 0 ECAPO IN PWMO OUT 68 Backlight PWM 4 3 Ethernet The AM43 SOM includes two EMAC designed to support 10 100 1000 Mbps Ethernet IEEE 802 3 networks The general features of the ethernet switch subsystem are Two 10 100 1000 Ethernet ports with and RGMII interfaces e Wire rate switching 802 1d e Non Blocking switch fabric e Flexible logical F
42. cessful products Our Mission To innovate with future proof solutions well ahead of the market To provide comprehensive rapid and premier technical support throughout the design cycle To deliver a one stop shop for total System on Module solutions and design services 13 1 Contact Information Headquarters Variscite Ltd 4 Hamelacha St Lod P O B 1121 Airport City 70100 ISRAEL phone 972 9 9562910 fax 972 9 9589477 email info variscite com sales sales variscite com technical support support variscite com 87
43. d and manufactured a powerful range of System on Modules consistently setting market benchmarks in terms of speed and innovation The company s portfolio is based on leading SoC vendors including Texas Instruments Freescale and Marvell All Variscite production is performed at fully ISO 13485 compliant facilities satisfying international customer and regulatory requirements for a broad range of industries including medical devices and related services The company s production facilities are equipped with the most advanced SMT machines that ensure punctual deliveries and high quality products Having first entered the embedded market in 2003 with specialized designs for a variety of industrial applications Variscite has continued to innovate and be first to market Just some System on Module launch highlights include the release of the first Cortex A8 SOM back in 2009 and on 2011 Breaking the speed record again with the first OMAP4460 based 1 5GHz Cortex A9 System on Module It s no surprise that within a decade Variscite has taken a leading position in the design and manufacture of system on modules Variscite serves more than 1 500 customers in over 50 countries worldwide delivering a cost effective high performance portfolio that combines interface flexibility with advanced power management A trusted provider of development and consulting services for a variety of embedded platforms Variscite transforms clients visions into suc
44. encing Power Domain Switch Off Sequencing Wake Up oequencing and Power Domain Switch On Sequencing Clocks e Integrated High Frequency Oscillator Used to Generate a Reference Clock 19 2 24 25 and 26 MHz for Various System and Peripheral Clocks e Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption e Five ADPLLs to Generate System Clocks MPU Subsystem DDR Interface USB and Peripherals MMC and SD UART SPI 2 L3 L4 Ethernet GFX SGX530 and LCD Pixel Clock Power e Two Non Switchable Power Domains RTC and Wake Up Logic WAKE UP e Three Switchable Power Domains MPU Subsystem SGX530 GFX Peripherals and Infrastructure PER e Implements SmartReflex Class 2B for Core Voltage Scaling Based On Die Temperature Process Variation and Performance Adaptive Voltage Scaling AVS Dynamic Voltage Frequency Scaling DVFS Real Time Clock RTC Real Time Date Day Month Year and Day of Week and Time Hours Minutes and Seconds Information Internal 32 768 kHz Oscillator RTC Logic and 1 1 V Internal LDO Independent Power On Reset PWRONRSThn Input 12 VAR SOM AM43 SYSTEM ON MODULE Dedicated Input Pin RTC_WAKEUP for External Wake Events Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wake Up or Cortex A9 for Event Notification Programmable Alarm Can Be Used with External Output
45. es or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document Variscite Ltd reserves the right to change details in this publication without notice Product and company names herein may be the trademarks of their respective owners Variscite Ltd 4 Hamelacha Street Lod P O B 1121 Airport City 70100 ISRAEL Tel 972 9 9562910 Fax 972 9 9589477 VAR SOM AM43 SYSTEM ON MODULE Document Revision History 20 01 2015 VAR SOM AM43 SYSTEM ON MODULE Table of Contents Document Revision HIStONY ndan aaa u au enen e nese ses enen nene sene ses ese sere e mese ses eses sere e mesem eses se sene eses mese ses esesoeses 3 POUR NIS DOCU AT ja aa S Ra cH SEN ES IUE SEN 7 1 1 ONOR 7 L2 VAR SOM AMA43 Features 5 1 44 nennen nennen 7 B VAR SOM AMA3 Block Diagram i 9 2 Main Hardware Components use ioi seis vaa 10 2 1 TEXAS INSTRUMENTS AM437x 9 22 10 Beke OVET E es 10 CR 17 2 2 MEMORY aiar inni ci 18 uc S 18 2 2 2 Non volatile Storage Memory speca ae 18 2235 AS E E E T 18 2 CMM 18 2 2 5 n 18 22 Ethernet PHY 8033
46. hree 32 Bit Enhanced Capture Modules eCAP Upto Three Enhanced Quadrature Encoder Pulse Modules eQEP Up to Six Enhanced High Resolution PWM Modules eHRPWM 10 VAR SOM AM43 SYSTEM ON MODULE MPU Subsystem Up to 1000 MHz ARM Cortex A9 32 Bit RISC Microprocessor 32KB of Both L1 Instruction and Data Cache 256KB of L2 Cache Option to Configure as L3 RAM 256KB of On Chip Boot ROM 64KB On Chip RAM Secure Control Module SCM Emulation and Debug JTAG Embedded Trace Buffer Interrupt Controller On Chip Memory Shared L3 RAM 256KB of General Purpose On Chip Memory Controller OCMC RAM Accessible to All Masters Supports Retention for Fast Wakeup Up to 512KB of Total Internal RAM 256KB of ARM Memory Configured as L3 RAM 256KB of OCMC RAM External Memory Interfaces EMIF DDR Controllers LPDDR2 266 MHz Clock LPDDR2 533 Data Rate DDR3 and DDRSL 400 MHz Clock DDR 800 Data Rate 32 Bit Data Bus 2GB of Total Addressable Space Supports One x32 Two x16 or Four x8 Memory Device Configurations General Purpose Memory Controller GPMC Flexible 8 and 16 Bit Asynchronous Memory Interface with Up to Seven Chip Selects NAND NOR Muxed NOR and SRAM Uses BCH Code to Support 4 8 or 16 Bit ECC Uses Hamming Code to Support 1 Bit ECC Error Locator Module ELM Used with the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm Supports 4 8 and 16 Bit Per 512
47. ignal to Noise Ratio 16 20 24 32 Bit Data Supports Rates From 8 kHz to 96 kHz 3D Bass Treble EQ De Emphasis Effects e Stereo Audio ADC 92 dBA Signal to Noise Ratio Supports Rates From 8 kHz to 96 kHz Digital Signal Processing and Noise Filtering Available During Record Programmable Input output Analog Gains e Automatic Gain Control AGC for Record e Programmable Microphone Bias Level e Concurrent Digital Microphone and Analog Microphone Support Available 25 Wi Fi amp Bluetooth The VAR SOM AM43 contains a certified high performance WL183xMOD 2 4 5 GHz IEEE 802 11 a b g n with optional MIMO Bluetooth 4 0 BLE module Features WLAN With Integrated RF Front End Module FEM Power Amplifier PA Crystal RF Switches Filters Passives and Power Management on a Single Module Wi Fi Bluetooth Single Antenna Coexistence Dual Mode Bluetooth and Bluetooth Low Energy HCl Transport for Bluetooth over UART and SDIO for WLAN Temperature Compensation Mechanism to Ensure Minimal Variation in RF Performance Over the Entire Temperature Range WLAN Baseband Processor and RF Transceiver Supporting IEEE Std 802 112 802 11b 802 11g and 802 11n Supports 4 Bit SDIO Host Interface Including High Speed HS and V3 Modes Optional 2x2 MIMO and 40 MHz Channels for High Throughput Wi Fi Direct Concurrent Operation Multi Channel Multi Role Support of Bluetooth 4 0 as well as CSA2 19 VAR SOM AM43 SYSTEM ON MODUL
48. ion amp shock conditions The VAR SOM AM43 can be fasten to the carrier board using the two mechanical holes All the holes are to be located symmetrically The holes plated inside and connected to GND HOLE1 HOLE2 2x4 5x6 2mm 2x4 5x6 2mm GND GND In TOP side a pad has diameter 180mil accordance to top of screw In BOTTOM side a pad has diameter 244mil according to STANDOFF A drill diameter 85mil The STANDOFF has good thermal and electrical conductivity It help for the SOM cooling good GND connection and reduce EMI Part Description Manufacturer PN Standoff SMT SPACER M2x0 4mm H 3mm PennEngineering P N SMTSO M2 3 ET M2x0 4mm length 4mm Essentra Components NSE 1207 M2 4 FLAT M2 STEEL B amp F Fastener Supply MFWZ 002 SPLIT LOCK M2 STEEL B amp F Fastener Supply MLWZ 002 9 Literature 1 AM437x ARM Cortex A9 Microprocessors MPUs literature number SPRS851 2 AM437x ARM Cortex A9 Microprocessors MPUs Technical Reference Manual literature Number SPRUHL7 10 RoHS compliance VAR SOM AM43 System on Module complies with the European Union Restriction on Use of Hazardous Substance Directive 2002 95 EC RoHS 1 Directive 2011 65 EU ROHS 2 as well as the China Management Methods for controlling Pollution by Electronic information Products China RoHS as defined and detailed inVariscite s website htto www variscite com company product compliance polic 85 VAR SOM AM4
49. l Microphone CLK O LCD data I O Digital Microphone DATA I O General Purpose Input output see note 14 I O 2 Clock I O General Purpose Input output see note 14 I O I2CO Data Power Digital GND O LCD data O LCD data O LCD data I O General Purpose Input output see note 14 I O Digital Input Output I O General Purpose Input output see note 14 I O Digital Input Output I O General Purpose Input output see note 14 27 Y12 AD13 12 AA13 13 AA12 14 AB13 AE13 AD14 AE14 D10 B8 AD24 31 Y23 29 B7 AC24 A7 Y22 C8 AB24 AC18 AC20 AA19 A6 AE20 B6 AD20 5 VAR SOM AM43 SYSTEM ON MODULE 9 DATAZ2 o kD deta SSCS 399 ICD DATAS o LD deta mu amaa 2208 GND E Notes 1 Do not use when on board Wi Fi module is mounted 2 12 0 is internally used by 0x34h EEPROM IC Ox1Bh and AUDIO CODEC IC 0x50h Pin function cannot be altered 3 LCD signals are sampled on POR for selecting System boot configurations 4 GPMC Bus signal internally used by Nand flash Can be configured and used as GPIO only if Nand flash is not used 5 UART3 and SOM pins 2 4 6 and 8 are used for on SOM Bluetooth if enabled 6 DATA signals are internally used by on SOM 10 100 1000 Ethernet PHY Do not alter pins functionality if Ethernet PHY is mounted 7 Pin is referenced to
50. lected from Any of the Eight Analog Inputs Multiplexed Through an 8 1 Analog Switch e ADCO Can Be Configured to Operate as a 4 5 or 8 Wire Resistive Touch Screen Controller TSC Upto Three 32 Bit Enhanced Capture Modules eCAP e Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs Up to Six Enhanced High Resolution PWM Modules eHRPWM e Dedicated 16 Bit Time Base Counter with Time and Frequency Controls e Configurable as Six Single Ended Six Dual Edge Symmetric or Three Dual Edge Asymmetric Outputs Upto Three 32 Bit Enhanced Quadrature Encoder Pulse eQEP Modules e Device Identification Factory Programmable Electrical Fuse Farm FuseFarm e Production ID Device Part Number Unique JTAG ID e Device Revision Readable by Host ARM e Feature Identification e Debug Interface Support JTAG and cJTAG for ARM Cortex A9 and PRCM and PRU ICSS Debug Supports Real Time Trace Pins for Cortex A9 64KB Embedded Trace Buffer ETB Supports Device Boundary Scan 15 VAR SOM AM43 SYSTEM ON MODULE Supports IEEE 1500 e DMA Enhanced DMA Controller EDMA Has Three Third Party Transfer Controllers TPTC and One Third Party Channel Controller TPCC Which Supports Up to 64 Programmable Logical Channels and Eight QDMA Channels EDMA is Used for e Transfers to and from On Chip Memories e Transfers to and from External Storage EMIF General Purpose Memory Controller
51. neral Purpose Inputs Signals SIGNAL NAME PRO PRUO GPIO PRO PRUO GPI1 PRO PRUO 10 PRO PRUO GPI11 PRO PRUO GPI12 PRO PRUO PRO PRUO GPI14 PRO PRUO GPI15 PRO PRUO 16 PRO PRUO GPI17 PRO PRUO 18 PRO PRUO GPI19 PRO PRUO GPI2 PRO PRUO GPI3 PRO PRUO 14 PRO PRUO GPI5 PRO PRUO GPI6 PRO PRUO GPI7 PRO PRUO GPI8 PRO PRUO GPI9 DESCRIPTION PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO DATA IN PRU ICSSO PRUO General Purpose Outputs Signals SIGNAL NAME PRO PRUO GPOO PRO PRUO GPO1 PRO PRUO GPO10 PRO PRUO GPO11 PRO PRUO GPO12 PRO PRUO GPO13 PRO PRUO GPO14 PRO PRUO GPO15 PRO PRUO GPO16 PRO PRUO GPO17 PRO PRUO GPO18 DESCRIPTION PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT PRU ICSSO PRUO DATA OUT 73 TYPE TYPE oOo ZDN N24 N22 C2 C1 D1 D2 AC20 AB19 19
52. onverter ADC with optional support for interleaving touchscreen TS conversions for 4 wire 5 wire or 8 wire resistive panel 5 ADC SS be configured for use in one of the following applications e 8 general purpose ADC channels e 4 wire TSC with 4 general purpose ADC channels e 5 wire TSC with 3 general purpose ADC channels e 8 wire TSC The SOM routes all 8bit of ADCO to the edge connector ADCO signals SIGNALNAME Description Type AGND Analog Negative Reference Input ADCO positive negative reference inputs ADCO VREFP ADCO VREFN should be supplied either from VDDA ADC GNDA ADC Respectively or from an external source ADCO VREFP ADCO VREFN signals SIGNALNAME Ping Min 164 ADCO VREFP ADCO_VREEN 18 4 13 1 Touch Screen 4 wire Touch Screen signals ADCO Controller Touch Panel ADCO AIN2 152 YPLL 68 VAR SOM AM43 SYSTEM ON MODULE Touchscreen Resistance 6 max e Drive Current 25 mA max Pen Touch Detect 2 max 4 13 2 Analog Inputs e Full scale Input Range 1 8V e Differential Non Linearity DNL 1LSB Integral Non Linearity INL 2LSB e Gain Error 2LSB e Offset Error 2LSB e Sampling Rate 800KSPS e Conversion Time 15 Clock Cycles Analog to Digital Convertor inputs signals SIGNALNAME pin Description Type ADCO AING Analog Input AGN
53. or from TEXAS INSTRUMENTS Sitara family The VAR SOM AM43 provides an ideal building block for simple integration with a wide range of products in target markets requiring rich connectivity in a compact cost effective SoM with low power consumption Variscite also provides a complete hardware and software development kit DVK for the SoM in the form of a carrier board with 204 pin edge connector for the VAR SOM AM43 and an optional TFT display and touch panel The carrier board of the VAR SOM AM43 is ideal not only as reference for the customer to develop its own custom board but also as a cost effective solution for production Details of this carrier board and development kit can be found inside the VAR AM43CustomBoard datasheet and the related documentation inside Variscite website www variscite com Supporting products VAR AM43CustomBoard evaluation board Y Carrier Board compatible with VAR SOM AM43 Y Schematics e O S support Linux Yocto Contact Variscite support services for further information mail to support variscite com 1 2 VAR SOM AM43 Features Summary High performance up to 1000 MHz ARM Cortex A9 32 Bit RISC Microprocessor NEON SIMD Coprocessor and Vector Floating Point VFPv3 Coprocessor SGX530 Graphics Engine 4 x 200MHz 32 bits RISC co processors programmable real time unit PRU Up to 1 GB DDR3 RAM Up to 32GB eMMC storage Up to 512MB NAND Flash for storage memory boot VAR SOM A
54. ors DCDC1 DCDC2 DCDC3 to 4 DCDC4 and 1001 to 5 PROTECTION DIAGNOSTICS CONTROL e Under voltage lockout e Over temperature warning shutdown e Always on push button monitor e Separate power good output for backup and main supplies e Open drain interrupt output pin 20 VAR SOM AM43 SYSTEM ON MODULE e User programmable default voltages and power sequencing e 2C interface Address Ox24h TPS65218 features are utilized internally by the VAR SOM AM43 and are not exposed to the VAR SOM AMA43 204 pin connector 21 VAR SOM AM43 SYSTEM ON MODULE 3 External Connectors The VAR SOM AM43 exposes a 204 DDR3 SODIMM mechanical standard interface Recommended Mating connector for baseboard interfacing is JAE MM80 204B1 1 or TE Connectivity 2 2013289 1or equivalent Pin Pin Number on the SO DIMM204 connector Pin Name Default VAR SOM AM43 Pin Name Type Pin Type amp Description e O Out 5 Differential Signal e A Analog e Power Power Pin e PD Internal Pull Down PU internal pull up Pin Group Pin functionality group AMA37x Ball AM437x ball number Mode Tables 3 2 amp 3 4 AM437x PinMux mode option 22 SYSTEM ON MODULE Pin Pin Name Oo _ VU BWIN WiiWii Wi iW WWW WN NY FP FP FP FP WN FP 0 TDD A WN FP WIN RGMII2 UART3 TXD RG
55. r pattern and Foveon sensor formats Generates HD VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator e Support for progressive and interlaced sensors hardware support for up to 2 fields and firmware support for higher number of fields typically 3 4 and 5 field sensors Support for up to the lesser of 75 MHz or 1 2 dma ocp clk sensor clock in the normal mode Support for REC656 CCIR 656 standard YCbCr 422 format either 8 or 16 bit Support for YCbCr 422 format either 8 or 16 bit with discrete and VSYNC signals Support for up to 16 bit input e Generates optical black clamping signals Support for digital clamping and black level compensation Support for 10 bit to 8 bit A law compression e Support for a low pass filter prior to writing to SDRAM If this filter is enabled 2 pixels each in the left and right edges of each line are cropped from the output Support for generating output to range from 16 bits to 8 bits wide e Support for downsampling via programmable culling patterns Ability to control output to the SDRAM via an external write enable signal Support for up to 16K pixels image size in both the horizontal and vertical direction Parallel Camera Interface 0 signals 32 50 T T 60 VAR SOM AM43 SYSTEM ON MODULE 4 7 2 Camera interface 1 Parallel Camera Interface 1 signals camldatag
56. ration supports Programmable master clock generation operating from fixed 48 MHz functional clock input Selectable clock phase and clock polarity per chip select The SOM includes four SPI I F routed out SPIO signals AMA37X SIGNAL ECCE ETIN Valid configuration PINs NAMIE e ee sooo soco 9 9 _ mja SPI1 signals AMA37X SIGNAL NAME DESCRIPTION Valid configuration PINs Iw ww 124 66 66 I S seichipselect 17 26 26 SPI Chip Select 19 13 64 VAR SOM AM43 SYSTEM ON MODULE SPI2 signals AM437X SIGNAL TT SPD DO SPiData_ 201 173 84 Ps CA SPD Ca SPiChpseet 198 198 198 SPI3 signals AMA37X SIGNAL Valid configuration PINs NAME sam 1 SPBCS2 5 No No No 4 10 QSPI The main features of the QSPI include Programmable divider for serial data clock generation e Six pin interface DCLK 5 DOUT DIN QDIN1 QDIN2 e Programmable data length No of bits from 1 32 e 4 external chip select signals e Support for 3 4 or 6 pin SPI interface mode uses spi as inout spi din not used 4 pin mode for dual read uses spi dout as in spi din as in 6 pin mode uses spi as in spi din as in spi qdin
57. rs to be routed to the edge connector The Mode pins of the AR8033 are set to 1G at wake up 0010 1000Base 50ohms RGMII 54 VAR SOM AM43 SYSTEM ON MODULE Gigabit Ethernet Signals 7 SIGNAL NAME DESCRIPTION pi ground signa A Media dependent interface A MDI B Media dependent interface _B GND ground signal MDI C Media dependent interface C MDI D Media dependent interface D 9 GND ground signal LED LINK 10 100 LED output for 10 100 BASE T link 4 3 2 Optional ROUTE OUT RGMIII interface In a configuration without a Wi Fi module RGMII2 Interface will be routed out Optional additional Gigabit Ethernet signals AM437X SIGNAL NAME DESCRIPTION PINE RGMII2_RCLK RGMII2_RCLK RGMII2_RDO D8 RGMII2 RDO Ba 9 55 VAR SOM AM43 SYSTEM ON MODULE 437 SIGNAL NAME DESCRIPTION Valid configuration PINs 4 4 USB 2 0 The SOM provides with 2 USB USBO is used as and 0581 is used as host interface 4 4 1 USB 2 0 HOST USB HOST1 signals AMA37X PINS DESCRIPTION 0581 DM 0581 Data minus USB1_DRVVBUS USB1 Active high VBUS control output 4 4 2 USB 2 0 On the Go USBO OTG signals AM437X SIGNAL NAME DESCRIPTION 0580 DM 0580 Data minus USBO DRVVBUS USBO Active high VBUS control output 98 USBO VBUS USBO VBUS 99 56 VAR SOM AM43 SYSTEM ON MODULE 4
58. s Card Detect and Write Protect e Complies with MMC4 3 and SD and SDIO 2 0 Specifications 13 VAR SOM AM43 SYSTEM ON MODULE Upto Three l2C Master and Slave Interfaces Standard Mode Up to 100 kHz e Fast Mode Up to 400 kHz Up to Six Banks of General Purpose I O GPIO 32 GPIOs per Bank Multiplexed with Other Functional Pins GPIOs Can be Used as Interrupt Inputs Up to Two Interrupt Inputs per Bank Upto Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs Twelve 32 Bit General Purpose Timers is a 1 ms Timer Used for Operating System OS Ticks DMTIMER4 DMTIMER7 are Pinned Out One Public Watchdog Timer One Free Running High Resolution 32 kHz Counter synctimer32K SGX530 3D Graphics Engine e Tile Based Architecture Delivering Up to 20M Poly sec e Universal Scalable Shader Engine is a Multi Threaded Engine Incorporating Pixel and Vertex Shader Functionality e Advanced Shader Feature Set in Excess of Microsoft VS3 0 PS3 0 and OGL2 0 e Industry Standard API Support of Direct3D Mobile OGL ES 1 1 and 2 0 and OpenVG 1 0 Fine Grained Task Switching Load Balancing and Power Management e Advanced Geometry DMA Driven Operation for Minimum CPU Interaction e Programmable High Quality Image Anti Aliasing e Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture Display Subsystem e Display Modes Programmable Pixel Memor
59. t interface 3 Minus MMC SD SDIO Card Detect Digital GND McASPO Transmit Bit Clock LED output for 10 100 1000 BASE T activity Digital Input Output LED output for 1000 BASE T link McASPO Receive Master Clock LED output for 10 100 BASE T link McASPO Transmit Master Clock UART Clear to Send McASPO Serial Data IN OUT USBO OTG VBUS Detect Input UART Request to Send USB1 DRIVER ENABLE UART Receive Data UART Transmit Data LCD BACKLIGHT PWM 2 1 Data I2C1 Clock UART Transmit Data Digital GND LCD horizontal sync LCD vertical sync LCD data LCD AC bias enable 24 AB20 15 B17 17 17 18 AB18 Y18 20 AA18 21 R25 N24 23 P25 24 M24 26 L24 L25 M25 F24 J25 F25 K25 J24 G24 T21 T20 T22 A23 B23 B22 A24 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 SYSTEM AM437X LCD DATA2P 437 LCD PCLK 437 LCD DATAS 437 LCD DATA15I AM437X LCD DATA9SI AM437X LCD DATA4P SPI2 CSO SPI2 DO GND UART2 RXD GPIOO 2 437 USB1 DP 437 USBO ID 437 0581 DM SPI2 D1 437 USB1 VBUS MCASPO FSX SPI1 DO GND SPI2 SCLK 437 USBO DP GND AM437X_USBO_DM AM437X_USBO_DRVVBUS AM437X_USBO_VBUS VBAT_3P3V GND VBAT_3P3V VBAT_3P3V VBAT_3P3V VBAT_3P3V GND VBAT_3P3V GND 2 519 VDDA AM437X_DCAN1_TX GNDA_ADC
60. ture Shock Resistance 50G 20 ms fs Note Extended and Industrial Temperature is only based on the operating temperature grade of the SoM components Customer should consider specific thermal design for the final product based upon the specific environmental and operational conditions 83 VAR SOM AM43 SYSTEM ON MODULE 8 Mechanical Specifications 8 1 Drawing V 67 6 0000000000000000 0000000000000000 0000000000000000 T OO0O00000000000000 IE ZA 0000000000 000000000 000 000 OOO 000 0900000900 OOO 000 eee U13 090000990 OOO 000 OOO 000 oooooooooooooooooo 600000000 oooooooo m 00000000000 oo oo oo oo 0000000000000000 0000000000000000 0000000000000000 OOO 000 oooooooo 00000000 od ODEN Li bot OT ISSO ac CAD file are available for download at http www variscite com 84 VAR SOM AM43 SYSTEM ON MODULE 8 2 SoM Fastening For extra mechanical strength required for operating in extreme vibrat
61. y Formats Palletized 1 2 4 and 8 Bit Per Pixel RGB 16 and 24 Bit Per Pixel and YUV 4 2 2 256 x 24 Bit Entries Palette in RGB Up to 2048 x 2048 Resolution e Display Support Four Types of Displays Are Supported Passive and Active Colors Passive and Active Monochromes 4 and 8 Bit Monochrome Passive Panel Interface Support 15 Grayscale Levels Supported Using Dithering Block RGB 8 Bit Color Passive Panel Interface Support 3 375 Colors Supported for Color Panel Using Dithering Block RGB 12 16 18 and 24 Bit Active Panel Interface Support Replicated or Dithered Encoded Pixel Values Remote Frame Buffer Embedded in the LCD Panel Support through the RFBI Module 14 VAR SOM AM43 SYSTEM ON MODULE Partial Refresh of the Remote Frame Buffer through the RFBI Module Partial Display Multiple Cycles Output Format on 8 9 12 and 16 Bit Interface TDM e Signal Processing Overlay and Windowing Support for One Graphics Layer RGB or CLUT and Two Video Layers YUV4 2 2 RGB16 and RGB24 RGB 24 bit Support on the Display Interface Optionally Dithered to RGB 18 Bit Pixel Output Plus 6 Bit Frame Rate Control Spatial and Temporal Transparency Color Key Source and Destination synchronized Buffer Update Gamma Curve Support Multiple Buffer Support Cropping Support Color Phase Rotation Two 12 Bit Successive Approximation Register SAR ADCs ADCO ADC1 e 867K Samples Per Second e Input Can Be Se

Download Pdf Manuals

Related Search

Related Contents

NOT-123101-001-AC  1/3” Tag/Nacht-Domekamera, Fix VKCD-1330  Kärcher CV 38/1  MILENIO Manual de usuario  

Copyright © All rights reserved. Failed to retrieve file