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Virtex™ -5 LX330T/FX200T/SX240T HTG-V5-PCIE

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1. 2 2 System Requirement 2 3 Summary Of Features 2 4 Block Diagram 2 5 User I Os amp Distribution 2 5 1 General Purpose RocketIO GTP Ports 2 5 2 High Speed LVDS Samtec Connectors 2 5 3 LED amp Switches 2 6 SO DIMM Memory 2 7 PCI Express 2 8 Serial ATA 2 9 Gigabit Ethernet 2 10 SMA Interface 2 11 Configuratio
2. www xilinx com 55 Software Flows for File Preparation and Programming Step 4 Select BPI Mode Direction and Width The fourth step of the process is to select the FPGA type the BPI PROM Parallel PROM density the BPI mode direction and the bus data width Click on the Create BPI Mode PROM checkbox and select the Virtex 5 Leave the Loading Direction specified as UP and the Data Width specified as x16 Figure 6 Click Next to proceed to Step 5 XAPP973 v1 2 February 6 2008 Checksum Fill Value 2 Hex Digits PROM File Name iMPACT Prepare PROM Files want to target a PROM 5 Generic Parallel PROM 3rd Party SPI PROM 2 XILINX PROM Supporting Multiple Design Versions Spartan3E PROM File Format MCS OTEK UFP C format Exo BIN ISC HEX Swap Bits Location C Virtex5 Figure 6 Select BPI Mode Direction www xilinx com X973_05_020608 56 Software Flows for BPI File Preparation and Programming XILINX Step 5 Summary of BPI PROM File Selections The fifth step in the process displays a summary of the options selected from the prior steps in the process Figure 7 The summary shows that a PROM file in the MCS file format with a fill value of hexadecimal FF is to be written to a file with a root name of PROM 32 MB PROM Cli
3. 859 FE 1 8V 3 3 3e Mode Selection irtex _UP FPGA 3 3V 3 3V E L9P CC GC 40 4 rZ 85 gs 1 0 7 Vi Pushbutton BED BM LED CCLK 5N HSWAPEN gt X973 02 020608 Notes 1 CONFIG VCCO 0 is the configuration output supply voltage and supplies the dedicated configuration pins TMS TDI M 2 0 HSWAPEN PROG B DONE INIT B CCLK D IN VCCO 1 supplies A 19 0 VCCO 2 supplies FCS FOE B FWE B A 25 20 and D 0 7 VCCO 4 supplies D 8 15 It is recommended to have the option for both JTAG M 2 0 101 and UP M 2 0 010 configuration modes HSWAPEN can be driven Low to enable pull ups on RS 1 0 and CSO B signals are used for advanced daisy chain and revisioned applications These signals are not connected for this setup Refer to Ref 3 for detailed information IO L9P CC GC 4 pin is recommended to be reserved and not connected in a design when using the iMPACT indirect programming If this signal is used the target application must consider that the iMPACT indirect programming core can drive this signal Low Caution The iMPACT indirect programming solution drives all FPGA address lines A 25 0 during ISP operations on the PROM The FPGA address lines must be connected directly to the PROM address
4. Bank FPGA Pin Description ed Signal Name 251613 9 VTT 1 GND 2 GND 3 13 IO L17N 13 AT42 DIMM DQ4 4 13 IO 15 13 41 DIMM 5 13 IO L19P 13 AU42 DIMM_DQ5 6 13 IO L17P 13 AR42 DIMM DQI 7 GND 8 GND 9 13 IO L15P 13 AMAT DIMM 10 13 IO LIIN CC 13 AC39 DIMM DQSO N 11 GND 12 13 IO LIIP CC 13 AC40 DIMM 0080 13 13 IO L4P 13 AF40 DIMM DQ6 14 GND 15 13 IO L6N SM3N 13 AJ41 DIMM_DQ7 16 13 IO L13N 13 AK42 DIMM DQ2 17 GND 18 13 IO L13P 13 AL41 DIMM_DQ3 19 13 IO_LON_SM8N_13 AB42 DIMM 012 20 GND 21 13 SMS8P 13 AB41 DIMM DQ13 22 13 IO L6P SM3P 13 AJ42 DIMM_DQ8 23 GND 24 13 IO_LIN_SM7N_13 AD42 DIMM_DQ9 25 13 IO LIP SM7P 13 AC41 DIMM DMI 26 GND 27 GND 28 13 IO L8N CC SMIN 13 AB38 DIMM N 29 13 IO L10P 13 AE40 DIMM_CLKO P 30 13 IO L8P CC SMIP 13 AB37 DIMM DQSI P 31 13 IO 110 CC 13 AD40 DIMM_CLKO_N 32 GND 33 GND 34 13 IO L2P SM6P 13 AE42 DIMM 010 35 13 IO_L3P_SMS5P_13 AF41 DIMM 0014 36 26 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 13 IO L2N SM6N 13 AD41 DIMM 11 37 13 IO L3N SMSN 13 AF42 DIMM_DQ15 38 GND 39 GND 40 GND 4l GND 42 13 IO L7N SM2N 13 AJ40 DIMM 0016 43 13 IO L5P 8 13 AG42 DIMM DQ20 44 13 IO L14P 13 AL42 DIMM 0017 45 13 IO L5N 13 DIMM 0021 46 GND 4 GND
5. File name bitfile bit File type All Design Files bit rbt isc nky mes exo mpm None Enable Programming of SPI Flash Device Attached to this FPGA Enable Programming of BPI Flash Device Attached to this FPGA X973_14_020608 Figure 14 Add New Configuration File XAPP973 v1 2 February 6 2008 www xilinx com 61 Software Flows for BPI File Preparation and Programming XILINX Step 4 Add a BPI PROM File for Indirect Programming Browse and select the PROM file for programming into the BPI PROM Figure 15 Choose the BPI_PROM mcs file and click Open Add PROM File Lookin Byres O v PROM mcs My Recent Documents e e 23 8 e My Network File name BPI_PROM Places Files of type MCS Files 5 v Cancel X973_15_020608 Figure 15 Add a BPI PROM File Step 5 Select Intel 28F256P30 Device Part Number After selecting the PROM file to load iMPACT displays the Select Device Part Name dialog box Figure 16 The fifth step of the process requires the target PROM type to be specified in this dialog box Select the Intel 28F256P30 part number for the target PROM type used in this demonstration Click OK to complete the PROM programming setup g FPGA BPI Flash Association Select Flash FPG xcSvix50
6. eur uu 9998 225 E ee 19196 c3 25 002006 Dedicated Pins IO LXXv VREF PROGRAM GND MGTAVCC 9 MGTRXP VRN cs B RDWR B RsvD MGTAVCCPLL MGTRXN D IN EB MGTAVITRX MGTTXP D DONE I TDI 4 VCCAUX E MGTAVITRXC MGTTXN D OUT BUSY 0 VCCINT P MGTAVTTTX Q cc HSWAPEN M TMS VCCO MGTREFCLKP 00 031 Y m NC MGTREFCLKN 6 A0 A25 211160 2 MO _ 0 DXN FLOAT MGTRREF e sm AVDD 0 AVSS 0 VP 0 VN 0 0 VREFN 0 Figure 2 Virtex 5 LX330T FF1738 Pin Diagram 11 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Chapter 2 Virtex 5 PCI Express LX330T SX240T FX200T Platform 2 1 Introduction The HTG V5 PCIE XXX board is powered by Xilinx Virtex 5 LX330T SX240T or FX200T FPGA which offers 24 RocketIOTM GTP GTX Transceivers up to 8 hard coded Gigabit Ethernet Media Access Controllers MAC up to four x8 PCI Express End Point Block up to two PPC440 processors and more than 331 000 FPGA logic cells The HTG V5 PCIE XXX provides wide variety of connectors and interfaces including PCI Express 8 lane upstream x2 Gigabit Ethernet with SGMII support using x2 RocketIO transceivers 2 SATA Connectors x10 General Purpose RocketIO GTP GTX transceivers with adjustab
7. Bus Interface Cores Support AHB AXI in development Avalon PLB future VFIFO Core Turns a memory segment into a virtual FIFO Multi Port Front End Core Provides a fully arbitrated multi port interface Read Modify Write Core Handles writing non aligned bursts into ECC protected memory e ECC Core Provides standard DRAM error detection correction Multi Burst Core Breaks extended bursts into multiple native memory bursts Memory Test Core Performs a random address and data memory test Data Analyzer Core Used to capture on chip signals of interest such as the Memory Test data Main Features High performance access logic allows cascading of read and write requests enabling up to 10096 throughput for all DDR2 burst length settings 4 or 8 Bank management logic monitors status of each SDRAM bank up to 8 banks monitored banks only opened or closed when necessary minimizing access delays Queue based user interface that enables the DDR2 SDRAM Controller Core to look ahead in order to optimize the performance and throughput at the DDR2 SDRAM memory device interface Pipelined design enables high clock rates with minimal routing constraints Supports all standard SDRAM chips and DIMMs Run time configurable timing parameters CAS Latency CL tRAS tRCD tRRD tRP tRC tRFC tMRD tXSNR tFAW tWR tWTR Timing parameters support operation up to 333MHz 667 Mb s pin
8. Prepare a System ACE File Prepare a Boundary Scan File Configure devices using Slave Serial mode X973_04_020608 Figure 4 Choose to Prepare a PROM File XAPP973 v1 2 February 6 2008 www xilinx com 54 Software Flows for BPI File Preparation and Programming XILINX Step 3 Specify the Output BPI PROM File Options The third step of the process is to specify the targeted PROM type the PROM file format and output file name and location Figure 5 Choose to target the Generic Parallel PROM type and then select the MCS PROM file format Maintain the default Checksum Fill Value which is a hexadecimal FF byte value Specify the PROM file name to be PROM to the PROM name iMPACT automatically adds the mcs file name extension corresponding to the chosen MCS PROM file format Specify a desired directory location for the output BPI XAPP973 v1 2 February 6 2008 PROM mcs file Click Next to continue to step 4 iMPACT Prepare PROM Files want to target a PROM 5 Generic Parallel PROM SPI PROM PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format MCS OTEK UFP C format BIN ISC Q HEX Swap Bits Checksum Fill Value 2 Hex Digits PROM File Name PROM Location C Virtex5 X973 05 020608 Figure 5 Specify the Output BPI PROM File Options
9. 7 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 1 8 Input Output Blocks SelectIOs IOBs are programmable and can be categorized as follows Programmable single ended or differential LVDS operation Input block with an optional single data rate SDR or double data rate DDR register Output block with an optional SDR or DDR register Bidirectional block Per bit deskew circuitry Dedicated I O and regional clocking resources Built in data serializer deserializer The IOB registers are either edge triggered D type flip flops or level sensitive latches IOBs support the following single ended standards LVTTL LVCMOS 3 3V 2 5V 1 8V 1 5V and 1 2V PCI 33 and 66 MHz PCI X GTL and GTLP HSTL 1 5 and 1 8V Class I II and IV HSTL 1 2V Class 1 SSTL 1 8V and 2 5V Class I and II The Digitally Controlled Impedance DCT I O feature can be configured to provide on chip termination for each single ended I O standard and some differential I O standards The IOB elements also support the following differential signaling I O standards LVDS and Extended LVDS 2 5V only BLVDS Bus LVDS ULVDS Hypertransport Differential HSTL 1 5V and 1 8V Class I and II Differential SSTL 1 8V and 2 5V Class I and IT RSDS 2 5V point to point Two adjacent pads are used for each differential pair Two or four IOB blocks connect to one swi
10. BPI Flash INTEL28F128J3 INTEL28F128J3 INTEL28F128P30 INTEL28F256 3 INTEL28F256P30 INTEL28F320J3 INTEL28F640J3 INTEL28F640P30 X973_16_020608 Figure 16 Select Device Part Name Dialog Box XAPP973 v1 2 February 6 2008 www xilinx com 62 Software Flows for BPI File Preparation and Programming 5 XILINX Step 6 Invoke the iMPACT Program Operation The sixth step of the process programs the target BPI PROM with the selected BPI PROM file contents Ensure the BPI PROM icon in the iMPACT window is selected by left clicking on the BPI PROM icon the BPI PROM icon is highlighted in green when selected Select Operations Program to begin programming Figure 17 iMPACT C Xilinx9 1i default ipf Boundary Scan fel gt File Edit View Operations Output Debug Window Help 0 Flows a Scan Z3ISelectM P 1 1 Verify 22 Desktop Configuration 1 1 Erase alDirect SPI Configuration 1 4 Get Device ID E SystemACE 5 50 Blank Check File Formatter bitfile bit Readback Right click device to select operations Assign New Configuration File Delete Boundary Scan Selected part INTEL28F256P30 BATCH CMD attachflash position 1 bpi INTEL28F256P30 BATCH CMD assignfiletoattachedflash position 1 file C Virtex5 BPI PROM mcs im
11. Run time configurable memory settings i e row bits column bits bank bits Supports up to eight chip selects Support for DDR2 SDRAM device Self Refresh mode Support for DDR2 SDRAM device Power Down mode Automatic generation of initialization and refresh sequences Commands may be issued with or without SDRAM auto precharge selectable at each transaction request ntegrated data path module for write DQS generation and read capture Core datapath tailored to FPGA family and or ASIC library Optional Error Correction Coding ECC Read Modify Write RMW and Multi Burst Modules available Source code license available Verilog and VHDL Architecture 79 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual sdram ddr2 Ib reset n DDR2 Configuration Ports SDRAM Device s cke EM Control and Timing os raddr b size 30 wreq busy Queue valid sa 13 0 Initialization Control datain 2n 1 0 dm in 2n 8 1 0 clk Oo dqs n 8 1 0 I bee Address bato y Generation dm n 8 1 0 Clock Module ext clk ext clk n clk in Figure 32 DDR 2 Memory Controller Block Diagram Additional information about the DDR 2 Memory Controller IP core is available at http www hitechglobal com IPCores DDR2Controller htm 80 www HiTechGlobal com
12. Simple handshake signals are provided to connect a DMA unit to the core module The DMA requests will be asserted as soon as any transmit data 1s available or is needed in the core s data FIFO The DMA unit will then access the data FIFO via the Wishbone slave interface A system interrupt will inform host software on completion of a data transfer Automatic flow control mechanisms control data throttling to avoid underflow or overflow of the transmit data FIFO The DMA unit or host software may work at any speed without the risk of data loss Data FIFO thresholds can be adjusted to optimize the data flow control Size amp Speed Sample Synthesis results for SATA Host IP Core The goal was smallest and fastest implementation Technology Gate Count UMC 0 18 um 24 000 gates Up to 300MHz PHY clock up to 77 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 200 MHz system clock Xilinx Spartan 3 XC381000 5 1479 Slices ro El ud Xilinx Virtex 2 XC2V1000 6 1466 Slices EE CERE Xilinx Virtex 4 20 10 2000 Slices 100 MHz Table 16 SATA IP Core Size amp Speed Additional information about the SATA core is available at http www hitechglobal com ipcores sata htm 4 3 DDR 2 Memory Controller Memory DDR PHY Loopback Figure 33 Complete Memory Controller Solution The DDR2 SDRAM Memory Controller IP Core provides a high performance interface to DDR2 SDRAM devices The DDR2
13. 1 0 1 40 14 0 17 5 Table 3 a ICS843001 U3 Programmable Output Divider Function Table N2 NO SW4 3 key SW4 2 key SW4 key 0 0 0 tn A Je le eR 1 1 10 Table 3 b ICS843001 U3 Programmable Output Divider Function Table 21 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Table 4 a and 4 b illustrate pin assignment for each high speed connector Connector J16 Lower Connector Connector Signal FPGA Connector Connector Signal Pin Pin Name Name Pin Pin Name Pin Name 2 LVDSO LVDSO N33 LVDS17 1 LVDS16 P N31 4 LVDSO_N LVDSO_N N34 LVDS17_N 3 LVDS16_N P31 6 GNDO GND GND21 3 GND 8 LVDS1 P LVDSI P M34 LVDSI18 7 LVDS17 G33 10 LVDS1_N LVDS1_N M33 LVDS18 9 LVDS17 N H33 12 GND1 GND GND22 11 GND 14 LVDS2_P LVDS2_P M32 LVDS19 P 13 LVDS18 H31 16 LVDS2 N LVDS2 N M31 LVDS19 N 15 LVDS18 N J31 18 GND2 GND GND23 17 GND 20 LVDS3 P LVDS3 P G32 LVDS20 P 19 LVDS19 P E34 27 LVDS3 N LVDS3 N G31 LVDS20 N 21 LVDS19 N F34 24 GND3 GND
14. 128 Single ended 3 3V IOs accessible via two independent high speed Samtec connectors gt 2 SATA Ports 111 2 Gigabit Ethernet Ports both with SGMII support PCI Express Jitter Attenuator with adjustable clock outputs gt Super Clocks with adjustable outputs for the SATA and GTP GTX ports External Clock input 256 Mb Intel Flash Memory for FPGA configuration and additional user Flash storage ATX and Standard 5V Power Connectors Jumpers for Stand Alone mode Jumper for FPGA configuration via PCIe bus 13 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 4 Block Diagram amp Dimensions Figure 3 illustrates the overall components placement and dimensions of the HTG V5 PCIE XXX board vit 486 eee o gt ER 111111 11114911 14 4 48 r 13 22212 e 2 2800 11 WERE gir Figure 3 HTG V5 PCIE XXX Components Placement 14 www HiTechGlobal com HTG V5 PCIE XXX User Manual Virtex 5 LX330T SX240T FX200T 1170 28mil X2 gt ton 4114 27mil X2 lt 2 884 06mil 1 0 00000001 2000000060 0414 C418 m mi TE 18838881 209301011 wp 5 b 18814
15. DMA Descriptor Engine fetches DMA Descriptors from a linked list of Descriptors stored in system memory or user logic can directly control the DMA Engine o Base Configuration has 1 Card to System DMA Engine and 1 System to Card DMA Engine 73 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual o Multi Engine Configuration has 1 4 Card to System DMA Engines and 1 4 System to Card DMA Engines o Engines are interleaved on a PCI Express packet basis o 32 bit and 64 bit System Address Support 32 bit and 64 bit Descriptor Linked List System Address Support o Up to 64 bit Card Address Support o Designed for DMA destination which are FIFOs or addressed memory o MSI and Legacy Interrupt support o System address Card Address and Byte Count support byte alignment allowing for maximum software flexibility o Supports fragmented system and card memory o Supports extremely long Descriptor chains Master Interface o Simple interface supports generation of Memory 32 64 bit address I O Configuration Root Complex implementations only and Message Msg MsgD transactions o Supports write and read transactions with up to one DWORD 32 bit of payload data Target Interface o Very flexible easy to use high performance independent target write and read interfaces o Supports 32 bit and 64 bit Memory Base Address Registers Register Interface o Implements a 32 bit Memory Base Address Register for DMA and
16. Duput Enor Waming Configuration Platform Cable USB 6 MHz usb hs X973 17 020608 Figure 17 Program Menu XAPP973 v1 2 February 6 2008 www xilinx com 63 Software Flows for BPI File Preparation and Programming XILINX Step 7 Select iMPACT Programming Properties In response to the invocation of the Program operation iMPACT presents the Programming Properties dialog box Figure 18 The seventh step of the process ensures the selection of proper programming properties Ensure that the Erase Before Programming option is checked for proper programming of the PROM Click OK to begin the erase and program operations Programming Properties Category Programming Properties Advanced PROM Programming Properties Revision Properties Verify General CPLD And PROM Properties le B Hex Digits CPLD Specific Properties Write Protect Functional Test n The Fly Program UES Enter up to 13 characters PROM Specific Properties Load FPGA Parallel Mode Use D4 for CF FPGA Device Specific Programming Properties Pulse PROG Program Key Spartan3AN Programming Properties Data Protect Data Lockdown Cancel X973 18 020608 Figure 18 BPI PROM Programming Properties Dialog Box iMPACT Message Log when loading the JTAG to BPI Bitstream At the start of the programming operation iMPACT automatically connects to the cable attached to the
17. J36 LVDS28 N 87 LVDS26 N U33 90 GND15 GND GND35 89 GND 92 LVDS12 LVDS11 P U34 LVDS29 P 9 LVDS27 P R35 94 LVDSI2 LVDSII N T35 LVDS29 N 95 LVDS27 N T36 96 GNDI6 GND GND36 95 GND 98 LVDS13 P LVDSI12 P U36 LVDS30 P 97 LVDS28 P F36 100 LVDSI3 N LVDSI2 N V36 LVDS30 N 99 LVDS28 N G36 102 GNDI7 GND GND37 101 GND 104 LVDSI4 P LVDSI3 P F37 LVDS31 P 103 LVDS29 P V35 106 LVDSI4 LVDSI3 E37 LVDS31 N 105 LVDS29 N V34 108 GND18 GND GND38 107 GND 110 LVDSI5 P LVDS14 P E38 LVDS32 P 109 LVDS30 P Y33 112 LVDS15_N 1 514 D37 LVDS32 N 111 LVDS30 N W32 114 GND19 GND GND39 113 GND 116 LVDS16 P 1 515 V33 LVDS33 P 115 LVDS31 P Y32 118 LVDS16 N LVDSI5 N W33 LVDS33 N 117 LVDS31_N AA32 120 GND20 GND GND40 119 Table 4 High Speed LVDS Connectors Summary Connector 1 lower Connector 17 Upper Connector Connector Signal FPGA Connector Connector Signal Pin Pin Name Name Pin Pin Name Pin 2 LVDSO LVDS32 P J12 LVDS17 1 LVDS48 14 4 LVDSO LVDS32 N LVDS17 N 3 LVDS48 5 6 GNDO GND GND21 3 GND 8 LVDSI LVDS33 P G12 LVDS18 P 7 LVDS49 P K10 10 LVDSI N LVDS33 N 11 LVDS18 9 LVDS49 L10 12 GND1 GND GND22 11 GND 14 LVDS2 P LVDS34 F12 LVDS19 P 13 LVDS50 L12 16 LVDS2 N LVDS34 N F11 L
18. generate the address and sample read data Parallel daisy chain active For parallel daisy chains User 1 Low chip select output Not this signal is driven Low CSO_B Output used in single FPGA when data is delivered to NC applications downstream device Data input sampled by the Data captured by FPGA User 1 0 D 15 0 Input rising edge of the FPGA DQ 15 0 CCLK Active High signal FPGA drives DONE Low Dedicated DONE Bidirectional indicating configuration is DONE Open Drain or complete NC active 0 FPGA not configured 1 FPGA configured Active Low Flash chip This output is actively User 1 0 2 select output driven Low It has a weak E FCS B Output pull up resistor during configuration Active Low Flash output This output is actively User 0 1 2 enable driven Low during mE FOE B Output configuration and has a OE weak pull up before configuration Active Low Flash write This output is actively User 1 00 2 enable driven High and has a WE FWE_B Output weak pull up during configuration Controls I O except Bank Pull up resistors during Dedicated HSWAPEN 0 dedicated I Os configuration This pin has a built in weak pull up resistor HSWAPEN Input 0 Pull up during NC configuration 1 3 state during configuration Low to delay configuration Drives Low after power on Dedicated INIT_B After the Mode pins are POR or when PROG Bis When the SEU sampled INIT B is an pulsed Low while FPGA is
19. 48 13 IO L9N CC SMON 13 AC38 DIMM DQS2 N 49 NC 50 13 IO L9P SMOP 13 AB39 DIMM 0062 P 51 13 IO L7P SM2P 13 40 DIMM DM2 52 GND 53 GND 54 13 IO L16P 13 AP42 DIMM DQ18 55 13 IO L18N 13 AUAI DIMM DQ22 56 13 IO L18P 13 41 DIMM_DQ19 57 13 IO L16N 13 DIMM 023 58 GND 59 GND 60 1 IO 11 R40 DIMM DQ24 61 11 IO L13P 11 P41 DIMM 0028 62 11 IO L15P_SM13P 11 T42 DIMM DQ25 63 11 IO L15N SMI3N 11 41 DIMM 0029 64 GND 65 GND 66 11 IO L8N CC 11 Y40 DIMM DM3 67 11 IO L9N CC 11 AA39 DIMM DQS3 N 68 NC 69 11 IO L9P CC 11 AA40 DIMM P 70 GND 71 GND 72 11 IO L6N 11 N41 DIMM DQ26 73 11 1 _111 _ 8 14 11 Y37 DIMM DQ30 74 11 IO L8P CC 11 W40 DIMM DQ27 75 27 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 11 IO LIIN CC 8 14 11 AA37 DIMM DQ31 76 GND 77 GND 78 11 DIMM CKE 79 11 IO LON 11 G42 DIMM CKE 80 VCC1V8 81 VCC1V8 82 NC 83 NC 84 17 IO L9N CC 17 AT40 DIMM 85 NC 86 VCCIV8 87 VCCIV8 88 17 IO L6N 17 AG38 12 89 17 IO L6P 17 AF39 DIMM 90 17 IO L5P 17 AE39 DIMM A9 91 17 IO L3N 17 AD37 DIMM A7 92 17 IO 17 AE37 DIMM A8 93 17 IO L3P 17 AD36 DIMM A6 94 VCCIV8 95 VCCIV8 96 17 IO L2N 17 AD35 DIMM A5 97 17 IO L2P 17 AC36 DIMM A4 98 17 IO LIN 17 AB36 DIMM A3 99 17 IO LIP 17 AC35 DIMM A2 100 17 IO 17 A
20. 71 LVDS56 P B5 74 LVDS9_N LVDS40 V10 LVDS26 N 73 LVDS56 N 5 76 GND12 GND GND32 75 GND 78 LVDS10 P 1 541 F9 LVDS27 P 77 LVDS57 R9 80 LVDSIO N LVDS41_N G9 LVDS27 N 79 LVDS57 N T9 82 GND13 GND GND33 81 GND 84 14 GND GND34 83 GND 86 LVDS11_P LVDS42 P G7 LVDS28 P 85 LVDS58 P F7 88 LVDSII N LVDS42 N G8 LVDS28 N 87 LVDS58 90 GND15 GND GND35 89 GND 2 LVDSI2P LVDS43 P U8 LVDS29 P 91 LVDS59_P R7 94 LVDSI2 N LVDS43_N U9 LVDS29 N 93 LVDS59 N R8 96 GND16 GND GND36 95 GND 98 LVDSI3 P LVDS44 P T10 LVDS30 P 97 LVDS60 P D7 100 LVDSI3 N LVDS44 N T11 LVDS30 N 99 LVDS60 N E7 102 GND17 GND GND37 101 GND 104 LVDS14 P LVDS45_P J8 LVDS31 P 103 LVDS61 P P7 106 LVDSI4 N LVDS45 N J7 LVDS31 105 LVDS61 N P8 108 GND18 GND GND38 107 GND 110 LVDSIS P LVDS46 P 011 LVDS32 109 LVDS62_P E9 112 LVDSIS N LVDS46_N LVDS32 111 LVDS62 E8 114 GND19 GND GND39 113 GND 116 LVDSI6 P LVDS47 K8 LVDS33 P 115 LVDS63 P N9 118 LVDSI6 N LVDS47 N K9 LVDS33 117 LVDS63 N N8 120 GND20 GND GND40 119 GND 24 www HiTechGlobal com Table 4 b High Speed LVDS Connectors Summary Connector 2 Upper Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 5 3 LED Switches amp Push Buttons The HTG V5 PCIE XXX is populated with one user DIP Switch SWS eight user LEDs 3 Push Buttons user Reset PCIE Reset and PCIE Wake Table 5 illustrates the FPGA pin assignmen
21. Cores FXT Only Embedded PowerPC 440 PPC440 cores Up to 550 MHz operation Greater than 1000 DMIPS per core Seven stage pipeline Multiple instructions per cycle Out of order execution 32 Kbyte 64 way set associative level 1 instruction cache 32 Kbyte 64 way set associative level 1 data cache Book E compliant ntegrated crossbar for enhanced system performance 128 bit Processor Local Buses PLBs ntegrated scatter gather DMA controllers Dedicated interface for connection to DDR2 memory controller Auto synchronization for non integer PLB to CPU clock ratios Auxiliary Processor Unit APU Interface and Controller Direct connection from PPC440 embedded block to FPGA fabric based coprocessors 128 bit wide pipelined APU Load Store Support of autonomous instructions no pipeline stalls Programmable decode for custom instructions 1 7 Tri Mode 10 100 1000 Mb s Ethernet Media Access Control MAC Virtex 5 FXT LXT SXT devices contain four embedded Ethernet MAC blocks The blocks have the following characteristics IEEE 802 3 compliant UNH compliance tested MII GMII Interface with SelectIO or SGMII interface when used with RocketIO transceivers Half or full duplex Supports Jumbo frames 1000 Base X PCS PMA When used with RocketIO GTP transceiver can provide complete 1000 Base X implementation on chip DCR bus connection to microprocessors
22. H E SystemACE E PROM File Formatter vallable Operations are Additional reading for Boundary Scan Virtex 5 devices support IEEE standards 1149 1 and 1532 IEEE 1532 is a standard for In System Configuration ISC based on the IEEE 1149 1 standard JTAG is an acronym for the Joint Test Action Group the technical subcommittee initially responsible for developing the standard This standard provides a means to ensure the board level integrity of individual components and the interconnections between them The IEEE 1149 1 Test Access Port and Boundary Scan Architecture is commonly referred to as JTAG With multi layer PC boards becoming increasingly dense and more sophisticated surface mounting techniques in use Boundary Scan testing is becoming widely used as an important debugging tool Devices containing Boundary Scan logic can send data out on I O pins in order to test connections between devices at the board level The circuitry can also be used to send signals internally to test the device specific behavior These tests are commonly used to detect opens and shorts at both the board and device level In addition to testing Boundary Scan offers the flexibility for a device to have its own set of user defined instructions The added common vendor specific instructions such as configure and verify have increased the popularity of Boundary Scan testing and functionality Additional information is available at http
23. LINK1000 J20J21 Figure 10 Jumper Setting PHY J22 J23 pins 1 2 GMII MII to Cu J22 J23 pins 2 3 SGMII to Cu no clk J22 pins 2 3 J7 ON RGMII modified MII in Cu VCC2V5 VCC2V5 15 PHYB CONFIG5 PHYB LED LINK10 PHYB CONFIG4 PHYB LED DPLX PHYB LED LINK1000 J22J23 Figure 11 PHY A Jumper Setting Bank FPGA Pin Description FPGA Pin Number PHY Pins PHYB_TXDO PHYB_TXDI PHYB PHYB TXD PHYB TXD4 PHYB TXD6 TXD 1014 PHYB TXEN IO LAN VREF 18 5 PHYB TXER 40 www HiTechGlobal com N 1 N 1 12 1 PHYB TXDS 1 1 1 Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 18 IO L5P 18 AC8 PHYB INT Ans ADIO 7 ACS AC APS AFG ADS ADT 18 IO LI3N 18 7 NC AES ADS AFT ADS AES AF10 ABS AEIO AFI 18 IO LI9N 18 AF12 PHYB RXER MGTTXPO 114 ACI PHYB TXP MGTTXNO 114 ADI PHYB TXN MGTRXPO 114 AB2 PHYB RXP MGTRXNO 114 AC2 PHYB Table 15 PHY B Pin Assignment 41 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 10 SMA Interface Picture 12 SMA Connectors Two RocketIO GTP GTX ports are connected to 8 SMA connectors TxN TxP RxN and RxP The GTP GTX reference clock is provided externally through 136 and J38 SMA conn
24. computer Before the PROM operations are executed iMPACT must load the bridge JTAG to BPI bitstream into the Virtex 5 FPGA After the JTAG to BPI bitstream is loaded iMPACT performs a synchronization query on the FPGA design and then performs CFI read on the attached BPI PROM After successful completion of these steps the desired PROM operation is issued A portion of the iMPACT message log for an erase operation is shown below Note This message log can vary slightly based on the BPI PROM operation issued and the version of the iMPACT software used Load the JTAG to BPI bitstream into the Virtex 5 FPGA and ensure the design is synchronized INFO iMPACT FW Created an MDM Uart Interface INFO iMPACT FW Created an MDM FSL Interface INFO iMPACT FW Sending SYN INFO iMPACT FW Awaiting ACK INFO iMPACT FW Resync succeeded Performing a standard CFI read on the attached BPI PROM Populating BPI CFT INFO iMPACT FW Loading CFI engine PROGRESS_START Starting Operation INFO 1 182 done INFO iMPACT FW Sending target CFI query cmd INFO iMPACT FW Sending meminfo to target bus width 16 INFO iMPACT FW Retrieving CFI query info CFI Query completed successfully XAPP973 v1 2 February 6 2008 www xilinx com 64 Software Flows for BPI File Preparation and Programming XILINX PROM parameter setup is established and Erase command sequen
25. detection function is open drain active Low clearing it s configuration enabled INIT B is Input or output output indicating whethera memory If CRC error is optionally driven Low INIT B when a read back NC open drain CRC error occurred during configuration detected during configuration FPGA drives INIT B Low again 0 CRC error 1 No CRC error error is detected XAPP973 v1 2 February 6 2008 www xilinx com 50 Introduction Table 3 Virtex 5 FPGA BPI Configuration Mode Signals and Descriptions Cont d 2 XILINX Intel Virtex 5 Direction StrataFlash FPGA Pin During Description During Configuration After Configuration P30 Common Name Configuration Signal Connection The Mode pins determine Must be at valid logic levels Dedicated M 2 0 the BPI mode for desired mode when M 2 0 Input 010 mode sampled at INIT going High NC 101 JTAG mode Active Low asynchronous Must be High during Dedicated PROG_B PROG_B Input full chip reset configuration to allow for RST configuration start Revision select pins Not RS 1 0 can be controlled User 1 used for typical single by the user through the bitstream applications bitstream or ICAP 3 stated and pulled up with weak resistors during the initial configuration after power RS 1 0 Output up or assertion of NC RS 1 0 are actively driven Low to l
26. direct xilinx com bvdocs userguides ug191 pdf 44 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Platform Flash Programming 41 45 4 7K R114 BPI Mode Jumper Setting http www xilinx com support documentation application_notes xapp973 pdf 45 www HiTechGlobal com Application Note 5 FPGAs Indirect Programming of PROMs with Virtex 5 FPGAs Author Stephanie Tapp 2 XILINX XAPP973 v1 2 February 6 2008 Summary Support for direct configuration from parallel NOR flash memory PROMs is included Virtex 5 Platform FPGAs creating an attractive solution for high density designs To support this new configuration mode iMPACT has added indirect programming support for select PROMs during prototyping This application note demonstrates how to program a Intel StrataFlash P30 BPI PROM indirectly using iMPACT 9 2i and a Xilinx cable In this solution the Virtex 5 FPGA serves as a bridge between the IEEE STD 1149 1 JTAG bus interface and the BPI bus interface The required hardware setup BPI UP PROM file generation flow and BPI indirect programming flow are shown The Virtex 5 FPGA BPI UP configuration sequence is also described Note Parallel NOR flash memory is referred to by the term PROM throughout this document Introduction Xilinx FPGAs are CMOS configurable latch CCL based and must be configured at power up from a
27. for a Intel StrataFlash JS28F256P30T BPI PROM If another package is selected please refer to the vendor s data sheet for any signal connection variations Caution iMPACT supports only the 16 bit data bus mode for PROM programming with Virtex 5 FPGAs If the Intel Embedded J3 v D family is chosen the data bus must be connected for the 16 bit mode to be programmed with iMPACT Hardware for PROM Indirect Programming Figure 2 page 4 shows a typical hardware setup used for Virtex 5 FPGA BPI configuration and indirect PROM programming When configuring a Virtex 5 FPGA in the BPI configuration mode the setup typically consists of a master device FPGA and a slave device BPI PROM Refer to the 5 FPGA Configuration from PROMs page 22 for details on the configuration sequence of the FPGA after the BPI PROM is successfully programmed Although Virtex 5 FPGAs support both 8 bit and 16 bit data bus width access for configuration the 16 bit mode is highlighted because the iMPACT BPI PROM programming only supports the 16 bit data bus width XAPP973 v1 2 February 6 2008 www xilinx com 48 Introduction x XILINX In BPI configuration mode the Virtex 5 FPGA configures itself from an industry standard parallel NOR Flash PROM as illustrated in Figure 2 Ribbon Cable Header for FPGA JTAG Configuration Intel SrataFlash JS28F256P30 3 3V 1 0V 3 3V BPI PROM
28. giving access functions to all the resources on the hardware Kernel Mode Performance WinDriver s API is optimized for performance For drivers that need kernel mode performance WinDriver offers the Kernel PlugIn This powerful feature enables you to create and debug your code in user mode and run the performance critical parts of your code such as the interrupt handling or access to I O mapped memory ranges in kernel mode thereby achieving kernel mode performance zero performance degradation This unique feature allows the developer to run user mode code in the OS kernel without having to learn how the kernel works There is no need to use the Kernel PlugIn when working with Windows CE or VxWorks since there is no separation between user and kernel modes in these operating systems This enables you to achieve optimal performance from user mode code Chapter 4 Intellectual Property IP Cores 4 1 PCI Express The HTG V5 PCIE XXX is designed to host any PCI Express PCI SIG compliant core or use the hard coded End point block in Virtex 5 LXT The PCI Express IP core used in the board s reference design supports following features High performance easy to use core Endpoint and Root Port support x1 x4 x8 lane versions available 32 and 64 bit address support Legacy interrupt and MSI support Status Port provides detailed access to low level core status and data Complete PCI Express PHY support including integrated
29. lines If the upper PROM address signals are tied to the FPGA RS 1 0 pins for a Fallback or Multiboot implementation the indirect programming solution cannot erase or program the BPI PROM address space accessed by the upper two address signals It is necessary to jumper the FPGA RS 1 0 pins with the FPGA upper address signals to combine the two setups Figure 2 Configuration Mode Setup Master 5 FPGA and Slave PROM XAPP973 v1 2 February 6 2008 www xilinx com 49 Introduction Virtex 5 FPGA BPI Configuration Signals The BPI configuration mode interface signals that influence the successful start and stop of data transfer are listed in Table 3 Details on the Virtex 5 FPGA configuration sequence and power up considerations are discussed in Power On Considerations for Configuration page 22 Table 3 Virtex 5 FPGA BPI Configuration Mode Signals and Descriptions 5 XILINX Intel Virtex 5 Direction StrataFlash FPGA Pin During Description During Configuration After Configuration P30 Common Name Configuration Signal Connection Address output Connects to PROM User 1 00 3 4 25 010 Output address 24 1 0 Configuration clock output FPGA drives clock for Dedicated CCLK user Output CCLK does not directly internal configuration logic controllable CCLK treat as I O for EM but NC signal integrity merna y tO
30. responsible for obtaining any rights they may require for their implementation HiTech Global expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose HiTech Global will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user HiTech Global products are not intended for use in life support appliances devices or systems Use of a HiTech Global product in such applications without the written consent of the appropriate HiTech Global officer is prohibited The contents of this manual are owned and copyrighted by HiTech Global Copyright 2002 2007 HiTech Global All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of HiTech Global Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Revision History Date Ve
31. user registers o Half of Base Address Register space is reserved for user registers o Simple fixed timing Register Interface makes adding user registers trivial Pre integrated with other IP Cores to provide a full out of the box PCI Express System Solution including o Reference design using PCI Express Core PCI Express Back End Multi Port Front End SDRAM Core and example Register and Target logic o PCI Express Verification Suite o Windows XP Vista Driver and Example Application o Linux Driver and Example Application Source code available Customization and Integration services available Expert technical support provided by core designers PCI Express Base Specification Revision 1 1 compliant 74 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual target write interface target read interface register interface PCI Express Base Core Receive Interface 1 4 Engnes Supported Interfaces are per Engine 522 cmd interface 52 data interface 52 direct contro completion Express Base Core Transmit A 25 direct control C25 cmd interface 25 data interface rd completion 1 4 Engines Supported Interfaces are per Engine Figure 32 PCI Express Back End Architecture 4 1 2 PCI Express Back End Module Descriptions RX Arbiter Arbitrates the base PCI Express core s receive interface o Received write requests are for
32. 2 14 14 MGTTXPI 128 B7 15 MGTRXNI 132 15 16 MGTTXNI 128 B8 17 GND2 18 GND8 19 MGTTXPI 132 B13 20 MGTTXPO 124 B6 21 MGTTXNI 132 4 22 MGTTXNO 124 B5 23 GND3 24 GND9 25 MGTTXPO 128 B12 26 124 AS 2 MGTTXNO 128 B11 28 MGTRXNO 124 A4 29 GND4 30 GND10 31 NC 32 33 34 34 GND5 36 GNDII 37 GTP CLCKO P 38 NC 39 GTP CLCKO N 40 NC Connector J15 Upper Connector FPGA Pin Connector Pin Signal Name Pin Signal Name MGTRXPI 124 MGTTXPI 116 3 MGTRXNI 124 MGTTXNI 116 5 GNDO 6 GND6 7 MGTTXPI 124 8 MGTTXPO 120 D2 9 MGTTXNI 124 B2 10 MGTTXNO 120 E2 11 GNDI 12 GND7 13 MGTTXPO 116 K2 14 120 EI 15 MGTTXNO 116 L2 16 MGTRXNO 120 Fl 17 GND2 18 GND8 19 MGTRXPO 116 L1 20 MGTRXPI 120 HI Pl MGTRXNO 116 MI 22 MGTRXNI 120 GI 23 GND3 24 GND9 25 MGTRXPI 116 P1 26 MGTTXPI 120 J2 27 MGTRXNI 116 NI 28 MGTTXNI 120 H2 29 GND4 30 GND10 31 NC 32 NC 33 NC 34 NC 34 GND5 36 GND11 37 GTP CLK2 P 38 NC 39 GTP CLK2 N 40 NC Table 2 Distribution of General Purpose RocketIO Ports www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 5 2 High Speed SelectI O Connectors 111111111111 11111111111111111111 Picture 2 High Speed Samtec QSE Connectors for 2 5 LVDS or 3 3 Single Ended IOs The HTG V5 PCIE XXX
33. 25V BANK 13 1 8V 500 21 33 29 Figure 4 User I O Allocation amp Distribution 2 5 1 General Purpose Data Rate Adjustable RocketIO GTP GTX Ports The HTG V5 PCIE XXX board provides access to 10 Reference Clock Adjustable RocketIO Gigabit Transceiver GTP GTX ports through two high speed Samtec connectors J14 and J15 with part number QSE 020 01 X D A http www samtec com ftppub pdf QSE PDF Each connector provides access to 5 RocketIO GTP GTX ports This makes the HTG V5 PCIE XXX a flexible platform for all SerialIO 16 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual standards The data throughputs of GTP GTX ports on these connectors are adjustable as illustrated in figure 5 a 5 b and 5 c and table 1 1 b and 1 c GTP 116 124 6128 Ul LX330T GTP 124 Tile Ref Clock GTP 120 132 amp 128 GTP GTP GTP CLK2 I U2 1CS843001 012 1 5874003 J SWI EXIT 25 10 Figure 5 a Adjustable Reference Clock for General Purpose RocketIO Ports 3 N2 NO SELO Pulkiown SEL1 Pulkiown SW3 Positions 0 1 2 02 ICS843001 XTAL INO XTAL OUTO X11 10 MHz XTAL IN1 OSC 01 XTAL OUT1 Detector X2 25MHz TEST Pulldown 10 X7 Socket MR Pulkiown M2 MO REF CLK OE R
34. 30T SX240T FX200T HTG V5 PCIE XXX User Manual SATA Host 0 SATA Host 1 Ul LX330T GTP 112 Tile Ref Clock 25 MHz 10 MHz Figure 9 Adjustable Reference Clock for SATA Ports Table 9 a and 9 b should be used for selection of and output dividers Inputs M Input Frequency MHz M2 1 0 SW2 6 key SW2 5 key SW2 4 key Value Minimum Maximum 0 0 0 18 31 1 38 9 0 0 1 22 25 5 31 8 0 1 0 24 23 3 29 2 0 1 1 25 22 4 28 0 1 0 0 32 17 5 21 9 1 0 1 40 14 0 17 5 Table 9 a ICS843001 U13 Programmable Output Divider Function Table Inputs N2 N1 NO SW2 3 key SW2 2 key SW2 1 key M Divider Value 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 1 0 1 6 1 1 0 8 1 1 1 10 Table 9 5 ICS843001 013 Programmable Output Divider Function Table 35 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T 112 112 FPGA Pin Description FPGA Pin Number SATA Connector SATA Host TX0 P SS HTG V5 PCIE XXX User Manual MGTRXPO_112 SATA Host MGTRXNO 112 996 SATA Host RXO N MGTREFCLKP 112 112 MGTAVTTRXC Table 10 SATA Pin Description SATA Host and Device IP Cores are available thro
35. 40T FX200T HTG V5 PCIE XXX User Manual JTAG Serial SelectMAP SPI and BPI and it discusses flows and techniques for bitstream encryption readback and reconfiguration Virtex 5 Packaging and Pinout Specification http direct xilinx com bvdocs userguides ug195 pdf This user guides describes Virtex 5 device pinouts and package specifications and pinout diagrams and thermal data Virtex 5 RocketIO GTP Transceiver User Guide http direct xilinx com bvdocs userguides ug196 pdf This guide describes the RocketIOTM GTP transceivers available in the Virtex 5 LXT platform devices Virtex 5 RocketIO GTX Transceiver User Guide http www xilinx com support documentation user_guides ug198 pdf This guide describes the RocketIOTM GTP transceivers available in the Virtex 5 FXT platform devices LogiCORE IP Endpoint Block Plus for PCI Express User Guide http www xilinx com support documentation ip_documentation pcie_ blk plus ug341 pdf This guide describes the functionality of the Endpoint Block Plus wrapper for PCI Express using the Integrated Endpoint Block for PCI Express available in the Virtex 5 LXT SXT FXT devices Virtex 5 Embedded Tri Mode Ethernet MAC User Guide http direct xilinx com bvdocs userguides ug194 pdf This guide describes the dedicated Tri Mode Ethernet Media Access Controller MAC available in the Virtex 5 LXT platform devices Virtex 5 System Monitor User Guide http direct xilinx com bvdocs userguides ug192 pdf This g
36. 438 Q O C268 DSW 0517 0510 59 9 7 x 5 cum abs 0514 0518 0518 0520 5 22 e 136 38 e ae e 428 5 134 5 e 5 3 2 4 e ec e e e 45 230 MHS gt a SILK TOP 782 68mil E 15 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 5 User I O amp Distribution The on board Virtex 5 XC5VLX330T SX240T FX200T FF1738 provides total of 960 user I Os which have been used for connection of different peripherals and components to the FPGA device Figure 4 illustrates distribution and allocation of the XC5VLX330T FF1738 user I Os Virtex 5 SX240T and FX200T devices have the same number of Select and RocektIOs MGT 124 MGT 128 MGT 132 BANK 31 BANK 27 CONN CONN x2 x2 MGT 120 CONN x2 BANK 20 MGT 116 CONN x2 MGT 112 SATA x2 CLK MGT 114 SGMII x2 MGT 118 PCIe x2 CLK MGT 122 PCIe MGT 126 900 25V 254 50 2910 P BANK 12 BANK 18 SOCEM OOK SOCIMN BANK 26 MGT 130 PCle 11 501 95 L VOS 2 5V 25V 500 9 BANK 15 BANK 17 10 500
37. 5 GND 196 11 IO L5P 11 L42 DIMM SCL 197 11 IO 2 11 141 DIMM 5 0 198 8 199 11 IO L5N 11 M41 DIMM SAI 200 Table 6 DDR2 Memory Connections Summary 2 7 PCI Express Picture 5 8 Lane PCI Express End Point The RocketIO GTP GTX Transceivers are used as PCI Express PHY and connected to the hard coded PCI Express Endpoint block of the on board Virtex 5 LX330T SX240T FX200T FPGA The HTG V5 PCIE 330 and 240 boards can be used for PCI Express Gen x1 x2 x4 x8 End Point applications The HTG V5 PCIE 200 board can be used for PCI Express Gen 1 x1 x2 x4 x8 using on chip hard coded PCIe block and Gen 2 x1 x2 x4 using soft IP core provided by HiTech Global As illustrated in table 7 eight RocketIO GTP GTX Transceivers of Virtex 5 LX330T SX240T FX200T are connected to an 8 lane upstream connector for PCIE end point applications GTP GTX 118 122 126 and 130 tiles Pin Description FPGA Pin Number Signal Name PCIe Connector Pin MGTTXPO 118 PERO C P 16 MGTAVTTTX 118 AVTTTIX M8 MGTTXNO 118 PERO C N 18 An B an Bis aw avcm ns AL 520 31 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual MGTREFCLKN 118 AK3 Bis AD MGTTXPO 122 MGTAVTTTX 122 MGTTXNO 122 MGTRXPO 122 MGTAVTTRX 122 MGTRAND 122 MGTAVCCPLL 122 MGTRXNL 122 MGTREFCLKN 122 MGTRXPI 122 MGTREFC
38. 5 FPGA Configuration from PROMs XILINX Virtex 5 FPGA Configuration from BPI PROMs Power On Considerations for BPI Configuration After the BPI PROM is successfully programmed with iMPACT pulsing the Virtex 5 FPGA s PROG B pin allows the FPGA to be configured from the PROM This section describes the Virtex 5 FPGA configuration sequence followed in the BPI configuration mode where a Virtex 5 FPGA is the master and the PROM is the slave An overview of the 5 FPGA configuration mode timing diagram is shown in Figure 21 In addition to a reconfiguration started by pulsing the PROG pin power cycling also initiates a configuration from the PROM with the mode pins set to the appropriate BPI configuration mode For the example described in this application note the modes pins are set to BPI UP configuration mode M 2 0 010 After initiating a configuration the Xilinx FPGA goes through an initialization sequence to clear the internal FPGA configuration memory At the beginning of this sequence both the DONE and INIT B pins go Low When initialization is finished the INIT B pin goes High and B and FOE go Low BPI configuration mode the CCLK output is not connected to the PROM however the internal FPGA configuration logic uses CCLK as reference The data is sampled by the FPGA on the rising edge of CCLK The CCLK output must receive the same parallel termination as i
39. 8 GND 149 GND 150 15 IO L19N 15 W37 DIMM DQ42 151 15 IO L16P 15 AA35 DIMM 0046 152 15 IO L18P 15 Y35 DIMM DQ43 153 29 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 15 IO L16N 15 AA36 DIMM DQ47 154 GND 155 GND 156 15 IO L13N 15 U38 DIMM DQ48 157 15 IO L13P 15 T37 DIMM 052 158 15 IO 115 15 W38 DIMM DQ49 159 15 IO L15P 15 V39 DIMM 053 160 GND 161 GND 162 NC 163 15 IO L8P CC 15 M38 DIMM CLKI P 164 GND 165 15 IO L8N CC 15 L39 DIMM 166 15 IO L9N CC 15 J38 DIMM DQS6 N 167 GND 168 15 IO L9P CC 15 K38 DIMM DQS6 P 169 15 IO L14P 15 T39 DIMM DM6 170 GND 171 GND 172 15 IO LIP 15 G38 DIMM DQ50 173 15 IO L6P 15 P38 DIMM 0054 174 15 IO L7N 15 M39 DIMM 051 175 15 IO L6N 15 N38 DIMM DQ55 176 GND 177 GND 178 15 IO L7P 15 N39 DIMM DQ56 179 15 IO LIN 15 G39 DIMM 0060 180 15 IO L4P 15 R39 DIMM 0057 181 15 IO L5P 15 R37 DIMM DQ61 182 GND 183 GND 184 15 IO L5N 15 P37 DIMM DM7 185 15 IO LIIN CC 15 K39 DIMM DQS7 N 186 GND 187 15 IO CC 15 K40 DIMM DQS7 P 188 15 IO L3P 15 E39 DIMM DQ58 189 GND 190 15 IO L3N 15 E40 DIMM 0059 191 15 IO L2N 15 F40 DIMM DQ62 192 30 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual GND 193 15 IO L2P 15 F39 DIMM DQ63 194 11 IO L7P 1 N40 DIMM SDA 19
40. A CardBus ISA EISA CompactPCI PCI Express PCMCIA is supported only on Windows 2000 XP Server 2003 WinDriver provides a complete solution for creating high performance drivers Easy Development WinDriver enables Windows 98 Me NT 2000 XP Server 2003 CE NET Linux Solaris and VxWorks programmers to create PCI PCMCIA CardBus IS A EISA CompactPCI PCI Express based device drivers in an extremely short time WinDriver allows you to create your driver in the familiar user mode environment using MSDEV Visual C C MSDEV NET Borland C Builder Borland Delphi Visual Basic 6 0 MS eMbedded Visual C MS Platform Builder C GCC or any other appropriate compiler You do not need to have any device driver knowledge nor do you have to be familiar with operating system internals kernel programming the DDK ETK or DDI DKI Cross Platform 71 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual The driver created with WinDriver will run on Windows 98 Me NT 2000 XP Server 2003 CE NET Linux Solaris and VxWorks In other words write it once run it on many platforms Friendly Wizards DriverWizard included is a graphical diagnostics tool that lets you view define the device s resources and test the communication with the hardware with just a few mouse clicks before writing a single line of code Once the device is operating to your satisfaction DriverWizard creates the skeletal driver source code
41. C34 DIMM 101 17 IO LOP 17 AB34 DIMM A0 102 VCCIV8 103 VCCIV8 104 17 IO L5N 17 AE38 DIMM 10 105 17 IO L9P CC 17 AR40 DIMM BAI 106 17 IO L8N CC 17 AP40 DIMM BAO 107 11 IO L2P 11 H41 DIMM RAS 108 11 IO LIP 11 41 DIMM WE N 109 11 IO L6P 11 M42 DIMM S0 N 110 VCCIV8 111 VCCIV8 112 11 IO LIN 11 641 DIMM CAS N 113 11 IO LOP 11 F42 DIMM ODT 114 28 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 11 IO L7N 11 P40 DIMM SI 115 17 IO L8P CC 17 40 DIMM A13 116 VCCIV8 117 VCCIV8 118 DIMM ODT 119 NC 120 GND 121 GND 122 11 IO L16N SMI2N 11 V41 DIMM 0032 123 11 IO L17N SMIIN 11 W41 DIMM 0036 124 11 IO L19P SM9P 11 AA42 DIMM 0033 125 11 IO L18N SMION 11 42 DIMM DQ37 126 GND 127 GND 128 11 IO LION CC SMISN 11 Y38 DIMM 0084 N 129 11 IO L19N SM9N 11 41 DIMM DM4 130 11 IO L10P CC SM15P 11 Y39 DIMM DQS4 P 131 GND 132 GND 133 11 IO L16P SMI2P 11 042 DIMM DQ38 134 11 IO L14P 11 T40 DIMM DQ34 135 11 IO L17P SMIIP 11 V40 DIMM DQ39 136 11 IO L18P SMIOP 11 W42 DIMM DQ35 137 GND 138 GND 139 15 IO LON 15 H39 DIMM DQ44 140 15 IO 117 15 Y34 DIMM DQ40 141 15 IO L17P 15 AA34 DIMM DQ45 142 15 IO L18N 15 W35 DIMM 0041 143 GND 144 GND 145 15 IO LION CC 15 J40 DIMM 085 N 146 15 IO L19P 15 W36 DIMM DM5 147 15 IO L10P CC 15 H40 DIMM 0085 P 14
42. EF Pulkiown Figure 5 b Input output Frequency Scheme Step 1 17 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual OEA Pullup Pulldown F_SEL2 0 To J14 nQAD QA1 Puldown nQA1 nCLK P 124 ref Input Clock from U2 M 5 fixed To 415 M Input Frequency MHz M2 Divider SW3 6 key SW3 5 key Value Minimum Maximum 0 0 0 18 31 1 38 9 0 0 1 22 25 5 31 8 0 1 0 24 23 3 29 2 0 1 1 25 22 4 28 0 1 0 0 32 17 5 21 9 1 0 1 40 14 0 17 5 Table 1 ICS843001 02 Programmable Output Divider Function Table Inputs N2 1 NO SW3 3 key SW3 2 key SW3 key M Divider Value 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 8 1 1 1 10 F SEL2 F_SEL1 F_SELO QA0 nQAO0 0 0 0 0 0 258 2 1 0 0 5 2 0 0 1 1 1 1 1 1 4 4 Table 1 c ICS874003 012 SEL 2 0 Function Table 18 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual MGTTXPO 132 8 MGTRXPO 128 1 2 3 MGTTXNO 132 B17 4 MGTRXNO 128 10 5 GNDO 6 GND6 7 132 Al7 8 MGTRXPI 128 8 9 MGTRXNO 132 16 10 MGTRXNI 128 A9 11 GNDI 12 GND7 13 MGTRXPI 13
43. G V5 PCIE XXX User Manual Bit 0 0 000 CONFIGI PAUSE PHYADR 4 PHYADR 3 000 PHY Address 00000 Do not advertise the PAUSE bit CONFIG2 ANEG 3 ANEG 2 ANEG 1 111 CONFIG3 ANEG 0 ENA XC DIS 125 111 Auto Neg enabled advertise all capabilities prefer slave Auto crossover enabled 125 CLK option disabled CONFIG4 HWCFG 2 HWCFG HWCFG MODE 0 111 5 DIS FC DIS SLEEP HWCFG MODE 3 111 to Cu mode Fiber copper auto detect disabled Sleep mode disabled CONFIG6 SEL_BDT INT POL 75 50 OHM 010 MDC MDIO selected Active LOW Interrupt 500hm SERDES option Table 13 PHY A amp Configuration Pin to Constant Mapping Pin Bit 2 0 VCC2V5 111 PHY LED LINKIO 110 PHY LED LINK100 101 PHY LED LINK1000 100 PHY LED DUPLEX 011 PHY LED RX 010 PHY LED TX 001 GND 000 Table 14 Pin To Constant Mapping 39 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 10 100 1000 Ethernet Jumper Setting PHY A J20 J21 pins 1 2 GMII MII to Cu 420 J21 pins 2 3 SGMII to Cu no clk J20 pins 2 3 J6 ON RGMII modified MII in Cu VCC2V5 VCC2V5 13 CONFIG5 PHYA LED LINK10 4 PHYA LED DPLX PHYA LED
44. GND24 23 GND 26 LVDSA4 LVDS4 H34 LVDS21 P 25 LVDS20 P F31 28 LVDS4 N LVDS4 N G34 LVDS21 N 27 LVDS20 F32 30 GND4 GND GND25 29 GND 32 85 85 F35 LVDS22 P 31 LVDS21 P K32 34 LVDSS 55 E35 LVDS22 N 33 LVDS21 N J32 36 GNDS5 GND GND26 35 GND 38 LVDS6 P LVDS6 P E32 LVDS23 P 37 LVDS22 P P33 40 LVDS6 N LVDS6 N E33 LVDS23 N 39 LVDS22 N P32 42 LVDS7 P LVDS7 P K33 LVDS24 P 41 LVDS23 P T32 44 LVDS7 N LVDS7 N J33 LVDS24 N 43 LVDS23 N U32 46 GND7 GND GND27 45 GND 48 PWRO LVDS66_P PWR6 47 LVDS64 P 50 PWRI LVDS66 N PWR7 49 LVDS64 N 52 GND8 GND GND28 51 GND 54 PWR2 VCCO PWRS 53 VCC2V5 56 PWR3 VCCO PWR9 55 VCC2V5 58 GND9 GND GND29 57 GND 60 LVDSS8 DIFFCLK J16 LVDS25 P 59 DIFFCLKI _ M26 0 P P 62 LVDS8 N DIFFCLK J15 LVDS25 N 61 DIFFCLKI _ L27 0 N N 64 GND10 GND GND30 63 GND 66 PWR4 VCCO 10 65 VCC2V5 68 PWRS VCCO 11 67 VCC2V5 70 GND11 GND GND31 69 GND 12 LVDS9 P LVDSS8 N35 LVDS26 P 71 LVDS24 P N36 74 LVDS9 N LVDS8 N M36 LVDS26 N 73 LVDS24 N P36 76 GND12 GND GND32 75 GND 78 LVDS10 P LVDS9 P L36 LVDS27 P 77 LVDS25 P K35 80 LVDS10_N LVDS9 N L35 LVDS27 N 79 LVDS25 N J35 82 GND13 GND GND33 81 GND 22 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 84 GNDI4 GND GND34 83 GND 86 LVDS11 P LVDSIO P H35 LVDS28 P 85 LVDS26 P T34 88 LVDSII LVDSIO
45. INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA LOST PROFITS OR FOR ANY SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE XAPP973 v1 2 February 6 2008 www xilinx com 69 Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 70 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Chapter 3 PCI Express Software amp Drivers The HTG V5 PCIE XXX board is shipped with the evaluation version of PCIE drivers WindDriver The WinDriver evaluation is valid for period of 30 days A complete list of PCI drivers are posted at http hitechglobal com DesignTools PCIDrivers htm WinDriver is a development toolkit that dramatically simplifies the difficult task of creating device drivers and hardware access applications WinDriver includes a wizard and code generation features that automatically detect your hardware and generate the driver to access it from your application The driver and application you develop using WinDriver is source code compatible between all supported operating systems WinDriver currently supports Windows 98 Me NT 2000 XP Server 2003 CE NET Linux Solaris and VxWorks The driver is binary compatible between Windows 98 Me NT 2000 XP Server 2003 Bus architecture support includes PCI PCMCI
46. LKP 122 MGTIXNI 122 122 122 MGTTXPO 126 MGTAVTTTX 126 MGTTXNO 126 MGTRXPO 126 MGTAVTTRX 126 MGTRXND 126 MGTAVCCPLL 126 MGTRXNL 126 MGTREFCLKN 126 MGTRXPI 126 MGTREFCLKP 126 MGTTXNI 126 BAS 126 AY6 MGTTXPI 126 MGTTXPO 130 7 130 MGTTXNO 130 MGTRXPO 130 BB8 MGTAVTTRX_130 AYS MGTRXNO 130 BB9 9 NG 32 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual MGTREFCLKP 130 AWO NC An avi aveo An _ ma wen avec aws avoe aws wes o Table 7 PCI Express Upstream Connections Summary PCI Express Jitter Attenuator An IDT ICS874003 02 is used as PCI Express Jitter Attenuator on the HTG V5 PCIE XXX board This chip is a high performance Differential to LVDS Jitter Attenuator designed for use in PCI Express systems In some PCI Express systems such as those found in desktop PCs the PCI Express clocks are generated from a low bandwidth high phase noise PLL frequency synthesizer In these systems a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board Figures 8 and Table 8 illustrate the implementat
47. M file image size in kilobytes The u 0 option specifies the data to start at address zero and fill the data array in the up direction The bitfile bit is the input bitstream file Table 6 Example PROMGen BPI PROM File Options PROMGen Option Description p lt f x PROM output file format Commonly accepted PROM file formats include Intel Hex mcs and Motorola Hex exo Specifies the size kilobytes The PROM size must power of 2 for this option The default setting is 64 kB Loads the bit file from the specified starting address in an u address upward direction This option must be specified immediately before the input bitstream file Specifies the data width of the targeted PROM For example data width width data width 8 specifies a byte wide PROM The default setting for the data width option is 8 Notes 1 Referto the PROMGen Software Manual for complete command line options and further details Preparing a BPI PROM File Using the ISE iMPACT Graphical Software The ISE iMPACT 9 2i software integrates PROM file formatting and in system programming features behind an intuitive graphical user interface The PROMGen file formatting functionality is provided through a step by step wizard in the iMPACT software The wizard steps through the output PROM file options and input bitstream selections After selecting all of the parameters using the wizard the final
48. P 12 PHYA 0 IO LON 1 PHYA TXDI IO L1 PHYA TXD2 5 5 PHYA TXD4 5 N 37 www HiTechGlobal com N 12 N 12 12 N 12 P 12 N Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 13 IO L5P 12 J6 PHYA INT PHYA TXCLK PHYA GTXCLK ic PAYA RXCLK 12 IO L13N 12 T6 NC NC NC PIA RXDO o founso n PHYA RXD2 fonno amo PHYA RXD4 Yi PHYA RXDS fome wi RX PHYA RXD7 PHYA RXDV 12 IO L19N 12 Y8 PHYA MGTTXPI 114 AG2 PHYA TXP MGTTXNI 114 AF2 PHYA TXN MGTRXPI 114 AFI PHYA RXP MGTRXNI 114 PHYA RXN Table 12 PHY A Pin Assignment The HTG V5 PCIE XXX board supports MII RGMII and SGMIII interface modes with the FPGA The PHYs are connected to two hard coded 10 100 1000 Ethernet Media Access Controllers MACs inside the Virtex 5 FPGA Two RocketIO GPT GTX ports have also been used to support SMII interface The other sides of PHYs are connected to two Halo HFJ11 1GO01E RJ 45 Eth A and Eth B Connectors with built in magnetic 25 MHZz crystal supplies the clock signal to the PHY The PHY is configured to default at power on or reset these settings may be overwritten via software I O connections to the Ethernet PHY are summarized in Table 11 38 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T Pin CONFIGO Bit 2 PHYADR Bit 1 PHYADR I HT
49. PACT C Xilinx91i default ipf Boundary Scan G File Edit View Operations Output Debug Window Help 89 Scan 3 Configuration 2 SPI Configuration E xcSvix50 s PROM File Formatter bitfile bit iMPACT Processes Available Operations are Program Verify Blank Check m Readback perations B Boundary Scan eu Program Erase Get Device ID Blank Check Readback Assign New Configuration File Delete Selected part INTEL28F256P30 BATCH CMD attachflash position 1 bpi INTEL28F256P30 BATCH CMD assignfiletoattachedflash position 1 file C Virtex5 BPI PROM mcs Output Error Warming _ Figure 20 Verify Operation Configuration Platform Cable USB 6 MHz usb hs X973 20 020608 Save the iMPACT PROM project for quickly reprogramming of the PROM whenever the BPI PROM file is revised To reprogram the BPI PROM reopen the saved iMPACT project and invoke the Program operation ensure the selection of the Erase Programming Property and click OK iMPACT reprograms the PROM assuming the revised PROM file is located the same location as the original PROM file XAPP973 v1 2 February 6 2008 www xilinx com 66 Virtex
50. PHY FPGAs discrete PHY chips and PIPE compliant ASIC PHYs Provided with a full featured Verification Suite PCI Express Base Specification Revision 1 1 amp 2 0 compliant Fully hardware validated and PCI SIG certified 72 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Block Diagram PCI EXPRESS CORE PHY INTERFACE PCI Express x1 x4 or x8 Local Interface Status Error Info CLK CONFIGURATION AND MANAGEMENT CONFIGURATION REGISTERS 4 1 1 PCI Express Back End Features Key features PCI Express Core Support Provides low level PCI Express functionality o x1 x4 and x8 PCI Express Core soft core o x1 x4 and x8 Xilinx PCI Express Endpoint Block Plus Virtex 5 hard core DMA Interface o Very flexible easy to use high performance DMA implementation o Card to System C2S DMA Engine Takes data from user logic and makes DMA Write Requests to system memory Demand driven user interface _ Flexible Control DMA Descriptor Engine fetches DMA Descriptors from a linked list of Descriptors stored in system memory or user logic can directly control the DMA Engine o System to Card S2C DMA Engine Makes DMA Read Requests from system memory handles the resulting Read Completions and forwards read data to user logic Demand driven user interface Guarantees read data ordering re orders completions that were received out of order Flexible Control
51. SDRAM Memory Controller IP Core accepts read and write commands using a simple Local Interface and translate these requests to the command sequences required by DDR2 SDRAM devices The IP core also performs all initialization and refresh functions The DDR2 SDRAM Controller IP Core uses bank management techniques to monitor the status of each DDR2 SDRAM bank Banks are only opened or closed when necessary minimizing access delays Up to eight banks can be managed at one time Access cascading is also supported allowing read or write requests to be chained together This results in no delay between requests enabling up to 10096 memory throughput for sequential accesses The DDR2 SDRAM Controller IP Core is provided with run time programmable inputs for all timing parameters CAS Latency tRAS tRCD tRRD tRP tRC tRFC tMRD tXSNR tFAW tWR tWTR as well as memory configuration settings This ensures compatibility with virtually any SDRAM configuration The core is also available with hard coded timing and memory configuration parameters for designs requiring low logic utilization or for designs requiring high clock rate operation in slower FPGAs Core Deliverables 78 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Core Netlist or Source Code Comprehensive Verification Suite Source Code Complete Documentation Expert Technical Support amp Maintenance Updates Available Add on Cores
52. Tech Global is available at http www hitechglobal com ipcores The Virtex 5 HTG V5 PCIE XXX can be bundled and shipped with evaluation version of the following IP Cores DDR 2 Memory Controller http www hitechglobal com IPCores DDR2Controller htm SATA http hitechglobal com ipcores sata htm PCI Express Back End Provides a high performance DMA Engine and a simplified user interface 12 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 2 System Requirements HTG V5 PCIE XXX Board PCI Express Based Mother Board for PCI Express based developments Not required if the HTG V5 PCIE XXX is used as stand alone The following PC Mother board with multiple PCIe slots is available through HiTech Global http hitechglobal com Accessories PC htm with installed PCIECV test Windows drivers and interface GUI Xilinx ISE Foundation 10 1 2 3 Summary of Features Xilinx Virtex 5 LX330T SX240 or FX200T FPGA FF1738 package gt 8 Lane PCI Express End Point upstream Connector gt Up to 2 GB of SO DIMM DDR2 Memory the SO DIMM socket is populated on the flip side 2 RocketIO GTP GTX Ports accessible through 8 SMA connectors 4 Rx amp 4 Tx gt 10 Reference Clock Adjustable RocketIO GTP GTX Ports accessible through two high speed Samtec QSE connectors ideal to host add on modules such as PCI Express Root port SFP SATA etc gt 64 Pairs of 2 5V LVDS IOs
53. VDS19 N 15 LVDS50 N L11 18 GND2 GND GND23 17 GND 20 LVDS3 P LVDS35 P E10 LVDS20 P 19 LVDSS 1 P G13 22 LVDS3 LVDS35 N F10 LVDS20 N 21 LVDS51_N G14 24 GND3 GND GND24 23 GND 26 54 LVDS36 14 LVDS21 P 23 LVDS52_P 14 28 LVDS4 LVDS36 K13 LVDS21 N 27 LVDS52 E13 30 GND4 GND GND25 29 GND 32 85 LVDS37 12 LVDS22 31 1 853 34 LVDSS LVDS37 LVDS22 33 LVDS53 P12 36 GND5 GND GND26 35 GND 38 LVDS6 P LVDS38 P J13 LVDS23 P 37 LVDS54 E12 40 LVDS6 N LVDS38 N H13 LVDS23 N 39 LVDS54 D12 42 LVDS7 P LVDS39 P H10 LVDS24 P 41 LVDSS5 P 44 LVDS7 LVDS39 N J10 LVDS24 N 43 LVDS55 N10 46 GND7 GND GND27 45 GND 23 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 48 PWRO LVDS67 P PWR6 47 LVDS65 P 50 PWRI LVDS67 N PWR7 49 LVDS65 N 52 GND8 GND GND28 51 GND 54 PWR2 VCCO PWR8 53 VCC2V5 56 PWR3 VCCO PWR9 55 VCC2V5 58 GND9 GND GND29 57 GND 60 LVDS8 P DIFFCLK2 _ L29 LVDS25 P 59 DIFFCLK3 _ L16 P P 62 LVDS8 DIFFCLK2 K28 LVDS25 N 61 DIFFCLK3 _ L15 N N 64 GND10 GND GND30 63 GND 66 PWR4 VCCO PWRIO 65 VCC2V5 68 5 VCCO PWRII 67 VCC2V5 70 GNDII GND GND31 69 GND 12 LVDS9 P LVDS40 P V9 LVDS26 P
54. Virtex 5 LX330T FX200T SX240T HTG V5 PCIE XXX User Manual HiTech Global Virtex 5 LX330T FX200T SX240T Multi Purpose Development Platform PCI Express or Stand Alone Modes HTG V5 PCIE XXX User Manual www HiTechGlobal com Version 1 4 June 2008 Copyright HiTech Global 2002 2008 HTG V5 PCIE 330 HTG V5 PCIE 200 HTG V5 PCIE 240 VIRTEX 4 XC5VLX330T ew com HTG V5 PCIE 330 www HiTechGlobal Doc HTG DOC 902 cQ EXPHESS 1 www HiTechGlobal com Virtex 5 LX330T FX200T SX240T HTG V5 PCIE XXX User Manual n Jaden HiTech Global does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or mask work rights or any rights of others HiTech Global reserves the right to make changes at any time in order to improve reliability and functionality of this product HiTech Global will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products HiTech Global provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard HiTech Global makes no representation that such implementation is free from any claims of infringement End users are
55. a Virtex 5 FPGA The basic hardware setup required for the iMPACT indirect BPI PROM programming method is shown in Figure 1 iMPACT Virtex 5 FPGA with JTAG to BPI Bitstream S XUNX Platform Cable USB BPI PROM JTAG Bus BPI Bus X973 01 020608 Figure 1 iMPACT Indirect PROM Programming with a Virtex 5 FPGA Minimum Requirements e Virtex 5b FPGA programming support for 16 bit data width only PROM refer to Table 1 e Xilinx Cable and Connector refer to Table 4 page 6 ISE iMPACT Software 9 21 Selecting PROMs Several factors are considered when selecting a PROM including PROM family density package and the data bus width When using iMPACT 9 2i for programming the BPI PROM family must be selected from the supported list in Table 1 Table 1 BPI PROM Programming Capability with iMPACT PROM Vendor Family Density intel StrataFlash Embedded P30 28FxxxP30 64 256 Mb Embedded J3 v D 28FxxxJ3 9 32 128 Mb Notes 1 Refer to Software Flows for BPI File Preparation and Programming page 8 for more information 2 If another revision of the listed Intel flash families are being used please refer to the vendor s data sheet for any differences 3 iMPACT supports only the 16 bit data bus width for indirect programming via Virtex 5 FPGA family members XAPP973 v1 2 February 6 2008 www xilinx com 47 Intr
56. able pre emphasis or pre equalization for the transmitter Programmable termination and voltage swing Programmable continuous time equalization for the receiver Programmable decision feedback equalization for the receiver Receiver signal detect and loss of signal indicator User dynamic reconfiguration using secondary configuration bus 6 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual OOB support SATA Electrical idle beaconing receiver detection and PCI Express spread spectrum clocking support Low power operation at all line rates 1 5 Integrated Endpoint Block For PCI Express Works in conjunction with RocketIO GTP transceivers LXT and SXT and GTX transceivers FXT to deliver full PCI Express Endpoint functionality with minimal FPGA logic utilization Conforms to the PCI Express Base Specification 1 1 PCI Express Endpoint block or Legacy PCI Express Endpoint block x8 x4 x2 or x1 lane width Power management support Block RAMs used for buffering Fully buffered transmit and receive e Management interface to access PCIe configuration space and internal configuration Support for a wide range of maximum payload size up to 512Bytes with the Block Plus Wrapper One virtual channel VCs Round robin weighted round robin or strict priority VC arbitration Up to 6 x 32 bit or 3 x 64 bit BARs or a combination of 32 bit and 64 bit 1 6 PowerPC 440 RISC
57. as long as Descriptors are made available to execute o Accepts Descriptors from either the associated DMA Registers or from the DMA Direct Control Interface o Supports 32 64 bit System and Card address of any byte alignment Supports byte counts from to 2 32 1 bytes o Implements a Reorder Queue to ensure that DMA read requests are returned in order PCI Express Devices are permitted to reorder read transactions which is problematic for FIFO interfaces if not handled 4 2 Serial ATA The Serial ATA SATA Link and Transport Layer IP core provides an interface to high speed serial link replacements for the parallel ATA attachment of mass storage devices The serial link employed is a high speed differential layer that utilizes Gigabit technology and 8b 10b encoding This core is fully compliant to the Serial ATA 1 0a specification and provides some features of the Serial ATA SATA II extensions 76 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual SATA Main Features 10 bit PHY interface Connects to SAPIS compliant serial ATA SATA PHY Fully compliant to SATA Gen 1 1 2 Gb s and Gen 2 2 4 Gb s Wishbone slave interface for register access and FIFO DMA data transfers Only very few FF s in the PHY clock domain main part on the Wishbone clock 128 byte 32 double word data FIFO optional 256 byte Implements the shadow register block and the serial ATA SATA status and control registers Paralle
58. ata to the original requestor DWORD Master o Completes read write and message requests initiated on the Master Interface Processes read completions from read and I O Cfg write requests and returns data and status Common Registers o Implements centralized registers for DMA interrupts and global PCI Express Back End capabilities DMA Registers o Implements the DMA registers for one DMA Engine o Registers are used by software to control and to obtain status from the DMA Engine o Processes DMA Chains makes Descriptor read requests to the Descriptor Engine Descriptor Engine o Centralized resource for fetching Descriptors from system memory Supports 32 64 bit address Descriptor Pointers Card to System DMA Engine o Takes DMA Data from user logic and transmits data to PCI Express using write requests o Executes the PCI Express and user logic transactions to fulfill a single Descriptor returns status and repeats as long as Descriptors are made available to execute o Accepts Descriptors from either the associated DMA Registers or from the DMA Direct Control Interface o Supports 32 64 bit System and Card addresses of any byte alignment Supports byte counts from to 2 32 1 bytes System to Card DMA Engine o Transmits PCI Express read requests and writes the resulting read completion data to user logic Executes the PCI Express and user logic transactions to fulfill a single Descriptor returns status and repeats
59. board provides access to 68 pairs of LVDS IOs 2 5V or 136 Single Ended IOs 3 3V through two high speed Samtec connectors part number QSE 060 01 F D A http www samtec com ftppub cpdf QSE XXX 01 X D XXX MKT pdf The dedicated IO banks voltages are set via the J26 jumper bank 19 20 23 and 24 In addition to the QTE mating connectors used on daughter cards interfacing the HTG V5 PCIE XXX board Samtec also offers wide variety of mating cables The following 6 inche QSE to QSE cable is available through HiTech Global Part Number QSE TO QSE Picture 3 QSE To QSE Cable The high speed connectors can be used for connecting add on modules to the HTG V5 PCIE XXX board The J25 header with 3 3V and J24 with 5 0V provide power supply and higher current for any customized add on module these headers can also be used for powering up cooling fans VCC5VO Figure 6 Power Headers For Add On Modules 20 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Dedicated differential clocks are available on both J15 and J16 connectors Figure 7 illustrates the clock control circuit J16 QS Diff amp Diff J17 QSE Ul LX330T Figure 7 Adjustable Reference Clock for High Speed Connectors M2 0 SW4 6 key SW4 5 key SW4 4 key 0 0 0 18 31 1 38 9 0 0 1 22 25 5 31 8 0 1 0 24 233 292 0 1 1 25 224 28 0 1 0 0 32 17 5 21 9
60. ce is started INFO iMPACT FW Loading ERASE engine for command set Intel Extended INFO iMPACT 182 done INFO iMPACT FW Sending meminfo to target INFO iMPACT FW Sending devinfo to target INFO iMPACT FW Sending params to target INFO iMPACT FW Target is busy INFO iMPACT FW Block erase done 4 Erasure completed successfully After the Erase operation a program operation sequence begins iMPACT displays a Progress Dialog box as it progresses through the in system erase and program operations Figure 19 Progress Dialog 71 Executing command X973 19 020608 Figure 19 Progress Dialog Box After completing a program operation iMPACT reports a Program Succeeded message The iMPACT log should be checked for any error conditions XAPP973 v1 2 February 6 2008 www xilinx com 65 Software Flows for File Preparation and Programming 2 XILINX Step 8 Perform a Verify Operation Optional After the erase and program operations are completed the user can verify the BP PROM file contents with the Verify operation as shown in Figure 20 The verify read operation takes significantly longer refer to the Expectations page 23 than the erase program write operations and should not be exited prematurely Caution If the Platform Cable USB is used and the operation is stopped unexpectedly it is recommended to unplug and reconnect the cable to the PC iM
61. ck Finish to complete the wizard and proceed to step 7 of the process iMPACT File Generation Summary You have entered following information PROM Type Parallel File Format mcs Fill Value FF PROM filename PROM Number of PROMs 1 Position Part Name Click Finish to start adding device files X973 07 020608 Figure 7 Summary of BPI PROM File Selections Step 6 Automated Notification to Add an Device File to the BPI PROM File After the iMPACT project wizard is finished the iMPACT BPI PROM generation project is set to generate a specific PROM file with the specified parameters At this stage in the process the PROM file memory image is empty The sixth step in the process is to add an FPGA bitstream to the PROM file memory image This step begins immediately after completion of the iMPACT project wizard with an automatic notification that the next step is to add a device file to the BPI PROM memory image Click OK in the Add Device notification dialog box Figure 8 to proceed to step 7 of the process Add Device 4 Start adding device File Data Stream 0 X973_08_020508 Figure 8 Add Device Notification Dialog Box XAPP973 v1 2 February 6 2008 www xilinx com 57 Software Flows for BPI File Preparation and Programming XILINX Step 7 Select the FPGA Bitstream File to Add to the PROM Memory Image After the Add Device notification IMPACT automatically o
62. ectors The following conversion modules can be used in conjunction with the SMA connectors Picture 13 SMA to SFP Picture 14 SMA to SATA Picture 15 SMA to HSSDC2 Picture 16 SMA to RJ45 SMA to SMA cables are available through HiTech Global Part Number SMA CBL2 Connector Pin Name Signal Name FPGA Pin 5 MGTTXPO 134 13 SMA N MGTTXNO 134 14 SMA MGTRXPO 134 14 SMA MGTRXNO 134 5 5 MGTRXNI 134 17 SMA MGTRXPI 134 16 5 MGTTXNI 134 18 SMA MGTTXPI 134 17 SMA MGTREFCLKN 134 16 SMA MGT P MGTREFCLKP 134 AYIS Table 16 SMA Connectors Pin Assignment 2 11 Configuration Options The on board FPGA can be configured direct or via Platform Flash 2 11 1 Direct FPGA Configuration 1 Asillustrated in Figure 12 connect the 14 pin header of the Xilinx USB programming cable to the J1 connector The USB header should be connected to USB port of a PC on the other side The Xilinx ISE 10 1 or higher should already been installed on the PC 2 Apply 5V 5 Amp supply either to J12 standard wall power supply OR J18 Power Connector Note Applying higher supply voltages will damage the board 3 Turn SW1 switch ON The voltage LEDs located at the bottom of the board should ill
63. ed to any target circuitry 14 INIT BIDIR Do not connect 1 3 5 7 9 11 13 GND GND Digital Ground Before starting the software sequence to program the BPI PROM there are few key hardware checks to perform XAPP973 v1 2 February 6 2008 Proper Xilinx cable connection The Xilinx cable must be properly connected to the computer and to the JTAG bus of the FPGA connected to the target PROM see Figure 2 for hardware connections from the Xilinx cable to the JTAG bus of the FPGA Cable power If using the Xilinx Parallel Cable IV or Xilinx MultiPRO cable then power must be applied to the cable Target system Power Power must also be supplied to the target system containing the Virtex 5 FPGA and PROM Isolate BPI bus signals from other devices other than the FPGA during the programming process The target FPGA must be allowed to program the PROM without contention from other devices which might access the memory device in other words any other potential BPI PROM master device on the address or data bus or control signals should be isolated www xilinx com 52 Software Flows for BPI File Preparation and Programming XILINX Software Flows Preparing a PROM File for BPI File This section details the software flow for creating PROM files for a BPI PROM for BPI UP Preparation and configuration mode The Xilinx ISE software tools PROMGen or iMPACT generate PROM files Prog rammin
64. eneration project for quick regeneration of the BPI PROM file whenever the FPGA bitstream design is revised To regenerate a BPI PROM file re open the saved iMPACT project and invoke the Generate File operation iMPACT generates a revised BPI PROM file from the new version of the FPGA bitstream file assuming the revised bitstream file is located in the same location as the original bitstream file If a project is not loaded when using the iMPACT GUI interface a user is guided through the wizard steps each time to create a new BPI formatted PROM file The designer is prompted to name the project and select the option Prepare a PROM File following the steps 1 8 outlined above to generate a new BPI File XAPP973 v1 2 February 6 2008 www xilinx com 58 Software Flows for File Preparation and Programming iMPACT C Xilinx91i default ipf PROM File Formatter 1 File Edit view aa Boundary Sc SlaveSerial 3 Cor Direct SPI Cc E System CE File mb Generate File Window Help Le BPI Parallel Daisy Chain 5 50 bitfile perations BATCH CMD file C Virtex5 bitfile bit used size PROM File Formatter setCurrentDeviceChain index 0 12556672 BATCH CMD setCurrentDeviceChain index 0 Add one device Next Start Address 17f46a lt Output Ero
65. ering zero delay buffering frequency synthesis and phase matched clock division 36 Kbit block RAM FIFOs True dual port RAM blocks Enhanced optional programmable FIFO logic Programmable 4 www HiTechGlobal com Virtex 5 LX330T FX200T SX240T HTG V5 PCIE XXX User Manual True dual port widths up to x36 Simple dual port widths up to x72 Built in optional error correction circuitry Optionally program each block as two independent 18 Kbit blocks High performance parallel SelectIO technology 1 2 to 3 3V I O Operation Source synchronous interfacing using ChipSync technology Digitally controlled impedance DCI active termination Flexible fine grained I O banking High speed memory interface support Advanced DSP48E slices 25 x 18 two s complement multiplication Optional adder subtracter and accumulator Optional pipelining Optional bitwise logical functionality Dedicated cascade connections Flexible configuration options SPI and Parallel FLASH interface Multi bitstream support with dedicated fallback reconfiguration logic Auto bus width detection capability System Monitoring capability on all devices On chip Off chip thermal monitoring On chip Off chip power supply monitoring JTAG access to all monitored quantities Integrated Endpoint blocks for PCI Express LXT SXT and FXT Platforms Compliant with t
66. es 192 1 056 384 PowerPC 440 Processor Blocks 2 PCI Express Endpoint Blocks 1 1 4 10 100 1000 Ethernet MAC Blocks 4 4 8 RocketIO GTP Low Power Transceivers 24 24 GTX High Power Transceivers 24 Commercial 1 2 1 2 1 2 Industrial 1 1 1 Configuration Memory Mbits 82 7 79 6 70 9 1 4 RocketIO Multi Gigabit Transceivers GTP GTX GTP Transceivers LXT SXT only Full duplex serial transceiver capable of 100 Mb s to 3 75 Gb s baud rates 8B 10B user defined FPGA logic or no encoding options Channel bonding support CRC generation and checking Programmable pre emphasis or pre equalization for the transmitter Programmable termination and voltage swing Programmable equalization for the receiver Receiver signal detect and loss of signal indicator User dynamic reconfiguration using secondary configuration bus Out of Band OOB support for Serial ATA SATA Electrical idle beaconing receiver detection and PCI Express and SATA spread spectrum clocking support Less than 100 mW typical power consumption Built in PRBS Generators and Checkers RocketIO GTX Transceivers FXT Only Full duplex serial transceiver capable of 150 Mb s to 6 5 Gb s baud rates 8B 10B encoding and programmable gearbox to support 64B 66B and 64B 67B encoding user defined FPGA logic or no encoding options Channel bonding support CRC generation and checking Programm
67. ex 5 FPGA The Virtex 5 family provides the newest most powerful features in the FPGA market Using the second generation ASMBL Advanced Silicon Modular Block column based architecture the Virtex 5 family contains four distinct platforms sub families the most choice offered by any FPGA family Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs In addition to the most advanced high performance logic fabric Virtex 5 FPGAs contain many hard IP system level blocks including powerful 36 Kbit block RAM FIFOs second generation 25 x 18 DSP slices SelectIOTM technology with built in digitally controlled impedance ChipSync source synchronous interface blocks system monitor functionality enhanced clock management tiles with integrated DCM Digital Clock Managers and phase locked loop PLL clock generators and advanced configuration options Additional platform dependant features include power optimized high speed serial transceiver blocks for enhanced serial connectivity PCI Express compliant integrated Endpoint blocks tri mode Ethernet MACs Media Access Controllers and high performance PowerPC 440 microprocessor embedded blocks These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA based systems Built on a 65 nm state of the art copper process technology Virtex 5 FPGAs are a programmable alternat
68. g formatted for BPI UP mode from the FPGA bitstream Just as with Xilinx Platform Flash PROMs PROMs these BPI PROMs output data bytes LSB first as the FPGA uses an asynchronous page mode read starting from address zero when accessing the PROM in BPI UP mode Before converting a FPGA bitstream to a PROM file formatted for BPI UP mode the designer must verify that the bitstream was generated with the bitgen g StartupClk Cclk option This option ensures proper FPGA functionality by synchronizing the startup sequence to the internal FPGA clock Preparing a BPI PROM File Using the ISE PROMGen Command Line Software The ISE PROMGen software takes a Xilinx FPGA bitstream bit file as input and with the appropriate options generates a memory image file for the data array of a BPI PROM The output memory image file format is chosen through a PROMGen software command line option Typical file formats include Intel Hex mcs and Motorola Hex exo The ISE PROMGen software utility is easily executed from command line refer to Ref 6 for command line options An example PROMGen software command line to generate an mcs formatted file for 32 MB or 256 Mb PROM used BPI UP mode is promgen p mcs o BPI PROM mcs s 32768 data width 16 u 0 bitfile bit The p mes option specifies Intel Hex mcs output file format The o PROM mcs specifies output to the PROM mcs file The s 32768 specifies a PRO
69. he PCI Express Base Specification 1 1 xl x4 or x8 lane support per block Works in conjunction with transceivers Tri mode 10 100 1000 Mb s Ethernet MACs LXT SXT and FXT Platforms RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII Media Independent Interface options RocketIOTM GTP transceivers 100 Mb s to 3 75 Gb s LXT and SXT Platforms RocketIO GTX transceivers 150 Mb s to 6 5 Gb s FXT Platform only PowerPC 440 Microprocessors FXT Platform only RISC architecture 7 stage pipeline 32 Kbyte instruction and data caches included Optimized processor interface structure crossbar 65 nm copper CMOS process technology 1 0V core voltage High signal integrity flip chip packaging 5 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T 1 3 Supported Virtex 5 Devices HTG V5 PCIE XXX User Manual Part Number XCSVLX330T 5 5 240 XCSVFX200T Slices 51 840 37 440 30 720 Logic Cells 331 776 239 616 196 608 CLB Flip Flops 207 360 149 760 122 880 Maximum Distributed RAM Kbits 3 420 4 200 2 280 Block RAM FIFO w ECC 36Kbits each 324 516 456 Total Block RAM Kbits 11 664 18 576 16 416 Digital Clock Managers DCM 12 12 12 Phase Locked Loop PLL PMCD 6 6 6 Maximum Single Ended Pins 960 960 960 Maximum Differential I O Pairs 480 480 480 DSP48E Slic
70. ion of the attenuator chip and output frequency selection modes Ul LX330T GTP CLEO GTP 118 amp 126 Tiles Ref Clock GTP PCle 100 CLE Uli 165874003 O PCIe Reset Figure 8 PCI Express Jitter Attenuator Diagram 33 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual Picture 9 PCIe Jitter Attenuator Control INPUT OUTPUT QA0 nQAO0 QA1 nQA1 DIV2 DIV5 DIV4 DIV2 DIV2 DIV5 DIV4 1 1 DIVA Table 8 PCI Express Jitter Attenuator Mode Select gt 2 8 Serial ATA SATA Picture 10 SATA Connector The HTG V5 PCIE XXX board supports two SATA I amp II ports via GTP GTX 112 tile An 5843001 21 Frequency Synthesizer used with the SATA ports As shown in Table 6 applying different input frequencies along with different selections of and N Divider values generates different output frequencies that can used for SATA and other applications The default crystal values are 25 MHz amp 10 MHz selected by the J2 jumper Additional GTP GTX reference clock frequencies can be generated by inserting different oscillators into the X6 socket and positioning the SW2 switch SATA Super Clock The clock circuit diagram for the SATA connectors is illustrated in figure 9 34 www HiTechGlobal com Virtex 5 LX3
71. irect ISP is preferred to easily accommodate design iterations The iMPACT 9 2i software included in the Xilinx ISE development software tools provides indirect programming for select PROMs Because BPI PROMs do not have a JTAG interface extra logic is required to serve as a bridge between the iMPACT programmer using a cable to drive the JTAG bus interface and the BPI PROM connected to the FPGA s BPI bus interface This extra logic must be downloaded into the FPGA by iMPACT before indirect programming is possible This application note is divided into three main sections The first section discusses the hardware connections required for the indirect in system programming of PROMS for prototype designs The second section shows the Xilinx software tool flows for generating a PROM file formatted for 16 bit BPI UP mode and then for programming the select PROMs 2007 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc PowerPC is a trademark of IBM Corp and is used under license All other trademarks are the property of their respective owners XAPP973 v1 2 February 6 2008 www xilinx com 46 Introduction 5 XILINX The third section provides a basic configuration flow overview for the FPGA after the BPI PROM is programmed and describes expectations when using this indirect setup iMPACT Indirect In System Programming with
72. ive to custom ASIC technology Most advanced system designs require the programmable strength of FPGAs Virtex 5 FPGAs offer the best solution for addressing the needs of high performance logic designers high performance DSP designers and high performance embedded systems designers with unprecedented logic DSP hard soft microprocessor and connectivity capabilities The Virtex 5 LXT SXT and FXT platforms include advanced high speed serial connectivity and link transaction layer capability 1 2 Summary of Features Four platforms LX LXT SXT and FXT Virtex 5 LX High performance general logic applications Virtex 5 LXT High performance logic with advanced serial connectivity Virtex 5 SXT High performance signal processing applications with advanced serial connectivity Virtex 5 FXT High performance embedded systems with advanced serial connectivity Cross platform compatibility LXT SXT and FXT devices are footprint compatible in the same package using adjustable voltage regulators Most advanced high performance optimal utilization FPGA fabric Real 6 input look up table LUT technology Dual 5 LUT option Improved reduced hop routing 64 bit distributed RAM option SRL32 Dual SRL16 option Powerful clock management tile CMT clocking Digital Clock Manager DCM blocks for zero delay buffering frequency synthesis and clock phase shifting PLL blocks for input jitter filt
73. l ATA legacy software compatibility 48 bit address feature set supported Master only emulation supports 1 device 8b 10b coding and decoding CONT and data scramblers to reduce EMI CRC generation and checking Auto inserted HOLD primitives Power management support partial and slumber Optional native mode programming model Many configuration options Serial ATA SATA IP Core Architecture The Serial ATA SATA Link and Transport Layer Core implements a serial ATA host interface which connects to a SATA PHY a 10bit interface and provides a Wishbone slave interface for register and DMA access It consists of the link layer module with 10bit data paths to the physical layer and a transport layer module which connects to the system via a Wishbone slave interface SAPIS PHY Interface This interface connects to any SAPIS compliant serial ATA PHY Power management and speed negotiation signals are included The PHY interface is synchronous to the Phy clock domain which may have a different clock frequency than the system clock domain Synchronization is done by the Serial ATA Link and Transport Layer Core Wishbone Slave Interface The slave interface is used to access all core internal registers as well as the data FIFO Software or an external DMA unit can write transmit data into the data FIFO or can read from the FIFO This interface can be easily adapted to AMBA AHB bus interface with our WISHBONE AMBA bridge DMA Handshake
74. le Reference Clock 8 SMA connected to two GTP GTX channels x2 Samtec with 68 pairs of LVDS 2 5V or 136 Single ended 3 3V for any customized or off the shelf modules such as FPGA expansion DVI USB etc 1 200 pin DDR 2 SO DIMM up to 2 GB xl 256 Mb Intel Flash for configuration or data storage The HTG V5 PCIE XXX can be used either as Stand Alone or PCI Express based card This provides additional functionality and cost saving so designers can use the same board for multiple designs projects and applications JP11 and JP43 can be used to switch between PCI Express and Stand alone mode PCI Express Mode gt J11 Removed turns ON U18 regulator amp 143 Placed when board is plugged into PCI Express slot Stand alone Mode gt J11 Placed turns OFF the U18 regulator amp J43 Removed when the board is in stand alone mode and powered by an external 5 V supply Notes The U18 is used to convert the 12V supply from PC motherboard to 5V The output of this regulator is fed to U14 U15 U16 and U17 for conversion to 1 0V 2 5V 1 8V and 3 3V The feature rich Virtex 5 LXT SXT FXT and availability of more than 100 different IP Cores through HiTech Global and variety of different connectors and interfaces make the HTG V5 PCIE XXX an extremely versatile platform for serial interface embedded system and storage designs complete list of IP Cores supported by Hi
75. licking Finish the JTAG chain appears in the iMPACT GUI Figure 13 For this demonstration a single Virtex 5 FPGA exists in the JTAG chain This Virtex 5 FPGA device is connected to the PROM iMPACT Boundary Scan gt File Edit View Operations Output Debug Window Help 1 230 9 Sm Right click device to select operations 38 3 Configuration Fa Direct SPI Configuration E SystemACE E PROM File Formatter 5 50 file Operations Boundary Scan PROGRESS START Starting Operation Identifying chain contents 1 Manufacturer s ID INFO iMPACT 1777 Reading C Xilinx9li virtex5 data xc5vlx50 bsd INFO iMPACT 501 1 1 xc5vl1x50 Version 0 Added Device xc5vlx50 successfully Transcript gt utput Error Warning _ Configuration Platform Cable USB 6 MHz usb hs X973 13 020608 Figure 13 iMPACT JTAG Chain Initialization of a Single Virtex 5 FPGA Step 3 Assign the FPGA Configuration File Select the FPGA bitstream and ensure that the Enable Programming of BPI Flash Device Attached to this FPGA option is checked Figure 14 Checking this option allows for the indirect programming of the attached BPI PROM through the FPGA g Assign New Configuration File Lookin Sq C Virtex5 bitfile bit BPILPROM mes
76. m a BPI PROM in system with iMPACT and a Xilinx cable include a ribbon cable header on the board Ensure the signals are connected properly as shown in Figure 2 and described in Table 5 Table 5 Xilinx Cables Ribbon Cable Connection Type and Description JTAG Configuration Mode Signal Type Header Usage Description for JTAG Reference Target Reference Voltage This pin should be connected to a voltage bus on the target system that serves the JTAG Slave 2 V Serial or BPI interface The target reference voltage must be REF regulated and must not have a current limiting resistor in series with the VREF pin see Figure 2 for the appropriate VREF needed in this setup Test Mode Select This is the JTAG mode signal that establishes appropriate TAP state transitions for target ISP devices It should d be connected to the TMS pin on all target ISP devices that share the same data stream Test Clock This is the clock signal for JTAG operations and should 6 TCK CCLK Out connected to the pin on all target ISP devices that share the same data stream Test Data Out This is the serial data stream received from the 8 TDO DONE In TDO pin on the last device in a JTAG chain Test Data In This is the serial data stream transmitted to the TDI 10 pin on the first device a JTAG chain 12 N C Reserved This is reserved for Xilinx diagnostics and should not be connect
77. n 2 11 1 Stand Alone Mode 2 11 2 PCI Express Mode 2 11 3 Via PCI Express Bus Chapter 3 PCI Express Software amp Drivers 3 1 Introduction 3 2 Overview 3 3 Architecture and Operation 3 4 Build Instructions Chapter 4 Intellectual Property IP Cores 4 1 PCI Express 4 2 Serial 4 3 DDR 2 Memory Controller 3 www HiTechGlobal com Virtex 5 LX330T FX200T SX240T HTG V5 PCIE XXX User Manual Chapter 1 Introduction to Virtex 5 1 1 Virt
78. n the other Master modes The FPGA drives the address lines to access the attached BPI PROM For configuration only asynchronous read mode is used where the FPGA drives the address bus and the PROM drives back the bitstream data cu AF LL INIT_B 1 FCS_B 11 7 E ADDR 25 0 0115 0 DONE x973 21 092807 Figure 21 Virtex 5 FPGA Basic Configuration Flow At power race condition between the 5 FPGA and PROM can exist The FPGA sends the address to the BPI PROM to acquire the bitstream after the FPGA has completed its power on reset sequence On the other hand the BPI PROM is not ready to receive a address until the PROM power on reset sequence has completed Under specific conditions when the Vcc power supply to the PROM powers up after the FPGA and VccAux power supplies the FPGA s address counter can pass the critical start of the bitstream within the PROM before the PROM becomes responsive The system must be designed such that the BPI PROM is ready to receive the address before the Virtex 5 FPGA sends the address XAPP973 v1 2 February 6 2008 www xilinx com 67 Expectations Expectations 2 XILINX iMPACT Operations and Programming Times Because PROMs can combine user data and configuration storage iMPACT only perform operations on the area bounded by the target PROM File This re
79. nd loaded by iMPACT when an operation is performed on the BPI PROM The core processes and usage are preformed in the background and are transparent to the user However the DONE status signal is activated whenever the core programming design is loaded for an PROM operation Caution This application note demonstrates a single FPGA to BPI PROM use case For daisy chained FPGA applications the DONE signals should not be tied together thereby preventing the BPI PROM programming bitstream from being loaded into the FPGA Refer to the Ref 3 for more information on daisy chained FPGA applications Ifthe user application utilizes the DONE signal status as a flag the signal is released both when the core design is loaded and then again when the application design is configured into the FPGA from the programmed BPI PROM ThelO L9P CC GC 4 should be treated as reserved because iMPACT s indirect programming core drives this signal Low Pull Ups and Pull Downs The designer should ensure that the board s device control signals such as reset or enable are tied appropriately on the board and do not rely on the FPGA s internal I O pull up or pull down settings As well as being good design practice it is also important because the JTAG to BPI programming core settings can differ from the board s target application I O requirements When using the indirect programming method Virtex 5 FPGAs are configured with a JTAG to BPI p
80. non volatile source FPGA configuration is traditionally accomplished with a JTAG interface a microprocessor or the Xilinx PROMs Platform Flash 5 In systems where the easiest solution is preferred Master Serial mode with a Xilinx Platform Flash PROM is still the most popular configuration mode because it has A direct JTAG interface for programming e The smallest interface pin requirement for configuration e Flexible I O voltage support Moreover this solution is available for any Virtex 5 FPGA device refer to Ref 1 for more information In addition to the traditional methods a direct configuration interface to third party PROMs is included on Virtex 5 FPGAs to address changing system requirements Systems with a BPI PROM already on board for random access non volatile application data storage can benefit from consolidating the configuration storage into the same memory device Similar to the traditional configuration memories PROMs must be loaded with the configuration data PROMs have a single interface for programming and three primary methods to deliver the data to this interface e Third party programmers off board programming e programming ISP with an embedded processor e Indirect ISP using or custom solution Production programming is often accomplished off board with a third party programmer or in system with a JTAG tool vendor During the prototyping phase ind
81. oad the fallback bitstream when a configuration error is detected Notes 1 2 3 4 If unused by default this pin is 3 stated with a weak internal pull down resistor after configuration Recommend external pull up for indirect setup iMPACT drives all FPGA address pins ADDR 25 0 regardless of the PROM size Actual PROM address connections depend on size of the PROM iMPACT supports a maximum Intel StrataFlash P30 size of 256 Mb maximum address pins A 24 1 Xilinx Cable Connections Xilinx cables are used with iMPACT to indirectly program the select PROMs through the traditional 1149 1 JTAG interface available on the Virtex 5 FPGAs Table 4 lists the Xilinx cables which can be used for indirect PROM programming using iMPACT Table 4 Xilinx Cables Supporting Indirect PROM Programming Xilinx Cables Interface Frequency Platform Cable USB USB Up to 24 MHz Parallel Cable IV Parallel Up to 5 MHz MultiPRO Desktop Tool Parallel Up to 5 MHz Notes 1 Refer to the specific Xilinx Cable data sheet for additional information XAPP973 v1 2 February 6 2008 www xilinx com 51 Introduction 5 XILINX The Xilinx cables listed in Table 4 page 6 use a standard 14 pin ribbon cable as shown in Figure 2 page 4 The ribbon cable is advantageous over flying leads due to the ease of connectivity and improved signal quality for programming at higher frequencies To progra
82. oduction XILINX After the BPI PROM family is selected consider the BPI PROM density All of the Virtex 5 FPGAs can be configured from a single BPI PROM typical configuration density requirements for Virtex 5 FPGAs are provided in Table 2 A larger BPI PROM can be used for daisy chained applications storing multiple FPGA configuration bitstreams or for applications storing additional user data such as code for embedded MicroBlaze core or embedded PowerPC processors Table 2 Typical Virtex 5 FPGA Configuration Bit Requirements Xilinx FPGA Device gt Sma Required XC5VLX30 8 374 016 8 Mb XC5VLX50 12 556 672 16 Mb XC5VLX85 21 845 632 32 Mb XC5VLX110 29 124 608 32 Mb XC5VLX155 1 41 048 064 64 Mb XC5VLX220 53 139 456 64 Mb XC5VLX330 79 704 832 128 Mb XC5VLX20T 6 251 200 8 Mb XC5VLX30T 9 371 136 16 Mb XC5VLX50T 14 052 352 16 Mb XC5VLX85T 23 341 312 32 Mb XC5VLX110T 31 118 848 32 Mb XC5VLX155T 43 042 304 64 Mb XC5VLX220T 55 133 696 64 Mb XC5VLX330T 82 696 192 128 Mb XC5VSX35T 13 349 120 16 Mb XC5VSX50T 20 019 328 32 Mb XC5VSX95T 35 716 096 64 Mb Notes 1 Indirect BPI programming support for the newest Virtex 5 FPGA family members is included in iMPACT 9 2 04i The other BPI PROM features package and the data bus width also need to be considered when using iMPACT This application note highlights a setup and software flow
83. pens a file browser to select the FPGA bitstream bit file to add to the PROM memory image Figure 9 Select the FPGA bitstream file to be written to the PROM Click Open in the browser to add the selected FPGA bitstream to the PROM memory image Click NO when asked if another design file is to be added Next click OK to complete the automated iMPACT process for preparing PROM file to be generated Proceed to step 8 to generate the PROM file Add Device Look in 5 Virtex5 My Recent Documents My Network be Cancel Places Files of type FPGA Bit Files bit X973 09 020608 Figure 9 Add Device File Browser Step 8 iMPACT Generate File Operation The eight and final step in the process is to generate the PROM file Under the iMPACT Operations menu invoke the Generate File menu item Figure 10 page 14 Once invoked the Generate File menu item causes iMPACT to generate the specified PROM file iMPACT reports a PROM File Generation Succeeded message after successful generation of the BPI PROM file After the Generate File operation has completed the generated PROM mcs file is available in the specified location The PROM mcs file can be used in any of the supported programming solutions to program the BPI PROM with the specified FPGA bitstream contained within the PROM file Save the iMPACT BPI PROM g
84. r Warning Generate System ACE or PFF file Using the ISE iMPACT Software to Indirectly Program PROMs gt PROM File Generation Target Parallel PROM 12 556 672 Bits used File PROM in Location c virtex5 X973 10 020608 Figure 10 Generate File Menu 5 XILINX In prototyping applications the ISE iMPACT 9 2i or later software can be used to in system program select PROMs with a memory image from a given BPI PROM file see Preparing a BPI PROM File Using the ISE iMPACT Graphical Software page 8 for instructions on the generation of a PROM file The following section demonstrates the iMPACT software process for in system programming a Intel 28F256P30 256 Mb or 32 MB BPI PROM The demonstrated process takes the BPI_PROM mcs PROM file generated in the Software Flows for BPI File Preparation and Programming page 8 as input erases the PROM programs the PROM file contents into the BPI PROM and verifies the PROM contents against the given BPI PROM file contents XAPP973 v1 2 February 6 2008 www xilinx com 59 Software Flows for BPI File Preparation and Programming XILINX Step 1 Create a New Project for Indirect In System Programming After launching the iMPACT software the iMPACT Project dialog box is displayed Figure 11 Choose the create a new project ipf option Optionally specify a project location using the Brow
85. rogramming core with all unused I Os set to PULLUP This setting activates the internal pull up on all I Os while the core is loaded If dictated by system requirements the user can pull down any I O using a 1 1 resistor In addition before the FPGA is configured Virtex 5 FPGA I Os can be controlled by the HSWAPEN pin When this pin is held Low internal pull ups on all the I Os are active Designers must ensure that the correct HSWAPEN settings are used if any of the FPGA pins are connected to a control signal of any other device Caution Software releases prior to 10 1 01 have the JTAG to BPI programming core internal I O set to PULLDOWN XAPP973 v1 2 February 6 2008 www xilinx com 68 Conclusion 5 XILINX Conclusion The ability to program BPI PROMS through the JTAG interface of a Virtex 5 FPGA with iMPACT can greatly increase the value of using Xilinx FPGAs in a system References Device 1 08123 Platform Flash In System Programmable Configuration PROMs Data Sheet 2 DS202 Virtex 5 FPGA Family Data Sheet 3 00191 Virtex 5 FPGA Configuration User Guide 4 Intel StrataFlash P30 Data Sheet refer to Intel website for download Software The Xilinx PROMGen and iMPACT software are available with the main Xilinx ISE Foundation software or with the downloadable Xilinx ISE WebPACK software packages 5 ISE Foundation software http www xilinx com ise logic design prod foundation htm 6 The Xilinx ISE soft
86. rsion Notes 09 10 2007 1 0 10 08 2007 1 1 Clock diagrams added 12 12 2007 1 2 High speed connectors updated 2 7 2008 1 3 Flash Configuration added 6 1 2008 1 4 SX240T FX200T info added 2 www HiTechGlobal com Virtex 5 LX330T FX200T SX240T HTG V5 PCIE XXX User Manual Table Of Contents Chapter 1 Introduction to Viretx 5 LXTFXT SXT 1 1 Virtex 5 FPGA General Description 1 2 Summary of Features 1 3 Supported Virtex 5 Devices 1 4 RocketIO O Multi Gigabit Transceivers GTP GTX 1 5 End Point Block for PCI Express 1 6 PowerPC 440 RISC Cores FXT Only 1 7 Tri Mode Ethernet MAC 1 8 Input Output Blocks SelectIOs 1 9 Additional Virtex 5 Resources Chapter 2 HTG V5 PCIE XXX Platform 2 1 Introduction
87. se button Then click OK button to continue to step 2 in the process iMPACT Project want to C Load most recent project file when iMPACT starts create new project ipf default ipf X973 11 020608 Figure 11 Create a New Project Step 2 Configure Devices Using the JTAG to BPI Method The second step of the process begins with the iMPACT project wizard The first dialog box of the wizard displays the available kinds of projects that can be created Figure 12 Select the Configure devices using Boundary Scan JTAG option Then select the Automatically connect to a cable and identify Boundary Scan chain item from the associated drop down list box Click Finish to complete the new project setup process At the completion of this process iMPACT is set into a mode for in system programming using a direct cable connection to the FPGA JTAG bus iMPACT Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain w Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Configure devices using Slave Serial mode Cancel X973_12_020608 Figure 12 Configure Devices Using Boundary Scan XAPP973 v1 2 February 6 2008 www xilinx com 60 Software Flows for BPI File Preparation and Programming XILINX After c
88. step Generate File creates the BPI PROM file The following section demonstrates the iMPACT software process for generating a PROM file in the MCS file format for a 32 MB BPI PROM in BPI UP Mode The demonstrated process takes the bitfile bit FPGA bitstream file as input and generates a PROM file named PROM mcs XAPP973 v1 2 February 6 2008 www xilinx com 53 Software Flows for BPI File Preparation and Programming XILINX Step 1 Create a New Project for PROM File Generation After launching the iMPACT software the iMPACT project dialog box is displayed Figure 3 Choose the create a new project ipf option Optionally specify a project location using the Browse button Then click OK to continue to step 2 in the process iMPACT Project want to C Load most recent project file when iMPACT starts 5 create a new project default ipf Cancel X973_03_020608 Figure 3 Create a New Project for PROM File Generation Step 2 Choose to Prepare a PROM File The first dialog box of the wizard displays the available actions that can be performed Figure 4 Check Prepare a PROM File and click Next to proceed to step 3 of the process 8 iMPACT Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File
89. striction is to prevent other user data from being modified unintentionally The erase operation for example does not erase the entire device contents but rather erases only the user area required to store the BPI PROM file In addition program verify and blankcheck all target only the area addressed by the BPI PROM file With iMPACT 9 2i and the Xilinx Platform Cable USB at the default 6 Mhz the user can expect a programming time of approximately 1 5 minutes per 8 Mbit of memory and a verify time of approximately 30 minutes per 8 Mbit of memory The user will see an enhanced verify time of approximately 30 seconds per 8 Mbit of memory in iMPACT 9 2 04i or later These times are only guidelines because PROM operations utilize device polling therefore the operation times vary slightly from device to device In addition the cable and cable TCK speed selection can be changed in iMPACT increasing or decreasing this time slightly Affect of Indirect Programming on the Rest of the System When using the JTAG interface to program the PROM through a Virtex 5 FPGA the user must understand the behavior of the FPGA during this process and how it can affect other devices in the system To access the BPI PROM through the JTAG interface a Xilinx proprietary JTAG to BPI bitstream must be loaded into the FPGA Loading the JTAG to BPI programming core in the FPGA replaces any already loaded design logic The core is automatically selected a
90. t FPGA Signal Name Signal Name FPGA Pin IO 25 SWO SWS Switch AG31 IO LON 25 SWI SWS5 Switch AF31 IO 25 SW2 SW5 Switch AF32 IO LIN 25 SW3 SWS5 Switch AG33 IO L2P 25 SWA SWS5 Switch AH33 IO L2N 25 5 5 SWS5 Switch AG32 IO L3P 25 SW6 SWS5 Switch AH3I IO L3N 25 SW7 SWS5 Switch AJ31 IO 25 LEDO DS14 AV35 IO LAN VREF 25 LEDI DS15 AV36 IO L5P 25 LED2 DS16 AU36 IO L5N 25 LED3 DS17 AT35 IO L6P 25 LED4 DS18 AU34 IO L6N 25 LEDS DS19 AT34 IO L7P 25 LED6 DS20 AR35 IO L7N 25 LED7 DS21 AR34 IO L8P CC 25 USR RESET AU32 IO L8N CC 25 PCIE PERST AU33 IO L9P CC 25 PCIEWAKE AV33 Table 5 LED amp Switches Connections Summary 2 6 DDR 2 SO DIMM Picture 4 DDR2 SODIMM The HTG V5 PCIE XXX board is populated with a 200 pin SO DIMM connector which supports installation of Dual Rank DDR2 SDRAM SO DIMMs up to 2 GB DDR2 533 and or DDR2 400 DDR 2 Memory Controller IP Core is available through HiTech Global Additional information is available at http www hitechglobal com IPCores DDR2Controller htm Connector Pin Numbers Pin Names Signal Names FPGA Pin Numbers and used Banks are summarized in Table 6 25 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual
91. tch matrix to access the routing resources Per bit deskew circuitry allows for programmable signal delay internal to the FPGA Per bit deskew flexibly provides fine grained increments of delay to carefully produce a range of signal delays This is especially useful for synchronizing signal edges in source synchronous interfaces General purpose I Os in select locations eight per bank are designed to be regional clock capable I O by adding special hardware connections for I O in the same locality These regional clock inputs are distributed within a limited region to minimize clock skew between IOBs Regional I O clocking supplements the global clocking resources 1 9 Additional Virtex 5 information and documents are available at the following sites Virtex 5 User Guide http direct xilinx com bvdocs userguides ug190 pdf The Virtex 5 User Guide includes chapters on Clocking Resources Clock Management Technology Phase Locked Loops Block RAM and FIFO memory Configurable Logic Blocks CLBs SelectIO resources and SelectIOTM logic resources Virtex 5 XtremeDSP User Guide http direct xilinx com bvdocs userguides ug193 pdf This document describes the Virtex 5 DSP48E slice Virtex 5 Configuration User Guide http direct xilinx com bvdocs userguides ug191 pdf This all encompassing configuration guide includes detailed information on the Virtex 5 configuration interfaces 8 www HiTechGlobal com Virtex 5 LX330T SX2
92. ugh HiTech Global Additional information is available at http www hitechglobal com ipcores sata htm Input Reference Divider N Divider VCO Output Applications Clock Value MHz Frequency MHz 25 24 4 600 150 SATA 25 24 8 600 75 SATA 26 5625 24 6 637 5 106 25 Fibre Channel 1 4 Gig Fibre 26 5625 24 3 637 5 212 5 Channel 10 Gig Fibre 26 5625 24 4 637 5 159 375 Channel Table 11 ICS Frequency Synthesizer Common Configuration 36 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 2 9 10 100 1000 Tri Speed Ethernet PHY ETH ETH 8 6765 nc 1 MSS Picture 11 Gigabit Ethernet RJ45 Connectors The HTG V5 PCIE XXX board is populated with two Marvell Alaska PHY devices 88E1111 operating at 10 100 1000 Mb s The Marvell Alaska PHY device enables copper 1000BASE T Gigabit Interface Converter GBIC modules as well as Small Form Factor Pluggable SFP modules The single port Alaska family offers additional support of 1000BASE X through an integrated 1 25 GHz Serializer Deserializer SERDES enabling the use of the device in fiber optic Gigabit Ethernet applications IEEE 802 3z The Marvell Alaska devices include advanced features such as Virtual Cable Tester VCT cable diagnostic Media Detect feature Low power consumption Small footprint 2 3 Pair Downshift Bank FPGA Pin Description FPGA Pin Number PHY A Pins IO LO
93. uide describes the System Monitor functionality available in all Virtex 5 devices Virtex 5 PCB Designer s Guide http direct xilinx com bvdocs userguides ug203 pdf This guide provides information on PCB design for Virtex 5 devices with a focus on strategies for making design decisions at the PCB and interface level 9 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 1 20 20 20 24 DENN 20 20 20 2 EXE EX NUI 1 2 2 alaj 20 20 2 Figure 1 Virtex 5 LX330T 1738 SelectI O Package Diagram 10 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 1 5 5 5 67 5 660 55 LIOOOUOOOQCIOOOOQCIOC 37 38 39 40 41 42 09949099490092900 5 ooo 8555083997 dn 28 im 8 ON 8583055 96505 208 39505 5825695 BONO 200942 ONDO 3598399889 Sees 6863660 2 E S uM L nos 8509 60 S 0520 D ur 2253 OTE ORC SOE 2 c 2835 250000 5 odo Mm Du AG X E ac 9 6686166 2600 59225998 25559450 penu 20959089 S OQ 0186601 5999339385538 E 271618 2050 QD OCIO
94. uminate after applying the power 42 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 4 5 Picture 12 Configuration in Stand Alone Mode Launch the ISE 10 1 iMPACT tool Start All Programs Xilinx ISE Accessories iMPACT Cancel the following window iMPACT Project This leads to verification of on board Xilinx components Oprane Output Debo Winder x o OX 2 Scan 335 Conhigusbon SP1 Coran 8 Load most recent project when PROM Fie Foenatter new ipi fhowse 43 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual 6 Double Click on the Boundary Scan the first item on the list and Single Click on the Initialize Chain icon the 7 icon from the left on the tool bar This verifies correct connection between the board and PC by identifying the on board Xilinx components in the chain Platform Flash and FPGA impact Boundary Scan File Edit View Operations Options Output Debug Window Help Bl 6 82 2 m Scan m SlaveSerial 99SeleciMAP Desktop Configuration Sa Direct SPI Configuration
95. warded to the Target module for termination on the Target Write Interface or Register Interface o Received read requests are forwarded to the Target module for termination on the Target Read Interface or Register Interface o Received completions read data resulting from master read requests are forwarded to the Completion Monitor module for termination at the appropriate DMA DWORD Master requestor TX Arbiter Arbitrates the base PCI Express core s transmit interface o Transmitted write requests originate from Card to System DMA Engines DWORD Master o Transmitted read requests originate from the Completion Monitor o Transmitted completions read data status from target reads originate from the Target module Target 75 www HiTechGlobal com Virtex 5 LX330T SX240T FX200T HTG V5 PCIE XXX User Manual o Generates the Target Write Interface for consuming received write requests o Generates the Target Read Interface for satisfying received read request o Generates the Register Interface for satisfying received write and read requests targeting the Base Address Register assigned to the PCI Express Back End and user registers o Supports 32 64 Memory Base Address Registers Completion Monitor Arbitrates among read requestors for PCI Express read request transmit resources o Manages limited PCI Express base core received completion buffer space o Re associates received completions with the original request o Routes completion d
96. ware manuals are available at http Avww xilinx com support software_manuals htm Hardware 7 Information regarding the Xilinx cables are found on the Xilinx Configuration Solutions website http www xilinx com products design_resources config_sol See the ISE iMPACT 9 2i or later software manuals for supported Xilinx cables Revision The following table shows the revision history for this document History Date Version Revision 05 22 07 1 0 Initial Xilinx release 07 06 07 1 0 1 Corrected value of pull up resistor on DONE pin in Figure 2 page 4 10 02 07 1 1 e Updated document template e Updated document for ISE Impact 9 2i support 11 21 07 1 1 1 Updated URLs 02 06 08 1 2 e Added support for XC5VLX155 XC5VLX20T and XC5VLX155T Updated Figure 2 page 4 to add the pin 19 GC 4 and associated note Updated Pull Ups and Pull Downs page 23 to clarify proper design techniques Notice of Xilinx is disclosing this Application Note to you AS IS with no warranty of any kind This Application Note Disclaimer is one possible implementation of this feature application or standard and is subject to change without further notice from Xilinx You are responsible for obtaining any rights you may require in connection with your use or implementation of this Application Note XILINX MAKES NO REPRESENTATIONS OR WARRANTIES WHETHER EXPRESS OR IMPLIED STATUTORY OR OTHERWISE

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