DE0-CV User Manual 1 www.terasic.com May 4, 2015
Contents
1. No Filename Description 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name gpf Quartus II Project File 3 Project name gt qsf Quartus II Setting File 4 Project name gt sdc Synopsis Design Constraints file for Quartus II 5 Project name htm Pin Assignment Document Users can add custom logic into the project in Quartus II and compile the project to generate the SRAM Object File sof DEO CV M asic CV User Manua www terasic com www terasic com May 4 2015 Chapter 5 Examples of Advanced Demonstrations This chapter provides examples of advanced designs implemented by RTL or Qsys on the DEO CV board These reference designs cover the features of peripherals connected to the FPGA such as PS 2 SDRAM and SD card All the associated files can be found in the directory Demonstrations of DEO CV System CD B Installation of Demonstrations To install the demonstrations on your computer Copy the folder Demonstrations to a local directory of your choice It is important to make sure the path to your local directory contains NO space Otherwise it will lead to error in Nios II Note Quartus II v14 0 or later is required for all DEO CV demonstrations to support Cyclone V FPGA device 5 1 DEO CV Factory Configuration The DEO CV board has a default configuration bit stream pre programmed which demonstrates some of the basic features onboard The setup required for2. GPIO 0 D30 GPIO_0_D31 5 GPIO 1 D30 T19 GPIO 0 D32 FEM OGPIO 0 D33 ien GPIO 1 D32 147 GPIO 0 D34 P GPIO O D35 e GPIO 1 D34 E x BOX Header 2x20M BOX Header 2x20M Figure 3 12 I O distribution of the expansion headers Table 3 7 Pin Assignment of Expansion Headers Signal Name FPGA Pin No Description GPIO 0 DO PIN N16 GPIO Connection O 0 GPIO 0 D1 PIN B16 GPIO Connection O 1 GPIO 0 D2 PIN M16 GPIO Connection 0 2 GPIO 0 D3 PIN C16 GPIO Connection O 3 GPIO 0 D4 PIN D17 GPIO Connection O 4 GPIO 0 D5 PIN K20 GPIO Connection O 5 GPIO 0 D6 PIN K21 GPIO Connection O 6 DEO CV User Manual 28 www terasic com D17 D29 GPIO 1 GPIO 1 GPIO 1 D1 D3 D5 D7 D9 A12 B12 B13 D13 G17 D11 D13 D15 J18 G11 J11 A15 L8 B15 E14 E16 D19 D21 D23 D25 D27 F45 F12 G15 G12 K16 D31 D33 D35 www terasic com May 4 2015 www terasic com GPIO 0 D7 GPIO 0 D8 GPIO 0 D9 GPIO 0 D10 GPIO 0 D11 GPIO 0 D12 GPIO 0 D13 GPIO 0 D14 GPIO 0 D15 GPIO 0 D16 GPIO 0 D17 GPIO 0 D18 GPIO 0 D19 GPIO 0 D20 GPIO 0 D21 GPIO 0 D22 GPIO 0 D23 GPIO 0 D24 GPIO 0 D25 GPIO 0 D26 GPIO 0 D27 GPIO 0 D28 GPIO 0 D29 GPIO 0 D30 GPIO 0 D31 GPIO 0 D32 GPIO 0 D33 GPIO 0 D34 GPIO 0 D35 GPIO 1 DO GPIO 1 D1 GPIO 1 D2 GPIO 1 D3 GPIO 1 D4 GPIO 1 D5 GPIO 1 D6 GPIO 1 D7 GPIO 1 D8 GPIO 1 D9 GPIO 1 D10 GPIO 1 D11 GPIO 1 D12 GPIO 1 D13 GPIO 1 D14 GPIO 1 D15 GPIO 1 D16 GPIO 1
3. X Displacement Y Displacement th Rn pm ps I Bee NI EE Middle Button Left Button Press Indicator Press Indicator Right Button Press Indicator Figure 5 6 Description of 7 segment Display and LED Indicators t asic DEO CV User Manual 52 www terasic com er May 4 2015 www terasic com Table 5 2 Description of 7 segment Display and LED Indicators Indicator Name Description LEDRO Left button press indicator LEDR1 Right button press indicator LEDR2 Middle button press indicator HEXO Low byte of X displacement HEX1 High byte of X displacement HEX2 Low byte of Y displacement HEX3 High byte of Y displacement 5 5 Micro SD Card file system read Many applications use a large external storage device such as a SD Card or CF card to store data The DEO CV board provides the hardware and software needed for Micro SD Card access In this demonstration we will show how to browse files stored in the root directory of an SD Card and how to read the file contents of a specific file The Micro SD Card is required to be formatted as FAT File System in advance Long file name is supported in this demonstration Figure 5 7 shows the hardware system block diagram of this demonstration The system requires a 50MHz clock provided by the board The PLL generates a 100MHz clock for the Nios II processor and other controllers Four PIO pins are connected to the Micro SD Card socket SD 4 bit Mode is used to access th
4. None Prefix Name GPIO 1 Header Save Setting Generate Load Setting Exit None Prefix Name Figure 4 2 The GUI of DEO CV System Builder B Enter Project Name Enter the project name in the circled area as shown in Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design entity beo cvv100 ATERA System Configuration PROGRAM ww terasic com Pro A Name DEO CV FPGA Board CIMEMNNNND V CLOCK 4 T Seqment x 6 LEDx10 V Switch x 10 MI Button x 4 v PS2 VI VGA VI SDRAM 64MB MI microSD Card GPIO 0 Header None X Prefix Name GPIO 1 Header Save Setting Generate LoadSeting Exit None X Prefix Name Figure 4 3 Enter the project name DE0 CV M 39 asic CV User Manua www terasic com www terasic com May 4 2015 B System Configuration Users are given the flexibility in the System Configuration to include their choice of components in the project as shown in Figure 4 4 Each component onboard is listed and users can enable or disable one or more components at will If a component is enabled the DEO CV System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard AU S RYAN UNIVERSITY ter PROGRAM WW Cerasic com DEO CV FPGA Board
5. V Figure 3 9 Connections between the 7 segment display HEXO and the Cyclone V FPGA Table 3 5 Pin Assignment of 7 segment Displays Signal Name FPGA Pin No Description HEX00 PIN_U21 Seven Segment Digit O 0 HEX01 PIN V21 Seven Segment Digit O 1 DEO CV User Manual 25 WWW terasic com asi May 4 2015 www terasic com HEXO2 PIN W22 Seven Segment Digit O 2 HEXO3 PIN W21 Seven Segment Digit 0131 HEX04 PIN_Y22 Seven Segment Digit O 4 HEX05 PIN Y21 Seven Segment Digit O 5 HEX06 PIN AA22 Seven Segment Digit O 6 HEX10 PIN AA20 Seven Segment Digit 1 0 HEX11 PIN AB20 Seven Segment Digit 1 1 HEX12 PIN AA19 Seven Segment Digit 1 2 HEX13 PIN AA18 Seven Segment Digit 1 3 HEX14 PIN AB18 Seven Segment Digit 1 4 HEX15 PIN AA17 Seven Segment Digit 1 5 HEX16 PIN U22 Seven Segment Digit 1 6 HEX20 PIN Y19 Seven Segment Digit 2 0 HEX21 PIN AB17 Seven Segment Digit 2111 HEX22 PIN AA10 Seven Segment Digit 2 21 HEX23 PIN Y14 Seven Segment Digit 2 31 HEX24 PIN V14 Seven Segment Digit 2 41 HEX25 PIN AB22 Seven Segment Digit 2 51 HEX26 PIN AB21 Seven Segment Digit 2 6 HEX30 PIN Y16 Seven Segment Digit 3 0 HEX31 PIN W16 Seven Segment Digit 3 1 HEX32 PIN Y17 Seven Segment Digit 3121 HEX33 PIN V16 Seven Segment Digit 3131 HEX34 PIN U17 Seven Segment Digit 3141 HEX35 PIN V18 Seven Segment Digit 3 5 HEX36 PIN V19 Seven Segment Digit 3 6 HEX40 PIN U20 Seven Segment Digit 4 0 HEX41 PIN Y20 Seven Segment Digit 4 1 HEX42 PIN V20 Seven Segm
6. 16 GPIO Connection 1 17 www terasic com May 4 2015 GPIO 1 D18 PIN J13 GPIO Connection 1 18 GPIO 1 D19 PIN L8 GPIO Connection 1 19 GPIO 1 D20 PIN A14 GPIO Connection 1 20 GPIO 1 D21 PIN B15 GPIO Connection 1 21 GPIO 1 D22 PIN C15 GPIO Connection 1 22 GPIO 1 D23 PIN E14 GPIO Connection 1 23 GPIO 1 D24 PIN E15 GPIO Connection 1 24 GPIO 1 D25 PIN E16 GPIO Connection 1 25 GPIO 1 D26 PIN F14 GPIO Connection 1 26 GPIO 1 D27 PIN F15 GPIO Connection 1 27 GPIO 1 D28 PIN F13 GPIO Connection 1 28 GPIO 1 D29 PIN F12 GPIO Connection 1 29 GPIO 1 D30 PIN G16 GPIO Connection 1 30 GPIO 1 D31 PIN G15 GPIO Connection 1 31 GPIO 1 D32 PIN G13 GPIO Connection 1 32 GPIO 1 D33 PIN G12 GPIO Connection 1 33 GPIO 1 D34 PIN J17 GPIO Connection 1 34 GPIO 1 D35 PIN K16 GPIO Connection 1 35 3 6 Using VGA The DEO CV board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone V FPGA and a 4 bit DAC using resistor network is used to produce the analog data signals red green and blue The associated schematic is given in Figure 3 13 and can support standard VGA resolution 640x480 pixels at 25 MHz VGA RO VGA R1 VGA R2 VGA R3 MA VGA GO VGA G1 ANU S RAN vos cz Cyclone y MAS an VGA BO VGA B1 VGA B2 VGA B3 MC VGA VS VGA HS Figure 3 13 Connections between the F
7. 3 12 Pin Assignment of Micro SD Card Socket Signal Name FPGA Pin No Description SD CLK PIN H11 Serial Clock SD CMD PIN B11 Command Response SD DATAO PIN K9 Serial Data 0 SD DATA1 PIN D12 Serial Data 1 SD DATA2 PIN E12 Serial Data 2 SD DATA3 PIN C11 Serial Data 3 3 9 Using SDRAM The board features 64MB of SDRAM with a single 64MB 32Mx16 SDRAM chip The chip consists of 16 bit data line control line and address line connected to the FPGA This chip uses the 3 3V LVCMOS signaling standard Connections between the FPGA and SDRAM are shown in Figure 3 19 and the pin assignment is listed in Table 3 13 DEO CV M asic CV User Manua www terasic com 34 www terasic com May 4 2015 NOS RYAN Cyclone y 32Mx16 SDRAM DRAM DQ 15 0 DRAM ADDR 12 0 DRAM BAN DRAM CLK DRAM CKE DRAM LDQM DRAM UDQM DRAM WE N DRAM CAS N DRAM RAS N DRAM CS N Figure 3 19 Connections between the FPGA and SDRAM Table 3 13 Pin Assignment of SDRAM D 15 0 A 12 0 BA 1 0 CLK CKE LDOM UDQM nWE nCAS nRAS nCS www terasic com Signal Name FPGA Pin No Description DRAM ADDRO PIN W8 SDRAM Address 0 DRAM ADDR1 PIN T8 SDRAM Address 1 DRAM ADDR2 PIN U11 SDRAM Address 2 DRAM_ADDR3 PIN_Y10 SDRAM Address 3 DRAM_ADDR4 PIN_N6 SDRAM Address 4 DRAM ADDR5 PIN AB10 SDRAM Address 5 DRAM
8. D17 DEO CV User Manual PIN K22 PIN M20 PIN M21 PIN N21 PIN R22 PIN R21 PIN T22 PIN N20 PIN N19 PIN M22 PIN P19 PIN L22 PIN P17 PIN P16 PIN M18 PIN L18 PIN L17 PIN L19 PIN K17 PIN K19 PIN P18 PIN R15 PIN R17 PIN R16 PIN T20 PIN T19 PIN T18 PIN T17 PIN T15 PIN H16 PIN A12 PIN H15 PIN B12 PIN A13 PIN B13 PIN C13 PIN D13 PIN G18 PIN G17 PIN H18 PIN J18 PIN J19 PIN G11 PIN H10 PIN J11 PIN H14 PIN A15 29 GPIO Connection O 7 GPIO Connection O 8 GPIO Connection O 9 GPIO Connection 0 10 GPIO Connection 0 11 GPIO Connection 0 12 GPIO Connection 0 13 GPIO Connection 0 14 GPIO Connection 0 15 GPIO Connection O 16 GPIO Connection 0 17 GPIO Connection O 18 GPIO Connection 0 19 GPIO Connection 0 20 GPIO Connection 0 21 GPIO Connection 0 22 GPIO Connection 0 23 GPIO Connection 0 24 GPIO Connection 0 25 GPIO Connection O 26 GPIO Connection 0 27 GPIO Connection O 28 GPIO Connection 0 29 GPIO Connection 0 30 GPIO Connection 0 31 GPIO Connection 0 32 GPIO Connection 0 33 GPIO Connection 0 34 GPIO Connection 0 35 GPIO Connection 1 0 GPIO Connection 1 1 GPIO Connection 1 2 GPIO Connection 1 3 GPIO Connection 1 4 GPIO Connection 1 5 GPIO Connection 1 6 GPIO Connection 1 7 GPIO Connection 1 8 GPIO Connection 1 9 GPIO Connection 1 10 GPIO Connection 1 11 GPIO Connection 1 12 GPIO Connection 1 13 GPIO Connection 1 14 GPIO Connection 1 15 GPIO Connection 1
9. DEO CV System Builder also provides the option to load a setting or save users current board configuration in cfg file as shown in Figure 4 6 NB S RYAN t lasic System Configuration UNIVERSITY er 5 PRO GP A Me u cerasic com Project Name DEO CV FPGA Board DEO Cv Em i si ZCLOCK M LEDx10 vi Button x 4 VI VGA MI microSD Card GPIO 0 Header VI 7 Seqment x 6 v Switch x 10 vi PS2 4 SDRAM 64MB None Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 6 Project Settings DEO CV M 41 tasie CV User Manua www terasic com www terasic com May 4 2015 B Project Generation When users press the Generate button as shown in Figure 4 7 the DEO CV System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 ATERA UNIVERSITY PROGRAM WWLerasic com DEO CV FPGA Board DEO CV v1 0 0 2 System Configuration Project Name DEO OV 4 CLOCK 4 7 Segment x 6 v LED x 10 Switch x 10 Button x 4 v PS2 VGA V SDRAM 64MB VI microSD Card GPIO 0 Header None Prefix Name GPIO 1 Header Saye Setting None Prefix Name Load Setting Figure 4 7 Generate Quartus Project Table 4 1 Files generated by the DE0 CV System Builder
10. I I I I RGB l aa 000 JT TEE 0D AD 000000000000 l DATA HSYNC Sync a Figure 3 14 VGA horizontal timing specification Table 3 8 VGA Horizontal Timing Specification VGA mode Horizontal Timing Spec Configuration Resolution HxV a pixel b pixel c pixel d pixel Pixel clock MHz clock clock clock clock cycle cycle cycle cycle VGA 60Hz 640x480 96 48 640 16 25 Table 3 9 VGA Vertical Timing Specification VGA mode Vertical Timing Spec Configuration Resolution HxV a lines b lines c lines d lines Pixel clock MHz VGA 60Hz 640x480 2 33 480 10 25 DEO CV User Manual 31 WWW terasic com Tiasic May 4 2015 www terasic com Table 3 10 Pin Assignment of VGA Signal Name FPGA Pin No Description VGA R0 PIN A9 VGA Red 0 VGA R1 PIN B10 VGA Red 1 VGA R2 PIN C9 VGA Red 2 VGA R3 PIN A5 VGA Red 3 VGA GO PIN L7 VGA Green 0 VGA G1 PIN K7 VGA Green 1 VGA G2 PIN J7 VGA Green 2 VGA G3 PIN J8 VGA Green 3 VGA B0 PIN B6 VGA Blue 0 VGA B1 PIN B7 VGA Blue 1 VGA B2 PIN A8 VGA Blue 2 VGA B3 PIN A7 VGA Blue 3 VGA HS PIN H8 VGAH SYNC VGA VS PIN G8 VGA V SYNC 3 7 PS 2 Serial Port The DEO CV board comes with a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 15 shows the connection of PS 2 circuit to the FPGA Users can use the PS 2 keyboard and mouse on the DEO CV board simultaneously by a PS 2 Y Cable as shown in
11. No Description KEYO PIN U7 Push button 0 KEY1 PIN W9 Push button 1 KEY2 PIN M7 Push button 2 KEY3 PIN_M6 Push button 3 Push button which connected RESET_N PIN P22 to DEV_CLRN Pin of FPGA Table 3 3 Pin Assignment of Slide Switches Signal Name FPGA Pin No Description SWO PIN U13 Slide Switch 0 SW1 PIN V13 Slide Switch 1 SW2 PIN T13 Slide Switch 2 SW3 PIN T12 Slide Switch 3 SWA PIN AA15 Slide Switch 4 SW5 PIN AB15 Slide Switch 5 SW6 PIN AA14 Slide Switch 6 SW7 PIN AA13 Slide Switch 7 SW8 PIN AB13 Slide Switch 8 SW9 PIN AB12 Slide Switch 9 asic DEO CV User Manual 24 n UE www terasic com Table 3 4 Pin Assignment of LEDs Signal Name FPGA Pin No Description LEDRO PIN AA2 LED 01 LEDR1 PIN AA1 LED 11 LEDR2 PIN W2 LED 2 LEDRS3 PIN Y3 LED 3 LEDR4 PIN N2 LED 4 LEDR5 PIN N1 LED 51 LEDR6 PIN U2 LED 61 LEDR7 PIN U1 LED 71 LEDR8 PIN L2 LED 81 LEDR9 PIN L1 LED 91 3 3 Using the 7 segment Displays The DEO CV board has six 7 segment displays These displays are paired to display numbers in various sizes Figure 3 9 shows the connection of seven segments common anode to pins on Cyclone V FPGA The segment can be turned on or off by applying a low logic level or high logic level from the FPGA respectively Each segment in a display is indexed from 0 to 6 with corresponding positions given in Figure 3 9 Table 3 5 shows the pin assignment of FPGA to the 7 segment displays JA DTE RYA Cyclone
12. approximately 8 seconds the SDRAM test is NG e Press KEYO again to repeat the SDRAM test Table 5 1 Status of LED Indicators Name Description LEDR1 ON if the test is PASS after releasing KEYO LEDR2 Blinks 5 4 PS 2 Mouse Demonstration A simply PS 2 controller coded in Verilog HDL is provided to demonstrate bi directional communication with a PS 2 mouse A comprehensive PS 2 controller can be developed based on it and more sophisticated functions can be implemented such as setting the sampling rate or resolution which needs to transfer two data bytes at once More information about the PS 2 protocol can be found on various websites DEO CV User Manual 49 www terasic com asi May 4 2015 www terasic com B Introduction PS 2 protocol uses two wires for bi directional communication One is the clock line and the other one is the data line The PS 2 controller always has total control over the transmission line but it is the PS 2 device which generates the clock signal during data transmission B Data Transmission from Device to the Controller After the PS 2 mouse receives an enabling signal at stream mode it will start sending out displacement data which consists of 33 bits The frame data is cut into three sections and each of them contains a start bit always zero eight data bits with LSB first one parity check bit odd check and one stop bit always one The PS 2 controller samples the data line at the falling edge o
13. disable data transmit unless an enabling instruction is received Figure 5 5 shows the waveform while communication happening on two lines DEO CV User Manual 50 www terasic com asi May 4 2015 www terasic com Sending command CLK Inhibit 1st 2nd gth 101 11 CLK CLK CLK CLK cuk eooo DATA ame Ae Start bit Bit0 Bit7 Parity bit Stop Line bit control bit Receiving data 4st 2nd 1 Om 1 qth CLK CLK CLK CLK CLK 9 4 Start bit BitO Bit7 Parity bit Stop bit Figure 5 5 Waveform of clock and data signals during data transmission Demonstration Source Code e Project directory DEO CV PS2 DEMO e Bitstream used DEO CV PS2 DEMO sof Demonstration Batch File Demo batch file directoy DEO CV PS2 DEMO Memo batch The folder includes the following files e Batch file DEO CV PS2 DEMO bat e FPGA configuration file DEO CV PS2 DEMO sof DEO CV User Manual 51 www terasic com TadasiC May 4 2015 www terasic com Demonstration Setup File Locations and Instructions e Load the bitstream into the FPGA by executing 1DEO CV PS2 DEMO Memo batch DEO CV PS2 DEMO bat e Plug in the PS 2 mouse e Press KEYO to enable data transfer e Press KEY to clear the display data cache e The 7 segment display should change when the PS 2 mouse moves The LEDR 2 0 will blink according to Figure 5 6 and Table 5 2 when the left button right button and or middle button is pressed mme DEO CY redai Mm
14. into the Altera EPCS64 serial configuration device It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DEO CV board is turned off When the board s power is turned on the configuration data in the EPCS64 device is automatically loaded into the Cyclone V FPGA The sections below describe the steps to perform both JTAG and AS programming For both methods the DEO CV board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device DEO CV User Manual 18 www terasic com asi May 4 2015 www terasic com B Configuring the FPGA in JTAG Mode Figure 3 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone V FPGA you need to perform the following steps e Ensure that power is applied to the DEO CV board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW 10 to the RUN position See Figure 3 2 e Connect the USB cable provided to the USB Blaster port on the DEO CV board e The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the sof filename extension USB Blaster Circuit Quartus II Programmer MAX II JTAG UART EPM 240 EE JTAG Config Signals QUARTUS II PROG Figure 3 1 The JTAG configuration scheme Figure 3 2 The RU
15. onto the board DEO CV User Manual 8 www terasic com iasic May 4 2015 www terasic com Please note that the Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until the USB port is closed 7 The Control Panel is now ready to use experience it by setting the ON OFF status for some LEDs and observing the result on the DEO CV board ETTPTITITETEYEE 6 PAPA EE irem FA eluletelete EI Figure 2 1 The DEO CV Control Panel The concept of the DEO CV Control Panel is illustrated in Figure 2 2 The Control Circuit that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to send commands to the control circuit It handles all the requests and performs data transfers between the computer and the DEO CV board DEO CV User Manual 9 www terasic com asi May 4 2015 www terasic com 7 SEG Display USB Blaster Button Switch SD Card Figure 2 2 The DEO CV Control Panel concept The DEO CV Control Panel can be used to light up LEDs change the values displayed on the 7 segment monitor buttons switches status read write the SDRAM Memory output VGA color pattern to VGA monitor read SD Card specification information The feature of reading writing a word or an entire file from to
16. pausing target processor OK Initializing CPU cache if present OK s Starting processor at address x200201B8 nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB device 1 instance nios2 terminal Use the IDE stop button or Ctrl C to terminate SDRAM Test Size 64MB CPU Clock 143000000 gt any KEV to start test KEVB for continued test SDRAM Testing Iteration 1 jurite LO 281 30 40 SBL 60 70 80 907 1887 read uerify LOL 20 30 40 580 680 70 80 90 1887 SDRAM test Pass 9 seconds gt SDRAM Testing Iteration 2 write 180 20 30 40 580 60 70 80 90 1887 read uverify 107 20 381 40x lc EE co x Figure 5 3 Display of progress and result for the SDRAM test in Nios II DEO CV M 47 asic CV User Manua www terasic com www terasic com May 4 2015 the directory 5 3 SDRAM Test in Verilog DEO CV system CD offers another SDRAM test with its test code written in Verilog HDL The memory size of the SDRAM bank tested is still 64MB B Function Block Diagram Figure 5 4 shows the function block diagram of this demonstration The SDRAM controller uses 50 MHz as a reference clock and generates 100 MHz as the memory clock Figure 5 4 Block diagram of the SDRAM test in Verilog RW Test module writes the entire memory with a test sequence first before comparin
17. refer to Figure 3 4 for detailed LED location Table3 1 Status LED Board Hen LED Name Description Reference IS 3 3 V Power Illuminates when 3 3 V power is active D ULED Illuminates when the on board USB Blaster is working AAAAAr DA tong arrears fa Brel Pesat ct sd ud t foe Figure 3 4 Status LED position 3 2 Using the LEDs and Switches B User Defined Push buttons The board includes four user defined push buttons and one FPGA reset button that allow users to interact with the Cyclone V device as shown in Figure 3 5 Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 3 6 The five outputs called KEYO KEYI DEO CV User Manual 21 WWW terasic com TidasiC May 4 2015 www terasic com KEY2 KEY3 and RESET N of the Schmitt Trigger devices are connected directly to the Cyclone V FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when depressed Since the push button switches are debounced they are appropriate for using as clocks or reset inputs in a circuit VCC3P3 Q wg N OTE RYAN Cyclone V 74AUC17 M7 Figure 3 5 Connections between the push button and Cyclone V FPGA pu depressed om released Before oo CNN EE RED ER PLL Schmitt Trigger Debounced GG Figure 3 6 Switch debouncing B User Defined Slide Switch There are ten slide switches connected to FPGA on the board See Figure 3
18. this demonstration and the location of its files are shown below Demonstration File Locations e Project directory DEO CV Default e Bitstream used DEO CV Default sof DEO CV Default pof or DEO CV Default jic Demonstration Setup and Instructions DEO CV User Manual 43 www terasic com T TjasiC May 4 2015 www terasic com e Power on the DEO CV board with the USB cable connected to the USB Blaster port If necessary that is 1f the default factory configuration is not currently stored in the EPCS device download the bit stream to the board via JTAG interface e You should now be able to observe the 7 segment displays are showing a sequence of characters and the red LEDs are blinking e Press FPGA RESET to make LEDs and 7 SEGs all light on e If the VGA D SUB connector is connected to a VGA display it would show a color picture Restore Factory Configuration e Configuring the EPCS64 in AS Mode 1 Ensure that power is applied to the DEO CV board Connect the supplied USB cable to the USB Blaster port on the DEO CV board Configure the JTAG programming circuit by setting the RUN PROG slide switch SW10 to the PROG position Execute the demo batch file pof DEO CV Default bat for USB Blaster under the batch file folder DEO CV Default demo batch Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this a
19. wrapper for users to add their own design logic The Ouartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Ouartus II programmer is used to download sof file to the development board via JTAG interface Start Launch Quartus II Launch DEO CV System and Open Project Builder Add User Create New DEO CV Design Logic System Builder Project Compile to Generate Quartus II generate SOF Project and Document Configure FPGA End Figure 4 1 Design flow of building a project from the beginning to the end 4 3 Using DEO CV System Builder This section provides the procedures in details on how to use the DEO CV System Builder B Install and Launch the DEO CV System Builder The DEO CV System Builder is located in the directory Tools SystemBuilder of the DEO CV System CD Users can copy the entire folder to a host computer without installing the utility A window will pop up as shown in Figure 4 2 after executing the DEO CV SystemBuilder exe on the host computer DEO CV User Manual 38 www terasic com TadasiC May 4 2015 www terasic com UNIVERSITY UNIVERSITY irane cor DEO CV FPGA Board LEERLO BAHAN System Configuration Project Name DEO CV M CLOCK V 7 Seqment x 6 MI LEDx10 M Switch x 10 M Button x 4 vl PS2 MIVGA V SDRAM 64MB microSD Card GPIO 0 Header
20. 4 1 Introduction The DEO CV System Builder is a Windows based utility It is designed to help users create a Ouartus II project for DEO CV within minutes The generated Ouartus II project files include e Quartus II project file gpf e Quartus II setting file gsf e Top level design file v e Synopsis design constraints file sdc e Pin assignment document htm The above files generated by the DEO CV System Builder can also prevent occurrence of situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are e Board is damaged due to incorrect bank voltage setting or pin assignment e Board is malfunctioned because of wrong device chosen declaration of pin location or direction is incorrect or forgotten e Performance degradation due to improper pin assignment 4 2 General Design Flow This section provides an introduction to the design flow of building a Quartus II project for DEO CV under the DEO CV System Builder The design flow is illustrated in Figure 4 1 The DEO CV System Builder will generate two major files a top level design file v and a Quartus II setting file qsf after users launch the DEO CV System Builder and create a new project according to their design requirements DEO CV User Manual 37 www terasic com asi May 4 2015 www terasic com The top level design file contains a top level Verilog HDL
21. 7 These switches are not debounced and are assumed for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone V FPGA When the switch is in the DOWN position closest to the edge of the board it provides a low logic level to the FPGA and when the switch is in the UP position it provides a high logic level DEO CV User Manual 22 www terasic com TadasiC May 4 2015 www terasic com JA DTE RYAN Cyclone v nmn Logic 1 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SWO Logic 0 Figure 3 7 Connections between the slide switches and Cyclone V FPGA B User Defined LEDs There are also ten user controllable LEDs connected to FPGA on the board Each LED is driven directly by a pin on the Cyclone V FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 3 8 shows the connections between LEDs and Cyclone V FPGA Table 3 2 Table 3 3 and Table 3 4 list the pin assignment of user push buttons switches and LEDs DEO CV User Manual 23 www terasic com TadasiC May 4 2015 www terasic com LEDRO LEDRO AA2 AM LEDRI LEDR1 ME LLEDR2 LEDR2 v3 LEDR3 LEDR3 ANU S RYAN No LEDR4 LEDR4 e NN LEDRS LEDR5 Cyclone V up LEDR6 LEDR6 yy LEDR7 LEDR7 y L2 LEDR8 LEDR8 4 LEDR9 LEDRI Figure 3 8 Connections between the LEDs and Cyclone V FPGA Table 3 2 Pin Assignment of Push buttons Signal Name FPGA Pin
22. ADDR6 PIN P12 SDRAM Address 6 DRAM ADDR7 PIN P7 SDRAM Address 7 DRAM ADDR8 PIN P8 SDRAM Address 8 DRAM ADDR9 PIN R5 SDRAM Address 9 DRAM ADDR10 PIN U8 SDRAM Address 10 DRAM ADDR11 PIN P6 SDRAM Address 11 DRAM ADDR12 PIN R7 SDRAM Address 12 DRAM DQO PIN Y9 SDRAM Data 0 DRAM DQ1 PIN T10 SDRAM Data 1 DRAM_DQ2 PIN R9 SDRAM Data 2 DRAM D 3 PIN Y11 SDRAM Data 3 DRAM DQ4 PIN R10 SDRAM Data 4 DRAM DQ5 PIN R11 SDRAM Data 5 DRAM DQ6 PIN R12 SDRAM Data 6 DRAM DQ7 PIN AA12 SDRAM Data 7 DRAM DQ8 PIN AA9 SDRAM Data 8 DRAM DQ9 PIN AB8 SDRAM Data 9 DEO CV User Manual 35 www terasic com May 4 2015 www terasic com DRAM DQ10 DRAM DQ11 DRAM DQ12 DRAM DQ13 DRAM DQ14 DRAM DQ15 DRAM BAO DRAM BA1 DRAM LDQM DRAM UDOM DRAM RAS N DRAM CAS N DRAM CKE DRAM CLK DRAM WE N DRAM CS N PIN AA8 PIN AA7 PIN V10 PIN V9 PIN U10 PIN T9 PIN T7 PIN AB7 PIN U12 PIN N8 PIN AB6 PIN V6 PIN R6 PIN AB11 PIN AB5 PIN U6 DEO CV User Manual 36 SDRAM Data 10 SDRAM Data 11 SDRAM Data 12 SDRAM Data 13 SDRAM Data 14 SDRAM Data 15 SDRAM Bank Address 0 SDRAM Bank Address 1 SDRAM byte Data Mask 0 SDRAM byte Data Mask 1 SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Clock Enable SDRAM Clock SDRAM Write Enable SDRAM Chip Select www terasic com May 4 2015 Chapter 4 DEO CV System Builder This chapter describes how users can create a custom design project with the tool named DEO CV System Builder
23. DEO CV User Manual www terasic com Copyright 2003 2015 Terasic Inc All Rights Reserved CONTENIS geo Chapter 1 Introduction 3 1 1 IIO CHOISIE 3 X2 DEOCV System CD ME ena en mua aa aa BA RR in 4 1 3 Layout and COMpODENES 4 mani bhn enak Hanana ea apa nahas aan 4 1 4 Block Diagram of the Cyclone V Starter Board ooooWo oo anaak 6 1 5 Getting Help nn ane dun mu emas alam Ska 7 Chapter 2 Control Pangkas 8 2 1 Control Panel Setup mn nini dia AN a a 8 2 2 Controlling the LEDs 7 segment Displays enak 10 2 3 Switches and PuSh buttonS isita basa kaan ea Esa SEA da 12 2 4 SDRAM Controller and Programmer oo mna 12 2 5 Nose rO M 14 DO MOA ni ne tenan RN aa en aan aan canes anne E anna Saree sates Den Btn binasa un 15 2 7 Overall Structure of the DEO CV Control Panel ooooooooooooWoW WWW 16 Chapter 3 Using the Starter Kit m 18 3 1 Configuration of Cyclone V FPGA on DEO CV oooocoo o om munnnannannaannnaa 18 3 2 Using the LEDs and Switches coooooooWom anna 21 3 3 Using the segment Displays eicere n terreni Lee tiep makin aa asa 25 3 4 gie Siri dE 27 3 5 Using 2x20 GPIO Expansion Headers ooooooooo oma 27 2003 USME Ceca as oon mn na ie AAA AA NA AA a ANA 30 Sed JPS ZSenal P
24. DEO CY Cvesenel Blaster ET L Fag Controller Chipset Altera 28 nm Cyclone V FPGA 5CEBA4F23C7N 2x20 GPIOx2 RUN PROG Switch for JTAG AS Modes 7 Segment Display LED x10 Switch x10 64MB Button x4 FPGA SDRAM Reset Figure 1 2 Development Board top view DEO CV User Manual 4 www terasic com ijasic May 4 2015 www terasic com Altera USB Blaster Controller Chipset one EPCS I Nl 64MB ccena eee x e x HNN Le 94v 0 o x cmos 1445 F e E P014100098 ci EEEE MEM Figure 1 3 Development Board bottom view This board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board FPGA Device Cyclone V SCEBA4F23C7N Device 49K Programmable Logic Elements 3080 Kbits embedded memory 4 Fractional PLLs Configuration and Debug e Serial Configuration device EPCS64 on FPGA e On Board USB Blaster Normal type B USB connector e JTAG and AS mode configuration supported Memory Device DEO CV User Manual 5 www terasic com TadasiC May 4 2015 www terasic com e 64MB SDRAM x16 bits data bus Communication e PS 2 mouse keyboard Connectors e 2x20 GPIO Header Display e Uses a 4 bit resistor network DAC e With 15 pin high density D sub connector Micro SD Card Socket e Provides SPI and 4 bit SD mode for Micro SD Card access Switches B
25. Eclipse v14 0 Demonstration Source Code e Quartus project directory DEO CV SDRAM Nios Test e Nios II Eclipse directory DEO CV SDRAM Nios Test Software Nios II Project Compilation e Click Clean from the Project menu of Nios II Eclipse before compiling the reference design in Nios II Eclipse DEO CV User Manual 46 WWW terasic com ijasic May 4 2015 www terasic com Demonstration Batch File The files are located in the director DEO CV SDRAM Nios Test demo batch The folder includes the following files e Batch file for USB Blaster IT DEO CV SDRAM Nios Test bat and DEO CV SDRAM Nios Test sh e FPGA configuration file DEO CV SDRAM Nios Test sof e Nios II program DEO CV SDRAM Nios Test elf Demonstration Setup e Quartus II v14 0 and Nios II v14 0 must be pre installed on the host PC e Power on the DEO CV board e Connect the DEO CV board J13 to the host PC with a USB cable and install the USB Blaster driver if necessary e Execute the demo batch file DEO CV SDRAM Nios Test bat from DEO CV SDRAM Nios Testidemo batch e After the program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Press any button KEY3 KEYO to start the SDRAM verification process Press KEYO to run the test continuously e The program will display the test progress and result as shown in Figure 5 3 r ES Altera Nios II EDS 14 0 gcc4 F o o Resetting and
26. Figure 3 16 Instructions on how to use PS 2 mouse and or keyboard can be found on various educational websites The pin assignment associated to this interface is shown in Table 3 11 Q Note If users connect only one PS 2 equipment the PS 2 signals connected to the FPGA I O should be PS2 CLK and PS2 DAT PS2 CLK D3 Ez PS2CLK2 ANU S n AN Cyclone V PS2_DAT2 J12 G1 al G2 PS2DAT Figure 3 15 Connections between the FPGA and PS 2 DEO CV User Manual 32 www terasic com LjasiC May 4 2015 www terasic com Sa G ity Figure 3 16 Y Cable for using keyboard and mouse simultaneously Table 3 11 Pin Assignment of PS 2 Signal Name FPGA Pin No Description PS2 CLK PIN D3 PS 2 Clock PS2 DAT PIN G2 PS 2 Data PS2 CLK2 PIN E2 PS 2 Clock reserved for second PS 2 device PS2 DAT2 PIN G1 PS 2 Data reserved for second PS 2 device 3 8 Micro SD Card Socket The development board supports Micro SD card interface using x4 data lines Figure 3 17 shows the related signals connections between the SD Card and Cyclone V FPGA and Figure 3 18 shows micro SD card plug in position Finally Table 3 12 lists all the associated pins Micro SD Card Socket SD DATA2 SD DATA3 CD Figure 3 17 Connection between the SD Card Socket and Cyclone V FPGA DEO CV User Manual 33 www terasic com Tasic May 4 2015 www terasic com Figure 3 18 Micro SD Card Table
27. N PROG switch SW10 is set in JTAG mode DE0 CV User Manual 19 WWW terasic com i34asiC May 4 2015 www terasic com B Configuring the EPCS64 in AS Mode Figure 3 3 illustrates the AS configuration setup To download a configuration bit stream into the EPCS64 serial configuration device you need to perform the following steps e Ensure that power is applied to the DEO CV board e Connect the USB cable provided to the USB Blaster port on the DEO CV board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW10 to the PROG position e The EPCS64 chip can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the pof filename extension e Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip USB Blaster Circuit Quartus II RU AS Mode Auto Power on NB S SYN NN Programmer MAX II Config Config E 9 EPM 240 QUARTUS II Cyclone V PROG EPCS64 Figure 3 3 The AS configuration scheme DEO CV User Manual 20 www terasic com asi May 4 2015 www terasic com B Status LED e The FPGA development board includes board specific status LEDs to indicate board status Please refer to Table 3 1 for the description of the LED indicator Please
28. ONdemo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Copy DE0 CV SD DEMOMWMemo batchttest txt files to the root directory of the SD Card e Insert the Micro SD Card into the SD Card socket of DEO CV as shown in Figure 5 9 DEO CV User Manual 55 www terasic com asi May 4 2015 www terasic com Figure 5 9 Insert the Micro SD card into DEO CV e Press KEY3 of the DEO CV board to start reading SD Card e The program will display SD Card information as shown in Figure 5 www terasic com Pr E Altera Nios II EDS 14 0 gcc4 DE CU SDCARD Demo please ensure the sd card has been inserted into de cv board Processing FAT IFAT32 IFAT1Fat Mount success FAT Fat Mount success sdcard mount success Root Directory Item Count 8 I lApplication Selector 1 1JPG 2 ITEST T3T C3 IMUSIC WAU 4Imusic 4mb wav 5 Imusic long wav 6 1PCIe Fundamental C7 1PCIe DriverInstall test txt dump Le 2 e 9 dib Kak x kk bada Kak kk Test Done KEY3 to test again Figure 5 10 Running result of SD CARD demo on DEO CV board DEO CV User Manual 56 www terasic com May 4 2015 5 6 VGA Pattern This demonstration displays a simple blue red and green color pattern on a VGA monitor using the VGA output interface on DEO CV board Figure 5 11 shows the block diagram of the design The major block called video s
29. PGA and VGA DEO CV User Manual 30 www terasic com A asi May 4 2015 www terasic com The timing specification for VGA synchronization and RGB red green blue data can be easily found on website nowadays Figure 3 13 illustrates the basic timing reguirements for each row horizontal displayed on a VGA monitor An active low pulse of specific duration is applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB output to the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of vertical synchronization vsync is similar to the one shown in Figure 3 14 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 8 and Table 3 9 show different resolutions and durations of time period a b c and d for both horizontal and vertical timing The pin assignments between the Cyclone V FPGA and the VGA connector are listed in Table 3 10 Back porch b Front porch d I I Display interval c I
30. System Configuration Project Name DEO CV MI CLOCK 4 T Seqment x 6 v LEDx10 4 Switch x 10 M Button x 4 M PS2 MI VGA SDRAM 64MB MI microSD Card GPIO 0 Header None Prefix Name GPIO 1 Header Save Setting Generate LoadSetting Exit None Prefix Name Figure 4 4 System configuration group B GPIO Expansion If users connect any Terasic GPIO based daughter card to the GPIO connector s on DEO CV the DEO CV System Builder can generate a project that include the corresponding module as shown in Figure 4 5 It will also generate the associated pin assignment automatically including pin name pin location pin direction and I O standard DEO CV M 40 asic CV User Manua www terasic com www terasic com May 4 2015 DEO CV V0 0 UNIVERSITY z P RO G RA Mii mw cerasic com Project Name ATERA System Configuration DE0 CV FPGA Board DEG LY 7 CLOCK VI LED x10 M Button x 4 i VGA VI microSD Card GPIO 0 Header 4 7 Seqment x 6 4 Switch x 10 v PS2 VI SDRAM 64MB D5M 5M Pixel Camera Prefix Name GPIO 1 Header Save Setting Generate None Prefix Name Load Setting Exit Figure 4 5 GPIO expansion group The Prefix Name is an optional feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank B Project Setting Management The
31. also shows how Altera s SDRAM controller IP accesses SDRAM and how the Nios II processor reads and writes the SDRAM for hardware verification The SDRAM controller handles complex aspects of accessing SDRAM such as initializing the memory device managing SDRAM banks and keeping the devices refreshed at certain interval B System Block Diagram Figure 5 2 shows the system block diagram of this demonstration The system requires a 50 MHz clock input from the board The SDRAM controller is configured as a 64MB controller The working frequency of the SDRAM controller is 143 MHz and the Nios II program is running on the on chip memory DEO CV User Manual 45 www terasic com asi May 4 2015 www terasic com FPGA QSYS On Chip Nios II lt gt e Memory PIO Le Controller f SDRAM L Seo 50 MHz System Intercoment Fabric Figure 5 2 Block diagram of the SDRAM test in Nios II The system flow is controlled by a program running in Nios II The Nios II program writes test patterns into the entire 64MB of SDRAM first before calling the Nios II system function alt dcache flush all to make sure all the data are written to the SDRAM It then reads data from the SDRAM for data verification The program will show the progress in nios terminal when writing reading data to from the SDRAM When the verification process reaches 100 the result will be displayed in nios terminal Design Tools e Quartus II v14 0 e Nios II
32. anel provides VGA pattern function that allows users to output color pattern to LCD CRT monitor using the DEO CV board Follow the steps below to generate the VGA pattern function Choosing the VGA tab leads to the window in Figure 2 8 Plug a D sub cable to the VGA connector of the DEO CV board and LCD CRT monitor The LCD CRT monitor will display the same color pattern on the control panel window Click the drop down menu shown in Figure 2 8 where you can output the selected pattern individually DEO CV User Manual 15 www terasic com asi May 4 2015 www terasic com CEPITITTEITI MAA PARA fad uh Amon PN DSAI Li Memory Pattern Figure 2 8 Controlling VGA display under Control Panel 2 7 Overall Structure of the DEO CV Control Panel The DEO CV Control Panel is based on a Nios II Qsys system instantiated in the Cyclone V FPGA with software running on the on chip memory The software part is implemented in C code the hardware part is implemented in Verilog HDL code with Qsys builder The source code is not available on the DEO CV System CD To run the Control Panel users should follow the configuration setting according to Section 3 1 Figure 2 9 depicts the structure of the Control Panel Each input output device is controlled by the Nios II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The Nios II interprets the commands sent from the PC and performs the corre
33. ction causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip e Configuring the EPCS64 with JIC File 1 Ensure that power is applied to the DEO CV board 2 Connect the supplied USB cable to the USB Blaster port on the DEO CV board 3 Execute the demo batch file DEO CV_Default bat for USB Blaster under the batch file folder DEO_CV_Default demo_batch 4 As shown in Figure 5 1 It is able to not only load the bit stream into the FPGA in command line but also program or erase jic file to the EPCS by executing the batch file 5 If users want to program a new design into the EPCS device an easy method is to copy the new sof file file name must be DEO_CV_Default sof into the demo_batch folder and execute the DEO CV Default bat Option 2 will convert the sof to jic and option 3 will program jic file into the EPCS device asic DEO CV User Manual 44 ga www terasic com Plesase choose your operation for programming sof to FPGA 2 for converting sof to jic for programming jic to EPCS for erasing jic from EPCS 9839839009009 eee Please enter your choise 1 2 3 4 Figure 5 1 Command line of the batch file to program the FPGA and EPCS device 5 2 SDRAM Test in Nios II There are many applications using SDRAM as a temporary storage Both hardware and software designs are provided to illustrate how to perform memory access in Qsys in this demonstration It
34. e Micro SD Card hardware The SD 4 bit protocol and FAT File System function are all implemented by Nios II software The software is stored in the on chip memory 50 MHz o lt o oO T 3 E LED oO a o 0 TM o F a SD Card Socket Figure 5 7 Block diagram of the Micro SD demonstration DEO CV User Manual 53 www terasic com iyasic May 4 2015 www terasic com Figure 5 8 shows the software stack of this demonstration The Nios PIO block provides basic IO functions to access hardware directly The functions are provided from Nios II system and the function prototype is defined in the header file lt io h gt The SD Card block implements 4 bit mode protocol for communication with SD Cards The FAT File System block implements reading function for FAT16 and FAT 32 file system Long filename is supported By calling the public FAT functions users can browse files under the root directory of the MicroSD Card Furthermore users can open a specific file and read the contents from the file The main block implements main control of this demonstration When the program is executed it detects whether an Micro SD Card is inserted If an MicroSD Card is found it will check whether the MicroSD Card is formatted as FAT file system If so it searches all files in the root directory of the FAT file system and displays their names in the Nios II terminal If a text file named test txt is found it will dump th
35. e Quartus II v14 1 must be pre installed to the host PC e Power on the DEO CV board e Connect USB Blaster to the DEO CV board and install USB Blaster driver if necessary e Connect VGA D SUB to a VGA monitor e Execute the demo batch file DEO CV VGA Pattern bat from the directory VDEO CV VGA Pattern Memo batch e The VGA monitor will display a color pattern Figure 5 13 illustrates the setup for this demonstration TAR PARRA Pet Figure 5 13 The setup for the VGA Pattern demonstration DEO CV User Manual 58 www terasic com Tasic May 4 2015 www terasic com Additional Information Getting Help Here are the addresses where you can get help if you encounter problems e Terasic Inc 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Web www terasic com DEO CV Web www DEO CV terasic com Revision History Date Version Changes 2014 12 First publication 2015 04 Document revision 2015 5 Modified DEO CV package content figure DEO CV User Manual 59 www terasic com asi May 4 2015 www terasic com
36. e file contents If it successfully recognizes the FAT file system it will turn on the LEDR4 LEDRO On the other hand it will turn on the LEDR9 LEDRS if it fails to parse the FAT file system or if there is no SD card found in the SD Card socket of the DEO CV board If users press KEY3 of the DEO CV board the program will perform the above process again Figure 5 8 Software of micro SD demonstration Design Tools e Quartus II14 0 e Nios IIEclipsel4 0 Demonstration Source Code e Quartus Project directory DEO_CV_SD_DEMO e Nios II Eclipse DEO_CV_SD_DEMO Software Nios II Project Compilation DEO CV User Manual 54 www terasic com ijasic May 4 2015 www terasic com e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstration Batch File Demo Batch File Folder DEO CV SD DEMO Memo batch The demo batch file includes following files Batch Filefor USB Blaster e DEO CV SD DEMO bat e DEO CV SD DEMO sh e FPGA Configure File DEO CV SD DEMO sof e Nios II Program DEO CV SD DEMO elf Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Power on the DEO CV board e Connect USB Blaster to the DEO CV board and install USB Blaster driver if necessary e Execute the demo batch file DEO CV SD DEMO bat for USB Blaster II under the batch file folder DEO CV SD DEM
37. ent Digit 4 2 HEX43 PIN U16 Seven Segment Digit 4 31 HEX44 PIN U15 Seven Segment Digit 4 4 HEX45 PIN Y15 Seven Segment Digit 4 5 HEX46 PIN P9 Seven Segment Digit 4 6 HEX50 PIN N9 Seven Segment Digit 5 0 HEX51 PIN M8 Seven Segment Digit 5 1 HEX52 PIN T14 Seven Segment Digit 5 2 HEX53 PIN P14 Seven Segment Digit 5 3 HEX54 PIN C1 Seven Segment Digit 5 4 HEX55 PIN C2 Seven Segment Digit 5 5 HEX56 PIN W19 Seven Segment Digit 5 6 asic DEO CV User Manual 26 o cus www terasic com 3 4 Clock Circuitry Figure 3 10 shows the clock circuit of DEO CV Board the crystal 50 MHz buffered to four SOMHz clock The associated pin assignment for clock inputs to FPGA Y O pins is listed in Table 3 6 CLOCK2 50 ecl 50MHz gt 50MHz a wo a c e lt i x c a Bank 3A Bank 3B Bank 4A CLOCK 50 CLOCK4 50 Figure 3 10 Clock circuit of the FPGA Board Table 3 6 Pin Assignment of Clock Inputs Signal Name FPGA Pin No Description CLOCK 50 PIN M9 50 MHz clock input Bank 3B CLOCK2 50 PIN H13 50 MHz clock input Bank 7A CLOCK3 50 PIN E10 50 MHz clock input Bank 8A CLOCK4 50 PIN V15 50 MHz clock input Bank 4A 3 5 Using 2x20 GPIO Expansion Headers The board has two 40 pin expansion headers Each header has 36 user pins connected directly to the Cyclone V FPGA It also comes with DC 5V VCC5 DC 3 3V VCC3P3 and two GND pins Both 5V and 3 3V can provide a total of 5W power Each pin
38. f the PS 2 clock signal This is implemented by a shift register which consists of 33 bits easily be implemented using a shift register of 33 bits but be cautious with the clock domain crossing problem B Data Transmission from the Controller to Device When the PS 2 controller wants to transmit data to device it first pulls the clock line low for more than one clock cycle to inhibit the current transmission process or to indicate the start of a new transmission process which is usually called as inhibit state It then pulls low the data line before releasing the clock line This is called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequence in less than 10ms time The transmit data consists of 12bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit always zero After sending out the parity check bit the controller should release the data line and the device will detect any state change on the data line in the next clock cycle If there s no change on the data line for one clock cycle the device will pull low the data line again as an acknowledgement which means that the data is correctly received After the power on cycle of the PS 2 mouse it enters into stream mode automatically and
39. g the data read back with the regenerated test sequence which is same as the data written to the memory KEYO triggers test control signals for the SDRAM and the LEDs will indicate the test result according to Table 5 1 Design Tools e Quartus II v14 0 Demonstration Source Code e Project directory DEO CV SDRAM RTL Test e Bitstream used DEO CV SDRAM RTL Test sof DEO CV User Manual 48 www terasic com TadasiC May 4 2015 www terasic com Demonstration Batch File Demo batch file folder DEO CV SDRAM RTL Testidemo batch The directory includes the following files e Batch file DEO CV SDRAM RTL Test bat e FPGA configuration file DEO CV SDRAM RTL Test sof Demonstration Setup e Quartus II v14 0 must be pre installed to the host PC e Connect the DEO CV board J13 to the host PC with a USB cable and install the USB Blaster II driver if necessary e Power on the DEO CV board e Execute the demo batch file DEO CV SDRAM RTL Test bat from the directoy DEO CV SDRAM RTL Test demo batch e Press KEYO on the DEO CV board to start the verification process When KEYO is pressed the LEDR 2 0 should turn on When KEYO is then released LEDR1 and LEDR2 should start blinking e After approximately 8 seconds LEDRI should stop blinking and stay ON to indicate the test is PASS Table 5 1 lists the status of LED indicators e If LEDR2 is not blinking it means 50MHz clock source is not working e If LEDRI failed to remain ON after
40. into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 2 6 depicts the result of writing the hexadecimal value 06CA into offset address 200 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 Toinitiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file location in the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789ABCDEF DEO CV User Manual 13 www terasic com asi May 4 2015 www terasic com defines eight 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively into the memory The Sequential Read function is used to read the contents of the SDRAM and fill them in
41. nd handheld devices The DEO CV development board includes hardware such as on board USB Blaster video capabilities and much more By leveraging all of these capabilities the DEO CV is the perfect solution for showcasing evaluating and prototyping the true potential of the Altera Cyclone V FPGA The DEO CV contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a photograph of the DEO CV package DEO CV board Type A to B USB Cable Power DC Adapter 5V Figure 1 1 The DEO CV package contents The DEO CV package includes e The DEO CV board e 5V DC Power Supply e Type A Male to Type B Male USB Cable DEO CV User Manual 3 www terasic com iasic May 4 2015 www terasic com 1 2 DEO CV System CD The DEO CV System CD contains the documentation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets User can download this System CD from the web http cd de0 cv terasic com 1 3 Layout and Components This section presents the features and design characteristics of the board A photograph of the board is shown in Figure 1 2 and Figure 1 3 It depicts the layout of the board and indicates the location of the connectors and key components USB Power Blaster VGA DC JACK Port Out PS 2 Micro SD Card Power ON OFF Altera USB EET ni m
42. on the expansion headers is connected to two diodes and a resistor for protection against high or low voltage level Figure 3 11 shows the protection circuitry applied to all 2x36 data pins Figure 3 11 shows the related schematics Table 3 7 shows the pin assignment of two GPIO headers DEO CV User Manual 27 www terasic com A asi May 4 2015 www terasic com GPIO 0 35 0 VORGSPS JP1 JP2 5 BERR ERE RE RER REE EEE ES RE E EE EEEBEEEEEERLEELX J L Figure 3 11 Connections between the GPIO header and Cyclone V FPGA GPIO 0 JP1 GPIO 0 DO GPIO 0 D2 GPIO 0 D4 GPIO 0 D6 GPIO 0 D8 Clock in Clock in GPIO D1 D3 D5 D7 D9 GPIO GPIO GPIO GPIO C16 K20 K22 M21 GPIO 1 JP2 Clock in SPIO DO 2 Clock in GPIO 1 D2 GPIO 1 D4 GPIO 1 D6 GPIO 1 D8 209 Mo GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO_ GPIO 0 D10 cpoooi ad GPIO 1 D10 m GPIO 0 D12 GPIO 0 D13 n GPIO 1 D12 PE GPIO 0 D14 GPIO 0 p15 e GPIO 1 D14 NEM Glodcoui non SPIOLO 16 GPIO 0 D17 pig GPIO_1_D16 o a GPIO 0 D18 GPIO 0 D19 Ta GPIO 1 D18 Ema GPIO 0 D20 GPIO 0 D21 wig GPIO 1 D20 Ew GPIO 0 D22 GPoorps GPIO 1 D22 GPIO 0 D24 GPIO 0 D25 um GPIO 1 D24 o E ERG Vegas GPIO 0 D26 GPIOO D27 Vecara GPIO 1 D26 s GPIO 0 D28 GPO002 p47 GPIO 1 D28
43. ort uii ee Nan 32 3 8 Micro SD Card Socket 5 hawa en sunan mangsa ganguan unggas 33 3 9 Using SDRA Meme 34 Chapter 4 DEO CY System Builder rini ema minan 37 4 1 Introduction a a a A AA A a ai 37 4 2 General Design HIOW tisk nn nn an dk ie ia ha ana anemia ana am anakan ia 37 4 3 Using DEO CV System Builder ie 38 DEO CV User Manual 1 www terasic com asic May 4 2015 www terasic com Chapter 5 Examples of Advanced Demonstrations oooooooooooooooooooooooooooooooo 43 5 1 DEO CV Factory Configuration o ooooooo enne nennen nnne tette netten enne 43 5 2 SDRAM Testin Nios UW er 45 5 3 SDRAM Testin Venlog desi ae tete enteng Ka unta mia Na nana 48 5 4 PS 2 Mouse Demonstration nn nona nan kan Na ea En hinaan 49 5 5 Micro SD Card file system read o ooooooooo om anna 53 550 MGA Pattern AN EA KRB ANN AAN NN 57 DEO CV User Manual 2 www terasic com iasic May 4 2015 www terasic com Chapter 1 Introduction The DEO CV presents a robust hardware design platform built around the Altera Cyclone V FPGA which is optimized for the lowest cost and power reguirement for transceiver applications with industry leading programmable logic for ultimate design flexibility With Cyclone V FPGAs you can get the power cost and performance levels you need for high volume applications including protocol bridging motor control drives and capture cards a
44. sponding actions DEO CV User Manual 16 www terasic com iasic May 4 2015 www terasic com FPGA ASYS lt gt 7 SEG Display JTAG Blaster Hardware LED Button Switch SDCard 9uqe joeuuoo1oju WajsAS Figure 2 9 The block diagram of the DEO CV control panel DEO CV User Manual 17 WWW terasic com asic May 4 2015 www terasic com Chapter 3 Using the Starter Kit This chapter provides an instruction to use the board and describes the peripherals 3 1 Configuration of Cyclone V FPGA on DEO CV The DEO CV board contains a serial configuration device that stores configuration data for the Cyclone V FPGA This configuration data is automatically loaded from the configuration device into the FPGA when powered on Using the Ouartus II software it is possible to reconfigure the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial configuration device Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone V FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded
45. the Memory allows the user to develop multimedia applications without worrying about how to build a Memory Programmer 2 2 Controlling the LEDs 7 segment Displays A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays Choosing the LED tab leads to the window in Figure 2 3 Here you can directly turn the LEDs on or off individually or by clicking Light All or Unlight All DEO CV User Manual 10 www terasic com IT TjasiC May 4 2015 www terasic com y ae Pers PN eejejelajetalaja js n Memory P 7 seG socard iu Xv SY Switches VGA i DA ED DISCONNECT LEOS RLED8 RLED7 RLEDS RLED5 RLED4 RLED3 RLED2 RLED1 RLE Figure 2 3 Controlling LEDs Choosing the 7 SEG tab leads to the window shown in Figure 2 4 From the window directly use the left right arrows to control the 7 SEG patterns on the DEO CV board which are updated immediately Note that the dots of the 7 SEGs are not enabled on the DEO CV board TETIT pag Mem um W o w vieizieizisisla P Figure 2 4 Controlling 7 SEG display DEO CV User Manual 11 www terasic com iasic May 4 2015 www terasic com The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives users a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be
46. to a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM are to be copied which involves all 64 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 2 5 SD Card The function is designed to read the identification and specification information of the SD Card The 4 bit SD MODE is used to access the SD Card This function can be used to verify the functionality of the SD Card Interface Follow the steps below to perform the SD Card exercise 1 Choosing the SD Card tab leads to the window in Figure 2 7 2 Insert an SD Card to the DEO CV board and then press the Read button to read the SD Card The SD Card s identification specification and file format information will be displayed in the control window DEO CV User Manual 14 www terasic com asi May 4 2015 www terasic com oh TPTirrrerryr 8 erra SAS ra O bd ed had BEL g Manufacturer ID 1Bh OEM Application ID 4D53h Product Name 00000 Product Revision 10h Serial No B113ASA1h Date Code 08Ah f Memory Capacity 3925MB DISCONNECT FAT32 i Figure 2 7 Reading the SD Card Identification and Specification 2 6 VGA DEO CV Control P
47. used for troubleshooting purposes 2 3 Switches and Push buttons Choosing the Switches tab leads to the window in Figure 2 5 The function is designed to monitor the status of slide switches and push buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the slide switches and push buttons Cesk Rae A ea Ob Tur elelele KEY3 KEY2 KEY1 KEYO e 1000000000 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SWO Figure 2 5 Monitoring switches and buttons The ability to check the status of push button and slide switch is not needed in typical design activities However it provides users a simple mechanism to verify if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 2 4 SDRAM Controller and Programmer The Control Panel can be used to write read data to from the SDRAM chips on the DEO CV board As shown below we will describe how the SDRAM may be accessed Click on the Memory tab and select SDRAM to reach the window in Figure 2 6 DEO CV User Manual 12 www terasic com asi May 4 2015 www terasic com CITTITTEIITYIS D alaa ea Asah oh e de Med bad Lad Lad al bbe lb Om e SDRAM 2000000h WORDS 64 MB Recess 00000200 METPENEROECA BaN Address Lenath lo Fi File Length Address Length O ll Entire Memory Figure 2 6 Accessing the SDRAM A 16 bit word can be written
48. uttons and LEDs e 10 LEDs e 10 Slide Switches e 4 Debounced Push Buttons e CPU reset Push Buttons e Six 7 Segments Power e 5V DC input 1 4 Block Diagram of the Cyclone V Starter Board Figure 1 4 gives the block diagram of the board To provide maximum flexibility for the user all connections are made through the Cyclone V FPGA device Thus the user can configure the FPGA to implement any system design DEO CV User Manual 6 www terasic com Tiasic May 4 2015 www terasic com P m m VGA 4 bit DC 5V Micro Cyclone V EI 5CEBA4F23C7N FT245 GPIO 0 GPIO 1 x39 SDRAM64MB 16bits oboe EPCS64 H _Clock OSC Clock Butter x42 x10 x10 x4 x1 Dpto e B8HBBSH e e Isi I8 c 7 Segment Display x6 PETE RRRRRRRRRR Slide Switch x10 Figure 1 4 Board Block Diagram 1 5 Getting Help Here are the addresses where you can get help if you encounter any problem e Terasic Inc 9E No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 5750 880 Web http www DEO CV terasic com DEO CV User Manual 7 www terasic com ijasic May 4 2015 www terasic com Chapter 2 Control Panel The DEO CV board comes with a Control Panel program that allows users to access various components on the board from a host computer The host computer communicates with the board through a USB connection The program can be used to verif
49. y the functionality of components on the board or be used as a debug tool while developing any RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in the block diagram form and finally describes its capabilities 2 1 Control Panel Setup The Control Panel Software Utility is located in the directory Tools ControlPanel in the DEO CV System CD It s free of installation just copy the whole folder to your host computer and launch the control panel by executing the DEOCV ControlPanel exe Specific control circuits should be downloaded to your FPGA board before the control panel can request it to perform required tasks The program will call Quartus II tools to download the control circuit to the FPGA board through the USB Blaster USB 0 connection To activate the Control Panel perform the following steps 1 Make sure Quartus II 14 0 or a later version is installed successfully on your PC 2 Setthe RUN PROG switch to the RUN position 3 Connect the USB cable provided to the USB Blaster port connect the 5V power supply and turn the power switch ON 4 Start the executable DEOCV ControlPanel exe on the host computer The Control Panel user interface shown in Figure 2 1 will appear 5 The DEOCV ControlPanel sof bit stream is loaded automatically as soon as the DEOCV ControlPanel exe is launched 6 Incase of a disconnect click on CONNECT where the sof will be re loaded
50. ync generator generates the VGA timing signals horizontal synchronization vertical synchronization and blank in standard VGA resolution 640x480 pixels at 25 MHz These signals will be used in vga controller block for RGB data generation and data output Please refer to the chapter 3 6 in DEO CV User Manual on the DEO CVSystem CD for detailed information of using the VGA output As shown in Figure 5 12 the RGB data drives each pixel in turn across the row being displayed after the time period of back porch FPGA CLOCK3 50 aa L RGB gt Ra a M RUSSES OR E sync signals gt REEE VGA_HS VGA VS Figure 5 11 Block diagram of the VGA Pattern demonstration Name PIEPER Drea rane Kn DEUM Jn NET FUR USO a a L vga pllutjoutclk 0 Vi VGA HS H Conf18 0 0 X1X2XGX4X8X9X7X8X9X X OOO OOO X YSS co X 630 OCC X VGA B 3 0 i Oh Eh VGA G 3 0 i Oh VGA R 3 0 Oh Figure 5 12 Timing Waveform of VGA interface Design Tools e Quartus II 14 1 Demonstration Source Code e Quartus Project directory DEO CV VGA Pattern e Bitstream used DEO CV VGA Pattern sof Demonstration Batch File Demo Batch File Folder DEO CV SD DEMOMemo batch The demo batch file includes following files DEO CV User Manual 57 www terasic com TadasiC May 4 2015 www terasic com e Batch Filefor USB Blaster DEO CV VGA Pattern bat e FPGA Configure File DEO CV VGA Pattern sof Demonstration Setup
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