IDT79RC4640 - Digi-Key
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1. RV4640 133MHz RV4640 150MHz Parameter Conditions Minimum Maximum Minimum Maximum VoL 0 1V 0 1V llour 200 Vou Vec 0 1V Vec 0 1V VoL 0 4V 0 4 4mA Vou 24V 24V ViL 0 5V 0 2 0 5V 0 2Vcc Vin 0 7Vcc Voc 0 5V 0 7 Voc 0 5V lin 10uA 10uA 0 lt V lt Vee Cin EE 10pF 10pF Cour 10pF 10pF VOLEAK 20uA 20uA Input Output Leakage RV4640 180MHz RV4640 200MHz RV4640 267MHz Parameter Conditions Minimum Maximum Minimum Maximum Minimum Maximum VoL 0 1V 0 1V 0 1V 20uA VoL 0 4V 0 4V 0 4V 4mA Vi 0 5V 0 2 0 5V 0 2Vcc 0 5V 0 2 0 7Vec Vec 0 5V 0 7 Vec 0 5V 0 7Vcc Vec 0 5V lin 10uA 10uA 10uA 0 Vw lt Vec 10pF 10pF 10pF Cour 10pF 10pF 10pF l Oi 200 200 20uA Input Output Leakage 1 Industrial temperature range is not available at 267MHz 15 of 23 December 5 2008 IDT79RC4640 Power Consumption RV4640 RV4640 133MHz RV4640 150MHz Parameter Conditions Typical Max Typical Max System Condition 133 67MHz 150 75MHz standby 60 mA 60mA C 0pF 110 2 110 2 C 50pF active 400 mA 450mA 450 mA 500mA C OpF No SysAd activity 500 2 5002. Typical integer instruction mix and cache miss rates Vcc 3 3V TA 25 2 These are not tested They are the results of engineering analysis and are provided for reference only 3 Guaranteed by design 4 These are the specifications IDT tests to insure compliance 13 of 23 December 5 2008 IDT79RC4640 AC Electrical Characteristics Commercial Temperature Range R4640 5 0 5 Tease 0 C to 85 C Clock Parameters R4640 R4640 R4640 Parameter Symbol Test Conditions TOOMHz 133MHz Units Min Max Min Max Pipeline clock frequency 50 100 50 133 MHz MasterClock HIGH tMCHIGH Transition lt tycriseFal 4 3 ns MasterClock LOW tucLow Transition lt tucmisepay 4 3 ns MasterClock Frequency 25 50 25 67 MHz MasterClock Period 20 40 15 40 ns Clock Jitter for MasterClock t 250 250 ps MasterClock Rise Time tucRise 5 4 ns MasterClock Fall Time luca 5 4 ns ModeClock Period IModeCKP 256 256 ns T Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled 2 Guaranteed by design System Interface Parameters R4640 5 0 5 Tease 0 C to 85 C Note Timings are measured from 1 5V of the clock to 1 5V of the signal R4640 R4640
3. 4 1 i T i i i 1 i 1 i i i i i i n i i i i i i i 1 i i i i i 1 i i 1 i i 1 i i 1 1 ValidOut i i Release ipo i lt i Control Signal CPU received E y RdRdy i i i i WrRdy ExtRqst Validin NMI Int 5 0 m active low signal Figure 5 System Clocks Data Setup Output and Hold timing 19 of 23 December 5 2008 IDT79RC4640 Mode Configuration Interface Reset Sequence 2 3V 2 3V as RN sue ess MCIk VCCOK L2 ModeClock Bit DE gt 64K cycles ColdReset IDS tT DS Reset Figure 6 Power on Reset Master x 2 a ee MeO ee eee Dee 4 N xx 4o Vexxx x wje leeds PES d MCIk gt TDS IDS 2 gt 100 5 256 VCCOK _ 56 cycles ModeClock dM TMDS gt lt TMDH Bit Bit rx m Modeln _ 0 1 255 TDS gt lt lg TDS gt 64K MCIk cycles ColdReset __ 64 MCIk cydles gt gt TDS IV Reset Figure 7 Cold Reset MCIk MECOK 256 cycle M
4. Features High performance embedded 64 bit microprocessor 64 bit integer operations 64 bit registers Based the MIPS RISC Architecture 100MHz 133MHz 150MHz 180MHz 200MHz and 267MHz operating frequencies 32 bit bus interface brings 64 bit power to 32 bit system cost High performance DSP capability 133 5 Million Integer Mul Accumulate operations sec 267MHz 89 MFlops floating point operations 267MHz High performance microprocessor 133 5 Mul Add second 267MHz 89 267MHz gt 640 000 dhrystone 2 1 sec capability 267MHz 352 dhrystone MIPS High level of integration 64 bit 267 MHz integer CPU 8KB instruction cache 8KB data cache Integer multiply unit with 133 5M Mul Add sec Upwardly software compatible with IDT RISController Family Easily upgradable to 64 bit system Block Diagram 267 MHz 64 bit CPU High Performance Integer Multiply Pipeline Control Control Bus Instruction Cache Set A Lockable Instruction Cache Set B Low Cost Embedded 64 bit RISController w DSP Capability System Control Coprocessor Address Translation Cache Attribute Control Exception Management Functions Instruction Bus Synchronized System Interface IDT79RC4640 RiSController Low power operation Active power management powers down inactive units Standby mode Large efficient on chip caches Separate 8KB Ins
5. 19 Vcc 51 Vss 83 NMI 115 Int4 20 Vss 52 Vss 84 SysAD23 116 Vcc 21 SysCmd6 53 Vss 85 Release 117 Vss 22 SysAD9 54 SysADC3 86 Vss 118 SysAD1 23 Vcc 55 VccOK 87 Vcc 119 Int5 24 Vss 56 Vss 88 SysAD22 120 SysAD2 25 SysCmd7 57 Vcc 89 Modein 121 Vcc 26 SysAD10 58 SysAD31 90 RdRdy 122 Vss 27 SysCmd8 59 Vss 91 SysAD21 123 SysCmd0 28 Vcc 60 Vcc 92 Vss 124 SysAD3 29 Vss 61 SysAD30 93 Vcc 125 Vcc 30 SysAD11 62 SysAD29 94 ExtRqst 126 Vss 31 SysCmdP 63 Reset 95 SysAD20 127 SysCmd1 32 SysAD12 64 Vss 96 ValidOut 128 SysAD4 22 of 23 December 5 2008 IDT79RC4640 Ordering Information T9 YY XXXX 999 A A Operating Device Speed Package Temp range Voltage Type Process Blank Commercial 0 to 85 Case Industrial 40 C to 85 C Case DU 128 pin PQFP DUG 128 pin PQFP Green DZ 128 pin PQFP 100 100 MHz 133 133 MHz PCIk 150 150 MHz PCIk 180 180 MHz PCIk 200 200 MHz 267 267 MHz PCLK 4640 64 bit processor w DSP Capability R 5 0 5 RV 3 3 5 Valid Combinations 79R4640 100 133MHz DZ T9RV4640 133 150 180 200 267MHz DU T9RV4640 133MHz DUG T9RV4640 133 150 180 200MHz DUI CORPORATE HEADQUARTERS for SALES 6024 Silver Creek Valley Road IDT San Jose CA 95138 PQFP package Commercial Temperature PQFP package Commercial Temperature Green PQFP package Commercial Temperature QFP package Industrial Temperature for Tech Support email
6. Frequency 25 75 25 90 25 100 50 125 MHz MasterClock Period 13 3 40 11 1 40 10 40 8 20 ns Clock Jitter for MasterClock 250 250 250 250 ps MasterClock Rise Time 3 2 5 2 2 ns MasterClock Fall Time 3 2 5 2 2 ns ModeClock Period 256 256 256 256 ns 1 Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled System Interface Parameters RV4640 Vec 3 3V 5 Commercial Tease 0 C to 85 C Industrial Tease 40 C to 85 C 17 of 23 December 5 2008 IDT79RC4640 Note Timings are measured from 1 5V of the clock to 1 5V of the signal RV4640 RV4640 Parameter Symbol Test Conditions 133MHz 150MHz Units Min Max Min Max Data Output tom Min 43 10 fastest 0 9 0 9 ns ipo M 01 sowes 0 12 0 12 ns Data Output Hold 43 10 fastest 0 0 ns Input Data Setup tos trise 51 45 4 5 ns Input Data Hold tou tall 508 15 1 5 ns Capacitive load for all output timings is 50pF 2 50pf loading on external output signals fastest settings RV4640 RV4640 RV4640 Parameter Symbol Test Conditions 180MHz 200MHZ Un
7. and features the same latencies and repeat rates The RC4640 does not directly implement the double precision opera tions found in the RC4700 However to maintain software compatibility the RC4640 will signal a trap when double precision operation is initi ated allowing the requested function to be emulated in software Alter natively the system architect could use a software library emulation of double precision functions selected at compile time to eliminate the overhead associated with trap and emulation Floating Point Units The RC4640 s floating point execution units perform single precision arithmetic as specified in IEEE Standard 754 The execution unit is broken into a separate multiply unit and a combined add convert divide square root unit Overlap of multiply and add subtract is supported The multiplier is partially pipelined allowing a new multiplication instruction to begin every 6 cycles As in the IDT79RC4700 the RC4640 maintains fully precise floating point exceptions while allowing both overlapped and pipelined opera tions Precise exceptions are extremely important in mission critical environments such as ADA and highly desirable for debugging in any environment The floating point units operation set includes floating point add subtract multiply divide square root conversion between fixed point and floating point format conversion among floating point formats and floating point compare These o
8. mode data clock output at the system clock frequency divided by 256 Modeln Input Boot mode data in Serial boot mode data input Int 5 0 Input Interrupt Six general processor interrupts bit wise OR d with bits 5 0 of the interrupt register NMI Input Non maskable interrupt Non maskable interrupt OR d with bit 6 of the interrupt register Absolute Maximum Ratings Note Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability R4640 RV4640 RV4640 Symbol Rating 5 0 5 3 3Vi5 3 3Vi5 Unit Commercial Commercial Industrial VrERM Terminal Voltage with respect to GND 0 51 to 7 0 0 51 to 4 6 0 51 to 4 6 V Tc Operating Temperature case 0 to 85 0 to 85 40 to 85 C TBlAs Case Temperature Under Bias 55 to 125 55to 125 55 to 125 C Storage Temperature 55 to 125 55 to 125 55 to 125 C IN DC Input Current 20 20 20 mA DC Output Current 503 503 503 NVIN minimum 2 0V for pulse width less than 15ns VIN should not exceed VCC 0 5 Volts 2 When VIN lt OV or VIN gt VCC 3 Not more than one output should be s
9. request Signals that the system interface needs to submit an external request Release Output Release interface Signals that the processor is releasing the system interface to slave state RdRdy Input Read Ready Signals that an external agent can now accept a processor read WrRdy Input Write Ready Signals that an external agent can now accept a processor write request ValidIn Input Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus ValidOut Output Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus SysAD 31 0 Input Output System address data bus A 32 bit address and data bus for communication between the processor and an external agent SysADC 3 0 Input Output System address data check bus A 4 bit bus containing parity check bits for the SysAD bus during data bus cycles SysCmd 8 0 Input Output System command data identifier bus A 9 bit bus for command and data identifier transmission between the processor and an external agent SysCmdP Input Output Reserved system command data identifier bus parity For the RC4640 this signal is unused on input and zero on output Clock Control interface MasterClock Input Master clock Master clock input used as the system interface ref
10. rischelp idt com phone 408 284 8208 800 345 7015 or 408 284 8200 fax 408 284 2775 www idt com The IDT logo is a trademark of Integrated Device Technology Inc 23 of 23 December 5 2008
11. used to supply and accept data with DDxxDD data pattern The RC4640 clocking interface allows the CPU to be easily mated with external reference clocks The CPU input clock is the bus reference clock and can be between 50 and 125MHz somewhat dependent on maximum pipeline speed for the CPU An on chip phase locked loop generates the pipeline clock from the system interface clock by multiplying it up an amount selected at system reset Supported multipliers are values 2 through 8 inclusive allowing systems to implement pipeline clocks at significantly higher frequency than the system interface clock System Address Data Bus The 64 bit System Address Data SysAD bus is used to transfer addresses and data between the RC4640 and the rest of the system It is protected with an 8 bit parity check bus SysADC When initialized for 32 bit operation SysAD can be viewed as a 32 bit multiplexed bus with 4 parity check bits The system interface is configurable to allow easier interfacing to memory and systems of varying frequencies The bus frequency and reference timing of the RC4640 are taken from the input clock The rate at which the CPU transmits data to the system interface is program mable via boot time mode control bits The rate at which the processor receives data is fully controlled by the external device Therefore either a low cost interface requiring no read or write buffering or a faster high performance interface can be
12. width caches and bus interface 64 bit architecture and careful attention to efficient control The cost of this performance is reduced by removing functional units frequently not required for many embedded applications The RC4640 supports a wide variety of embedded processor based applications such as internetworking equipment routers switches office automation equipment printers scanners and consumer multi media game systems Also being upwardly software compatible with the RC32300 family as well as bus and upwardly software compatible with the IDT RC4000 family the RC4640 will serve in many of the same applications And the RC4640 supports applications that require integer digital signal processing DSP functions The RC64475 and RC64575 processors offer a direct migration path for designs based on IDT s RC4650 processors through full pin and socket compatibility The RC4640 brings 64 bit performance levels to lower cost systems High performance is preserved by retaining large on chip two way set associative caches a streamlined high speed pipeline high bandwidth 64 bit execution and facilities such as early restart for data cache misses These techniques allow the system designer over 3 2 GB sec aggre gate internal bandwidth 500 MB sec bus bandwidth almost 352 Dhrys tone MIPS 89MFlops and 133 5 M Mul Add sec An array of tools facilitates rapid development of RC4640 based systems allowing a wide variety of c
13. 0 includes an 8KB on chip data cache that is two way set associative with a fixed 32 byte eight words line size Table 4 lists the RC4640 cache attributes Characteristics Instruction Data Size 8KB 8KB Organization 2 way set associative 2 way set associative Line size 32B 32B Index vAddr44 o vAddr44 o Tag pAddra 12 pAddra 12 Write policy n a writeback writethru Line transfer order read sub block order read sub block order write sequential write sequential Miss restart after transfer of entire line first word Parity per word per byte Cache locking set A setA Table 4 RC4640 Cache Attributes The data cache is protected with byte parity and its tag is protected with a single parity bit It is virtually indexed and physically tagged to allow simultaneous address translation and data cache access The normal write policy is writeback which means that a store to a cache line does not immediately cause memory to be updated This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation Software can however select write through for certain address ranges using the CAlg register in CPO Cache protocols supported for the data cache are Uncached Addresses in a memory area indicated as uncached will not be read from the cache Stores to such addresses will be
14. B 0xA0000000 Ox9FFFFFFF Cached kernel physical address space kseg0 Unmapped 0 5GB 0x80000000 Ox7FFFFFF User virtual address space useg Mapped 2 0GB 0x00000000 Figure 1 Mode Virtual Addressing 32 bit mode Virtual to Physical Address Mapping The 4GB virtual address space of the RC4640 is shown in Figure 1 The 4 GB address space is divided into addresses accessible in either kernel or user mode kuseg and addresses only accessible in kernel mode 2 0 The RC4640 supports the use of multiple user tasks sharing common virtual addresses but mapped to separate physical addresses This facility is implemented via the base bounds registers contained in When user virtual address is asserted load store or instruction fetch the RC4640 compares the virtual address with the contents of the appropriate bounds register instruction or data If the virtual 4 of 23 December 5 2008 IDT79RC4640 address is in bounds the value of the corresponding base register is added to the virtual address to form the physical address for that refer ence If the address is not within bounds an exception is signalled This facility enables multiple user processes in a single physical memory without the use of a TLB This type of operation is further supported by a number of development tools for the RC4640 including real time operating systems and position independent code Kernel mode a
15. Parameter Symbol Test Conditions 100MHz 133MHz Units Min Max Min Max Data Output tpo mode4 43 10 Fastest 02 9 02 9 ns modey4 43 11 85 0 0 modey4 43 00 66 0 0 mode44 43 01 slowest 0 12 0 12 ns Data Output Hold mode 13 10 0 0 ns 45 11 0 0 ns mode 00 0 0 ns mode 13 01 0 0 ns Input Data Setup tos trise ONS 5 5 4 5 ns Input Data Hold b ffa Sns 2 E 15 ns E Capacitive load for all output timings is 50pF 2 Guaranteed by design 3 50pf loading on external output signals fastest settings 14 of 23 December 5 2008 IDT79RC4640 Boot time Interface Parameters R4640 5 0 5 TCASE C to 85 Test R4640 100MHz R4640 133MHz Parameter Symbol Conditi Units onditions Min Max Min Max Mode Data Setup tps 3 3 Mode Data Hold 0 0 Master Clock Cycle Capacitive Load Deration R4650 Test 100MHz 133MHz Parameter Symbol Conditi Units onditionS Min Max Min Max Load Derate Cip 2 2 ns 25pF DC Electrical Characteristics Commercial Industrial Temperature Range RV4640 Vec 3 345 Commercial Tease 0 C to 85 C Industrial 40 C to 85 C
16. c operations the logic unit performs all of the logic and shift operations Each unit is highly optimized and can perform an operation in a single pipeline cycle Integer Multiply Divide The RC4640 uses a dedicated integer multiply divide unit optimized for high speed multiply and multiply accumulate operation Table 1 shows the performance expressed in terms of pipeline clocks achieved by the RC4640 integer multiply unit Opcode Latency Repeat Stall MULT U MAD U 16 bit 3 2 0 32 bit 4 3 0 MUL 16 bit 3 2 1 32 bit 4 3 2 DMULT DMULTU any 6 5 0 DIV DIVU any 36 36 0 DDIV DDIVU any 68 68 0 Table 1 RC4640 Integer Multiply Operation 2 of 23 December 5 2008 IDT79RC4640 The MIPS III architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers The values can then be transferred to the general purpose register file using the MFHI MELO instructions The RC4640 adds new multiply instruction MUL which can specify that the multiply results bypass the Lo register and are placed immediately in the primary register file By avoiding the explicit Move from Lo instruction required when using Lo throughput of multiply intensive operations is increased An additional enhancement offered by the RC4640 is an atomic multiply add operation MAD used to perform multiply accumulate operations This instru
17. cted Changes to version dated March 1997 Features Added preliminary 150 MHz operation frequency Thermal Considerations Added thermally enhanced packaging DU and drop in heat spreader information Upgraded 80 to 133MHz speed grade specs to final Changes to version dated May 1997 Features Added 180 MHz spreader information Eliminated 80 MHz Changes to version dated March 1998 Features Added 200MHz operating frequency Changes to version dated April 1998 Features Added 400MB sec bandwidth reference Power Consumption RV4640 Upgraded System Condition Icc active parameters Changes to version dated July 1999 Corrected several incorrect references to tables and figures Changes to version dated March 2000 Replaced existing figure in Mode Configuration Interface Reset Sequence section with 3 reset figures Revised values in System Interface Parameters table Changes to version dated July 2000 Revised package information in the Thermal Considerations section Physical Specifications section Ordering Information section and the Valid Combinations section Changes to version dated April 2001 In the Data Output and Data Output Hold categories of the System Interface Parameters tables changed values in the Min column for all speeds from 1 0 and 2 0 to 0 Changes to version dated June 2006 Added Green PQFP package for 133MHz DUG on Order Page Changes to version da
18. ction multiplies two numbers and adds the product to the current contents of the HI and LO registers This operation is used in numerous DSP algorithms and allows the RC4640 to cost reduce systems requiring a mix of DSP and control functions Finally aggressive implementation techniques feature low latency for these operations along with pipelining to allow new operations to be issued before a previous one has fully completed Table 1 also shows the repeat rate peak issue rate latency and number of processor stalls required for the various operations The RC4640 performs automatic operand size detection to determine the size of the operand and imple ments hardware interlocks to prevent overrun allowing this high perfor mance to be achieved with simple programming Floating Point Coprocessor The RC4640 incorporates an entire single precision floating point coprocessor on chip including a floating point register file and execution units The floating point coprocessor forms a seamless interface with the integer unit decoding and executing instructions in parallel with the integer unit The floating point unit of the RC4640 directly implements single precision floating point operations which enables the RC4640 to perform functions such as graphics rendering without requiring exten sive die area or power consumption The single precision unit of the RC4640 is directly compatible with the single precision operation of the RC4700
19. ddresses do not use the base bounds registers but rather undergo a fixed virtual to physical address translation Debug Support To facilitate software debug the RC4640 adds a pair of watch regis ters to When enabled these registers will cause the CPU to take an exception when a watched address is appropriately accessed Interrupt Vector The RC4640 also adds the capability to speed interrupt exception decoding Unlike the RC4700 which utilizes a single common exception vector for all exception types including interrupts the RC4640 allows kernel software to enable a separate interrupt exception vector When enabled this vector location speeds interrupt processing by allowing software to avoid decoding interrupts from general purpose exceptions Cache Memory To keep the RC4640 s high performance pipeline full and operating efficiently the RC4640 incorporates on chip instruction and data caches that can each be accessed in a single processor cycle Each cache has its own 64 bit data path and can be accessed in parallel The cache subsystem provides the integer and floating point units with an aggre gate bandwidth of over 3200 MB per second at a pipeline clock frequency of 267 MHz The cache subsystem is similar in construction to that found in the RC4700 although some changes have been imple mented Table 4 is an overview of the caches found on the RC4640 Instruction Cache The RC4640 incorporates a two way
20. designed to communicate with the RC4640 Again the system designer has the flexibility to make these price performance trade offs System Command Bus The RC4640 interface has a 9 bit System Command SysCmd bus The command bus indicates whether the SysAD bus carries an address or data If the SysAD carries an address then the SysCmd bus also indicates what type of transaction is to take place for example a read or write If the SysAD carries data then the SysCmd bus also gives information about the data for example this is the last data word trans mitted or the cache state of this data line is clean exclusive The SysCmd bus is bidirectional to support both processor requests and external requests to the RC4640 Processor requests are initiated by the RC4640 and responded to by an external device External requests are issued by an external device and require the RC4640 to respond The RC4640 supports single datum one to eight byte and 8 word block transfers on the SysAD bus In the case of a single datum transfer the low order 3 address bits gives the byte address of the transfer and the SysCmd bus indicates the number of bytes being transferred Handshake Signals There are six handshake signals on the system interface Two of these RdRdy and WrRdy are used by an external device to indicate to the RC4640 whether it can accept a new read or write transaction The RC4640 samples these signals before deasserting the address o
21. e the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations This is known as Standby Mode Entering Standby Mode Executing the WAIT instruction enables interrupts and enters Standby mode When the WAIT instruction finishes the W pipe stage if the SysAd bus is currently idle the internal clocks will shut down thus freezing the pipeline The PLL internal timer and some of the input pins Int 5 0 NMI ExtReq Reset and ColdReset will continue to run Address Boot DRAM ROM 80ns Control lt Z 32 Memory I O gt P Controller RV4640 9 2 gt 2 p lt 7 Figure 2 Typical RC4640 System Architecture 7 of 23 December 5 2008 IDT79RC4640 If the conditions are not correct when the WAIT instruction finishes the W pipe stage i e the SysAd bus is not idle the WAIT is treated as a Once the CPU is in Standby Mode any interrupt including the inter nally generated timer interrupt will cause the CPU to exit Standby Mode Thermal Considerations The RC4640 utilizes special packaging techniques to improve the thermal properties of high speed processors The RV4640 is packaged using cavity up packaging in a 128 pin thermally enhanced PQFP package DU with a drop in heat spreader for devices with low peak power The R4640 utilizes the PQFP package f
22. erence clock All output timings are relative to this input clock Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization VccP Input Quiet VCC for PLL Quiet Vcc for the internal phase locked loop VssP Input Quiet VSS for PLL Quiet Vss for the internal phase locked loop Interrupt interface Int 5 0 Input Interrupt Six general processor interrupts bit wise OR d with bits 5 0 of the interrupt register NMI Input Non maskable interrupt Non maskable interrupt OR d with bit 6 of the interrupt register Initialization interface Vccok Input VCC is OK When asserted this signal indicates to the RC4640 that the power supply has been above Vcc minimum for more than 100 millisec onds and will remain stable The assertion of Vccok initiates the reading of the boot time mode control serial stream 11 of 23 December 5 2008 IDT79RC4640 Pin rr Name Type Description ColdReset Input Cold reset This signal must be asserted for a power on reset or a cold reset ColdReset must be de asserted synchronously with MasterClock Reset Input Reset This signal must be asserted for any reset sequence It may be asserted synchronously or asynchronously for a cold reset or syn chronously to initiate a warm reset Reset must be de asserted synchronously with MasterClock ModeClock Output Boot mode clock Serial boot
23. he processor tristates its drivers and releases the system interface to slave state by asserting Release The external device can then begin sending the data to the RC4640 Fundamental operational modes for the processor are initialized by the boot time mode control interface The boot time mode control inter face is a serial interface operating at a very low frequency MasterClock divided by 256 The low frequency operation allows the initialization information to be kept in a low cost EPROM alternatively the twenty or so bits could be generated by the system interface ASIC or a simple PAL Immediately after the VCCOK Signal is asserted the processor reads a serial bit stream of 256 bits to initialize all fundamental opera tional modes After initialization is complete the processor continues to drive the serial clock output but no further initialization bits are read Boot Time Modes The boot time serial mode stream is defined in Table 6 Bit 0 is the bit presented to the processor when VCCOK is asserted bit 255 is the last Power Management is also used to control the power management for the RC4640 This is the standby mode and it can be used to reduce the power consumption of the internal core of the CPU The standby mode is entered by executing the WAIT instruction with the SysAD bus idle and is exited by any interrupt Standby Mode Operation The RC4640 provides a means to reduc
24. horted at a time Duration of the short should not exceed 30 seconds Recommended Operation Temperature and Supply Voltage 12 of 23 December 5 2008 R4640 RV4640 Grade Temperature GND Vcc Commercial 0 to 85 C Case ov 5 0V 5 3 3 5 Industrial 40 85 Case OV N A 3 3 5 IDT79RC4640 DC Electrical Characteristics Commercial Temperature Range R4640 Voc 5 045 Tease 0 C to 85 C R4640 100MHz R4640 133MHz Parameter Conditions Minimum Maximum Minimum Maximum VoL 0 1V E 0 1V 20uA Vec 0 1V Voc 0 1V VoL 04V 04V 4mA Vou 24V 24V Vi Q 5V 02Vcc 0 5V 0 2Vcc 2 0V Voc 0 5V 2 0V Voc 0 5V lin 10uA 100 0 lt Vin lt Vcc Cw 2 10pF 10pF Cour 10pF 10pF 20uA oa 20uA Input Output Leakage Power Consumption R4640 R4640 100MHz R4640 133MHz Parameter Conditions Typical Max Typical Max System Condition 100 50MHz 133 67MHz loc standby 75 mA 100 mA C OpF m 150 mA 200 mA C 50pF active 700 mA 900 mA 900 mA 950 mA C OpF 64 bit bus No SysAd activity option 800 mA 1000 mA2 1000 mA 1100 mA C 50pF R4x00 compatible writes Tc 25 C 800 mA 1200 mA 1000 mA 1350 C 50pF Pipelined writes or write re issue 25 C
25. ite back If the cache lookup misses then only main memory is written Associated with the Data Cache is the store buffer When the RC4640 executes a Store instruction this single entry buffer gets written with the store data while the tag comparison is performed If the tag matches then the data is written into the Data Cache in the next cycle that the Data Cache is not accessed the next non load cycle The store buffer allows the RC4640 to execute a store every processor cycle and to perform back to back stores without penalty Write Buffer Writes to external memory whether cache miss writebacks or stores to uncached or write through addresses use the on chip write buffer The write buffer holds up to four address and data pairs The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory update System Interface The RC4640 supports a 32 bit system interface that is syntactically compatible with the RC4700 system interface The interface consists of a 32 bit Address Data bus with eight check bits and a 9 bit command bus protected with parity In addition there are eight handshake signals and six interrupt inputs The interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 500MB sec at 125MHz on the bus Figure 2 on page 7 shows a typical system using the RC4640 In this example two banks of DRAMs are
26. its Min Max Min Max Min Max Data Output tow Min mode 13 10 fastest 0 9 0 4 5 0 4 5 ns 14201 lowest 0 10 o 50 50 Data Output Hold toon mode 13 10 fastest 0 0 0 ns Data Input tos trise 3NS 45 4 5 2 5 ns m tan Sns 15 45 9 f 50pf loading on external output signals fastest settings Boot Time Interface Parameters RV4640 Test 133MHz 150MHz 180MHz 200MHz 267MHz Parameter Symbol Conditi Units Conditions oneruonS Min Max Min Min Min Min Max Mode Data tos 3 3 3 3 3 ns Master Clock Setup Cycle Mode Data 0 0 0 0 0 ns Master Clock Hold Cycle Capacitive Load Deration RV4640 133MHz 150MHz 180MHz 200MHz 267MHz Test Parameter Symbol Conditions Units Min Max Min Min Min Max Min Max Load Derate Cip 2 2 2 2 1 ns 25pF 18 of 23 December 5 2008 IDT79RC4640 Timing Characteristics RV4640 Cycle 1 2 MasterClock Iucke mene pega pex ue A 3 dx tbo SysAD SysCmd Received SysADC 5 Y BEL BEL c T 1 d4 gt lt DM eee ees gt lt DM Control Signal CPU driven i 1 i i i 1 1 1 1 1 n i i i D
27. mA2 550mA 50pF R4x00 compatible writes option Tc 25 C 500 2 575mA 550 2 625mA 50pF Pipelined writes or Write re issue 25963 E Typical integer instruction mix and cache miss rates Vcc 3 3V TA 25xC These are not tested They are the result of engineering analysis and are provided for reference only 3 Guaranteed by design 4 These are the specifications IDT tests to insure compliance RV4640 180MHz RV4640 200MHz RV4640 267MHz Parameter Conditions Typical Max Typical Max Typical Max System Condition 180 60MHz 200 67MHz 267 89MHz standby 60mA 60mA 60mA C 110m 110m 110mA C 50 active 610 mA 680mA 685mA 760 650mA 800mA OpF No SysAd activity 750mA 760mA2 835mA 750 2 900mA 50pF R4x00 compatible writes option Ere Te 25 C 750mA 850mA 835 2 950 900 2 1200mA 50pF Pipelined writes or Write re issue Tc 25 C Typical integer instruction mix and cache miss rates Vcc 3 3V TA 25 These are not tested They are the result of engineering analysis and are provided for reference only 3 Guaranteed by design These are the specifications IDT tests to insure compliance 16 of 23 December 5 2008 IDT79RC4640 AC Electrical Characteristics Commercial I
28. mum Icc specification for the device Typical values for at various air flows are shown Table 5 OCA Airflow ft min O 200 400 600 800 1000 128 PQFP DU 17 9 7 5 4 3 128 PQFP DZ 20 12 9 5 8 7 6 5 Table 5 Thermal Resistance at Various Airflows Note that the RC4640 implements advanced power management to substantially reduce the average power dissipation of the device This operation is described in the IDT79RC4640 IDT79RC4650 RISC Processor Hardware User s Manual MasterClock Y SysAD X Addr X Data X Data1 X 1 X Datas X Data7 X SysCmd X Read 4 CData X CData X X CEOD X ValidOut f RdRdy HUM PIE WrRdy Figure 3 RC4640 Block Read Request 8 of 23 December 5 2008 IDT79RC4640 Data Sheet Revision History Changes to version dated December 1995 Features Added 32 bit bus interface info Deleted items from low power operation descriptions Hardware Overview Added detailed descriptions of features Changed Boot Time Mode Stream table values for mode bit 12 DC Electrical Characteristics The Cy and values have been changed AC Electrical Characteristics n System Interface Parameters tables RC4640 and RV4640 Data Setup and Data Hold minimums changed Valid Combinations List of valid combinations has been corre
29. n read and write requests The following is a list of the supported external requests Read Response Null 6 of 23 December 5 2008 IDT79RC4640 Boot Time Options ExtRqst and Release are used to transfer control of the SysAD and SysCmd buses between the processor and an external device When an external device needs to control the interface it asserts ExtRqst The RC4640 responds by asserting Release to release the system interface to slave state ValidOut and Validln are used by the RC4640 and the external device respectively to indicate that there is a valid command or data on the SysAD and SysCmd buses The RC4640 asserts ValidOut when it is driving these buses with a valid command or data and the external device drives ValidIn when it has control of the buses and is driving valid command or data Non overlapping System Interface The RC4640 requires a non overlapping system interface compat ible with the RC4700 This means that only one processor request may be outstanding at a time and that the request must be serviced by an external device before the RC4640 issues another request The RC4640 can issue read and write requests to an external device and an external device can issue read and write requests to the RC4640 The RC4640 asserts ValidOut and simultaneously drives the address and read command on the SysAD and SysCmd buses If the system interface has RdRdy or Read transactions asserted then t
30. ndustrial Temperature Range RV4640 Vec 3 3V 5 Commercial Tease 0 C to 85 C Industrial Tc Asc 40 C to 85 C Clock Parameters RV4640 Note Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled RV4640 Parameter Symbol Test Conditions oe Units Min Max Pipeline clock Frequency 50 133 MHz MasterClock HIGH Transition lt tycrise Fall 9 ns MasterClock LOW tucLow Transition lt tycrise Fall 3 ns MasterClock Frequency 25 67 MHz MasterClock Period 15 40 ns Clock Jitter for MasterClock 250 ps MasterClock Rise Time 4 ns MasterClock Fall Time 4 ns ModeClock Period tModecKP 256 ns 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability RV4640 RV4640 RV4640 RV4640 Parameter 150MHz 180MHz 200MHz 267MHz Units Min Max Min Max Min Max Min Max Pipeline clock Frequency 50 150 50 180 50 200 100 267 MHz MasterClock HIGH 3 3 3 3 ns MasterClock LOW 3 3 3 3 ns MasterClock
31. nstruction set architecture addition MIPS III specifies new instructions defined to take advantage of the 64 bit archi tecture of the processor Finally the RC4640 also implements additional instructions which are considered extensions to the MIPS III architecture These instruc tions improve the multiply and multiply add throughput of the CPU making it well suited to a wide variety of imaging and DSP applications These extensions which use opcodes allocated by MIPS Technologies for this purpose are supported by a wide variety of development tools The MIPS integer unit implements a load store architecture with single cycle ALU operations logical shift add sub and autonomous multiply divide unit The 64 bit register resources include 32 general purpose orthogonal integer registers the HI LO result registers for the integer multiply divide unit and the program counter In addition the on chip floating point co processor adds 32 floating point registers and a floating point control status register Register File The RC4640 has 32 general purpose 64 bit registers These regis ters are used for scalar integer operations and address calculation The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline Arithmetic Logic Unit The RC4640 ALU consists of the integer adder and logic unit The adder performs address calculations in addition to arithmeti
32. odeClock ColdReset _ TDS e TDS gt Reset gt 64 cycles Figure 8 Warm Reset 20 of 23 December 5 2008 IDT79RC4640 Physical Specifications 128 Pin PQFP i cl ND El Max em DIMENSIONS ARE IN MILLIMETERS ss sse Jus eed o so as 80 BSC 20 REF 21 of 23 December 5 2008 RC4640 Package Pin Out N C pins should be left floating for maximum flexibility as well as for compatibility with future designs An asterisk identifies a pin that is active when low Pin Function Pin Function Pin Function Pin Function 1 N C 33 Vcc 65 Vcc 97 Vec 2 SysCmd2 34 Vss 66 SysAD28 98 Vss 3 Vcc 35 SysAD13 67 ColdReset 99 SysAD19 4 Vss 36 SysAD14 68 SysAD27 100 Validin 5 SysAD5 37 Vss 69 Vss 101 Vcc 6 WrRdy 38 Vcc 70 Vcc 102 Vss 7 ModeClock 39 SysAD15 71 N C 103 SysAD18 8 SysAD6 40 Vss 72 SysAD26 104 IntO 9 Vcc 41 Vcc T3 N C 105 SysAD17 10 Vss 42 SysADC1 74 Vss 106 Vcc 11 SysCmd3 43 Vss 75 Vcc 107 Vss 12 SysAD7 44 Vcc 76 SysAD25 108 Int1 13 SysCmd4 45 MasterClock TT Vss 109 SysAD16 14 Vcc 46 VssP 78 Vcc 110 Int2 15 Vss 47 VccP 79 SysAD24 111 Vcc 16 SysADCO 48 Vss 80 SysADC2 112 Vss 17 SysCmd5 49 Vss 81 Vss 113 Int3 18 SysAD8 50 Vss 82 Vcc 114 SysADO
33. or higher power consumption devices the DZ package which is an all aluminum package with the die attached to a normal copper lead frame mounted to the aluminum casing Due to the heat spreading effect of the aluminum the PQFP package allows for an efficient thermal transfer between the die and the case The aluminum offers less internal resistance from one end of the package to the other reducing the temperature gradient across the package and therefore presenting a greater area for convection and conduction to the PCB for a given temperature Even nominal amounts of air flow will dramatically reduce the junction temperature of the die resulting in cooler operation The PQFP package is pin and socket compatible with the 128 pin QFP package The R4640 and the RV4640 are guaranteed in a case temperature range of 0 to 85 for commercial temperature parts and the RV4640 in a case temperature range of 40 C to 85 C for industrial temperature parts The type of package speed power of the device and air flow conditions affect the equivalent ambient temperature condi tions that will meet this specification The equivalent allowable ambient temperature TA can be calculated using the thermal resistance from case to ambient Oca of the given package The following equation relates ambient and case tempera tures TC P CA where P is the maximum power consumption at hot temperature calculated by using the maxi
34. perations comply with IEEE Standard 754 Double precision operations are not directly supported attempts to execute double precision floating point operations or refer directly to double precision registers result in the RC4640 signalling a trap to the CPU enabling emulation of the requested function Table 2 gives the latencies of some of the floating point instructions in internal processor cycles Operation Instruction Latency ADD 4 SUB 4 MUL 8 DIV 32 SQRT 31 CMP 3 FIX 4 FLOAT 6 ABS 1 MOV 1 NEG 1 LWC1 2 SWC1 1 Table 2 Floating Point Operation Floating Point General Register File The floating point register file is made up of thirty two 32 bit regis ters These registers are used as source or target registers for the single precision operations References to these registers as 64 bit registers as supported in the RC4700 will cause a trap to be signalled to the integer unit The floating point control register space contains two registers one for determining configuration and revision information for the copro cessor and one for control and status information These are primarily involved with diagnostic software exception handling state saving and restoring and control of rounding modes 3 of 23 December 5 2008 IDT79RC4640 System Control Coprocessor CPO The system control coprocessor in the MIPS architecture is respon sible for the vi
35. rtual to physical address translation and cache protocols the exception control system and the diagnostics capability of the processor In the MIPS architecture the system control coprocessor and thus the kernel software is implementation dependent In the RC4640 significant changes in CPO relative to the RC4600 have been implemented These changes are designed to simplify memory management facilitate debug and speed real time processing System Control Coprocessor Registers The RC4640 incorporates all system control co processor registers on chip These registers provide the path through which the virtual memory system s address translation is controlled exceptions are handled and operating modes are controlled kernel vs user mode interrupts enabled or disabled cache features In addition the RC4640 includes registers to implement a real time cycle counting facility which aids in cache diagnostic testing assists in data error detection and facil itates software debug Alternatively this timer can be used as the operating system reference timer and can signal a periodic interrupt Table 3 shows the CPO registers of the RC4640 Number Name Function 0 IBase Instruction address space base 1 IBound Instruction address space bound 2 DBase Data address space base 3 DBound Data address space bound 4 7 10 20 25 Not used 29 31 8 BadVAddr Virt
36. set associative on chip instruc tion cache This virtually indexed physically tagged cache is 8KB in size and is parity protected Because the cache is virtually indexed the virtual to physical address translation occurs in parallel with the cache access thus further increasing performance by allowing these two operations to occur simul taneously The tag holds a 20 bit physical address and valid bit and is parity protected The instruction cache is 64 bits wide and can be refilled or accessed in a single processor cycle Instruction fetches require only 32 bits per cycle for a peak instruction bandwidth of 1068MB sec at 267MHz Sequential accesses take advantage of the 64 bit fetch to reduce power dissipation and cache miss refill can write 64 bits per cycle to minimize the cache miss penalty The line size is eight instructions 32 bytes to maximize performance In addition the contents of one set of the instruction cache set A can be locked by setting a bit in a CPO register Locking the set prevents its contents from being overwritten by a subsequent cache miss refill occurs then only into set B This operation effectively locks time critical code into one 4 set while allowing the other set to service other instruction streams in a normal fashion Thus the benefits of cached performance are achieved while deterministic real time response is preserved Data Cache For fast single cycle data access the RC464
37. ted December 2008 Removed IDT from ordering codes on Ordering Information page MasterClock Addr Datao Datat X 1 SysAD d Data6 X Data7 X SysCmd K Write bi CData K CData X T 7 x CData CEOD Y ValidOut N Validin Y RdRdy WrRdy Release Figure 4 RC4640 Block Write Request 9 of 23 December 5 2008 IDT79RC4640 Mode bit Description 0 Reserved must be zero 4s 1 Writeback data rate 32 bit 0 0 19 WWx 2 gt WWxx 3 gt WxWx 4 gt WWxxx 5 WWxxxx 6 WxxWxx 7 WWxxxxxx 8 gt WxxxWxxx 9 15 reserved 7 5 Clock multiplier 022 123 24 335 456 5 7 68 7 reserved 8 0 2 Little endian 1 2 Big endian 10 9 00 R4000 compatible 01 reserved 10 2 pipelined writes 11 write re issue 11 Disable the timer interrupt on Int 5 12 Must be 1 14 13 Output driver strength 10 100 strength fastest 11 83 strength 00 67 strength 01 50 strength slowest 255 15 Must be zero Table 6 Boot time mode stream 10 of 23 December 5 2008 IDT79RC4640 Pin Description The following is a list of interface interrupt and miscellaneous pins available on the RC4640 Pin names ending with an asterisk identify pins that are active when low Pin Name Type Description System Bus Interface ExtRqst Input External
38. truction and 8KB Data caches Over 3200MB sec bandwidth from internal caches 2 set associative Write back and write through support Cache locking to facilitate deterministic response High performance write protocols for graphics and data communications Bus compatible with RC4000 family System interfaces to 125MHz provides bandwidth up to 500 MB sec Direct interface to 32 bit wide systems Synchronized to external reference clock for multi master operation Socket compatible with IDT RC 64474 and RC64574 Improved real time support Fast interrupt decode Optional cache locking Note R refers to 5V parts RV refers to 3 3V parts RC refers to both 89 MFlops Single Precision FPA FP Register File Pack Unpack FP Add Sub Cvt Div Sqrt FP Multiply Pipeline Control Data Bus Data Cache Set A Lockable Data Cache Set B The IDT logo is a trademark and RC4600 RC4650 RC3081 RC3052 RC3051 RC3041 RISController and RISCore are trademarks of Integrated Device Technology Inc 1 of 23 2008 Integrated Device Technology Inc December 5 2008 DSC 3486 2 IDT79RC4640 Description The IDT79RC4640 is a low cost member of the Integrated Device Technology Inc RC4000 family targeted to a variety of performance hungry embedded applications The RC4640 continues the RC4000 tradition of high performance through high speed pipelines high band
39. ual address on address exceptions 9 Count Counts every other cycle 11 Compare Generate interrupt when Count Compare 12 Status Miscellaneous control status 13 Cause Exception Interrupt information 14 EPC Exception PC 15 PRId Processor ID 16 Config Cache and system attributes 17 CAlg Cache attributes for the 8 512MB regions of the virtual address space 18 IWatch Instruction breakpoint virtual address 19 DWatch Data breakpoint virtual address 26 ECC Used in cache diagnostics 27 CacheErr Cache diagnostic information 28 TagLo Cache index information 30 ErrorEPC CacheError exception PC Table 3 RC4640 CPO Registers Operation Modes The RC4640 supports two modes of operation user mode and kernel mode Kernel mode operation is typically used for exception handling and operating system kernel functions including manage ment and access to IO devices In kernel mode software has access to the entire address space and all of the co processor 0 registers and can select whether to enable co processor 1 accesses The processor enters kernel mode at reset and whenever an exception is recognized User mode is typically used for applications programs User mode accesses are limited to a subset of the virtual address space and can be inhibited from accessing CPO functions OxFFFFFFFF Kernel virtual address space kseg2 Unmapped 1 0 GB 0xC0000000 OxBFFFFFFF Uncached kernel physical address space 1 Unmapped 0 5G
40. ustomers access to the processor s high performance capabilities while maintaining short time to market goals Hardware Overview Some key elements of the RC4640 are briefly described below More detailed information is available in the DT79RC4640 IDT79RC4650 RISC Processor Hardware User s Manual Pipeline The RC4640 uses a 5 stage pipeline that is similar to the IDT79RC3000 and the IDT79RC4700 processors The simplicity of this pipeline allows the RC4640 to cost less than super scalar processors and require less power than super pipelined processors So unlike superscalar processors applications that have large data dependen cies or require frequent load stores can still achieve peak performance Integer Execution Engine The RC4640 implements the MIPS III Instruction Set Architecture and is fully upward compatible with applications that run on earlier generation parts The RC4640 is software compatible with the RC4650 and includes the instruction set found in the RC4700 microprocessor targeted at higher performance while maintaining binary compatibility with RC32300 processors The extensions result in better code density greater multi processing support improved performance for commonly used code sequences in operating system kernels and faster execution of floating point intensive applications All resource dependencies are made trans parent to the programmer insuring transportability among implementa tions of the MIPS i
41. written directly to main memory without changing cache contents Writeback Loads and instruction fetches will first search the cache reading main memory only if the desired data is not cache resident On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache con 5 of 23 December 5 2008 IDT79RC4640 tents will be updated and the cache line marked for later write back If the cache lookup misses the target line is first brought into the cache before the cache is updated Write through with write allocate Loads and instruction fetches will first search the cache reading main memory only if the desired data is not cache resident On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache con tents will be updated and main memory will also be written the state of the writeback bit of the cache line will be unchanged If the cache lookup misses the target line is first brought into the cache before the cache is updated Write through without write allocate Loads and instruction fetches will first search the cache reading main memory only if the desired data is not cache resident On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache con tents will be updated and the cache line marked for later wr
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