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1. A VMEbus Adapter for G 64 by J Niewold L Arnaudon C Parkman and M Saich CERN 1211 Geneva 23 Switzerland D ECP Division SL Division ABSTRACT The limited address space of the G64 bus poses problems in an increasing number of applications particularly for the use of the modern high level communications protocols Whilst the replacement of G 64 by single height VMEbus systems would provide a long term answer to its technical limitations an adapter permitting a limited number of single height VMEbus modules to be inserted into an existing G64 system supplies an interim solution This paper describes such an adapter which provides up to three VMEbus slots for the G 64 crates in the Aleph experiment s control system at CERN together wih a brief description of the OS 9 software environment INTRODUCTION The provision of modern communications in systems based on the G 64 1 backplane bus has proved to be difficult owing in part to its restricted address space Whilst its total replacement by single height 3U VMEbus 2 could provide a radical long term solution to the deficiencies of G 64 the use of an adapter to permit the insertion of a limited number of single height VMEbus modules into an existing G 64 system provides a less costly interim solution The development of such an adapter is under way for the Aleph 3 controls system at CERN and will provide 2 or 3 slots of VMEbus in their existing G642. Mbytes of dynamic memory maximum 8 Mbytes 2 RS232 serial ports and 512 Kbytes of EPROM maximum 2 Mbytes 2 VLAN Ethernet controller 7 Am7990 LANCE controller with an on board MC68000 processor SOFTWARE amp SYSTEM ASPECTS The existing G 64 crates in Aleph are networked together with UTINET 8 and controlled by Motorola M6809 microprocessors with code programmed in EPROM Communication with controlling tasks on the main Aleph computers passes through UTINET Ethernet gateways and a central server task This has resulted in performance problems due to the communications bottlenecks at the gateways and the server task and the inflexibility of having the code controlling and monitoring the hardware in EPROM The use of the VMEbus G 64 adapter permits all crates to be networked together through Ethernet and to run the OS9 operating system This gives direct communication from controlling tasks on the central machines to monitoring and control programs running on the VMEbus based MC68020 microprocessor using the TCP IP 9 package Programming is much simplified as code can be written in C and debugged directly on the hardware it is acting on Monitoring information can be stored on the microprocessor as data modules and accessed directly over the network A considerable advantage is also gained in that use of the semaphore facility of OS 9 allows different programs to share a single resource It is therefore possible to have sev
3. atus id vector chosen by means of user selected jumpers The interrupter circuits are based on a VME3000 device from PLX Corporation 4 which is fully compatible with the TEEE1014 1987 VMEbus specification Address Mapping The G 64 VPA address space of 1Kbyte is mapped into VMEbus standard space but occupies 64Kbytes owing to the use of implicit decoding This corresponds to address modifier codes 39 3A 3D 3E The base address of the G64 space may be set to any legal 64Kbyte boundary depending on the requirements of the VMEbus master The VMEbus address and address modifier decoding is performed in a PAL and may easily be reprogrammed Data The VMEbus data lines DOO DO7 and D08 D15 are multiplexed onto the G 64 s DO D7 lines with the necessary logical inversion G 64 data is negative true VMEbus is positive true The G 64 D8 D15 lines are not used The adapter assures the generation of the G64 AO line and requires the VMEbus master to access G64 with D08 O or D08 EO cycles only Reset The VMEbus SYSRESET line directly drives the G64 RST line VMEbus MODULES The Aleph application requires the installation of a CPU capable of running the OS 9 5 real time operating system and a thin wire Ethernet connection 3U VMEbus modules from PEP Modular Computers GmbH have been chosen for this initial application having the following configurations 1 VM20 CPU Module 6 MC68020 MC68882 CPU module equipped with 4
4. crates which will continue to be used otherwise unaltered for input output functions MECHANICAL LAYOUT The VMEbus G 64 adapter allows the insertion of up to three single height VMEbus modules into a G64 crate The VMEbus part consists of an independent plug in mechanical housing cassette which requires no modification to existing G 64 crates Figure 1 Two versions will be available with two and three VMEbus slots respectively The insertion of the cassette into the extreme left or right hand positions of the G 64 crate implies the loss of one G 64 elsewhere two slots will be lost Hence the version with three VMEbus slots will normally require the use of four G 64 slots and that with two VMEbus slots three G64 slots The implementation of the protocol adaptation logic and power connections is on two spacer modules Figure 1 These modules fit between the G 64 s 64 pin DIN connector and the rear of a slightly special VMEbus backplane carrying 96 pin connectors on the rear of each of the extreme slots One spacer carries all the necessary logic implemented using surface mounted components to save space the other an identical but unmounted printed circuit carries only power connections Figure 1 Mechanical layout not to scale schematic only The otherwise standard VMEbus backplane is reduced in height to that of a G 64 module 100mm so that it may fit between the modul
5. e guides of the G 64 crate The entire assembly of mechanical housing VMEbus backplane and adapter modules adapter logic and power connections is one mechanical part which is inserted as one part into the G 64 crate Screw fixings are provided in the manner of a normal module ADAPTER LOGIC Data transfer The adapter allows the VMEbus master to generate G64 VPA input output cycles only Thus access to G64 memory from the VMEbus master is not possible neither is access to VMEbus from a G 64 master The adapter transforms the asynchronous VMEbus cycles into synchronous G 64 cycles and provides a 1MHz clock on the G 64 Enable line A block diagram is given in Figure 2 Figure 2 Adapter block diagram A VMEbus master read cycle is shown in Figure 3 Following a successful decoding of the address and address modifier lines the receipt of either of the VMEbus data strobes DSO or DS1 by the adapter will provoke a G64 data read On the negative going edge of the next 1MHz clock cycle the data will be latched in the adapter and DTACK asserted on the VMEbus Recognition of the release of the VMEbus data strobes will signal the termination of the read cycle by the VMEbus master a eee ea E a Figure 3 Read cycle Interrupts One of the three G 64 interrupt lines NMI IRQ or FIRQ may be patched into a VMEbus interrupter in the adapter This in turn may be patched onto any of the seven VMEbus interrupt lines with a st
6. eral programs running on the microprocessor and accessing the G 64 address space giving greater flexibility to the programmer For example the functions of monitoring and control can be separated The G 64 hardware configuration is determined at boot time from a scan of the backplane and parameters for monitoring are downloaded in the form of data modules from a central database ACKNOWLEDGEMENTS In the design of the VMEbus G 64 Adapter the concept of an independent mechanical housing came from conversations with Jean Zaslavsky CERN ECP Division REFERENCES G 64 and G 96 Specifications Manual 1984 Gespac SA Geneva Switzerland VMEbus Specification IEEE1014 1987 ALEPH Collaboration D Decamp et al Nuclear Instruments and Methods A 294 1990 121 VME3000 VMEbus Interrupt Generator data sheet January 1989 PLX Technology Mountain View California USA OS 9 Technical Manual Microware Systems Corporation Des Moines Iowa USA VM20 68020 Micro Processor Module for the VMEbus User s Manual PEP Modular Computers GmbH VLAN Ethernet 802 3 Cheapernet Controller User s Networker s Manual PEP Modular Computers GmbH The UTI NET Book A K Barlow et al CERN SPS ACC Technical Note 84 1 Using OS 9 Internet Microware Corporation Des Moines Iowa USA
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