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RL78/G12 Data Sheet - Renesas Electronics

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1. RO1DS0193EJ0200 Rev 2 00 Page 57 of 106 se 2010 RENESAS _ RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 85 C Vepr lt Von lt 5 5 V Vss 0 V lt R gt Parameter Conditions Detection supply voltage Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time LIISIS SSIS S SSIS SISI SISI SSIS SSIS Power supply fall time Minimum pulse width Detection delay time RO1DS0193EJ0200 Rev 2 00 Page 58 of 106 se 2010 RENESAS _ RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt LVD detection voltage of interrupt amp reset mode Ta 40 to 85 C Vepr lt Voo lt 5 5 V Vss 0 V Interrupt and reset Vivogo Vrocz Vroc1 Vroco 0 0 1 fa
2. P60 P61 4 0 V lt Voo lt 5 5 V lout 15 0 mA 4 0V lt Vp0 lt 5 5 V lot1 5 0 mA 2 7 V lt Von lt 5 5 V lott 3 0 mA 1 8 V lt Voo lt 5 5 V lott 2 0 mA P121 P122 Vi Voo Input port or external X1 X2 EXCLK clock input When resonator 10 LA connected Other than P121 Vi Vss 1 HA P122 P121 P122 Vi Vss Input port or external 1 LA X1 X2 EXCLK clock input When resonator 10 LA connected 20 24 pin products Vi Vss input port 10 20 100 kQ P00 to PO3 P10 to P14 P40 to P42 P125 RESET 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 22 of 106 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 3 2 Supply current characteristics 1 20 24 pin products Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 1 2 Supply loo1 Operating HS High speed fix 24 MHz Pan ene 18 mA current main mode 4 operation lvo 30v fas v v 28 ar LS Low speed fin 8 MHz Voo 3 0 V Jaz 18 mA mA Note 4 main mode Voo 2 0 V HS High speed fmx 20 MH2 Square wave input p Note4 main mode Voo 5 0 V Resonator connection fux 20 MH2 Square wave input Voo 3 0 V Resonator connectio
3. 2 7 V lt V b lt 4 0 V Theoretical value of the maximum transfer rate C 50 pF Rb 1 4 KQ Vb 2 7 V 2 7 V lt Voo lt 4 0 V 2 3 V lt V lt 2 7 V Theoretical value of the maximum transfer rate C 50 pF Rb 2 7 KQ Vb 2 3 V 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V Theoretical value of the maximum transfer rate C 50 pF R 5 5 KQ Vb 1 6 V lt R gt Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only lt R gt 2 Use it with Voo gt Vb lt R gt 3 The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 24 MHz 2 7 V lt Voo lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V LS low speed main mode 8 MHz 1 8 V lt Voo lt 5 5 V lt R gt 4 The smaller maximum transfer rate derived by using fmc K 6 or the following expression is the valid fmck 6 fmck 6 bps Notes1 2 Notes1 2 o 3 a maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt Voo lt 5 5 V and 2 7 V lt Vb lt 4 0 V 1 Maximun transfer rate 22 bps Cb x Rb x In 1 Vb yx 3 1 2 2 Transfer rate x 2 pape Rex In 1 7 1 Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides RO1DS0193EJ0200 Rev 2 00 Page 38 of 106 Sep 0 201 RENESAS _ RL78 G12 2
4. 80 and lot 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 4 24 pin products only Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Page 20 of 106 Sep 06 2013 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 3 4 Input voltage high Normal input buffer 0 8Vpp Voo V 20 24 pin products P00 to PO3 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 20 24 pin products P10 P11 3 3 V lt Voo lt 4 0 V 20 vo ve DD V 30 pin products P01 P10 1 8 V lt Voo lt 3 3 V 1 5 Vi P11 P13 to P17 Input voltage low Normal input buffer 20 24 pin products POO to PO3 P10 to P14 P40 to P42 30 pin products P00 P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 20 24 pin products P10 P11 3 3V lt Vo lt 40v o los v 30 pin products P01 P10 1 8 V lt Voo lt 3 3 V 0 32 V P11 P13 to P17 V P121 P122 p125 1 P137 EXCLK RESET o Joxo v 20 24 pin products 4 0 V lt V lt 5 5V Voo 1 5 V POO to P03 e P10 to P14 lom 10 0 mA P40 t
5. Integral linearity error Add 0 5 LSB to the MAX value when reference voltage AVrerm Differential linearity error Add 0 2 LSB to the MAX value when reference voltage AVRerm RO1DS0193EJ0200 Rev 2 00 Page 56 of 106 see 2010 RENESAS _ RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 6 2 Temperature sensor internal reference voltage characteristics Ta 40 to 85 C 2 4 V lt Von lt 5 5 V Vss 0 V HS high speed main mode lt R gt Parameter Conditions Temperature sensor output voltage Vimes25 Setting ADS register 80H TA 25 C Internal reference voltage VBcR Setting ADS register 81H Temperature coefficient Fyvtmps Temperature sensor output voltage that depends on the temperature Operation stabilization wait time 2 6 3 POR circuit characteristics Ta 40 to 85 C Vss 0 V lt R gt Parameter Conditions Detection voltage Power supply rise time Power supply fall time Minimum pulse width lt R gt Note Minimum time required for a POR reset when Voo exceeds below Veror This is also the minimum time required for a POR reset from when Voo exceeds below 0 7 V to when Voo exceeds Vror while STOP mode is entered or the main system clock is stopped through setting bit O HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC Supply voltage Vpp Vppr or 0 7 V
6. 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 Use it with Voo Vb lt R gt Cautions 1 Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For V and Vi see the DC characteristics with TTL input buffer selected 2 CSI01 and CSI11 cannot communicate at different potential Remarks 1 R Q Communication line SCKp SOp pull up resistance Cb F Communication line SCKp SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 CSI mode connection diagram during communication at different potential lt Master gt RL78 microcontroller User s device RO1DS0193EJ0200 Rev 2 00 Page 45 of 106 Sep 06 2013 RENESAS z RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy1 tki tkHi SCKp SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 SCKp SOp Output data RO1DS0193EJ0200 Rev 2 00 Page 46 of 106 Sep 06 2013 REN
7. 3 6 5 Power supply voltage rising slope characteristics Ta 40 to 105 C Vss 0 V Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 3 4 AC Characteristics RO1DS0193EJ0200 Rev 2 00 Page 101 of 106 see 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 105 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is affected but data is not retained when a POR reset is affected l STOP mode Operation mode Data retention mode gt Voo 4 STOP instruction execution Standby release signal interrupt request 3 8 Flash Memory Programming Characteristics Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions System clock frequency Code flash memory rewritable times Retained for 20 years Notes 1 2 3 Data flash memory rewritable times Retained for 1 year 1 000 000 Notes 1 2 3 Retained for 5 years 100 000 Retained for 20 years 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When usi
8. 85 C 5 0 5 0 oscillator oscillation frequency accuracy 1 3 3 Peripheral Functions The following are differences in peripheral functions between the R5F102 products and the R5F103 products R5F102 product R5F103 product RL78 G12 20 24 pin 30 pin product 20 24 pin 30 pin product product product Serial interface UART 1 channel 3 channels 1 channel CSI 2 channels 3 channels 1 channel Simplified C 2 channels 3 channels None DMA function 2 channels None Safety function CRC operation Yes None RAM guard Yes None SFR guard Yes None RO1DS0193EJ0200 Rev 2 00 Page 6 of 106 se 2010 RENESAS _ RL78 G12 1 OUTLINE 1 4 Pin Configuration Top View 1 4 1 20 pin products lt R gt e 20 pin plastic LSSOP 4 4 x 6 5 mm 0 65 mm pitch P20 ANIO AVreFP O P42 ANI21 SCKO1 SCLO1 T103 TOO3 O P41 ANI22 SO01N YSDA01 T102 TOO2 INTP1 O P40 KRO TOOLO O P125 KR1 SI01N RESET O P137 INTPO O P122 KR2 X2 EXCLK TI02 INTP2 O P121 KR3 X1 TI03 INTP3 O Vss O Voo O O P21 ANI1 AV reFm O P10 ANI16 PCLBUZ0 SCK00 SCLOON O P11 ANI17 S100 RxD0 SDA00 TOOLRxD O P12 ANI18 S000 TxDO0O TOOLTxD O P13 ANI19 TI00 TOOO INTP2 O P14 ANI20 T101 TO01 INTP3 O P61 KR5 SDAA0 RxD0 O P60 KR4 SCLA0 TxD0 Note Provided only in the R5F102 products Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure ca
9. ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 5 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer The smaller maximum transfer rate derived by using fuck 6 or the following expression is the valid maximum transfer rate lt R gt 6 Expression for calculating the transfer rate when 2 7 V lt Voo lt 4 0 V and 2 3 V lt V lt 2 7 V 1 Maximun transfer rate bps 2 0 Cb x Rb x In 1 7 3 1 2 0 Transfer rate x2 Cb Ro x In 1 7 x 100 Fransfer rate x Number of transferred bits Baud rate error theoretical value This value is the theoretical value of the relative difference between the transmission and reception sides This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer The smaller maximum transfer rate derived by using fmck 6 or the following expression is the valid maximum transfer rate lt R gt 7 lt R gt 8 Expression for calculating the transfer rate when 1 8 V lt Voo lt 3 3V 1 6V lt Vb lt 2 0V 1 Maximum transfer rate bps 1 5 Cb x Rb x In 1 Vb jy x 3 1 1 5 Transfer rate x 2 Cb x Rb x In a 7 x 100 Transfer rate x Number
10. Maximun transfer rate bps 2 0 Cb x Rb x In 1 7 3 1 2 0 Transfer rate x2 CC Rb x In 1 yp Baud rate error theoretical value 4 a a 100 Fransfer rate x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 6 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer 7 The smaller maximum transfer rate derived by using fmck 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 4 V lt Voo lt 3 3 V 1 6 V lt V lt 2 0 V 1 Maximun transfer rate 15 bps Cb x Rb x In 1 Vb yy x 3 1 1 5 Transfer rate x 2 Cb Rb ine Baud rate error theoretical value DE Aaa i 100 x Number of transferred bits Transfer rate This value is the theoretical value of the relative difference between the transmission and reception sides 8 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance mode for the TxDq pin by using port input mode register g
11. P01 P40 P120 20 24 pin products POO to PO3 5 100 mA P10 to P14 30 pin products P10 to P17 P30 P31 P50 P51 P147 lon2 Per pin P20 to P23 0 5 mA Total of all pins 2 mA Output current low lout Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20 24 pin products P40 to P42 70 mA 30 pin products POO P01 P40 P120 20 24 pin products POO to P03 100 mA P10 to P14 P60 P61 30 pin products P10 to P17 P30 P31 P50 P51 P60 P61 P147 love Per pin P20 to P23 1 mA Total of all pins 5 mA Operating ambient TA 40 to 85 C temperature Storage temperature Tstg 65 to 150 C Notes 1 30 pin product only 2 Connect the REGC pin to Vss via a capacitor 0 47 to 1 uF This value determines the absolute maximum rating of the REGC pin Do not use it with voltage applied 3 Must be 6 5 V or lower 4 Do not exceed AVrer 0 3 V in case of A D conversion target pin 5 24 pin products only Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the character
12. mode operation Vaa 3 0V ff as Noma Vio s0v 33 63 ma 3 5 3 fix 16 MHZ Voo 5 0 V 25 39 mA Voo 3 0 V mA fux 20 MH Square wave input Voo 5 0 V Resonator connection fux 20 MHZ Square wave input rie 2 8 mA 8 mA 8 fux 10 MHZ Square wave input Voo 5 0 V Resonator connection EME rie 2 Notes 1 Total current flowing into Vpp including the input leakage current flowing when the level of the input pin is fux 10 MHz Square wave input Vo 3 0 V Oo 7 Vo 3 0 V Resonator connection faso 4 8 Resonator connection fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator clock is stopped 3 When high speed system clock is stopped 4 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vop 2 7 V to 5 5 V 1 MHz to 24 MHz Vo 2 4 V to 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH high speed on chip oscillator clock frequency 3 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0200 Rev 2 00 P
13. or DAPmn 1 and CKPmn 0 tkcy2 tkH2 tkL2 SCKp SOp Output data Remark p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 RO1DS0193EJ0200 Rev 2 00 Page 49 of 106 Sep 06 2013 RENESAS m RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 10 Communication at different potential 1 8 V 2 5 V 3 V simplified rc mode Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode LS low speed main Mode MIN MAX MIN MAX SCLr clock frequency fsc 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V 400 1 300 kHz Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V 4008 300 kHz Co 100 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 300 300 kHz C 100 pF Ro 5 5 KQ Hold time when SCLr L trow 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 1150 1550 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 1150 1550 ns C 100 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Ve lt 2 0 V 1550 1550 ns C 100 pF Re 5 5 KQ Hold time when SCLr H tuich 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 675 610 ns C 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 60
14. to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 Cis the load capacitance of the SOp output lines 5 Transfer rate in the SNOOZE mode MAX 1 Mbps Caution Select the normal input buffer for the Sip and SCKp pins and the normal output mode for the SOp pin by using port input mode register 1 PIM1 and port output mode registers 0 1 4 POMO POM1 POM4 CSI mode connection diagram during communication at same potential SCK F SO User s device microcontroller SI RO1DS0193EJ0200 Rev 2 00 Page 79 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tKey1 2 Input data tkso1 2 SOp q Output data CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkev1 2 Input data tks01 2 SOp Output data Remarks 1 p CSI number p 00 01 11 20 m Unit number m 0 1 n Channel number n 0 1 3 2
15. tolerance mode for the SOp pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vix and Vit see the DC characteristics with TTL input buffer selected CSI01 and CSI11 cannot communicate at different potential RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 47 of 106 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at different potential lt Slave gt Vb RL78 microcontroller User s device Remarks 1 Rb Q Communication line SOp pull up resistance Cb F Communication line SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 10 CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy2 tkL2 tkH2 SCKp Slp SOp Output data R01DS0193EJ0200 Rev 2 00 Page 48 of 106 Sep 06 2013 RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1
16. 5 5 V Vss 0 V lt R gt Oscillators Parameters Conditions High speed on chip oscillator clock frequency S High speed on chip oscillator R5F102 products Ta 20 to 85 C clock frequency accuracy Ta 40 to 20 C R5F103 products Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H and bits 0 to 2 of HOCODIV register 2 This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time RO1DS0193EJ0200 Rev 2 00 Page 18 of 106 Sep 06 2013 RENESAS al lt R gt RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 3 DC Characteristics 2 3 1 Pin characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 1 4 Parameter Conditions Output current high Note 1 20 24 pin products Per pin for POO to P03 4 P10 to P14 P40 to P42 30 pin products Per pin for POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 20 24 pin products 4 0 V lt Voo lt 5 5 V Total of P40 to P42 2 7 V lt Voo lt 4 0 V 30 pin products Total of P00 P01 P40 P120 When duty lt 70 3 20 24 pin products 4 0 V lt Voo lt 5 5 V Total of POO to PO03 4 P10 to P14 1 8 V lt Voo lt 2 7 V 2 7
17. 5 kQ Note When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 Cautions and Remarks are listed on the next page RO1DS0193EJ0200 Rev 2 00 Page 86 of 106 see 2010 RENESAS _ RL78 G12 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 3 3 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Slp setup time to SCKpl Note Conditions 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V C 30 pF Rb 1 4 KQ HS high speed main Mode MIN MAX 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V 30 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 KQ Slp hold time from SCKpJ N 4 0 V lt Voo lt 5 5 V 2 7 V lt Veb lt 4 0 V C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V Cb 30 pF Rb 5 5 KQ Delay time from SCKpT to SOp output 4 0 V lt Voo lt 5 5 V 2 7 V lt Veb lt 4 0 V C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 30 pF Rb 2 7 KQ Note When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Cautions 1 Select the TTL input buffer for the Sip pin
18. 50 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 kQ SI00 setup time to SCKOOT N 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 kQ S100 hold time from SCKOO7 N 4 0 V lt Vo lt 5 5 V 2 7 V lt Vb lt 4 0 V Cb 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 kQ Delay time from SCKOOL to SOOO output 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V C 20 pF Rb 2 7 kQ SI00 setup time to SCKOOL e 4 0 V lt Vm lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 kQ S100 hold time from SCKOOL Nt 4 0 V lt Vm lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 kQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 kQ Delay time from SCKOOT to SO00 output 4 0 V lt Vm lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 kQ Notes Caution and Remarks are listed on the next page R01DS0193EJ0200 Rev 2 00 S
19. Generator Reset Generator Poer on reset voltage detector Voo Vss Note Provided only in the R5F102 products High Speed On chip oscillator 1 to 24 MHz 1 TOOL TOOL TxD RxD Main OSC 1to 20 MHz X1 X2 EXCLK timer gt 12 bit Interval timer 10 bit gt A D converter dich POO to P03 P10 to P14 P20 to P23 P40 to P42 P60 P61 P121 P122 125 P137 PCLBUZO KPO to KR9 INTPO to INTP3 Low Speed On chip oscillator 15 KHz ANI2 ANI3 ANI16 to ANI22 ANIO AVRerP ANI1 AVrerm RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 12 of 106 RL78 G12 1 OUTLINE 1 6 3 30 pin products TAU 8ch TIO0O TOOO TI01 TOO1 T102 TOO2 TI03 TOO3 Tl04 TO04 T105 T005 T106 TO06 T107 T007 RxDO TxDO RxD1 TxD1 SCKOO S100 S000 SCK11 Sl11 S011 SCLOO SDA00 SCL11 SDA11 RxD2 TxD2 SCK20 S120 S020 SCL20 SDA20 TOOLO On chip debug KC gt BCD adjustment KC gt Multiplier amp divider multiply accumulator Code flash 16 KB Data flash 2 KBN Clock Generator SCLAO SDAAO ICAO KC Reset Generator Poer on reset voltage detector Voo Vss Note Provided only in the R5F102 products High Speed On chip oscillator 1 to 24 MHz TOOL TOOL TxD RxD Main OSC 1 to 20 MHz X1 X2 EXCLK rno K gt POO PO1 D on P10 to P17 A
20. Rev 2 00 Sep 06 2013 Please refer to specification for details Page 1 of 106 2tENESAS RL78 G12 O ROM RAM capacities Code flash Data flash 1 OUTLINE R5F102AA R5F103AA R5F1026A Noe R5F1027A N R5F1036A Note R5F1037A Noe R5F10269 No R5F10279 Note R5F102A9 R5F10369 N R5F10379 Noe R5F103A9 R5F10268 N R5F10278 Note R5F102A8 R5F10368 N R5F10378 Ne R5F103A8 RSF 10267 RSF 10277 R5F102A7 RSF 10367 R5F 10377 R5F103A7 R5F10266 Note R5F10366 N Notes 1 This is 640 bytes when the self programming function or data flash function is used For details see CHAPTER 3 CPU ARCHITECTURE in the RL78 G12 User s Manual Hardware 2 The self programming function cannot be used for R5F10266 and R5F10366 Caution When the flash memory is rewritten via a user program the code flash area and RAM area are used because each library is used When using the library refer to RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual RO1DS0193EJ0200 Rev 2 00 Page 2 of 106 see 2010 RENESAS _ RL78 G12 1 OUTLINE 1 2 List of Part Numbers Figure 1 1 Part Number Memory Size and Package of RL78 G12 lt R gt PartNo R5FIO2Z2AAAxxxSP VO Packaging specifications U0 Tray HWQFN V0 Tray LSSOP30 Tube L
21. Ta 40 to 85 C 2 7 V lt Von lt 5 5 V Vss 0 V Parameter Conditions HS high speed main LS low speed main Mode Mode MIN MAX MIN MAX SCKOO cycle time tkcy1 2 fcik 83 3 250 SCKOO high low 4 0 V lt Voo lt 5 5 V tkcy1 2 7 tkcy1 2 50 level width 2 7V lt Vo lt 5 5V txov1 2 10 txcv1 2 50 S100 setup time 4 0 V lt Voo lt 5 5 V 23 110 Note 1 to SCKOOT 2 7 V lt Voo lt 5 5 V 33 110 S100 hold time 10 10 from SCKOOT ote Delay time from C 20pF Note 4 SCKO00J to S000 t Note 3 outpu Notes 1 When DAPOO 0 and CKPOO 0 or DAPOO 1 and CKPOO 1 The SI00 setup time becomes to SCKO0J when DAPOO 0 and CKP00 1 or DAP00 1 and CKP00 0 2 When DAPOO 0 and CKPOO 0 or DAPOO 1 and CKPOO 1 The SIO0 hold time becomes from SCKO0J when DAPOO 0 and CKP00 1 or DAP00 1 and CKPO00 0 3 When DAPOO 0 and CKPOO 0 or DAPOO 1 and CKPO0 1 The delay time to SO00 output becomes from SCKOO1 when DAPOO 0 and CKP00 1 or DAPOO 1 and CKP00 0 4 Cis the load capacitance of the SCKOO and SOOO output lines Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00 pins by using port input mode register 1 PIM1 and port output mode register 1 POM1 Remarks 1 This specification is valid only when CSI00 s peripheral I O redirect function is not used 2 fuck Serial
22. V lt Voo lt 4 0 V 30 pin products Total of P10 to P17 P30 P31 P50 P51 P147 When duty lt 70 3 Total of all pins When duty lt 70 3 Per pin for P20 to P23 1 8 V lt Voo lt 2 7 V Total of all pins Notes 1 value of current at which the device operation is guaranteed even if the current flows from the Vop pin to an output pin 2 However do not exceed the total current value 3 The output current value under conditions where the duty factor lt 70 If duty factor gt 70 The output current value can be calculated with the following expression where n represents the duty factor as a percentage e Total output current of pins loH x 0 7 n x 0 01 lt Example gt Where n 80 and loH 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 4 24 pin products only Caution P10 to P12 and P41 for 20 pin products P01 P10 to P12 and P41 for 24 pin products and P00 P10 to P15 P17 and P50 for 30 pin products do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Page 19 of 106 Sep 06 2013 ztENESAS lt R gt RL78 G12
23. and the normal output mode for the SOp pin by using port input mode register 1 PIM1 and port output mode registers 0 1 4 POMO POM1 POM4 RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 34 of 106 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at same potential SCK RL78 SO User s device microcontroller SI CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcv1 2 tks01 2 SOp Output data CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkev1 2 tks01 2 Remarks are listed on the next page RO1DS0193EJ0200 Rev 2 00 Page 35 of 106 Sep 06 2013 RENESAS E RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Remarks 1 p CSI number p 00 01 11 20 m Unit number m 0 1 n Channel number n 0 1 3 1 3 is only for the R5F102 products 2 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 1 3 1 3 is only for the R5F102 products lt R gt 5 During communication at same potential simplified C m
24. fick Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 1 3 RO1DS0193EJ0200 Rev 2 00 Page 80 of 106 Sep 06 2013 RENESAS E RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 4 During communication at same potential simplified C mode Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode MIN MAX SCLr clock frequency fsc Co 100 pF Ro 3 KQ 100 e1 Hold time when SCLr L tLow C 100 pF Rb 3 kQ 4600 Hold time when SCLr H tHIGH C 100 pF Rb 3 kQ 4600 Data setup time reception tsu DaT C 100 pF Ro 3kQ 1 fmek 580 Ne Data hold time transmission tHD DAT Cb 100 pF Rb 3 KQ 0 Notes 1 The value must also be equal to or less than fuck 4 2 Set tsu pat so that it will not exceed the hold time when SCLr L or SCLr H Caution Select the N ch open drain output Voo tolerance mode for SDAr by using port output mode register h POMh Simplified I C mode connection diagram during communication at same potential Voo RL78 g User s device microcontroller SCL Simplified IC mode serial transfer timing during communication at same potential 1 fscL tLow THIGH SCLr SD
25. gt 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 11 4 UARTO of the 20 and 24 pin products supports communication at different potential only when the peripheral I O redirection function is not used RO1DS0193EJ0200 Rev 2 00 Page 40 of 106 Sep 06 2013 RENESAS E RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKOO internal clock output corresponding CSI00 only Ta 40 to 85 C 2 7 V lt Voo lt 5 5 V Vss 0 V Parameter SCKOO0 cycle time Conditions tkcy1 gt 2 fCLK 4 0 V lt Voo lt 5 5 V 2 7V lt Vos 4 0V HS high speed main Mode LS low speed main Mode 20 pF Rb 1 4 KQ MIN MAX MIN MAX 2 7 V lt Voo lt 4 0 V 2 3 V lt V lt 2 7 V 20 pF Rb 2 7 KQ SCKO0O0 high level width 4 0 V lt Vm lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 KQ tkcy1 2 50 tkcy1 2 50 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 20 pF Rb 2 7 KQ tkcy1 2 120 tkcy1 2 120 SCKO0 low level width 4 0 V lt Vm lt 5 5 V 2 7 V lt Vb lt 4 0 V C 20 pF Rb 1 4 KQ tkcy1 2 7 tkcy1 2
26. in 2 6 1 2 C 1 Sep 06 2013 Description 55 Summary Modification of description and Notes 3 and 4 in 2 6 1 3 56 Modification of description and Notes 3 and 4 in 2 6 1 4 57 Modification of table in 2 6 2 Temperature sensor internal reference voltage characteristics 57 Modification of table and Note in 2 6 3 POR circuit characteristics 58 Modification of table in 2 6 4 LVD circuit characteristics 59 Modification of table of LVD detection voltage of interrupt amp reset mode 59 Modification of number and title to 2 6 5 Power supply voltage rising slope characteristics 61 Modification of table figure and Remark in 2 10 Timing of Entry to Flash Memory Programming Modes 62 to 103 Addition of products of industrial applications G TA 40 to 105 C 104 to 106 Addition of products of industrial applications G TA 40 to 105 C All trademarks and registered trademarks are the property of their respective owners SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technology licensed from Silicon Storage Technology Inc C 2 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS de
27. lt R gt tENESAS Datasheet RL78 G12 RENESAS MCU RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 True Low Power Platform as low as 63 UA MHz 1 8V to 5 5V operation 2 to 16 Kbyte Flash 31 DMIPS at 24MHz for General Purpose Applications 1 OUTLINE 1 1 Features Ultra Low Power Technology e 1 8 V to 5 5 V operation from a single supply e Stop RAM retained 0 23 pA LVD enabled 0 31 pA e Snooze 0 7 mA UART 1 20 mA ADC e Operating 63 pA MHz 16 bit RL78 CPU Core e Delivers 31 DMIPS at maximum operating frequency of 24 MHz e Instruction Execution 86 of instructions can be executed in 1 to 2 clock cycles CISC Architecture Harvard with 3 stage pipeline e Multiply Signed amp Unsigned 16 x 16 to 32 bit result in 1 clock cycle MAC 16 x 16 to 32 bit result in 2 clock cycles 16 bit barrel shifter for shift amp rotate in 1 clock cycle 1 wire on chip debug function Main Flash Memory e Density 2 KB to 16 KB e Block size 1 KB e On chip single voltage flash memory with protection from block erase writing Data Flash Memory e Data Flash with background operation e Data flash size 2 KB size options e Erase Cycles 1 Million typ e Erase programming voltage 1 8 V to 5 5 V RAM e 256 B to 1 5 KB size options e Supports operands or instructions e Back up retention in all modes High speed Oscillator Oscillator e 24MHz with 1 accuracy over voltage 1 8 V to 5 5 V and tempera
28. number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 The pins mounted depend on the product Refer to 2 1 Port Functions to 2 2 1 Functions for each product in the RL78 G12 User s Manual Hardware 3 Please contact Renesas Electronics sales office for derating of operation under Ta 85 C to 105 C Derating is the systematic reduction of load for the sake of improved reliability There are following differences between the products G Industrial applications Ta 40 to 105 C and the products A Consumer applications and D Industrial applications Parameter A Consumer applications Application G Industrial applications Operating ambient temperature D Industrial applications Ta 40 to 85 C Ta 40 to 105 C Operating mode Operating voltage range HS high speed main mode 2 7 V lt Von lt 5 5 V 1 MHz to 24 MHz 2 4 V lt Voo lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Voo lt 5 5 V 1 MHz to 8 MHz HS high speed main mode only 2 7 V lt Voo lt 5 5 V 1 MHz to 24 MHz 2 4 V lt Voo lt 5 5 V 1 MHz to 16 MHz High speed on chip oscillator clock accuracy RSF 102 products 1 8 V lt Voo lt 5 5 V 1 0 Ta 20 to 85 C 1 5 Ta 40 to 20 C RSF 1
29. rne KO P20 to P23 A Pns K gt P30 P31 ap pons K gt P50 P51 gt rne K P60 P61 gt P120 m E P121 P122 A ea jme e je Buzzer clock A PCLBUZO PCLBUZ1 Interrupt control 2 agent er INTPO to INTP5 Window watchdog timer kK 12 bit Interval timer 10 bit gt A D converter 8ch VOLTAGE REGULATOR Low Speed On chip oscillator 15 KHz cm ANI2 ANI3 ANI16 to ANI19 ANIO AVreEFP ANI1 AVrerm REGC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G12 User s Manual Hardware RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 13 of 106 RL78 G12 1 OUTLINE 1 7 Outline of Functions This outline describes the function at the time when Peripheral I O redirection register PIOR is set to OOH 1 2 20 pin 24 pin 30 pin R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax Code flash memory 2 to 16 6 KB Data flash memory 2 KB 2 KB 2 KB RAM 256 B to 1 5 KB 512 B to 1 5 KB 512 B to 2KB Address space 1 MB Main High speed system clock X1 X2 crystal ceramic oscillation external main system clock input EXCLK system 1 to 20 MHz Voo 2 7 to 5 5 V 1 to 8 MHz Vop 1 8 to 5 5 V clock High speed on chip HS High speed main mode 1 to 24 MHz Von 2 7 to 5 5 V 1
30. scale value 3 When AVrere lt Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVrere Vov Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVrere Voo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVrere Voo 4 Refer to 3 6 2 Temperature sensor internal reference voltage characteristics 2 When reference voltage AVrerr ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pin ANI16 to ANI22 Ta 40 to 105 C 2 4 V lt AVrerp lt Voo lt 5 5 V Vss 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Conditions Resolution nolo 10 bit resolution Note 3 AVrere Voo Overall error Conversion time 10 bit resolution 3 6V lt Vpp lt 5 5V Target ANI pin ANI16 to ANI22 27V lt Vpp lt 55V 2 4 V lt VoD lt 5 5 V Notes 1 2 10 bit resolution Note 3 AVReFP Voo Zero scale error Notes 1 2 10 bit resolution Note 3 AVReFP Vopn Full scale error Note 10 bit resolution Note 3 AVreFP Voo Integral linearity error Differential linearity 10 bit resolution error N AVrerp Von Note Analog input voltage ANI16 to ANI22 AVREFP and Voo Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full sca
31. the duty factor as a percentage e Total output current of pins lot x 0 7 n x 0 01 lt Example gt Where n 80 and lot 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 4 24 pin products only Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Page 66 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V 3 4 Parameter Conditions Input voltage high Normal input buffer 20 24 pin products POO to PO3 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 TTL input buffer 4 0V lt Vo0 lt 5 5V 20 24 pin products P10 P11 3 3 V lt Voo lt 4 0 V 30 pin products P01 P10 2 4 V lt Voo lt 3 3 V P11 P13 to P17 Normal input buffer P20 to P23 P60 P61 P121 P122 P125 1 P137 EXCLK RESET Input voltage low Normal input buffer 20 24 pin products POO to PO3 P10 to P14 P40 to P42 30 pin products P00 P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 TTL input buffer 4 0 V lt Voo lt 5 5 V 20 24 pin product
32. 0 610 ns C 100 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Ve lt 2 0 V 610 610 ns C 100 pF Re 5 5 KQ Data setup time reception tsu pat 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 1 fuck 1 fuck ns Co 100 pF Ro 2 8 KQ 190 190 Note3 Note3 2 7 V lt Voo lt 4 0 V 2 3 V lt Veo lt 2 7 V 1 fuck 1 fuck ns Co 100 pF Ro 2 7 KQ 190 190 Note3 Note3 1 8 V lt Voo lt 3 3 V 1 6 V lt Vbo lt 2 0 V 4 fuck 1 fmck ns C 100 pF Rb 5 5 kQ 190 190 Note3 Note3 Data hold time tyovat 4 0 V lt Voo lt 5 5 V 2 7 V lt Ve lt 4 0 V 0 355 0 355 ns transmission Cb 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V 0 355 0 355 ns Co 100 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V 0 405 0 405 ns C 100 pF Rb 5 5 kQ lt R gt Notes 1 The value must also be equal to or less than fuck 4 2 Use it with Vop Vb 3 Set tsu pat so that it will not exceed the hold time when SCLr L or SCLr H lt R gt Cautions 1 Select the TTL input buffer and the N ch open drain output Voo tolerance mode for the SDAr pin and the N ch open drain output Voo tolerance mode for the SCLr pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vin and Vi see the DC characteristics with TTL input buffer selected 2 IIC01 and IIC11 cannot communicate at different potential Re
33. 0 MHz Square wave input Ta 1000 Note 6 LS Low speed fmx 8 MHz Square wave input 95 330 main mode Voo 3 0 V Resonator connection 145 3s0 m nese O OOOO ee mws oOo oo i S mo mos T Tea mes OOOO S l o a lt R gt Notes 1 Total current flowing into Voo including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory lt R gt When high speed on chip oscillator clock is stopped When high speed system clock is stopped Not including the current flowing into the 12 bit interval timer and watchdog timer oar a Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Voo 2 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vpop 1 8 V to 5 5 V 1 MHz to 8 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH high speed on chip oscillator clock frequency 3 Except STOP mode temperature condition of the TYP value is Ta 25 C RO1DS0193EJ020
34. 0 Rev 2 00 Page 26 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 3 Peripheral functions Common to all products Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Low speed onchip oscillator operating current Conditions 12 bit interval timer operating current ITmka Notes 1 2 3 Watchdog timer operating current lwot f 15 kHz Notes 1 2 4 A D converter operating current Notes1 5 When conversion at maximum speed lanc Normal mode AVrere Voo 5 0 V Low voltage mode AVrerp Voo 3 0 V A D converter reference voltage operating current Temperature sensor operating current Note 1 Itwps LVD operating current Notes 1 6 ILvb Self programming operating current Notes 1 8 IFSP BGO operating current Notes 1 7 IBco SNOOZE operating current Notes 1 2 3 Remarks 1 fi 2 Temperature condition of the TYP value is Ta 25 C Note 1 Isnoz The mode is performed N 9 ADC operation The A D conversion operations are performed Low voltage mode AVrerp Voo 3 0 V CSI UART operation Current flowing to the Vpp When high speed on chip oscillator and high speed system clock are stopped Current flowing only to the 12 bit interval timer excluding the operating current of the low speed o
35. 0 V Parameter Conditions HS high speed main Mode SCKp cycle time tkcy1 4 fcik 2 7 V lt Voo lt 5 5 V 334 MIN MAX 2 4 V lt Voo lt 5 5 V 500 SCKp high low level width 4 0 V lt Voo lt 5 5 V tkcy1 2 24 2 7 V lt Voo lt 5 5 V tkcy1 2 36 2 4 V lt Voo lt 5 5 V tkcy1 2 76 Slp setup time to SCKp 4 0 V lt Voo lt 5 5 V 66 2 7 V lt Voo lt 5 5 V 66 2 4 V lt Voo lt 5 5 V Slp hold time from SCKpT Delay time from SCKp1 to C 30 pF Ns SOp output Notes 1 Caution Remarks Note 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 C is the load capacitance of the SCKp and SOp output lines Select the normal input buffer for the Slp pin and the normal output mode for the SOp and SCKp pins by using port input mode register 1 PIM1 and port output mode registers 0 1 4 POMO POM1 POM4 1 p CSI number p 00 01 11 20 m Unit number m 0 1 n Channel number n 0 1 3 2
36. 03 products 1 8 V lt Voo lt 5 5 V 5 0 Ta 40 to 85 C R5F102 products 2 4 V lt Von lt 5 5 V 2 0 Ta 85 to 105 C 1 0 Ta 20 to 85 C 1 5 Ta 40 to 20 C Serial array unit UART CSI fcLk 2 supporting 12 Mbps fctk 4 Simplified C communication UART CSI fcLk 4 Simplified C communication Voltage detector Rise detection voltage 1 88 V to 4 06 V 12 levels Fall detection voltage 1 84 V to 3 98 V 12 levels Rise detection voltage 2 61 V to 4 06 V 8 levels Fall detection voltage 2 55 V to 3 98 V 8 levels Remark The electrical characteristics of the products G Industrial applications Ta 40 to 105 C are different from those of the products A Consumer applications and D Industrial applications For details refer to 3 1 to 3 10 RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 62 of 106 RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C Parameter Symbols Conditions Ratings Supply Voltage 0 5 to 6 5 REGC terminal input 0 3 to 2 8 Note1 voltage and 0 3 to Voo 0 3 Note 2 Input Voltage Other than P60 P61 0 3 to Von 0 3 P60 P61 N ch open drain 0 3 to 6 5 Output Voltage 0 3 to Von 0 3 Analog input voltage 20 24 pin products ANIO to ANI3 ANI16 to ANI22 0 3 to Voo 0 3 30 pin products ANIO
37. 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 2 4 Parameter Conditions Output current low Note 1 20 24 pin products Per pin for POO to PO3 4 P10 to P14 P40 to P42 30 pin products Per pin for POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 Per pin for P60 P61 20 24 pin products 4 0 V lt Voo lt 5 5 V Total of P40 to P42 27V lt Vo lt 40V 30 pin products 1 8 V lt Voo lt 2 7 V Total of POO P01 P40 P120 When duty lt 70 20 24 pin products 4 0 V lt Voo lt 5 5 V Note 4 Total of POO to P03 27V lt Vp0 lt 4 0V P10 to P14 P60 P61 1 8 V lt Voo lt 2 7 V 30 pin products Total of P10 to P17 P30 P31 P50 P51 P60 P61 P147 When duty lt 70 Total of all pins When duty lt 70 Per pin for P20 to P23 Total of all pins Notes 1 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the Vss pin 2 However do not exceed the total current value 3 The output current value under conditions where the duty factor lt 70 If duty factor gt 70 The output current value can be calculated with the following expression where n represents the duty factor as a percentage e Total output current of pins lot x 0 7 n x 0 01 lt Example gt Where n
38. 3 ANI16 to ANI22 AVREFM AVREFP EXCLK INTPO to INTP5 KRO to KR9 POO to PO3 P10 to P17 P20 to P23 P30 to P31 P40 to P42 P50 P51 P60 P61 P120 to P122 P125 P137 P147 PCLBUZO PCLBUZ1 Analog input Analog Reference Voltage Minus Analog reference voltage plus External Clock Input Main System Clock Interrupt Request From Peripheral Key Return Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 12 Port 13 Port 14 Programmable Clock Output Buzzer Output REGC RESET RxDO to RxD2 SCKO0 SCK01 SCK11 SCK20 SCLOO SCLO01 SCL11 SCL20 SCLAO SDAO00 SDA01 SDA11 SDA20 SDAAO S100 S101 S111 S120 S000 S001 S011 S020 TI00 to T107 TOOO to TOO7 TOOLO TOOLRxD TOOLTxD TxDO to TxD2 VDD Vss X1 X2 Regulator Capacitance Reset Receive Data Serial Clock Input Output Serial Clock Input Output Serial Data Input Output Serial Data Input Serial Data Output Timer Input Timer Output Data Input Output for Tool Data Input Output for External Device Transmit Data Power supply Ground Crystal Oscillator Main System Clock R01DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 10 of 106 RL78 G12 1 OUTLINE 1 6 Block Diagram 1 6 1 20 pin products T100 TOOO T101 TOO1 T102 TOO2 T103 TOO3 RxDO TxDO SCKOO S100 S000 SCK01 S 01 S001 SCLOO SDAOO SCLO1 SDA01 TOOLO On chip debu
39. 300 fin 16 MHz 4 Voo 5 0 V 400 1700 uA Voo 3 0 V 400 1700 fmx 20 MHZ Square wave input 280 1900 uA Voo 5 0 V Resonator connection 450 2000 fmx 20 MHz Square wave input 280 1900 uA Vov 3 0 V Resonator connection 450 2000 fmx 10 MHZ Square wave input 190 1020 uA Voo 5 0 V Resonator connection 260 1100 fmx 10 MHZ Square wave input 190 1020 uA Vov 3 0 V Resonator connection 260 1100 looa e5 STOP Ta 40 C 0 18 0 50 uA mode Ta 25 C 0 23 0 50 Ta 50 C 0 30 1 10 Ta 70 C 0 46 1 90 Ta 85 C 0 75 3 30 Ta 105 C 2 94 15 30 Notes 1 Total current flowing into Voo including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator clock is stopped When high speed system clock is stopped Not including the current flowing into the 12 bit interval timer and watchdog timer oa PF ON Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Voo 2 7 V to 5 5 V 1 MHz to 24 M
40. 50 Slp setup time to SCKpT Noe 4 0 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 0 V 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V 1 8 V lt Voo lt 3 3 V 1 6 V lt Voo lt 2 0 V 1 fmck 20 1 fmck 20 1 fuck 30 1 fuck 30 1 fmck 30 1 fuck 30 Slp hold time from SCKp7 te Tifivck 31 1 fuck 31 Delay time from SCKp to SOp output Note 5 Notes 1 2 3 Cautions 1 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 30 pF Ro 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 VN 30 pF Rb 5 5 KQ Transfer rate in the SNOOZE mode MAX 1 Mbps Use it with Voo Vb When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip setup time becomes to SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 fuck 120 2 fuck 573 2 fuck 214 2 fuck 573 2 fuck 573 2 fuck 573 Select the TTL input buffer for the Sip and SCKp pins and the N ch open drain output Voo
41. 50 2 4 2 7 55 6 0 Supply voltage V pp V Tey vs Vo LS low speed main mode When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected Cycle time Tcy us 0 10 20 30 40 50 60 Supply voltage Voo V RO1DS0193EJ0200 Rev 2 00 Page 29 of 106 Sep 06 2013 RENESAS m RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt AC Timing Test Point Vin VoH F Vin VoH Vi Vot Tesi points oe Vi VoL lt R gt External Main System Clock Timing EXCLK TI TO Timing lt trit tri TI00 to TIO7 I 1 fto TOOO to TO07 Interrupt Request Input Timing lt TINTL TINTH INTPO to INTP5 I tkR gt KRO to KR9 I tRsL RESET R01DS0193EJ0200 Rev 2 00 Page 30 of 106 Sep 06 2013 RENESAS m Key Interrupt Input Timing RESET Input Timing RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 5 Peripheral Functions Characteristics lt R gt AC Timing Test Point Vin VoH ViHn VoH Na Test points lt ViN 2 5 1 Serial array unit lt R gt 1 During communication at same potential UART mode Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Symbol Conditions HS high speed LS low speed main Mode main Mode I MAX MIN
42. 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vopp 1 8 V to 5 5 V 1 MHz to 8 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH high speed on chip oscillator clock frequency 3 Except temperature condition of the TYP value is Ta 25 C other than STOP mode RO1DS0193EJ0200 Rev 2 00 Page 24 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 30 pin products 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Ipp1 Operating HS High speed main mode 4 Supply current ote LS Low speed main mode HS High speed main mode 4 LS Low speed main mode 4 Conditions fi 24 MHz fin 16 MHZ fix 8 MHZ fux 20 MHz Vo 5 0 V fux 20 MHz Voo 3 0 V fux 10 MHz Voo 5 0 V fux 10 MHz Voo 3 0 V fux 8 MHzN Voo 3 0 V fux 8 MH2 Vo 2 0 V 1 2 on Voo 5 0 V 3 7 5 5 3 0 V Voo 2 0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection lt R gt Notes 1 Total current flowing into Voo including the inp
43. 78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode connection diagram during communication at different potential lt Slave gt Vb RL78 microcontroller User s device CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy2 tkL2 tkH2 SCKp tsik2 tksi2 Slp SOp Output data Remarks 1 Rb Q Communication line SOp pull up resistance C F Communication line SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn RO1DS0193EJ0200 Rev 2 00 Page 90 of 106 Sep 06 2013 RENESAS E RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy2 tkH2 tkL2 SCKp SOp Output data Remark p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 RO1DS0193EJ0200 Rev 2 00 Page 91 of 106 Sep 06 2013 RENESAS m RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 8 Communication at differ
44. Ar tHD DAT tsu DAT Remarks 1 R Q Communication line SDAr pull up resistance Cb F Communication line SCLr SDAr load capacitance 2 r 1lC number r 00 01 11 20 h POM number h O 1 4 5 3 fick Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number 0 1 3 RO1DS0193EJ0200 Rev 2 00 Page 81 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Transfer Reception 4 0 V lt Vp lt 5 5V rate ote 2 7 V lt Vo lt 4 0 V Theoretical value of the maximum transfer rate Note 2 fuck fck 2 7 V lt Vop lt 4 0 V 2 3 V lt V lt 2 7 V Theoretical value of the maximum transfer rate Note 2 fuck fck 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V Theoretical value of the maximum transfer rate Note 2 fuck fck Transmission 4 0 V lt Vmp lt 5 5V 2 7 V lt V lt 4 0 V Theoretical value of the maximum transfer rate Co 50 pF Rb 1 4 KQ Vb 2 7 V 2 7 V lt Voo lt 4 0 V 2 3 V lt V lt 2 7 V Theoretical value of the maximum transfer rate Co 50 pF Rb 2 7 KQ Vb 2 3 V 2 4 V lt Vo lt 3 3 V 1 6 V lt Vb lt 2 0 V Theo
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46. Clock Oscillator in the RL78 G12 User s Manual Hardware 3 2 2 On chip oscillator characteristics Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Oscillators Parameters Conditions High speed on chip oscillator clock frequency S High speed on chip oscillator R5F102 products Ta 20 to 85 C clock frequency accuracy Ta 40 to 20 C Ta 85 to 105 C Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte O00C2H and bits 0 to 2 of HOCODIV register 2 This only indicates the oscillator characteristics Refer to AC Characteristics for instruction execution time RO1DS0193EJ0200 Rev 2 00 Page 64 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 3 DC Characteristics 3 3 1 Pin characteristics Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V 1 4 Parameter Conditions Output current high Notes 1 4 Caution Note 1 20 24 pin products Per pin for POO to P03 4 P10 to P14 P40 to P42 30 pin products Per pin for POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 20 24 pin products 4 0 V lt Voo lt 5 5 V Total of P40 to P42 2 7 V lt Voo lt 4 0 V 30 pin products Total of P00 P01 P40 P120 Wh
47. D Ta 40 to 85 C 1 20 24 pin products Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 2 2 Supply lope N _ HALT HS High speed fin 24 MHz 4 Hvoo 5 0v so 120 uA current ote mode main mode lvo 3 0v so izo wzo 00 fo LS Low speed fin 8 MHz 4 a eee uA HS High speed fmx 20 MHZ CE fux 20 MHZ 3 Square wave input BE A 1000 fmx 10 MHZ 3 Square wave input 1 5 fmx 10 MHz 3 Square wave input f 190 590 LS Low speed fmx 8 MHz Square wave input f no 360 P Note 6 fmx 8 MHzZNo 3 Square wave input no 360 lt R gt Notes 1 Total current flowing into Vpp including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory lt R gt When high speed on chip oscillator clock is stopped When high speed system clock is stopped Not including the current flowing into the 12 bit interval timer and watchdog timer oar on Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Voo 2
48. D DAT 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 0 1420 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 0 1420 ns Co 100 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 0 1215 ns Co 100 pF Rb 5 5 KQ Notes 1 The value must also be equal to or less than fuck 4 2 Set tsu pat so that it will not exceed the hold time when SCLr L or SCLr H Cautions 1 Select the TTL input buffer and the N ch open drain output Voo tolerance mode for the SDAr pin and the N ch open drain output Voo tolerance mode for the SCLr pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vin and Vi see the DC characteristics with TTL input buffer selected 2 I1CO1 and IIC11 cannot communicate at different potential Remarks are listed on the next page RO1DS0193EJ0200 Rev 2 00 Page 92 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Simplified C mode connection diagram during communication at different potential SDAr RL78 F User s device microcontroller SCLr SCL Simplified 17 C mode serial transfer timing during communication at different potential 1 fscL trow tHIGH SCLr SDAr HD DAT tsu DAT Remarks 1 Rb Q Communication line SDAr SCLr pull up resistance C F Communication line SDAr SCLr load capacit
49. ESAS E RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter SCKp cycle time Conditions HS high speed main Mode LS low speed main Mode MIN MAX MAX Note 1 4 0V lt Vo0 lt 5 5V 20 MHz lt fuck lt 24 MHz 2 7 V lt Vo lt 4 0 V 12 fmcK 10 fmcK 8 MHz lt fuck lt 20 MHz 4 MHz lt fuck lt 8 MHz 8 fuck 6 fuck 16 fuck 14 fuck 12 fuck 8 fuck 6 fuck 16 fuck fuck lt 4 MHz 10 fuck 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 20 MHz lt fuck lt 24 MHz 16 MHz lt fuck lt 20 MHz 8 MHz lt fuck lt 16 MHz 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 10 fuck 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V Note 2 20 MHz lt fuck lt 24 MHz 36 fuck 16 MHz lt fuck lt 20 MHz 32 fuck 8 MHz lt fuck lt 16 MHz 26 fuck 4 MHz lt fuck lt 8 MHz 16 fuck 10 fuck 16 fuck fuck lt 4 MHz 10 fuck SCKp high low level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Ve lt 4 0 V 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V e tkcy2 2 12 tkcy2 2 50 tkcy2 2 18 tkcy2 2 50 tkcy2 2 50 tkcy2 2
50. Hz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fix high speed on chip oscillator clock frequency 3 Except STOP mode temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0200 Rev 2 00 Page 72 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 Peripheral functions Common to all products Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Conditions Low speed onchip oscillator operating current 12 bit interval timer ItKa operating current Notes 1 2 3 Watchdog timer lwo fi 15 kHz operating current Notes 1 2 4 A D converter lanc When conversion Normal mode AVrere Voo 5 0 V operating current Notes 1 5 5 at maximum speed Low voltage mode AVrere Voo 3 0 V A D converter reference voltage operating current Temperature sensor Itwps operating current Note 1 LVD operating current ILvo Notes 1 6 Self programming lFsP operating current Notes 1 8 BGO operating IBco current Notes 1 7 SNOOZE operating Isnoz ADC operation The mode is performe Note 1 current d Note 9 The A D conversion operations are performed Low voltage mode AVrerp Vop 3 0 V CSI UART operation Current flowing to the Vpp Wh
51. IONS G Ta 40 to 105 C Minimum Instruction Execution Time during Main System Clock Operation Tey vs Voo HS high speed main mode 10 1 0 no When the high speed on chip oscillator clock is selected O During self programming ea When high speed system clock is selected E 2 S gt O 0 1 0 0625 0 04167 0 01 0 10 20 30 40 50 60 24 2 7 55 Supply voltage Voo V AC Timing Test Point Vin VoH Vin Vou Test point Vi VoL a a Vi Vor External Main System Clock Timing EXCLK RO1DS0193EJ0200 Rev 2 00 Page 75 of 106 Sep 06 2013 RENESAS m RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C TI TO Timing trit tTIH T100 to TI07 1 fto TOOO to TO07 Interrupt Request Input Timing I TINTL gt TINTH INTPO to INTP5 Key Interrupt Input Timing I tkr gt KRO to KR9 RESET Input Timing I tRsL RESET R01DS0193EJ0200 Rev 2 00 Page 76 of 106 Sep 06 2013 RENESAS m RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 5 Peripheral Functions Characteristics AC Timing Test Point Vin VoH Vin VoH Viia gt Test points lt L Ne 3 5 1 Serial array unit 1 During communication at same potential UART mode Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high spee
52. L78 G12 4 PACKAGE DRAWINGS 4 3 30 pin products R5F102AAASP R5F102A9ASP R5F102A8ASP R5F102A7ASP RS5F103AAASP R5F103A9ASP R5F103A8ASP R5F103A7ASP R5F102AADSP R5F102A9DSP R5F102A8DSP R5F102A7DSP R5F103AADSP R5F103A9DSP R5F103A8DSP R5F103A7DSP lt R gt RSF102AAGSP R5F102A9GSP R5F102A8GSP R5F102A7GSP lt R gt RSF103AAGSP R5F103A9GSP R5F103A8GSP R5F103A7GSP JEITA Package Code RENESAS Code Previous Code MASS TYP g P LSSOP30 0300 0 65 PLSP0030JB B S30MC 65 5A4 3 0 18 detail of lead end F G y T Z Te 4 ry p LE a lt U ITEM MILLIMETERS Lk A 9 85 0 15 0 45 MAX 0 65 T P 0 08 NOTE 0 24007 Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition 0 10 05 1 340 1 1 2 8 140 2 6 140 2 1 0 0 2 0 1740 03 0 5 0 13 0 10 atta 0 25 0 6 0 15 Cla D ZIZ Xj T O n im o 0 w 2012 Renesas Electronics Corporation All rights reserved R01DS0193EJ0200 Rev 2 00 Page 106 of 106 Sep 06 2013 RENESAS m Revision History RL78 G12 Data Sheet Description Summary 1 00 Dec 10 2012 First Edition issued 2 00 Sep 06 2013 1 Modification of 1 1 Features 3 Modification of 1 2 List of Part Num
53. MAX Transfer rate fmck 6 fmck 6 E Theoretical value of the maximum transfer rate 4 0 1 3 fork fmc E pe Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only lt R gt 2 The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 24 MHz 2 7 V lt Voo lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V LS low speed main mode 8 MHz 1 8 V lt Voo lt 5 5 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg UART mode connection diagram during communication at same potential i User s device microcontroller UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 q UART number q 0 to 2 g PIM POM number g 0 1 2 fmok Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 11 R01DS0193EJ0200 Rev 2 00 Page 31 of 106 Sep 06 2013 RENESAS l RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 2 During communication at same potential CSI mode master mode SCKOO internal clock output corresponding CSI00 only
54. NIO to ANI3 ANI16 to ANI22 Internal reference voltage Veer Notes HS high speed main mode Temperature sensor output voltage Vimpsas 3 HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 3 6 2 Temperature sensor internal reference voltage characteristics RO1DS0193EJ0200 Rev 2 00 Page 97 of 106 Sep 06 2013 RENESAS z RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 4 When reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage AVrerm ADREFM 1 target pin ANIO ANI2 ANI3 and ANI16 to ANI22 Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Reference voltage Veser Reference voltage AVrerm t 0 V HS high speed main mode Parameter Conditions Resolution Conversion time 8 bit resolution 39 Zero scale error 8 bit resolution 0 60 Integral linearity error 8 bit resolution 2 0 Differential linearity error N 8 bit resolution 1 0 Analog input voltage Vecer Note3 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 3 6 2 Temperature sensor internal reference voltage characteristics 4 When reference voltage Vss the MAX values are as foll
55. NS D 6 50 0 10 E 4 40 0 10 NOTE HE 6 40 0 20 1 Dimensions X1 and X2 do not include mold flash A VAS NAS A1 0 10 0 10 2 Dimension X3 does not include trim offset A2 1 15 e 0 65 0 12 bp 0 224010 c 0 15 40 03 L 0 50 0 20 y 0 10 0 0 to 10 2012 Renesas Electronics Corporation All rights reserved RO1DS0193EJ0200 Rev 2 00 Page 104 of 106 Sep 06 2013 2tENESAS RL78 G12 4 PACKAGE DRAWINGS 4 2 24 pin products R5F1027AANA R5F10279ANA R5F10278ANA R5F10277ANA R5F1037AANA R5F10379ANA R5F10378ANA R5F10377ANA R5F1027ADNA R5F10279DNA R5F10278DNA R5F10277DNA R5F1037ADNA R5F10379DNA R5F10378DNA R5F10377DNA lt R gt RSF1027AGNA R5F10279GNA R5F10278GNA R5F10277GNA lt R gt R5F1037AGNA R5F10379GNA R5F10378GNA R5F10377GNA JEITA Package Code RENESAS Code Previous Code MASS TYP g P HWQFN24 4x4 0 50 PWQN0024KE A P24K8 50 CAB 1 0 04 DETAIL OF A PART UNIT mm ITEM DIMENSIONS D 4 00 0 05 E 4 00 0 05 A 0 75 40 05 b EXPOSED DIE PAD 0 05 0 25 0 07 e 0 50 Lp 0 40 0 10 x 0 05 y 0 05 D2 E2 EXPOSED DIE PAD A 2 45 2 50 2 55 2 45 2 50 2 55 VARIATIONS 2012 Renesas Electronics Corporation All rights reserved R01DS0193EJ0200 Rev 2 00 Page 105 of 106 Sep 06 2013 2tENESAS R
56. O1DS0193EJ0200 Rev 2 00 Page 43 of 106 Sep 06 2013 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock lt R gt lt R gt output 2 3 Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Slp setup time to SCKpT 8 Conditions 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V C 30 pF Rb 1 4 kQ HS high speed main Mode LS low speed main Mode MIN MAX MIN MAX 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 30 pF Rb 2 7 kQ 1 8 V lt Vo lt 3 3 V 1 6 V lt Vo lt 2 0 V 2 C 30 pF Rb 5 5 kQ Slp hold time from SCKp7 N 4 0 V lt Vom lt 5 5 V 2 7 V lt Vb lt 4 0 V C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V Cb 30 pF Rb 2 7 kQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V C 30 pF Rb 5 5 kQ Delay time from SCKp to SOp output Note 1 4 0 V lt Vom lt 5 5 V 2 7 V lt Vb lt 4 0 V C 30 pF Rb 1 4 kQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 30 pF Rb 2 7 kQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V C 30 pF Rb 5 5 kQ Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 Use it with Voo g
57. P VO R5SF1026ADSP XO R5F10269DSP X0 R5F10268DSP X0 R5F10267DSP XO R5F10266DSP XO RSF1026AGSP VO0 R5F10269GSP V0 R5F10268GSP V0 R5F10267GSP VO RSF 10266GSP VO RSF1026AGSP X0 R5F10269GSP X0 R5F10268GSP X0 R5F10267GSP X0 R5SF10266GSP X0 Not mounted R5F1036AASP V0 RSF10369ASP VO R5F10368ASP VO R5F10367ASP VO R5SF10366ASP VO R5SF1036AASP X0 RSF10369ASP XO R5F10368ASP XO R5F10367ASP XO R5F10366ASP X0 R5F1036ADSP V0 R5F10369DSP VO R5F10368DSP V0 R5F10367DSP VO R5F10366DSP VO R5F1036ADSP XO R5F10369DSP X0 R5F10368DSP X0 R5F10367DSP XO R5F10366DSP X0 24 pin plastic HWQFN 4x4 mm 0 5 mm pitch Mounted RS5F1027AANA U0 R5F10279ANA U0 R5F10278ANA UO R5F10277ANA U0 R5F1027AANA WO R5F10279ANA WO R5F10278ANA WO R5F10277ANA WO R5F1027ADNA UO0 R5F10279DNA UO R5F10278DNA U0 R5F10277DNA U0 R5F1027ADNA WO R5F10279DNA WO R5F10278DNA WO R5F10277DNA WO R5F1027AGNA U0 R5F10279GNA U0 R5F10278GNA UO R5F10277GNA U0 R5F1027AGNA WO R5F10279GNA WO R5F10278GNA WO R5F10277GNA WO Not mounted R5F1037AANA VO R5F10379ANA VO R5SF10378ANA VO R5F10377ANA VO R5F1037AANA X0 R5F10379ANA XO R5F10378ANA XO R5F10377ANA XO R5F1037ADNA VO0 R5F10379DNA VO R5F10378DNA VO R5F10377DNA VO R5F1037ADNA X0 R5F10379DNA X0 R5F10378DNA XO R5F10377DNA XO 30 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch Mounted R5SF102AAASP V0 R5F102A9ASP VO R5SF102A8ASP V0 RSF102A7A
58. PIMg and port output mode register g POMg For Vi and Vit see the DC characteristics with TTL input buffer selected RO1DS0193EJ0200 Rev 2 00 Page 83 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C UART mode connection diagram during communication at different potential RL78 User s device microcontroller RxDq UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance Ee ee ee TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remarks 1 Rp Q Communication line TxDq pull up resistance Co F Communication line TxDq load capacitance V V Communication line voltage 2 q UART number q 0 to 2 g PIM and POM number g 0 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 11 4 UARTO of the 20 and 24 pin products supports communication at different potential only when the peripheral I O redirection function is not used RO1DS0193EJ0200 Rev 2 00 Page 84 of 106 Sep 06 2013 RENESAS E RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 6 Communication at different potential 1 8
59. S0193EJ0200 Rev 2 00 Page 88 of 106 Sep 06 2013 RENESAS E RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 7 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Conditions HS high speed main SCKp cycle time 4 0V lt Vo0 lt 5 5V 20 MHz lt fuck lt 24 MHz 24 fuck Mode MIN MAX 2 7 V lt V b lt 4 0V 8 MHz lt fuck lt 20 MHz 20 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 12 fuck 2 7 V lt Vbpo lt 4 0V 20 MHz lt fuck lt 24 MHz 32 fuck 2 3V lt Vo lt 2 7V 16 MHz lt fuck lt 20 MHz 28 fuck 8 MHz lt fuck lt 16 MHz 24 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck lt 4 MHz 12 fuck 2 4 V lt Vpn lt 3 3 V 20 MHz lt fuck lt 24 MHz 72 fuck 1 6 V lt Vo lt 2 0 V 16 MHz lt fuck lt 20 MHz 64 fuck 8 MHz lt fuck lt 16 MHz 52 fuck 4 MHz lt fuck lt 8 MHz 32 fuck fuck lt 4 MHz 20 fuck SCKp high low level 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V tkcy2 2 24 width 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V tkcy2 2 36 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V tkcy2 2 100 Slp setup time Note 2 to SCKpT 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V 1 fucx 40 4 0 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 0 V 1
60. SP VO R5F102AAASP XO R5F102A9ASP XO0 R5SF102A8ASP X0 R5F102A7ASP XO R5F102AADSP VO R5F102A9DSP V0 R5F102A8DSP VO R5F102A7DSP V0 R5F102AADSP XO0 R5F102A9DSP XO R5F102A8DSP X0 R5F102A7DSP XO R5F102AAGSP V0 R5F102A9GSP VO0 R5F102A8GSP VO R5F102A7GSP VO R5F102AAGSP X0 R5F102A9GSP XO R5F102A8GSP XO R5F102A7GSP X0 Not mounted RSF103AAASP V0 R5SF103A9ASP VO0 R5SF103A8ASP V0 R5SF103A7ASP VO R5F103AAASP X0 R5SF103A9ASP X0 RSF103A8ASP X0 R5F103A7ASP XO R5F103AADSP VO R5F103A9DSP V0 R5F103A8DSP VO R5F103A7DSP VO R5F103AADSP XO R5F103A9DSP X0 R5F103A8DSP X0 R5F103A7DSP X0O Note For fields of application see Figure 1 1 Part Number Memory Size and Package of RL78 G12 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 4 of 106 ztENESAS RL78 G12 1 OUTLINE 1 3 Differences between the R5F102 Products and the R5F103 Products The following are differences between the R5F102 products and the R5F103 products O Whether the data flash memory is mounted or not O High speed on chip oscillator oscillation frequency accuracy O Number of channels in serial interface O Whether the DMA function is mounted or not O Whether a part of the safety functions are mounted or not 1 3 1 Data Flash The dat
61. SSOP20 W0 Embossed Tape HWQFN X0 Embossed Tape LSSOP30 LSSOP20 Package type SP LSSOP 0 65 mm pitch NA HWQEN 0 50 mm pitch ROM number Omitted with blank products Classification A Consumer applications Ta 40 C to 85 C D Industrial applications Ta 40 C to 85 C G Industrial applications Ta 40 C to 105 C ROM capacity 6 2KB 7 4KB 8 8KB 9 12KB A 16KB Pin count 6 20 pin 7 24 pin A 30 pin RL78 G12 group 102 103 tes 1 2 Memory type F Flash memory Renesas MCU Renesas semiconductor product Notes 1 For details about the differences between the R5F102 products and the R5F103 products of RL78 G12 see 1 3 Differences between the R5F102 Products and the R5F103 Products 2 Products only for A Consumer applications Ta 40 to 85 C and D Industrial applications Ta 40 to 85 C RO1DS0193EJ0200 Rev 2 00 Page 3 of 106 Sep 06 2013 RENESAS D lt R gt lt R gt RL78 G12 Package 20 pin plastic LSSOP 4 4 x 6 5 mm 0 65 mm pitch Data flash Mounted Table 1 1 Fields of Application 1 OUTLINE List of Ordering Part Numbers Part Number R5F1026AASP VO0 R5F10269ASP VO R5F10268ASP VO R5F10267ASP VO R5F10266ASP VO R5F1026AASP X0 R5F10269ASP XO R5F10268ASP XO R5F10267ASP XO R5F10266ASP X0 R5F1026ADSP VO0 R5F10269DSP VO R5F10268DSP VO0 R5F10267DSP VO R5F10266DS
62. TRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 3 When reference voltage Voo ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI3 ANI16 to ANI22 internal reference voltage and temperature sensor output voltage Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Reference voltage Voo Reference voltage Vss Parameter Conditions Resolution 10 Nosa 10 bit resolution 7 0 10 5 Note 3 Overall error Conversion time 10 bit resolution 3 6 V lt VD 39 Target pin ANIO to ANI3 27V lt VD 39 ANI16 to ANI22 1 8 V lt VD 39 95 Conversion time 10 bit resolution 3 6 V lt VDI 39 Target pin internal reference 27V lt VD 39 voltage and temperature sensor output voltage HS high speed main mode 2 4V lt VD 39 Zero scale error Ss 10 bit resolution 0 60 0 85 Note 3 Full scale error s 10 bit resolution 0 60 0 85 Note 3 Integral linearity error 10 bit resolution 4 0 46 5 Note 3 Differential linearity error 10 bit resolution 2 0 425 Note 3 Analog input voltage ANIO to ANI3 ANI16 to ANI22 Voo Internal reference voltage Vacr e4 2 4 V lt VDD lt 5 5 V HS high speed main mode Temperature sensor output voltage Vimpsas No 4 2 4 V lt VDD lt 5 5 V HS high speed main mode Note
63. V 2 5 V 3 V CSI mode master mode SCKp internal clock output 1 3 Ta 40 to 105 C 2 4 V lt Voo lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode MIN MAX SCKp cycle time tkcy1 tkey1 gt 4 fcLk 4 0 V lt Voo lt 5 5 V 600 ns 2 7V lt Vos 4 0 V 30 pF Rb 1 4 KQ 2 7 V lt Von lt 4 0 V 1000 ns 2 3 V lt Vo lt 2 7 V Cb 30 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 2300 ns 1 6 V lt Vo lt 2 0 V 30 pF Rb 5 5 KQ SCKp high level width tkH1 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V tkcy1 2 150 ns C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V tkcy1 2 340 ns C 30 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V tkcy1 2 916 ns C 30 pF Rb 5 5 KQ SCKp low level width tku1 4 0 V lt Voo lt 5 5 V 2 7 V lt Veb lt 4 0 V tkcy1 2 24 ns C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Veb lt 2 7 V tkcy1 2 36 ns C 30 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V tkcy1 2 100 ns C 30 pF Rb 5 5 KQ Cautions 1 Select the TTL input buffer for the Slp pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vin and Vit see the DC characteristics with TTL input buff
64. a flash memory of 2 KB is mounted on the R5F102 products but not on the R5F103 products Product Data Flash R5F102 products R5F1026A R5F1027A R5F102AA R5F 10269 R5F10279 R5F102A9 R5F 10268 R5F10278 R5F102A8 R5F 10267 R5F10277 R5F102A7 R5F10266 Note R5F103 products R5F1036A R5F1037A R5F103AA R5F 10369 R5F10379 R5F103A9 R5F 10368 R5F10378 R5F103A8 R5F 10367 R5F10377 R5F103A7 R5F 10366 Not mounted Note The RAM in the R5F10266 has capacity as small as 256 bytes Depending on the customer s program specification the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory Caution When the flash memory is rewritten via a user program the code flash area and RAM area are used because each library is used When using the library refer to RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 5 of 106 ztENESAS RL78 G12 1 OUTLINE 1 3 2 On chip oscillator characteristics 1 High speed on chip oscillator oscillation frequency of the R5F102 products Oscillator High speed on chip Ta 20 to 85 C oscillator oscillation Ta 40 to 20 C frequency accuracy Ta 85 to 105 C 2 High speed on chip oscillator oscillation frequency of the R5F103 products High speed on chip Ta 40 to
65. age 69 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 1 20 24 pin products Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V 2 2 Parameter Conditions Supply loo2 HALT HS High speed fin 24 MHzNote4 Voo 5 0 V 440 2230 uA current 1 mode main modeN V 3 0 V 440 2230 fin 16 MHz 4 Voo 5 0 V 400 1650 uA Voo 3 0 V 400 1650 fmx 20 MHZ Square wave input 280 1900 uA Vo 5 0 V Resonator connection 450 2000 fmx 20 MHZ 3 Square wave input 280 1900 uA Voo 3 0 V Resonator connection 450 2000 fmx 10 MHz Square wave input 190 1010 uA Voo 5 0 V Resonator connection 260 1090 fmx 10 MHz Square wave input 190 1010 uA Voo 3 0 V Resonator connection 260 1090 loos e5 STOP Ta 40 C 0 19 0 50 uA mode T 25 C 0 24 0 50 Ta 50 C 0 32 0 80 Ta 70 C 0 48 1 20 Ta 85 C 0 74 2 20 Ta 105 C 1 50 10 20 Notes 1 Total current flowing into Vpp including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instru
66. al damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 AVrer side reference voltage of the A D converter 3 Vss Reference voltage RO1DS0193EJ0200 Rev 2 00 Page 63 of 106 Sep 0 201 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 2 Oscillator Characteristics 3 2 1 X1 oscillator characteristics Ta 40 to 105 C 2 4 V lt Voo lt Voo lt 5 5 V Vss 0 V X1 clock oscillation Ceramic resonator 2 7 V lt Voo lt 5 5 V MHz Note P Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator refer to 5 4 System
67. ance Vb V Communication line voltage 2 r IIC Number r 00 20 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 RO1DS0193EJ0200 Rev 2 00 Page 93 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 5 2 Serial interface IICA Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high speed main mode Standard Mode Fast Mode MIN MAX MIN MAX SCLAO clock frequency Fast mode fc k 2 3 5 MHz Normal mode fck gt 1 MHz Setup time of restart condition tsu sTa Hold time 1 tHD sTA Hold time when SCLAO L tow Hold time when SCLAO H tHIGH Data setup time reception tsu DaT Note 2 Data hold time transmission tHD DAT Setup time of stop condition tsu sto Bus free time tBuF Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of tHp pat is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution Only in the 30 pin products the values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the p
68. and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vi and Vit see the DC characteristics with TTL input buffer selected 2 CSI01 and CSI11 cannot communicate at different potential Remarks 1 R Q Communication line SCKp SOp pull up resistance Cb F Communication line SCKp SOp 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 KQ load capacitance V V Communication line voltage 2 p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 CSI mode connection diagram during communication at different potential lt Master gt RL78 microcontroller R01DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS User s device Page 87 of 106 RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy1 tki tkHi SCKp SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 SCKp SOp Output data Remark p CSI number p 00 20 m Unit number m 0 1 n Channel number n 0 R01D
69. angor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2013 Renesas Electronics Corporation All rights reserved Colophon 2 2
70. array unit operation clock frequency Operation clock to be set by the serial clock select register O SPSO and the CKSO0 bit of serial mode register 00 SMROO RO1DS0193EJ0200 Rev 2 00 Page 32 of 106 Sep 06 2013 RENESAS z RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 3 During communication at same potential CSI mode master mode SCKp internal clock output Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Symbol Conditions HS high speed LS low speed main Unit main Mode SCKp cycle time tkcy1 tkcy1 2 4 fcik 2 7 V lt Voo lt 5 5 V ep fe SCKp high low level width 4 0 V lt Voo lt 5 5 V tkcy1 2 12 tkcy1 2 50 Note 1 2 7 V lt Voo lt 5 5 V tkcy1 2 18 tkcy1 2 50 es 2 4 V lt Voo lt 5 5 V tkcy1 2 38 tkcy1 2 50 ons Sip setup time to SCKp1 40V lt V lt 55 V EEA Slp hold time from SCKp7 N Notes 1 Caution Note 3 1 8 V lt Voo lt 5 5 V 110 l 19 Delay time from SCKp to C 30 pF 4 SOp output When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp o
71. ash memory is rewritten via a user program the code flash area and RAM area are used because each library is used When using the library refer to RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual RO1DS0193EJ0200 Rev 2 00 Page 14 of 106 Sep 06 2013 ii RENESAS RL78 G12 Clock output buzzer output R5F1026x R5F1036x R5F1027x R5F1037x RSF 102Ax 1 2 44 kHz to 10 MHz Peripheral hardware clock fma 20 MHz operation 8 10 bit resolution A D converter 11 channels Serial interface R5F1026x 20 pin R5F1027x 24 pin CSI 2 channels Simplified IC 2 channels UART 1 channel R5F102Ax 30 pin CSI 1 channel Simplified IC 1 channel UART 1 channel CSI 1 channel Simplified IC 1 channel UART 1 channel CSI 1 channel Simplified IC 1 channel UART 1 channel R5F 1036x 20 pin R5F1037x 24 pin CSI 1 channel Simplified IC 0 channel UART 1 channel R5F103Ax 30 pin CSI 1 channel Simplified IC 0 channel UART 1 channel IC bus 1 channel Multiplier and divider multiply accumulator e 16 bits x 16 bits 32 bits unsigned or signed e 32 bits x 32 bits 32 bits unsigned e 16 bits x 16 bits 32 bits 32 bits unsigned or signed DMA controller 2 channels 2 channels 2 channels Vectored interrupt Internal 18 16 18 16 26 sources External Key interru
72. bers 4 Modification of Table 1 1 List of Ordering Part Numbers Note and Caution 7to9 Modification of package name in 1 4 1 to 1 4 3 14 Modification of tables in 1 7 Outline of Functions 17 Modification of description of table in 2 1 Absolute Maximum Ratings Ta 25 C 18 Modification of table Note and Caution in 2 2 1 X1 oscillator characteristics 18 Modification of table in 2 2 2 On chip oscillator characteristics 19 Modification of Note 3 in 2 3 1 Pin characteristics 1 4 20 Modification of Note 3 in 2 3 1 Pin characteristics 2 4 23 Modification of Notes 1 and 2 in 1 20 24 pin products 1 2 24 Modification of Notes 1 and 3 in 1 20 24 pin products 2 2 25 Modification of Notes 1 and 2 in 2 30 pin products 1 2 26 Modification of Notes 1 and 3 in 2 30 pin products 2 2 27 Modification of 3 Peripheral functions Common to all products 28 Modification of table in 2 4 AC Characteristics 29 Addition of Minimum Instruction Execution Time during Main System Clock Operation 30 Modification of figures of AC Timing Test Point and External Main System Clock Timing 31 Modification of figure of AC Timing Test Point 31 Modification of description and Note 2 in 1 During communication at same potential UART mode 32 Modification of description in 2 During communication at same potential CSI mode 33 Modification of description in 3 During communication at same potential CSI mode 34 Modification of description in 4 During communi
73. cation at same potential CSI mode 36 Modification of table and Note 2 in 5 During communication at same potential simplified C mode 38 39 Modification of table and Notes 1 to 9 in 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 40 Modification of Remarks 1 to 3 in 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 41 Modification of table in 7 Communication at different potential 2 5 V 3 V CSI mode 42 Modification of Caution in 7 Communication at different potential 2 5 V 3 V CSI mode 43 Modification of table in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 1 3 44 Modification of table and Notes 1 and 2 in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 2 3 45 Modification of table Note 1 and Caution 1 in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 3 3 47 Modification of table in 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 50 Modification of table Note 1 and Caution 1 in 10 Communication at different potential 1 8 V 2 5 V 3 V simplified IC mode 52 Modification of Remark in 2 5 2 Serial interface IICA 53 Addition of table to 2 6 1 A D converter characteristics 53 Modification of description in 2 6 1 1 54 Modification of Notes 3 to 5 in 2 6 1 1 54 Modification of description and Notes 2 to 4
74. ction execution by flash memory When high speed on chip oscillator clock is stopped When high speed system clock is stopped Not including the current flowing into the 12 bit interval timer and watchdog timer oa PF ON Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Voo 2 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fix high speed on chip oscillator clock frequency 3 Except temperature condition of the TYP value is Ta 25 C other than STOP mode RO1DS0193EJ0200 Rev 2 00 Page 70 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 30 pin products Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V 1 2 Parameter Conditions Supply Operating HS High speed fH 24 MHz Basic Voo 5 0 V mode main mode tNote 1 curren operation Vap 3 0 V Normal Voo 5 0 V operation Von 3 0 V fn 16 MHz Voo 5 0 V Voo 3 0 V fux 20 MHz Square wave input Vo 5 0 V Resonator connection fux 20 MHz Square wave input Vo 3 0 V Resonator connection fux 10 MHz Square wave input Vo 5 0 V Resonator connection fux 10 MHz Square wa
75. d main Mode MIN MAX Transfer rate N 1 a ate Theoretical value of the maximum transfer rate Note2 fcik fuck Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The maximum operating frequencies of the CPU peripheral hardware clock fcLk are HS high speed main mode 24 MHz 2 7 V lt Voo lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg UART mode connection diagram during communication at same potential RL78 User s device microcontroller UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 q UART number q 0 to 2 g PIM POM number g 0 1 2 fmck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 11 RO1DS0193EJ0200 Rev 2 00 Page 77 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 During communication at same potential CSI mode master mode SCKp internal clock output Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss
76. de During self HS High 2 7 V lt Voos 5 5 V 0 04167 o lajs mode LS Low 1 8 V lt Voo lt 5 5 V 0 125 1 US speed main mode External main system clock 2 7V lt Vo0 lt 5 5 V 10 200 me External main system clock texn tex 2 7 V lt Voo lt 5 5 V 2 fn input high level width low DAV lt Vope27V a ee width low level width 10 TOO0 to TOO7 output 4 0 V lt Voo lt 5 5 V frequency 2 7 V lt Voo lt 4 0 V 1 8 V lt Voo lt 2 7 V PCLBUZO or PCLBUZ1 4 0V lt Vp0 lt 5 5V output frequency 27V lt Vo0 lt 40V INTPO to INTP5 input high fica level width low level width KRO to KR9 input available width RESET low level width tRsL Remark _ fick Timer array unit operation clock frequency ae Operation clock to be set by the timer clock select register 0 TPSO and the CKSOn bit of timer mode register On TMROn n Channel number n 0 to 7 RO1DS0193EJ0200 Rev 2 00 Page 28 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt Minimum Instruction Execution Time during Main System Clock Operation Tey vs Voo HS high speed main mode 10 1 0 SS Se T 3 3 When the high speed on chip oscillator clock is selected 3 During self programming r When high speed system clock is selected E 2 S gt O 0 1 0 0625 0 04167 1 Jb 0 01 0 1 0 20 4 0 30 40
77. ectronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics rPENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara
78. ed for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 The pins mounted depend on the product Refer to 2 1 Port Functions to 2 2 1 Functions for each product in the RL78 G12 User s Manual Hardware RO1DS0193EJ0200 Rev 2 00 Page 16 of 106 see 2010 RENESAS _ RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C lt R gt Parameter Symbols Conditions Ratings Supply Voltage Voo 0 5 to 6 5 V REGC terminal input Virecc REGC 0 3 to 2 8 V voltage and 0 3 to Voo 0 3 Note 2 Input Voltage Vi Other than P60 P61 0 3 to Voo 0 39 V Viz P60 P61 N ch open drain 0 3 to 6 5 V Output Voltage Vo 0 3 to Voo 0 3 3 v Analog input voltage Vai 20 24 pin products ANIO to ANI3 ANI16 to ANI22 0 3 to Voo 0 3 V 30 pin products ANIO to ANI3 ANI16 to ANI19 and 0 3 to AVREF 0 3 Notes 4 Output current high lon1 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20 24 pin products P40 to P42 70 mA 30 pin products POO
79. eleased POR and LVD reset must be released before the external reset is released lt 3 gt The TOOLO pin is set to the high level lt 4 gt Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark tsut Communication for the initial setting must be completed within 100 ms after the external reset is released during this period tsu Time to release the external reset after the TOOLO pin is set to the low level tHo Time to hold the TOOLO pin at the low level after the external reset is released excluding the processing time of the firmware to control the flash memory RO1DS0193EJ0200 Rev 2 00 Page 103 of 106 Sep 06 2013 RENESAS al RL78 G12 4 PACKAGE DRAWINGS 4 PACKAGE DRAWINGS 4 1 20 pin products R5F1026AASP R5F10269ASP R5F10268ASP R5F10267ASP R5F10266ASP R5F1036AASP R5F10369ASP R5F10368ASP R5F10367ASP R5F10366ASP R5F1026ADSP R5F10269DSP R5F10268DSP R5F10267DSP R5F10266DSP R5F1036ADSP R5F10369DSP R5F10368DSP R5F10367DSP R5F10366DSP lt R gt R5F1026AGSP R5F10269GSP R5F10268GSP R5F10267GSP R5F10266GSP lt R gt R5F1036AGSP R5F10369GSP R5F10368GSP R5F10367GSP R5F10366GSP JEITA Package Code RENESAS Code Previous Code MASS TYP g P LSSOP20 4 4x6 5 0 65 PLSP0020JB A P20MA 65 NAA 1 0 1 x2 detail of lead end i c L i HE UNIT mm ITEM DIMENSIO
80. en duty lt 70 3 20 24 pin products 4 0 V lt Voo lt 5 5 V Total of POO to PO03 4 P10 to P14 2 4 V lt Voo lt 2 7 V 2 7 V lt Voo lt 4 0 V 30 pin products Total of P10 to P17 P30 P31 P50 P51 P147 When duty lt 70 3 Total of all pins When duty lt 70 3 Per pin for P20 to P23 2 4 V lt Voo lt 2 7 V Total of all pins value of current at which the device operation is guaranteed even if the current flows from the Voo pin to an output pin However do not exceed the total current value The output current value under conditions where the duty factor lt 70 If duty factor gt 70 The output current value can be calculated with the following expression where n represents the duty factor as a percentage e Total output current of pins loH x 0 7 n x 0 01 lt Example gt Where n 80 and loH 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 24 pin products only P10 to P12 and P41 for 20 pin products P01 P10 to P12 and P41 for 24 pin products and POO P10 to P15 P17 and P50 for 30 pin products do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pi
81. en high speed on chip oscillator and high speed system clock are stopped Current flowing only to the 12 bit interval timer excluding the operating current of the low speed on chip oscillator The current value of the RL78 microcontrollers is the sum of pp1 Ipp2 or Ipp3 and Ifi and ItwKa when the 12 bit interval timer operates Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The current value of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or Ibos and Iwot when the watchdog timer operates Current flowing only to the A D converter The current value of the RL78 microcontrollers is the sum of Ipp1 or Ipp2 and lanc when the A D converter operates in an operation mode or the HALT mode Current flowing only to the LVD circuit The current value of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or Ipp3 and ILvp when the LVD circuit operates Current flowing only during data flash rewrite Current flowing only during self programming For shift time to the SNOOZE mode see 17 3 3 SNOOZE mode in the RL78 G12 User s Manual Hardware Remarks 1 fit Low speed on chip oscillator clock frequency 2 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0200 Rev 2 00 Page 73 of 106 Sep 06 2013 ztENESAS RL78 G12 3 4 AC Characteristics Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Instruction cycle minimum instruction execution t
82. ent potential 1 8 V 2 5 V 3 V simplified Pc mode Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode MIN MAX SCLr clock frequency fsc 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 100 kHz Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V 100 kHz Co 100 pF Rb 2 7 KQ 2 4 V lt Von lt 3 3 V 1 6 V lt Vo lt 2 0 V 100 kHz Co 100 pF Rb 5 5 KQ Hold time when SCLr L tow 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 4600 ns Co 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 4600 ns Co 100 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 4650 ns Cb 100 pF Rb 5 5 KQ Hold time when SCLr H tHicH 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V 2700 ns Cb 100 pF Rb 2 8 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 2400 ns Co 100 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 1830 ns Co 100 pF Rb 5 5 KQ Data setup time reception tsu DaT 4 0 V lt Vm lt 5 5 V 2 7 V lt Vo lt 4 0 V 1 fuck ns C 100 pF Rb 2 8 KQ 760 Notes 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 1 fuck ns Cb 100 pF Rb 2 7 KQ 760 N73 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 1 fuck ns Note3 Cb 100 pF Rb 5 5 KQ 570 Data hold time transmission tH
83. ep 06 2013 ztENESAS Page 41 of 106 RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 When DAPOO 0 and CKP00 0 or DAPOO 1 and CKPOO 1 2 When DAPOO 0 and CKPOO 1 or DAPOO 1 and CKPO0 0 lt R gt Caution Select the TTL input buffer for the SI00 pin and the N ch open drain output Von tolerance mode for the SO00 pin and SCKO0 pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For V and Vit see the DC characteristics with TTL input buffer selected Remarks 1 Rb Q Communication line SCKO0 SOOO pull up resistance C F Communication line SCKO0 SO00 load capacitance Vb V Communication line voltage 2 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register O SPSO and the CKSOO bit of serial mode register 00 SMROO RO1DS0193EJ0200 Rev 2 00 Page 42 of 106 Sep 06 2013 RENESAS z RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 1 3 Ta 40 to 85 C 1 8 V lt Voo lt Voo lt 5 5 V Vss 0 V Parameter SCKp cycle time Conditions HS high speed main LS low speed main Mode Mode MIN MAX MIN MAX tkcy1 gt 4 ferk 4 0 V lt Voo lt 5 5 V 2 7 V lt V b lt 4 0V C 30 pF Rb 1 4 KQ 2 7 V lt V
84. er s device microcontroller Simplified IC mode serial transfer timing during communication at same potential 1 fscL SCLr SDAr HD DAT tsu DAT Remarks 1 R Q Communication line SDAr pull up resistance Cb F Communication line SCLr SDAr load capacitance 2 r IlC number r 00 01 11 20 h POM number h O 1 4 5 3 fick Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number 0 1 3 4 Simplified IC mode is supported only by the R5F102 products RO1DS0193EJ0200 Rev 2 00 Page 37 of 106 Sep 06 2013 RENESAS z RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Symbol Conditions HS high speed LS low speed main Mode main Mode Transfer Reception 4 0 V lt Vom lt 5 5 V Note4 rate 2 7 V lt V lt 4 0V Theoretical value of the maximum transfer rate Note3 fuck fck 2 7 V lt Voo lt 4 0 V 2 3 V lt V lt 2 7 V Theoretical value of the maximum transfer rate Note3 fuck fck 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V Theoretical value of the maximum transfer rate Note3 fuck fck Transmission 4 0 V lt Voo lt 5 5 V
85. er selected 2 CSI01 and CSI11 cannot communicate at different potential Remarks 1 R Q Communication line SCKp SOp pull up resistance Cb F Communication line SCKp SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 RO1DS0193EJ0200 Rev 2 00 Page 85 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 2 3 Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode MIN MAX Slp setup time to SCKp 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V role Cp 30 pF Ro 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V C 30 pF Rb 2 7 kQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5 5 kQ Slp hold time 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V from SCKp7 Cp 30 pF Re 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 30 pF Rb 2 7 kQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 30 pF Rb 5 5 KQ Delay time from SCKp to 4 0 V lt Voo lt 5 5 V 2 7 V lt Vo lt 4 0 V SOp output C 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Rb 2 7 KQ 2 4 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V C 30 pF Rb 5
86. erp Reference voltage AVrerm 0 V Parameter Conditions Resolution RES 8 10 bit Overall error AINL 10 bit resolution 1 2 3 5 LSB AVreFP Vop Note Conversion time tconv 10 bit resolution 3 6 V lt VDD lt 5 5 V 2 125 39 Ls Target pin ANI2 ANI3 9 7 V lt Voo lt 5 5V 3 1875 39 us 2 4 V lt VDD lt 5 5 V 17 39 Ls 10 bit resolution 3 6V lt Vpp lt 5 5 V 2 375 39 Ls Target pin Internal 2 7V lt V0 lt 5 5V 3 5625 39 US reference voltage and 2 4 V lt VDD lt 5 5 V 17 39 Ls temperature sensor output voltage HS high speed main mode Zero scale errorN s EZS 10 bit resolution 0 25 FSR AVrerp Vop Note Full scale error s 1 EFS 10 bit resolution 0 25 FSR AVrerp Vop Notes Integral linearity errorN ILE 10 bit resolution 2 5 LSB AVrerp Voo Notes Differential linearity error DLE 10 bit resolution 1 5 LSB Note 1 AVrerp Voo Notes Analog input voltage VAIN ANI2 ANI3 0 AVREFP V Internal reference voltage Veer No 4 v HS high speed main mode Temperature sensor output voltage Vrmps25 Note 4 V HS high speed main mode Notes are listed on the next page RO1DS0193EJ0200 Rev 2 00 Page 95 of 106 Sep 06 2013 ii RENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full
87. exposed die pad to Vss RO1DS0193EJ0200 Rev 2 00 Page 8 of 106 Sep 06 2013 RENESAS m RL78 G12 1 OUTLINE 1 4 3 30 pin products lt R gt 30 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch O Y N 5 Z gt lt D q P20 ANIO AVrere O 1 P01 ANI16 TOOO RxD1 O 2 O P22 ANI2 P00 ANI17 TO00 TxD1 O 3 O P23 ANI3 P120 ANI19 O 4 O P147 ANI18 P40 TOOLO O 5 O P10 SCK00 SCL00 T107 TO07 RESET O 6 O P11 SI00 RxDO0 TOOLRxD SDA00 T106 TO06 P137 INTPO O 7 O P12 SO00 TxD0 TOOLTxD TI05 TO05 P122 X2 EXCLK O 8 O P13 TxD2 SO20 SDAAO T104 TO04 P121 X1 O P14 RxD2 S120 SDA20 SCLA0 T103 TO03 REGC O 10 O P15 PCLBUZ1 SCK20 SCL20 T102 TO02 Vss O _ 11 O P16 TI01 TOO1 INTP5 RxDO Voo O _ 12 O P17 T102 T002 TxD0 P60 SCLA0 O O PSO INTP1 SI1 1 P61 SDAAO O O PS51 INTP2 SO11 SDA11 O P30 INTP3 SCK11 SCL11 Note Provided only in the R5F102 products Caution Connect the REGC pin to Vss via capacitor 0 47 to 1 WF Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G12 User s Manual Hardware RO1DS0193EJ0200 Rev 2 00 Page 9 of 106 Sep 06 2013 RENESAS m RL78 G12 1 OUTLINE 1 5 Pin Identification ANIO to ANI
88. fmck 40 2 4 V lt Voo lt 3 3 V 1 6 V lt Voo lt 2 0 V 1 fmck 60 Slp hold time from SCKp7 te 1 fmck 62 Delay time from SCKp1 to 4 0 V lt Voo lt 5 5 V 2 7 V lt Veb lt 4 0 V 2 fuck Note 4 SOp output Cp 30 pF Ro 1 4 KQ 240 2 7 V lt Voo lt 4 0 V 2 3 V lt Vo lt 2 7 V 2ifuck Cp 30 pF Ro 2 7 KQ 428 2 4 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V 2ifuck C 30 pF Ro 5 5 kQ 1146 Notes 1 Transfer rate in the SNOOZE mode MAX 1 Mbps 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpJv when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp1 when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Cautions 1 Select the TTL input buffer for the Sip and SCKp pins and the N ch open drain output Voo tolerance mode for the SOp pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vin and Vit see the DC characteristics with TTL input buffer selected 2 CSI01 and CSI11 cannot communicate at different potential RO1DS0193EJ0200 Rev 2 00 Page 89 of 106 Sep 06 2013 ztENESAS RL
89. fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 1 3 RO1DS0193EJ0200 Rev 2 00 Page 78 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 During communication at same potential CSI mode slave mode SCKp external clock input Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode MIN MAX SCKp cycle time 4 tkcy2 4 0 V lt Voo lt 5 5 V 20 MHz lt fuck 16 fmck ns fuck lt 20 MHz 12 fuck ns 2 7 V lt Voo lt 5 5 V 16 MHz lt fuck 16 fmcK ns fuck lt 16 MHz 12 fuck ns 2 4V lt Vpn lt 5 5 V 12 fuck ns and 1000 SCKp high low level width tkx2 4 0V lt Vo lt 5 5V tkcy2 2 14 ns tkl2 2 7 V lt Vo lt 5 5 V tkcy2 2 16 ns 2 4 V lt Voo lt 5 5 V tkcy2 2 36 ns Slp setup time to SCKp tsix2 2 7 V lt Voo lt 5 5 V 1 fuck 40 ns 24V lt Vo0 lt 5 5V 1 fmck 60 ns Slp hold time tksi2 1 fuck 62 ns from SCKp7 Ne Delay time from SCKpJ to tksoz C 30 pF N 2 7V lt Vo0 lt 5 5V 2ffuck 66 ns SOp output 2 4V lt Vo0 lt 5 5V 2u 113 ns Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip setup time becomes
90. g BCD adjustment Multiplier amp divider multiply accumulator SCLAO SDAAO ICAO Code flash 16 KB Data flash 2 KBN Interrupt control K gt KS 5 P10 to P14 A Pome K gt r v P23 lt 7 3_ gt P40 to P42 KZ Ponte K 2 gt Pen P61 O rome ka P121 P122 P125 Ae jee Buzzer clock a output control PCLBUZO Key return Y Sn 6_ KRO to KR5 INTPO to INTP3 Interrupt control 4ch Clock Generator Reset Generator Power on reset voltage on detector i Voo Vss Note Provided only in the R5F102 products High Speed Main OSC 1 to 20 MHz X1 X2 EXCLK chip oscillator to 24 MHz TOOL TOOL TxD RxD Low Speed On chip oscillator 15 kHz ANI2 ANI3 ANI16 to ANI22 ANIO AVrEFP ANI1 AVREFM RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 11 of 106 RL78 G12 1 OUTLINE 1 6 2 24 pin products TAUO 4ch TI00 TOOO T101 TOO1 T102 TOO2 T103 TOO3 RxDO TxDO SCKOO S100 S000 SCK01 S101 S001 SCLOO SDA00 SCLO1 SDAO1 TOOLO On chip debug _ BCD adjustment a Multiplier amp divider multiply accumulator ICAO SCLAO SDAAO ICAO Code flash 16 KB Data flash 2 KBN Interrupt control DM ANote Jap 2ch ee ofan ko Lake flee ke ee ka Lem ofa Ea aa arga gontrol n CE Ky Window watchdog Clock
91. i i i tuo software i i processing 1 byte data for time setting mode lt R gt i TOOLO i f f tsu tsuiniT pt peers 1 1 1 1 1 1 1 1 pe l lt 1 gt The low level is input to the TOOLO pin lt 2 gt The external reset is released POR and LVD reset must be released before the external reset is released lt 3 gt The TOOLO pin is set to the high level lt R gt lt 4 gt Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark tsut Communication for the initial setting must be completed within 100 ms after the external reset is released during this period tsu Time to release the external reset after the TOOLO pin is set to the low level lt R gt tHo Time to hold the TOOLO pin at the low level after the external reset is released excluding the processing time of the firmware to control the flash memory RO1DS0193EJ0200 Rev 2 00 Page 61 of 106 Sep 06 2013 RENESAS al RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C lt R gt 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C This chapter describes the electrical specifications for the products G Industrial applications Ta 40 to 105 C Cautions 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed
92. ime Main system clock fMAIN operation 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Conditions HS High 2 7 V lt Voo lt 5 5 V 0 04167 speed main mode 2 4 V lt Voo lt 2 7 V 0 0625 During self programming HS High 2 7 V lt Voo lt 5 5 V 0 04167 speed main mode 2 4 V lt Voo lt 2 7 V 0 0625 External main system clock frequency 2 7 V lt Voo lt 5 5 V 1 0 2 4 V lt Voo lt 2 7 V 1 0 External main system clock input high level width Ilow level width EXH tex 2 7 V lt Voo lt 5 5 V 24 2 4 V lt Voo lt 2 7 V 30 TIOO to TIO7 input high level width low level width TOO0O0 to TOO7 output frequency 4 0 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 0 V 2 4 V lt Voo lt 2 7 V PCLBUZO or PCLBUZ1 output frequency 4 0 V lt Voo lt 5 5 V 2 7 V lt Voo lt 4 0 V 2 4 V lt Voo lt 2 7 V INTPO to INTP5 input high level width low level width NTH tINTL KRO to KR9 input available width RESET low level width Remark Operation clock to be set by the timer clock select register 0 TPSO and the CKSOn bit of timer mode fuck Timer array unit operation clock frequency register On TMROn n Channel number n 0 to 7 RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 74 of 106 RL78 G12 3 ELECTRICAL SPECIFICAT
93. in characteristics loH1 lot1 Vou1 Voi1 must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Normal mode Cb 400 pF Rb 2 7 kQ Fast mode Cb 320 pF Rb 1 1 KQ IICA serial transfer timing tHD sTA TtHD STA Stop Start Restart Stop condition condition condition condition RO1DS0193EJ0200 Rev 2 00 Page 94 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 6 Analog Characteristics 3 6 1 A D converter characteristics Classification of A D converter characteristics Input channel Reference Voltage Reference voltage AVREFP Reference voltage VDD Reference voltage VBGR Reference voltage AVREFM Reference voltage Vss Reference voltage AVREFM ANIO to ANI3 Refer to 3 6 1 1 Refer to 3 6 1 3 Refer to 3 6 1 4 ANI16 to ANI22 Refer to 3 6 1 2 Internal reference voltage Refer to 3 6 1 1 Temperature sensor output voltage 1 When reference voltage AVrerr ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pin ANI2 ANI3 internal reference voltage and temperature sensor output voltage Ta 40 to 105 C 2 4 V lt AVrerp lt VDD lt 5 5 V Vss 0 V Reference voltage AVr
94. istics of alternate function pins are the same as those of the port pins 2 AVrer side reference voltage of the A D converter 3 Vss Reference voltage RO1DS0193EJ0200 Rev 2 00 Page 17 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 2 Oscillator Characteristics 2 2 1 X1 oscillator characteristics Ta 40 to 85 C 1 8 V lt Voo lt Voo lt 5 5 V Vss 0 V X1 clock oscillation Ceramic resonator 2 7 V lt Voo lt 5 5 V 1 0 MHz Note P lt R gt Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics lt R gt Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator refer to 5 4 System Clock Oscillator in the RL78 G12 User s Manual Hardware 2 2 2 On chip oscillator characteristics Ta 40 to 85 C 1 8 V lt Voo lt
95. le value 3 When AVrere lt Von the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVrerp Vov Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVrere Voo Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVrere Vo RO1DS0193EJ0200 Rev 2 00 Page 96 of 106 Sep 06 2013 RENESAS al RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 When reference voltage Voo ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI3 ANI16 to ANI22 internal reference voltage and temperature sensor output voltage Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Reference voltage Voo Reference voltage Vss Parameter Conditions Resolution Note 1 Overall error 10 bit resolution Conversion time 10 bit resolution 3 6 V lt VD Target pin ANIO to ANI3 27V lt VD ANI16 to ANI22 2 4 V lt VD Conversion time 10 bit resolution 3 6 V lt VD Target pin internal reference 27V lt VD voltage and temperature sensor output voltage HS high speed main mode 2 4 V lt VD Notes 1 2 Zero scale error 10 bit resolution Notes 1 2 Full scale error 10 bit resolution Note 1 Integral linearity error 10 bit resolution Note 1 10 bit resolution Differential linearity error Analog input voltage A
96. lling reset voltage 1 84 za Penne ee Vrocz Vroc1 Vroco 0 1 0 falling reset voltage KARA za eee see ea Vpoc2 Veoci1 Veoci 0 1 1 falling reset voltage Ea EA a a or lt R gt 2 6 5 Power supply voltage rising slope characteristics Ta 40 to 85 C Vss 0 V Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 2 4 AC Characteristics RO1DS0193EJ0200 Rev 2 00 Page 59 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is affected but data is not retained when a POR reset is affected l STOP mode Operation mode Data retention mode gt Voo 4 STOP instruction execution Standby release signal interrupt request 2 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Conditions System clock frequency Code flash memory rewritable times Retained for 20 years Notes 1 2 3 Data flash memory rewritable times Retained for 1 year 1 000 000 Notes 1 2 3 Retained for 5 years 100 000 Retained for 20
97. lt 5 5 V lott 3 0 mA 2 7 V lt Von lt 5 5 V lott 1 5 mA 2 4V lt Von lt 5 5 V lot1 0 6 mA P20 to P23 loc2 400 A P60 P61 4 0 V lt Vo lt 5 5 V lott 15 0 mA 4 0 V lt Vo lt 5 5 V lot1 5 0 mA 2 7V lt Von lt 5 5 V lot1 3 0 mA 2 4V lt Von lt 5 5V lott 2 0 mA Input leakage current high Other than P121 P122 P121 P122 X1 X2 EXCLK Input port or external clock input When resonator connected Input leakage current low Other than P121 P122 P121 P122 X1 X2 EXCLK Input port or external clock input When resonator connected On chip pull up resistance Note 24 pin products only 20 24 pin products POO to P03 P10 to P14 P40 to P42 P125 RESET 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 Vi Vss input port Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 68 of 106 RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 3 2 Supply current characteristics 1 20 24 pin products Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V 1 2 Supply loot Operating HS High speed fin 24 MHz Basic Voo 5 0 V of as mA Note 1 Note 4 current main
98. marks are listed on the next page RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 50 of 106 RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Simplified C mode connection diagram during communication at different potential SDAr RL78 F User s device microcontroller SCLr SCL Simplified 17 C mode serial transfer timing during communication at different potential 1 fscL trow tHIGH SCLr SDAr HD DAT tsu DAT Remarks 1 Rb Q Communication line SDAr SCLr pull up resistance C F Communication line SDAr SCLr load capacitance Vb V Communication line voltage 2 r IIC Number r 00 20 3 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 4 Simplified C mode is supported only by the R5F102 products RO1DS0193EJ0200 Rev 2 00 Page 51 of 106 Sep 06 2013 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 5 2 Serial interface IICA Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high speed main mode LS low speed main mode Standard Mode Fast Mode MIN MAX MIN MAX SCLAO clock frequency Fast mode fc k 2 3 5 MHz Normal mode fctk gt 1 MHz Setup
99. n fux 10 MHz Square wave input Voo 5 0V Resonator connection fux 10 MHz Square wave input Voo 3 0 V Resonator connection LS Low speed fmx 8 MHz Square wave input Note 4 main mode Vo 3 0V Resonator connection fux 8 MHZ Square wave input Vo 2 0V Resonator connection lt R gt Notes 1 Total current flowing into Vpp including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite lt R gt 2 When high speed on chip oscillator clock is stopped 3 When high speed system clock is stopped 4 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vop 2 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vopp 1 8 V to 5 5 V 1 MHz to 8 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH high speed on chip oscillator clock frequency 3 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0200 Rev 2 00 Page 23 of 106 se 2010 RENESAS _ RL78 G12 2 ELECTRICAL SPECIFICATIONS A
100. n ANI16 to ANI22 Ta 40 to 85 C 1 8 V lt AVrerp lt Voo lt 5 5 V Vss 0 V Reference voltage AVrerr Reference voltage AVrerm 0 V Parameter Conditions Resolution Note 1 10 bit resolution Note 3 AVrere Voo Overall error Conversion time 10 bit resolution 3 6 V lt VoD lt 5 5 V 39 Target ANI pin ANI16 to ANI22 27V lt Vpp lt 55V 39 1 8V lt Vpp lt 5 5V 39 95 Zero scale error Ns t 10 bit resolution 0 35 AVrerp Voo Ne 0 60 Note4 Full scale error 10 bit resolution 0 35 AVrere Vp Note 0 60 Note4 Integral linearity error 10 bit resolution 43 5 1 AVrerp Vop e3 46 0 Notes Differential linearity 10 bit resolution 2 0 error Note AVrerp Voo Note 8 49 5 Note 4 Analog input voltage ANI16 to ANI22 AVREFP and Voo Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVrere lt Vm the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVrere Voo Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVrere Voo Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVrere Voo 4 When the conversion time is set to 57 ws min and 95 ws max RO1DS0193EJ0200 Rev 2 00 Page 54 of 106 Sep 06 2013 RENESAS E RL78 G12 2 ELEC
101. n anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and acc
102. n be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G12 User s Manual Hardware RO1DS0193EJ0200 Rev 2 00 Page 7 of 106 Sep 06 2013 RENESAS m RL78 G12 1 OUTLINE 1 4 2 24 pin products lt R gt e 24 pin plastic HWQFN 4 x 4 mm 0 5 mm pitch O P10 ANI16 PCLBUZ0 SCK00 SCLOO O P11 ANI17 SI00 SDA00 TOOLRxD O P12 ANI18 SO00 TxDO TOOLTxD O P13 ANO19 TIOO ONTP2 O P14 ANO20 TI01 ONTP3 2 Zz lt fe N A O 1817 16 15 14 13 exposed die pad P22 ANI2 O P61 KR5 SDAA00 RxD0 P21 ANI1 AVrerm O O P60 KR4 SCLAO TxDO P20 ANIO AVrere O 10 O P03 KR9 P42 ANI21 SCK01 SCLO1 T103 TO03O 9 O P02 KR8 SCK01 SCLO01 P41 ANI22 S001 SDA01 T102 TOO2 INTP1O O P01 KR7 SO01 yNeteSDAO1 yNete P40 KR0 TOOLO O bd 7 O POO KR6 S101 yNete INDEX MARK 000000 oznauva N D HWonass EEE melee To Sn F EE Sieg ey ae lt r E xX E Of 1O W y N as i X A oo Xx hn N N a Note Provided only in the R5F102 products Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G12 User s Manual Hardware lt R gt 3 It is recommended to connect an
103. n chip oscillator The current value of the RL78 microcontrollers is the sum of pp1 Ipp2 or Ipp3 and Ifi and ItwKa when the 12 bit interval timer operates Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The current value of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or Ibos and Iwot when the watchdog timer operates Current flowing only to the A D converter The current value of the RL78 microcontrollers is the sum of Ipp1 or Ipp2 and lanc when the A D converter operates in an operation mode or the HALT mode Current flowing only to the LVD circuit The current value of the RL78 microcontrollers is the sum of Ipp1 Ipp2 or Ipp3 and ILvp when the LVD circuit operates Current flowing only during data flash rewrite Current flowing only during self programming For shift time to the SNOOZE mode see 17 3 3 SNOOZE mode in the RL78 G12 User s Manual Hardware Low speed on chip oscillator clock frequency RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 27 of 106 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 4 AC Characteristics Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Instruction cycle minimum Main system HS High 2 7V lt Vo0 lt 5 5V 0 04167 mp Tn instruction execution time clock fMAIN speed main 24V lt Vo lt 27V 0 0625 us operation mode LS Low 1 8 V lt Voo lt 5 5 V 0 125 1 us speed main mo
104. ng flash memory programmer and Renesas Electronics self programming library 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation RO1DS0193EJ0200 Rev 2 00 Page 102 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 9 Dedicated Flash Memory Programmer Communication UART Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V 3 10 Timing of Entry to Flash Memory Programming Modes Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V Parameter Conditions Time to complete the communication for the initial tsuinit POR and LVD reset are released setting after the external reset is released before external release Time to release the external reset after the TOOLO tsu POR and LVD reset are released pin is set to the low level before external release Time to hold the TOOLO pin at the low level after the POR and LVD reset are released external reset is released before external release excluding the processing time of the firmware to control the flash memory A See ee cee eee eee ee Vv RESET lt I gt lt 2 gt lt 3 gt tuo software processing 1 byte data for time setting mode TOOLO a ees tsu tsuiniT y 1 1 1 1 1 1 1 i 1 pe l lt 1 gt The low level is input to the TOOLO pin lt 2 gt The external reset is r
105. ns are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Page 65 of 106 Sep 06 2013 ztENESAS RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Ta 40 to 105 C 2 4 V lt Von lt 5 5 V Vss 0 V 2 4 Parameter Conditions Output current low Note 1 20 24 pin products Per pin for POO to PO3 4 P10 to P14 P40 to P42 30 pin products Per pin for POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 Per pin for P60 P61 20 24 pin products 4 0 V lt Voo lt 5 5 V Total of P40 to P42 27V lt Vo lt 40V 30 pin products 24V lt Vo lt 27V Total of POO P01 P40 P120 When duty lt 70 20 24 pin products 4 0 V lt Voo lt 5 5 V Note 4 Total of POO to P03 27V lt Vp0 lt 4 0V P10 to P14 P60 P61 2 4 V lt Voo lt 2 7 V 30 pin products Total of P10 to P17 P30 P31 P50 P51 P60 P61 P147 When duty lt 70 Total of all pins When duty lt 70 Per pin for P20 to P23 Total of all pins Notes 1 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the Vss pin 2 However do not exceed the total current value 3 The output current value under conditions where the duty factor lt 70 If duty factor gt 70 The output current value can be calculated with the following expression where n represents
106. ntellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life suppo
107. o P42 4 0 V lt V lt 5 5V Voo 0 7 V 30 pin products lon1 3 0 mA P00 P01 P10 to P17 P30 37y lt Vws lt 5 5V Voo 0 6 v P31 P40 P50 P51 P120 _ lon1 2 0 mA P147 1 8V lt Vo0 lt 5 5V Voo 0 5 v lon1 1 5 mA Notes 1 20 24 pin products only Output voltage high 2 24 pin products only Caution The maximum value of Vin of pins P10 to P12 and P41 for 20 pin products P01 P10 to P12 and P41 for 24 pin products and P00 P10 to P15 P17 and P50 for 30 pin products is Voo even in N ch open drain mode High level is not output in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Page 21 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 4 4 Output voltage low Input leakage current high Input leakage current Iu low On chip pull up resistance Note 24 pin products only 20 24 pin products 4 0 V lt Voo lt 5 5 V POO to PO3 P10 to P14 lonn 20 0 mA P40 to P42 4 0 V lt V lt 5 5V 30 pin products POO P01 lou 8 5 mA P10 to P17 P30 P31 P40 P50 P51 P120 P147 2 7 V lt Voo lt 5 5V lott 3 0 mA 2 7 V lt Von lt 5 5 V lor 1 5 MA 1 8 V lt Voo lt 5 5 V lott 0 6 mA P20 to P23 lorz 400 4A
108. ode Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions HS high speed main Mode LS low speed main Mode MIN MAX SCLr clock frequency 1 8 V lt Voo lt 5 5 V C 100 pF Rb 3 KQ 1 8 V lt Voo lt 2 7 V Cp 100 pF Rb 5 KQ Hold time when SCLr L 1 8 V lt Voo lt 5 5 V Cp 100 pF Rb 3 kQ 1 8V lt Vo0 lt 2 7V Cp 100 pF Ro 5 KQ Hold time when SCLr H 1 8V lt Vp0 lt 5 5 V C 100 pF Rb 3 kQ 1 8V lt Vp0 lt 2 7V 1550 C 100 pF Rb 5 kQ Data setup time reception tsu DaT 1 8 V lt Voio lt 5 5 V 1 fmek 145 No 2 C 100 pF Rb 3 kQ 1 8 V lt Voo lt 2 7 V 1 fmck 230 N 2 Cb 100 pF Rb 5 kQ Data hold time transmission 1 8 V lt Voo lt 5 5 V C 100 pF Rb 3 kQ 1 8V lt Vo0 lt 2 7V C 100 pF Rb 5 kQ Notes 1 The value must also be equal to or less than fuck 4 lt R gt 2 Set tsu pat so that it will not exceed the hold time when SCLr L or SCLr H Caution Select the N ch open drain output Voo tolerance mode for SDAr by using port output mode register h POMh Remarks are listed on the next page RO1DS0193EJ0200 Rev 2 00 Page 36 of 106 Sep 06 2013 RENESAS al RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Simplified C mode connection diagram during communication at same potential Voo Fa SDA SCL RL78 g Us
109. of transferred bits Baud rate error theoretical value This value is the theoretical value of the relative difference between the transmission and reception sides 9 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer lt R gt Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output Voo tolerance mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For Vi and Vit see the DC characteristics with TTL input buffer selected RO1DS0193EJ0200 Rev 2 00 Page 39 of 106 Sep 06 2013 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C UART mode connection diagram during communication at different potential RL78 User s device microcontroller RxDq UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq lt R gt Remarks 1 Rp Q Communication line TxDq pull up resistance C F Communication line TxDq load capacitance V V Communication line voltage lt R gt 2 q UART number q 0 to 2 g PIM and POM number g 0 1 lt R
110. onverter characteristics Input channel Reference Voltage Reference voltage AVREFP Reference voltage VDD Reference voltage VBGR Reference voltage AVREFM Reference voltage Vss Reference voltage AVREFM ANIO to ANI3 Refer to 2 6 1 1 Refer to 2 6 1 3 Refer to 2 6 1 4 ANI16 to ANI22 Refer to 2 6 1 2 Internal reference voltage Refer to 2 6 1 1 Temperature sensor output voltage lt R gt 1 When reference voltage AVrerr ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pin ANI2 ANI3 internal reference voltage and temperature sensor output voltage Ta 40 to 85 C 1 8 V lt AVrerr lt VDD lt 5 5 V Vss 0 V Reference voltage AVrerr Reference voltage AVrerm 0 V Parameter Conditions Resolution 10 Note 1 10 bit resolution 3 5 AVrerp Voo Notes 70 Note4 Overall error Conversion time 10 bit resolution DD lt 5 5 V 39 Target pin ANI2 ANI3 DD lt 5 5 V 39 DD lt 5 5 V 39 95 10 bit resolution DD lt 5 5 V 39 Target pin Internal DD lt 5 5 V 39 reference voltage and temperature sensor output voltage HS high speed main mode DD lt 5 5 V 39 Notes 1 2 10 bit resolution 0 25 AVrerp Vp Note 0 50 Noe 4 Zero scale error Notes 1 2 10 bit resolution 0 25 AVrerp Vop e3 0 50 Note4 Full scale e
111. oo lt 4 0 V 2 3 V lt V lt 2 7 V 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 V C 30 pF Rb 5 5 KQ SCKp high level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V tkcy1 2 75 tkcy1 2 75 Cb 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V tkcy1 2 170 tkcy1 2 170 C 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V Note tkcy1 2 458 tkcy1 2 458 Cb 30 pF Rb 5 5 KQ SCKp low level width 4 0 V lt Voo lt 5 5 V 2 7 V lt Vb lt 4 0 V tkcy1 2 12 tkcy1 2 50 30 pF Rb 1 4 KQ 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V tkcy1 2 18 tkcy1 2 50 Cb 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Ve lt 2 0 V Note tkcy1 2 50 tkcy1 2 50 Cb 30 pF Rb 5 5 KQ Note Use it with Voo Vb Cautions 1 Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance mode for the SOp pin and SCKp pin by using port input mode register 1 PIM1 and port output mode register 1 POM1 For Vin and Vu see the DC characteristics with TTL input buffer selected 2 CSI01 and CSI11 cannot communicate at different potential Remarks 1 Rb Q Communication line SCKp SOp pull up resistance C F Communication line SCKp SOp load capacitance Vb V Communication line voltage 2 p CSI number p 00 20 R
112. oo lt 5 5 V 1 8 V lt Voo lt 5 5 V 6 fuck and 750 SCKp high low level width 4 0 V lt Voo lt 5 5 V tkcy2 2 7 tkcy2 2 7 tkcy2 2 8 tkcy2 2 18 1 8 V lt Voo lt 5 5 V 2 7 V lt Vo0 lt s 5 5 V tkcy2 2 8 2 4 V lt Voo lt 5 5 V tkcy2 2 18 tkcy2 2 18 Slp setup time to SCKpT Note 1 fuck 30 1 fuck 20 2 7 V lt Voo lt 5 5 V 1 fuck 30 1 fuck 30 1 8 V lt Voo lt 5 5 V 2 4 V lt Voo lt 5 5 V 1 fuck 30 Slp hold time from SCKp7 Note 1 fuck 31 Delay time from SCKp1 to SOp output te Notes 1 Caution C 30 pF Note4 2 7 V lt Voo lt 5 5 V 2ffuck 110 2 4 V lt Voo lt 5 5 V 2ffuck 110 2 fuck 110 1 8 V lt Voo lt 5 5 V When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Sip setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 C is the load capacitance of the SOp output lines Transfer rate in the SNOOZE mode MAX 1 Mbps Select the normal input buffer for the Slp and SCKp pins
113. ording to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other i
114. ows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVRerm Integral linearity error Add 0 5 LSB to the MAX value when reference voltage AVrerm Differential linearity error Add 0 2 LSB to the MAX value when reference voltage AVRerm RO1DS0193EJ0200 Rev 2 00 Page 98 of 106 see 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 6 2 Temperature sensor internal reference voltage characteristics Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V HS high speed main mode Parameter Conditions Temperature sensor output voltage Vimps25 Setting ADS register 80H TA 25 C Internal reference voltage VBGR Setting ADS register 81H Temperature coefficient Fvtmps Temperature sensor output voltage that depends on the temperature Operation stabilization wait time 3 6 3 POR circuit characteristics Ta 40 to 105 C Vss 0 V Parameter Conditions Detection voltage Power supply rise time Power supply fall time Minimum pulse width Note Minimum time required for a POR reset when Voo exceeds below Veor This is also the minimum time required for a POR reset from when Voo exceeds below 0 7 V to when Voo exceeds Vror while STOP mode is entered or the main system clock is stopped through setting bit O HIOSTOP and bit 7 MSTOP in the clock operation status con
115. pt 6 Reset e Reset by RESET pin e Internal reset by watchdog timer e Internal reset by power on reset e Internal reset by voltage detector e Internal reset by illegal instruction execution e Internal reset by RAM parity error e Internal reset by illegal memory access Note Power on reset circuit e Power on reset 1 51 V TYP e Power down reset 1 50 V TYP Voltage detector e Rising edge 1 88 to 4 06 V 12 stages e Falling edge 1 84 to 3 98 V 12 stages On chip debug function Provided Power supply voltage Voo 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C A Consumer applications D Industrial applications Ta 40 to 105 C G Industrial applications Note The illegal instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the in circuit emulator or on chip debug emulator RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS 1 OUTLINE 8 channels Page 15 of 106 RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C This chapter describes the electrical specifications for the products A Consumer applications Ta 40 to 85 C and D Industrial applications Ta 40 to 85 C Cautions 1 The RL78 microcontrollers have an on chip debug function which is provid
116. retical value of the maximum transfer rate 50 pF Rb 5 5 KQ Vb 1 6 V Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The maximum operating frequencies of the CPU peripheral hardware clock fck are HS high speed main mode 24 MHz 2 7 V lt Voo lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V 3 The smaller maximum transfer rate derived by using fmcK 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt Voo lt 5 5 Vand 2 7 V lt Vb lt 4 0 V 1 Maximun transfer rate bps 2 2 Cb x Rb x In 1 3 1 2 2 Transfer rate x 2 fr Obt Ree e 1 Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides RO1DS0193EJ0200 Rev 2 00 Page 82 of 106 Sep 0 201 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 4 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer 5 The smaller maximum transfer rate derived by using fmck 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt Voo lt 4 0 V and 2 3 V lt V lt 2 7 V 1
117. rror Note 1 10 bit resolution a AVrerp Voo Notes 5 Note4 Integral linearity error Differential linearity error 10 bit resolution 1 5 Note 1 AVrerp Voo Notes 2 Note4 Analog input voltage ANI2 ANI3 AVREFP Internal reference voltage Veer Note 2 4 V lt VoD lt 5 5 V HS high speed main mode Temperature sensor output voltage Vimpsas No 2 4 V lt VoD lt 5 5 V HS high speed main mode Notes are listed on the next page RO1DS0193EJ0200 Rev 2 00 Page 53 of 106 Sep 06 2013 RENESAS lt R gt lt R gt lt R gt lt R gt lt R gt lt R gt lt R gt RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVrere lt Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVrere Vov Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVrere Von Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVrere Voo 4 Values when the conversion time is set to 57 ws min and 95 ws max 5 Refer to 2 6 2 Temperature sensor internal reference voltage characteristics 2 When reference voltage AVrerr ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pi
118. rt devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of ph
119. s P10 P11 3 3 V lt Voo lt 4 0 V 30 pin products P01 P10 2 4 V lt Voo lt 3 3 V P11 P13 to P17 P20 to P23 P60 P61 P121 P122 P125 1 P137 EXCLK RESET Output voltage high 20 24 pin products 4 0 V lt Vm lt 5 5 V POO to PO3N P10 to P14 lom 3 0 mA P40 to P42 2 7 V lt Von lt 5 5V 30 pin products lon1 2 0 mA P00 P01 P10 to P17 P30 oayevon lt 55 V P31 P40 P50 P51 P120 P147 P20 to P23 lon2 100 wA lon1 1 5 mA Notes 1 20 24 pin products only 2 24 pin products only Caution The maximum value of Vin of pins P10 to P12 and P41 for 20 pin products P01 P10 to P12 and P41 for 24 pin products and P00 P10 to P15 P17 and P50 for 30 pin products is Voo even in N ch open drain mode High level is not output in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins RO1DS0193EJ0200 Rev 2 00 Page 67 of 106 se 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V Parameter Output voltage low Conditions 20 24 pin products POO to P03 P10 to P14 P40 to P42 30 pin products POO P01 P10 to P17 P30 P31 P40 P50 P51 P120 P147 4 0 V lt Vo lt 5 5 V lott 8 5 mA 4 4 2 7V lt Von
120. s 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value lt R gt 3 When the conversion time is set to 57 ws min and 95 us max lt R gt 4 Refer to 2 6 2 Temperature sensor internal reference voltage characteristics RO1DS0193EJ0200 Rev 2 00 Page 55 of 106 Sep 06 2013 ii RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 4 When reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage AVrerm ADREFM 1 target pin ANIO ANI2 ANI3 and ANI16 to ANI22 Ta 40 to 85 C 2 4 V lt Voo lt 5 5 V Vss 0 V Reference voltage Vesar Reference voltage AVreFm Note 42 0 V HS high speed main mode Parameter Conditions Resolution Conversion time 8 bit resolution 39 Zero scale error 8 bit resolution 0 60 Integral linearity error 8 bit resolution 2 0 Differential linearity error N 8 bit resolution 1 0 Analog input voltage Vecer Note3 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value lt R gt 3 Refer to 2 6 2 Temperature sensor internal reference voltage characteristics lt R gt 4 When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVRerm
121. t Vb Cautions and Remarks are listed on the next page RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 ztENESAS Page 44 of 106 RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 3 3 Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Conditions HS high speed LS low speed main Mode main Mode MIN MAX MIN MAX Slp setup time 4 0 V lt Voo lt 5 5 V 2 7 V lt Ve lt 4 0 V to p b 30 pF Rb 1 4 KQ SCKpJ e1 C 30 pF Rb 1 4 ki 2 7 V lt Voo lt 4 0 V 2 3 V lt Vb lt 2 7 V 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V e C 30 pF Rb 5 5 KQ Slp hold time 4 0 V lt Voo lt 5 5 V 2 7 V lt V lt 4 0 V rom p b pF Ro 41 Q from SCKp4 et C 30 pF Rb 1 4 k 2 7 V lt Voo lt 4 0 V 2 3 V lt V lt 2 7 V Co 30 pF Rb 2 7 KQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vb lt 2 0 V e Co 30 pF Rb 5 5 KQ Delay time from 4 0 V lt Voo lt 5 5 V 2 7 V lt Ve lt 4 0 V SCKpT to Co 30 pF Ro 1 4 KQ Note 1 SOp output 2 7 V lt Voo lt 4 0 V 2 3 V lt Ve lt 2 7 V Co 30 pF Rb 2 7 kQ 1 8 V lt Voo lt 3 3 V 1 6 V lt Vo lt 2 0 vy Note 2 C 30 pF Rb 5 5 kQ lt R gt Notes 1 When DAPmn
122. time of restart condition tsu sTa Hold time 1 tHD sTA Hold time when SCLAO L tow Hold time when SCLAO H tHicH Data setup time reception tsu DaT Note 2 Data hold time transmission tHD DAT Setup time of stop condition tsu sto Bus free time tBuF Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of tHp pat is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution Only in the 30 pin products the values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics loH1 loL1 Von1 Vou1 must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Normal mode Cb 400 pF Rb 2 7 kQ lt R gt Fast mode Cb 320 pF Rb 1 1 KQ IICA serial transfer timing SCLAO tHD STA tsu sTO SDAAO tBUF Stop Start Restart Stop condition condition condition condition RO1DS0193EJ0200 Rev 2 00 Page 52 of 106 Sep 06 2013 RENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 6 Analog Characteristics lt R gt 2 6 1 A D converter characteristics Classification of A D c
123. to 16 MHz Von 2 4 to 5 5 V oscillator clock LS Low speed main mode 1 to 8 MHz Voo 1 8 to 5 5 V Low speed on chip oscillator clock 15 kHz TYP General purpose register 8 bit register x 8 x 4 banks Minimum instruction execution time 0 04167 us High speed on chip oscillator clock fin 24 MHz operation 0 05 us High speed system clock fmx 20 MHz operation Instruction set Data transfer 8 16 bits Adder and subtractor logical operation 8 16 bits Multiplication 8 bits x 8 bits Rotate barrel shift and bit manipulation set reset test and Boolean operation etc Total 18 22 26 CMOS I O 12 16 21 N ch O D I O N ch O D I O N ch O D I O lt R gt Voo withstand voltage 4 Voo withstand voltage 5 Voo withstand voltage 9 CMOS input 4 4 3 N ch open drain I O 2 6 V tolerance 16 bit timer 4 channels 8 channels Watchdog timer 1 channel 12 bit Interval timer 1 channel Timer output 4 channels 8 channels PWM outputs 3 PWM outputs 7 9e 3 Note 2 Notes 1 The self programming function cannot be used in the R5F10266 and R5F10366 2 The maximum number of channels when PIORO is set to 1 3 The number of PWM outputs varies depending on the setting of channels in use the number of masters and slaves See 6 9 3 Operation as multiple PWM output function in the RL78 G12 User s Manual Hardware Caution When the fl
124. to ANI3 ANI16 to ANI19 and 0 3 to AVREF 0 3 Notes 4 Output current high Per pin Other than P20 to P23 40 Total of all pins All the terminals other than P20 to P23 170 20 24 pin products P40 to P42 70 30 pin products POO P01 P40 P120 20 24 pin products POO to PO3 5 P10 to P14 30 pin products P10 to P17 P30 P31 P50 P51 P147 Per pin P20 to P23 Total of all pins Output current low Per pin Other than P20 to P23 Total of all pins All the terminals other than P20 to P23 20 24 pin products P40 to P42 30 pin products POO P01 P40 P120 20 24 pin products POO to P03 P10 to P14 P60 P61 30 pin products P10 to P17 P30 P31 P50 P51 P60 P61 P147 Per pin P20 to P23 1 Total of all pins 5 Operating ambient 40 to 105 temperature Storage temperature 65 to 150 Notes 1 30 pin product only 2 Connect the REGC pin to Vss via a capacitor 0 47 to 1 uF This value determines the absolute maximum rating of the REGC pin Do not use it with voltage applied 3 Must be 6 5 V or lower 4 Do not exceed AVrer 0 3 V in case of A D conversion target pin 5 24 pin products only Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physic
125. trol register CSC Supply voltage Vpp Vppr or 0 7 V RO1DS0193EJ0200 Rev 2 00 Page 99 of 106 see 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 3 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 105 C Vppr lt Voo lt 5 5 V Vss 0 V Parameter Conditions Detection supply voltage Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time LIISIS ISISI SIISII SISI S lt Power supply fall time Minimum pulse width Detection delay time RO1DS0193EJ0200 Rev 2 00 Page 100 of 106 see 2010 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C LVD detection voltage of interrupt amp reset mode Ta 40 to 105 C Vror lt Voo lt 5 5 V Vss 0 V ea Interrupt and reset Vrocz Veoc1 Voc 0 1 1 falling reset voltage 2 75 LVIS1 LVISO 1 0 Rising reset release voltage mode Vivops LVIS1 LVISO 0 0 Rising reset release voltage LVIS1 LVISO 0 1 Rising reset release voltage
126. ture 20 C to 85 C e Pre configured settings 24 MHz 16 MHz 12 MHz 8 MHz 6 MHz 4 MHz 3 MHz 2 MHz and 1 MHz Reset and Supply Management e Power on reset POR monitor generator e Low voltage detection LVD with 12 setting options Interrupt and or reset function Data Memory Access DMA Controller e Up to 2 fully programmable channels e Transfer unit 8 or 16 bit Multiple Communication Interfaces Up to 3 x C master Up to 1 x C multi master Up to 3 x CSI SPI 7 8 bit Up to 3 x UART 7 8 9 bit Extended Function Timers e Multi function 16 bit timers Up to 8 channels e Interval Timer 12 bit 1 channel e 15 kHz watchdog timer 1 channel window function Rich Analog e ADC Up to 11 channels 10 bit resolution 2 1 us conversion time e Supports 1 8 V to 5 5 V e Internal voltage reference 1 45 V e On chip temperature sensor Safety Features IEC or UL 60730 compliance Flash memory CRC calculation RAM parity error check RAM write protection SFR write protection Illegal memory access detection Clock stop frequency detection ADC self test General Purpose I O e 5 V tolerant high current up to 20 mA per pin e Open Drain Internal Pull up support Operating Ambient Temperature e Standard 40 C to 85 C e Extended 40 C to 105 C Package Type and Pin Count e QFN 24 e SSOP 20 30 There is difference in specifications between every product RO1DS0193EJ0200
127. ut leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite lt R gt 2 When high speed on chip oscillator clock is stopped 3 When high speed system clock is stopped 4 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vop 2 7 V to 5 5 V 1 MHz to 24 MHz Voo 2 4 V to 5 5 V 1 MHz to 16 MHz LS Low speed main mode Vopp 1 8 V to 5 5 V 1 MHz to 8 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH high speed on chip oscillator clock frequency 3 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0200 Rev 2 00 Sep 06 2013 Page 25 of 106 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 30 pin products Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V 2 2 Supply lope N HALT HS High speed fin 24 MHz te Voo 5 0 V mo 1280 uA current 1 mode main mode Voo 3 0 V m 1280 fin 16 MHz 4 Voo 5 0 V a 1000 uA LS Low speed fin 8 MHz 4 Voo 3 0 V ear uA Note 6 HS High speed fux 2
128. utput becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 C is the load capacitance of the SCKp and SOp output lines Select the normal input buffer for the Slp pin and the normal output mode for the SOp and SCKp pins by using port input mode register 1 PIM1 and port output mode registers 0 1 4 POMO POM1 POM4 Remarks 1 p CSI number p 00 01 11 20 m Unit number m 0 1 n Channel number n 0 1 3 1 3 is only for the R5F102 products 2 fuck Serial array unit operation clock frequency Operation clock to be set by the serial clock select register m SPSm and the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 1 3 1 3 is only for the R5F 102 products RO1DS0193EJ0200 Rev 2 00 Page 33 of 106 Sep 06 2013 ztENESAS RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C lt R gt 4 During communication at same potential CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter SCKp cycle time Conditions HS high speed main Mode MIN MAX LS low speed main Mode MAX Note4 4 0V lt Vp0 lt 5 5V 20 MHz lt fuck 8 fuck 6 fuck fuck lt 20 MHz 8 fuck 6 fmcK 6 fuck and 500 2 7 V lt Voo lt 5 5 V 16 MHz lt fuck fuck lt 16 MHz 6 fuck 6 fuck and 500 2 4 V lt V
129. ve input Vo 3 0 V Resonator connection Notes 1 Total current flowing into Voo including the input leakage current flowing when the level of the input pin is fixed to Voo or Vss The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator clock is stopped 3 When high speed system clock is stopped 4 Relationship between operation voltage width operation frequency of CPU and operation mode is as follows HS High speed main mode Vop 2 7 V to 5 5 V 1 MHz to 24 MHz Vo 2 4 V to 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH high speed on chip oscillator clock frequency 3 Temperature condition of the TYP value is Ta 25 C RO1DS0193EJ0200 Rev 2 00 Page 71 of 106 Sep 0 201 RENESAS _ RL78 G12 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 30 pin products Ta 40 to 105 C 2 4 V lt Voo lt 5 5 V Vss 0 V 2 2 Parameter Conditions Supply lope N HALT HS High speed fin 24 MHz 4 Voo 5 0 V 440 2300 uA current mode main mode Voo 3 0 V 440 2
130. vice stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in a
131. years 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation RO1DS0193EJ0200 Rev 2 00 Page 60 of 106 Sep 06 2013 RENESAS al RL78 G12 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 9 Dedicated Flash Memory Programmer Communication UART Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V 2 10 Timing of Entry to Flash Memory Programming Modes Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V lt R gt Parameter Conditions Time to complete the communication for the initial tsut POR and LVD reset are setting after the external reset is released released before external reset release Time to release the external reset after the TOOLO POR and LVD reset are pin is set to the low level released before external reset release Time to hold the TOOLO pin at the low level after POR and LVD reset are the external reset is released released before external reset release excluding the processing time of the firmware to control the flash memory A Sentee see ee eeeeeeee Vv RESET lt 1 1 gt lt 2 gt lt 3 gt i i i H
132. ysical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas El

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