Embedded System Design using IP Integrator
Contents
1. xil printf DIP Switch Status x r n dip check for i 0 i lt 9999999 i Figure 28 Snippet of source code www xilinx com support university ZYNQ 3 21 3 XILINX Xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook Test in Hardware Step 7 In case of Zybo make sure that the JP7 is set to select USB power so that one cable can be used for both programming and powering up the board In case of ZedBoard you will need two micro usb cables one to program the device and another for serial communication 7 1 Connect the board with necessary micro usb cable s and power it ON Establish the serial communication using SDK s Terminal tab 7 1 1 Zybo only Make sure that the JP7 is set to select USB power 7 1 2 ZedBoard Connect the Micro USB cable to the UART port of the ZedBoard Turn ON the power Zybo Make sure that a micro USB cable is connected to the JTAG PROG connector next to the power supply connector Turn ON the power 7 1 3 Select the Terminal tab If itis not visible then select Window gt Show view gt Terminal 7 1 4 Click on andif required select Serial as the connection type select appropriate COM port depends on your computer and configure it with the parameters as shown These settings may have been saved from previous lab ZYNQ 3 22 wwwxilinx com support university YH INIY xup xilinx com XILINX copyright 2014 Xi2. click on btns_5bit and select Assign Address Note that both peripherals are assigned in the address range of 0x40000000 to Ox7FFFFFFF GPO range EN Cell Interface Pin Base Name Offset Address Range High Address processing _system _O Data 32 address bits 45 jm sw Abit SAKSI Reg O 41200000 4k 0x4l20FFFF mm btns_5bit 5_ As Reg Ox41210000 pk Ox41elFFFF Figure 21 Peripheral Memory Map for ZedBoard Zybo Notice that sw_4bit has been automatically assigned an address but btns_4bit has not Right click on bitns_4bit and select Assign Address Note that both peripherals are assigned in the address range of 0x40000000 to Ox7FFFFFFF GPO range A cell Interface Pin Base Name Offset Address Range High Address ir sw 4hit S_AXI Reg Ox41200000 64K Ox4d120FFFF ope btns 4bit S_AXI Reg Ox41210000 B4K Ox4121FFFF Figure 21 Peripherals Memory Map for Zybo Make GPIO Peripheral Connections External Step 4 4 1 The push button and dip switch instances will be connected to the corresponding pins on the board This can be done manually or using Designer Assistance The location constraints are automatically applied by the tools as the information for the target board is already known Normally one would consult the board s user manual for this information ZYNQ 3 14 xilinx com support universit x aaa amp XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator In the Di
3. 0_0 Board IP Configuration V Generate Board based 10 Constraints Associate IP interface with DIGILENTINC COM ZYBO PARTO 1 0 Board interface IP Interface Board Interface GPIO GPIO2 4bS_AXI s_axi_aclk s_axi_aresetn Figure 14 Configuring GPIO instance for switches on Zybo Click the P Configuration tab Notice the set GPIO Width Notice that the peripheral can be configured for two channels but since we want to use only one channel without interrupt leave the GPIO Supports Interrupts and Enable Channel 2 unchecked ZedBoard The GPIO width is set to 8 Board IP Configuration GPIO All Inputs All Outputs GPIO Width 8 1 32 Default Output Value Ox00000000 Ox00000000 0x FFFFFFFF Default Tri State Value OxFFFFFFFF Ox00000000 0x FFFFFFF _ Enable Dual Channel GPIO 2 Figure 15 Configuring GPIO instance for ZedBoard Zybo The GPIO width is set to 4 Board IP Configuration All Inputs All Qutputs GPIO Width 4 1 37 Default Output Value Ox00000000 0x00000000 0xFFFFFFFF Default Tri State Value O0xFFFFFFFF 0x00000000 0xFFFFFFFF Enable Dual Channel Figure 15 Configuring GPIO instance for Zybo 7 www xilinx com support university ZYNQ 3 9 XI LI NX xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook 3 1 7 Click OK to save and close the customization window 3 1 8 Notice that Design assistance is available Click on R
4. DDR __ FIXED_IO processing_system7_0_axi_periph ZYNQ7 Processing System ag f gt btns_Sbit rst_processing_system7_0_100M mb_reset ext_reset_in bus_struct_reset 0 0 aux_reset_in peripheral_reset 0 0 mb_debug_sys_rst interconnect_aresetn 0 0 sw_8bit AXI Interconnect Processor System Reset AXI GPIO Figure 20 Block diagram view after adding the peripherals for ZedBoard XILINX wwwaxilinx com support university ZYNQ3 13 Xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook processing_system7_0 DDR FIXED_IO DDR 2 FIXED 104 M_AXL_GPO_ACLK ZYN ia FCLK_RESETO_N processing_system7_0_axi_periph LK ZYNQ7 Processing System sw_4bit las an GPIO Ss axi_adk S_axi_aresetn i AXI GPIO btns_4bit JS_AXI AXI Interconnect T s_axi_adk GPIO cen rst_processing_system7_0_100M mb_reset ext_reset_in bus_struct_reset 0 0 aux_reset_in peripheral_reset 0 0 mb_debug_sys_rst interconnect_aresetn 0 0 a dem_locked peripheral_aresetn 0 0 A Processor System Reset AXI GPIO Figure 20 Block diagram view after adding the peripherals for Zybo 3 1 16 Click on the Address Editor and expand processing_system7_0 gt Data gt Unmapped Slaves ZedBoard Notice that sw_8bit has been automatically assigned an address but btns_5bit has not Right
5. Lab Workbook Embedded System Design using IP Integrator Embedded System Design using IP Integrator Introduction This lab guides you through the process of using Vivado and IP Integrator to create a simple ARM Cortex A9 based processor design targeting either the ZedBoard or the Zybo development board You will use IP Integrator to create the hardware block diagram and SDK Software Development Kit to create an example application to verify the hardware functionality Objectives After completing this lab you will be able to e Create a Vivado project for a Zynq system e Use the IP Integrator to create a hardware system e Use IP Catalog to use AXI GPIO peripheral to extend the design e Use SDK to create a standard memory test project e Run the test application on the board Procedure This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow Follow these detailed instructions to progress through the lab Design Description The purpose of the lab exercise is to walk you through a complete hardware and software processor system design The following diagram represents the completed design Figure 1 In this lab you will use IP Integrator to create a processing system based design consisting of the following ARM Cortex A9 core PS UART for serial communication DDR3 controller for external DDR3_ SDRAM memory AXI Interconnect block Two insta
6. Voltage LVCMOS 1 8V PS PL Configuration Search Peripheral I O Pins Peripheral 10 Signal 10 Type Memory Interfaces Quad SPI Flash Clack Configuration ft E SRAM NOR Flash DDR Configuration EE E NAND Flash VO Peripherals EE enero SMC Timing Calculation Interrupts E ENET i1 o a E 5D 0 Ll f E _ SD 1 UART 0 UART 1 MIO 48 49 7 PCO PC 1 Ae osaa SPIO spr CAN 0 E E cani GPIO Ea GPIO MIO E EMO Gro Wi H Resets EF Application Processor Unit Figure 9 Selecting only UART 1 2 2 3 Click on the Clock Configuration expand PL Fabric Clocks and observe that FCLK_CLKO is enabled with 100 MHz frequency ZYNQ3 6 wwwxilinx com support university lt YH INIY xup xilinx com XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator 2 2 4 Click OK We left the rest of the configuration as is since we want to add two GPIO peripherals in the PL section which will be connected through the GPO master interface using FOCLK_CLKO as the clock source and FCLK_RESET0O_N as the reset control signal processing_system _0 DDR y DDR FIXED 104 FIXED_IO M_AXI_GPO_ACLK ZYNQ_ M_AXI_GPO E ZYN Q7 Processi ng Syste m Figure 10 Updated Zynq Block Add Two Instances of GPIO Step 3 3 1 3 1 1 Add two instances of the GPIO Peripheral from the IP catalog to the p
7. agram view notice that Designer Assistance is available This will be ignored for now and a port will be manually created and connected for the switch instance Designer Assistance will be used to connect the buttons peripheral 4 1 1 Right Click on the gpio port of the sw_8bit instance for ZedBoard or the sw_4bit for Zybo and select Make External to create the external port This will create the external port named gpio and connected to the peripheral 4 1 2 Select the gpio port and change the name to sw_ 8bit for ZedBoard or sw_4bit for Zybo in its properties form The width of the interface will be automatically determined by the upstream block 4 1 3 Connection automation will be used to create a port for the buttons ZedBoard Add the port for the btns_5bit component automatically by clicking on Run Connection Automation and selecting btns_5bit GPIO n the Select Board Interface drop down menu select btns_5bits and click OK to create and connect the external port Zybo Add the port for the bins_4bit component automatically by clicking on Run Connection Automation and selecting btns_4bit GPIO In the Select Board Interface drop down menu select btns_ 4bits and click OK to create and connect the external port 4 1 4 Run Design Validation Tools gt Validate Design and verify there are no errors The design should now look similar to the diagram below processing_system7_0 gt DDR FIXED_IO sw_8bit S
8. alar ports 0 7 fg GPIO_61115 8 Input Z Multiple LVCMOS25 5 Scalar ports 0 4 Hl A Tcl Console Messages E Log 3 Reports 3 Design Runs Package Pins Figure 24 Check the IP port pin constraints Zybo In the I O ports tab expand GPIO_23532 gt btns_4bit_tri_i and notice pins have already been assigned to this peripheral The pin information was included in the board files and automatically assigned when the IP was connected to the port The sw_4bit_tri_ihave also been automatically assigned pin locations along with the other Fixed ports in the design ZYNQ3 16 wwwxilinx com support university YH INIY xup xilinx com XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator A Name Direction Board Part Pin Board Part Interface Neg Diff Pair Site Fixed Bank YO Std a m All ports 138 da HE DDR_1497 71 In Out Multiple Multiple E GPIO_23532 4 34 LYCMOS33 B btns_4bits_tri_i 4 34 LVCMOS33 i of btns_4bits_tri_i 3 btns_4hbits_tri Y16 34 LVCMOS33 i btns_4bits_tri_i btns_4hbits_tri V16 34 LVCMOS33 of btns_4bits_tri_i 1 btns_4bits tri P16 34 LVCMOS33 btns_4bits_tri R18 34 LYVCMOS33 Multiple LYCMOS33 Multiple LVCMOS33 sis Scalar ports 0 Scalar ports 0 NB Tel Console Messages E Log 3 Reports 3 Design Runs E Package Pins _ D 1 0 Port Figure 24 Check th
9. e IP port pin constraints Generate the Bitstream and Export to SDK Step 5 5 1 Generate bitstream export the hardware and start SDK by 5 1 1 Click on Generate Bitstream and click Yes if prompted to launch Implementation Click Yes if prompted to save the design 5 1 2 Select Open Implemented Design option when the bitstream generation process is complete and click OK Click Yes if prompted to close the synthesized design You may see a Critical Messages window pop up Click OK to ignore it You should have the block design open before you export the design and launch SDK If it is closed then open the block design by clicking on the Open Block Design under the IP Integrator sub menu of the Flow Navigator pane 5 1 3 Select File gt Export gt Export Hardware 5 1 4 Make sure that Include Bitstream option is selected and click OK leaving the target directory set to local project directory Export hardware platform for software development tools J Include bitstream Export to lt Local to Project gt Figure 25 Exporting hardware www xilinx com support university ZYNQ 3 17 XILINX xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook The lab3 sdk directory will be created under the lab3 project directory The system_wrapper hdf file will be placed under the lab3 sdk directory Click OK Select File gt Launch SDK SDK should n
10. ed peripheral_aresem 0 0 p processing system _O_axi_periph gt FIXED_IO ZY NO Pr Ores img Sys tem Figure 19 Connect the interfaces Zybo Click on the s_axi port of the new bins_4bit block and drag the pointer towards the AXI Interconnect block The message Found 1 interface should appear and a green tick should appear beside the M01_AXI port on the AXI Interconnect indicating this is a valid port to connect to Drag the pointer to this port and release the mouse button to make the connection ZYNQ 3 12 xilinx com support universit OT ae amp XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator 3 1 15 processing_system7_0 DDR FIXED_IO btns_4bit bus_struct_reset 0 0 aux_reset_in peripheral_reset 0 0 interconnect_aresetn 0 0 AXI Interconnect Processor System Reset AXI GPIO Figure 19 Connect the interfaces In a similar way connect the following ports AXI Interconnect M01_ACLK gt Zyng7 Processing System FCLK_CLKO AXI Interconnect M01_ARESETN gt Proc Sys Reset peripheral_aresetn ZedBoard btns_5bit s_axi_aclk gt Zynq7 Processing System FCLK_CLKO btns_5bit s_axi_aresetn gt Proc Sys Reset peripheral_aresetn Zybo btns_4bit s_axi_aclk gt Zyng7 Processing System FCLK_CLKO btns_4bit s_axi_aresetn gt Proc Sys Reset peripheral_aresetn The block diagram should look similar to this processing_system7_0 2
11. ing System Figure 17 Design with sw_8bit automatically connected for ZedBoard rst_processing_system7_0_100M processing_system7_0_axi_periph slowest_sync_cdk mb_reset ext_reset_in bus_struct_reset 0 0 4bit aux_reset_in peripheral_reset 0 0 sash ch mb_debug_sys_rst interconnect_aresetn 0 0 S_AXI dem_locked peripheral_aresetn 0 0 s_axi_adk GPIO 4 ll s_axi_aresetn Processor System Reset AXI GPIO gt DDR _ gt FIXED_IO FCLK_RESETO_N ZYNQ7 Processing System Figure 17 Design with sw_4bit automatically connected for Zybo 3 1 11 Add another instance of the GP O peripheral Add IP and using the board flow configure it to connect to either the btns 5bit on ZedBoard or the btns 4bits on Zybo 3 1 12 Change the name of the block either to btns_5bit for ZedBoard or to btns_4bit for Zybo Click on the block to select it and change the name in the properties view At this point connection automation could be run or the block could be connected manually This time the block will be connected manually 3 1 13 Double click on the AXI Interconnect and change the Number of Master Interfaces to 2 and click OK lt vVIlINY wwwxilinx com support university ZYNQ3 11 amp XILINX xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook F Re customize IP P TE ei l o AXI Interconnect 2 1 Documentation IP Location Component Name system_processing_sy
12. l connections for FIXED_IO Trigger and DDR interfaces NOTE Apply Board Preset will discard existing IP configuration please uncheck this box if you wish to retain previous configuration Instance processing_system7_0 Make Interface External FIXED_IO DDR Apply Board Preset FA Cross Trigger In Disable v Cross Trigger Out Disable v Figure 6 Run Block Automation Once Block Automation has been complete notice that ports have been automatically added for the DDR and Fixed IO and some additional ports are now visible A default configuration for the Zynq depending on the target board has been applied which will now be modified ZYNQ 3 4 www xilinx com support university g XI L NX xup xilinx com copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator processing_system _0 DDR FIXED_IO 9 R M_AXI GPO ACLK Z Y NOQ TTCO_WAVEO_OUT TTCO_WAVEL_OUT TTCO_WAVE2 OUT FOLK CLEO FCLK_RESETO_N ZYNQ Processing System Figure 7 Zynq Block with DDR and Fixed IO ports 2 1 7 Inthe block diagram double click on the Zynq block to open the Customization window for the Zynq processing system 2 1 8 A block diagram of the Zynq should now be open showing various configurable blocks of the Processing System At this stage the designer can click on various configurable blocks highlighted in green and change the system configuration F Re customize IP ZYNQ7 Proces
13. linx Lab Workbook Embedded System Design using IP Integrator 50K Terminal Settings 2 View Settings View Title Terminal 1 Encoding ISO 8859 1 Connection Type Settings Port COM5 v Baud Rate 115200 v Data Bits Stop Bits Parity Flow Control Timeout sec 5 Figure 29 Setting up the Terminal tab 7 2 Program the FPGA by selecting Xilinx Tools gt Program FPGA Run the TestApp application and verify the functionality 7 2 1 Select Xilinx Tools gt Program FPGA 7 2 2 Click Program to download the hardware bitstream When FPGA is programmed the DONE LED blue color will be lit 7 2 3 Select TestApp in Project Explorer right click and select Run As gt Launch on Hardware GDB to download the application execute ps _init and execute TestApp elf 7 2 4 You should see the something similar to the following output on Terminal console g XILINX www xilinx com support university ZYNQ 3 23 xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook IP Switch Status 56 IP Switch Status 56 Figure 30 Program output on ZedBoard Push Buttons Status DIP Switch Status 6 Push Buttons Status DIP Switch Status 6 Push Buttons Status DIP Switch Status 6 Push Buttons Status DIP Switch Status 6 Push Buttons Status DIP Switch Status 6 Push Buttons Status DIP Switch Status 6 Figure 30 Program output on Zybo Select the Console tab and click
14. n www xilinx com support university xup xilinx com copyright 2014 Xilinx amp XILINX Lab Workbook Embedded System Design using IP Integrator Project Explorer 2 O system hdf 4 AS 7 iii system_wrapper_hw_platform_0 Hardware Platform a system_wrapper_hw_platform_ OTOES B ps7 inite Specification l ps7_inith Design Information ps7_init html 5 B ps7_inittcl Target FPGA Device 7z010 G system hdf Created With Vivado 2014 2 Created On Mon Jul 21 13 10 24 2014 Address Map for processor ps7_cortexa9_0 bins 4bit 0x41210000 0x4121ffff ps7_afi_ 0 Oxf8009000 Oxfeoosrre os7_afi_ Oxf8009000 0zf8009fff os7_afi_2 Oxf800a000 Ozf800afff os7_afi_3 Oxf 800b000 Oxf800bFrt os7_coresight_comp_0 Oxf 8800000 Oxfearrrrs ps7 ddr 0 0x00100000 Ox1fffffff ps7 _ddrc 0 Oxf8006000 OxfE006fff ps7 dev cfg_0 Oxf8007000 0zf80070ff os7_dma_ns Ozf8004000 Oxf8004Fff os7_dma_s Oxf 8003000 Ozf8003fff os7_globaltimer_0 Oxf8f00200 Oxfaroozre Figure 26 SDK C C development view for Zybo Generate TestApp Application in SDK Step 6 6 1 Generate software platform project with default settings and default software project name 6 1 1 From the File menu select File gt New gt Board Support Package 6 1 2 Click Finish with the standalone OS selected 6 1 3 Click OK to generate the board support package named standalone_bsp_0 This will create a new Board Support Package Project The library generator will run in
15. nces of GPIO peripheral to connect push buttons and slide switches Push Buttons i Figure 1 Processor Design of this Lab www xilinx com support university ZYNQ 3 1 amp XILINX xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook General Flow for this Lab Step 1 Step 2 Step 3 Add Step 4 Step 5 Create a Create Two Make GPIO Generate project using Processor Instances of Connections Bitstream Vivado System using GPIO External IP Integrator Step 6 Step 7 Create a Verify Memory Functionality TestApp in in Hardware SDK Create a Vivado Project Step 1 1 1 Launch Vivado and create an empty project either targeting the ZedBoard having xc7z020clg484 1 device or Zybo having xc7z010clg400 1 device and using the Verilog language References to lt 2014 2 zynq_labs gt means c xup sys_ design 2014 2 zynq_labs and lt 2014 2 zynq_sources gt means c xup sys_design 2014 2 zynq_sources directories 1 1 1 Open Vivado by selecting Start gt All Programs gt Xilinx Design Tools gt Vivado 2014 2 gt Vivado 2014 2 1 1 2 Click Create New Project to start the wizard You will see the Create a New Vivado Project dialog box Click Next 1 1 3 Click the Browse button of the Project Location field of the New Project form browse to lt 2014 2 zynq_labs gt and click Select 1 1 4 Enter lab3 in the Project Name field Make sure that the Create Project Subdirectory bo
16. on the Terminate button to stop the program Close SDK and Vivado programs by selecting File gt Exit in each program 7 2 5 7 2 6 7 2 7 Power OFF the board Conclusion Vivado and the IP Integrator allow base embedded processor systems and applications to be generated very quickly GPIO peripherals were added from the IP catalog and connected to the Processing System through the 32b Master GPO interface The peripherals were configured and external FPGA connections were established Pin location constraints since we used the board aware port names were automatically applied to connect the peripherals to the push buttons and DIP switches of the target board After the system has been defined the hardware can be exported and SDK can be invoked from Vivado Software development was done in SDK which provides several application templates including memory tests You verified the operation of the hardware by downloading a test application executing on the processor and observing the output in the serial terminal window ZYNQ 3 24 www xilinx com support university ad xup xilinx com XI LINX copyright 2014 Xilinx
17. ow be open A Hardware platform project should have been created and the system_wrapper_hw_platform_0O folder should exist in the Project Explorer panel The system hdf file for the Hardware platform should be open in the preview pane Double click system hdf to open it if it is not Basic information about the hardware configuration of the project can be found in the hdf file along with the Address maps for the PS systems and the IPs used information amp Project Explorer a system_wrapper_hw_platform_0 ps7_init c l ps7_init h ps7_inithtml ps7_init tcl g system hdf g system hdf 3 y Design Information Target FPGA Device 7z020 Created With Vivado 2014 2 Created On Sat Jul 12 15 13 42 2014 Address Map for processor ps7_cortexa9_0 btns_5bit 0x41210000 ps7_afi_0 0z 8008000 ps7_afi_1 0z f8009000 ps7_afi_2 0xf800a000 ps7_afi_3 Oxf800b000 ps7_coresight_comp_0 Uxf8s00000 ps7_ddr_0 0x00100000 ps7_ddrc_0 Oxf 8006000 ps7_dev_cfg_0 0xf8007000 ps7_dma_ns Uxf 8004000 ps7_dma_s Uxfs003000 ps7_globaltimer_0 Oxf6 O00200 ps7_gpv_0 OxfsS900000 ps7_intc_dist_O Uxfef01000 0x4121ffff Oxf s006f ff Oxf S009 fF OxfbO00arft Oxfb00bf ff Oxfoorrrtret Oxlffrrfrfret Oxf s006fft Oxf 80070fFF Oxf 8004ffFf Oxfb00sf ff OxfbfrO002rFf Oxf69ffFFKE OxfofrOlrfret Figure 26 SDK C C development view for ZedBoard ZYNQ 3 18 system_wrapper_hw_platform_0 Hardware Platform Specificatio
18. rocessor system Click the Add IP icon F and search for gp 7 matches 1 Name VLNY TF 3GPP LTE Channel Estimator xilinx com ip lte_3gpp_channel_esti F 3GPP LTE MIMO Decoder xilinx com ip lte_3gpp_mimo_decode iF 3GPP LTE MIMO Encoder xilinx com ip lte_3gpp_mimo_encode iF 3GPPLTE Turbo Encoder xilinx com ip tec_encoder_3gpplte 4 0 TF 3GPP Mixed Mode Turbo Decoder xilinx com ip tcc_decoder_3gppmm 2 0 IF 3GPP Turbo Encoder xilinx com ip tec_encoder_3gpp 5 0 IF AXI GPIO xilinx com ip axi_gpio 2 0 Select and press ENTER or drag and drop ESC to cancel Figure 11 Add GPIO IP Double click the AXI GPIO to add the core to the design The core will be added to the design and the block diagram will be updated processing_system7_0 r axi_gpio_0 4 DDR DDR FIXED_IO h FIXED_IO M_AXI_GPO_ACLK ZYNQ M_AXI_GPOQ P Il FPCLK_CLKO i FCLK_RESETO_N L AXI GPIO 4 ZYNQ7 Processing System Figure 12 Zynq system with AXI GPIO added 3 1 3 Click on the AXI GPIO block to select it and in the properties tab ZedBoard Change the name to sw_ 8bit g XI LI NX www xilinx com support university ZYNQ 3 7 xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator gt Blr TF axi_gpio_0 Name sw_8bit Parent name system General Properties Figure 13 Change AXI GPIO default name Zybo Change the name to sw_4bit Block Proper
19. s _axi_aresetn rst_processing_system7_0_100M f Sync_cik mb reset _reset_in bus struct_reset 0 0 aux _reset_in peripheral_ reset 0 0 h b debug_sys_rst _ interconnect_aresetn 0 jocked peripheral_aresetn 0 0 f AXI Interconnect lt pe s_axi_adk GPIO b sw_8bit AXI GPIO btns_5bit Processor Sy stem Reset _AXI _axi_adk GPIO btns_5Sbits G v D ns I AXI GPIO Figure 22 Completed design for ZedBoard processing_system7_0 DDOR DDR e FXD0 gt FIXED_IO M_AXI_GP0_ACLK M_AXI_GPO lt b tem7_0_axi_ h ZYNQ nr a gae system7_0_axi_perip FCLK_RESETO_N 4 S00_AXI ACLK sw_4bit S AXI s_axi_adk GPIO gt sw_4bit s_axi_aresetn bus_struct_reset 0 0 AXI GPIO 7 aux_reset_in peripheral_reset 0 0 btns_ 4bit mb_debug_sys_rst interconnect_aresetn 0 0 d dem_locked peripheral_aresetn 0 0 S AXI gt Processor System Reset i y h p btns_4bits eo l Figure 22 Completed design for Zybo g XILINX www xilinx com support university ZYNQ 3 15 a xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook 4 1 5 In the Flow Navigator window click on the Generate Block Design to generate the relevant files of each IP in the design Click Generate 4 1 6 In the sources view Right Click on the block diagram file system bd and select Create HDL Wrapper to create the HDL wrapper file When prompted select Let Vi
20. sing System 5 4 Documentation Presets IP Location Import XPS Settings Page Navigator Zynq Block Design PS PL Configuration E Application Processor Unit APU Peripheral 1 0 Pins F iE Ea ARM Cortex A MIO Configuration System Level CPU Control Regs Clock Configuration Snoop Control unit DDR Configuration 512 KB L2 Cache and Contolier Interrupts SMC Timing Calculation eS 256 KB i i i i i Processing System PS T a CT once amor oes E a MIO EMIO Crock Ports Programmable Logic PL Figure 8 Zynq System Configuration View www xilinx com support university ZYNQ 3 5 3 XI LI NX xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook 2 2 Configure I O Peripherals block to use UART 1 only Only the UART is required for this lab so all other peripherals will be deselected 2 2 1 Click on one of the peripherals in green in the OP Peripherals block or select the MIO Configuration tab in the Page Navigator on left to open the configuration form 2 2 2 Expand I O peripherals if necessary and deselect all the O peripherals except UART 1 i e Remove ENET USB 0 SD 0 Expand GPIO to deselect GPIO MIO Expand Memory Interfaces to deselect Quad SPI Flash Expand Application Processor Unit to deselect Timer 0 Fage Navigator MIO Configuration Zynq Block Design Bank 0 10 Voltage LVCMOS 3 3V Bank 110
21. source code is shown in figure below ZYNQ 3 20 Wwwxilinx com support university lt YH INIY xup xilinx com XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator include xparameters h include xgpio h int main void XGpio dip push int i psb_check dip_check xil_printf Start of the Program r n XGpio Initialize amp dip XPAR_SW 8BIT DEVICE ID XGpio SetDataDirection amp dip 1 Oxffftfftff XGpio Initialize amp push XPAR_BTNS 5BIT DEVICE ID XGpio SetDataDirection amp push 1 Oxf FttFFFF while 1 psb check XGpio DiscreteRead amp push 1 xil printf Push Buttons Status x r n psb check dip check XGpio DiscreteRead amp dip 1 xil printf DIP Switch Status x r n dip check for i 0 i lt 9999999 i Figure 28 Snippet of source code G system hdf lmh system mss include xparameters h include xgpio h Sint main void XGpio dip push int i psb_check dip_check xil_printf Start of the Program r n XGpio_Initialize amp dip XPAR_SW_4BIT_DEVICE_ID XGpio SetDataDirection amp dip 1 Oxffffffff XGpio_Initialize amp push XPAR_BTNS_4BIT_DEVICE_ID XGpio_SetDataDirection amp push 1 Oxffffffff while 1 psb_ check XGpio DiscreteRead amp push 1 xil printf Push Buttons Status x r n psb check dip check XGpio DiscreteRead amp dip 1
22. stem7_0_axi_periph_0 Number of Slave Interfaces 1 j Number of Master Interfaces 2 Interconnect Optimization Strategy AXI Interconnect includes IP Integrator automatic converter insertion and configuration i When the endpoint IPs attached to the interfaces of the AXI Interconnect differ j in width clock or protocol a converter IP will automatically be added inside the interconnect If a converter IP is inserted IP integrator s parameter propagation automatically configures the converter to match the design To see which conversion IPs have been inserted use the IP integrator expand hierarchy buttons to explore inside the AXI Interconnect hierarhcy NOTE Addressing information for AXI Interconnect is specified in the IP Integrator address editor _ Enable Advanced Configuration Options 3 de z el m ll a nm Figure 18 Add slave port to AXI Interconnect 3 1 14 ZedBoard Click on the s_ax port of the new btns_5bit block and drag the pointer towards the AXI Interconnect block The message Found 1 interface should appear and a green tick should appear beside the M01_AXI port on the AXI Interconnect indicating this is a valid port to connect to Drag the pointer to this port and release the mouse button to make the connection bins Sbit mb reset AXI GPIO ext reset ii bus_struct_reset 0 0 aux reset in peripheral_reset o 0 p h debug sys rst intercomect_aresetn 0 0 dem_lack
23. system This design is empty To get started from the catalog e p Prop i Ctrl E R Delete Ctrl C a Ctrl V A Ctrl F t Select All Ctrl A k Ctrl I F IP Settings Y Validate Design F6 5 Create Hierarchy D Create Comment al Create Port Ctrl K Create Interface Fort Ctrl L Regenerate Layout Save as PDF File Figure 3 Add IP to Block Diagram XILINX wwwailinx com support university ZYNQ33 xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook 2 1 4 Once the IP Catalog is open type zy into the Search bar find and double click on ZYNQ7 Processing System entry or click on the entry and hit the Enter key to add it to the design 2 matches 1 Name VLA iF ZYNQ7 Processing System xilinx com ip processing_system7 5 4 iF ZYNQ7 Processing System BFM xilinx com ip processing_system7 _bf Select and press ENTER or drag and drop ESC to cancel Figure 4 Add Zynq block to the design Notice the message at the top of the Diagram window that Designer Assistance available Click on Run Block Automation and select processing system7_0 G Designer Assistance available Run Block Automation iF processing_system7_0 Figure 5 Designer Assistance message 2 1 6 Click OK when prompted to run automation A Run Block Automation lp 2s Zynq7 block automation applies current board preset and generate externa
24. the background and will create the xparameters h file in the lt 2014 2 zynq_labs gt lab3 lab3 sdk standalone_bsp O ps _cortexa9_O include directory 6 1 4 From the File menu select File gt New gt Application Project 6 1 5 Name the project TestApp and in the Board Support Package section select Use existing to select standalone_bsp_0 and click Next g XILINX www xilinx com support university ZYNQ 3 19 xup xilinx com copyright 2014 Xilinx Embedded System Design using IP Integrator Lab Workbook 50K New Project os Application Project Create a managed make application project Project name V Use default location C xup sys_design labs lab3 lab3 sdk TestApp default v Target Hardware Hardware Platform system_wrapper_hw_platform_0 v Processor ps7_cortexa9_0 v Target Software Language C C OS Platform standalone Board Support Package Create New TestApp_bsp standalone_bsp_0 Figure 27 Application project settings 6 1 6 Select Empty Application and click Finish This will create a new application project directory named TestApp under lab3 sdk directory 6 1 7 Expand TestApp in the project view and right click on the src folder and select Import 6 1 8 Expand General category and double click on File System 6 1 9 Browse to lt 2014 2 zynq_sources gt lab3_zed for ZedBoard or lt 2014 2 zynq_ sources gt lab3_zybo for Zybo 6 1 10 Select lab3 c and click Finish A snippet of the
25. ties EEA E el eat e gt k IF sw_4bit Name sw _4bit Parent name system General Properties Figure 13 Change AXI GPIO default name Lab Workbook 3 1 4 Double click on the AXI GPIO block to open the customization window If a board specify was selected during the project creation and board files were available for the Zybo Vivado has knowledge of available resources on the board 3 1 5 Click on Generate Board Based IO Constraints and under Board Interface for GPIO ZedBoard Click on Custom to view the dropdown menu options and select sws 8bits f LF Re customize IP AXI GPIO 2 0 P w Documentation L5 IP Location Show disabled ports Component Name zynq_axi_gpio_1_0 a Board IP Configuration V Generate Board based IO Constraints s qP5_AXI Associate IP interface with EM AYNET COM ZYNQ ZED D Board interface saxi ack GPIO P s_axi_aresetn a stom O f Cusstom J btns Sbits leds 8bits Enable Interrupt sws bits Cancel Figure 14 Configuring GPIO instance for switches on ZedBoard ZYNQ 3 8 www xilinx com support university xup xilinx com copyright 2014 Xilinx amp XILINX Lab Workbook Embedded System Design using IP Integrator Zybo Click on Custom to view the dropdown menu options and select sws 4bits oF Re customize IP o ee a AXI GPIO 2 0 i Documentation L3 IP Location Show disabled ports Component Name system_axi_gpio_
26. un Connection Automation and select sw_8bit S_AXI for the ZedBoard or sw_4bit S_AXI for the Zybo 3 1 9 Click OK when prompted to automatically connect the master and slave interfaces g Run Connection Automation a lm 2S i Connect Slave interface sw_8bit S_AXT to a selected Master address space Master processing_system7_0 M_AXI_GP0 Clock Connection for unconnected clks Auto Figure 16 Run Connection Automation for ZedBoard Run Connection Automation Eee le 2 i Connect Slave interface sw_4bit S_AXI to a selected Master address space Master processing_system7_0 M_AXI_GP0O Clock Connection for unconnected clks Auto Figure 16 Run Connection Automation for Zybo 3 1 10 Notice two additional blocks Proc Sys Reset and AXI Interconnect have automatically been added to the design The blocks can be dragged to be rearranged or the design can be redrawn ZYNQ 3 10 xilinx com support universit OT ae amp XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator rst_ processing _system7_0_100M processing_system _O_axi_periph mb _ reset ext_reset_in bus_struct_reset 0 0 aux _reset_in penpheral_reset O 0 mb debug ssr intenoonnect_aresetn 0 0 a dom _locked perpheral_aresetn 0 0 AXI GPIO gi a DDR h FIXED _IO H A FIXED IO M_AXI_GPO_ACLK Z YNO M_AXI_GPO4E i FOLK_CLKOF FOLK_RESETO_N ZYNQ Process
27. vado manage wrapper and auto update click OK 4 1 7 In the Flow Navigator click Run Synthesis Click Save when prompted and when synthesis completes select Open Synthesized Design and click OK 4 1 8 In the shortcut Bar select I O Planning from the Layout dropdown menu 22 Default Layout hi 22 Default Layout 1 0 Planning 25 Clock Planning 25 Floorplanning Figure 23 Switch to the IO planning view 4 1 9 ZedBoard In the I O ports tab expand GPIO_42989 gt BTNs_5bit_tri_i and notice pins have already been assigned to this peripheral The pin information was included in the board files and automatically assigned when the IP was connected to the port The sw_8bit_tri_ihave also been automatically assigned pin locations along with the other Fixed ports in the design Name Direction Board Part Pin Board Part Interface Neg Diff Pair Site Fixed Bank YO Std A A x c H All ports 143 w DDR_1497 71 In Out Iv Multiple FIXED_IO_1497 59 In Out m Multiple kg GPIO_42989 5 Input iv 34 LVCMOS25 op EW btns_5Sbits_tri_i 5 Input m 34 LVCMOS25 Der btns_5bits_tri_i 4 Input btns_5bits_tri Tis W 34 LVCMOS25 btns_5Sbits_tri_i 3 Input btns_5bits_tri Ris V 34 LVCMOS25 btns_5Sbits_tri_i 2 Input btns_5bits_tri N15 W 34 LVCMOS25 v btns_5Sbits_tri_i 1 Input btns_5bits_tri R16 34 LVCMOS25 btns_Sbits_tri_i 0 Input btns_5Sbits_tri Pi6 Wi 34 LVCMOS25 Sc
28. x is checked Click Next 1 1 5 Select RTL Project in the Project Type form and click Next 1 1 6 Select Verilog as the Target language and as the Simulator language in the Add Sources form and click Next 1 1 7 Click Next two more times to skip Adding Existing IP and Add Constraints 1 1 8 In the Default Part form select Boards specify and either select ZedBoard or Zybo Click Next 1 1 9 Check the Project Summary and click Finish to create an empty Vivado project ZYNQ3 2 S Wwwxilinx com support university YH INIY xup xilinx com XILINX copyright 2014 Xilinx Lab Workbook Embedded System Design using IP Integrator Create the System Using the IP Integrator Step 2 2 1 Use the IP Integrator to create a new Block Design and generate the ARM Cortex A9 processor based hardware system 2 1 1 Inthe Flow Navigator pane click Create Block Design under IP Integrator 2 1 2 Enter system for the design name and click OK gs Create Block Design m lt Se o Please specify name of block design Design name system Directory lt Local to Project gt Figure 2 Create New Block Diagram 2 1 3 IP from the catalog can be added in different ways Click on Add IP in the message at the top of the Diagram panel or click the Add IP icon iF in the block diagram side bar press Ctrl I or right click anywhere in the Diagram workspace and select Add IP Diagram X ite
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