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MPC8349EA MDS Processor Board User Manual

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1. Pressing button SWB results in a Hard Reset for the MPC8349EA Not available when installed in a PC HRESET Pressing button SW9 results in a Soft Reset for SW9 the MPC8349EA Despite the reset clock and Soft Reset chip select data as well as SDRAM if installed contents are retained SRESET Not available when installed in a PC MPC8349EA MDS Processor Board Rev A Freescale Semiconductor Figure 4 2 MPC8349EA MDS Processor Board Push Buttons and Auxiliary POR MPC8349E A MDS Processor Board Rev A 4 6 Freescale Semiconductor Chapter 5 Functional Description In this chapter the design details of various modules of the MPC8349EA MDS Processor Board are described This includes memory map details and software initialization of the board 5 1 Reset amp Reset Configuration There are several reset sources on the MPC8349EA MDS Processor Board e Power On Reset Manual Hard Reset Manual Soft Reset e MPC8349EA see also the MPC8349EA Reference Manual 5 1 1 Power On Reset The power on reset to the MPC8349EA MDS Processor Board initializes the processor s state after power up dedicated logic unit asserts PORESET input for a period long enough to cover the MPC8349EA core voltage stabilization When the MPC8349EA MDS Processor Board is working in Stand Alone Mode or PIB Combined Mode a Power On Reset may be generated manually as well by an on board dedicated push button S
2. ue SUR 18 Chip framework alignment correct Figure 7 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 7 10 Figure 7 19 Chip framework alignment incorrect MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 7 11 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor MPC8349EA MDS Processor Board Rev A Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O B
3. SW4 7 DIP Switch Defined by operating configuration Defined by operating configuration Setup defined Freescale Semiconductor Table 5 5 BCSR4 Description Offset 4 Default BIT MNEMONIC upon PORESET 7 DDR2 SDRAM Clock Mode If this bit set high the DDR2 SDRAM memory controller operates with frequency equal to twice the frequency of the csb cik If this bit is low the DDR2 SDRAM memory controller operates at the csb cik frequency The DIP switch SW6 6 may change DDRCM bit setting May be rewritten any time via JTAG LBIU 5 2 6 BCSR5 Board Control Status Register 5 On the board the BCSR acts as a control register The BCSRS which may be read or written at any time receives its defaults immediately after the PORESET signal The BCSRS fields are described below in Table 5 6 Table 5 6 BCSR5 Description Offset 5 Default MNEMONIC upon PORESET TSEC1M TSEC port 1 Config Mode Two bits select standard reduced versus width and the protocol used by the TSEC1 controller See Table 5 7 May be rewritten any time via JTAG LBIU TSEC2M TSEC port 2 Config Mode Two bits select standard reduced versus width and the protocol used by the TSEC2 controller See Table 5 7 May be rewritten any time via JTAG LBIU TSEC1MST GETH1 Master Mode If high GETH1 transceiver configures in Master Mode Otherwise when low GETH1 transceiver operates as Slave May be rewritten any time via JTAG LBIU TSEC2MST GETH2
4. Status Register 2 5 4 5 24 BCSR3 Board Control Status Register 3 oa oven RA kv 5 5 5 25 BCSR4 Board Control Status Register 4 5 6 5 2 6 BCSRS Board Control Status Register 5 5 7 5 2 7 BCSR6 Board Misc Register at 10005 0055 da epee res Paw aU Late da 5 8 5 2 8 BCSR7 Board Misc Register Zeus sea ka hes Coe BEES bh v 5 8 5 2 9 BCSR8 Board Misc Resister masa real ete aa 5 9 5 2 10 BCSR10 Board Status Register 1 2 nst due notant ee dames asa 5 10 5 2 11 BCSR11 Board Status Register 2 sos da uussa ks A cad De aw ao 5 10 5 2 12 CCR COP Control Register ii ua EA rage A an tan 5 11 53 External COnnecnOns ns stenen a 0 a cade 0 i entend ld RU ee wn Sr 5 12 5 3 1 Ps MiB USB Connector si snt ai e e preia Pes Gun biien 5 12 5 3 2 P DUSR EPO aan aara 000 ul daca al o da pia ha E 5 12 5 3 3 Logic Analyzer Connectors sed AI O A ded 5 13 5 3 4 Poe NB CONES puk s A a wed Se dn 5 13 5 3 5 POS Debus COR COMNCELOF if sua si Beten A 5 13 5 3 6 P10 FPGA s In System Programming ISP 5 14 5 3 7 PIL Power Connector assedi ra A A Weed 13 tn 5 15 5 3 8 J1 J2 Ethernet Port Connector ccc ee eee eee eee ees 5 15 Chapter 6 Clocking 6 1 MPCS349R A as Host Device fes SA t kada pede ees Mie r n 6 1 62 MPC83J49EA as ACE aa aia WARE KEINO K Suk nee 6 2 MPC8349EA MDS Processor
5. SODIMM Memory release retaining clips MPC8349EA MDS Processor Board Rev A 7 4 Freescale Semiconductor up PE a MALU c Figure 7 9 SODIMM Memory remove unit 7 3 Replacing MPC8349EA Processor To remove the MPC8349EA processor follow the instructions in Figure 7 10 to Figure 7 19 below To replace the MPC8349E A processor follow the instructions in Figure 7 19 to Figure 7 10 below in that order Note that the Allen wrench is provided in the tool kit When replacing the framework of the chip make sure that it is properly aligned as shown in Figure 7 18 Incorrect alignment is shown in Figure 7 19 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 7 5 Figure 7 11 Remove Allen screws by hand MPC8349EA MDS Processor Board Rev A 7 6 Freescale Semiconductor Figure 7 12 Allen screws removed Figure 7 13 Remove heat sink MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 7 7 TIBIA TALMA pe LIN TR TETE TETE aati m SUN u Alignment Indicator i aligned correctly 3 8 E v v HR ria Figure 7 15 Chip alignment Correct MPC8349EA MDS Processor Board Rev A Freescale Semiconductor la i Figure 7 16 Chip alignment Incorrect MPC8349EA MDS Processor Board Rev A CH CAS A TETONA H EE GS MRC 190 ra Freescale Semiconductor Figure 7 17 Remove chip J Pollet
6. the debug host may initialize the memory controller via the JTAG COP connector in order to allow additional access to bus addressable peripherals The DDR2 SDRAM and FLASH PSRAM optional memories respond to all types of memory access program data and Direct Memory Access DMA Table 3 1 MPC8349EA SYS Memory Map Window Volume Port Address Range Target Device Name Size in Number in Bytes Bits 00000000 OFFFFFFF DDR2 SDRAM WV3HG32M72EEU403PD 256MB 00000000 Main SODIMM 4GG with ECC 1GB 64 8 7 3FFFFFFF CS2 CS3 for 256MB space ECC Or 10000000 1FFFFFFF DDR2 SDRAM WV3HG128M72EEU PD4 256MB 40000000 Second SODIMM with ECC for 1GB space 1GB TFFFFFFF optional optional not supplied with CS0 CS1 board 5 80000000 9FFFFFFF PCI1 Inbound Outbound window 512MB 32 64 6 A0000000 BFFFFFFF PCI2 Empty Inbound Outbound window 512MB 32 C0000000 Empty Space 512MB DFFFFFFF 0 E0000000 EOOFFFFF 8349 Internal Memory Register 1MB 32 Space E0100000 EFFFFFFF Empty Space 256MB 3 F0000000 F2FFFFFF Local Bus MT48LC16M16A2TG 6A x 64MB 32 8 F0000000 SDRAM optional 2 128MB parity F4FFFFFF on CS2 MT48LC16M16A2TG 6A x 1 for parity MT48LC32M16A2TG 7E F5000000 F7FFFFFF Empty Space 64MB F8000000 F8007FFF BCSR on CS1 Xilinx FPGA 32KB 8 F8008000 FDFFFFFF Empty Space 96MB MPC8349EA MDS Processor Board Rev A Freescale
7. 333MHz Flash Memory 32MB space 16bits wide 8MB space 16bits wide 1 1 3 Working Configurations 1 1 3 1 Stand Alone The MPC8349EA MDS Processor Board can be run in a stand alone mode like other ADS s with direct connections to deubggers via a JTAG COP connector and JTAG Parallel Port command converter power supply and the GETH MiniAB USB and Dual RS 232 DUART connections In this mode the MPC8349EA MDS Processor Board acts as a Host 1 1 3 2 With PIB board PIB Combined Mode The MPC8349EA MDS Processor Board can be connected to the PIB which allows it to be used in a back plane and provides room and connections for an additional USB board and up to three additional PCI cards Each of the PCI cards provides a connection interface for an optional additional processor board from the MPC83xx family This capability allows the MPC8349 processor on the MPC8349EA MDS Processor Board to act as a master for up to three slave processors in the MPC83xx family In this mode the MPC8349EA MDS Processor Board acts as a Host Voltage is provided by the PIB which also provides additional signal connections via the back plane if used and optical GETH connectors on the front plane side of the PIB The MPC8349EA MDS Processor Board can be connected to a PC in this configuration via a parallel port connector without needing an external command converter 1 1 3 3 PCI Add On Agent Mode Using its
8. Analyzer Connector on mux bus for evaluation only e Two Hi speed Riser Connectors to enable connection to the PIB Board Debug port access via dedicated 16 pin connector COP via PCI port or from parallel port interface on the PIB MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 1 5 1 6 One I2C port for EEPROM 256Kbyte Real Time Clock RTC and SODIMM SPD EEPROM parts the second I2C port connects to the Board Revision Detect IKbyte EEPROM Can function in one of three configurations Stand alone As a PCI add in card for a standard PC computer Agent Mode PIB combined mode development platform with Processor Board and PIB connected together Board Control and Status Register BCSR implemented in Xilinx FPGA Three power options Main SV power is fed from external power supply for stand alone mode Power from PC supply when acting as a PCI add in card Power from the PIB when PIB and Processor Boards are combined PCI add in card form factor dimensions 285mm x 106mm External Connections The MPC8349EA MDS Processor Board interconnects with external devices via the following set of connectors P1 MiniAB USB connector P2 RJ45 10 for DUART signals P3 P6 P7 P8 four Logic Analyzer MICTOR Connectors P4 64 bit PCI Edge Connector P5 SMB RF Connector for external pulse generator not assembled P9 16 pin COP JTAG Connector P10 16 pin header fo
9. Board continue from Section 2 2 2 Agent Mode installed in a PC continue from Section 2 2 3 2 2 1 Stand Alone Mode For Stand Alone Mode only Connect the four plastic spacers See Figure 2 1 and Figure 2 2 Connect external cables in accordance with your laboratory environment Connect PSU to P11 and turn the power on off switch to ON Verify that LD1 and LD2 turn on and turn off see Figure 2 3 for location They should be on for only a few moments This indicates that the board has successfully completed the boot up sequence A E MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 2 1 Tightening Spacers x4 Figure 2 2 Tightening Plastic Spacers MPC8349EA MDS Processor Board Rev A 2 2 Freescale Semiconductor om Figure 2 3 Boot Up sequence LD1 and LD2 turn on then off 2 2 2 For PIB combined mode only 1 Remove protective covers from the 300 pin connectors on the bottom side of the processor board See Figure 2 4 2 Remove protective covers from the 300 pin connectors on the PIB board see Figure 2 5 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 2 3 z Remove protective cover by hand Figure 2 4 Remove Protective Covers from 300 pin connectors underside of MPC8349EA MDS Processor Board shown Protective Covers Figure 2 5 Remove Protective Covers from 300 pin connectors underside of PIB shown MPC8349EA MDS Processor Bo
10. Board Rev A ii Freescale Semiconductor Chapter 7 Replacing Devices 7 1 Replacing Flash MEMO Y erts ir Du k Ad 7 1 7 1 1 Cleaning Flash Memory sa sars ties PR ESAS A E No 7 3 72 Replacing SODIMM UNAS 3255 mes as BA AN ES NN 7 4 7 3 Replacing MPC8349EA Processors sont R hr oe A SN ARA S IE A eS 7 5 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor iii MPC8349EA MDS Processor Board Rev A Freescale Semiconductor Chapter 1 General Information 1 1 Introduction This document describes the MPC8349EA MDS Processor Board in its stand alone operating mode in addition to its operating mode via a PCI slot in a PC or its operating mode on the PowerQUICC MDS Platform I O Board PIB 1 1 1 MPC8349EA MDS Processor Board The MPC8349EA MDS Processor Board is an ADS that provides a complete debugging environment for engineers developing applications for the MPC8349EA series of Freescale processors The MPC8349EA is a cost effective general purpose integrated host processor that implements the PowerPC architecture required for networking infrastructure telecommunications Wireless LANs and other embedded applications The MPC8349EA can also be used for control processing in applications such as network routers and switches mass storage subsystems network appliances and print and imaging systems The MPC8349EA MDS Processor Board includes various peripherals such as data input output devices
11. GETH USB DUART memories DDR2 SDRAM optional Serial EEPROM PSRAM optional amp FLASH and BCSR s registers and control switches and LED indicators Using its on board resources and debugging devices a developer is able to upload code run the code set breakpoints display memory amp registers and connect his own proprietary hardware to be incorporated into a target system that uses the MPC8349EA as a processor The software application developed for the MPC8349 can be run in a bare bones operation with only the MPC8349 processor or with various input or output data streams such as from the GETH connection PCI or the USB connections Results can be analyzed using the Code Warrior debugger in addition to using other methods for directly analyzing the input or output data stream The BSP is built using the Linux OS This board can also be used as a demonstration tool for the developer For instance the developer s application software may be programmed into its Flash memory and run in exhibitions MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 1 1 1 1 2 MPC8349EA MDS vs MPC8349E MDS Differences The MPC8349EA MDS is an upgrade to the MPC8349E MDS and has the following new features Table 1 1 MPC8349EA MDS vs MPC8349E MDS Differences DDR MPC8349EA MDS MPC8349E MDS DDR2 DDR1 512MB space 72bit wide 256MB space 64bit wide 64bits data 8bits ECC Data rate 400MHz Data rate
12. MNEMONIC Function Defn CNFLOCK Config Bit Lock When low BCSR contents don t update during 1 PORESET High provides normal operation when BCSR default Set at value is set according DIP switches Used for debug purpose Power On May be rewritten any time via JTAG SPARE8 Not Implemented 4111111 5 2 10 BCSR10 Board Status Register 1 The BCSR 10 is a read only status register The BCSR 10 fields are described below in Table 5 11 Table 5 11 BCSR10 Description Offset 0xA MNEMONIC Function PCI HOST PCI HOST Indicates the boar s working mode This is high when installed in a PC Agent Mode and low when in Stand Alone or PIB Combined Mode 1 QUISCE QUISCE Status Allows the processor to determine the power down mode when bit is low by reading via JTAG If the bit is high the power down mode is determined by internal processor logic regardless of JTAG settings SWOP Software Option Three bit code reading from the SW2 switch 5 FCFG FLASH Configuration When high and configuration source set as Local Bus BCSR1 1 3 0 the RCW is loaded from FLASH if low the RCW is loaded from the BCSR 5 2 11 BCSR11 Board Status Register 2 The BCSR11 Register is a status register accessed from the Local Bus The BCSR11 fields are described below in Table 5 12 Table 5 12 BCSR11 Description Offset 0xB BIT MNEMONIC Function Attr 0 3 REV BCSR Revision Four most significant bits revision coding Progr
13. Master Mode If high GETH2 transceiver configures in Master Mode Otherwise when low GETH2 transceiver operates as Slave May be rewritten any time via JTAG LBIU INT USB Internal USB phy If high on board USB phy is tied to USB port 0 MPC8349EA When working in the PIB Combined Mode the combined INT USB bit initiates low to select off board USB phys and mode disable on board USB phy Wrong programming in PIB Combined 1 for other Mode may cause USB digital signals contention modes MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 7 Table 5 7 TSEC Port Mode Setting Value TSEC Mode 00 The TSEC controller operates in the RGMII protocol using only four transmit data signals and four receive data signals The TSEC controller operates in the RTBI protocol using only four transmit data signals and four receive data signals The TSEC controller operates in the GMII protocol using eight transmit data signals and eight receive data signals The TSEC controller operates in the TBI protocol using eight transmit data signals and eight receive data signals 5 2 7 BCSR6 Board Misc Register 1 On the board the BCSR6 acts as a control register The BCSR6 which may be read or written at any time receives its defaults immediately after PORESET signal The BCSR6 fields are described below in Table 5 8 Table 5 8 BCSR6 Description Offset 6 Default MNEMONIC Function upon PORESET
14. Semiconductor Table 3 1 MPC8349EA SYS Memory Map Window Volume Port Address Range Target Device Name 5 Size in Number in Bytes E Bits FE000000 FE7FFFFF FLASH on CSO MT28F640 8MB or or 16 FE000000 FE3FFFFF PSRAM on CSO TC51WHM516AXBN70 4MB optional FE800000 FFFFFFFF Empty Space 24MB PCI2 Memory Space defined for PCI2 host mode The memory map defined in Table 3 1 MPC8349EA SYS Memory Map is only a recommendation The user can choose to work with alternative memory mapping It should be noted that the described mode is supported by the Code Warrior debug tool MPC8349EA MDS Processor Board Rev A 3 2 Freescale Semiconductor Chapter 4 Controls and Indicators This chapter describes controls and indicators of the MPC8349EA MDS Processor Board This includes switches jumpers LEDs and other miscellaneous controls and indicators 4 1 Switches and Jumpers Locations Figure 4 1 below shows the locations of the Jumpers and DIP Switches Note that when ON the value of the switch is zero Jp2 JP3 DIP Switches epee m A pan T JP1 Figure 4 1 MPC8349EA MDS Processor Board Switches and Jumpers Locations MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 4 1 4 1 1 Switches SW3 Configuration Set 1 SW3 1 SW3 3 CFG_RS sets the Reset Configuration Words Source ON value of zero factory setting 000 when RCW is fetched from th
15. connect the power supply to the voltage input as shown in Figure 2 10 Figure 2 10 Connecting Power input to the PIB 8 Ifyou wish to work with the USB card or any of the PCI cards follow the illustrations in Figure 2 11 Figure 2 12 and Figure 2 13 to connect these cards to the PIB Note that the USB card can only be inserted in the upper most section as shown The PCI card can be inserted in any section for up to 4 PCI cards up to 3 if using also a USB card MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 2 7 Connect using PCI car s 1 latches as shown am T HE S hand Figure 2 13 Inserting spacers between PCI card and PIB 9 The fully assembled PIB Processor board is shown in Figure 2 14 which also shows the PIB external connections relevant when the MPC8349EA is used All external connections of the Processor board are active when the Processor board is installed on the PIB except the voltage input recieves power from the PIB power input or the back plane MPC8349EA MDS Processor Board Rev A 2 8 Freescale Semiconductor only and the JTAG COP connection P9 which is replaced by the parallel port connection to a PC Three PCI cards and one USB card are shown installed on the PIB The PCI cards are ready to receive any 83xx Processor board installed in this case in the same manner as they are in a PC Using this system these processor boards up to three function as slaves wh
16. for the MPC8349EA can be done by toggling bit 4 in the CCR register 5 1 2 3 Manual Soft Reset To allow a run time Soft reset manual Soft reset is facilitated via SW9 Note that this cannot be done when the MPC8349E A MDS Processor Board is connected in a PC Agent Mode In addition a manual hard reset for the MPC8349EA can be done by toggling bit 5 in the CCR register 5 2 Board Control 8 Status Registers BCSR The BCSR is an 8 bit wide read write register file that controls or monitors most of the MPC8349EA MDS Processor Board hardware options The BCSR s register may be accessed from the Local Bus or via the FPGA internal JTAG controller The BCSR includes up to 16 registers some of which are optional BCSR registers are duplicated numerous times within a CS1 region This is due to the CS region s 32KB minimum block size and the fact that only address lines A 28 31 are decoded for register selection by the BCSR BCSR is implemented on a Xilinx FPGA device that provides register and logic functions over some MPC8349EA MDS Processor Board signals The BCSR controls or monitors the following functions 1 Power on Reset amp Hardware configuration setting for the processor 2 Most of the Hardware Reset Configuration bits are stored in BCSR registers available from the Local Bus or JTAG 3 Hard Soft Reset and NMI IRQ pushbuttons debounce function 4 Hardware Configuration for the both GETH transceivers 5 Enable Disa
17. 4 1 2 JUMPER tente Ra n A MRS O LAN Ne a A Ne TN 4 2 1 LD1 LD2 Signaling LEDs sn e A nA vaa v 4 2 2 LDS lt USB EOWEl parar aa ne aci pesadelo adm ba ces ha ti 4 2 3 LDA EDS GETH Enable 0 an qui atnto n SALSA D O 4 2 4 ED6 DUART Enable ornaat A tas a 4 2 5 LD7 FUNG Indication sussa 2 onu VA no 4 MPC8349EA MDS Processor Board Rev A 1 2 1 2 Freescale Semiconductor 4 2 6 LDS Power GOOD ss aa ner NaS senti VS Dona e n pi SEEN Sin de 4 4 4 2 7 ED9 lt GPIO EL Indico as ii ATER ape A a al 4 4 4 2 8 EDIO ALDIE PCTEOL USB hm R a 4 4 4 2 9 EDI2 BOOT Indicator cuia rana dada Ma a RE a TA a Sw 4 4 4 4 2 10 EDI E53 9 Power Indicator sas sr rent landis ent Ea Sout Kee en Se 4 4 4 3 Other Controls and Indicators 2 RE Aa oo 00 ea Da aul 4 5 Chapter 5 Functional Description 5 1 Reset amp Reset Configuratio Ludacris 5 1 5 1 1 Power On Reset zo do A ee awe ae O a A mettent 5 1 5 1 2 Hard RESCl anc Da a ts A 5 1 5 1 2 1 COP JTAG Port Hard Reset stand alone only 5 2 5 1 2 2 Manual Hard Reset a ae Sa Ma En 5 2 5 1 2 3 Manual Soft REsCL seeni keea aed E te a ai A ee kek i al ba 5 2 5 2 Board Control amp Status Registers BCSR 5 2 5 2 1 BCSRO Board Control Status Register O 5 3 5 2 2 BCSRI Board Control Status Register 1 5 4 5 2 3 BCSR2 Board Control
18. DI and changes the state of the JTAG machines This line is pulled up internally by the MPC8349EA MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 13 Table 5 17 P9 JTAG COP Connector Pin No Signal Name Attr Description 11 nSRSTc O P U When asserted by an external HW generates Soft Reset sequence for the MPC8349EA Pulled Up on the ADS using a 4 7KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might resultin permanent damage to the processor and or to ADS logic 13 nHRSTC O P U When asserted by an external HW generates Hard Reset sequence for the MPC8349E A Pulled Up on the ADS using a 4 7KQ resistor When driven by an external tool MUST be driven with an Open Drain gate Failure to do so might resultin permanent damage to the processor and or to ADS logic 14 KEY No pin in connector Serves for correct plug insertion See Figure 9 1 for location 15 Check Stop Output O Machine Check Stop Output X X X X X X X X X O X X X X X X 16 14 2 Figure 5 1 P9 COP connector front view 5 3 6 P10 FPGA s In System Programming ISP This is a 16 pin generic 0 100 pitch header connector providing In System Programming capability for on board programmable logic devices by Xilinx FPGA Spartan 2E The pinout of P10 is shown in Table 5 18 P10 FPGA Programming ISP Connector below
19. LL Multiplication Factor The seven bits reflect SW7 1 7 COREPLL 0 6 signals logic level during Hard Reset Configuration sequence The bits are set by default by appropriate DIP switch SW7 1 7 May be rewritten via JTAG LBIU Software Watchdog Enable The bit reflect SWEN signals logic level during Hard Reset Configuration seguence The bit are setby default by appropriate DIP switch SW6 8 May be rewritten via JTAG LBIU MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 5 5 2 5 BCSR4 Board Control Status Register 4 On the board the BCSR4 acts as a control register The BCSR4 which may be read or written at any time receives its defaults immediately after PORESET signal The BCSR4 fields are described below in Table 5 5 MNEMONIC Table 5 5 BCSR4 Description Offset 4 Function Default upon PORESET PCIHOST PCI64 PCI1ARB COREDIS BIT 0 PCIZARB i LBIUCM PCI Host Mode If working as a PCI add in card Agent Mode this bit is set low When the MPC8349EA MDS Processor Board is combined with the PIB PIB combined mode the PCIHOST bit will be high to set PCI processor s port as the host mode May be rewritten via JTAG PCI 64 bit Mode The bit reflects PCI64 signal logic level during Hard Reset Configuration seguence When it is low the PCI1 2 ports are 32 bit mode if high the PCI1 port uses 64 bit I F The bit is controlled by the appropriate DIP switch SW4 7 May be rew
20. MPC8349EA MDS Processor Board User Manual Rev A 12 2006 4 N s fre escale semiconductor MPC8349EA MDS Processor Board Rev A Freescale Semiconductor Contents Chapter 1 General Information 1 1 Ito domi ssa ssa buka uda bob daras 1 1 1 MPC8349EA MDS Processor Board 1 1 2 MPC8349EA MDS vs MPC8349E MDS Differences 1 1 3 Working Configurations usas ss Kon ksi Ks dn K 1 1 3 1 Stand Oda a E E E 1 1 3 2 With PIB board PIB Combined Mode 1 1 3 3 PCI Add On Agent Mode 12 Definitions Acronyms and Abbreviations 13 Related Documentation ns veerde eet sE de Se EE 14 gt SPC CMC ALON hes arene aa hdd NO VS Kan a 1 5 MPC8349EA MDS Processor Board Features 1 6 External Connections so OKA T SEs A aa 1 77 2BI6CKDiaSt mnsest A r a de Chapter 2 Hardware Preparation and Installation 2 1 Unpacking Instructions oa a usa SE k o Le 2 2 Installation Instructions po a V a Vi 2 2 1 St nd Alonemode hd Aorta ander odd De vak de as DDD For PIB combined modeonly i234 a e 4 34044 SA a n 225 For Agent mods Only nand Nasa a v Kaan Chapter 3 Memory Map 3 1 MPC8349EA MDS Processor Board Mapping Chapter 4 Controls and Indicators 4 1 Switches and Jumpers Locations aia ape tes sevens 4 1 1 SWITCHES sc ra enten ew AA AR
21. PCI edge connector the MPC8349EA MDS Processor Board can be inserted in a PC Power and debugging are supplied from the PC no command converter necessary Other external connections are the same as in the Stand Alone Mode In this mode the MPC8349EA MDS Processor Board acts as an Agent MPC8349EA MDS Processor Board Rev A 1 2 Freescale Semiconductor 1 2 Definitions Acronyms and Abbreviations ADS Application Development System BCSR Board Control and Status Register BRD Board Revision Detect I2C EEPROM BSP Board Support Package CCR COP Control Register FPGA COP Common On chip Processor JTAG Debug Port CS Chip Select CW Metrowerks Code Warrior IDE for PowerPC DAC Digital to Analog Converter DDR Double Data Rate DIP Dual In Line Package DMA Direct Memory Access DUART Dual UART EEPROM Electrical Eraseable Programmable Memory FCFG Flash Configuration Select FCI Type of Riser Connector FLASH Non volatile reprogrammable memory FPGA Field Programmable Gate Array GbE Gigabit Ethernet GETH Gigabit Ethernet GPCM General Purpose Chip select Machine GPL General Purpose Line 12C Philips Semi Serial Bus LED Light Emitting Diode Isb least significant bit MII Media Independent Interface GMII General Media Independent Interface JTAG Joint Test Access Group OTG On the Go PC IBM compatible Personal Computer PCI Peripheral Components I
22. SPARE60 Not implemented N A RW Test Port Enable Should be set high to place the processor in RW Test Mode When low the processor operates in normal mode May be rewritten any time via JTAG True Little Endian Low selects Big Endian Mode High value RW provides Little Endian Mode May be rewritten any time via JTAG Local Bus Timing When bit sets high LALE has earlier negation RW Low provides normal LALE timing May be rewritten any time via JTAG 4 JTAG2SEL JTAG Chain Select Select JTAG chain for external devices on PMC cards when high Low provides JTAG normal configuration SPARE65 7 Not Implemented om o 5 2 8 BCSR7 Board Misc Register 2 On the board the BCSR7 acts as a control register The BCSR7 which may be read or written at any time receives its defaults immediately after PORESET signals The BCSR7 fields are described below in Table 5 9 MPC8349EA MDS Processor Board Rev A 5 8 Freescale Semiconductor Table 5 9 BCSR7 Description Offset 7 Default MNEMONIC Function upon PORESET TESTEN Enable Chip Test Mode For Internal use only May be rewritten 0 any time via JTAG LEDs Enable All LEDs remain darkened for Failure Analysis purposes when set high When low the LEDs behave normally according to Section 4 2 LEDs May be rewritten any time via JTAG LBIU 2 SHMOOEN SHMOO Test Enable An enable signal to allow programming of 1 the Internal Core Power Supply and the application ofan ext
23. TLO 1 USB LED s LD10 LD11 green are used for extra visibility on the USB Port 1 4 29 LD12 BOOT Indicator The LD12 indicates MPC8349 boot processing 4 2 10 LD13 5V Power Indicator The green LED LD13 indicates a 5V power level on the MPC8349E A MDS Processor Board MPC8349EA MDS Processor Board Rev A 4 4 Freescale Semiconductor A 5V power supply is plugged into the P11 Power Connector on the board s front side for the Stand Alone Mode The MPC8349EA MDS Processor Board is powered by the 5V external power supply when the SW5 Power Switch is turned to the ON up position When the MPC8349E A MDS Processor Board is plugged into an PC via the PCI edge connector it 1s powered from the edge connector s 5V power rail Agent Mode In the PIB Combined Mode 5V power is supplied from the PIB s power supply via risers connectors Note that if working in either of these two modes the position of SW1 is ignored 4 3 Other Controls and Indicators Table 4 1 The MPC8349EA MDS Processor Board Push Buttons SW1 Power on Reset Pressing button SW1 results in Power On Reset for all components on the MPC8349EA MDS Processor Board Use this reset button when the MPC8349EA PRESET MDS Processor Board is installed in a PC Rotary Switch SW2 allows the user to change SW2 the program flow according to eight available Software Option cases SW OPT Not available when installed in a PC SW8 Slave Hard Reset
24. Table 5 18 P10 FPGA Programming ISP Connector Pin No Signal Name Attr Description 1 ISP TDO Transmit Data Output 2 10 12 GND P Main GND plane 16 3 ISP_TDI O Transmit Data In 4 5 8 11 1 N C Not Connected 3 14 15 MPC8349EA MDS Processor Board Rev A 5 14 Freescale Semiconductor Table 5 18 P10 FPGA Programming ISP Connector Pin No Signal Name Attr Description 6 SENSE P Connect to 3 3V power supply bus via protection resistor Use for programmer powering 7 ISP TCK O Test port Clock 9 ISP_TMS O Test Mode Select 5 3 7 P11 Power Connector P11 is 2mm Power Jack RAPC722 which provides a connection to an external power supply 5DC 2 5A 5 3 8 J1 J2 Ethernet Port Connector The Ethernet connectors on the MPC8349EA J1 J2 are both Twisted Pair 1000 Base T compatible connectors They are implemented with a 90 8 pin RJ45 Combo connector with internal magnetics and two LEDs indicating communication speed signals of which are described in Table 5 19 J1 J2 Ethernet Port Interconnect Signals below These connections are on the front panel For location see Table 1 2 Green LED indicates 1000Mbit Data rate Yellow LED is lit when 100Mbit Data rate mode Table 5 19 J1 J2 Ethernet Port Interconnect Signals Wire Color 10Base T 100Base T Signal 1000 Base T Signal Twisted Pair Transmit Data positive BI DA output 2 White Or
25. W1 In addition a power on reset for the MPC8349EA can be done by toggling bit 7 in BCSR7 5 1 2 Hard Reset Hard Reset may be generated on the MPC8349E A MDS Processor Board by any one of the following sources e COP JTAG Port in Stand Alone Mode only Manual Hard reset Internal sources Hard Reset when generated causes the MPC8349EA to reset all its internal hardware except for PLL logic and re acquires the Hard reset configuration from its current source Since hard reset also resets the refresh logic for dynamic RAMs their content is lost as well CAUTION HRESET is an open drain signal and must be driven with an open drain gate by whatever external source is driving it Otherwise contention will occur over that line and that might cause permanent damage to either board logic and or to the MPC8349EA MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 1 5 1 2 1 COPIJTAG Port Hard Reset stand alone only To provide convenient hard reset capability for a COP JTAG controller an HRESET line has been connected to the COP JTAG port connector The COP JTAG controller may directly generate a hard reset by asserting low this line 5 1 2 2 Manual Hard Reset To allow a run time Hard reset a manual Hard reset is facilitated via SW8 Note that this cannot be done when the MPC8349E A MDS Processor Board is connected in a PC Agent Mode but instead SW1 can be used In addition a manual hard reset
26. ammed value MPC8349EA MDS Processor Board Rev A 5 10 Freescale Semiconductor SubREV BCSR Revision Four least significant bits revision coding value Table 5 13 BCSR Revision Coding Revision Number 0 3 Board Revision 5 2 12 CCR COP Control Register CCR COP Control Register is a service register accessed from the Local Bus It is a part of PCIZJTAG converter for the Agent Mode when the Processor Board is plugged into a PC The CCR fields are described below in Table 5 14 Table 5 14 CCR Description Offset 0xF Default BIT MNEMONIC Function upon PORESET TDI TAP Data Input Drive serial Data into COP port Disabled W 0 TAP Data Output Read serial Data from COP port Disabled R 1 TCK TAP Clock When asserted low TAP clock is enabled and Disabled W driven into the COP port If negated high TAP clock is disabled TAP Mode Select Drive TMS signal into COP port Disabled TRST TAP Reset Reset TAP controller of COP port Disabled 4 HRESET Hard Reset Low provides short negative HRST pulse on the Disabled W board SRESET Soft Reset Low provides short negative SRST pulse on the Disabled board e CKSTPI Check Stop Causes Machine Check Stop of the processor Pw 7 COPEN CCR COP Enable Low permits access to processor JTAG port 1 W via CCR register High disables the CCR register MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 11 5 3 External Connection
27. ange Twisted Pair Transmit Data negative Bl DA output 3 White Green Twisted Pair Receive Data positive BI DB n input Twisted Pair Receive Data negative BI DB input MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 15 MPC8349EA MDS Processor Board Rev A 5 16 Freescale Semiconductor Chapter 6 Clocking This chapter describes the clocking and timing of the MPC8349EA while being used on the MPC8349EA MDS Processor Board Two primary clock sources are available for the MPC8349EA CLKIN or PCICLK depending on whether the device 1s a Host that is in Stand Alone or PIB Combined Mode or working in the Agent Mode inserted in a PC compatible computer Mode1 PCI SYNC OUT A DDR2 CLK 0 5 y M Bus Switch U52 U1001 v ZD c 3 Buffer CLK PCICLK s CI PCI SYNC IN o U1002 E ZD To 5 Buffer BCSR MPC8349EA 5 LSYNC OUT LBIU DLL LSYNC IN PCI CLK 0 5 To agent Mode3 JP1 u Programmable clock EXT Mode1 from PIB GEN Q Mode1 Host Modes Mode2 Agent Mode Mode3 SHMOO MODE on PIB Figure 6 1 Clocking Scheme 6 1 MPC8349EA as Host Device When the MPC8349EA is a Host device Stand Alone or PIB Combined Mode CLKIN is its primary input clock See the red colored lines and circuits in Figure 6 1 The MPC8349EA supports eight PCI CLK output signals not to be confused with the PCICLK signals which are only used in the Agent Mod
28. ard Rev A 2 4 Freescale Semiconductor Press down to fasten anani FALL LU LLL ea Figure 2 6 Connect Processor board to PIB and press down with fingers 3 Connect processor board to PIB board as shown in Figure 2 6 4 Ensure a tight fit by pressing down on the processor board by hand only until the pins engage see Figure 2 6 5 Manually fasten the four screws as shown in Figure 2 7 Figure 2 7 Fasten the four tightening screws 6 If you will be working with a back plane and wish GETH signals to traverse either the back plane connection or the front plane optical connection connect the two GETH sockets on the MPC8349EA MDS Processor Board with sockets on the PIB board as shown in Figure 2 8 and Figure 2 9 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 2 5 Note that if you do not do this you can still connect GETH cables directly to the Processor boar s sockets if they are accessible in your laboratory configuration GETH Inter connecting Cables GETH Inter connecting Cable connected Fa Figure 2 9 Connect GETH interconnecting cables to sockets on PIB MPC8349EA MDS Processor Board Rev A 2 6 Freescale Semiconductor 7 If you are not working with either the USB or the PCI cards and you will be working with the PIB in a table top configuration as opposed to inserting it in a rack to use its back plane connections you can at this point
29. ard Control Status Register 2 On the board the BCSR2 acts as a control register The BCSR2 which may be read or written at any time receives its defaults immediately after the PORESET signal The BCSR2 fields are described below in Table 5 3 MPC8349EA MDS Processor Board Rev A 5 4 Freescale Semiconductor Table 5 3 BCSR2 Register Description Offset 2 Default MNEMONIC Function upon PORESET SPMF 0 3 System PLL Multiplication Factor The four bits reflect SPMF 0 3 SW3 5 8 signals logic level during Hard Reset Configuration seguence The bits are set by default by appropriate DIP switch SW3 5 8 May be rewritten via JTAG LBIU 4 5 SVCODI4 5 VCO Division The two bits reflect SVCOD 4 5 signals logic level during Hard Reset Configuration seguence The bits are set low by default May be rewritten via JTAG LBIU 6 7 BOOTSEQ 6 7 Boot Sequencer Configuration The two bits reflect BOOTSEQ 6 7 signals logic level during Reset Configuration sequence The bits are set by appropriate DIP switch SW5 1 2 May be rewritten via JTAG LBIU 5 2 4 BCSR3 Board Control Status Register 3 On the board the BCSR3 acts as a control register The BCSR3 which may be read or written at any time receives its defaults immediately after the PORESET signal The BCSR3 fields are described below in Table 5 4 Table 5 4 BCSR3 Register Description Offset 3 Default MNEMONIC Function upon PORESET COREPLL 0 6 Core P
30. ated high the GETH Transceiver enters standby mode May be rewritten via JTAG LBIU GETH2EN GETH Transceiver 2 Enable Upon activation low the MPC8349EA TSEC port 1 transceiver is enabled When negated high the GETH Transceiver enters standby mode May be rewritten via JTAG LBIU BIT 0 2 GETHRST GETH Transceiver Reset The GETH devices are reset when the GETHRST is asserted low The Board Hard Reset signal of the MPC8349EA resets GETH devices May be rewritten via JTAG LBIU RS232EN UART Ports Transceivers Enable Upon activation low the Dual RS232 Transceiver using the UART ports of the MPC8349EA is enabled When negated high the RS232 Transceiver enters standby mode May be rewritten via JTAG LBIU BOOTWP BOOT I2C EEPROM Protect When asserted low BOOT EEPROM functions normally when negated high write operations are disabled May be rewritten via JTAG LBIU SIGNALO Signal LED 0 A dedicated Green LED is illuminated when SIGNALO is active low The LED is unlit when it is in an inactive default state high During the Reset Configuration seguence the LED indicates the SRESET assertion The user may utilize the LED for software Slave signalling purposes May be rewritten via JTAG LBIU MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 3 Table 5 1 BCSRO Description Offset 0 Default BIT MNEMONIC upon SIGNAL1 Signal LED Slave 1 A dedicated Red LED is illuminated when SIGNAL I i
31. ations CHARACTERISTICS SPECIFICATIONS Memory DDR2 512MB space 72bit wide 64bits data 8bits ECC in one SODIMM 200 Data rate 400MHz Local Bus SDRAM Optional Buffered Memory Flash on socket PSRAM optional BCSR on FPGA Expansion 64MB space 32bit wide 4bit parity implemented in three SDRAM parts 133MHz clock 32MB space 16bits wide 4MB space 16bits wide use for Flash emulation 16 registers 8bits wide Four banks with 16bit Address bus 16bit Data bus Operating temperature 0 C 70 C Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions according to PCI 64 bit Add in card form factor Length Width Height 285 mm 106 mm 16 mm 1 5 MPC8349EA MDS Processor Board Features Supports MPC8349EA running up to 667MHz at 1 2V Core voltage e DDR2 72 bit 400MHz on SODIMM Second SODIMM is optional PCI edge connector interfaces with 64 bit PCI bus used when inserted in a PC e Two 10 100 1000Mb sec Ethernet Phys on TSEC ports USB 2 0 ULPI High Speed OTG Transceiver Dual RS232 transceiver on one DUART port Flash Memory 32MB space 16 bit wide e Local Bus interface Three parts of 133MHz SDRAM memory optional 64Mbyte size with parity One 32Mbyte expandable Flash with 16bit port size in socket Address Latch and Buffers to support slow devices on the PIB Board Mictor Logic
32. ble to Two GETH1 2 Transceivers Dual RS232 Transceiver PSRAM if installed or FLASH select SHMOO function LED off 6 BCSR provides h w write protection for FLASH and BRD I2C EEPROM 7 Two LEDs one green one red provide s w signaling MPC8349EA MDS Processor Board Rev A 5 2 Freescale Semiconductor 8 Special CCR COP register for JTAG port connectivity 9 Status registers BCSR10 BCSR 11 include PCI Host Mode indicates 1f the Board is working in a Host Mode Stand Alone or PIB Combined or the Agent Mode Processor Low Power Mode QUISCE Software Option Identification set by SW2 Rotary Switch BCSR Revision code Sections of the BCSR slice control registers generally have low active notations This means that a bit function will be realized while the bit is zero When a bit is set to high a related function is disabled The default setting is assumed to be non functional The most significant bit 1s bit 0 5 2 1 BCSRO Board Control Status Register 0 The BCSRO serves as a 8 bit control register on the board The BCSRO may be read or written at any time BCSRO defaults are attributed immediately after a Power On Reset or HRESET BCSRO fields are described below in Table 5 1 Table 5 1 BCSRO Description Offset 0 Default MNEMONIC Function upon HRST GETHIEN GETH Transceiver 1 Enable Upon activation low the MPC8349EA TSEC port 1 transceiver is enabled When neg
33. default setting 10101000 MPC8349EA MDS Processor Board Rev A 4 2 Freescale Semiconductor SW6 Configuration Set 3 a A V o BOOT SEG0 ON BOOT SEQ1 ROMLOCO ROMLOC1 ROMLOC2 DDRCM LBIUCM N oak V Na BL gt Za AN Bret SW6 1 SW6 2 Boot seguencer configuration Boot seguencer loads configuration data from the serial ROM Factory setting 00 disables access to I2C ROM SW6 3 SW6 5 Boot ROM location Factory setting 110 provides flash boot on local bus SW6 6 DDR2 Clock mode Factory setting 0 operates with DDR2 clock identical to csb_clk SW6 7 Local bus clock mode Factory setting 1 operates with local bus clock half of csb_clk SW6 8 Software watchdog Factory setting 0 with software watchdog disabled Factory default setting 00110010 SW7 1 SW7 7 Core PLL setting Sets the ratio between the e300 core clock and the internal csb_clk Factory setting 000010000 for core clk 533MHz U asi Recommended secondary setting 00000110 for core clk 500MHz 1 COREPLLO Ca ON SW7 8 Core disable 2 COREPLL1 S E Factory setting 0 core enabled for boot operation 3 COREPLL2 N 7 4 COREPLL3 al E 5 COREPLLA M Factory default setting 00001000 6 COREPLL5 ol 7 COREPLL6 A E 8 COREDIS E 4 1 2 Jumpers JP1 Internal External Clock JP1 S
34. e These are divided into three groups Each group can be independently configured to provide the output clock as equal to or half of the frequency of CLKIN Six of these PCI_CLK clocks are used by the ADS for clocking agent cards that are plugged into the PIB CLKIN directly feeds the PCI CLK output clocks dividers and is also driven out on the PCI SYNC OUT pin for de skewing of the external PCI CLK clocks with the CLKIN signal MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 6 1 Since the PIB uses a programmable clock synthesizer this clocking mode will be preferable for chip verification To provide more flexibility an external pulse generator EXT GEN may be used via an SMB Hi Freguency connector 6 2 MPC8349EA as Agent When the MPC8349EA is working in the Agent Mode installed in a PC the MPC8349EA is synchronized with the clock from the Host PC as default via the PCI edge connector This clock is designated by PCICLK in Figure 6 1 see the blue colored lines and circuits Note that on the MPC8349EA chip only the PCI 1 port can work in Agent Mode the PCI 2 port cannot If when this mode is activated the PCI ports were found to be operating as a host the clock switch turns to position 1 so that the input clock to the MPC8349EA is driven by the clock received via the PCI edge connector MPC8349EA MDS Processor Board Rev A 6 2 Freescale Semiconductor Chapter 7 Replacing Devices This chapter p
35. e local bus ie 5 DIP switch SW9 3 FCFG chooses between BCSR or Flash RCW source 1 CFGRSO Da ON SW3 4 Z CFGRSI v E CLKDIV selects the relationship between CLKIN and PCI SYNC OUT 3 CFG_RS2 cd E if the MPC8349EA is configured as a PCI Agent factory setting then 4 CLKDIV TH CLK DIV is low amp SPMFO E SW3 5 SW3 8 6 SPMF1 off SPMF selects System PLL Multiplication Factor 7 SPMF2 H factory setting 0100 8 SPMF3 o a clock ratio csb_clk CLKIN 4 csb clk 266MHz or csb clk PCI CLK 4 The On DIP Switch position Factory default setting 00000101 corresponds to a signal value of Zero SW4 Configuration Set 2 SW4 1 SW4 2 TSEC1 TSEC2 Selects the protocol used by the two port TSEC controller fa sa factory setting enters GMII mode when TSEC1 and TSEC2 initiate similar 2b10 do 10 M N SW4 5 BMS Selects boot memory space cala N factory setting is 1 when boot memory resides in upper eight Mbytes at ee M OxFF80 0000 to OxFFFF FFFF TT 1 H SW4 6 TLE Selects endian mode PM OL factory setting 0 big endian mode E ie E SW4 7 PCI64 Selects PCI width ui L factory setting 0 32 bit width E SW4 8 FCFG Sets RCW source on local bus V BCSR source setting uses values from SW3 and SW6 Flash source setting is burned in flash memory Factory setting 0 Factory
36. ed Optional 5 3 5 P9 Debug COP Connector P9 is a Freescale standard JTAG COP connector for the PowerPC It is a 16 pin 90 two row header connector with key During debug all processors connected by the JTAG chain may be accessed through connector P9 The pinout of P9 is shown in Table 5 17 P9 JTAG COP Connector below Table 5 17 P9 JTAG COP Connector Pin No Signal Name Attr Description 1 TDOc Transmit Data Output This is the MPC8349EA JTAG serial data output driven by Falling edge of TCK 2 10 12 GND P Main GND plane 16 3 TDlc O Transmit Data In This is the JTAG serial data input of the MSC8101 sampled on the rising edge of TCK 4 NTRSTC O Test port Reset When this signal is active Low it resets the JTAG logic This line is provides a pull down on the ADS with a 4 7KQ resistor which provides a continuous reset of the JTAG logic when connector is unplugged 5 N C Not Connected 6 SENSE P Connect to 3 3V power supply bus via protection resistor May be used for Command Convertor power 7 TCKc O Test port Clock This clock shifts in out data to from the JTAG logic Data is driven on the falling edge of TCK and is sampled both internally and externally on its rising edge 8 Check Stop Input Machine Check Stop Input 9 TMSc O Test Mode Select This input selects test mode and is sampled on the rising edge of TCK This line is qualified with TCK in a same manner as T
37. elects the source for the CLOCKIN signal 4 If a jumper is located between JP1 pins 1 2 factory setting the processor is pa clocked from the on board clock oscillator U21 socket VSS Ifa jumper is located between JP1 pins 2 3 the processor is clocked from an 2 EN external source via P5 ZEN The SHMOO mode clock source is I2C manually programmed clock 3 synthesizer residing on PIB Internal External Clock Source Clock Source MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 4 2 LEDs The MPC8349EA MDS Processor Board has the following LEDs 4 2 1 LD1 LD2 Signaling LEDs LED s LD1 green and LD2 red are program controlled They are used for extra visibility on the running utility They are lit up by setting bits BCSRO 5 6 respectively 4 2 2 LD3 USB Power When lit the USB Vbus is powered 4 2 3 LD4 LD5 GETH Enable The green LED LD4 5 indicates enable for GETH Transceivers U5 U6 4 2 4 LD6 DUART Enable A green LED LD6 indicates enable for the RS232 Dual Transceiver 4 2 5 LD7 FUNC Indication A green LED LD7 indicates different board setting modes LD7 blinks when the JTAG controller implemented in Xilinx FPGA is active 4 2 6 LD8 Power GOOD A green LED LD8 indicates that the MPC8349EA MDS Processor Board power is operating normally 4 2 7 LD9 GPIO1 1 Indication A green LED LD9 indicates the state of the MPC8349 GPIO1 1 pin U54 E24 42 8 LD10 LD11 PC
38. ernal Setat clock from the PIB Board when low May be rewritten any time Power On via JTAG LBIU 3 EM FLASH Emulation PSRAM Low enables PSRAM accesses to provide Flash emulation When high PSRAM is disabled Flash may be enabled instead May be rewritten any time via JTAG LBIU 4 FLEN FLASH Enable Low enables Flash accesses When high Flash operation is not available PSRAM part may be enabled instead May be rewritten any time via JTAG LBIU 5 BUFFEN Expansion Buffer Enable Low enables access to the PIB forthe Setup defined PIB combined mode High level sets off the expansion buffer for at the stand alone mode May be rewritten any time via JTAG LBIU Power On BRDWP BRD Write Protect When high the BRD EEPROMs on the MPC8349EA MDS Processor Board are hardware protected for Set at ee write operation Low level allows the content of the BRDs to be updated May be rewritten any time via JTAG LBIU PORESET Power On Reset Toggling low high within 1ms time window will generate a PORESET negative pulse on the MPC8349EA MDS Processor Board May be rewritten any time via JTAG LBIU 5 2 9 BCSR8 Board Misc Register 3 On the board the BCSR8 acts as a control register The BCSR8 which may be read or written at any time receives its defaults immediately after PORESET The BCSR8 fields are described below in Table 5 10 MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 5 9 Table 5 10 BCSR8 Description Offset 8
39. ile the Processor board already installed functions as a master This allows you to take advantage of the parallel processing capabilities of the 83xx line of products Power input for table top configuration Front plane connection optical GETH Power input for working with a back plane A Back plane connection Pr incl GETH and voltage Double RS 232 da connected to RJ45 DUART Ea qo a GETH twisted pair Not relevant for MPC8349EA Figure 2 14 Fully Assembled Combined system PIB Processor Board USB and PCI cards 2 2 3 For Agent Mode only 1 Insert the MPC8349EA MDS Processor Board into a PC using its PCI edge connector 2 Operate Code Warrior to verify that the processor board has been installed properly 3 Connect external cables in accordance with your laboratory environment MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 2 9 4 Verify that LD1 and LD2 turn on and then turn off see Figure 2 3 for location They should be on for only a few moments This indicates that the board has successfully undergone the boot up sequence MPC8349EA MDS Processor Board Rev A 2 10 Freescale Semiconductor Chapter 3 Memory Map 3 1 MPC8349EA MDS Processor Board Mapping The MPC8349EA Memory Controller governs all accesses to the processor memory slaves Consequently the memory map may be reprogrammed according to user needs After performing a Hard Reset
40. nterconnect Phy Physical Layer MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 1 3 PIB Platform I O Board expands the ADS functionality PSRAM Pseudo Static Random Access Memory PSU Power Supply Unit RCWL RCWH Reset Configuration Word Low High RGMII Reduced General Media Independent Interface RTC Real Time Clock SDRAM Synchronous Dynamic Random Access Memory SMB Type of Mini RF connector SODIMM Mini DIMM Form Factor SPD Serial Present Detect TBD To Be Defined TSEC Triple Speed Ethernet Controller ULPI UTMI Low Pin Interface UPM User Programmable Machine USB Universal Serial Bus ZD Zero Delay clock buffer with internal PLL for skew elimination 1 3 Related Documentation MPC8349EA HW Specification e MPC8349EA Reference Manual PowerQUICC MDS Platform I O Board User s Manual e MPC8349EA Hardware Getting Started 1 4 Specifications The MPC8349EA MDS Processor Board specifications are given in Table 1 2 Table 1 2 MPC8349EA MDS Processor Board specifications CHARACTERISTICS SPECIFICATIONS Power requirements Stand Alone Mode 5V 3A external DC power supply PIB Combined Mode Power supplied by PIB Working in PC Power supplied by PC MPC8349EA processor Internal clock runs up to 667MHz 1 2V MPC8349EA MDS Processor Board Rev A 1 4 Freescale Semiconductor Table 1 2 MPC8349EA MDS Processor Board specific
41. ox 5405 Denver Colorado 80217 1 800 521 6274 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for su
42. r FPGA In System Programming P11 Voltage Input P12 P13 300 pin FCI Expansion Connectors J1 J2 RJ45 8pin Gigabit Ethernet Connectors MPC8349EA MDS Processor Board Rev A Freescale Semiconductor P10 16 pin header for FPGA programming TE e P11 Voltage Input SAN sl mad Po sTAGICOP P3 P6 P7 P8 MICTOR x4 Logic Analyzer P5 SMB RF Connector P12 P13 300 pin FCI Expansion Connectors on underside P4 PCI Edge Connector Front Panel P2 RJ45 J1 J2 RJ45 P1 MiniAB USB DUART signals Gigabit Ethernet Figure 1 1 MPC8349EA MDS Processor Board External Connections MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 1 7 1 7 Block Diagram SODIMM DDR SPD SODIMM DDR2 72bit 256MB 400Mhz From Riser Connector 5 5 S F D L R A DDR controller RJ45 o E 9 E o o v 3 ca gt n g o a s amp x a TSECx2 LBIU 1000 100 10 Ethernet phy x ADD Latch MPC8349EA FPGA A see USB2 0 0TG wite MiniAB s CH ULPI Gael ow a ZH s E CCR To Riser 4 p Comnector PP I F nee from PIB Dual 2C2 RS232 a Mode PCI2 32 PCI1 32 PCI1 64 PMC ITAG MG COP PCI2 Host PCI Host via RC L via RC RR EEPROM 256Kb lt RTC Buffer for Voltage Clamp Connector 5V PCI 64 bit PCI Edge Connector A SDRAM and PSRAM an are Note RC Riser Connector fo
43. r PIB connectivity optional Figure 1 2 MPC8349EA MDS Processor Board Block Diagram MPC8349EA MDS Processor Board Rev A 1 8 Freescale Semiconductor Chapter 2 Hardware Preparation and Installation This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC8349EA MDS Processor Board including all three configurations Stand Alone PIB Combined Mode and Agent Mode inserted in a PC For more details on hardware preparation see the Getting Started document for the MPC8349EA MDS Processor Board 2 1 Unpacking Instructions NOTE If the shipping carton is damaged upon receipt request carrier s agent to be present during unpacking and inspection of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE CAN DAMAGE CIRCUITS 1 Unpack equipment from shipping carton 2 Refer to packing list and verify that all items are present 3 Save packing material for storing and reshipping of equipment 2 2 Installation Instructions Do the following in order to install the MPC8349EA MDS Processor Board properly 1 Verify that Jumpers and Swtiches are in default positions For default positions see the Getting Started document for the MPC8349EA MDS Processor Board 2 Determine in which working configuration you will operate the MPC8349EA MDS Processor Board Stand Alone continue from Section 2 2 1 PIB Combined Mode with the PIB
44. rgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 All rights reserved
45. ritten via JTAG LBIU PCI1 Arbiter If working in Agent Mode this bit is set low to provide external arbiter When the MPC8349EA MDS Processor Board is working in the PIB Combined Mode this bit is set high to configure the PCI1 port with an internal arbiter May be rewritten any time via JTAG PCI2 Arbiter If working in the Agent Mode this bit is set low to provide an external arbiter When the MPC8349EA MDS Processor Board is working in the PIB Combined Mode this bit is set high to configure the PCI2 port with an internal arbiter May be rewritten any time via JTAG Core Disable When high the e300 core is prevented from fetching boot code until configuration by an external master is complete If low the core runs normally May be rewritten any time via JTAG Boot Mode When low sets lower 8MByte boot memory space location if used for DDR2 or PCI boot source Otherwise for LBIU boot source the BMS will be high for upper boot memory space location User may change boot source location by reguest May be rewritten any time via JTAG LBIU Local Bus Clock Mode When set high local bus memory controller operates with a freguency egual to twice the freguency of the csb cik If this bit is low the local bus memory controller will operate at the csb cik frequency The DIP switch SW6 7 may change LBIUCM bit setting May be rewritten any time via JTAG LBIU MPC8349EA MDS Processor Board Rev A Defined by operating configuration
46. rovides instructions on replacing various devices on the MPC8349EA MDS Processor Board 7 1 Replacing Flash Memory To remove the flash memory follow the instructions below in Figure 7 1 to Figure 7 4 below in that order Note that the flash memory can be changed no more than 50 times To replace the flash memory follow the instructions in Figure 7 4 to Figure 7 1 in that order then secure the casing as shown in Figure 7 5 Figure 7 1 Flash Memory push to dislodge casing MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 7 1 il Ja Figure 7 2 Flash Memory open casing 1 i yal f pr j E Figure 7 3 Flash Memory remove memory unit MPC8349EA MDS Processor Board Rev A 7 2 Freescale Semiconductor Figure 7 4 Flash Memory unit removed Figure 7 5 Flash Memory replacing unit push in until click is heard 7 1 1 Cleaning Flash Memory If there is some decrease in performance from the flash memory unit the socket may need to be cleaned Do this by dipping a tooth pick dipped in isopropyl alcohol and gently removing any residual debris from the flash memory socket MPC8349EA MDS Processor Board Rev A Freescale Semiconductor 7 3 7 2 Replacing SODIMM units To remove or replace the SODIMM units follow the instructions in Figure 7 6 through Figure 7 9 in that order Figure 7 6 SODIMM Memory Location on underside of board Figure 7 7
47. s 5 3 1 P1 MiniAB USB Connector MiniAB USB connector pinout is shown in Table 5 15 P1 MiniAB USB Connector below This connector is used for connectivity to external devices USB1 1 USB2 0 OTG It is accessible from the front panel of the board see Figure 1 1 for location Table 5 15 P1 MiniAB USB Connector Signal Name Description 5V Pomer for USB Power is generated internally if working in PCI mode or is supplied from a cable in stand alone mode while the USB controller configures the device Differential Positive Data Identification Signal for Host Device Mode Setting PCI mode vs stand alone mode Ground 5 3 2 P2 DUART Port The DUART port connector P2 is implemented with a 90 10 pin RJ45 connector signals of which are described in Table 5 16 Table 5 16 P2 DUART Signals Clear To Send Transmit Data Ready To Send MPC8349EA MDS Processor Board Rev A 5 12 Freescale Semiconductor For connection to regular D Type 9 RS232 cable use special cable from MPC8349EA MDS Processor Board set 5 3 3 Logic Analyzer Connectors P3 P6 P7 and P8 are 38 pin SMT high density matched impedance connectors made by AMP and used for Logic Analyzer measurements They contain all MPC8349EA signals except for the DDR2 signals 5 3 4 P5 SMB Connector RF Subminiature Coaxial Connector P5 is used to connect an external clock to the MPC8349E A which is enabled only when jumper JP1 2 3 is clos
48. s active low The LED is unlit when it is in an inactive default state high During the Reset Configuration seguence the LED indicates the HRESET assertion May be rewritten via JTAG LBIU 5 2 2 BCSR1 Board Control Status Register 1 On the board the BCSR1 acts as a control register The BCSR1 which may be read or written at any time receives its defaults immediately after Power On or PORESET The BCSR1 fields are described below in Table 5 2 Table 5 2 BCSR1 Description Offset 1 MNEMONIC Function Defn CFG CLKIN DIV CLKIN Division The bit reflects CFG CLKIN DIV signal logic SW3 4 level during Power Reset Configuration sequence The bitis set Sampled at by default by appropriate DIP switch SW3 4 May be rewritten Power ON via JTAG LBIU CFG RS 0 2 Reset Configuration Words Source The bits reflect SW3 1 3 CFG _RS 0 2 signals logic level during PON Reset Sampled at Configuration sequence The bits are set by default by Power ON appropriate DIP switch SW3 1 3 May be rewritten via JTAG LBIU 4 6 ROMLOCI0 2 Boot ROM interface location The bits reflect ROMLOC 0 2 SW5 3 5 signals logic level during Reset Configuration sequence The Sampled at bits are set by default by appropriate DIP switch SW6 3 5 May PORESET be rewritten via JTAG LBIU neg 7 FLASHPRT Flash Protect Upon activation low the Flash may be written 1 When high the write protection is set Sampled at PORESET neg 5 2 3 BCSR2 Bo

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