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LPC122x - NXP Semiconductors

1. 16 Memory map 16 Nested Vectored Interrupt Controller NVIC 17 Features 17 Interrupt sources 18 IOCONFIG block 18 Features uu xd UNE node SACRA RR E 18 Micro DMA controller 18 Features 18 CRG engine i cree et sean 19 Features 19 Fast general purpose parallel I O 19 Features 19 WARTS nere amer eR URP 19 Features corri Rb EIL ER 20 SSP SPI serial I O controller 20 FOatureS 22 440020 ey oe Tg 2 20 I C bus serial I O controller 20 Features eci 2408 ar 8 e pes dde him ee 20 10 bit ADC 21 FeatUles lt ZE KTR R RN T un Earl 21 Comparator block n a nananana nann 21 F atUIeS 2 22 244 8 gare canton Sa baad eee 21 General purpose external event counter timers 22 Features 22 Windowed WatchDog timer WWDT 22 Features cec nur num de ne ste 22 Real time clock RTC 23 Features Preeria rendi iiaiai EE Le dant 23 Clocking and power control 23 Crystal oscillators 23 Internal RC oscillator 24 7 18 1 2 System oscillator 24 LPC122X All information provided in this document
2. 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages tcLcx Toy clk 002aaa907 Fig 21 External clock timing with an amplitude of at least Virus 200 mV LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 46 of 61 NXP Semiconductors LPC122x 11 4 LPC122X 32 bit ARM Cortex M0 microcontroller Internal oscillators Table 14 Dynamic characteristic internal oscillators Tamb 40 to 85 C Vpp aya over specified ranges D Symbol Parameter Conditions Min Typ l Max Unit fosc RC internal RC oscillator frequency 11 88 12 12 12 MHz 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at nominal supply voltages 12 15 002aag020 12 MHz 196 fosc RC VDD 3 6 V MHz 8 3 V 3 0V 12 05 11 95 12 MHz 196 11 85 40 15 10 35 60 85 temperature C Fig 22 Internal RC oscillator frequency versus temperature Table 15 Dynamic characteristics Watchdog oscillator Symbol Parameter Conditions Min Typll Max Unit fosc int internal oscillator DIVSEL Ox1F FREQSEL 2 0x1 IS 7 8 E kHz frequency in the WDTOSCCTRL register DIVSEL 0x00 FREQSE
3. 24 MHz S 3 12 Maz S PCR NC S mq ee Dr 4 MHz 1 1 MHz se ss ee EE _ ___ _ 0 3 0 3 2 3 4 3 6 Vpp va V Conditions Vpp ava 3 3 V sleep mode entered from flash all peripherals disabled in the SYSAHBCLKCTRL register SYSAHBCLKCTRL 0x1F all peripheral clocks disabled internal pull up resistors disabled BOD disabled 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled 3 System oscillator enabled with external clock input IRC and system PLL disabled Fig 10 Sleep mode Typical supply current Ipp versus supply voltage Vpp avs for different system clock frequencies 002aag190 50 g IDD pA V 3 6V 40 DD 3V3 30 20 10 40 15 10 35 60 85 temperature C Conditions BOD disabled all oscillators and analog blocks disabled in the PDSLEEPCFG register Fig 11 Deep sleep mode Typical supply current Ipp versus temperature for different supply voltages Vpp 3v3 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 37 of 61 NXP Semiconductors LPC122x LPC122X 10 3 32 bit ARM Cortex M0 microcontroller 1 0 002aag189 IDD pA 0 9 0 8 Vop ava 3 6 V
4. 7 4 ARM Cortex MO processor The ARM Cortex MO is a general purpose 32 bit microprocessor which offers high performance and very low power consumption System tick timer The ARM Cortex MO includes a System Tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a 10 ms interval On chip flash program memory The LPC122x contain up to 128 kB of on chip flash memory On chip SRAM The LPC122x contain a total of up to 8 kB on chip static RAM memory Memory map The LPC122x incorporates several distinct memory regions shown in the following figures Figure 4 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping The AHB peripheral area is 2 megabyte in size and is divided to allow for up to 128 peripherals The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kilobytes of space This allows simplifying the address decoding for each peripheral All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 16 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 8 kB custom ROM Ox1FFE 0000 reserved Ox1FFC 4000 16 kB NXP library ROM Ox1FFC 0000 reserved 0x1000 2000 8kB SRA
5. Table 3 LPC122x pin description continued Symbol 2 Start Type Reset Description HE n logic state O O input D cl 2l B E a PIOO0 27 ACMPO O 12 12 M no lO E PU PIOO 27 General purpose digital input output pin high current output driver O ACMPO O Output for comparator 0 PIOO 28 ACMP1 O 13 17 M no lO 5 PU PIOO 28 General purpose digital input output pin CT16BO CAPO high current output driver CT16BO MATO O ACMP1 O Output for comparator 1 I CT16BO CAPO Capture input channel 0 for 16 bit timer 0 O CT16BO MATO Match output channel 0 for 16 bit timer 0 PIO0_29 ROSC 14 18 BI no lO 5 PU PIOO 29 General purpose digital input output pin CT16BO CAP1 high current output driver CT16B0_MAT1 VO ROSC Relaxation oscillator for 555 timer applications CT16BO CAP1 Capture input channel 1 for 16 bit timer O O CT16B0_MAT1 Match output channel 1 for 16 bit timer 0 R PIO0_30 ADO 34 46 M no PU R Reserved Configure for an alternate function in the SI IOCONFIG block VO PIOO 30 General purpose digital input output pin ADO A D converter input 0 R PIOO 31 AD1 35 47 El no PU R Reserved Configure for an alternate function in the 3 IOCONFIG block VO PIOO 31 General purpose digital input output pin AD1 A D converter input 1 PIO1 0 to PIO1 6 y o Port 1 Port 1 is a 32 bit I O port with individual direction and fu
6. 26 August 2011 6 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller XTALIN XTALOUT VREF_CMP PIOO_19 PIOO_20 PIOO_21 PIOO_22 PIOO_23 PIOO_24 SWDIO PIOO 25 SWCLK PIOO 26 P1O0_27 1 1 High current output driver Fig 3 O1 6 O14 O1 3 WAKEUP O1 2 45 RTCXOUT 44 VpDp sv3 43 Vss 42 P 37 R PIO1 1 48 Vssio 47 VDD IO 46 RTCXIN 40 P 39 P 38 P LPC122x O0_6 21 PIOO_29 1 14 PIOO_28 1 13 P P P P P P P P P P Remark For a full listing of all functions for each pin see Table 3 Pin configuration LQFP48 package R PIO1 0 R PIOO 31 R PIOO 30 PIOO_18 PIOO_17 PIOO_16 PIOO_15 PIOO_14 RESET PIOO_13 PIO0 1211 PIOO 11 PIOO_10 002aaf724 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 7 of 61 NXP Semiconductors LPC122x 6 2 Pin description 32 bit ARM Cortex MO microcontroller All pins except the supply pins can have more than one function as shown in Table 3 The pin function is selected through the pin s IOCON register in the IOCONFIG block The multiplexed functions see Table 4 include the counter timer inputs and outputs the UART receive transmit and control functions and the serial wire debug functions For each pin the default function is listed first to
7. iA YA 1 A IZ aZ m 1 HH H HHH L D2 8x bs E Bx gt lt Ax La Generic footprint pattern Refer to the package outline drawing for actual layout Z solder land Wa occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 13 300 13 300 10 300 10 300 1 500 0 280 0 400 10 500 10 500 13 550 13 550 Fig 28 Reflow soldering of the LQFP64 package sot314 2 fr LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 55 of 61 NXP Semiconductors LPC122x 15 Abbreviations 32 bit ARM Cortex M0 microcontroller LPC122X Table 18 Abbreviations Acronym ADC AHB APB BOD CCITT CRC DMA FIFO GPIO 1 0 IrDA IRC JEDEC PLL SPI SSI SSP UART Description Analog to Digital Converter Advanced High performance Bus Advanced Peripheral Bus BrownOut Detection Comit Consultatif International T l phonique et T l graphique Cyclic Redundancy Check Direct Memory Access First In First Out General Purpose Input Output Input Output Infrared Data Association Internal Resistor Capacitor Joint Electron Devices Engineering Council Phase Locked Loop Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Universal Asynchronous Receiver Transmitter All information provided in this document is subjec
8. 31 no VO E PU PIO2 2 General purpose digital input output pin S CT16B1 CAPO 3 x CT16B1_CAPO Capture input channel 0 for 16 bit timer 1 CT16B1 MATO TXDO O CT16B1_MATO Match output channel 0 for 16 bit timer 1 O TXDO Transmitter output for UARTO PIO2_3 32 2 no VO E PU PIO2 3 General purpose digital input output pin 3 CT16B1_CAP1 ____ 3l CT16B1_CAP1 Capture input channel 1 for 16 bit timer 1 CT16B1_MAT1 DTRO O CT16B1 MAT1 Match output channel 1 for 16 bit timer 1 O DTRO Data Terminal Ready output for UARTO PIO2_4 33 2 no VO E PU PIO2 4 General purpose digital input output pin 3 CT32B0_CAPO ____ B s CT32B0 CAPO Capture input channel 0 for 32 bit timer 0 CT32BO MATO CTSO O CT32B0_MATO Match output channel 0 for 32 bit timer 0 CTSO Clear To Send input for UARTO PIO2_5 34 2 no VO E PU PIO2 5 General purpose digital input output pin 3 CT32B0_CAP1 __ B CT32B0_CAP1 Capture input channel 1 for 32 bit timer 0 CT32B0_MAT1 RI0 O CT32B0_MAT1 Match output channel 1 for 32 bit timer 0 LPC122X All information provided in this document is subject to legal disclaimers RIO Ring Indicator input for UARTO NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 12 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 3 LPC122x pin descriptio
9. mode a minimum of 200 mV RMS is needed LPC1xxx 002aae788 Fig 24 Slave mode operation of the on chip oscillator XTAL Printed Circuit Board PCB layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors C 4 C 2 and Cy3 in case of third overtone crystal usage have a common ground plane The external components must also be connected to the ground plain Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible Also parasitics should stay as small as possible Values of C and Cys should be chosen smaller accordingly to the increase in parasitics of the PCB layout All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 50 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex MO microcontroller 12 3 ElectroMagnetic Compatibility EMC Radiated emission measurements according to the IEC61967 2 standard using the TEM cell method are shown for the LPC1227FBD64 301 in Table 17 LPC122X Table 17 ElectroMagnetic Compatibility EMC for part LPC1227FBD64 301 TEM cell method Vpp 3 3 V Tamb 25 C Parameter Frequency band System clock Unit 12 MHz 24 MHz 33 MHz Input clock IRC 12 MHz maximum 150 kHz 30 MHz 4 2 8 8
10. 0 CT32B0 0 08 0 08 0 04 0 04 32 bit timer 1 CT32B1 0 08 0 08 0 04 0 04 GPIOO s 0 34 0 34 0 17 0 17 GPIO1 0 34 0 34 0 17 0 17 GPIO2 0 36 0 37 0 18 0 18 12C gt 0 09 0 09 0 05 0 05 IOCON 0 09 0 10 0 05 0 05 RTC 0 10 0 10 0 05 0 05 SSP E 0 30 0 29 0 15 0 15 UARTO 0 52 0 51 0 26 0 26 UART1 0 52 0 51 0 26 0 26 DMA 0 18 0 18 0 09 0 09 WWDT 0 06 0 06 0 03 0 03 10 2 Power consumption Power measurements in Active Sleep and Deep sleep modes were performed under the following conditions see LPC 122x user manual Active mode all GPIO pins set to input with external pull up resistors Sleep and Deep sleep modes all GPIO pins set to output driving LOW Deep power down mode all GPIO pins set to input with external pull up resistors LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 34 of 61 NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller 16 002aag 186 IDD mA us 33 MHz EE NC sn 12 24 MHz 8 12 Maz NN T m 4 4 MHz 1 MHz 0 3 3 2 34 3 6 Vpp ava V Conditions Tamb 25 C active mode entered executing code while 1 from flash all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled internal pull up resistors disabled BOD disabled System
11. 2 for 32 bit timer 1 O TXD1 Transmitter output for UART1 PIO2_11 62 B no lO 1 PU PIO2 11 General purpose digital input output pin CT32B1_CAP3 8 T T32B1_CAP3 h 3 for 32 1 CT32B1 MAT3 RXD1 CT32B1 CAP3 Capture input channel 3 for 32 bit timer O CT32B1_MAT3 Match output channel 3 for 32 bit timer 1 RXD1 Receiver input for UART1 PIO2 12 RXD1 13 2 no VO EL PU PIO2 12 General purpose digital input output pin 3 Pu S RXD1 Receiver input for UART1 PIO2_13 TXD1 14 2 no lO E PU PIO2 13 General purpose digital input output pin E O s TXD1 Transmitter output for UART1 PIO2 14 15 B no lO E PU PIO2 14 General purpose digital input output pin 3 PIO2 15 16 B no lO E PU PIO2_15 General purpose digital input output pin 3 RTCXIN 46 58 0 Input to the 32 kHz oscillator circuit RTCXOUT 45 57 M O Output from the 32 kHz oscillator amplifier XTALIN 1 1 Input to the system oscillator circuit and internal clock generator circuits XTALOUT 2 2 S O Output from the system oscillator amplifier VREF CMP 8 8 l S Reference voltage for comparator LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 13 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 3 LPC122x pin description co
12. CT32BO0O MATO PIOO 1 PIOO 18 PIO2 4 CT32BO MATT O PIOO 2 PIOO 19 PIO2 5 CT32B0 MATS PIOO 3 PIOO 20 PIO2 6 CT32B0 MATS PIOO 4 PIOO 21 PIO2 7 CT32B1 CT32B1 CAPO l PIOO 6 PIOO 23 PIO2 8 CT32B1 CAP1 PIOO 7 PIOO 24 PIO2 9 CT32B1 CAP2 PIOO 8 PIOO 25 PIO2 10 CT32B1 CAP3 l PIOO 9 PIOO 26 PIO2 11 CT32B1 MATO PIOO 6 PIOO_ 23 PIO2 8 CT32B1 MATT O PIOO 7 PIOO 24 PIO2 9 CT32B1 MATS PIOO 8 PIOO 25 PIO2 10 CT32B1 MATS PIOO 9 PIOO 26 PIO2 11 UARTO RXDO PIOO 1 PIO2 1 TXDO O PIOO 2 PIO2 2 CTSO PIOO 7 PIO2 4 z DCDO PIOO 5 PIO2 6 DSRO l PIOO 4 PIO2 7 DTRO O PIOO 3 PIO2 3 RIO PIOO 6 PIO2 5 RTSO O PIOO 0 PIO2 0 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 15 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 4 Pin multiplexing Peripheral Function Type Available on ports UART1 RXD1 PIOO 8 PIO2 11 PIO2 12 TXD1 O PIOO 9 PIO2 10 PIO2 13 SSP SPI SCK UO PIOO 14 MISO UO PIOO 16 MOSI UO PIOO 17 SSEL UO PIOO 15 12C SCL UO PIOO 10 SDA UO PIOO 11 2 S SWD SWCLID PIOO_ 18 PlO0 26 SWDIOI y o PIOO 25 PIO1 2 Reset RESET PIOO0 13 Clockout pin CLKOUT O PIOO 12 1 After reset the SWD functions are selected by default on pins PIOO 26 and PIOO 25 7 Functional description LPC122X 7 1 7 2 7 3
13. UO latch up current 0 5Vpp lt Vi lt 1 5Vpp Tj 125 C Tstg storage temperature Piot pack total power dissipation per package based on package heat transfer not device power consumption Vesp electrostatic discharge voltage human body model all pins ei ei 5 Min 3 0 3 0 0 5 8000 Max 3 6 3 6 3 6 5 5 100 100 100 150 1 5 8000 Unit lt lt lt mA mA C V 1 2 3 4 5 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted Including voltage on outputs in 3 state mode The peak current is limited to 25 times the corresponding maximum current Dependent on package type Human body model equivalent to discharging a 100 pF capacitor through a 1 5 kO series resistor LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 29 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 9 Thermal chara
14. a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 17 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to t
15. clearing any number of outputs simultaneously The value of the output register may be read back as well as the current state of the port pins Features Bitlevel set and clear registers allow a single instruction to set or clear any number of bits in one port Direction control of individual bits All I O default to inputs after reset UARTs The LPC122x contains two UARTs UARTO supports full modem control and RS 485 9 bit mode and allows both software address detection and automatic hardware address detection using 9 bit mode The UARTS include a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 19 of 61 NXP Semiconductors LPC122x 7 10 1 7 11 7 11 1 7 12 7 12 1 LPC122X 32 bit ARM Cortex M0 microcontroller Features 16 byte Receive and Transmit FIFOs Register locations conform to 16C550 industry standard e Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit mode UARTO e Support for modem
16. control UARTO SSP SPI serial I O controller The LPC122x contain one SSP SPI controller The SSP SPI controller is capable of operation on a SSP 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SSP supports full duplex transfers with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses Synchronous serial communication Master or slave operation s 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame I C bus serial UO controller The LPC122x contain one I C bus controller The I C bus is bidirectional for inter IC control using only two wires a serial clock line SCL and a serial data line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C is a multi master bus and can be controlled by more than one bus master connected
17. data sheet Rev 2 26 August 2011 18 of 61 NXP Semiconductors LPC122x 7 8 7 8 1 7 9 7 9 1 7 10 LPC122X 32 bit ARM Cortex M0 microcontroller Supports memory to memory memory to peripheral and peripheral to memory transfers Supports multiple DMA cycle types and multiple DMA transfer widths Performs all DMA transfers using the single AHB Lite burst type CRC engine The Cyclic Redundancy Check CRC engine with programmable polynomial settings supports several CRC standards commonly used To save system power and bus bandwidth the CRC engine supports DMA transfers Features Supports three common polynomials CRC CCITT CRC 16 and CRC 32 CRC CCITT x16 x12 x54 1 CRC 16 x16 4 x15 x2 4 1 CRC 32 x32 x26 x23 x22 x16 x12 x11 4 x10 4 x84 x7 4 x9 x44 x2 ex 1 Bit order reverse and 1 s complement programmable setting for input data and CRC sum Programmable seed number setting e Supports CPU programmed I O or DMA back to back transfer Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle operation 8 bit x 2 cycle 32 bit write 4 cycle operation 8 bit x 4 cycle Fast general purpose parallel UO Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Separate registers allow setting or
18. input A LOW on this pin resets the 3 device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 VO PIOO 13 General purpose digital input output pin PIOO 14 SCK 29 41 Bl no VO E PU PIOO 14 General purpose digital input output pin 5 Bl lO SCKC Serial clock for SSP SPI PIOO 15 SSEL 30 42 PI no lO E PU PIOO 15 General purpose digital input output pin 3 CT16B1 CAPO Bl lO SSEL Slave select for SSP SPI CT16B1 MATO l CT16B1 CAPO Capture input channel 0 for 16 bit timer 1 O CT16B1_MATO Match output channel 0 for 16 bit timer 1 PIOO 16 MISO 31 43 Bl no VO E PU PIOO 16 General purpose digital input output pin 3 CT16B1_CAP1 B lO MISO Master In Slave Out for SSP SPI CT16B1 MAT1 CT16B1 CAP1 Capture input channel 1 for 16 bit timer 1 O CT16B1_MAT1 Match output channel 1 for 16 bit timer 1 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 9 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 3 LPC122x pin description continued Symbol 2 Start Type Reset Description f Tu logic state G O input DI cl 2 B E oa PIOO 17 MOSI 32 44 PI no VO E PU PIOO 17 General purpose digital input output pin 3 Bl lO MOSI Master Out Slave In fo
19. oscillator and system PLL disabled IRC enabled System oscillator and system PLL enabled IRC disabled 3 System oscillator enabled IRC and system PLL disabled Fig 6 Active mode Typical supply current lpp versus supply voltage Vpp ava for different system clock frequencies all peripherals disabled T 002aag023 IDD mA 33 MHz 12 24 MHz 8 12 MHz 1 4 4 MHz 1 MHz 3 0 40 15 10 35 60 85 temperature C Conditions Vpp ava 3 3 V active mode entered executing code while 1 from flash all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled internal pull up resistors disabled BOD disabled 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled 3 System oscillator enabled IRC and system PLL disabled Fig 7 Active mode Typical supply current Ipp versus temperature for different system clock frequencies peripherals disabled All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 35 of 61 NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller 002aag187 33 MHz L NHS 8 12 Maz Nn 4 MHz j 1 MHz 2 Vopp 3v3 V Conditions Tamb 25 C active mode entered
20. outline SOT314 2 LQFP64 LPC122X All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 26 August 2011 NXP B V 2011 All rights reserved 52 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 detail X DIMENSIONS mm are the original dimensions UNIT Ai A2 Ag bp C 0 25 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT313 2 136E05 MS 026 E 03 02 25 ISSUE DATE Fig 26 Package outline SOT313 2 LQFP48 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 53 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 14 Soldering Footprint information for reflow soldering of LQFP48
21. the requirement tsu par 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line lamasi tsu pAr 1000 250 1250 ns according to the Standard mode I C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 48 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller SDA SCL 002aaf425 Fig 23 12C bus pins clock timing LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 49 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 12 Application information 12 1 12 2 LPC122X XTAL input The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with Cj 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cg which attenuates the input voltage by a factor C C Cg In slave
22. 0 19 23 21 yes I O I PU PIO0_4 General purpose digital input output pin CT32B0_CAP3 SI Rep DSRO D R for UARTO CT32B0 MATS SRO ata Set Ready input for U 0 CT32B0 CAP3 Capture input channel 3 for 32 bit timer 0 O CT32B0_MAT3 Match output channel 3 for 32 bit timer 0 PIOO_5 DCDO 20 24 ll yes WO I PU PIOO 5 General purpose digital input output pin E 3 l DCDO Data Carrier Detect input for UARTO PIO0_6 RI0 21 25 2 yes IO I PU PIOO 6 General purpose digital input output pin CT32B1_CAPO 3 Sin S RIO Ring for UARTO CT32B1_MATO 0 ing Indicator input for U 0 CT32B1 CAPO Capture input channel 0 for 32 bit timer 1 O CT32B1 MATO Match output channel 0 for 32 bit timer 1 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 8 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 3 LPC122x pin description continued Symbol 2 Start Type Reset Description n a logic state O O input D S E E oa PIOO 7 CTSO 22 26 2 yes IO 1 PU PIOO 7 General purpose digital input output pin CT32B1 CAP1 3 an TSO Clear T for UARTO CT32B1 MAT CTSO Clear To Send input for U 0 CT32B1 CAP1 Capture input channel 1 for 32 bit timer 1 O 2 CT32B1 MAT Match output chann
23. 011 Document identifier LPC122X
24. 1 Condition 0 lt V x 400 mV at start of power up t t1 Fig 20 Power up ramp All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 45 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 11 2 Flash memory Table 12 Dynamic characteristic flash memory Tamb 40 C to 85 C Vpp ava over specified ranges Symbol Parameter Conditions Min Max Unit ter erase time for one page 512 byte n 20 ms for one sector 4 kB iui 162 ms for all sectors mass n 20 ms erase tprog programming one word 4 bytes n 49 us time four sequential words p 194 us 128 bytes one row of 32 m 765 us words Nendu endurance 2 20000 cycles tret retention time 10 years 1 Erase and programming times are valid over the lifetime of the device minimum 20000 cycles 2 Number of program erase cycles 11 3 External clock Table 13 Dynamic characteristic external clock Tamb 40 C to 85 C Vpp ava over specified ranges D Symbol Parameter Conditions Min Typ Max Unit fosc oscillator frequency 1 25 MHz Tey cik clock cycle time 40 1000 ns tcHcx clock HIGH time Tog x 0 4 ns tcLox clock LOW time Tog x 0 4 ns toLcH clock rise time ns tcucL clock fall time ns 1 Parameters are valid over operating temperature range unless otherwise specified
25. 122x block diagram LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 5 of 61 NXP Semiconductors LPC122x 6 Pinning information 32 bit ARM Cortex M0 microcontroller 6 1 Pinni ng XTALIN XTALOUT VREF_CMP PIOO 19 PIOO 20 PIOO 21 PIOO 22 PIOO 23 PIOO 24 SWDIO PIOO 25 SWCLK PIOO 26 PIOO_27 1 PIO2_12 PIO2_13 PIO2_14 PIO2_15 1 Fig 2 o o e gt E 63 Vpp o 62 PIO2 11 61 PIO2 10 60 PIO2 9 59 PIO2 8 58 RTCXIN 57 RTCXOOUT 56 Vpp 3v3 55 Vss 54 PIO1 6 53 PIO1 5 LPC122x 52 PIO1 4 51 PIO1 3 WAKEUP 50 PIO1 2 49 R PIO1 1 PIOO 28 1 17 High current output driver PIOO 29 1 18 PIOO 1 20 PIOO 2 21 PIO0 3 22 PIOO 4 23 PIOO 5 24 PIOO 6 25 PIOO 7 26 PIOO 8 27 PIOO 9 28 PIOO 0 19 Remark For a full listing of all functions for each pin see Table 3 Pin configuration LQFP64 package PIO2 0 29 PIO2 1 30 PIO2 2 31 PIO2 3 32 002aaf554 R PIO1 0 R PIOO 31 R PIOO 30 PIOO 18 PIOO 17 PIOO 16 PIOO 15 PIOO 14 RESET PIOO 13 PIOO_12 1 PIOO_11 PIOO 10 PIO2 7 PIO2 6 PIO2 5 PIO2 4 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2
26. 3 3 V 3 0 7 different supply voltages Vpp 3v3 60 85 temperature C Fig 12 Deep power down mode Typical supply current lpp versus temperature for Electrical pin characteristics 2aag17 3 6 002aag175 VoH V 3 2 low mode 40 C 2 8 low mode 25 C 40 C 70 C 25 C 85 C 70 C _4 85 C 24 2 0 16 32 48 Conditions Vpp o 3 3 V Fig 13 High drive pins Typical HIGH level output voltage Voy versus HIGH level output current lon loH mA All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller 1 2 VoL V 0 8 0 4 002aag310 high mode 40 C i low mode E 40 C 85 C 25 C 70 C 85 C 16 32 48 lot mA Conditions Vpp o 8 3 V Fig 14 High drive pins Typical LOW level output voltage Voi versus LOW level output current Io 0 8 002aag180 Conditions Vpp o 3 3 V Fig 15 I C bus pins high current sink Typical LOW level output voltage Vo versus LOW level output current Io lou mA All infor
27. 6 4 dBuV peak level 30 MHz 150 MHz 7 3 5 4 9 dBuV 150 MHz 1 GHz 16 4 20 1 23 4 dBuV IEC level M L L Input clock crystal oscillator 12 MHz maximum 150 kHz 30 MHz 4 8 4 6 6 dBuV peak level 30 MHz 150 MHz 6 9 5 6 10 dBuV 150 MHZ 1 GHz 16 3 20 3 22 3 dBuV IEC level M L L 1 IEC levels refer to Appendix D in the IEC61967 2 Specification All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 51 of 61 NXP Semiconductors LPC122x 13 Package outline 32 bit ARM Cortex M0 microcontroller LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4mm DIMENSIONS mm are the original dimensions SOT314 2 detail X A UNIT P Ai A2 A3 bp c 1 S 0 05 1 45 1 35 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE SOT314 2 136E10 MS 026 Edge 60 61 49 03 02 25 Fig 25 Package
28. 8 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC1226FBD48 301 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC1225FBD48 321 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC1225FBD48 301 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC1224FBD48 121 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC1224FBD48 101 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 3 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 4 1 Ordering options Table 2 Ordering options for LPC122x Type number Flash Total UART I2C SSP ADC GPIO Package SRAM FM SPI channels LPC1227 LPC1227FBD64 301 128kB 8kB 2 1 1 8 55 LQFP64 LPC1227FBD48 301 128kB 8kB 2 1 1 8 39 LQFP48 LPC1226 LPC1226FBD64 301 96kB 8kB 2 1 1 8 55 LQFP64 LPC1226FBD48 301 96kB 8kB 2 1 1 8 39 LQFP48 LPC1225 LPC1225FBD64 321 80kB 8kB 2 1 1 8 55 LQFP64 LPC1225FBD64 301 64kB 8kB 2 1 1 8 55 LQFP64 LPC1225FBD48 321 80kB 8kB 2 1 1 8 39 LQFP48 LPC1225FBD48 301 64kB 8kB 2 1 1 8 39 LQFP48 LPC1224 LPC1224FBD64 121 48kB 4kB 2 1 1
29. 8 55 LQFP64 LPC1224FBD64 101 32kB 4kB 2 1 1 8 55 LQFP64 LPC1224FBD48 121 48kB 4kB 2 1 1 8 39 LQFP48 LPC1224FBD48 101 32kB 4kB 2 1 1 8 39 LQFP48 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 4 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 5 Block diagram XTALIN XTALOUT SWD RESET LPC122x IRC OSCILLATORS CLOCK GENERATION BOD POWER CONTROL CLKOUT SYSTEM TEST DEBUG FUNCTIONS INTERFACE clocks and controls ARM CORTEX M0 MICRO DMA S 4 8 kB CONTROLLER FLASH SRAM system bus master slave slave slave AHB LITE BUS i slave TT slave Q slave RC GINE GPIO ports G AHB APB C BRIDGE EN Pau SCK SSEL MES SSP SPI C gt 10 bit ADC AD 7 0 MOSI eo renee o TXDO r UARTO RS 485 C COMPARATORO 1 ACMPO O DTRO DSRO CTSO xcmpro DCDO RIO RTSO VREF CMP RXD1 TXD1 UNS gt C gt WINDOWED WDT SCL SDA 2c C9 z IOCONFIG RTCXOUT 4 x MAT RTC 32 kHz OSCILLATOR 32 bit COUNTER TIMERO C gt RTCXIN 4 x CAP 4 MAT 32 bit COUNTER TIMER 1 lt C gt SYSTEM CONTROL 4 x CAP 7 Ral 16 bit COUNTER TIMERO C 7 LH MICRO DMA REGISTERS x 2 x MAT x 16 bit COUNTER TIMER 1 C 2x CAP M Grey shaded blocks represent peripherals with connection to the micro DMA controller 002aaf269 Fig 1 LPC
30. A 45 mA 50 mA 100 HA 100 nA 100 nA 100 nA Vppuo V Vppiio V V V V V 0 4 V 0 4 V NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 32 of 61 NXP Semiconductors LPC122x Table 7 Tamb 40 C to 85 C unless otherwise specified Static characteristics continued 32 bit ARM Cortex M0 microcontroller Symbol loH loL lois lou Parameter HIGH level output current LOW level output current LOW level short circuit output current pull up current I C bus pins PIOO_10 and PIOO 11 Vin Vi Vhys VoL lu Ci Oscillator pins Vi xtal Vo xtal HIGH level input voltage LOW level input voltage hysteresis voltage LOW level output voltage input leakage current capacitance for each UO pin crystal input voltage crystal output voltage Conditions low mode Vou Vpp o 0 7 high mode Vou Vpp o 0 7 Vor 0 4 V low mode high mode Vor Vpop Vj 0V lois 20 mA Vi Vpp o Vi 5V on pins PIOO 10 and PIOO 11 see Section 12 1 Min 20 28 12 0 0 Typi o 05Vppuo 1 8 1 8 Max Unit mA mA mA mA mA 100 uA V 0 3Vppq V O V 0 4 V 4 HA 22 uA 8 pF 1 95 V 1 95 V 1 2 3 4 5 6 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages Includin
31. Burst conversion mode for single or multiple inputs Optional conversion on transition of input pin or counter timer match signal Individual result registers for each ADC channel to reduce interrupt overhead 7 14 Comparator block The comparator block consists of two analog comparators 7 14 1 Features LPC122X Up to six selectable external sources per comparator fully configurable on either positive or negative comparator input channels BOD 0 9 V internal reference voltage selectable on both comparators configurable on either positive or negative comparator input channels 32 stage voltage ladder internal reference voltage selectable on both comparators configurable on either positive or negative comparator input channels Voltage ladder source voltage is selectable from an external pin or an internal 3 3 V voltage rail if external power source is not available Voltage ladder can be separately powered down for applications only requiring the comparator function Relaxation oscillator circuitry output for a feedback 555 style timer application Common interrupt connected to NVIC Comparator outputs selectable as synchronous or asynchronous All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 21 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Comparator outputs connect to two timer
32. Dynamic characteristics 45 Power up ramp conditions 45 Flash memory 45 External clock 46 Internal oscillators 47 I G DUS c or ub eod beer vars Dee Pers 47 Application information 50 XTAL InpUt sas mme nes dentiste 50 XTAL Printed Circuit Board PCB layout guidelines 50 ElectroMagnetic Compatibility EMC 51 Package outline 52 Soldering 5 4 iecore meme mets 54 Abbreviations 56 Revision history 57 Legal information 58 Data sheet status 58 Definitions 58 Disclaimers 22444448 sexes ape a 58 continued gt gt NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 60 of 61 NXP Semiconductors LPC122x 17 4 18 19 Trademarks 2 22 tbe RS Contact information Contents 32 bit ARM Cortex M0 microcontroller Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2011 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 26 August 2
33. L OxF AB 1700 kHz in the WDTOSCCTRL register 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 The typical frequency spread over processing and temperature Tamb 40 C to 85 C is 40 3 See the LPC122x user manual All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 47 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 11 5 I C bus Table 16 Dynamic characteristic I2C bus pins Tamb 40 C to 85 CL Symbol Parameter Conditions Min Max Unit fscL SCL clock frequency Standard mode 0 100 kHz Fast mode 0 400 kHz Fast mode Plus 0 1 MHz ty fall time BIALI of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1 x Og 300 ns Fast mode Plus 120 ns tLow LOW period of the SCL clock Standard mode 4 7 US Fast mode 1 3 US Fast mode Plus 0 5 US tHIGH HIGH period of the SCL clock Standard mode 4 0 us Fast mode 0 6 us Fast mode Plus 0 26 us tHD DAT data hold time 2 37 Standard mode 0 us Fast mode 0 S US Fast mode Plus 0 US tsu DAT data set up time ISIS Standard mode 250 ns Fast mode 100 ns Fast mode Plus 50 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 tHD DAT is the data hold time that is measured from the fal
34. LPC122x RIZ BUS 32 bit ARM Cortex MO microcontroller up to 128 kB flash and 8 kB SRAM Rev 2 26 August 2011 Product data sheet 1 General description The LPC122x extend NXP s 32 bit ARM microcontroller continuum and target a wide range of industrial applications in the areas of factory and home automation Benefitting from the ARM Cortex MO Thumb instruction set the LPC122x have up to 50 higher code density compared to common 8 16 bit microcontroller performing typical tasks The LPC122x also feature an optimized ROM based divide library for Cortex MO which offers several times the arithmetic performance of software based libraries as well as highly deterministic cycle time combined with reduced flash code size The ARM Cortex MO efficiency also helps the LPC122x achieve lower average power for similar applications The LPC122x operate at CPU frequencies of up to 45 MHz They offer a wide range of flash memory options from 32 kB to 128 kB The small 512 byte page erase of the flash memory brings multiple design benefits such as finer EEPROM emulation boot load support from any serial interface and ease of in field programming with reduced on chip RAM buffer requirements The peripheral complement of the LPC122x includes a 10 bit ADC two comparators with output feedback loop two UARTs one SSP SPI interface one I2C bus interface with Fast mode Plus features a Windowed Watchdog Timer a DMA con
35. M LPC1225 6 7 4kB SRAM LPC1224 0x1000 1000 0x1000 0000 reserved S 0x0002 0000 0x0001 8000 0x0001 4000 0x0001 0000 128 kB on chip flash LPC1227 301 96 kB on chip flash LPC1226 301 80 kB on chip flash LPC1225 321 64 kB on chip flash LPC1225 301 GL E comparator 0 1 0x4005 4000 LPC122x 4 GB ODO OxFFFF FFFF ES reserved ENS 0xE010 0000 rivate peripheral bus p ERE 0xE000 0000 reserved is 0x5008 0000 F IW AHB peripherals 0x5000 0000 reserved 0x4008 0000 1GB APB peripherals 0x4000 0000 reserved 0x1FFF 2000 8 kB boot ROM 0x1FFF 0000 reserved 0x1FFE 2000 AHB peripherals 0x5008 0000 li ERE 0x5007 0000 3 6 reserved 0x5003 0000 21 GPIO PIO2 Md 1i oer 0x5001 0000 0 GPIO PIOO 0x5000 0000 APB peripherals 0x4008 0000 22 31 reserved 0x4005 8000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 9 18 reserved 0x4002 4000 0x4002 0000 0x4001 C000 32 bit counter timer 0 0x4001 8000 32 bit counter timer 1 16 bit counter timer 1 0x4001 4000 16 bit counter timer 0 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 0x0000 00CO 0x0000 C000 48 kB on chip flash LPC1224 121 0x0000 8000 T 32 kB on chip flash LPC1224 101 0x0000 0000 Fig 4 LPC122x memory map active interrupt vectors 0x0000 0000 002aaf270 7 5 Nested Vectored Interrupt Controller NVIC The Nested Vectored Inte
36. age 3 3 V IDD supply current Conditions Min on pin Vpp o 3 0 3 0 Active mode Vpp ava 3 3 V Tamb 25 C code while 1 executed from flash all peripherals disabled CCLK 12 MHz CCLK 24 MHz CCLK 33 MHz all peripherals enabled CCLK 12 MHz CCLK 24 MHz CCLK 33 MHz Sleep mode Vpp ava 3 3 V Tamb 25 C all peripherals disabled CCLK 12 MHz CCLK 24 MHz CCLK 33 MHz Deep sleep mode Vpp ava 3 3 V Tamb 25 C Deep power down mode Vpp ava 3 3 V Tamb 25 C Normal drive output pins Standard port pins RESET liL LOW level input current liu HIGH level input current loz OFF state output current Vi input voltage Vo output voltage Vin HIGH level input voltage LPC122X Vi lt 0 V Vi Vop o Vo 0 V Vo Vpp oy 3 pin configured to provide a LISA 0 digital function output active 0 0 7Vpp o All information provided in this document is subject to legal disclaimers Typ 3 3 3 3 4 6 12 2 6 6 10 9 14 1 1 8 3 3 4 4 30 720 Max Unit 3 6 V 3 6 V mA mA v uA 100 nA 100 nA 100 nA Vppuo V Vooo V NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 31 of 61 NXP Semiconductors LPC122x Table 7 32 bit ARM Cortex M0 microcontroller Static characteristics continued Tamb 40 C to 85 C unless otherwise spe
37. and Deep sleep modes via the RTC Brownout detect with three separate thresholds each for interrupt and forced reset Power On Reset POR Integrated PMU Power Management Unit Unique device serial number for identification 3 3 V power supply Available as 64 pin and 48 pin LQFP package All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 2 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 3 Applications eMetering Lighting Industrial networking Alarm systems White goods 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC1227FBD64 301 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC1226FBD64 301 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC1225FBD64 321 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC1225FBD64 301 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC1224FBD64 121 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC1224FBD64 101 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC1227FBD48 301 LQFP48 LQFP4
38. ator The system oscillator can be used as the clock source for the CPU with or without using the PLL LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 24 of 61 NXP Semiconductors LPC122x 7 18 1 3 7 18 2 7 18 3 7 18 4 7 18 5 7 18 5 1 LPC122X 32 bit ARM Cortex M0 microcontroller The system oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL The ARM processor clock frequency is referred to as CCLK elsewhere in this document Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU the watchdog timer or the CLKOUT pin The watchdog oscillator nominal frequency is programmable between 7 8 kHz and 1 7 MHz The frequency spread over processing and temperature is 40 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set to di
39. cified Symbol Vi Vhys VoH VoL loH loL loHs lots lou Parameter LOW level input voltage hysteresis voltage HIGH level output voltage LOW level output voltage HIGH level output current LOW level output current HIGH level short circuit output current LOW level short circuit output current pull up current High drive output pins PIOO 27 PIOO 28 PIOO 29 PIOO 12 liL LH loz Vi LPC122X LOW level input current HIGH level input current OFF state output current input voltage output voltage HIGH level input voltage LOW level input voltage hysteresis voltage HIGH level output voltage LOW level output voltage Conditions Min low mode lon 2 mA Vpb o 0 4 high mode lop 4 mA Vpp o 0 4 low mode loj 2 mA high mode lo 4 mA low mode Vou Vpp o 2 0 4 V high mode Vou Vpp oy 4 0 4 V low mode Vo 0 4 V 2 high mode VoL 0 4 V Vou 0V El 7 VOL VppA El Vi 0V 50 Vis0V B Vi Voo o Vo 0 V Vo Vppiio S pin configured to provide a 2l 0 digital function Bl output active 0 0 7Vpp o low mode lou 20 mA Vpp o 0 7 high mode lou 28 mA Vpb o 0 7 low mode lo 12 mA S high mode lo 18 mA All information provided in this document is subject to legal disclaimers Typi 0 4 Max Unit 0 3Vpp V O V V V 0 4 V 0 4 mA mA mA m
40. cteristics 9 1 Thermal characteristics The average chip junction temperature T C can be calculated using the following equation T Tamo Pp x Ring 4 1 e Tamb ambient temperature C Rina the package junction to ambient thermal resistance C W e Pp lt sum of internal and I O power dissipation The internal power dissipation is the product of Ipp and Vpp The I O power dissipation of the I O pins is often small and many times can be negligible However it can be significant in some applications Table6 Thermal characteristics Vpp 3 0 V to 3 6 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Rih j a thermal resistance from JEDEC test board no junction to ambient air flow LQFP64 package 61 C W LQFP48 package 86 C W Rih j c thermal resistance from JEDEC test board S junction to case LQFP64 package 19 s C W LQFP48 package 36 C W Tjmax maximum junction 150 C temperature LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 30 of 61 NXP Semiconductors LPC122x 10 Static characteristics 32 bit ARM Cortex M0 microcontroller Table 7 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Vpp 0 input output supply voltage Vpp av3 supply volt
41. ded for shutting down the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider which provides even better power control Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the clock to the ARM core All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 25 of 61 NXP Semiconductors LPC122x 7 18 5 2 7 18 5 3 7 19 7 19 1 7 19 2 LPC122X 32 bit ARM Cortex M0 microcontroller In Sleep mode execution of instructions is suspended until either a reset or interrupt occurs Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses Deep sleep mode In Deep sleep mode the chip is in Sleep mode and in addition all analog blocks are shut down As an exception the user has the option to keep the watchdog oscillator and the BOD circuit running for self timed wake up and BOD protection Deep sleep mode allows for additional power savings The GPIO p
42. el 1 for 32 bit timer 1 PIOO 8 RXD1 23 27 2 yes IO I PU PIOO 8 General purpose digital input output pin CT32B1 CAP2 8 EU RXD1 R for UART1 CT32B1 MAT2 eceiver input for U CT32B1 CAP2 Capture input channel 2 for 32 bit timer 1 O CT32B1_MAT2 Match output channel 2 for 32 bit timer 1 PIOO 9 TXD1 24 28 1 yes UO I PU PIOO 9 General purpose digital input output pin CT32B1 CAP3 3 TXD1 T for UART1 CT32B1 MAT3 O ransmitter output for U CT32B1_CAP3 Capture input channel 3 for 32 bit timer 1 O CT32B1_MAT3 Match output channel 3 for 32 bit timer 1 PIOO 10 SCL 25 37 A yes IO LIA PIOO 10 General purpose digital input output pin VO SCL 12C bus clock input output PIOO 11 SDA 26 38 4 yes IO LIA PIOO 11 General purpose digital input output pin CT16B0_CAP0 DA I2C CT16B0 MATO O S C bus data input output CT16BO CAPO Capture input channel 0 for 16 bit timer 0 O CT16BO MATO Match output channel 0 for 16 bit timer 0 PIOO 12 CLKOUT 27 39 A no VO 5 PU PIOO 12 General purpose digital input output pin A LOW CT16BO CAP1 level on this pin during reset starts the ISP command handler CT16BO MAT1 High current output driver O CLKOUT Clock out pin CT16BO CAP1 Capture input channel 1 for 16 bit timer 0 O CT16BO MAT1 Match output channel 1 for 16 bit timer 0 RESET PIOO 13 28 40 Dl no PU RESET External reset
43. et Description B m logic state G O input DI cl E E oa PIO1 5 AD7 41 53 1 no VO E PU PIO1 5 General purpose digital input output pin CT16B1 CAPO 3 AD7 A D 7 CT16B1 MATO D converter input CT16B1 CAPO Capture input channel 0 for 16 bit timer 1 O CT16B1 MATO Match output channel 0 for 16 bit timer 1 PIO1 6 42 54 BI no VO E PU PIO1 6 General purpose digital input output pin 3 ee eta MATE 3l CT16B1 CAP1 Capture input channel 1 for 16 bit timer 1 O CT16B1_MAT1 Match output channel 1 for 16 bit timer 1 PIO2_0 to PIO2_15 UO Port 2 Port 2 is a 32 bit I O port with individual direction and function controls for each bit The operation of port 2 pins depends on the function selected through the IOCONFIG register block Pins PIO2 16 through PIO2 31 are not available PIO2 0 29 HB no VO E PU PIO2 0 General purpose digital input output pin CT16B0_CAP0 8 Tm T16BO CAPO h 10 for 16 CT16B0_MATO CT16BO CAPO Capture input channel 0 for 16 bit timer 0 RTSO O S CT16B0_MATO Match output channel 0 for 16 bit timer 0 O RTSO Request To Send output for UARTO PIO2_1 30 2 no VO E PU PIO2 1 General purpose digital input output pin 3 CT16B0 CAP1 B CT16B0 CAP1 Capture input channel 1 for 16 bit timer 0 CT16BO MAT1 RXDO O CT16B0_MAT1 Match output channel 1 for 16 bit timer 0 RXDO Receiver input for UARTO PIO2_2
44. executing code while 1 from flash all peripherals enabled in the SYSAHBCLKCTRL register 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled 3 System oscillator enabled with external clock input IRC and system PLL disabled Fig 8 Active mode Typical supply current lpp versus supply voltage Vpp ava for different system clock frequencies all peripherals enabled 12 24 16 002aag0 33 MHz IDD mA 24 MHz 2 12 12 MHz 1 EO NP T H T AT ttt 4 MHz _ 1 MHz MMC MEN H 1 77 H 40 15 10 35 60 85 temperature C Conditions Vpp ava 3 3 V active mode entered executing code while 1 from flash all peripherals enabled in the SYSAHBCLKCTRL register 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled 3 System oscillator enabled with external clock input IRC and system PLL disabled Fig 9 Active mode Typical supply current Ipp versus temperature for different system clock frequencies peripherals enabled All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 36 of 61 NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller 0022ag188 5 IDD 33 MHz m
45. g voltage on outputs in 3 state mode Vpp 3va and Vpp io supply voltages must be present 3 state outputs go into 3 state mode when Vpp o is grounded Allowed as long as the current limit does not exceed the maximum current allowed by the device To Vss LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 33 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 10 1 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG for analog blocks registers All other blocks are disabled in both registers and no code is executed Measured on a typical sample at Tamp 25 C and Vpp av3 3 3 V Table 8 Peripheral power consumption Peripheral Typical current consumption lnn in mA Frequency 24 MHz 12 MHz independent system IRC PLL system IRC oscillator PLL oscillator IRC 0 29 PLL PLL output 1 87 frequency 24 MHz WDosc WDosc output 0 25 gt frequency 500 kHz BOD 0 06 S S Analog comparator 0 1 0 05 0 05 0 03 0 02 ADC 1 86 1 85 1 61 1 61 CRC engine 0 04 0 04 0 02 0 02 16 bit timer 0 CT16BO 0 09 0 09 0 04 0 04 16 bit timer 1 CT16B1 0 09 0 09 0 04 0 04 32 bit timer
46. gether with the pin s reset state Table 3 LPC122x pin description Symbol 2 Start Type Reset Description fE E logic state o G input DI cl al G PIOO 0 to PIOO 31 UO Port 0 Port 0 is a 32 bit I O port with individual direction and function controls for each bit The operation of port 0 pins depends on the function selected through the IOCONFIG register block PIOO O RTSO 15 19 21 yes UO I PU PIOO0 0 General purpose digital input output pin 3 B O RTSO Request To Send output for UARTO PIOO 1 RXDO 16 20 l yes IO I PU PIOO 1 General purpose digital input output pin CT32B0_CAP0 3 ae RXDO H for UARTO CT32B0_MATO 0 eceiver input for U 0 CT32B0_CAPO Capture input channel 0 for 32 bit timer 0 O CT32B0_MATO Match output channel 0 for 32 bit timer 0 PIOO_2 TXDO 17 21 l yes IO I PU PIOO 2 General purpose digital input output pin CT32B0_CAP1 3 TXDO T for UARTO CT32B0_MAT1 O 0 ransmitter output for U 0 CT32B0 CAP1 Capture input channel 1 for 32 bit timer O O CT32B0_MAT1 Match output channel 1 for 32 bit timer 0 PIOO S DTRO 18 22 yes IO I PU PIOO 3 General purpose digital input output pin CT32B0_CAP2 3 pps DTRO Data T IR for UARTO CT32B0_MAT2 O 0 ata Terminal Ready output for U 0 CT32B0 CAP2 Capture input channel 2 for 32 bit timer 0 O CT32B0_MAT2 Match output channel 2 for 32 bit timer 0 PIO0_4 DSR
47. he Watchdog reset power on reset POR and the BrownOut Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip reset by any source once the operating voltage attains a usable level starts the IRC and initializes the flash controller When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 26 of 61 NXP Semiconductors LPC122x 7 19 3 7 19 4 32 bit ARM Cortex M0 microcontroller An external pull up resistor is required on the RESET pin if Deep power down mode is used Brownout detection The LPC122x includes four levels for monitoring the voltage on the Vop ava pin If this voltage falls below one of the four selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register An additional threshold level can be selected to cause a forced reset of the chip Code security Code Read Protection CRP This feature of the LPC122x allows user t
48. he removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or LPC122X All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk App
49. he timer value on the trailing edge Supports timed DMA requests 7 16 Windowed WatchDog timer WWDT The purpose of the watchdog is to reset the microcontroller within a windowed amount of time if it enters an erroneous state When enabled the watchdog will generate a system reset if the user program fails to feed or reload the watchdog within a predetermined amount of time 7 16 1 Features LPC122X Internally resets chip if not periodically reloaded Debug mode Incorrect Incomplete feed sequence causes reset interrupt if enabled Safe operation can be locked by software to be always on Flag to indicate watchdog reset Programmable 24 bit timer with internal prescaler All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 22 of 61 NXP Semiconductors LPC122x 7 17 7 17 1 7 18 7 18 1 LPC122X 32 bit ARM Cortex M0 microcontroller e Selectable time period from Tcy WDCLk x 256 x 4 to Tcy WDCLk x 224 x 4 in multiples of Tcy WDCLK x 4 The Watchdog Clock WDCLK source can be selected from the Internal RC oscillator IRC or the Watchdog oscillator This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal a
50. ins PIOO 0 to PIOO 11 up to 12 pins total and the RTC match interrupt can serve as a wake up input to the start logic to wake up the chip from Deep sleep mode Unless the watchdog oscillator is selected to run in Deep sleep mode the clock source should be switched to IRC before entering Deep sleep mode because the IRC can be Switched on and off glitch free Deep power down mode In Deep power down mode power is shut off to the entire chip with the exception of the Real Time Clock the four general purpose registers and the WAKEUP pin The LPC122x can wake up from Deep power down mode via the WAKEUP pin or the RTC match interrupt When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH The RESET pin must also be held HIGH to prevent it from floating while in Deep power down mode System control Start logic The start logic connects external pins to corresponding interrupts in the NVIC Each pin shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt vector table The start logic pins can serve as external interrupt pins when the chip is running In addition an input signal on the start logic pins can wake up the chip from Deep sleep mode when all clocks are shut down The start logic must be configured in the system configuration block and in the NVIC before being used Reset Reset has four sources on the LPC122x the RESET pin t
51. ions 17 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 59 of 61 NXP Semiconductors LPC122x 19 Contents 32 bit ARM Cortex M0 microcontroller m W EK Eb QM 6 1 6 2 7 7 1 7 1 1 7 2 7 3 7 4 7 5 7 5 1 7 5 2 7 6 7 6 1 7 7 7 7 1 7 8 7 8 1 7 9 7 9 1 7 10 7 10 1 7 11 7 11 1 7 12 7 12 1 7 13 7 18 1 7 14 7 14 1 7 15 7 15 1 7 16 7 16 1 7 17 7 17 1 7 18 7 18 1 7 18 1 1 General description 1 Features and benefits 1 Applications 3 Ordering information 3 Ordering options 4 Block diagram 5 Pinning information 6 PINNING a 25 57 LR E oun ec ET Bd a Bike d xtd D Pin description s n a nanana aaa 8 Functional description 16 ARM Cortex MO processor 16 System tick timer 16 On chip flash program memory 16 On chip SRAM
52. is subject to legal disclaimers 7 18 1 3 7 18 2 7 18 3 7 18 4 7 18 5 7 18 5 1 7 18 5 2 7 18 5 3 7 19 7 19 1 7 19 2 7 19 3 7 19 4 7 19 5 7 19 6 7 19 7 7 20 7 21 9 1 10 10 1 10 2 10 3 10 4 10 5 11 11 1 11 2 11 3 11 4 11 5 12 12 1 12 2 12 3 13 14 15 16 17 17 1 17 2 17 3 Watchdog oscillator 25 System PLL 25 Clock output 25 Wake up process 25 Power control 25 Sleep mode 25 Deep sleep mode 26 Deep power down mode 26 System control 26 Start logic i 3444444 da e rl eee ews 26 RSE noni kie R aude 26 Brownout detection 27 Code security Code Read Protection CRP 27 APB interface 27 AHB Lite 27 External interrupt inputs 27 Emulation and debugging 28 Integer division routines 28 Limiting values 29 Thermal characteristics 30 Thermal characteristics 30 Static characteristics 31 Peripheral power consumption 34 Power consumption 34 Electrical pin characteristics 38 ADC characteristics 42 BOD static characteristics 44
53. ler 10 4 ADC characteristics LPC122X Table 9 ADC static characteristics Tamb 40 C to 85 C unless otherwise specified ADC frequency 9 MHZ Vpp ava 3 0 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit Via analog input voltage 0 Vpp avs V Cia analog input capacitance 1 pF Ep differential linearity error LISIA 1 LSB Ei adj integral non linearity BIS 2 5 LSB Eo offset error BIS 1 LSB Ec gain error 7 t3 LSB Er absolute error 2 8 3 LSB fc ADC ADC conversion frequency S 257 kHz Ri input resistance BHO 3 9 MQ 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 Conditions Vss 0V Vpp 3v3 3 8 V 3 The ADC is monotonic there are no missing codes 4 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 19 5 The integral non linearity E ag is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 19 6 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 19 7 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing
54. lications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting
55. ling edge of SCL applies to data in transmission and the acknowledge 3 A device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the Viu min of the SCL signal to bridge the undefined region of the falling edge of SCL 4 Cp total capacitance of one bus line in pF If mixed with Hs mode devices faster fall times are allowed 5 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified t 6 In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing 7 The maximum tgup par could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ pAr or tvp ack by a transition time This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 8 tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge 9 A Fast mode l2C bus device can be used in a Standard mode I C bus system but
56. ller 10 5 BOD static characteristics Table 10 BOD static characteristics Tamb 25 C Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 1 assertion 2 25 V de assertion 2 39 V interrupt level 2 assertion 2 54 V de assertion 2 67 V interrupt level 3 assertion 2 83 V de assertion 2 93 V reset level 1 assertion 2 04 V de assertion 2 18 V reset level 2 assertion 2 34 V de assertion 2 47 V reset level 3 assertion 2 62 V de assertion 2 76 V 1 Interrupt levels are selected by writing the level value to the BOD control register BODCTRL see LPC122x user manual LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 44 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 11 Dynamic characteristics 11 1 Power up ramp conditions LPC122X Table 11 Power up characteristics Tamb 40 C to 85 C Symbol Parameter Conditions Min Typ Max Unit tr rise time att t4 0 lt V lt 400 mV EH 0 500 ms twait wait time Ha 12 us VI input voltage att t on pin Vpp 0 400 mV 1 See Figure 20 2 The wait time specifies the time the power supply must be at levels below 400 mV before ramping up t Voo 400 mV 0 ar I lwait tst 002aag00
57. ls Micro DMA controller with 21 channels CRC engine Two UARTS with fractional baud rate generation and internal FIFO One UART with RS 485 and modem support and one standard UART with IrDA SSP SPI controller with FIFO and multi protocol capabilities C bus interface supporting full I2C bus specification and Fast mode Plus with a data rate of 1 Mbit s with multiple address recognition and monitor mode 2C bus pins have programmable glitch filter Up to 55 General Purpose I O GPIO pins with programmable pull up resistor open drain mode programmable digital input glitch filter and programmable input inverter Programmable output drive on all GPIO pins Four pins support high current output drivers All GPIO pins can be used as edge and level sensitive interrupt sources Four general purpose counter timers with four capture inputs and four match outputs 32 bit timers or two capture inputs and two match outputs 16 bit timers Windowed WatchDog Timer WWDT IEC 60335 Class B certified Analog peripherals One 8 channel 10 bit ADC Two highly flexible analog comparators Comparator outputs can be programmed to trigger a timer match signal or can be used to emulate 555 timer behavior Power Three reduced power modes Sleep Deep sleep and Deep power down Processor wake up from Deep sleep mode via start logic using 12 port pins Processor wake up from Deep power down
58. mation provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 39 of 61 NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller 1 2 002aag181 lot mA Conditions VppvI0 3 3 V Fig 16 Normal drive pins Typical LOW level output voltage Vo_ versus LOW level output current Io 2aag 182 34 002aag18 VoH v 3 0 low mode 2 6 2 2 1 8 loH mA Conditions Vpp o 3 3 V Fig 17 Normal drive pins Typical HIGH level output voltage Voy versus HIGH level output source current loy All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 40 of 61 NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller 0022ag185 Conditions Vpp o 8 3 V Fig 18 Typical pull up current lau versus input voltage Vi Vi mA All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 41 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex MO microcontrol
59. memory the main static RAM and the Boot ROM External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 27 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 7 20 Emulation and debugging Debug functions are integrated into the ARM Cortex MO Serial wire debug is supported 7 21 Integer division routines The LPC122x contain performance optimized integer division routines with support for up to 32 bit width in the numerator and denominator Routines for signed and unsigned division and division with remainder are available The integer division routines are ROM based to reduce code size LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 28 of 61 NX P Semiconductors LPC122x 8 32 bit ARM Cortex M0 microcontroller Limiting values Table 5 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 Symbol Parameter Conditions Vpp 3v3 supply voltage 3 3 V VDpD IO input output supply voltage Vi input voltage on all digital pins on pins PIOO 10 and PIOO 11 2C bus pins Ipp supply current per supply pin Iss ground current per ground pin latch
60. n continued Symbol 2 Start Type Reset Description n a logic state G O input DI cl al B E oa PIO2_6 35 l no VO I PU PIO2 6 General purpose digital input output pin CT32B0_CAP2 3 ST T32B0 CAP2 h 2 for 32 CT32B0 MAT2 DCDO CT32BO C Capture input channel 2 for 32 bit timer 0 O CT32B0_MAT2 Match output channel 2 for 32 bit timer 0 DCDO Data Carrier Detect input for UARTO PIO2_7 36 2 no VO E PU PIO2 7 General purpose digital input output pin CT32B0_CAP3 3 E om CT32B0_CAP3 Ch 3 for 32 CT32B0 MAT3 DSRO 32B0_CAP3 Capture input channel 3 for 32 bit timer 0 O CT32B0_MAT3 Match output channel 3 for 32 bit timer 0 DSRO Data Set Ready input for UARTO PIO2_8 59 BP no lO E PU PIO2 8 General purpose digital input output pin 3 res 3 CT32B1 CAPO Capture input channel 0 for 32 bit timer 1 O CT32B1_MATO Match output channel 0 for 32 bit timer 1 PIO2_9 60 B no VO I PU PIO2_9 General purpose digital input output pin 3 CT32B1_CAP1 m CT32B1_CAP1 Capture input channel 1 for 32 bit timer 1 CT32B1_MAT1 O CT32B1_MAT1 Match output channel 1 for 32 bit timer 1 PIO2_10 61 B no VO E PU PIO2 10 General purpose digital input output pin CT32B1 CAP2 B e T32B1_CAP2 h 2 for 32 1 CT32B1 MAT2 TXD1 CT32B1 C Capture input channel 2 for 32 bit timer O CT32B1_MAT2 Match output channel
61. nction controls for each bit The operation of port 1 pins depends on the function selected through the IOCONFIG register block Pins PIO1 7 through PIO1 31 are not available R PIO1 0 AD2 36 48 El no O PU R Reserved Configure for an alternate function in the 3 IOCONFIG block VO PIO1 0 General purpose digital input output pin AD2 A D converter input 2 R PIO1 1 AD3 37 49 l8 no PU R Reserved Configure for an alternate function in the 3 IOCONFIG block Do not pull this pin LOW at reset VO PIO1_1 General purpose digital input output pin l AD3 A D converter input 3 PIO1_2 SWDIO AD4 38 50 8 no lO E PU PIO1_2 General purpose digital input output pin 3 3l VO SWDIO Serial wire debug input output alternate location l AD4 A D converter input 4 PIO1_3 AD5 WAKEUP 39 51 Bl no VO I PU PIO1_3 General purpose digital input output pin 5 Bl AD5 A D converter input 5 WAKEUP Deep power down mode wake up pin PIO1 4 AD6 40 52 6 no VO E PU PIO1 4 General purpose digital input output pin LPC122X All information provided in this document is subject to legal disclaimers AD6 A D converter input 6 NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 11 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 3 LPC122x pin description continued Symbol 2 Start Type Res
62. nd its associated components and wiring for increased reliability Real time clock RTC The RTC provides a basic alarm function or can be used as a long time base counter The RTC generates an interrupt after counting for a programmed number of cycles of the RTC clock input Features Uses dedicated 32 kHz ultra low power oscillator Selectable clock inputs RTC oscillator 1 Hz delayed 1 Hz or 1 kHz clock or main clock with programmable clock divider 32 bit counter Programmable 32 bit match compare register Software maskable interrupt when counter and compare registers are identical Generates wake up from Deep sleep and Deep power down modes Clocking and power control Crystal oscillators The LPC122x include four independent oscillators These are the system oscillator the Internal RC oscillator IRC the RTC 32 kHz oscillator for the RTC only and the Watchdog oscillator Except for the RTC oscillator each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC122x will operate from the Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency See Figure 5 for an overview of the LPC122x clock generation All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data
63. ns after reset Table 4 Pin multiplexing Peripheral Function Type Available on ports Analog comparators ROSC UO PIOO 29 ACMPO 10 l PIOO 19 ACMPO 11 l PIOO 20 ACMPO I2 PIOO 21 ACMPO I3 PIOO 22 ACMPO O O PIOO 27 ACMP1_l0 l PIOO 23 ACMP 1 11 PIOO 24 ACMP 1 I2 PIOO 25 S S ACMP1_13 l PIOO 26 ACMP1 O O PIOO 28 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Pin state at reset for default function Input O Output PU internal pull up enabled IA inactive no pull up down enabled Product data sheet Rev 2 26 August 2011 14 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Table 4 Pin multiplexing Peripheral Function Type Available on ports ADC ADO PIOO 30 AD1 l PIOO 31 AD2 PIO1 0 AD3 PIO1_1 AD4 PIO1 2 AD5 PIO1 3 AD6 PIO1 4 AD7 PIO1 5 CT16BO CT16BO CAPO PIOO_11 PIOO 28 PIO2 0 CT16BO CAP1 PIOO0 12 PIOO 29 PIO2 1 CT16BO MATO PIOO0 11 PIO0 28 PIO2 0 CT16BO MATT O PIOO 12 PIOO 29 PIO2 1 CT16B1 CT16B1 CAPO PIOO 15 PIO1 5 PIO2 2 CT16B1 CAP1 PIOO0 16 PIO1 6 PIO2 3 CT16B1 MATO 0 PIOO 15 PIO1 5 PIO2 2 CT16B1 MATT O PIO0O 16 PIO1 6 PIO2 3 CT32B0 CT32BO CAPO l PIOO 1 PIOO 18 PIO2 4 CT32B0_CAP1 PIOO 2 PIOO 19 PIO2 5 CT32B0_CAP2 l PIOO 3 PIOO 20 PIO2 6 CT32B0_CAP3 l PIOO 4 PIOO 21 PIO2 7
64. ntinued Symbol e st Start Type Reset Description i 6 n logic state O O input D d E E oa Vpp 0 47 63 l Input output supply voltage Vpp 3v3 44 56 3 3 V supply voltage to the internal regulator and the ADC Also used as the ADC reference voltage Vssio 48 64 s Ground Vss 43 55 Ground 1 2 3 3 V tolerant digital I O pin default pull up enabled no hysteresis 3 If set to output this normal drive pin is in low mode by default 4 2C bus pins 5 V tolerant open drain default no pull up pull down no hysteresis 5 3 3 V tolerant digital I O pin with RESET function default pull up enabled no hysteresis An external pull up resistor is required on this pin for the Deep power down mode 6 3 3 V tolerant digital I O pin with analog function default pull up enabled no hysteresis 7 If set to output this normal drive pin is in high mode by default 8 3 3 V tolerant digital I O pin with analog function and WAKEUP function default pull up enabled no hysteresis 9 3 3 V tolerant high drive digital I O pin default pull up enabled no hysteresis 10 If the RTC is not used RTCXIN and RTCXOUT can be left floating To enable a peripheral function find the corresponding port pin or select a port pin if the function is multiplexed and program the port pin s IOCONFIG register to enable that function The primary SWD functions and RESET are the default functions on their pi
65. o enable different levels of security in the system so that access to the on chip flash and use of the SWD and ISP can be restricted When needed CRP is invoked by programming a specific pattern into a dedicated flash location IAP commands are not affected by the CRP There are three levels of Code Read Protection 1 CRP1 disables access to chip via the SWD and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased 2 CRP2 disables access to chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands 3 Running an application with level CRP3 selected fully disables any access to chip via the SWD pins and the ISP This mode effectively disables ISP override using PIOO 12 pin too It is up to the user s application to provide if needed flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UARTO CAUTION A If level three Code Read Protection CRP3 is selected no future factory testing can be performed on the device 7 19 5 7 19 6 7 19 7 LPC122X In addition to the three CRP levels sampling of pin PIOO_12 for valid user code can be disabled APB interface The APB peripherals are located on one APB bus AHB Lite The AHB Lite connects the CPU bus of the ARM Cortex MO to the flash
66. o export control regulations Export might require a prior authorization from national authorities NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 58 of 61 NXP Semiconductors LPC122x Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s 18 Contact information 32 bit ARM Cortex M0 microcontroller own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specificat
67. offset error and the straight line which fits the ideal transfer curve See Figure 19 8 The absolute error Er is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 19 9 Tamb 25 C maximum sampling frequency fs 257 kHz and analog input capacitance Cia 1 pF 10 Input resistance R depends on the sampling frequency fs Rj 1 fs x Cia All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 42 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 1023 offset error Eo gain error Eg 1022 1021 1020 1019 1018 code out Las 1 1018 Via LSBideal offset error Eo 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity EL agj 5 Center of a step of the actual transfer curve Fig 19 ADC characteristics L 1019 l es L L L 1020 1021 1022 1023 1024 Vpp 3v3 s 1024 002aae787 LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 43 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontro
68. package SOT313 2 Hx Le Gx gt gt P2 je gt P1 a aa p IAA A A PA AA iar ia A A EA pat TAA AA A A A A A D A 7 AO OGG DIA MN I I I ZZ ZA Z Z L pum ZA TA ZA A Zz Hy Gy LL EEE By Ay ZA ZZ TZ ZZ ere ES EZA EZ gigi EES ZA ZZA EZ ZZ 1 et I I Y up 1 11 1 1 Wt o HHDH H 0 D d D2 8x B L D1 La Bx gt a Ax gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land Occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 10 350 10 350 7 350 7 350 1 500 0 280 0 500 7 500 7 500 10 650 10 650 sot313 2 fr Fig 27 Reflow soldering of the LQFP48 package LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 54 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314 2 La Hx gt Gx gt P2 je gt P1 a wmm uuum r I 1 1 l A IAM I Z E SES A A A A A i 7 ns ER EZZ ZZA EE ZZA ZA 1 I ZA ZA 1 ZZ ZZ Sooo Hy Gy ZZ ZA By Ay Lou Z ZA LZ D TT TIT PRU le ZZ ZA oe pc ri ZZ ZZ i f I Y v 1 E TRR HHHH HHT C
69. r SSP SPI PIOO 18 SWCLK 33 45 BI no VO E PU PIOO 18 General purpose digital input output pin 3 CM B SWCLK Serial wire clock alternate location CT32B0 CAPO Capture input channel 0 for 32 bit timer 0 O CT32B0 MATO Match output channel 0 for 32 bit timer 0 PIOO 19 ACMPO Il 4 4 E no VO E PU PIOO 19 General purpose digital input output pin CT32B0_CAP1 Ul 7 ACMPO 10 f i CT32B0 MAT1 CMPO I0 nput 0 for comparator 0 CT32B0 CAP1 Capture input channel 1 for 32 bit timer O O CT32B0_MAT1 Match output channel 1 for 32 bit timer 0 PIOO_20 ACMP0_11 5 5 El no VO E PU PIOO 20 General purpose digital input output pin CT32B0 CAP2 Ul G ACMPO 11 1f 2 CT32B0_MAT2 CMPO nput 1 for comparator 0 CT32B0 CAP2 Capture input channel 2 for 32 bit timer 0 O CT32B0_MAT2 Match output channel 2 for 32 bit timer 0 PIOO_21 ACMP0_12 6 6 E no VO E PU PIOO 21 General purpose digital input output pin CT32B0_CAP3 Ul 7 ACMPO 12 2f 3 CT32B0_MAT3 CMPO nput 2 for comparator 0 CT32B0 CAP3 Capture input channel 3 for 32 bit timer 0 O CT32B0_MAT3 Match output channel 3 for 32 bit timer 0 PIOO 22 ACMPO I3 7 7 F8 no lO E PU PIOO 22 General purpose digital input output pin Y u ACMPO I3 Input 3 for comparator 0 PIOO 23 8 8 El no lO E PU PIOO 23 General purpose digital input output pin ACMP1_10 Z ACMP1 I0 Input 0 for compa
70. rator 1 CT32B1 CAPO CT32B1_MATO CT32B1 CAPO Capture input channel 0 for 32 bit timer 1 O CT32B1_MATO Match output channel 0 for 32 bit timer 1 PIOO_24 ACMP1_11 9 9 amp no VO I PU PIOO 24 General purpose digital input output pin CT32B1 CAP1 Ul ACMP1 H 1f 1 CT32B1 MAT C L nput 1 for comparator CT32B1 CAP1 Capture input channel 1 for 32 bit timer 1 O z CT32B1_MAT1 Match output channel 1 for 32 bit timer 1 SWDIO ACMP1_12 10 10 no VO E PU SWDIO Serial wire debug input output default location CT32B1 CAP2 Ul ACMP1_12 2f 1 CT32B1_MAT2 C E nput 2 for comparator PIOO 25 l CT32B1_CAP2 Capture input channel 2 for 32 bit timer 1 O S CT32B1_MAT2 Match output channel 2 for 32 bit timer 1 VO PIOO 25 General purpose digital input output pin SWCLK ACMP1 I3 11 11 Bl no l PU SWCLK Serial wire clock default location CT32B1 CAP3 Ul 7 ACMP1 I3 f 1 CT32B1 MAT3 C _13 nput 3 for comparator PIOO 26 l CT32B1_CAP3 Capture input channel 3 or 32 bit timer 1 O CT32B1_MAT3 Match output channel 3 for 32 bit timer 1 UO PIOO 26 General purpose digital input output pin LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 10 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller
71. rrupt Controller NVIC is an integral part of the Cortex MO The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 5 1 Features Controls system exceptions and peripheral interrupts LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 17 of 61 NXP Semiconductors LPC122x 7 5 2 7 6 7 6 1 7 7 7 7 1 LPC122X 32 bit ARM Cortex M0 microcontroller Inthe LPC122x the NVIC supports 32 vectored interrupts In addition up to 12 of the individual GPIO inputs are NVIC vector capable Four programmable interrupt priority levels with hardware priority level masking e Software interrupt generation Non maskable Interrupt NMI can be programmed to use any of the peripheral interrupts The NMI is not available on an external pin Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags Individual interrupt flags may also represent more than one interrupt source Any GPIO pin total of up to 55 pins regardless of the selected function can be programmed to generate an interrupt on a level a rising edge or falling edge or both IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function Configuration register
72. s allowing for the recording of comparison event time stamps 7 15 General purpose external event counter timers The LPC122x includes two 32 bit counter timers and two 16 bit counter timers The counter timer is designed to count cycles of the system derived clock It can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes up to four capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt 7 15 1 Features A 32 bit 16 bit timer counter with a programmable 32 bit 16 bit prescaler Counter or timer operation Up to four capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event may also generate an interrupt Four match registers per timer that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match The timer and prescaler may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing t
73. s control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Features Programmable pull up resistor Programmable digital glitch filter Programmable input inverter Programmable drive current Programmable open drain mode Micro DMA controller The micro DMA controller enables memory to memory memory to peripheral and peripheral to memory data transfers The supported peripherals are UARTO transmit and receive UART1 transmit and receive SSP SPI transmit and receive ADC RTC 32 bit counter timer 0 match output channels 0 and 1 32 bit counter timer 1 match output channels 0 and 1 16 bit counter timer 0 match output channel 0 16 bit counter timer 1 match output channel 0 comparator 0 comparator 1 GPIOO to GPIO2 Features Single AHB Lite master for transferring data using a 32 bit address bus and 32 bit data bus e 21 DMA channels Handshake signals and priority level programmable for each channel Each priority level arbitrates using a fixed priority that is determined by the DMA channel number All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product
74. sheet Rev 2 26 August 2011 23 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller m AHB clock 0 system main clock CLOCK System clock DIVIDER at AHB clocks 1 to 31 memories and peripherals SYSAHBCLKCTRL 1 31 AHB clock enable s CLOCK f DIVIDER peripheral clocks SSP UARTO UART1 7 G peripheral clocks IOCONFIG glitch filter CLOCK DIVIDER IRC oscillator RTC oscillator 1 Hz clock RTC oscillator 1 Hz delayed clock RTC watchdog oscillator RTC oscillator 1 kHz clock MAINCLKSEL RTCOSCCTRL main clock select IRC oscillator IRC oscillator s SYSTEM PLL system oscillator CLOCK LKOUT oi system oscillator system ru watchdog oscillator DIVIDER CLKOUT pin SYSPLLCLKSEL CLKOUTUEN CLKOUT clock update enable IRC oscillator gt WWDT watchdog oscillator WDCLKSEL WWDT clock select 002aaf271 Fig 5 LPC122x clocking generation block diagram 7 18 1 1 Internal RC oscillator The IRC may be used as the clock source for the WDT and or as the clock that drives the PLL and subsequently the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 96 accuracy over the entire voltage and temperature range Upon power up or any chip reset the LPC122x use the IRC as the clock source Software may later switch to one of the other available clock sources 7 18 1 2 System oscill
75. t to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 56 of 61 NXP Semiconductors LPC122x 32 bit ARM Cortex M0 microcontroller 16 Revision history Table 19 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC122X v 2 20110826 Product data sheet LPC122X v 1 2 Modifications Power consumption data updated in Table 7 Power consumption graphs added in Section 10 2 Electrical pin characteristics updated for all pins in Table 7 and Section 10 3 Parameter R added to Table 9 EMC data added Section 12 3 Parameter V updated for I2C bus pins in Table 5 Section 11 1 Power up ramp conditions added Data sheet status updated to Product Data Sheet SSP dynamic characteristics removed LPC122X v 1 2 20110329 Objective data sheet LPC122X v 1 1 Modifications Figure 2 Pin configuration LQFP64 package Pin RTCXIN changed to 58 and pin RTCXOUT changed to 57 Table 3 LPC122x pin description In column Pin LQFP64 pin RTCXIN changed to 58 and pin RTCXOUT changed to 57 LPC122X v 1 1 20110221 Objective data sheet LPC122X v 1 Modifications Section 1 General description Updated text Section 2 Features and benefits Updated text LPC122X v 1 20110214 Objective data sheet LPC122X All information provided in this document is subject to legal disclaimers NXP B V 2011 All righ
76. to it Features e The l2C interface is a standard I2C compliant bus interface with open drain pins and supports I C Fast mode Plus with bit rates of up to 1 Mbit s Programmable digital glitch filter providing a 60 ns to 1 us input filter Easy to configure as master slave or master slave Programmable clocks allow versatile rate control All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved Product data sheet Rev 2 26 August 2011 20 of 61 NXP Semiconductors LPC122x 7 13 7 13 1 32 bit ARM Cortex M0 microcontroller Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I C bus can be used for test and diagnostic purposes The I C bus controller supports multiple address recognition and a bus monitor mode 10 bit ADC The LPC122x contains one ADC It is a single 10 bit successive approximation ADC with eight channels Features 10 bit successive approximation ADC Input multiplexing among 8 pins Power down mode Measurement range 0 V to Vpp ava 10 bit conversion time of 257 kHz
77. troller a CRC engine four general purpose timers a 32 bit RTC a 1 96 internal oscillator for baud rate generation and up to 55 General Purpose I O GPIO pins 2 Features and benefits m Processor core ARM Cortex MO processor running at frequencies of up to 45 MHz one wait state from flash or 30 MHz zero wait states from flash The LPC 122x have a high score of over 45 in CoreMark CPU performance benchmark testing equivalent to 1 51 MHz ARM Cortex MO built in Nested Vectored Interrupt Controller NVIC Serial Wire Debug SWD System tick timer E Memory Up to 8 kB SRAM Up to 128 kB on chip flash programming memory In System Programming ISP and In Application Programming IAP via on chip bootloader software Includes ROM based 32 bit integer division routines W Clock generation unit NXP Semiconductors LPC122x LPC122X 32 bit ARM Cortex M0 microcontroller Crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz Internal RC IRC oscillator trimmed to 1 accuracy that can optionally be used as a system clock PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the system oscillator or the internal RC oscillator Clock output function with divider that can reflect the system oscillator clock IRC clock main clock and Watchdog clock Real Time Clock RTC E Digital periphera
78. ts reserved Product data sheet Rev 2 26 August 2011 57 of 61 NXP Semiconductors LPC122x 17 Legal information 32 bit ARM Cortex M0 microcontroller 17 1 Data sheet status Document status 1l2 Product status Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 Theterm short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 17 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from
79. values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights Export control This document as well as the item s described herein may be subject t
80. vide by 2 4 8 or 16 to produce the output clock The PLL output frequency must be lower than 100 MHz Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle The PLL is turned off and bypassed following a chip reset and may be enabled by software The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is 100 us Clock output The LPC122x features a clock output function that routes the IRC oscillator the system oscillator the watchdog oscillator or the main clock to an output pin Wake up process The LPC122x begin operation at power up and when awakened from Deep power down mode by using the 12 MHz IRC oscillator as the clock source This allows chip operation to resume quickly If the main oscillator or the PLL is needed by the application software will need to enable these features and wait for them to stabilize before they are used as a clock source Power control The LPC122x support a variety of power control features There are three special modes of processor power reduction Sleep mode Deep sleep mode and Deep power down mode The CPU clock rate may also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This allows a trade off of power versus processing speed based on application requirements In addition a register is provi

LPC122x - NXP Semiconductors

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