CubeSuite+ Simulator for V850ES/Jx2 V3.00.03 Release Note
Contents
1. ee ccceccececsneceeecsneceeecsneeeeeeseaeeeeesaeeeessseeeesssneeeenees 11 5 1 17 1 Hz pin output of real time counter 0 2 eee eeceecee cece ee ee cece ae cece eect tees aaeaeeeeeeesesenceeeeeeeeeseeseaeees 11 5 118 REC back Up Modessa a vate eee revue aa E E e EA 11 5 1 19 Reset during RTC back Up Moga sesiis akini Ea N aAA EAEAN 12 5 1 20 Interrupt response time sessies eiiiai a iiaia ia a aA 12 9 1 21 Low voltage dateci esinsin E AAA R Aa 12 5 2 Cautions for using simulator GUI eee cent eee entree eee ae erence ae t nunn t AESA EEEn SEEE EA AEE En nE EEEn at Ennan ennn ae 13 5 2 1 Cautions for controlling each WINGOWS sssssssseessssrrssesrrssttrrtsternttttrrnnattnnasttnnnatennnnttnnnne tn nnnten nannt 13 5 2 2 Cautions for closing simulator GUI WINdOW sesssssssssesresssrrsseerrssttnrssttrrsssttnnnnttnnnsttnnantennnseen nannt 13 5 2 3 Cautions for showing help for the simulator GUI WiINGOW ssssssssssssrssssrrsserrsssirrestirrssrennssrrnssne 13 5 2 4 Cautions for disconnecting the debug tool 0 0 eee eee teeters erties nannan RAKAN NNNNA NAANA 13 5 2 5 Cautions for setting the Host Machine s language and region eceeeeeeeeeeeeeeeeeeeeeneeeeeteteeeeeeeee 14 Chapter 6 Restrictions 2 2 5 sicecccesesdscesscccarsaacsedcesazcuadanaesdicersandncseuedad convannadeeseaqeadesteiuadaodneaqecetaccadasasaecgavanes 15 6 1 Restrictions for the Simulator for V850ES Ux2 oo cc cecececeecee cece eeeeeeeaeeeeeeeeeeeesecacaee2. Devices Description Workaround Fix V850ES JC3 L V850ES JE3 L V850ES JC3 H V850ES JE3 H List of restrictions for the Simulator for V850ES Jx2 Target Devices Restrictions Restriction on accessing PMDL PDL registers Restriction Details for the Simulator for V850ES Jx2 Restriction on accessing PMDL PDL registers V850ES JC3 L V850ES JE3 L V850ES JC3 H V850ES JE3 H It is impossible to access PMDL and PDL registers by 16 bit access instructions Please use 8 bit access instructions or 1 bit access instructions for accessing PMDLL and PDLL registers In planning All trademarks and registered trademarks are the property of their respective owners R20UT2508EJ0100 Rev 1 00 Page 15 of 15 February 25 2013 RENESAS Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability wha
3. matter what value the oscillation stabilization time selection register OSTS is set to the simulator s oscillation stabilization time is always 0 seconds Therefore the value of CCLS register is always OOH The simulator also does not simulate the PLL s lock up time No matter what value the PLL lock up time specification register PLLS is set to the lock up time is always 0 seconds Additionally bit 0 the LOCK bit of the lock register L OCKR is cleared at the same time as the above lock up 5 1 4 Internal feedback resister of main clock and sub clock The simulator does not simulate the internal feedback resister of the main clock or sub clock For this reason the main clock and sub clock will always oscillate regardless of the settings of the MFRC and FRC bits on the processor clock control register PCC 5 1 5 Port function If both of the conditions below are met then the simulator will ignore writes to the port registers e g PO and PDL Don t perform writes under the conditions below Conditions for ignoring writes to port registers The corresponding bit of the port mode control register e g PMCO or PMCDL is set to 1 port s dual function is enabled The corresponding bit of the port mode register e g PMO or PMDL is clear to 0 set to output mode R20UT2508EJ0100 Rev 1 00 Page 7 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 1 6 Noise reduction circ
4. conversion mode conversion time 5 1 14 Default voltage of AVrero pin and AVreri pin Default voltage of AVrero pin is 3 3V And default voltage of AVrer pin is 3 6V Note The meaning of Default voltage is the voltage when the pin have no connection 5 1 15 Capture trigger of 16 bit timer event counter Q TMQ The simulator does not support the CAN controller For this reason you should not select the CANO s TSOUT signal as the TIABO2 pin s capture trigger input signal as the capture trigger of the 16 bit timer event counter AB TAB do not set the ISELO bit of selector operation control register 0 SELCNTO to 1 If this setting is made the capture trigger will not be activated 5 1 16 Noise filter of 16 bit timer event counter Although the target device s 16 bit timer event counters AA TAA and T TMT have noise filters to reduce noise on the input pin the simulator does not simulate this Since there is no noise in the simulator s signal it would be meaningless to simulate this function 5 1 17 1 Hz pin output of real time counter If the waveform of the RTC1HZ pin is checked in the timing chart window using 1 Hz pin output of the real time counter the output waveform has a frequency of 32 768 Hz In this case determine that 1 Hz output is being performed without problems 5 1 18 RTC back up mode RTC back up mode simulation is supported but simulation when turning off the power supply VDD or EVDD is not
5. supported When you want to simulate RTC back up mode please set condition for RTC back up mode by only software R20UT2508EJ0100 Rev 1 00 Page 11 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 1 19 Reset during RTC back up mode Reset operations during RTC back up mode are following The case pushing CPU Reset button RTC is stopped RTC registers are initialized The case setting RESET signal level low RTC continues to count 5 1 20 Interrupt response time The interrupt response times of the target device and simulator differ Target device It takes at least 4 clock cycles after an interrupt is generated until execution branches to the handler address Simulator Execution branches to the handler address immediately upon the interrupt 5 1 21 Low voltage detector The simulator does not simulate the internal RAM data status register RAMS Although the initial value will be the same as the target device 0x01 the behavior differs on the following three points Writing is possible without a specific sequence The RAMF bit will not be set to 1 if a voltage below the RAM hold voltage is detected Setting the EVARAMIN bit of peripheral emulation register 1 PEMU7 to 1 will not cause the RAMF bit to be set to 1 R20UT2508EJ0100 Rev 1 00 Page 12 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 2 Cautions fo
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7. Differences from behavior of target devices due to simulator specifications Notes for using simulator GUI Notes for using the simulator GUI window 5 1 Differences between target devices and simulator 5 1 1 Unsupported peripheral functions The simulator does not support the following peripheral functions of the target device the following functions cannot be debugged on the simulator Flash self programming function CRC function Clock monitor Regulator USB function controller USB host controller CAN controller IIC 5 1 2 Reset If a reset is generated by the low voltage detector circuit the simulator will display STANDBY in the status bar The status is actually reset not standby And the behavior differs as follows if a reset is generated by the RESET pin Target device Goes into reset status when the RESET pin goes to low level Reset status is released when it goes to high level Simulator Does not go into reset status when the RESET pin goes to low level When it goes to high level the simulator momentarily goes into reset status and then the reset status is released immediately R20UT2508EJ0100 Rev 1 00 Page 6 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 1 3 Oscillation stabilization time and lock up time of clock generator The simulator does not simulate the oscillation stabilization time of the clock generator For this reason no
8. F3765 uPD70F3766 uPD70F3767 uPD70F3771 V850ES JG3 U UPD70F3763 uPD70F3764 V850ES JH3 U uPD70F3768 uPD70F3769 R20UT2508EJ0100 Rev 1 00 February 25 2013 RENESAS Page 2 of 15 CubeSuite Simulator for V850ES Jx2 V3 00 03 Chapter 2 User s Manuals Please read the following user s manuals together with this document Manual Name Document Number CubeSuite V2 00 00 V850 Debug R20UT2446EJ0100 CubeSuite V2 00 00 Message R20UT2448EJ0100 R20UT2508EJ0100 Rev 1 00 February 25 2013 RENESAS Release Note Page 3 of 15 CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note Chapter 3 Key Word for Uninstallation To uninstall this product use the integrated uninstaller uninstalls CubeSuite R20UT2508EJ0100 Rev 1 00 Page 4 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note Chapter 4 Changes This chapter describes changes from V3 00 02 to V3 00 03 4 1 Specifications changed 4 1 1 Simulation on CubeSuite V2 00 00 Support simulation on CubeSuite V2 00 00 There is no functional change R20UT2508EJ0100 Rev 1 00 Page 5 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note Chapter 5 Cautions This section describes cautions for using the V850ES Jx2 simulator The following two types of caution are described Differences between target devices and simulator
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10. RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 R20uT2508EJ0100 Rev 1 00 Release Note February 25 2013 Contents Chapter 1 Target Devices 000 2 eccceeeeeeeee ee eeee eter teen ee eeeeeeeeeteaeeeeeseeeeeeseeaeeeseeeaeeeeeeeaeeeseeeaeeeseeaeeeeeeaeees 2 Chapter 2 User s Manuals 2 ccccccceceeencceceeeeeeeeeenaeeeeeeeeescaaeaeeeeeeeseseqaaeaeceseeeeeesedensaeeeseeeeesetennineeeeeeess 3 Chapter 3 Key Word for Uninstallation 0 cccccccecsecceceeeeeeeceeaeeeeeeeeesecaaaeceeeseeeseccacaeceeeeeeeesessnnueaeeeeeess 4 Chapter 4 CNanGeS circenis iia ivet lene cee cian ine a aai aeaa apera a a aa basta vitesse qaad AEAEE E 5 4 1 Specifications changed ccecccceceeeeeeeeeeceeeeeeececeaeaeeeeeeeeeceeaaeceeeeeeesecaaaaeaeeeeeseseesecaeeeeeeeeeseesenaeees 5 4 1 1 Simulation on CubeSuite V2 00 00 ececcccecceceeeeeeeeeecaeeeeeeeeesecacaeceeeeeeeseccacaeeeeeeesesecsnenueaeeeeeens 5 Chapter 5 Cautions i icon haiti esl cites eae ees at ete eee E es anaes EN E 6 5 1 Differences between target devices and simulator 0 0 2 eee eeeeee ee erent ee ee teeter teaser tnaeeeeetneeeees 6 5 1 1 Unsupported peripheral fUNCtiONS cccccceeeeeeeneeceeeeeeeeececaeeeeeeeeeseceaeaeeeeeeeeeseccaeaeeeeeeeeenseesnaeees 6 BAZ RESO ataa a aa dinar aaa a aaa a a a a Ta 6 5 1 3 Oscillation stabilization time and lock up time of clock generator eeeesseeesssersseerreserrresrerrsseeens 7 5 1 4 Internal feedb
11. The transfer speeds of the target device and simulator differ as follows when simulating the DMA controller Target device The time required for a DMA transfer is DMA response time memory access time of transfer source 1 clock cycle memory access time of transfer destination If there is a contention of DMA transfer timing between CPU bus access and DMA bus access by another channel then the bus access with the lower priority waits until the bus access with the higher priority completes Simulator It takes zero clock cycles to complete one DMA transfer If there is a contention of DMA transfer timing between CPU bus access and DMA bus access by another channel then the bus accesses are performed simultaneously 5 1 9 Noise filter on asynchronous serial interface Although the target device s asynchronous serial interfaces UARTA UARTC have a noise filter to reduce noise on the input pin the simulator does not simulate this Since there is no noise in the simulator s signal it would be meaningless to simulate this function 5 1 10 Baud rate of asynchronous serial interface If the baud rate of the asynchronous serial interface UARTA UARTC is set to 233 bps or lower operation will be abnormal it will operate at a higher baud rate than the one set Don t specify a baud rate that is 233 bps or lower 5 1 11 Baud rate clock input of asynchronous serial interface Although the target device s asynchronous serial i
12. ack resister of main clock and SUD clock ccccceceeeeeeececeeeeeeeeeeneeceeeeeeesessnceeeeees 7 5 1 5 0 800101 0 1 5 0 9 cree 7 5 1 6 Noise reduction circuit for external interrupt pin ccececeeceeceeeeeeeeeeeceaeceeeeeeeseceaeaeeeeeeesesensiaeeees 8 5 1 7 External bus interface fUNCtIONS c ccccceceeeeeecee aces eeeeeeceeeeeaeceeeeeeececaanaeceeeeeeesenaneaeeeeeeeensennenaees 9 5 1 8 DMA COMtON GN einni auch cgaraetacnanaden daersdugdeahencedaenadentnneiedun O lt ssanaadeetesdedsbaasnucaetea ds 10 5 1 9 Noise filter on asynchronous Serial interface eee erent eee e tenets ee teneeeeeetneeeee teases tneeeeetea 10 5 1 10 Baud rate of asynchronous Serial interface 0 ceceeeeeeee etter ee eeneee ee eeeeeeeeseeeee teaser tieeeeeeaa 10 5 1 11 Baud rate clock input of asynchronous Serial interface 00 eee eeeeeeeeeneeeeeeeneeeeetteeeeeetneeeeeeee 10 5 1 12 Constant 0 1 bits of I O registers 2 eect eect eee ete ee eee ne eee eee aeee ee teeeee teases tiieeeestieeeeenaa 10 5 1 13 Stabilization time of A D Converter ccccccceccecceceeeeeteeecaeeeeeeeeeesesecaeaeeeeeeesesenneeeeeeeeetenseaeess 11 5 1 14 Default voltage of AVrero pin ANd AV REF PIN ceeccccceceeeeecneececeeeeeseceeeaeceeeeeeeesetsnnieeeeeeeeesenseaeees 11 5 1 15 Capture trigger of 16 bit timer event counter Q TMQ eect teeters ee teieeeee teasers tneeeeeeea 11 5 1 16 Noise filter of 16 bit timer event counter
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14. eeeeesetsnnaeaeeeeeess 15 6 1 1 List of restrictions for the Simulator for V850ES UX2 cccccccceeeeeceeceeceeeeeeesecenaeeeeeeeeeeeeesenaees 15 6 1 2 Restriction Details for the Simulator for V850ES Jx2 0 ccccccccecceceesneeeeeseneeeeessneeeeesesteeeessseeeeeees 15 R20UT2508EJ0100 Rev 1 00 Page 1 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Chapter 1 Target Devices Below is a list of devices supported by the V850ES Jx2 simulator Release Note Nickname Device name V850ES JG2 uPD70F3715 uPD70F3716 uPD70F3717 uPD70F3718 uPD70F3719 V850ES JJ2 UPD70F3720 uPD70F3721 uPD70F3722 uPD70F3723 uPD70F3724 V850ES JG3 uPD70F3739 uPD70F3740 uPD70F3741 uPD70F3742 V850ES JJ3 UPD70F3743 uPD70F3745 uPD70F3744 uPD70F3746 V850ES JC3 L uPD70F3797 uPD70F3798 uPD70F3799 uPD70F3800 uPD70F3801 UPD70F3802 uPD70F3803 uPD70F3804 V850ES JE3 L uPD70F3805 uPD70F3806 uPD70F3807 uPD70F3808 V850ES JF3 L UPD70F3735 uPD70F3736 V850ES JG3 L uPD70F3737 uPD70F3738 uPD70F3792 uPD70F3793 uPD70F3794 uPD70F3795 uPD70F3796 V850ES JC3 H uPD70F3809 uPD70F3810 uPD70F3811 uPD70F3812 uPD70F3813 uPD70F3814 UPD70F3815 uPD70F3816 uPD70F3817 uPD70F3818 uPD70F3819 V850ES JE3 H uPD70F3820 uPD70F3821 uPD70F3822 uPD70F3823 uPD70F3824 uPD70F3825 V850ES JG3 H uPD70F3760 uPD70F3761 uPD70F3762 uPD70F3770 V850ES JH3 H UPD70
15. following dialog boxes is open from the simulator GUI window Make sure that the following dialog boxes are closed before disconnecting the debugging tool Save As Parts Button Properties Open Analog Button Properties New Parts Key Properties Color Parts Level Gauge Properties Font Parts Led Properties Customize Parts Segment LED Properties Loop Parts Matrix Led Properties Select Pin Parts Buzzer Properties Search Data Pull up Pull down Format UART Entry Bitmap Format CSI Object Properties Message e g Error R20UT2508EJ0100 Rev 1 00 Page 13 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 2 5 Cautions for setting the Host Machine s language and region If a Japanese OS is installed on your Host Machine then if the language or region is set to other than Japanese Japan the menus and dialog box names of the simulator GUI window will be shown in English Similarly if a non Japanese OS is installed on your Host Machine then if the language or region is set to Japanese Japan the menus and dialog box names of the simulator GUI window will be shown in Japanese R20UT2508EJ0100 Rev 1 00 Page 14 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note Chapter 6 Restrictions This section describes the restrictions for the Simulator for V850ES Jx2 6 1 Restrictions for the Simulator for V850ES Jx2 6 1 1 6 1 2 No 1
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18. nterfaces UARTA UARTC have ASCKAO and ASCKCO pins as baud rate clock input pins the simulator does not simulate this Inputs of baud rate clocks to these pins are ignored 5 1 12 Constant 0 1 bits of I O registers The I O register has bits that are always 0 or 1 For example bits 3 to 7 are always 0 for the oscillation stabilization time selection register OSTS 7 6 5 4 3 2 1 0 osts 0 o f o 0 0 JosTs2 OSTS1 OSTSO NN t 7A Bits are always 0 Although the values of these bits cannot be changed from the target device the can be changed from the simulator Note that changing these values has no effect on behavior R20UT2508EJ0100 Rev 1 00 Page 10 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 1 13 Stabilization time of A D converter The simulator does not simulate the stabilization time of the A D converter This causes the following differences in behavior Time from start to end of A D conversion on target device Normal conversion mode stabilization time conversion time wait time High speed conversion mode stabilization time conversion time Continuous conversion mode stabilization time conversion time first conversion conversion time second and subsequent conversions Time from start to end of A D conversion on simulator Normal conversion mode conversion time wait time High speed conversion mode conversion time Continuous
19. r using simulator GUI 5 2 1 Cautions for controlling each windows The following keyboard operations are not available in the simulator windows signal data editor window I O panel window and serial window Navigation via tab or arrow keys lt ft Deletion via the Del or Backspace keys Copy amp paste and other operations via the Ctrl C V X A or Z keys Perform the above operations as follows Navigation Navigate using the mouse Deletion Right click and perform the action via the context menu Copy amp paste etc Right click and perform the action via the context menu 5 2 2 Cautions for closing simulator GUI window The simulator GUI window can only be closed by disconnecting from the debugging tool or by closing CubeSuite proper The X button cannot be clicked Additionally although it appears that the X button can be pressed if Aero is enabled in Windows Vista pressing this button will not close the GUI window 5 2 3 Cautions for showing help for the simulator GUI window Pressing the F1 key in the simulator GUI window will not display the help if none of the internal windows are visible e g the I O panel window To display the help for the simulator GUI window from the GUI window s menu select Help gt Main Window 5 2 4 Cautions for disconnecting the debug tool CubeSuite may exit if the debugging tool is disconnected while any of the
20. rnal bus related SFR simulation External bus access is possible even without configuring SFR Check signal input to external bus pins in the Timing Chart window It will appear as high impedance Input to WAIT or HLDRQ pin It will be ignored Access Speed always 0 clock When connecting ROM or RAM to the external bus perform configuration in the Property panel from the Debugging Tool Setting tab Connect by entering Type of memory to connect to emulation ROM area or emulation RAM area Memory address to connect to L5 i 2 V850 Simulator Property This setting enables both Memory iti 4 Writing to external bus E Access Memory While Running Reading from external bus Update display during the execution Yes Display update interval ms 500 Memory mappings For the addition and delet Bnge in start address or end address select mapping dialog box ROM RAM area target memory area and Memory Mapping Memory type Address range Emulation ROM area v 100000 HEX fff Memory type Address range Internal ROM area Ox00000000 Ox000fffft Non map area 0x00100000 O0Ox03feffff mp Internal RAM area OxO03ff0000 Ox03ffefff 60 KBytes 32 bits I O Register area OxO03fff000 OxO03ffFLff E 4 KBytes 8 bits OK Cancel Help R20UT2508EJ0100 Rev 1 00 Page 9 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 1 8 DMA controller
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22. uit for external interrupt pin The simulator does not simulate the noise reduction circuit For example if you input the active level to an external interrupt pin with a noise reduction circuit the interrupt will be received even if the active level amplitude is too low The example below considers the case when there is input to the INTPO pin There is a noise reduction circuit on the INTPO pin of the target device For this reason in order to generate an interrupt it is necessary to input an effective edge to the target device and subsequently maintain the signal level See the user s manual of the target device for the length of time it must be maintained Target device behavior falling effective edge Signal input to INTPO pin In the case of the simulator however this noise reduction circuit is not simulated For this reason an interrupt will be generated any time a valid edge is generated No need to maintain signal level Simulator behavior falling effective edge Signal input to INTPO pin q eB eB R20UT2508EJ0100 Rev 1 00 Page 8 of 15 February 25 2013 RENESAS CubeSuite Simulator for V850ES Jx2 V3 00 03 Release Note 5 1 7 External bus interface functions Some of the external bus interface functions can be simulated and some cannot Functions that can be simulated ROM and RAM connection Access to connected ROM RAM Functions that cannot be simulated Exte
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