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BusyBox User Guide

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1. YVVVVYYVY branch_controller i nitecture of multi channel receiver FA Receiver Module VHDL Entity Hierarchy 1 Multi Channel Receiver 18 Page e Single Channel Receiver Serial Decoder Branch Controller Backbone Controller BusyBox User Guide 5 7 2 Entity Multi Channel Receiver Module The Multi Channel Receiver module has structural architecture that instantiates and connects the correct numbers of single channel receivers and branch controllers The single channel serial receivers are connected to branch controllers and the branch controllers are then connected to the backbone controller See Figure 5 8 The number of channels and number of branches to instantiate is defined through generics c1k200 rst200 lill CHEN_vector serial_channels in data_out gt channel out gt write _req gt Figure 5 8 Entity for Channel Receiver Module clk200 Input areset Input serial_channel_in Input CHEN_vector Input data_out Output channel_out Output write_req Output Table 5 11 I O details for Channel receiver Module 5 7 3 Entity Single Channel Receiver 120 120 48 8 1 std_logic the clk200 frequency is 200 MHz std_logic asynchronous reset std_logic_vector 0 to num_of_channels LVDS serial channels from D RORCs std_logic_vector 0 to num_of_channels CHEN vector is a register in the Control and Stat
2. ses f es s_send_request tx req 1 tx_data request eventID cmd tx_ack 1 c1k40 rst40 force validate halt_validator new_eventid_av inbox_emty event_valid_int req timeout tx_ack num_of_channels neeevedee new_eventid_en inbox_read_req event_valid_out event_reset tx_req tx_data requestID retry_count LLELLLI Figure 5 30 Entity for EventID Control 34 Page BusyBox User Guide Port Name Bit n clk40 1 the clk40 frequency is 40 08 MHz rst40 1 std_logic synchronous reset force_validate 1 std_logic halt_validator 1 std_logic new_eventid_av 1 std_logic inbox_emty i std_logic event_valid_int 1 std_logic req_timeout 16 std_logic_vector 15 downto 0 tx_ack 1 std_logic new_evetid_en 1 std_logic inbox_read_req Output 1 std_logic event_valid_out Output 1 std_logic event_reset Output 1 std_logic tx_req Output 1 std_logic tx_data Output 8 std_logic_vector 7 downto 0 requestID Output 4 std_logic_vector 3 downto 0 retry_count Output 16 std_logic_vector 15 downto 0 Table 5 27 I O details for EventID Control I 5 12 5 Entity EventID Processor In this module all the verification occurs and based on the CEHN register it will continuously compare the event IDs and set each individual channel with 1 if match or 0 if mismatch in a register called EID
3. For more latest firmware relase and latest discussion about the BusyBox check out the wiki at https wikihost uib no ift index php Busy_Box_and_related 2 Page BusyBox User Guide 5 10 si 5 12 5 13 5 14 6 1 6 2 6 3 6 4 6 5 71 81 8 2 8 3 8 4 91 9 2 9 3 9 4 9 5 9 6 9 7 98 99 9 10 10 10 1 10 2 10 3 Table of content TABLE OF CONTENT INTRODUCTION Document History SYSTEM OVERVIEW BUSYBOX HARDWARE Xilinx Virtex IV FPGA DCS BUSYBOX FIRMWARE Introduction BusyBox top level wrapper Module digital_clock_manager Busylogic_top Module Reset_logic module DCS Bus Arbiter and Address Decoder Receiver Module Transmitter Module RX Memory Module RX Memory Filter Module Trigger Receiver Module Event ID Verification Module Busy Controller Module Control and Status Registers FUNCTIONAL VERIFICATION OF THE BUSYBOX FIRMWARE Introduction Support packages The RCU and DRORC emulator module Testbench execution flow Running the simulation in QuestaSim ModelSim BUSYBOX DCS BOARD in Setting up DCS board Firmware to use with BusyBox BUSYBOX COMMUNICATION BusyBox DRORC Communicatio TTCrx Communication DCS Communication LTU Communication GETTING STARTED WITH THE BUSYBOX Introduction SVN Repository and Project Setup Hardware Setup Logging on to the DCS boare RCU Shell Programming the FPGA Configuring the Firmware Monitoring the B
4. c1k40 rst40 ttcrx_rdy LO_trigger Lla_trigger L2a_trigger L2r trigger L2_timeout busy_triggermodule event_valid trig_timout fee_buffers available bel velba vend fee_buffers_used busy_out busy _time Figure 5 34 Entity for Busy Controller Module rst40 Input P clk40 Input 1 ttcrx_rdy Input 1 LO_trigger Input 1 L1a_trigger Input 1 L2a_trigger Input 1 L2r_trigger Input 1 L2_timeout Input sJ busy_triggermodule Input 1 event_valid Input 1 trig_timeout Input 16 fee_buffers_available Input 4 busy_out Output 1 fee_buffers_used Output 4 busy_time Output 32 Table 5 29 I O details for Busy Controller Module 5 14 Control and Status Registers std_logic synchronous resets std_logic the clk40 frequency is 40 08 MHz std_logic ttcrx_rdy out from dcs_ctrl7 physical line on the DCS RCU connector If not asserted it implies a physical problem with connection to the LTU or that the CTP is issuing a global reset via the TTCrx std_logic N A std_logic L1a_trigger output from trigger_receiver_busy_model Starts buffering data in Fee if L1a_trigger signal is asserted std_logic N A std_logic L1r_trigger output from trigger_receiver_busy_model Overwrites buffers in Fee if L2r_trigger signal is asserted std_logic L2_timeout output from trigger_receiver_busy_model Overwrites buffers in Fee if L2_timeout signal is asserted std_logic busy_triggermodule output from trigger_receiver_module st
5. regpoll sh channels I 9 9 Resetting the BusyBox To activate the global asynchronous reset of the Busy Box firmware both FPGAs run rcu sh fw r This will reset all registers in the Busy Box except for the block RAMs The configuration registers must be set again including channel registers Sending and Receiving messages to from the D RORCs 9 10 CTP Emulator When testing or debugging the BusyBox a trigger emulator can be used Open a terminal window in Linux Type ssh X Itu vme1 and enter the password when prompted Type vmecrate Itu bash 3 2 ssh X ltu vmel Scientific Linux CERN Release 3 0 8 SL ltu vmel s password Last login Thu Dec 18 15 28 56 2008 from iftmikro039165 klientdrift uib no This version of Scientific Linux CERN SLC3 is obsolete and no longer receives automatic security updates See http cern ch lLinux slc4 docs migration campaign for more information vme1 home ltu gt vmecrate ltu Use right mouse button to get help Figure 9 3 Example of login Then the VME menu is displayed Click Configuration and LTUinit Click Configuration and TTCreset Click CTP Emulator The CTP Emulator window pops up CTP emulator Sequence L2a seq Load sequence Sequencer editor Errors disabled Automatic START BC downscaling jx S s lt i lt lt i lt lt signal selection BC factor a Generate SW Start signal s of signals j1 Spacing ms 0 Chec
6. L1_latency time L1Msg_latency time L2Msg_latency time L1_ESR std_logic LI CIT std_logic L1_SwC std_logic L1_RoC std_logic_vector 3 downto 0 Ll Class std_logic_vector 49 downto 0 L2_ESR std_logic L2_CIT std logic L2_SwC std_logic L2_Cluster std_logic_vector 5 downto 0 L2_Class std_logic_vector 49 downto 0 BCID std_logic_vector 11 downto 0 OrbitID std_logic_vector 23 downto 0 end record sequence type A more detailed description of the trigger sequence parameters follow description A string of 80 characters that can be used to describe the sequence Default sequence This string will be printed to console when the sequence is executed LO L1A L1Msg during simulation runs L2AMsg LO_enable Include the LO trigger in the sequence true L1_enable Include the L1 trigger in the sequence true L1Msg_enable Include the L1 Message in the sequence true L2Msg_enable Include the L2 Message in the sequence true L2Accept true gt Level 2 Accept Message true false gt Level 2 Reject Message L1_latency Latency from rising edge of LO trigger to rising edge of L1 triggeron 5 3 us the L1Trig signal L1Msg_latency Latency from rising edge of LO trigger to the start bit of the L1 6 3 us Message on the serialB signal L2Msg_latency Latency from rising edge of LO trigger to the start bit of the L2 85 us Page 41 Message L1_ESR Level 1 Message content Enable Segemented Readout Oo
7. The purpose of the BusyBox is to let the Central Trigger Processor CTP know when the FEE s buffers are full by asserting a busy signal which prevents further issuing of triggers The BusyBox and D RORCs receive a unique event ID from the FEE after an event After a valid trigger sequence ends the BusyBox will ask the D RORCs if they have received the same event ID as the BusyBox did If they do not reply with the same ID it means data has not been shipped from the Fee to the D RORC hence the buffer in the Fee still holds event data The BusyBoxes are located in the DAQ counting rom and is a FPGA based system developed at the University of Bergen The first of three development phases was done by Anders Rossebg He designed the BusyBox hardware including the 19 rack case Then Magne Munkejord developed the firmware and PhD student Johan Alme contributed with the Trigger Receiver Module to make the firmware complete And finally a full test integration and commissioning was done by Rikard Bglgen and Magne Munkejord This User Guide is about the whole BusyBox system The intention is to give newcomers to the system an intuitive understanding without going too much in detail The first part of this user manual is an overview of the BusyBox Hardware Firmware DCS board and communication systems will be discussed The second part is how to interact with everything How to program and read registers in the FPGA to emulate triggers from an emulator
8. 15 0 Latest received DAQ Header 4 31 16 Latest received DAQ Header 5 15 0 Latest received DAQ Header 5 31 16 Latest received DAQ Header 6 15 0 Latest received DAQ Header 6 31 16 Latest received DAQ Header 7 15 0 Latest received DAQ Header 7 31 16 0 Rol enabled 1 Region of Interest announced ESR 2 Rol received 3 Within region of interest 4 7 Calibration SW trigger type RoC 8 Software trigger event 9 Calibration trigger event 10 Event has L2 Reject trigger 11 Event has L2 Accept trigger 0 Serial B Stop Bit Error 1 Single Bit Hamming Error Individually Addr 2 Double Bit Hamming Error Individually Addr 3 Single Bit Hamming Error Broadcast 4 Double Bit Hamming Error Broadcast 5 Unknown Message Address Received 6 Incomplete L1 Message 7 Incomplete L2a Message 8 Incomplete Rol Message 9 TTCrx Address Error not X 0003 10 Spurious LO 11 Missing Lo 12 Spurious L1 13 Boundary L1 Page 59 14 Missing L1 15 L1 message arrives outside legal timeslot Event_error 1 1 0 0x3053 R 16 L1 message missing timeout 17 L2 message arrives outside legal timeslot 18 L2 message missing timeout 19 Rol message arrives outside legal timeslot 20 Rol message missing timeout 21 Prepulse error 0 possible future use 22 L1 message content error 23 L2 message content error 24 Rol message content error Debug Latest received L1 Message Deb
9. 5 6 start questa modelsim cd to trunk simulation source project_setup tcl vsim tb_trigger_busybox add wave run all Some files only testbench files may fail compilation because they use some features from VHDL 2008 Set the compiler to use VHDL 2008 to compile these files Page 45 7 BusyBox DCS board Figure 7 1 PCB layout of DCS board 1 Optical input Input from LTU or CTP emulator 2 UART RS 422 connection 3 Connector DCS bus connector to BusyBox PCB 4 Ethernet Ethernet link to communicate with DCS board Table 7 1 Connectors on the DCS board 46 Page BusyBox User Guide 7 1 Setting up DCS board Firmware to use with BusyBox The DCS board firmware needs to be adapted for the BusyBox If the DCS board is not already modified it needs to be reprogrammed to fit the BusyBox The latest firmware is available here https wikihost uib no ift index php Electronics_for_the_Time_Projection_Chamber_ 28TPC 29 DCS_board_ firmware_for_TPC_and_PHOS Here a description of how to update the DCS board flash device is also given Page 47 8 BusyBox Communication This chapter discusses the how the BusyBox handles communication with the D RORCs 8 1 BusyBox DRORC Communication A robust serial communication has been developed for communication between the BusyBox and the D RORCs Serial 48 bit oriented bidirectional data transfer can be made at up to 8 1 1 Physical Layer
10. daq_header_extractor i_event_queue FIFOsync108x512 Core i_eventid_control eventid_control i_event_processsor event_processor 000 0 The Receiver module operates in the 200 MHz domain while the internal logic of the verification module runs in the 40 MHz domain Page 31 o i_drorc_inbox_buffer drorc_inbox_buffer Core 5 12 2 Entity Event_validator_top c1k200 clk40 rst40 DRORC_data_in DRORC_channel DRORC_data_en CHEN_vector DAQ_header_data buffered_events DAQ_read_counter force validate halt_validator req_ timeout fw_tx_ack bee bad ead ea EIDOK vector read_enable event_valid_out current_event_id most_recent_event_id requestID retry_count num of_eventids fw_tx_request fw_tx_data fw_tx_mask Waa a Figure 5 27 Entity for event_validator_top module rst40 Input d clk200 Input 1 clk40 Input 1 DRORC_data_in Input 48 DRORC_channel Input 8 DRORC_data_en Input 1 CHEN_vector Input 120 DAQ_header_data Input 33 buffered_events Input 4 DAQ_read_counter Input 4 force_validate Input 1 halt_validator Input 1 req_timeout Input 16 fw_tx_ack Input 1 EIDOK_vector Output 120 read_enable Output 1 event_valid_out Output 1 current_event_id Output 36 most_recent_event_id Output 36 requestID Output 4 retry_count Output 16 num_of_eventids Output 4 fw_tx_request Output 1 fw_tx_data Output 8 fw_tx_mask Output 120 Table 5 25 I O details for Event Validator std_logic synchronous reset
11. std_logic the clk200 frequency is 200 MHz std_logic the clk40 frequency is 40 08 MHz std_logic_vector 47 downto 0 std_logic_vector 7 downto 0 std_logic std_logic_vector 0 to num_of_channels std_logic_vector 32 downto 0 std_logic_vector 3 downto 0 std_logic_vector 3 downto 0 std_logic std_logic std_logic_vector 15 downto 0 std_logic std_logic_vector 0 to num_of_channels std_logic std_logic std_logic_vector 35 downto 0 std_logic_vector 35 downto 0 std_logic_vector 3 downto 0 std_logic_vector 15 downto 0 std_logic_vector 3 downto std_logic std_logic_vector 7 downto 0 std_logic_vector 0 to num_of_channels 32 Page BusyBox User Guide 5 12 3 Entity DAQ Header Extractor This module reads out the DAQ header also called CDH Common Data Header that the trigger receiver module generates and buffers The Trigger Receiver Module stores the DAQ header as 9 32 bit words in an internal FIFO Each word contains information about the received trigger sequence The DAQ Header Extractor reads out all 9 words and outputs selected fields of information in parallel Most importantly the EventID is extracted from the header The extracted information is to a FIFO The information is also forwarded to the Control and Status Register module cl1k40 DAQ rden rst40 extracting_event gt DAQ header data extracted_event_id gt gt DAQ_read_counter extracte
12. 0x200A DATA 0x0000 11200 Running trigger sequence number 1 11200 Sending Level 0 Trigger 16500 Sending Level 1 Trigger Time since sequence init 5300 ns 17500 Sending Level 1 Message Time since sequence init 6300 ns 96200 Sending Level 2 Accept Message Time since sequence init 85000 ns Trigger Receiver DAQ event FIFO Event Info 0xA9501800 Bit 11 L2 Accept received Bit 12 Include payload Event Error 0x00002000 Bit 13 Buondary L1 DAQ1 0x02000789 DAQ2 0x00123456 DAQ3 0x00000000 DAQ4 0x0100028E DAQ5 0x00000000 DAQ6 0x00000000 DAQ7 0x00000000 204850 ns Running trigger sequence number 2 204850 ns Sending Level 0 Trigger 210150 ns Sending Level 1 Trigger Time since sequence init 5300 ns 211150 ns Sending Level 1 Message Time since sequence init 6300 ns 289850 ns Sending Level 2 Accept Message Time since sequence init 85000 ns Trigger Receiver DAQ event FIFO Event Info 0xA9501800 JE E SE FE k k SE SE k SE k SE k k k k SE e SE SR k k e He SE 44 Page BusyBox User Guide DAQ1 DAQ2 DAQ3 DAQ4 DAQ5 DAQ6 DAQ7 Se e Fe ESE SE SE de de SEE Bit 11 L2 Accept received Bit 12 Include payload Event Error 0x00002000 Bit 13 Buondary L1 0x02000789 0x00123456 0x00000000 0x010000D0 0x00000000 0x00000000 0x00000000 6 5 Running the simulation in QuestaSim ModelSim 1 2 3 4
13. 39 4 Table 5 2 Default values for generic parameters for BusyBox wrappers clock_Ivds_P Input 1 std_logic clock_Ivds_N Input 1 std_logic areset_n Input 1 std_logic serialB_in Input 1 std_logic L1Trig_P Input 1 std_logic L1Trig_N Input 1 std_logic serial_rx_p Input 120 std_logic_vector 0 to num_of_channels serial_rx_n Input 120 std_logic_vector 0 to num_of_channels dcs_adr Input 16 std_logic_vector 15 downto 0 dcs_strobe_n Input 1 std_logic dcs_RnW Input 1 std_logic intercom_busy Input Output 1 std_logic serial_tx_p Output 1 std_logic_vector 0 to num_of_channels serial_tx_n Output 1 std_logic_vector 0 to num_of_channels dcs_data Bidirectional 16 std_logic_vector 15 downto 0 dcs_ack_n Output 1 std_logic BUSY_1 Output 1 std_logic BUSY_2 Output 1 std_logic leds Output 13 std_logic_vector 1 to 13 Table 5 3 I O details for BusyBox FPGA Modules 5 3 Module digital_clock_manager This core has been generated by the Xilinx tool Architect Wizard available through the CoreGen GUI It a single DCM configured to deskew and output two clock signals generated from the incoming clock The incoming clock from the DCS board is approximately 40 MHz The DCM multiplies this clock signal by 5 to generate a 200 MHz output used in the design The 40MHz and 200 MHz are routed to global clock buffers that drive global clock nets to distribute the clock signals around the chips The DCM is setup in a system synchronous
14. 5 1 The Ethernet connector on the DCS card is a 6 pin Milli Grid crimp housing and the cable connections can be found here http www kip uni heidelberg de ti DCS Board current mechanic DCS160Ethernet01 htm 9 4 Logging on to the DCS board The DCS board mounted on the BusyBox is the easiest way to interact with the firmware From her registers can be accessed and new firmware can be programmed to the Virtex 4 chip s Interfacing with the DCS board is done either trough Ethernet or UART but Ethernet is the preferred way The DCS board runs on a lightweight version of Linux and is access through a SSH shell For Microsoft Windows users a SSH client can be used like the PuTTY SSH client Open a terminal window on a Linux computer or a SSH client on a Windows computer To login type ssh root dcsxxxx The xxxx is substituted with the number on the DCS card Then you will be prompted for a password To get the password contact Page 53 9 5 RCU Shell The RCU Shell is a small command line software for communicating with the firmware on the BusyBox It is started by simply typing rcu sh at the command line This will bring you to the shell mode where different types of commands can be executed for example for reading and writing registers in the BusyBox firmware Type h and press enter to see available commands in the RCU shell 9 6 Programming the FPGA The FPGA s will not be programmed automatically when the box
15. Category 5 cables with RJ 45 connectors are the communication channel between the BusyBox and D RORCs Built in I O blocks in the Virtex 4 FPGA is set to I O standard specified as LVDS_25 and DIFF_TERM attribute is set to true Pin Pair Wire Color la 3 1 white green 2 3 2 GEE green 3 2 11 0 white orange BusyBox D RORC 41 2 CHD e RX 1 3 Ta 5 1 1 O white blue ia k a 6 2 2 B orange TX 6 2 RX za h white brown la a 2 ED brown Figure 8 1 RJ 45 pin connection scheme 8 1 2 Data Link Layer Serial data is transmitted with NRZ encoding at a 40 MHz bit rate Three 16 bit data packages are sent from the D RORCs to the BusyBox on request from the BusyBox The packages are concatenated to one 48 bit message in the BusyBox receiver module The messages from the BusyBox to the D RORCs are 16 bit long The receiver samples the incoming serial data at 200 MHz into a 98 bit shift register When bits 1 to 8 are 00001111 and bits 96 to 98 are 000 in the shift register the capture condition is valid and the data is passed to the majority vote Bit value O O 0 0 1 2 1 4 x x x O Oo O Table 8 1 Capture condition for a data frame One bit period is 5 cycles and the three middle bits are run through a majority gate The captured data word is 17 bit long with the LSB as the parity bit If there is any parity error or timeout error during the data capture data is discarded The timeout clock counts 110 cycles from th
16. To DCS bus interface Figure 5 20 Illustration of the RX Memory module From Magne I 5 9 1 Entity RX Memory Module gt c1k200 mem_pointer gt gt c1k40 module_data_in gt gt rst200 module_data_out gt data_in module_address gt data_in_en module_rnw gt module_en Figure 5 21 Entity for RX Memory Module Port Name Direction Bit Desc clk200 Input 1 std_logic the clk200 frequency is 200 MHz clk40 Input 1 std_logic the clk40 frequency is 40 08 MHz rst200 Input 1 std_logic synchronous reset rst40 Input 1 std_logic synchronous reset data_in Input 64 std_logic_vector 63 downto 0 data_in_en Input 1 std_logic mem_pointer Output 10 std_logic_vector 9 downto 0 module_data_in Output 16 std_logic_vector 15 downto 0 module_data_out Output 16 std_logic_vector 15 downto 0 module_address Output 12 std_logic_vector 11 downto 0 module_rnw Output 1 std_logic module_en Output 1 std_logic Table 5 22 I O details for RX Memory Module Page 27 5 10 RX Memory Filter Module The RX Memory filter can be used to filter which messages from specific channels will trigger the write enable signal form the RX Memory Module Each message from the Receiver Module will have an 8 bit channel number appended to it Each individual bit of this 8 bit word can be compared with bits in a register in the RX Memor
17. available for the Event processor which compares the event ID The Event Processor has a register called EIDOK Event ID OK and together with the CHEN vector it compares the two event IDs from the Event ID Queue module and the D RORC Inbox buffer If the ID matches the verification gate will assert an event verified signal An overview of the ID verification model is shown in The BusyBox has no direct communication with the FEE and keeps track of available buffers by communicating with the D RORCs The Trigger System sends triggers to the BusyBox and the FEE Figure 3 1 cs s event_validator_top x T DAQ header daq_header_extractor eventid_controi event valid ctrl 4 2 553 7 2 Cis a2 3 S Iri Y l lt i event_queue event id gt event_processor j lt DRORC messages drorc_inbox_buffer DRORC messages gt clk200 domain clk40 domain CHENS Figure 5 26 Illustration of the structure of event_validator_top module The eventid_control block controls the flow of new eventIDs from the event_queue and DRORC messages from the drorc_inbox_buffer to the event_processor It is also commands the TX controller to transmit requests to the DRORCs The event_processor block determines when the current event has been verified validated 5 12 1 Event_validator_top VHDL Entity Hierarchy e Event_validator_top i_daq_header_extractor
18. configuration This means that the clock is fed back to the DCM after it has gone through the clock distribution network The DCM will regulate the phase of its output clocks so that 1 Number of channels implemented is configurable This is an input on FPGA1 and an output on FPGA1 It does not exist in the busybox_fpga1_solo wrapper z Only exists on FPGA1 Page 13 the feedback clock s rising edge and incoming s clock rising edge are aligned This is done to compensate for the delay of the clock distribution network in the chip This configuration ensures that the chip FPGA is clocked synchronously with the rest of the system other synchronous elements During startup of the FPGA right after the configuration data has been loaded the internal circuits of the DCM will try to lock on the incoming clock signal This is an operation that might take several thousand clock cycles to complete and may fail if the incoming clock contains glitches and or sporadic behavior The clocks supplied by the DCM are not reliable until the DCM has acquired lock A dedicated output signal named lock from the DCM indicates when lock has been acquired This signal is forwarded to the reset logic which will hold the design in reset until the lock signal is deasserted The wizard that generates the DCM core does not support enabling of the DIFF_TERM attribute of the differential global clock input buffer IBUFGDS Therefore the clock input buffer is dis
19. details for Transmitter Module I 5 8 3 Entity Serial Encoder gt c1k40 busy_out gt rst40 serial_out gt data_in gt data_wren Figure 5 19 Entity for Serial Encoder Direction Description Input 1 std_logic synchronous reset Input A std_logic the clock_in frequency is 200 MHz data_in Input 1 std_logic_vector data_wren Input 3 std_logic busy_out Output 1 std_logic serial_out Output 1 std_logic Table 5 21 I O details for Serial Encoder I 5 9 RX Memory Module The BusyBox can store up to 1024 D RORC messages from the Receiver module in the RX Memory module Four BRAM modules are instantiated in the FPGA and can be accessed from both clock domains Data from the Receiver module is 56 bit and is written into memory at the address given by a 10 bit counter The DCS bus is limited to read 16 bit at a time and needs four read operations to get the whole word from memory The RX Memory module can be written to by the DCS bus for testing and verification purposes The Receiver module operates in the 200 MHz domain while the internal logic of the BusyBox runs in the 40 MHz domain 26 Page BusyBox User Guide Data from Receiver module 56 bit Address generator 10 bit counter ahaaa se 4 Virtex 4 Virtex 4 Virtex 4 Virtex 4 BRAM 40 MHz n MUX DCS address 11 3 DCS address 1 0
20. enable Input 1 std_logic Input 1 std_logic serial signal from D RORC parity_error Output 1 std_logic data_av Output 1 std_logic data_out Output 16 std_logic_vector 15 downto 0 data from D RORC Table 5 13 I O details for Serial Decoder If the Serial Decoder is enabled it listens to the transmission line for serial data Each data word is packed into a frame and encoded on the serial signal as illustrated in i f signal l sampes 11 1111111100000iddd ddipppppio000011111 phase idleline startbt1 startbit2 16 data bits partybit stopbit idle line Figure 5 11 When the line is idle it pulled to logic 1 A frame starts with two start bits to create 1 0 transition The decoder looks for this transition to lock on to the data frame Each bit is sampled 5 times This is necessary to detect the bit phase of the incoming serial bit stream Once the 1 0 transition of the start bits are found a state machine in the decoder triggers and start capturing data The state machine picks the sample that is believed to be the middle of each bit by counting samples at the local clock rate After 16 data bits have been sampled a parity bit and a stop bit are sampled Both must have the correct logic value before the frame is accepted and data forwarded The parity bit is a even parity generated by XOR ing the data bits as they are received The stop bit is always logic 0 signal i i sampes 111 11111100
21. has to FIFOs for eventIDs The first is used for storing EventIDs as they are triggered and the second to hold EventiDs that have been transmitted to the DRORCs Internally the module generates random times from 100 to 500 us that it will wait before moving an EventID 42 Page BusyBox User Guide from the first FIFO to the second The random time emulates the variance in event data sizes The concept is illustrated in Figure 6 2 RCU emulation Random DRORC emulation transit time EE DRORC eventID Serial TX a eventiD from wigger Gist IFO fp EVentiD my queue Controller second FIFO Serial RX l4 Figure 6 2 Illustration of the RCU and DRORC emulation The number of EventIDs stored in the FEE buffer corresponds to Multi Event Buffers MEBs in use on the real system This number is monitored by the testbench to check that it never exceeds the specified maximum numbers events that can be stored on the FEE The DRORC emulator takes care of the communications with the BusyBox Requests commands from the BusyBox are handled in the same manner as for the real DRORC Serial receiver and transmitter modules are used for communication with the BusyBox 6 4 Testbench execution flow The process tb_main controls the simulation It begins by setting some signals to default values and resetting the UUT and any support modules At line 7 the dcm_lock signal is asserted to indicate to the busylogic_
22. messages 8 1 4 Sequence Diagrams Start i z7 ra XK Reset ststus registers J A No Tep lt EventiD in Queue gt yes Pop EventID from Queue N Generate RequestiD fe R Request EventiD trom D RORCs je Start timer i yA Process incomming messages Update status registers Yes lt lt lt Event Valid gt Ake No lt Retry gt limit gt _ y ves s Update error registers 4 Wait for DCS intervention Store received request ID Pop eventlD from queue Page 49 Figure 8 2 Sequence diagram for the BusyBox on the left and D RORC on the right v r Update output buffer Y y i Transmit output buffer to BusyBox _ A See chapter 4 5 and 4 6 for more information on how the sending and receiving hardware modules work 50 Page BusyBox User Guide 8 2 TTCrx Communication The trigger information from the LTU is acquired by the TTC receiver chip TTCrx on the DCS board The Trigger Receiver module on the BusyBox decodes the information into three parts Channel A Channel B and BC Channel A LO and L1 triggers are transmitted on Channel A using LVDS from the TTCrx chip Channel B Channel B transmits two types of messages Broadcast messages and individual address messages The broadcast message is decoded into a pre pulse bit an event count reset bit an
23. two main tasks keep track of available buffers and maintain a past future protection If the buffers are full or a L1 trigger is issued the BusyBox asserts a busy signal to the CTP which will halt further triggers The busy is then removed if these conditions are no longer true The BusyBox has no direct communication with the FEE and keeps track of available buffers by communicating with the D RORCs The Trigger System sends triggers to the BusyBox and the FEE Figure 3 1 below illustrates the BusyBox place in the readout chain DAQ __ BusyBox a D RORC FEE Trigger System pa Page 5 Data Storage Counting Room Experiment Hall Figure 3 2 Illustration of the data flow for the BusyBox system The BusyBox and D RORCs are placed in the counting rooms above the experiment hall 6 Page BusyBox User Guide 4 BusyBox Hardware This chapter discusses the hardware and some key components Figure 4 1 BusyBox PCB Page 7 1 LED indicators Indicates numbers of buffers used 2a LEMO contact LVDS busy signal from FPGA 1 2b LEME contact LVDS busy signal from FPGA 1 3 LED indicators 4 RJ 45 contact RJ 45 contacts for D RORCs 5 Mezzaine connectors Mezzaine card holders to additional RJ 45 connectors 6 Resistors FPGA1 configuration resistors Sets the configuration mode to 8bit SelectMAP slave 7 8a FPGA 1 X
24. wait until busy out 0 30 run_sequence clk40 trigger_sequencel Litrig serialB 31 wait until busy out 0 32 run_sequence clk40 trigger_sequencel Litrig serialB 33 wait until busy out 0 34 run_sequence clk40 trigger_sequencel Litrig serialB 35 wait until busy out 0 36 run_sequence clk40 trigger_sequencel Litrig serialB 37 wait until busy out and BusyBox_MEB cnt 0000 38 clk_en lt false 39 wait Next the process starts sending trigger sequences by calling the run_sequence procedure A wait statement ensures that BUSY is not asserted before sending a trigger sequence The simulation will end when all statements in this process have completed The final statements wait until the BUSY has been de asserted and the BusyBox MEB count has reached 0 Then the clocks are disabled and the process goes to sleep During the entire simulation a concurrent assert statement makes sure that the MEB counts from all the rcu_drorc_emulator modules are never higher than the MEB count of the BusyBox This is important as it tests whether the BusyBox will toggle the BUSY output correctly so that the FEE cannot experience buffer overflows during operation assert RCU_MEB cnt_array i lt BusyBox_MEB cnt report Possible Buffer overflow detected severity warning Below is an excerpt from the output console when running the testbench 10400 bb_bus_ write ADDR 0x2009 DATA 0x0004 10650 bb_bus_ write ADDR
25. 000 ddd ddipppppio000011111 phase idleline startbit statbt2 16 data bits paritybt stopbit idle line Figure 5 11 Encoding of serial data on transmission line 5 7 5 Entity Branch Controller The Branch Controller reads data from up to 16 Single Channels Receiver s and feed the data to the backbone controller It scans the receivers for data available flag and copies the data to a buffer when the flag is raised The branch controller will hold until the Backbone Controller has verified that it has read the message Page 21 c1k200 read_ack_vector gt rst200 data_out gt data_in_array count_out gt data_av_vector data_av gt read_ack Figure 5 12 Entity for Branch Controller Port Name Dire n B Des n clk200 Input 1 std_logic the clk200 frequency is 200 MHz Rst200 Input 1 std_logic synchronous reset data_in_array Input 16 receiver_busy_array 0 to 15 data_av_vector Input 16 std_logic_vector 0 to 15 1 when data is available read_ack Input 1 std_logic from backbone controller read_ack_vector Output 16 std_logic_vector 0 to 15 data_out Output 48 std_logic_vector 47 downto 0 48 bit data count_out Output 4 std_logic_vector 3 downto 0 counter to keep track of serial channel being scanned data_av Output 1 std_logic 1 when data from serial receiver is ready to be sent Table 5 14 I O details for
26. 2 Groove Folder Synchronization gt Export E Add to new encrypted archive EER http tortoisesvn net downloads Add to existing encrypted archive Import E Adobe Drive cst E ip Sctings TortoiseSVN is a shell extension that is integrated into Send ti gt 2 Help the Windows explorer So after you have downloaded Met Kopier and installed TortoiseSVN open the explorer and ag snarvei right click on any folder you like to bring up the Siet context menu where you will find all TortoiseSVN fera Egenskaper commands 2 Figure 9 1 TortoiseSVN example Select TortoiseSVN and Create repository here Then you right click on the folder again and select import The URL for the repository is https svn ift uib no svn busybox_firmware Username and password can be acquired by contacting the microelectronics division at IFT UIB 52 Page BusyBox User Guide 9 3 Hardware Setup Ethernet CTP Emulator BusyBox PC Figure 9 2 Principle hardware setup for experimenting with the BusyBox The BusyBox is connected to the Ethernet and the CTP Emulator The physical distance between the two devices are limited by the optical cable and the PC can be anywhere but for practical reasons it should be in near proximity to the others The optical fibre cable from the CTP Emulator goes into 1 in figure 5 1 The Ethernet cable goes into 4 in figure
27. 3 RCU4 Page 61 71 0x2147 C11 RCUS 59 OxC13b A11 RCUS 72 0x2148 C12 RCUO 60 0xC13c A12 RCUO 73 0x2149 C12 RCU1 61 OxC 13d A12 RCU1 74 0X214a C12 RCU2 62 0xC13e A12 RCU2 75 0x214b C12 RCU3 63 OxC13f A12 RCU3 76 0x214c C12 RCU4 64 0xC 140 A12 RCU4 77 0x214d C12 RCUS 65 OxC141 A12 RCUS 78 0x214e C13 RCUO 66 OxC142 A13 RCUO 79 0x214f C13 RCU1 67 0xC143 A13 RCU1 80 0x2150 C13 RCU2 68 0xC144 A13 RCU2 81 0x2151 C13 RCU3 69 OxC145 A13 RCU3 82 0x2152 C13 RCU4 70 OxC 146 A13 RCU4 83 0x2153 C13 RCUS 71 OxC 147 A13 RCU5 84 0x2154 C14 RCUO 72 0xC148 A14 RCUO 85 0x2155 C14 RCU1 73 0xC149 A14 RCU1 86 0x2156 C14 RCU2 74 0xC14a A14 RCU2 87 0x2157 C14 RCU3 75 0xC14b A14 RCU3 88 0x2158 C14 RCU4 76 0xC14c A14 RCU4 89 0x2159 C14 RCUS 77 0xC14d A14 RCU5 90 0X215a C15 RCUO 78 OxC14e A15 RCU0 91 0x215b C15 RCU1 79 OxC14f A15 RCU1 92 0x215c C15 RCU2 80 0xC150 A15 RCU2 93 0x215d C15 RCU3 81 0xC151 A15 RCU3 94 0x215e C15 RCU4 82 OxC152 A15 RCU4 95 0x215f C15 RCUS 83 OxC153 A15 RCU5 96 0x2160 C16 RCUO 84 OxC 154 A16 RCUO 97 0x2161 C16 RCU1 85 OxC155 A16 RCU1 98 0x2162 C16 RCU2 86 OxC 156 A16 RCU2 99 0x2163 C16 RCU3 87 0xC157 A16 RCU3 100 0x2164 C16 RCU4 88 OxC158 A16 RCU4 101 0x2165 C16 RCUS 89 OxC 159 A16 RCUS 102 0x2166 C17 RCUO 90 OxC 15a A17 RCUO 103 0x2167 C17 RCU1 91 0xC15b A17 RCU1 104 0x2168 C17 RCU2 92 OxC15 A17 RCU2 105 0x2169 C17 RCU3 93 OxC 15d A17 RCU3 106 0X216a C17 RCU4 94 OxC15e A17 RCU4 107 0x216b C17 RCUS 95 OxC15f A17 RCU5 Table 10 3 Li
28. 7 18 Busy receiving sequence 19 Not Used 23 20 CDH version onan 0x2 Module reset 0x3002 T Reset Module Rol_Config1 15 0 0x3004 RW Rol Definition Bit 15 0 Rol_Config1 1 0 0x3005 RW Rol Definition Bit 17 16 Rol_Config2 15 0 0x3006 RW Rol Definition Bit 33 18 Rol_Config2 1 0 0x3007 RW Rol Definition Bit 35 34 Reset_Counters 0x3008 T Write to this registers will reset the counters in the module Issue_TestMode 0x300A T Debug Issues testmode sequence Note that serialB channel input MUST be disabled when using this feature L1_Latency 15 0 0x300C RW 15 12 Uncertainty region N default value Ox2 50 ns 11 0 Latency from LO to L1 default value 0x30D4 5 3 us L2_Latency 15 0 0x300E RW 15 0 Max Latency from BCO to L2 L2_Latency 15 0 0x300F RW 31 16 Min Latency from BCO to L2 PrePulse_Latency 7 0 0x3010 RW 7 Legend W write R read T write trigger not physical registers 58 Page Rol_Latency 15 0 Rol_Latency 15 0 L1_msg_latency 15 0 L1_msg_latency 15 0 Pre_pulse_counter 15 0 BCID_Local 1 1 0 LO_counter 15 0 L1_counter 15 0 L1_msg_counter 15 0 L2a_counter 15 0 L2r_counter 15 0 Rol_counter 15 0 Bunchcounter 1 1 0 hammingErrorCnit 15 0 hammingErrorCnt 15 0 ErrorCnt 15 0 ErrorCnt 15 0 Buffered_events 4 0 DAQ_Header01 15 0 DAQ_Header01 15 0 DAQ_Header02 15 0 DAQ_Header02 15 0 DAQ_Header03 15 0 DAQ_Header03 15 0 DAQ_Header04 15 0 DAQ_Header04 15 0 DA
29. Branch Controller I 5 7 6 Entity Backbone Controller The Backbone Controller reads data from up to 8 Branch Controller s and writes the data to the RX Memory module and the D RORC inbox buffer in the Event Validator Top module c1k200 read_ack_vector gt rst200 data_out gt data_in_array count_out gt count_in_array write_req gt data_av_vector Figure 5 13 Entity for Backbone Controller iret Input std_logic the clk200 frequency is 200 MHz 1 rst200 Input 1 std_logic synchronous reset data_in_array Input 8 receiver_bus_array 0 to 7 work busylogic_pkg count_in_array Input 8 count_array 0 to 7 work busylogic_pkg read_ack_vector Output 8 std_logic_vector 0 to 7 data_out Output 48 std_logic_vector 47 downto 0 48 bit data count_out Output 8 std_logic_vector 7 downto 0 data_av_vector Output 8 std_logic_vector 0 to 7 write_req Output 1 std_logic Table 5 15 I O details for Backbone Controller I 5 8 Transmitter Module 22 Page BusyBox User Guide The transmitter module transmits serial data to the D RORCs and consists of a controller a serial decoder and a masking vector A message register and a channel register are available for the DCS bus module and Event ID Verification module Data from the message register will be loaded into the serial encoder and the masking vector will be created based on the channe
30. FMD and EMCal sub detectors and it is an FPGA based device It will verify the transfer of event data from the sub detectors Front End Electronics FEE to the Data Acquisition system DAQ The BusyBox also keeps track of free buffers in the FEE If the buffers are full or a collision is detected the BusyBox will flag a busy signal to a Central Trigger Processor CTP which halts further triggers from being issued Interaction with the BusyBox is done through the DCS board either via Ethernet or UART 4 Page BusyBox User Guide 3 System Overview The BusyBox is a part of the data acquisition in four of the ALICE sub detectors namely TPC PHOS FMD and EMCal The latter is currently in development There are some minor differences between the BusyBoxes for each sub detector because of the different numbers of D RORCs they use TPC 216 5 units PHOS 20 unit FMD 24 unit EMCal 3 1 unit Table 3 1 Number of D RORCs per detector Data acquisition in ALICE is trigger based and is controlled by a Central Trigger Processor CTP The CTP distributes a trigger sequence starting with a LO trigger when it senses a collision Then depending on the quality of the collision a L1 followed by an L2a or L2r trigger is issued by the CTP via the LTU The TPC FEE starts buffering data upon receiving a L1 trigger and PHOS a LO trigger The FEE on the four sub detectors can buffer 4 or 8 events depending on number of samples configured So the BB has
31. Input std_logic serialBchannel Input std_logic read_enable Input std_logic data_in Input std_logic_vector 15 downto 0 addr Input std_logic_vector 11 downto 0 rnw Input std_logic module_enable Input std_logic FEE_reset Output std_logic N A busy Output std_logic cal_pre_pulse Output std_logic N A start_of_run Output std_logic N A end_of_run Output std_logic N A event_reset Output std_logic N A bunch_reset Output std_logic N A bunchcnt_overflow Output std_logic N A LO_trigger Output std_logic L1a_trigger Output std_logic L2a_trigger Output std_logic L2r_trigger Output std_logic L2_timeout Output std_logic DAQ_header_out Output std_logic_vector 32 downto 0 read_counter_out Output 4 std_logic_vector 3 downto 0 buffered_events Output 4 std_logic_vector 3 downto 0 data_out Output 16 std_logic_vector 15 downto 0 30 Page BusyBox User Guide Table 5 24 I O details for Trigger Receiver Module 5 12 Event ID Verification Module The Trigger Receiver module s FIFO is constantly monitored by the Event ID Verification module Data from an L2a L2r or L2 timeout trigger is stored in the CDH format in the FIFO and will be read out by the Event ID Queue module The event controller then requests the Transmitter module to read out the data and send it to the D RORCs The Receiver module forwards D RORC data to the D RORC Inbox Buffer The Inbox operates in both frequency domains and makes the data
32. L1 CIT Level 1 Message content Calibration trigger flag Oo L1_SwC Level 1 Message content Software trigger Oo L1_RoC Level 1 Message content ReadOut Chamber 0000 L1_Class Level 1 Message content Level 1 Class trigger state flag others gt 0 L2_ESR Level 2 Message content Enable Segmented Readout Oo L2_CIT Level 2 Message content Calibration trigger flag Oo L2_SwC Level 2 Message content Software trigger flag Oo L2_Cluster Level 2 Message content Cluster trigger flag others gt 0 L2_Class Level 2 Message content Level 2 Class trigger flag others gt 0 BCID Level 2 Message content Bunch Crossing ID X 789 OrbitID Level 2 Message content Orbit ID X 123456 e Itis a required relationship that L1_latency lt L1Msg_latency lt L2Msg_latency e The BCID and OrbitID values combined make up the eventID e Message content entries besides the eventID are not relevant for the BusyBox operation e A constant with default values for all parameters is defined in the busybox_tb_pkg This constant can be used as init value to instantiate a record with default values Refer to documentation for the ALICE trigger system for more information on the message contents Procedure for executing a sequence and driving the L1Trig and SerialB signals procedure run_sequence signal clk in std_logic constant seq in sequence type signal Litrig out std logic signal serialb out std logic The procedure produc
33. OK A verification gate will flag an event verified signal if either the CHEN register is disabled or all channels where checked in the EIDOK register c1k40 rst40 trigger_eventid DRORC_message CHEN_vector local_requestID event_reset TISTE EIDOK vector event_valid tx mask Figure 5 31 Entity for EventID Processor Port Name clk40 1 std_logic the clk40 frequency is 40 08 MHz rst40 1 std_logic synchronous reset trigger_eventid 36 std_logic_vector 35 downto 0 DRORC message 56 std_logic_vector 55 downto 0 CHEN_vector 120 std_logic_vector 0 to num_of_channels local_requestID 4 std_logic_vector 3 downto 0 event_reset Input 1 std_logic EIDOK_vector Output 120 std_logic_vector 0 to num_of_channels tx_mask Output 120 std_logic_vector 0 to num_of_channels event_valid Output 1 std_logic Page 35 Table 5 28 I O details for EventID Processor 5 13 Busy Controller Module The busy_controller module is responsible for generating the BUSY signal It does this by evaluating inputs from other modules and counting occupied Multi Event Buffers MEB in the FEE There are four conditions that sets the busy signal high and only one have to be true TTCrx_ready gt MEB used MEB limit Trigger Receiver Busy BUSY LO Timeout Figure 5 32 BUSY generation 1 The TTCrx ready ttcrx_rdy is added to the BusyBox
34. Q_Header05 15 0 DAQ_Header05 15 0 DAQ_Header06 15 0 DAQ_Header06 15 0 DAQ_Header07 15 0 DAQ_Header07 15 0 Event_info 1 1 0 Event_error 15 0 BusyBox User Guide 0x3012 0x3013 0x3014 0x3015 0x3016 0x3018 0x301A 0x301C Ox301E 0x3020 0x3022 0x3024 0x3026 0x302C 0x302D 0x302E 0x302F 0x3040 0x3042 0x3043 0x3044 0x3045 0x3046 0x3047 0x3048 0x3049 0x304A 0x304B 0x304C 0x304D 0x304E Ox304F 0x3050 0x3052 DIDDDDDIIDIDIDDDDID DdD DdD ddd d DI 15 0 Max Latency from BCO to Rol msg 81 16 Min Latency from BCO to Rol msg 15 0 Max Latency from BCO to L1 msg 15 0 Max Latency from BCO to L1 msg Number of decoded pre pulses Number of bunchcrossings at arrival of L1 trigger Number of LO triggers Number of L1 triggers Number of successfully decoded L1 messages Number of successfully decoded L2a messages Number of successfully decoded L2r messages Number of successfully decoded Rol messages Debug Number of bunchcrossings 15 0 Number of single bit hamming errors 31 16 Number of double bit hamming errors 15 0 Number of message decoding errors 31 16 Number of errors related to sequence and timeouts Number of events stored in the FIFO Latest received DAQ Header 1 15 0 Latest received DAQ Header 1 31 16 Latest received DAQ Header 2 15 0 Latest received DAQ Header 2 31 16 Latest received DAQ Header 3 15 0 Latest received DAQ Header 3 31 16 Latest received DAQ Header 4
35. _RnW Input 1 std_logic 1 read and 0 write dcs_addr Input 16 std_logic_vector 15 downto 0 address module and submodule register dcs_data Inout 16 std_logic_vector 15 downto 0 bi directional data line dcs_ack_n Output 1 std_logic the asynchronous handshake is done with ACK_N from the busy board 16 Page BusyBox User Guide module_data_array Output 7 std_logic_vector 0 to num_of_modules 1 communication with modules module_en_array Output 7 std_logic_vector 0 to num_of_modules 1 communication with modules module_address Output 12 std_logic_vector 11 downto 0 communication with modules module_RnW Output 1 std_logic communication with modules Table 5 9 I O details for DCS Bus Arbiter and Address Decoder 5 7 Receiver Module Serial data from the D RORCs are handled by the receiver module and up to 120 single channels can be implemented in one FPGA TPC 120 96 PHOS 20 N A FMD 24 N A EMCal 3 N A Table 5 10 Numbers of channels per detector pr FPGA In order to implement error tolerance the 48 bit word from the D RORC is sampled in a 16 bit data frame A state machine in the Single Channel Receiver module reads out the data word one word after another when the serial decoder flags that data is ready to be sent A countdown timer in the state machine discards the data if the strict timing between data readout is compromised In that case the next word is then considered the first in the readou
36. _logic 120 std_logic_vector 0 to num_of_channels 16 std_logic_vector 15 downto 0 1 std_logic 1 std_logic a std_logic 4 std_logic_vector 3 downto 0 120 std_logic_vector 0 to num_of _channels a std_logic a std_logic 16 std_logic_vector 15 downto 0 Table 5 4 0 details for BusyBox Top Module 5 5 Reset_logic module This module implements some simple reset logic to generate proper reset signals to the design The reset signals will be asserted asynchronously whenever the DCM s locked signal is low In other words the design will not activate before the DCM locks on the incoming clock After the DCM achieves lock it will assert the lock signal The reset logic implements a shift register that is used to delay a synchronous release of the reset signals Reset signals for both clock domains are generated This is done to let the synthesis tools employ register duplication to reduce fanout and routing delay of the resets in both clock domains Generic Name Type g_rst_length Comment Page 15 natural Sets the time in number of clock clk40 cycles before the resets are released Table 5 5 Tabel of generic parameters for reset_logic module Port Name Direction Type Comment clk200 in std_logic 200 MHz clock input clk40 in std_logic 40 MHz clock input clk_lock in std_logic acts active low asynchronous reset rst200 out std_logic synchronous reset for the 200 MHz cloc
37. abled in the wizard and instead the input buffer is instantiated in the BusyBox top level wrapper files where the DIFF_TERM attribute is enabled This is essential for the design to operate reliable otherwise the DCM may not lock on the incoming reference clock and the internal clock signals will be full of glitches and spurious behavior NOTE The differential termination could can also be enabled by constraints in the User Constraints File UCF gt CLKIN CLKO_OUT gt RST_IN CLKFX_OUT gt LOCKED_OUT Figure 5 4 Entity for digital_clock_manager 14 Page 5 4 Busylogic_top Module BusyBox User Guide The busylogic_top module is the common top level for all three firmware versions It has a structural architecture where all main modules are instantiated and connected 5 4 1 Entity for busylogic_top Module ee eS c1k200 c1k40 areset serialB_ in LiTfrig_ in channels in dcs_addr dcs_strobe_n dcs_RnwW ttcrx_rdy Figure 5 5 Entity for BusyBox top module clk200 clk40 areset serialB_in L1Trig_in channels_in dcs_addr dcs_strobe_n dcs_RnW ttcrx_rdy buffers_used channels_out busy_out dcs_ack_n dcs_data Input Input Input Input Input Input Input Input Input Input Output Output Output Output In Out buffers used channels out gt busy out gt dcs_ack_n gt dcs_data gt gt 1 std_logic 1 std_logic 1 std_logic 1 std_logic 3 std
38. ansmitter module o Serial encoder The Transmitter module is initiating the serial encoder and setting the masking vector 5 8 2 Entity Transmitter module The Transmitter module is initiating the serial encoder and setting the masking vector A 16 bit register can be accessed from the DCS bus as shown in figure 5 15 The register contains a message register and a channel register dcs_tx_channel dcs_tx_data 15 8 7 0 Table 5 18 Bit map for DCS data The channel register selects which channel to be masked and unmasked the other channels If the value in the channels register does not specify a specific channel all channels are unmasked and the message is broadcasted to all channels A flag is raised in to indicate that data are available to be written from the DCS board to the message register A state machine see figure 5 16 in the controller sees the flag and starts loading data into the serial encoder and sets the masking vector The flag is removed and the procedure is executed The Event ID module sends a request to the transmitter module and the request is granted if there is no pending flag from the DCS bus The controller loads data and the masking vector from the EventID module Messages are Hamming coded in the Transmitter module in an 8 4 code applied to the 4 bit command word and request ID The receiver D RORC will discard data if it finds any errors The Hamming function is in the busylogic_pkg 24 Page 8 4 2 jos
39. c08 C08 C08 cog cog cog cog cog cog C10 C10 C10 C10 C10 C10 C11 C11 C11 C11 C11 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 BusyBox User Guide 0xC104 0xC105 0xC106 0xC107 0xC108 0xC109 0xC10a 0xC10b 0xC10c 0xC10d 0xC10e 0xC10f 0xC110 0xC111 0xC112 0xC113 0xC114 OxC115 OxC116 OxC117 0xC118 0xC119 OxC11a OxC11b OxC11 OxC11d 0xC11e OxC11f 0xC120 0xC121 0xC122 0xC123 0xC124 OxC125 OxC 126 OxC127 OxC128 0xC129 OxC12a OxC12b OxC12c OxC 12d OxC12e OxC 12f 0xC130 0xC131 0xC132 0xC133 0xC134 OxC135 0xC136 0xC137 0xC138 0xC139 0xC13a A02 A02 A03 A03 A03 A03 A03 A03 A04 A04 A04 A04 A04 A04 A05 A05 A05 A05 A05 A05 A06 A06 A06 A06 A06 A06 A07 A07 A07 A07 A07 A07 A08 A08 A08 A08 A08 A08 A09 A09 A09 A09 A09 A09 A10 A10 A10 A10 A10 A10 A11 A11 A11 A11 A11 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCU0 RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU3 RCU4 RCUS RCUO RCU1 RCU2 RCU
40. d a bounchcount reset bit The individual addressed messages are decoded into L1a L2a L2r and Rol messages BC The Bunch Count 40 Mh is distributed to the BusyBox logic and DCS board 8 3 DCS Communication Reading Writing i i i i i STROBEN y if rs _ _ St 1 H 1 i i i i R i i i i i i i i i i 4 i if ACK N i i y i 1 i i t i i i i i i j 7 7 7 7 7 ADDRESS y i i i i i i i i i DATA b f a p N T T i l h i Time Figure 8 3 Read and write transactions on the DCS bus From Magne Communication between the DCS board FPGA and the BusyBox motherboard FPGA is a 16 bit asynchronous handshake protocol The DCS card is the master and the FPGA is the slave A transaction starts with STROBE_N on the DCS and ACK_N from the BusyBox RnW indicates read write and when reading the BusyBox drives the data lines When writing the DCS board drives the data lines If an address given by the DCS board does not point to any module sub module in the BusyBox firmware the request is be ignored and the transaction times out 15 14 12 11 0 Table 8 5 Bit mapping of DCS bus address 8 4 LTU Communication The BusyBox has two LEMO contacts The busy signal is driven through a CERN certified LVDS driver via coaxial cables from the counting room to the LTU in the experiment hall Page 51 9 Getting started with the BusyBox This chapter will give some insight in how to get started wit
41. d_event_info gt gt DAQ_event_count extracted_event_error e Figure 5 28 Entity for EventID Extractor clk40 Input 1 std_logic the clock_in frequency is 40 08 MHz rst40 Input 1 std_logic synchronous reset DAQ_header_data Input 33 std_logic_vector 32 downto 0 33 bit word DAQ_read_counter Input 4 std_logic_vector 3 downto 0 counts through the 9 words in the CDH message DAQ_event_count Input 4 std_logic_vector 3 downto 0 counts numbers of buffered events in the FIFO DAQ_rden Output 1 std_logic extracting_event Output 1 std_logic status output extracted_event_id Output 36 std_logic_vector 35 downto 0 the extracted orbit end bunch cross IDs extracted_event_info Output 13 std_logic_vector 12 downto 0 extracted_event_error Output 25 std_logic_vector Table 5 26 I O details for EventID Extractor 5 12 4 Entity EventID Control The EventID Control module is a state machine that monitors and controls the event verification process Under is a state diagram of the controller halt_validator 0 amp amp event_valid_int 1 IL halt_validator 1 amp amp force_validate 1 _wait_for_messages timer_reset false j Page 33 New_eventid_av 1 halt_event_validator 1 Halt_validator 0 event_valid_int 0 8 timeout true Figure 5 29 State diagram for EventID Controller event i hnew_eventid_en 4
42. d_logic std_logic_vector 15 downto 0 programmable timeout following the start of a trigger sequence 10 us resolution Register 0x2008 in Control and Status Register Set Register to A 10 decimal to get 100 us timeout std_logic_vector 3 downto 0 Holds the numbers of buffers assumed on the FEE Register Ox2009 Default is 4 std_logic busy_out is asserted when busy conditions are met std_logic_vector 3 downto 0 std_logic_vector 31 downto 0 busy_time count numbers of clock cycles busy signal is asserted Page 37 This module has information about register and control signals available for the BusyBox See chapter 8 for more information 5 14 1 Entity Control and Status Register c1k40 rst40 module_en module_rnw module_address module_data_in mem_pointer event_count current_eventid most_recent_eventid requestID retry_count EIDOK vector busy_time Pee del rx_mem_matching_mask fee buffers available rx_mem_pattern trig_timeout req timout halt_validator force validate CHEN vector out module _data_out ee eesee Figure 5 35 Entity for Control and Status Registers clk40 Input 1 rst40 Input 1 module_en Input 1 module_rnw Input 1 module_address Input 12 module_data_in Input 16 mem_pointer Input 10 event_count Input 4 current_eventid Input 36 most_recent_eventid Input 36 requestID Input 4 retry_count Input 16 EIDOK_vector Input 120 busy_time Input 32 module_data_out Output 16 r
43. e 00 Holds DRORC message 47 32 All addresses in range where the 2 LSBs are 01 Holds DRORC message 31 16 All addresses in range where the 2 LSBs are 10 Holds DRORC message 15 0 All addresses in range where the 2 LSBs are 11 Holds DRORC channel number Value indicates where next message from DRORC will be written in RX Memory Number of Event Ids extracted from triggers and stored in FIFO Bit 35 32 of Event ID currently being matched Bit 31 16 of Event ID currently being matched Bit 15 0 of Event ID currently being matched Bit 35 32 of Event ID most recently received from triggers Bit 31 16 of Event ID most recently received from triggers Bit 15 0 of Event ID most recently received from triggers Number of clock cycles busy will be asserted after an LO trigger Note The busy will not be deasserted if the buffers are full Configuration register which indicates how many events can be stored in the buffers on the FEE When set to 1 the FSM that controls the Event ID matching will halt in a known state Writing 1 to this register when the FSM has been halted will cause the FSM to move on to the next Event ID Number of clock cycles 40 MHz domain to wait in between sending requests to the DRORCs Holds the Request ID the Busy Box uses to request Event Ids from the DRORCs Number of iterations the FSM has made while trying to match the current Event ID Bit 31 16 o
44. e first received bit before a timeout error is issued When three 16 bit data packages are received without error they are concatenated into a 48 bit package and stored 48 Page BusyBox User Guide it mA e Raa EA E il position P4 D4 D3 D2 P3 D1 P2 P1 X X X P1 P1 P2 x x x P2 P3 x x x P3 P4 P4 x x x x x x x Table 8 2 Hamming code table Messages from the BusyBox to the D RORCs are Hamming encoded with an 8 4 code applied and sent in series Each bit is cycled five times and the transmission starts with two start bits followed by 16 data bit one parity bit and a stop bit iStart bit 1 Startbit2 Data bitO Data bit 1 15 Parity bit 0 5 10 15 90 95 100 Time clock cycles Figure 8 1 One serial data transmission I 8 1 3 Network Layer The BusyBox will request event IDs from all active D RORCs when a Level 2 Accept trigger is issued The transmitter will keep sending new request at a programmable time interval until all the D RORC have replied Request can either be issued automatically by the firmware or manually by the DCS software 15 12 11 8 7 0 Command type Request ID Unused Table 8 3 Bit map for BusyBox Messages The messages from the D RORCs are 48 bits long and the time to receive one message is 1 2 us Every channel is checked every 120 clock cycle i e 3 us 47 44 43 32 EZEZ Request ID Bunch Count ID Orbit ID D RORC ID Table 8 4 Bit map for D RORC
45. ed on inputs from three sources TTCrx BusyBox DCS card and the D RORCs The above figure shows the main firmware modules of the BusyBox and will be discussed in more detail As mentioned before the BusyBox has two main functions assert the busy signal if FEE buffers are full or when a L1 trigger has been issued by the CTP 5 1 1 An intuitive explanation of how the BusyBox firmware works It all starts with a collision of hadrons in the LHCs ALICE detector The CTP detects this collision and notifies the LTU which issues a LO trigger to all four BusyBoxes via its optical fiber network The LO trigger is the start of a sequence of triggers and ends with either an L2a or L2r trigger The LTU broadcasts the BC Channel A and Channel B to the BusyBox through its fiber network and is converted by the TTCrx chip on the DCS card to electrical signals Then the information is decoded by the trigger receiver module Page 9 Not all of the decoded messages are useful for the BusyBox Hence the trigger receiver module only extracts the bunch count event ID and triggers The triggers are forwarded to the busy controller module which asserts the busy when a L1 trigger is received The bunch count and event ID is used to assure that all D RORCs have received data from an event and with that information in hand the BusyBox can keep track of the FEE buffers If all D RORCs have received event data this will imply that the event data have been read out f
46. es a sequence in the following order LO tirgger L1 trigger L1 Message L2 Message The different stages can be enabled and disabled by setting the flags in the sequence record type The LO trigger is executed at the first rising edge of the testbench clock after the procedure is called All other latencies are referenced from this time If e g the L2 Message latency has already passed when the L1 message is finished it will be executed right away This is true for all latencies defined in the trigger sequence record type 6 3 The RCU and DRORC emulator module This module has been designed to emulate the RCU and DRORC devices from the BusyBox s point of view Only the functions required for the operation of the BusyBox are emulated In the real system the RCUs will read event data from the Front End Cards and push it to the DRORCs The event data is preceded by a Common Data Header CDH which contains information related to the event amongst others the EventID When the DRORC has received an event including the CDH from the RCU the EventID is extracted and put in a FIFO queue When the BusyBox requests a new EventID the DRORC will look for it in this FIFO queue Since the size of the event data will vary between events and FEE patches RCU with FECs attached the time taken from an event has been triggered until the EventID ends up in the DRORCs EventID queue will vary as well To emulate this behaviour the rcu_drorc_emulator module
47. es for performing master read and write bus transactions using the bus record types defined in the package The procedures are used for accessing and testing the internal busybox registers during simulation They must be called from a sequential process and will block the calling process until they return procedure bb bus read constant addr in std_logic vector variable data out std logic vector signal bb_bus inout t_bb_bus_record procedure bb bus write constant addr data in std_logic vector signal bb bus inout t bb bus_record The clk_gen procedure makes it easy to generated clocks in the testbench The procedure is called from the concurrent section of a module and will act as a process 40 Page BusyBox User Guide e The period is specified by a constant and cannot be changed afterwards e The clock output can be enabled or disabled by the clk_en input procedure clkgen constant period in time signal clk_en in boolean signal clk out std logic For a convenient and compact definition of a trigger sequence a record type is defined that holds all relevant parameters of a trigger sequence A defined sequence is executed by calling a procedure run_sequence with an instance of this record type is one of its parameters type sequence _type is record description string 1 to 80 LO_enable boolean L1_enable boolean L1Msg_enable boolean L2Msg_enable boolean L2Accept boolean
48. f register that holds number of cycles the BUSY has been asserted Page 57 Busy Timer 15 0 0x2011 R Bit 15 0 of register that holds number of cycles the BUSY has been asserted RX Memory 0x2012 RW Filters which messages will be stored in RX Filter 15 0 Memory by channel number Bit 7 0 is matching pattern Bit 15 8 is matching mask to enable disable matching of individual bits LO deadtime offset 15 0 0x2013 RW Bit 31 16 of register that holds number of cycles the busy will be asserted after a LO trigger LO deadtime offset 15 0 0x2014 RW Bit 15 0 of register that holds number of cycles the busy will be asserted after a LO trigger Channel Register 3 0 Ox21XX RW Provides information on status of channel XX Bit 0 1 receiver for the channel is enabled and a matching Event ID from this channel is required Bit 1 1 indicates that the current Event ID has been matched for this channel This bit is read only Table 10 1 List of registers that can be accessed externally 10 2 Trigger Receiver Module Register Interface Control 15 0 0x3000 RW 0 Serial B channel on off Default 1 1 Disable_error_masking 0 2 Enable Rol decoding 0 3 LO support 1 4 7 Not Used 8 L2a FIFO storage mask 9 L2r FIFO storage mask 10 L2 Timeout FIFO storage mask 11 L1a message mask 12 Trigger Input Mask Enable 13 15 Not Used Control 7 0 0x3001 R 16 Bunch_counter overflow 17 Run Active
49. g_registers to false but during the development of HW FW they come in handy for DdD D DdD Ddd dd dd d d d d d d d d testing and verification The module address is not given in this table 10 3 TPC Channel Register Interface 0 0X2100 coo RCUO 108 0x216c A00 RCUO 1 0X2101 coo RCU1 109 0x216d A00 RCU1 2 0X2102 coo RCU2 110 0x216e A00 RCU2 3 0X2103 coo RCU3 111 0x216f A00 RCU3 4 0X2104 C00 RCU4 112 0x2170 A00 RCU4 5 0X2105 C00 RCUS 113 0x2171 A00 RCUS 6 0X2106 C01 RCUO 114 0x2172 A01 RCUO 7 OX2107 C01 RCU1 115 0x2173 A01 RCU1 8 0X2108 C01 RCU2 116 0x2174 A01 RCU2 9 0X2109 C01 RCU3 117 0x2175 A01 RCU3 10 0X210a C01 RCU4 118 0x2176 A01 RCU4 11 0x210b c01 RCUS 119 0x2177 A01 RCUS 12 0x210c c02 RCUO 0 0xC100 A02 RCU0 13 0x210d C02 RCU1 1 OxC101 A02 RCU1 14 0x210e C02 RCU2 2 OxC102 A02 RCU2 15 0x210f C02 RCU3 3 OxC103 A02 RCU3 60 Page 0x2110 0x2111 0x2112 0x2113 0x2114 0x2115 0x2116 0x2117 0x2118 0x2119 OX211a 0x211b Ox211 0x211d 0x211e 0x211f 0x2120 0x2121 0x2122 0x2123 0x2124 0x2125 0x2126 0x2127 0x2128 0x2129 0X212a 0x212b 0x212c 0x212d 0x212e 0x212f 0x2130 0x2131 0x2132 0x2133 0x2134 0x2135 0x2136 0x2137 0x2138 0x2139 0X213a 0x213b 0x213c 0x213d 0x213e 0x213f 0x2140 0x2141 0x2142 0x2143 0x2144 0x2145 0x2146 C02 C02 C03 C03 C03 C03 C03 C03 C04 C04 C04 C04 C04 C04 c05 COs COs COs c05 c05 c06 c06 C06 C06 C06 c06 C07 C07 C07 C07 C07 C07 C08 C08 C08
50. h the BusyBox and make changes to the firmware In addition the CTP emulator will be discussed 9 1 Introduction TCL scripts sets up projects in Xilinx ISE Design Suit and Mentor Graphics QuestaSim All the files needed for the BusyBox are in a repository The scripts are written to implement the files to checkout and build or simulate the design Furthermore knowledge about the interaction with the BusyBox hardware is given on how to program read write registers and test the design with triggers from a trigger emulator 9 2 SVN Repository and Project Setup The BusyBox firmware has been written in Xilinx ISE Design Suite and tested in Mentor Graphics QuestaSim The source code and other relevant files for the BusyBox are stored in a SVN repository to make it easy to see the latest work done 9 2 1 SVN Repository A repository has been created to have a place where f data is stored and maintain for future retrieval to manage ongoing development of digital documents in pee the BusyBox project Any changes in the document Open as Notebook in OneNote Lagg ti Windows Media Player are identified by incrementing an associated number es UEP oe termed the revision number The University of Bergen Keep inact pt nett uses a SVN repository eee ki Sok ettesviuses TortoiseSVN is an open source revision control bili SVN Checkout software for Microsoft Windows To download the 4 rae a 5 ee software go to
51. ilinx Virtex IV 8b FPGA 2 Xilinx Virtex IV TPC only 9 Connector for digital analyzer Also serves as inter connect between FPGAs 10 DCS board Connectors for DCS board 11 Power supply connector Connector for external power supply Power supply 5V 12 A 12 SelectMAP resistor for pull ups pulldowns and thevenin termination of clock CCLK 13 Pin connectors GND 1 2V 2 5V and 3 3V output 14 FPGA2 configuration resistors Sets the configuration mode to 8bit SelectMAP slave 15abc Voltage regulator PTHOSOOOW voltage regulators from Texas Instruments 16 Test point JTAG interface Standard JTAG access port Used for configuration and debug 17 Test point SelectMap BUG SelectMAP CCLK must be cut at certain point on PCB to prevent interface ringing Table 4 1 List of components on the PCB 4 1 Xilinx Virtex IV FPGA The BusyBox use the Virtex 4 LX 40 with the ff1148 package from Xilinx There are 640 user programmable I O pins that support LVDS 2 5 standard used to communicate with the D RORCs The Virtex 4 can run on clock speeds up to 500 MHz store 18 Kbits in 96 BRAM modules and has DCM to provide flexible clocking and synchronization A Multiple device SelectMap bus is used to program the FPGAs since two FPGAs can be used with different firmware Linux kernel device drivers have been developed so that the Linux OS running on the DCS board can redirect the programming bit file to the FPGA The BusyBox can also be progra
52. in the UUT The decoded triggers are read out from the extra trigger_receiver and the eventID is extracted and pushed to the rcu_drorc_emulator modules which communicate with the BusyBox over serial links The trigger sequences are easily generated by a procedure call to run_sequence defined in the busybox_tb_pkg VHDL package which is described in section The busybox_tb_pkg package6 2 1 6 2 Support packages The testbench makes use of the following packages ieee std_logic_1164 all IEEE package defining std_logic type and derived types ieee numeric_std all IEEE package for numeric operations on std_logic based sub types ieee math_real all IEEE package for math operations used for random generation std textio all Package for modifying and printing text strings work tb_pkg all e work busybox_tb_pkg all Package containing various definitions of types functions and procedures used in the testbench 6 2 1 The busybox_tb_pkg package This package was written specifically for this testbench and holds definitions required by it A record type is defined that contains all signals related to the bus interface with the DCS board Procedures for performing read and write operations on this interface are also defined type t_bb_bus_record is record strobe _n std_logic Rnw std_logic addr std_logic_vector 15 downto 0 data std_logic_vector 15 downto 0 ack_n std_logic end record t bb bus record Procedur
53. in the VHDL file tb_trigger_busybox vhd It emulates the outside world of all these interfaces providing stimuli and interaction Figure 6 1 shows a structural overview of the testbench The Unit Under Test UUT is the rectangular box in the middle Other rectangular boxes are modules instantiated in the testbench Elliptic shapes are processes defined in the testbench tb_trigger_busybox Litrig amp SerialB Clock generators PA 5 B Q Unit Under Test Q busylogic_top eaman i ta 1al e PEER Ta lt lt wm trigger_receiver p4 ial Busy g MEB Count g 3 3 a trigger_receiver DAQ headem Extract N ea rcu_drorc_emulator EventID T SS 5 ae Ti lt Yyyy MEB Counts Figure 6 1 Stuctural overview of the testbench for the BusyBox logic The clock generators are simply concurrent procedure calls to clk_gen in the busybox_tb_pkg See section 6 2 1 for more details on the procedure The system needs two clocks to operate one at 200 MHz and one at 40 MHz p_clockA clkgen clkA period clk_en clk200 p_clockB clkgen clkB period clk en clk40 Page 39 The process tb_main generates trigger sequences and access registers in the UUT over the DCS bus An extra trigger_receiver is instantiated in the testbench to acquire the same trigger information as produced by the trigger_receiver
54. is powered up To check if the FPGAs are programmed one can try to read some register with the RCU shell e g shell prompt on DCS board rcu sh r 0x1000 If the result is no target answer then the FPGA is not programmed Otherwise you should get the value of the register The easist way to program the FPGAs is to use the shell script program This script should be located with the programming files for the FPGAS bit in the directory mnt dcsbro busy busybox files Prompt on DCS board program lt programmingfile1 bit gt lt programmingfile2 bit gt There should be four programming files in the directory 1 busybox_fpga1 bit for the first of two FPGAs 2 busybox_fpga2 bit for the second of two FPGAs 3 busybox_fpga1_solo bit for FPGAs on boards boxes where only on FPGA is mounted 4 busybox_dummy bit will be used by the script to program the second FPGA if no second programming file is given Note When two FPGAs are mounted then both must be programmed or the firmware will not start up The bit files to be programmed into the FPGA s must be put in the folder nfs_export dcscard on kjekspc7 9 7 Configuring the Firmware Modify the shell script bbinit sh to fit your setup 9 8 Monitoring the BusyBox registers Use regpoll sh status to view most of the status registers of the BusyBox Type regpoll sh status To display the channel registers use regpoll sh channels Type 54 Page BusyBox User Guide
55. ition P4 3 2 PZ Ele ie x x BusyBox User Guide P1 X P1 P2 x x X P2 P3 x x x m P4 pa x x x x x x x Table 5 19 Hamming code table fw_req 1 ldcs_tx_pending 1 lencoder_busy 0 encoder_busy 0 s_fw init tx_data fw_dat fw_ack 1 encoder_data_en 1 s_des_init tx_data des_tx_data encoder_data_en 1 des_tx_ack 1 encoder_busy 0 S_wait_for_decoder Figure 5 17 State diagram for TX controller c1k200 c1k40 rst40 fw_req fw_data fw_mask module_en module_rnw module_data_in module_address yee beaey te serial channels out fw_ack gt gt module data_out Figure 5 18 Entity for Transmitter Module Page 25 Port Name rst40 std_logic synchronous reset clk200 std_logic the clk200 frequency is 200 MHz clk40 std_logic the clk40 frequency is 40 08 MHz fw_req std_logic fw_data std_logic_vector 7 downto 0 fw_mask std_logic_vector 0 to num_of_channels module_en 1 std_logic module_rnw 1 std_logic module_data_in 16 std_logic_vector 15 downto 0 module_address 12 std_logic_vector 11 downto 0 serial_channels_out 120 std_logic_vector 0 to num_of_channels fw_ack Output 1 std_logic module_data_out Output 16 std_logic_vector 15 downto 0 16 bit request data to D RORCs Table 5 20 I O
56. k domain rst40 out std_logic synchronous reset for the 40 MHz clock domain Table 5 6 10 table for reset_logic module I 5 6 DCS Bus Arbiter and Address Decoder The DCS bus arbiter and address decoder module is an asynchronous 16 bit data address handshake protocol for communication between the FPGA and DCS board This protocol is used to read and write registers in the BusyBox firmware The MSB of the 16 bits DCS bus address selects which FPGA to communicate with Then each module can be accessed with the next three bits and the remaining bits are used to target specific sub module registers FPGA address Module address Sub module address 15 14 12 0 Table 5 7 Bit mapping of DCS bus address J 5 6 1 _ Entity DCS bus arbiter and address decoder TERET c_fpga_id c1k40 dcs_strobe_n dcs_RnW des_addr dces_data dcs_ack_n module_data_array module_en_array module_data_out module_address module _RnW ERRER Figure 5 6 Entity for DCS Bus Arbiter and Address Decoder Generic name c_fpga_id Type std_logic Comment This bit sets the slave FPGA MSB address 0 for FPGA1 or 1 for FPGA2 Table 5 8 Generic parameters for des_arbit_addr_dec Port Name __ Direction la Bit Description clk40 Input 1 std_logic the clk40 frequency is 40 08 MHz dcs_strobe_n Input 1 std_logic the asynchronous handshake is done with STROBE_N from the DCS board dcs
57. k emulation Start Break Quit status emulation emulation emulation SSS E Page 55 Next to the Sequence tag click L2a seq and click Load sequence Click Start emulation So when you click the Generate SW Start signal s trigger sequences are sent to the BusyBox To get the password contact 56 Page 10 Register All registers for the BusyBox are listed below 10 1 BusyBox Register Interface TX Register 15 0 0x30001 RW RX Memory1 15 0 0x1000 RW Ox1FFF RX Memory2 15 0 0x1000 RW Ox1FFF RX Memory3 15 0 0x1000 RW Ox1 FFF RX Memory4 15 8 0x1000 RW Ox1FFF RX Memory Pointer 11 0 0x2000 R Event ID Count 8 0 0x2001 R Current EventID 3 0 0x2002 R Current EventID 15 0 0x2003 R Current EventID 15 0 0x2004 R Newest EventID 3 0 0x2005 R Newest EventID 15 0 0x2006 R Newest EventID 15 0 0x2007 R LO trigger timeout 0x2008 RW FEE Buffers 0x2009 RW Available 3 0 Halt FSM 0 0x200A RW Force Event ID Match 0 0x200B wW Re request Timeout 15 0 0x200C RW Current Request ID 3 0 0x200D R Request Retry 0x200E R Count 15 0 Busy Timer 15 0 0x2010 R Legend W write R read T write trigger not physical registers BusyBox User Guide Transmits a message on serial ports when written to Bit 7 0 is TX Data Bit 15 8 gives channel number in hexadecimal Any value greater than the actual number of channels will result in a broadcast on all channels All addresses in range where the 2 LSBs ar
58. l number in the channel register The masking vector lets the Event ID Verification module and DCS bus module select which channels to enable or disable The controller handles requests from the Event ID Verification module and DCS bus module to prevent communication conflicts A state machine in the serial encoder module sends a 16 bit word to the PISO Parallell In Serial Out module by request from the controller Serial signals to LVDS drivers HEHHE Masking vector 1 1 1 1 1 1 1 1 1 Disa 1 Mask Serial encoder i 1 1 Message 1 Event ID verification 1 module l 1 Request Controller 1 Grant Su 1 1 i i i Message register Channel register 1 1 1 1 Latest es oe e DCS bus arbiter and address decoder Figure 5 14 Transmitter system From Magne The transmitter module will request eventiDs from the D RORCs The request is a 16 bit word and is sent to all D RORCs Command type Request ID Unused Table 5 16 Bit map for Trigger module request Page 23 Request Event ID 0100 Request an Event ID from the D RORC Resend last message 0101 Command the D RORC to re transmit the last message sent Force pop Event ID 0110 Command the D RORC to pop one Event ID from its local queue Force Request ID 0111 Command the D RORC to store the attached Request ID Table 5 17 Request commands 5 8 1 Transmitter module VHDL Entity Hierarchy e Tr
59. mmed via JTAG interface on the PCB When one FPGA is used a jumper on the PCB needs to be applied to bypass the missing JTAG chain 4 2 DCS The DCS board was originally designed for the TRD and TPC sub detectors but because it was very versatile it has been adapted for the BusyBox and other instrumenst in ALICE experiment It is running a lightweight version of Linux and implements TCP IP network protocol The DCS board has a TTCrx chip to receive the LHC clock first level trigger accept and trigger messages Each card runs a FEE server that interfaces with the system it is connected to Thus it makes it possible to program the FPGA s and read write registers remotely from the control room at Point 2 8 Page BusyBox User Guide 5 BusyBox Firmware This chapter discusses the functionality of the firmware and gives a description of each module with sub modules The firmware modules are described with text pictures entities and port details 5 1 Introduction BUSY signal to LTU Data from D RORCs Data to D RORCs I Event ID Transmitter Busy Controller Verification e Receiver Module Module Module 7 Trigger Receiver Control and RX Memory Module Status Registers Module Signal from TTC DCS Bus Arbiter and Address Decoder DCS bus interface Figure 5 1 Main BusyBox firmware modules The firmware controls the BusyBox and executes its designed purpose bas
60. mplemented by using one of three different top level wrappers The different top level wrappers are necessary to adapt the firmware to fit different hardware configurations If two FPGAs are present then they must work in parallel and be coordinated If only one FPGA is present it must operate in standalone mode Figure 5 2 shows a graphical representation of the same information as above In addition the 1O buffers that are instantiated in the top level wrappers are included in the figure 10 Page BusyBox User Guide busybox_fpgat busybox_fpga2 busybox_fpga1_solo IBUFGDS IBUFDS OBUF OBUFDS digital_clock_manager busylogic_ top reset_logic ctrLregs busy_controller des_arbit_addr_dec rx_mem filter multi_channel_reciever event_validator_top receiver_memory_module braa onoir drorc_inbox_buffer Tinali FIF eyni OR 12 transmitter_module backbone_controller serial_encoder eventid_control single_channel_receiver event_processor trigger_receiver_busylogic serial x trigger_receiver daq_header_extractor Figure 5 2 Module instantiation hierarchy 5 2 BusyBox top level wrappers The BusyBox PCB can be fitted with one or two FPGAs depending on the number of channels required The different hardwa
61. re configurations require slightly modified versions of the firmware at the toplevel HDL source A BUSY signal from FPGA2 is combined in FPGA1 among other things There are three different toplevel HDL files busybox_fpga1 vhd busybox_fpga2 and busybox_fpgai_solo There three are different usage scenarios e For BusyBoxes with 2 FPGAs mounted FPGA1 should be programmed with firmware based on busybox_fpga1 and FPGA with busybox_fpga2 e if the second FPGA is not going to be used then FPGA1 can be programmed with busybox_fpga1_solo but FPGA2 must then be programmed with a dummy configuration for the programming operation to finish without errors e For BusyBoxes with only one FPGA firmware based on busybox_fpga1_solo must be used At the toplevel HDL wrappers it is possible to specify the number of channels to be implemented Each channel is connected to the rest of the design through a branch One branch controller can support up to 16 channels There must be enough branches to connect the number of channels specified or the implementation will fail 5 2 1 Entity BusyBox FPGA Modules Page 11 Acts as a wrapper for each version of the three firmware versions busybox_fpga1 vhd busybox_fpga2 vhd and busybox_fpga1_solo vhd These wrappers instantiates the BusyBox top module with the required generic parameters and extra logic The wrapper also adds and configures the necessary Virtex 4 IO buffers and Digital Clock Manager DCM around the b
62. rom the FEE buffers It is the busy controller module that keeps track of the FEE buffers FEE buffers can hold 4 or 8 events and starts buffering data on a LO trigger TPC starts on a L1 So if there is a LO trigger 1 buffer is occupied and if all the D RORCs have responded with the same event ID and bunch count the EventID is OK EIDOK Then the event data have been read out and the buffer is free A control and status register can as the name implies control and check the status of registers in the BusyBox Registers in the trigger receiver module and stored data from the receiver module in the RX memory module can also be accessed All this is done via the FeeServer on the DCS card mounted on the BusyBox PCB 5 1 2 VHDL Entity Hierarchy e busybox_fpga1_solo busybox_fpga1 busybox_fpga2 o busylogic_top o ctrl_regs Control and Status Registers o dcs_arbit_addr_dec DCS Bus Arbiter and Address Decoder o _transmitter_module Transmitter Module serial_encoder o multi_channel_receiver Multi Channel Receiver Module single_channel_receiver e serial rx branch_controller backbone_controller o rx_mem_filter o receiver_memory_module RX Memory Module rx_bram o event_validator_top Event ID Verification Module drorc_inbox_buffer FIFOsync108x512 daq_header_extractor eventid_control eventid_processor o trigger_receiver_busylogic Trigger Receiver Module o busy_controller Busy Controller The firmware can be i
63. s from the CDH Figure 5 23 shows an overview of the Trigger Receiver module 28 Page BusyBox User Guide t clk Inteface je Counters a Tisoers Errors Errorfinfo gt FIFO_wrapper Buffered events FIFO q Read enable depth 128 width 33 CDHp JHHeader i Start of run End of run Lir trigger p Addressed Hamming data p Message Msgt Seguenos By gt L2a L2r trigger L2 timeout p Fee reset p Cal pre pulse p Bunchent reset p date gt Broadcast Decoder Channel A Eventent reset p La trigger p LO trigger p phase internal logic Inputs from Figure 5 24 Block diagram of the Trigger Receiver module From Johan gt 5 11 1 Entity Trigger Receiver Module Page 29 clk reset_n L1lAccept serialBchannel read_enable data_in Addr Rnw module_enable Pea e eee FEE_reset busy start_of_run end_of_run event_reset bunch_reset buchcnt_overflow LO_trigger Lla_trigger L2a_trigger L2r_trigger L2_timeout DAQ_header_out read_counter_out buffered_events Data_out cal_pre_pulse LT a Gad dled Figure 5 25 Entity for Trigger Receiver Module clk Input std_logic the clk frequency is 40 08 MHz reset_n Input std_logic L1Accept
64. since each sub detector should report busy if this is not asserted If there is a physical problem with the connection to the LTU or the CTP is issuing a global reset the busy is set JohanA Every time a LO trigger is detected a countdown timer timeout_active starts and the busy is set for this time period The busy time can be set manually with a register in the Control and Status Register module The busy_controller keeps track of how many Multi Event Buffers MEB are occupied in the FEE If the number of occupied MEBs is greater or equal than then a programmable limit then BUSY is asserted The BUSY is asserted whenever the trigger receiver is busy which means we are in the middle of a trigger sequence The Busy Controller module increment a register buffer_count when a LO is detected L1 for TPC decrements the register when a L2 Reject trigger is asserted and when the Event ID Verification module asserts the event valid signal The number of occupied MEBs is calculated by monitoring the triggers and the validation of event IDs process L1 Trigger UP el L2 Reject MEB used DOWN CNT gt L2 Timout DOWN Event Valid Event Payload Figure 5 33 MEB counter The counter is incremented when a L1 trigger is seen It decrements on a L2 Reject or L2 Timeout and when event valid and event payload is active at the same time See Figure 5 33 5 13 1 Entity Busy Controller Module 36 Page BusyBox User Guide
65. st registers for all BusyBox channel numbers in decimal the address to their registers and which RCU DRORC pair should be connected to this channel
66. t sequence of three words If all three words have been read out successfully and no parity errors and timeouts were found the state machine will send the data to a multiplexer tree Up to sixteen Single Channel Receivers can be connected to a Branch Controller module The Branch Controller buffers data from the Single Channel Receivers and stops further buffering until data have been read out by the Backbone Controller The Backbone Controller may have up to eight Branch Controllers and the concept is illustrated in Up to 16 channels per branch si ngl e_channel_recei ver serial _recei ver si ngl e_channel _recei ver seri al_recei ver si ngl e_channel_recei ver seri al _recei ver Up to 16 channels per branch single_channeL receiver Up to8 branch controllers branch_cont rol I er branch_cont rol I er branch_cont rol I er Up to8 branch controllers serial receiver YYYYYYYYY branch_controller single_channel receiver serial receiver VYVYVYVYY branch_controller single_channel receiver Page 17 Received messages backbone_control er ___ backbone_controller Received messages gt serial receiver
67. top module the the DCM has locked on the external clock Then the reset is released At lines 11 and 12 it writes to two configuration registers to set the MEB limit to 4 and release the busybox FSM set the halt FSM bit to 0 All other registers are left at their default value Now the BusyBox should release the BUSY and be ready to receive triggers 1 clk_en lt true 2 dcm_lock lt 0 3 serialb lt 4 Litrig lt 0 5 areset lt 1 6 wait for 200 ns 7 dcm_lock lt 1 8 wait for 10 us 9 areset lt 0 10 header Testbench for BusyBox A sequence of basic triggers 11 bb_bus write X 2009 X 0004 dcs_bus set MEB to 4 12 bb_bus write X 200A X Q000 dcs_bus release busybox FSM 13 wait for 500 ns 14 run_sequence clk40 trigger _sequencel Litrig serialB 15 wait for 100 us 16 run_sequence clk40 trigger _sequencel Litrig serialB 17 wait until busy out 0 18 run_sequence clk40 trigger_sequencel Litrig serialB 19 wait until busy out 0 20 run_sequence clk40 trigger_sequencel Litrig serialB 21 wait until busy out 0 22 run_sequence clk40 trigger_sequencel Litrig serialB 23 wait until busy out 0 24 run_sequence clk40 trigger_sequencel Litrig serialB 25 wait until busy out 0 Page 43 26 run_sequence clk40 trigger_sequencel Litrig serialB 27 wait until busy out 0 28 run_sequence clk40 trigger_sequencel Lltrig serialB 29
68. ug Latest received L1 Message Debug Latest received L1 Message Debug Latest received L1 Message Debug Latest received L1 Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2a Message Debug Latest received L2r Message Debug Latest received Rol Message Debug Latest received Rol Message Debug Latest received Rol Message Debug Latest received Rol Message Debug Triggers a readout pulse to FIFO L1_MessageHeader 11 0 0x3060 L1_MessageData1 11 0 0x3062 L1_MessageData2 11 0 0x3064 L1_MessageData3 11 0 0x3066 L1_MessageData4 11 0 0x3068 L2aMessageHeader 11 0 0x306A L2aMessageData1 11 0 0x306C L2aMessageData2 11 0 0x306E L2aMessageData3 11 0 0x3070 L2aMessageData4 11 0 0x3072 L2aMessageData5 11 0 0x3074 L2aMessageData6f 11 0 0x3076 L2aMessageData7 11 0 0x3078 L2rMessageHeader 11 0 0x307A RolMessageHeader 11 0 0x307C RolMessageData1 11 0 0x307E RolMessageData2 11 0 0x3080 RolMessageData3 11 0 0x3082 FIFO_read_enable 0x3100 FIFO_DAQHeader 15 0 0x3102 Debug Output of FIFO 15 0 FIFO_DAQHeader 15 0 0x3103 Debug Output of FIFO 31 16 Table 10 2 List of registers that can be accessed externally Note that the registers marked debug can be excluded by setting the generic include_debu
69. us Register module one bit set or disable channels std_logic_vector 47 downto 0 48 bit data from D RORCs std_logic_vector 7 downto 0 toggles the data from the different channels to be outputted std_logic 1 D RORC data ready to send A state machine checks for parity errors and make sure that the 16 bit words from the serial decoder is within the allowed time limit Three 16 bit words are concatenated to a 48 bit message and stored temporary in three different registers If the registers are not read out fast enough they will be overwritten c1k200 rst200 enable serial_in read_ack litl data_av gt data_out gt Figure 5 9 Entity for Single Channel Receiver Page 19 clk200 Input 1 the clk200 frequency is 200 MHz rst200 Input 1 std_logic synchronous rest enable Input 1 std_logic serial_in Input 1 std_logic data bit from serial decoder data_out Output 48 std_logic_vector 47 downto 0 48 bit data from D RORC read_ack Input 1 std_logic data_av Output 1 std_logic Table 5 12 I O details for Single Channel Receiver 20 Page BusyBox User Guide 5 7 4 _ Entity Serial Decoder gt c1k200 parity error gt gt rst200 data_av gt enable data_out gt serial in Figure 5 10 Entity for Serial Decoder clk200 Input 1 std_logic the clk200 frequency is 200 MHz rst200 Input 1 std_logic synchronous reset
70. usyBox registers Resetting the BusyBox CTP Emulato REGISTER BusyBox Register Interface Trigger Receiver Module Register Interface TPC Channel Register Interface DONNA ARWHWN wae N S 14 Page 3 2 Introduction The purpose of this document is to give users of the BusyBox an understanding of what it is by discussing the hardware firmware and software which is the key components of the ALICE BusyBox system The scope of this technical paper and user guide will be to collect all the information necessary to understand use and modify the BusyBox I 2 1 Document History evision Revision date Summary of changes Author ee 1 0 09 12 08 N A Rikard Bglgen 11 08 12 09 e Merged into one file Magne Munkejord e Added chapter Feil Fant ikke referansekilden Feil Fant ikke referansekilden Changed document style e Updated some interface tables and figures to latest firmware revision 12 14 09 2010 Updated first page Kjetil Ullaland e Edited layout Table 2 1 Revision history Package Version Firmware BusyBox 41 Trigger Receiver Module 15 DCS card Version 2 84 BUSYBOX Table 2 2 Firmware versions corresponding to this guide I 2 2 Abstract ALICE is one of four large detectors situated at the collision points in the LHC at CERN The BusyBox utilizes the TPC PHOS
71. usylogic_top module busybox_fpga1 beeeE PLE clock_Ivds_P _ serial_tx_p clock_Ivds_N _ serial_tx_n areset_n dcs_data serialB_in dcs_ack_n L1Trig_P BUSY_1 L1Trig_N BUSY_2 serial_rx_p leds serial_rx_n dces_adr dcs_strobe_n dcs_RnW intercon_busy TTXrx_ready Thue busybox_fpga2 one eee clock_Ivds_P _ serial_tx_p clock_Ivds_N _ serial_tx_n areset_n dcs_data serialB_in dcs_ack_n L1Trig_P intercon_busy L1Trig_N serial_rx_p serial_rx_n dcs_adr dcs_strobe_n dcs_RnW TTXrx_ready Wd busybox_fpga1_solo fo a aes clock_Ivds_P serial_tx_p clock_Ivds_N _ serial_tx_n areset_n dcs_data serialB_in dcs_ack_n L1Trig_P BUSY_1 L1Trig_N BUSY_2 serial_rx_p leds serial_rx_n dces_adr dcs_strobe_n dcs_RnW TTXrx_ready TUTTI Figure 5 3 Entity for BusyBox FPGA modules BUSY1 and BUSY2 outputs only exist on FPGA1 These outputs are the same logical signal 12 Page BusyBox User Guide e Busybox_fpga1 wrapper takes busy input intercon_busy from FPGA2 and combines it with its own BUSY output through an OR gate num_of_channels natural Oto 119 119 Specifies the number of channels 1 that will be instantiated at compile time num_of_branches natural 1to amp 8 Specifies number of branches at compile time Each branch can connect 16 serial receiver channels Table 5 1 Generics at the HDL top level wrappers busybox_fpga1 119 8 busybox_fpga2 96 6 busybox_fpga1_solo
72. x_mem_matching_mask Output 8 rx_mem_pattern Output 8 fee_buffers_available Output 4 trig_timeout Output 16 req_timout Output 16 halt_validator Output 1 force_validate Output 1 CHEN_vector_out Output 120 Table 5 30 I O details for Control and Status Registers std_logic the clk40 frequency is 40 08 MHz std_logic synchronous resets std_logic std_logic std_logic_vector 11 downto 0 std_logic_vector 15 downto 0 std_logic_vector 9 downto 0 std_logic_vector 3 downto 0 std_logic_vector 35 downto 0 std_logic_vector 35 downto 0 std_logic_vector 3 downto 0 std_logic_vector 15 downto 0 std_logic_vector 0 to num_of_channels std_logic_vector 31 downto 0 std_logic_vector 15 downto 0 std_logic_vector 7 downto 0 std_logic_vector 7 downto 0 std_logic_vector 3 downto 0 std_logic_vector 15 downto 0 vector 15 downto 0 std_logic std_logic_vector 0 to num_of_channels 38 Page BusyBox User Guide 6 Functional verification of the BusyBox firmware 6 1 Introduction This chapter describes a testbench for the BusyBox firmware The testbench is designed to emulate a complete environment around the BusyBox top level module busylogic_top The FPGA specific wrappers are not included in the test setup The BusyBox interacts with the outside world through numerous interfaces Clocks amp Reset Trigger System L1Trig and SerialB DCS bus Serial RX and TX to DRORCs AWN The testbench is impelemented
73. y Filter that is accessible from the DCS bus interface The RX Memory Filter has registers with 16 bits The first 8 bits are used to toggle matching individual bits The last 8 bits are the bits that will be compared with the channel number bits of the message This feature makes it easier to see the response of only a subset of channels in the RX Memory without disabling the other channels in the CHEN registers 5 10 1 Entity RX Memory Filter Module pattern filtered_we gt match_mask drorc_address write_en oe Figure 5 22 Entity for RX Memory Filter pattern Input 8 std_logic_vector 7 downto 0 match_mask Input 8 std_logic_vector 7 downto 0 drorc_address Input 8 std_logic_vector 7 downto 0 write_en Input 1 std_logic filtered_we Output 1 std_logic Table 5 23 I O details for RX Memory Filter 5 11 Trigger Receiver Module The optical signals from the CTP are converted to electrical signals by the TTCrx chip on the DCS board into Channel A and Channel B The Trigger Receiver module decodes the information and stores it in a FIFO in the CDH Common Data Header format Triggers will appear as individual signal at the module outputs Channel A transmits the LO and L1 triggers Channel B transmits the broadcast message and the individually addressed messages The addressed messages are decoded into the CDH format and put in a FIFO The BusyBox extracts the event ID OrbitID BunchCountID event info and event error

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