Home

OVERVIEW

1. Personnel and SUDS Usage We assume that most engineers will be interested in running SUDS at least at the beginning fact it is recommended that the engineer become quite conversant in SUDS as it is a complex system and you can only get the best use out of a tool you know weii However we expect the majority of the actual use to come from a technician or draftsperson as schematics are currently their responsibility anyway Most important however is the need for at least one person in each group to become the SUDS guru to answer questions about it s operations interface with library support and software support and direct the module release non trivial set of OK So How Do I Actually Use It We have given much thought to exactly how to use all the Components of SUDS and if it would be possibie to document this We have come to the conclusion that there can be no one document to serve all of the generai Engineering communities Fach dou has their own personnel their own area and their own way of doing design Although there are points in the general process where certain data is needed or certain functions ought to have been performed the way to der there can Yu greatly What we are suggesting is that each group sit down with their SUDS guru Engineering Manager the iocal Engineering Services Site Manager and perhaps the SUDS trainer and come up with a definitive document of
2. m O 2 TABLE 1 14 FINS Ul dD t 0 2 de dr Grm 14 19 05575 00 IP SUB MODE x n 7400 3 DIPS DIP File Listing for DRW Symbol 7406 TIS TO TIS TIS TO TG TO TIS TIS TO TIS TIS UG FACKAGE TIS LOW 1 60 1 60 16 00 1 60 1 60 16 00 16 00 1 60 1 60 16 00 1 60 j 60 5 004 3 HI 0 04 0 04 0 40 0 04 0 04 0 40 0 40 0 04 0 04 0 40 0 04 0 04 USE 22 pt HM gt gt Ol Gl SECTION RULE 1 0 2 0 3 0 1 1 2 1 3 1 3 2 2 2 1 2 3 3 2 3 1 3 45 TABLE 2 Excerpts from RES Listing 270 OHMS PRES RES 2 FINS PIN TYPE 1 I 2 I XARES PROPERTY SUB MODE KE UALUE RATING 04 OHMS 2W 10 OHMS 20 5 Su 1 MEG OHMS 1 4W 1 OHMS 1 4W 2 0W 1 1K OHMS 1 4W 1 2K OHMS 1 4W 3 9 110 OHMS 1 44 113K OHMS 1 40 120 OHMS 1 44 121 OHMS 128K OHMS 1 41 130K OHMS 1 4W 137K OHMS 1 4U 140 MILLIOHMS Sid 147 OHMS 1 44 150 OHMS 1 2W 1 4W iW 2W 150K OHMS 1 4W 178 OHMS 1 4W 180 OHMS 1 4W 196 OHMS 1 4W 200 OHMS 1 2W 1 44 215 OHMS 1 4U 220 OHMS 1 4U 237 OHMS 1 44 261 OHMS 1 4U 1 4W whe Che cn CH F CH 0 00 0 00 h NN 3 5 10 1 1 5 55 1027 3 1 1 1 1
3. 17 1 107 54 M N NNN NN N NON NON N USE TOLERANCE 46 FS SECTION RULE 1 0 2 0 FART NUMBER X13 17515 00 13 15240 00 13 13358 00 13 09595 00 K13 17522 00 13 14350 00 13 02645 00 13 14491 00 13 01320 00 13 11523 00 13 09296 00 13 00247 00 13 02957 00 13 05516 00 3 14252 00 x13 05422 00 13 10189 00 13 02874 00 K13 12699 00 3 00250 00 13 00256 00 3 00257 00 13 02396 00 13 11422 00 K13 01322 00 13 02956 00 X13 02381 00 13 02962 00 x13 11522 00 13 05123 00 13 00271 00 X13 13347 00 13 04857 00 X13 02873 00 13 01972 00 47 PUBLIC LIBRARIES The user can get the body definitions from any iibrary by using the GETLIB command can also inspect the contents of any library that has been gotten by using L to list the names of the bodies the terminal or L to list them in a file to be printed He can also make a visuai inspection of the symbols contained in the libraries getting a set of show drawings for them from the site librarian The presentiy available iibraries are these PTTL All plain TTL dips 7404 HTTL All high speed TTL dips 74H94 STTL All Schottky ITL dips 74504 LSTTL 11 low power Schottky TTL dips 741 504 PARTS Discrete components resistors switches etc NCOMP Hash mark and ground symbols CMOSBD All CMOS dips 4044 ECLBOD All 19K ECL dips 10124 CKECL Aii
4. Eliminating the disagreement between the print sets and the physical design data Supplying control over the print set to the Engineer Reducing the hassles invoived in discerning the incrementai difference between an ECOed design and it s base rev Interface Specifically many interfaces exist in SUDS to allow you to communicate with other CAD processes used at DEC Some examples of these interfaces and other capabilities follow Draw and post process piot diagrams Extract the wirelist from the SUDS drawing data base that is suitable for input to the CALDEC and IDEA P C and I C EBTOME Extract wirelist for input to the SAGE 2 simulator Extract a wirelist for input to the CALMA 14 layout Eu Obtain reports on data such as gate loading nus d pins naming violations parts lists used on information and Combine data together from many modules for wirewrap of E backplane Obtain a wirelist for wirewrap of prototype board Create procedures Macros for sequences of often used or Complex drawing commands Create and maintain cover sheets to print sets contents etc Create simpie mechanical diagrams Draw auxiliary data such as Capacitor Drawings Parts Lists etc Do flow charts and architectural diagrams using SUDS SUDS is actually only the starting point in a whole array of computer aided CAD tools under at DEC
5. THE STANFORD UNIVERSITY DESIGN SYSTEM 5005 OVERVIEW Opening Engineering Information Control Introduction What is SUDS How is it used Available Services The Environment System Configuration CADNET System description Programmable Graphics Processor SUDS User Station SUDS Library _ General Description DRW file b DIPS DIP file Public Libraries SUDS Overview 5005 Drawing Program Wirelister Pro ram General Description _ Design Aids a Logic Simulation b Placement Optimization Delay Calculation 5005 other pEC Programs ass We b Multiwire es KPL the 5005 Processes 5105 Idea SUDS to a _ Conclusion 5005 vs Manual THE STANFORD UNIVERSITY DESIGN SYSTEM 5005 INTRODUCTION What is SUDS The Stanford University Design System SUDS was originally developed at the Stanford Artificial Intelligence Lab by Dick Helliwell It is schematics logic drawing package which not only offers hardcopy capabilities but is also the nucleus of a data base which provides input to the IDEA and CALDEC automated printed circuit board design systems operative here at Digital The data entered into SUDS for generating logic schematics wili also generate wirelist information and layout verification for use by the layout designers In short SUDS allows you to draw schematic using interactive graphics and then feed this drawing directiy to
6. 65 WIRELISTER WL A set of 5005 wirelist files WD is the source of information for the wirelister program WL which from it generates ali sorts of option files for other programs XMAKALL Is the wirelister command that will automaticaliy qenerate the following files and listings Wirelist WL Wirelist Summary WLS Wirelist Utilization WLU Parts List PRT OPTION FILES SUDS output files that are used for input to other programs XTLE Generates a CMD file for input to IDEA XCALDEC Generates a CON file for input to CALDEC XCS Generates a CS file for input to IDEA and CALDEC to do a wireiist compare WLCOMP to insure that the drawings and PC board are compatibie SAGE 2 Generates WIR fiie for input to the SAGE 2 logic simulator RENAME PROGRAM The rename program receives an tape from CALDEC which contains an old and new file These two files are processed using the rename program to generate an UML file which is used as an input to the GCD GTD program to automatically update the DRW fiie PLOT PROGRAM RU P Running the piot program P on a set of SUDS piot files DPL results in a PLO fiie which serves as an input to most of the different hardcopy units Versatic to produce plot of the finish drawing GREAT NAME CHANGE Is used to put prefixes on ail signal names It generates C ange fiie CHG enge is used to inpu
7. piacement optimization system and for many other procedures The Wirelister aiso has many faciiities to assist the user in both drafting and design in the former by such things as checking for inconsistent signal names and in the latter keeping track of loading power consumption and other physical characteristics Drawing files of the schematics for a circuit board or chip constitute a permanent database that serves as the central information source for ail of these other activities Layout The principie output of the wirelister is the materiais needed for input to CALDEC and IDEA The basic item is a connection file CON for CALDEC and for IDEA which list all the wiring connections on the entire board sometimes with power grounds and terminators sometimes without depending upon the stage of the process This fiie should usuaily be on paper tape for CALDEC and on DECTAPE for IDEA but requirements may vary The other materials qenerated by WL are printouts T first by the designer to check his design and correct errors and then by CALDEC IDEA people for reference purposes These include wirelist WL a wirelist summary WLS a yii eh pin utilization WLU and a component parts list s With this package the user should of course suppiy a set of circuit schematics for the board must also prepare cover sheet CVR listing any special directions such minimum or maximum lengths for
8. 2080 109K ECL dips CK124 MCABD2 11 Venus celis C330 MOSBOD Ali MOS dips 36179 BlOCK Block diagram symbois FiOW Flow chart symbols PERT PERT chart symbols MECH Mechanical parts fan etc UA Symbols for Unit Assembly drawings SHAPES Forms for constructinq bodies MISC Miscellaneous shapes MOSCAP Special MF2 capacitors GNDCAP Special KL1 capacitors To draw circuit schematics the user invariably requires more than one library Hence for convenience there are top level libraries that contain only pointers to sets of libraries so that getting a top ievel library is equivalent to getting all of the libraries in the set This is the preferred method of accessing standard libraries Present top libraries and the libraries point to are these PTTL STTL HTTL PARTS NCOMP CMOSBOD CMOS1 CMOSBOD PARTS NCOMP E ECLI _ ECLBOD PARTS NCOMP MCA2 MCABD2 NCOMP MOS MOSBOD expansion expected MOSCAP and CNDCAP contain pointers to PARTS and NCOMP 5005 OVERVIEW 48 49 SUDS OVERVIEW Refer to D FD SUDS 94 OVV1 Engineering Is where the design of a P C board starts The Engineer Starts by doing rough sketches of circuit schematics When he has completed the sketches he submits them to SUDS for processing SUDS The SUDS operator Engineer Technician Drafter wiil convert the above sketches to formai drawings usinq the SUDS automated drawing program Once the drawings ha
9. CALDEC IDEA PCLS SAGE 2 simulator multiwire or wirewrap without ever hand coding a wirelist For the user the most significant factor is that the product of the system is data fiies that can be handled by a computer How is it used The Stanford University Design System SUDS is confiqured to run on either DECsystem 19 29 operating Systems with graphics terminais 5005 was specifically designed for schematics but its data structure and command language are general enough to support a veritable multitude of appiications from fiow charts floor plans and biock diagrams to logic and circuit schematics In addition SUDS has an extremely powerful Macros command repetition facility and a convenient set mode that allows a subset of schematic elements to be manipulated as a singie item The SUDS singie key stroke command type language may initially feel cumbersome but the 5005 user will quickly become adapted to the Stanford and the total Stanford NYSE Design dens m y Reduction of High Design Time and Cost In generai SUDS or most any automated schematics system reduces the high design time and cost associated with getting a product out It accomplishes this SUDS Eliminating the manual re translation of data represented by a schematic parts list wire list into a machine readable format for subsequent CAD processing Eliminating the manual re drawing of print sets to standaris
10. ERROR LEVEL C WLS INFO Wi rn CHANGE ID OF CURRENT WIRELIST RENAME WLSSEL WRITE WLS FILE AND SELECT CATEGORY OS WRESIS OUTPUT FILE FOR RESISTOR DRAWING MODE OR DIF SUR MODE AVAILA LIST AVAILABLE NOMENCLATURES CLEAR CLEAR CORE EXCEPT FOR RESIDENT DEFS ont CALL DUT DSKIN ACCEPT TTY INPUT FROM DISK NSKHLO HOLD DISK INFUTCCLOSES FILE DSKCON CONTINUE DISK INFUT IOREOPENS FILE READS TO LAST POSITION USKSKF SKIP OVER LINES IN DSKIN FILE ECL DEFAULT FIN TYPES TO ECL IN MznIP COMMANI THIS TABLE T WC INPUT WIRE RULE CHECK DEFINITION FILE LWIRER LIST AVAILABLE WIRE RULES SELECT NOMENCLATURE FAGE SET LINES FER PAGE FOR LISTINGS RESIDE MAKE DECS RESIDENT SAVE SAVE A DUMP FILE TTL DEFAULT TYFES TO TTL COMMAND WIDTH SET CHARACTERS PER LINE FOR LISTINGS UIRERLU SET RESET WIRE RULES WRUREF OUTPUT SOME WIRE RULE CHECK DATA IN USER READARLE FORM SUR MODE T INFUT 1 DEFINITION FROM FILE LES LIST ALL ULF TYPES ON TERMINAL PACRAG SET CLEAR VARIABLE GEOMETRY WIREWRAF PACKAGE TYPE 56 TABLE 5 Runs with LEVEL 9 I O runs that are heavily loaded mm more than one I O pin Inactive inputs Unused extra outputs Runs with no unique prefix possible Runs that LEVEL 1 are overloaded Unused outputs Runs with Runs with Runs with wit
11. memory communication link Old price 24K New price Host J PDP10 512 memory communication link A RPO6 disks LP10 2 magtapes 1919 DECtape 20290 512K memory communication link 2 RM 3 disks l magtape TU77 UNIGRAPHICS PDP11 70 512K memory communication lines 4 work station graphic terminal 2 RM 03 l magtape l piotter unigraphic Ssoftware 2 spares Unigraphic licenced Software price being negotiated on substantial Savings on total cost of system graphic terminal 22 38K 47K 9K 24K 37K 37X 293K 53K O 319K s 822K 23 APPLICON PDP11 34 64K memory Applicon software 1 m ijtape 1 large disk 2 graphic raster display 2 12x12 tablets 34x44 tablitizer terminal 250K VAX BASED LAYOUT SYSTEM Development system only VAX 11 780 STAR 2 megbyte memory 2 iarge disks l magtape l iine printer communication lines 55 and interface 100K Production iayout system is aimed at a low end VAX C P U Comet Nebula with a totai cost in the neighborhood of 50 S1 K DRW BODIES BODYDEF DIPNAME SUDS LIBRARY DRAWING PROGRAM WIRELIST 42 DIPDEF DIPTYPE 43 SUDS LIBRARY The SUDS Library is comprised of two sub libraries DRW and the DIPS DIP which are used in tandem with each other in preparing drawings and listings necessary in the designin
12. original program MINCUT was specifically for placing the 400 gqate array chips used in the Comet project The new program FINCUT is much more general in that it is not limited to the physical and logicai characteristics of any particular technology Instead for each piacement run it gets the appropriate technological specifications from a pair of library files the grid file GRD which specifies the positions where packages can be piaced on the physicai unit and the logical packages group fiie LPG which defines the characteristics of the components FINCUT exists in several versions geared to specific uses such as MCACUT for MCAS and ECLCUT for PC and multiwire boards with ECL parts The wirelister suppiies the necessary information about the design to Merlin in the S2M fiie and Meriin returns the optimal dip and connector pin positions in the M2S file With this information the designer can go back to SAGE 2 to get real delays and begin a more confident layout Deiay Calculation see D FD SUDS OVVS This software package aiiows the designer to determine the physical deiays between individual signai points in a circuit design either a singie or a set of boards in a back piane From the SUDS wirelist file and the CALDEC IDEA output DLY creates a database that represents the physical hardware as it would be buiit and from that CAL calculates ail signai propagation times taking into account gate delays wire iinks and e
13. their own process flow refer to D FD SUDS 0 FLOW This should include the checks to be performed and the functions with long lead times e g library additions purchase specs etc along with the normal processing may take a bit of time but we are confident this time spent up front will more than compensate for itself through lack of lost time later So What is the Su ested Module Design Process Using SUDS A The best time to capture the information schematic is during it s creation when you are scribbling on envelopes and changing logic significantly At this time SUDS can be operated by the Engineer or technician The best environment to aliow this is the 5005 terminal right in neat the lab B When schematics have been developed to the breadboard Stage a wirewrap board can be produced a matter of days or a quick and dirty P C layout in weeks both using the data base created in A by the origina designer C During debug groups of changes are entered to the on iine SUDS data base This assures the data base always matches the breadboard I D After debug the final data base from the debugged schematics is sent directly to P C layout with no hand coding At this time the print set may have to be brought to DEC Standards However here as in any stage in the game two versions of the data base can be compared automaticaily and a wirelist of the changes repo
14. using DL11 s and an asynchronous communications system In either case a GT40 or GT69 graphics terminai may be used The host system must be DECsystem 14 in CADNET for pMCll configuration or any DEC10 or 28 for the DC11 communications B Software SUDS is written in MACRO 10 assembler language is heavily conditionalized to allow for different configurations and operating systems ie TOPS 1 or TOPS 20 The only special systems software needed is the PGP DMC 11 communications System standard on all CADNET machines In both communication configurations there is piece of Software that is resident in the SUNS terminal VT 5G or NVT05GC that handles the keyboard and display This is down line loaded from the host 19 or 20 or loaded from local disk storage The current drawing program is GCD Also data bases are ali stored as disk BUTTON BOX pem PEN PROGRAMMABLE GRAPHICS PROCESSOR FIGURE 2 2 SUDS SYSTEM USERS STATION ST HARDWARE COMPONENTS OF CAD TOOLS AND APPROXIMATE COST OF TOOLS GEMS PDP8E 24K memory DECtape VT01 A scope Bendix digitizer CALDEC 5 95K MEMORY 4 SCOPE RF15 RS909 _ SUDS PDP11 34 32K memory communication link VR17 LC VT11 8065 only PDP11 69 64K memory communication link 550 SUDS or IDEA Old price Must have a PDP10 or 2020 host New price IDEA Terminal PDP11 49 64K
15. 05 PROCESS See D FD SUDS 0 PRC3 OBTAIN PPN PPN number can be obtained by filling out a CADNET operations access form and submitting it to computer operations REVIEW PARTS LIST Review Parts List to insure that ail information on the parts iist 15 contained in the SUDS Library SUDS LIBRARY Contains the defined graphics symbols and the electrical characteristics of components RUN GCD GTD Puts you into the SUDS drawing program CREATE DRW FILE The DRW file represents a drawing circuit Schematic fiow and block diagrams floor pians etc which is generated by caliing bodies from the SUDS Library DANGLE POINTS XDA Checks for two types of dangie points a stand alone point which has no iogical function it just clutters up the DRW fiie b A line that has missing signal name wili have a dangle point error message POLARITY CHECK XPOLCK Checks for poiarity errors This command checks the DRW fiie for polarity errors such as high signai connected to iow signal b A signal name that has the high indicated in the name but connected to a iow input output of a body or in reverse _ PLOT DPL Is the process by which the SUDS designer generates a DPL file which is used as the input into the p piot program mE WIRING DIAGRAM XEL WD Is the process by which the SUDS designer generates a WD fiei which is used as an input into the Wireiister program _
16. AS NET FILE TO MULTIWIRE SYSTEM QUTPUT RESC CONNECTION i Lor ENABLE MULTIPLE SIGNAL REFERENCES QUTPUT Wik FILE OF SINGLE CARD F R INPUT SAGE2 S ATOS QUTPUT FILE OF ALL CARUS FOR INPUT TU SAG E GEIE CHECK FOR 005 SIGNAL NAMES FOR PARTICULAR MAKE SIGNAL SUMMARY OUTFUT SMP FILE TO GEC WIRELISTER OUTPUT WIR FILE FOR INPUT TO SAGE SIMULATOR REAL TAL FILE TEMPLATE GENERATE OUTPUT FI QUTPUT SIGA LIST FOR GREAT SIGNAL CHANGE OUTPUT SR SCHEMATIC REPRESENTATION FOR MODULE TEST WRITE 8 ASK ABOUT SPEC Le LU FEATURES OUTPUT FOR GREAT SIONAL NAME CHANGE SELECT Orrin peret CURFENT STATUS Yid Kao a aec pedin s lt lt I HT 46 EP VI Paul ENED QUININGU RUN C L TERMLI WRITE TERMINATOR TEST FOINT LIST TEST WRITE CARD TESTER FILE 55 TLE OUTFUT FILE FOR INPUT TLE TRMUDC MAKE UML FILE FOR TERMINATOR REFERENCE DESIONATORS EY Uwr NG 2 DRAWING WIRELISTS TRMWLC UML FILE FOR UFDATING TERMINATOR REFERENCE IESIGNATORS HY Lu DRAWING WIRELIST TO F WIRELIST USAGE COUNT FREE STORAGE USAGE USEI USE D WIRELIST USEFC USE PC WIRELIST VGSIMP OUTPUT BOARD TO WIRELISTER WCOL OUTPUT CAL FORMAT FILE FOR DLYEI AND DLYSRT WLELUL WRITE FILE SELECTING
17. NEL SUMMARY CONNECTION LIST MAKE CONNECTORS SUMMARY DUTPUT CS CIRCUIT SCHEMATIC NETWORK FILE FOR WRLCOM GOARE SET DEFAULT DEVICE FOR INFUT ONLY SET DEFAULT DIRECTORY FOR INPUT ONLY SET DEFAULT DIRECTORY FOR INFUT ONLY QUTFUT ALL LOCS WITH FOWER GROUND PINS TO FILE OUTPUT ZUM FILE TO REDISTRIBUTE REFERENCE DESIGNATORS BY rpg QUTFUT STG D LASAR STIMULUS WIRELTST WL FILE INCLUDE WIRE DELAY FILE DATA UUTFUT FILE FOR Anu nELETES TO TLE LOGIC ERROR SUMMARY BACK TO D FRINT FILE LIST FOR CARI QUTPUT LIST OF CONNECTOR FINS FOR UPDATING DIRAUINGS SET CURRENT AT WHICH HEAVILY LOADED OCCURS ENABLE WIRE LIST INFUT ERRORS TO GO TO FILE ENABLE DISABLE CHECKING OF LAYOUT MAKE FARTS LIST SAME AS PART WRITE UL AND WLU FILES SET MARGIN FOR RUN OVERLOAD ERROR WRITE S2M FILE FOR INFUT TO MERLIN PLACEMENT SYSTEM WRITE MIL FILE FOR NEWFUN FUNCTIONAL MODEL GENERATION MAKE MASTER FARTS LIST FROM FILES OUTPUT BOARU FILE TO MULTIWIRE SYSTEM OUTPUT SUMMARY OF FING IN NETS FILE WRITE PIN TERMINATION SUMMARY MAKE PARTS LIST SAME AS MANE TAR PARTS LIST FILE FOR INFUT TXT2F WRITE ASI ILE FOR ASI S FRANCE WIRE URAP SYSTEM ENABLE SIGN PREFIX CHECKING WHITE SME VILE WITH Y FOWER FINS IN IT QUTPUT BOARN INNER LAYER INFO
18. Name Change Program Automaticaily assigns prefixes to signai names J E Ei nau COMMAND MEANING TYPE THIS LIST 4 54 MOTE gt AS IMPL BOS BRFILES RLCOMF BLIST HMANAL BMULTI EFRINT JS TMP L GS UM M EREE HEE EEN CR MUL D LP UM Yl S AR Bt YL ST CO SUM ILES e LAYOUT ON yl L BERLIN HOREL HEART MUL T IU NETSLM OUTSLIM HART PRANCE i RECHK FS THE OMULT SAGE SAGALA S IGCHN S1LOSUM MELE SIMULA SFFILE SFREFI SK SSIMFL 9 SPARE F SM gt Ze WRITE FILE TO SET AUTOMATIC PIN RULES F R FULLDOWNS WRITE SME FILE BUT ASSIGN REAL FIN NAMES IN PLACE OF TUM pig cadi QUTFUT 765 CIRCUIT SCHEMATIC NETWORK FILE FOR URLCOM CBACNTaMU PRINT FILE LIST FOR BACKFANEL WRITE BLC FILE COMPARING TO BACK WIRELISTS BACK PANEL WIKI LIST WRITE RL AND BLS FILES NETS FILE TO MUL TIWIRE SYSTEM OUTPUT BACKRANEL INNER LAYER INFO AS NETS FILE TO MULTIWIRE YS PRINT BACK SIGNAL WRITE RSE b ILE SELECTING ERROR LEVEL C BS INFO WRITE FILE INCLUDING ALL FINS WRITE RS FILE ANT SELECT CATEGORY 5 BACK PA
19. There are three programs that the wirelister will generate input to which can reduce time and cost of a design They are the Logic Simulation Piacement Optimization and Deiay Caicuiation au en Logic Simulation D FD SUNS A oVV3 One of the products of the wireilster is a WIR This is the input to the SAGE 2 iogic simulator which heips the user determine whether the logic on a board or chip really works before going ahead with Layout SAGE 2 simulates the hardware of individual gates and iogic subsystems with the abiiity to inspect the interaction between individual gates in real time to determine whether logic actually does what it was designed to do entire system can aiso be simulated with inspection at levels higher than individual gates similar wirelister output the NWS file is used by the VOTE simuiator which tests the effectiveness of diagnostic test patterns programs and microcode In the next both simulators wiil use the same input Piacement Optimization D FD SUDS a owa Since both CALDEC and IDFA use placement procedures that are particularly automated layout can be expedited making prior use of the Merlin automatic piacement optimization System These programs heip the designer determine the optimal position of circuit elements from critical parameters supplied by the designer and known characteristics of the materiais E ad even the capacitance of metal runs 90 The
20. certain runs and whether particular IC s must occupy specific positions on the board In addition CALDEC requires a list CLK of runs of which clock rules apply for IDEA this is taken care of by signal properties in the TLE file d The process of getting a iayout completed may involve several transfers of materiai back and forth If errors are found the package must be returned to the SUDS user for correction r any event a preliminary layout is returned for the user check that everything is where it should be that no _ problems are caused by the way things got iaid SEES and to assign finai component locations 59 SUDS itself has a number of facilities for helping with these activities and there are also associated programs to assist in checking renaming and comparing In some cases the user returns to the drawing program using materials supplied by the wirelister When all the problems have been solved a final routing and clean up pass through CALDEC IDEA generates the finished P C board layout For an ECO the wireiister suppiies a iist of the changes a wirelister compare WDC fiie CALDEC and add delete TLE file for IDEA IDEA can be used for designing individuai MCA chips it is more advanced than CALDEC and can handie many more iayers Then with the input package iimited to the external chip connections CALDEC or IDEA can be used for laying out a P C board containing the chips
21. ck of signal polarities and nomenclature I O pins Manually it wouid be vary time consuming and costly to do the above It allows the user to automatically trace runs The drafter technician would have to physicaiiy trace runs Has many facilities to assist in catching design and documentation errors Has many facilities to assist in catching design and documentation errors 67 Manualiy it wouid invoive the Engineer and drafter technician to manualiy check drawings and design to catch the above errors where SUDS will do it automatically That leaves the Engineer and drafter technician time to do more productive work The major advantage of an automated system is not so much a saving in total drafting as an ability to do a great deal more useful work in the time avaiiabie just having more information on the circuit schematics makes them more valuable to Fieid Service Manufacturing and other users In many cases using SUDS aiiows activities that wouid otherwise be impossible Suppose for example that as a production deadline approaches it is decided the signal prefix used on a qroup of a dozen drawings is misieading in light of the way the design has evolved manuai drafting department wouid simpiy inform Engineering that nothing couid be done about it But an automated department would have just SUDS search through the files for all instances of the prefix and change them Some Engineers have become adept enough a
22. epe mones and te for the time You use ama _ DEC SYSTEM IP CADNET CONFIGURATION Disk ps MAIN _ MEMORY LERS s e a srsrEMS DISK PACKS T x Be ae MONITOR FROGRAMS GECONDARY MEMORY PROGRAMS VvI 56C vea une lue av GOD DELETE 362 760 362 761 ETC FIGURE 2 1 005 SYSTEM CONFIGURATION HIGH SPEED LINE PRINTER DIRECTORY 362 120 4 DRY USERS PEN EOS WITH DATA FILES 864 DRW 14 PROGRAMMABLE GRAPHICS SUDS USER STATION Hardware The basic SUDS system user station is a subsystem comprised of a program that links with internal system programs to communicate through the DECsystem 10 to display a SUDS designer s layout on a programmable graphics processor PGP60 The PGP68 is comprised of an 11 34 minicomputer attached to a VS69 graphics display and an LA35 teletype The SUDS designer aiso has the option of using a lightpen and button box which are attached to the PGP6A as a means of interacting with the graphics display tube see figure 2 2 Currentiy there are two basic confiqurations supported by CADSE a PGP configuration using DMC 11 communications and a GT40 like system
23. g of P C boards SUDS DRW The SUDS DRW library consists of a collection of DRW files which Contain weil defined graphic symbols and their pin identifications These symbols are used by the designer to create graphic presentations on the VS60 display Depending on the fiie selected from the library the designer may have access to electrical symbols or symbols used in designing flow charts block diagrams and floor pians Figure 3 1 contains some of the electrical symbols stored in the DRW library DIPS DIP The purpose of the DIPS DIP iibary is to provide information on the electricai characteristics of the components represented by the DRW library symbois Each file within the DIPS DIP library is automatically associated with a specific electricai graphic symbol from the DRW file whenever that symbol is used This means that the output will contain not only the DRW symbols but the associated DIPS DIP files other computer programs SAGE IDEA CALDEC MULTIWIRE etc will be able to test and check the electrical properties of the compieted design for accuracy When the designer is using an electrical symbol he has the option of referencing the associated DIPS DIP file to add or extract additionai information For example assume the designer is working with l4 pin IC part 819 05575 00 the DRW library this part is represented as four gates with the same symbol see Fiqure 3 2 To distinguish one gate from another t
24. ger 223 8083 Cindy Pekkaia Training Coordinator ML4 2 E99 223 9719 Tig Richardson CADSE Support Supervisor 3 5 728 5005 Software Release 223 3325 Norm Rheault SUDS Trainer ML4 2 E998 223 8789 Tom Witowski Library Support MLA 2 E960 SUDS ALM 223 4242 Jim Fleming Engineering Process ML4 2 E90 EN Systems S 223 2287 pat Barry IDEA Trainer _ ML4 2 E906 x PEE _ 223 6157 ECO Process Systems MLA 2 E90 22323172 Moe Marchand 2S IDEA Trainer EE ML4 2 E90 223 5235 Don DiMatteo Trainer ML4 2 E90 223 2438 John Hartiing 5008 Support B NEL BS Manager E 522 2203 Dick Helliwell SUDS Support Father PLUS Fs ee v v of SUDS Software AN I 522 2009 Engineer ET g 2 George Bourbeau SUDS KR I cx uide pru cg IUE aire v eee gt prais 1 6006 Support v 70 CX 522 ans 12 5005 SYSTEM CONFIGURATION CADNET SYSTEM DESCRIPTION 11 the SUDS programs are run on CADNET systems and so it is necessary to understand how it functions and how to communicate with it The following information is a brief and simpie explanation of the CADNET system and how it serves the SUDS user The CADNET system on which the 5005 run on is a DEC system 1 time sharing system that contains XXXK of core ma
25. gns pin numbers and reference designations which may already have been done by the Engineer In the layout process the Engineer may submit design changes which wiii extend the compietion date of the board Upon completion of the board the P C designer will generate a UML fiie that will contain all his iayout changes will submit this file to SUDS The SUDS operator will process the UML fiie with the DRW files circuit schematics This process automaticaliy updates the SUDS DRW files Once the SUDS operator has completed the above he wili process the DRW files through the drawing and wirelist programs The wirelister is then used to generate a CS file circuit schematic representation that is then submitted to IDEA The P C designer wili use the 5 fiie to varify that the SUDS drawings and board are compatabie they are not the above process has to be repeated If they are compatable then the soara is submitted to production 5005 CALDEC see D FD SUDS 0 PRC2 Is the same process as SUDS to IDEA except for the UML process At that stage the P C desginer generates an RL amp AH tape The tape contains the oid fiie originai file submitted to designer and new file fiie with designer changes The tape is submitted to SUDS It is then processed using the RENAME program which automatically updates all the DRW files The drawings and board varification process is the same as 5005 to IDEA 64 50
26. h wire Runs with Runs with Runs with Runs with Runs with Flip flop more than one pull up wire or warnings all outputs on same DIP wire or warnings all outputs on different DIPs I O runs or warnings incorrect or missing signal prefixes no polarity for signal names more than one terminator questionable terminator delay values not in recommended range output driving flip flop inputs of other DIPs Runs with Runs with Runs with Runs with Runs that LEVEL 2 NO Drive no HIGH drive no LOW drive UN or NC pins need termination ECL runs with no terminator rules Runs with Runs with Runs with Runs with runs that don t match terminator rule pull down not needed missing pull down pull down value not found in delay data Runs with pull down value found but no delay data for fan in fan out Runs with more than 2 mA of pull down more than four outputs _ 1 0 runs with lower level inputs Runs with Runs with Runs with Runs with Runs with Runs with no inputs or outputs inputs and or outputs connected to power output connected to ground power connected to ground mixed voltages ECL connected to TTL Unnamed I O runs Runs with termination rules signal property conflicts LEVEL 3 WIRELISTER 57 58 THE WIRELISTER PROGRAM The Wireiister produces materiai for Wirewrap for CALDEC or IDEA to generate P C board layouts for the Meriin automatic
27. he designer can reference the associated DIPS DIP file 749 the number shown within the symbol to acquire the listing in Table one The designer can then use the next to last column of the listing called section to label the gates in their appropriate order this case the gates would be numbered as shown in Figure 3 2 For another example assume the designer wishes to obtain the part number for a 1000HMS resister he is using shown in top row of Figure 3 1 referencing the DIPS DIP RES fiie the fiie for all standard resistors the designer can obtain the standard type listing shown in Tabie 2 The designer can then reference the p subiisting to obtain the 13 00229 00 part number 44 FIGURE 3 1 Samples of Electrical Symbols Found n the SUDS DRW Library Y2 GNO 12 485 RES d a i 1288 19 F T igav T ww N orcoE 0100 P ZENER ZENER P t A ameen NUNGER NUMBER NUNGER Sv SX Sv SY 2 X 74 5 74998 I 74401 743881 74566 e M g X y 6 e x a 8 m lt P 8 4 m 2 Dr uS 5 3 4 Tru s 2 DE F7400 7400 7400 SUB MOLE 3 2 Presentation of Part 19 05575 980 PIN ORDER 7406 SUDS ORW FILE NO BEFORE PIN DESIGNATION PIN
28. hes have been reviewed then go on to the Drawing Program Drawing Program Is mostiy for actuaily creating drawings but it also has some features that heip in the design process e g it automaticaliy keeps track of signal polarities and nomenclature I O pins and it has commands that aliow the user to trace runs It also checks for polarity and dangie errors Closely associated with the Drawing Program is the Plot and Wireiist E Plot Program Creates the input fiie DPL for various hardcopy piotters Wirelist Program Creates the input fiie C WD for the Shea Tau It recieves input generated in the Drawinq Program and automatically generates wirelist files WL WLU WLS PRT WL Wirelist WLU Pin Utilization WLS Wirelist Summary PRT Component parts List 53 The 1 155 Program has two main functions It is used to create the multitude of files that serve as input to other CAD processes See Table 4 It has many facilities to assist in catching design and documentation errors These errors will appear in the wirelist files See Table 5 The final stage in the SUDS process just before reiease is the generating of a cap drawing CAP DRW and prefixing all the signal names There are two programs that will create them automatically the Cap and Great Name Change programs Cap Program Automaticaliy generates a cap drawing showing ali the liter caps that are on board Great
29. in memory a monitor program that schedules and allocates processing time and memory required for each user Time sharing enables multipie users to have access to a computer system at the same time by sharing the resources of the computer between users In addition to main memory the DECsystem 10 provides secondary memory in the form of Disk Packs These disk packs are used for storing many types of data as well as allocating each user a maximum amount of unique disk blocks for fiies that may be created while running programs see figure 2 1 In order to use the CADNET sytem all SUDS users must first obtain a project programmer number PPN PPN provides the user with three important functions 1 working area on disk where the user can store data files created by running programs Other portions of the disk will be used for other PPN s to store programs and data files 2 The user will identify this area by a unique PPN a number representing a project and the idividual s number seperated by a coma e g 352 120 3 To protect each user from others a unique password is given to each user when the PPN is assigned fen Y Each time a user runs on the CADNET system they are required to iog into the computer This process will cause the computer to ask the user for a PPN password cost center and charge number This is necessary to tell the computer where your files are stored and what S
30. inates of pin l of each dip position a package fiie PKG that gives the coordinates of all other pins relative to pin 1 for each package type and WL produced assignment fiie ASG that teils what styie package occupies each position A similar system using the SMP files for ali of the boards but with internal connections deleted i e containing oniy I O pins is employed for laying out the background wirewrap KPL see D FD SUDS 0 OVV6 The parts information on the SUDS database PRT is used as input to the KPL program The benefits of using this program are A Fliminates manual input to KPL human errors Minimizes document errors number quan ety and reference designator on KPL C Reduced time and cost in generating a KPL D Information sent to the KPL will be consistent 5005 PROCESSES 6008 TO IDEA SUDS TO CALDEC 2 63 SUDS TO IDEA CALDEC The wirelister qenerates the materials need for input to CALDEC and IDEA The basic item is a connection file CON for CALDEC TLE for IDEA which list ali the wiring connections on the entire board sometimes with power grounds and terminators sometimes without depending on the stage of the process This file should usuaiiy be on paper tape for CALDEC and on for IDEA but requirements may TO IDEA see D FD SUDS A PRC1 The wireiister generates the TLE CMD file that inputs into IDEA The P C designer lays out the M and assi
31. ircuit design either a singie board or a set of boards in a backpiane P C Design The use of more up to date interactive Computer Aided Design CAD System by P C Designers at DEC Computer Aided Design CAD System is a combination of Hardware Computers and Software programs developed to save designers the time and effort spent on tedious manual tasks Presently IDEA and CALDEC are the two CAD systems being used bY the CAD designers Verification The process by which the designer insures that the drawings and P C board are compatible The P C Designer generates files that will automaticaily update SUDS drawing files Once the SUDS Designer has compieted the update he generates a file that is submitted to P C Designer The Designer then uses this file to verify that the drawings and the board are compatible Once the verification has been completed the board is released to PERCE 5005 51 52 5105 Refer to D FD SUDS 2 OVV2 SUDS is comprised of three basic steps the SUDS Input Drawing Program and the Wirelister SUDS Input Ail projects start with a parts list and sketches The first thing to do is check to see if all the parts lists are in the SUDS library If not submit a SUDSER form for submitting new parts to the SUDS library group for impiementation of new parts Then check sketches to make sure that all information to do the drawing is on them Once the parts list and sketc
32. rted E Finally before Limited Release LR the data 11 artwork for manufacturing can be compared to the wirelist from the Engineer s print set assuring a match Available SUDS Services Library Support Library support means a central group that enters and helps define new bodies parts into the SUDS library and causes it to be distributed to all sites All user library parts requests see Appendix 1 are to be submitted to Engineering Information Control E I C library group with preferred drawing shape specification for the part DEC Spec if it exists and a project name and charge number Training Training is provided by f ginesting Information Control Please contact the Training Coordinator ML4 2 E9 DTN 223 9719 to receive a course catalog and or related periodicals ona continuous basis Documentation the oniy documentation is SUDS TXT written by Dick M Heliiweil Digital Mariboro The LCG Group Mariboro is in the process of writing a total SUDS User Guide with complete definitions of all SUDS commands During training classes a comprehensive training user manual will be made availabie to all trainees to hasten the learning process This text is oniy an introduction in how to use BERE SUDS Design 19 KEY 5005 PEOPLE The following is a list of key people and their areas Name Punction Location Bob St Cyr CAD Tool x ML4 2 E90 Mana
33. t to programs CAP PROGRAM Is a program that automaticaily generates a drawing DRW showing all filter caps that are the board 55 Conclusion The days of the Engineer designing with rough sketches of circuit schematics changing them frequently and scribbling directions to the drafter ail over them are numbered An automated design system eliminates much of the Effort required to produce a finished drawing Sources of error in communication between Engineer P C designer and drafter technician Drafter s Technician s erasing or sticking an added circuit element way off at the edge disconnected from its associated logic Instead he just changes the file and plots anew Inconsistencies in drawings symbols iettering and iine thickness To the user the most significant factor is that the products of the System are data fiies that can be handied by a computer every hardcopy of a drawing is simpiy a copy there is no original paper This means much shorter turnaround time both for deveiopment changes and later ECO s It means much greater accuracy speciaily for repetitive operations and common elements used in a number of situations The advantages of SUDS over manual drafting are Much iess drafting is required to transiate a sketch into an initiai drawing Manuaily it would take ten to twelve hours to do a drawing vs six to eight hours if done on SUDS It automatically keeps tra
34. t usinq the system so that they even make minor revisions such as IC substitutions at an office terminai with no graphic dispiay at ali I hope the SUNS Overview has eniightened you to what SUNS is and what it can do for the Engineering and Fngineering Services Community in reducing design time and cost Please feel free to cali me Norm Rheault Ext 2982 3789 MLA 2 E9A for more WHAT IS THE SUGGESTED MODULE DESIGN PROCESS USING SUDS HE BEST TIME TO CAPTURE THE LOGIC INFORMATION SCHEMATIC IS DURING IT S CREATION THIS TIME SUDS BE OPERATED BY THE ENGINEER OR TECHNICIAN B WHEN SCHEMATICS HAVE BEEN DEVELOPED TO THE BREADBOARD STAGE A WIREWRAP BOARD CAN BE PRODUCED IN A MATTER OF DAYS OR A QUICK AND DIRTY LAYOUT IN WEEKS BOTH USING THE DATA BASE DuRING DEBUG GROUPS OF CHANGES ARE ENTERED TO THE ON LINE SUDS DATA BASE TO ASSURE THE DATA BASE ALWAYS MATCHES THE BREADBOARD D THE FINAL DATA BASE FROM THE DEBUGGED SCHEMATICS IS SENT DIRECTLY TO P C LAYOUT WITH NO HAND CODING WO VERSIONS OF THE DATA BASE CAN BE COMPARED AUTOMATICALLY AND A WIRELIST OF THE CHANGES REPORTED THE MIF CAN BE COMPARED TO THE WIRELIST FROM THE ENGINEER S PRINT SET ASSURING A MATCH
35. ve been generated the operator will then run the wirelist program which will automatically generate the foliowing printouts used first by the designer to check out his design and correct errors and then by CALDEC IDEA people for reference purposes WL Wirelist A list of net runs WLU Wirelist Utilization how sonponenee and pins are utilized WLS Wirelist Summary indicates documentation and logic errors PRT E Part List lists all the part numbers and their descriptions that are being used on the P C board 59 Besides automatically generating drawings and wirelist the program will also create the multitude of files that serve as input to other CAD processes Functional Verification At this stage in the flow the Engineer has a choice of either going the software or hardware route Simulation Layout Preparation Software There are three programs that an Engineer can run before going to iayout 1 Logic Simulation Helps the Engineer determine whether the iogic on a board or chip really works before going ahead with layout 2 Placement Optimization Programs These programs heip the designer determine the optimal position of circuit elements from critical parameters supplied by the designer and known characteristics of the materiais inciuding the capacitance of metal runs 3 Delay Caiculation Allows the designer to determine the physical deiays between individual signal points in a c
36. ven stubs Then with DLYED the user can determine the delay structure of his design by inspection of propagation times across individuai elements in each signal path For MCA inspection the CAL file which is equivalent to the output of the CAL LE be generated by the The wirelister aiso generates files that input to programs such as MULTIWIRE l RENEA RY and KPL MULTIWIRE po D FD SUDS 0 OVV6 Utilizing the program parts of the drawing program muitiwire software the MDT package outputs of the wireiister NET and files and the routing rules built into the module wirewrap program see below or FINCUT the user can iayout his own multiwire boards and generate the materials for the muitiwire vendor to produce it Sometimes these serve as prototypes while one waits for the CALDEC IDEA process but where expected voiume is small may be used for the finished product 61 Designing etch board is much more expensive and time consuming than multiwire but etch boards are cheaper to manufacture Thus for only a few dozen units it is probably better to use multiwire whereas for volume production it pays off to layout etch boards WIREWRAP see D FD SUDS 92 OVV6 Another product of the WL program is a SMP file which serves as input to the module wirewrap system These programs have buiit in routing rules and make use of three major inputs piacement file PLC that defies the coord

OVERVIEW

Contents

Download Pdf Manuals

Related Search

Related Contents