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78K/0 Series instruction

1. ener nnne nnn nnn nnn nnn innen nns 85 5 10 Call Return 0 0 93 5 11 Stack Manipulation Instructions 101 5 12 Unconditional Branch Instruction 105 5 13 Conditional Branch 4 0 00 0 107 5 14 CPU Control Instructions sonne mu cc rec ex ceu aaa 116 APPENDIX A REVISION HISTORY 2 123 APPENDIX INSTRUCTION INDEX MNEMONIC BY FUNCTION 124 APPENDIX INSTRUCTION INDEX MNEMONIC IN ALPHABETICAL ORDER 126 10 User s Manual U12326EJ4VOUM LIST FIGURES Figure No Title Page 2 1 Program Counter 14 2 2 Program Status Word Config ration cvs divas To bene Eae ene 14 2 3 Stack Pointer Configuration 16 2 4 Data to Be Saved to Stack eee Ion icut 16 2 5 Data to Be Reset from Stack 16 2 6 General Purpose Register Configuration 18 LIST OF TABLES Table No Title Page 2 1 General Purpose Register Absolute Address Correspondence Table
2. 17 4 1 Operand Identifiers and Description Methods 32 User s Manual U12326EJ4VOUM 11 1 MEMORY SPACE 1 1 Memory Spaces The 78K 0 Series product program memory map varies depending on the internal memory capacity For details of memory mapped address area refer to the user s manual of each product 1 2 Internal Program Memory Internal ROM Space Each 78K 0 Series product has internal ROM in the address space Program and table data etc are stored in the ROM Normally this memory space is addressed by the program counter PC For details of the internal ROM space refer to the user s manual of each product 1 3 Vector Table Area The 64 byte area 0000H to is reserved as a vector table area The program start addresses for branch upon RESET input or interrupt request generation are stored in the vector table area Of the 16 bit address the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses For the vector table area refer to the user s manual of each product 1 4 CALLT Instruction Table Area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruction CALLT 1 5 CALLF Instruction Entry Area The 2048 byte area 0800H to OFFFH can perform a direct subroutine call with a 2 byte call instruction CALLF 1 6 Internal Data Memory Internal RAM Space 78K 0 Series products incorporate the f
3. PSW and the next instruction address 1 are saved to the stack After that the IE flag is cleared 0 and the saved data is branched to the address indicated with the word data at the vector address Because the IE flag is cleared 0 the subsequent maskable vectored interrupts are disabled The RETB instruction is used to return from the software vectored interrupt generated with this instruction User s Manual U12326EJ4VOUM 97 CHAPTER 5 EXPLANATION OF INSTRUCTIONS R ET Return Return from Subroutine Instruction format RET Operation PC lt SP lt SP 1 SP lt 5 2 Operand None Description This is a return instruction from the subroutine call made with the CALL CALLF and CALLT instructions The word data saved to the stack returns to the PC and the program returns from the subroutine 98 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Return from Interrupt RETI Return from Hardware Vectored Interrupt Instruction format RETI Operation lt SP PCH lt SP 1 PSW lt 5 2 SP lt SP 3 NMIS lt 0 Operand None Description This is a return instruction from the vectored interrupt The data saved to the stack returns to the PC and the PSW and the program returns from the interrupt service routine e This instruction cannot be used for return from the software inter
4. system provided that the system conforms to the I C Standard Specification as defined by Philips User s Manual U12326EJ4VOUM 3 The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is current as of August 2001 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under an
5. 4 INSTRUCTION 20 32 4 1 32 4 1 1 identifiers description Methods eese 32 4 1 2 Description of operation column 33 4 1 3 Description of flag operation column eese eene nnne nnne nnns 33 4 1 4 Description of number of 34 4 1 5 Instructions listed by addressing type 34 4 2 Instruction Codes 38 4 2 1 Description of instruction code table 38 4 2 2 Instruction code LIST 39 User s Manual U12326EJ4VOUM 9 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 46 5 1 8 Bit Data Transfer 48 5 2 16 Bit Data Transfer 5 5 51 5 3 8 Bit Operation Instructions 54 5 4 16 Operation Instructions 63 5 5 Multiply Divide Instructions 67 5 6 Increment Decrement Instructions 2 4 0 0 70 57 Rotate 5 5 75 5 8 BCD Adjust Instructions 82 5 9 Bit Manipulation
6. A saddr Saddr offset A laddr16 Low addr High addr A HL A HL byte Data A HL B 111 1011 A HL C 1111010 A byte a co ao Data saddr byte Saddr offset A r 100 1 ReRi Ro r A 100 A saddr Saddr offset A addr16 Low addr High addr A HL A HL byte Data A HL B ak 1001011 A HL C oO a E 100 1010 User s Manual U12326EJ4VOUM CHAPTER 4 INSTRUCTION SET Instruction Group 16 Bit Operation Mnemonic Operands AX word Operation Code B2 Low byte Hig B3 h byte AX word Low byte Hig h byte AX word Low byte Hig h byte Multiply divide 10001000 1000 0010 Increment decrement Saddr offset Saddr offset 70 Rotate 001 000 000 1001 Bit Manipulation CY saddr bit 0 Bo Saddr offset CY sfr bit 0 Bo Sfr offset CY A bit 1 B2B Bo CY PSW bit 0 Bo 0001 1110 CY HL bit o o o o oc o o o 1 B2B Bo saddr bit CY 0 Bo Saddr offset sfr bit C
7. CM PW Compare Word Word Data Comparison Instruction format CMPW dst src Operation dst src Operand Operand dst src CMPW AX word Description The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed e f the subtraction result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe subtraction generates a borrow out of bit 15 the flag is set 1 In all other cases the CY flag is cleared 0 Asa result of subtraction the AC flag becomes undefined Description example CMPW AX ABCDH is subtracted from the AX register and only the flags are changed comparison of the AX register and the immediate data 66 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS 5 5 Multiply Divide Instructions The following are multiply divide instructions MULU 68 DIVUW 69 User s Manual U12326EJ4VOUM 67 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Multiply Unsigned MULU Unsigned Multiplication of Data Instruction format MULU src Operation AX Ax src Operand Description The A register contents and the source operand src data are multiplied as unsigned data and the result is stored in the AX register De
8. our customers Old Company Name in Catalogs and Other Documents On 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 5 5 10 11 12 Notice information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise
9. saddr HL C Note Exceptr Description The source operand src specified by the 2nd operand and the CY flag are subtracted from the destination operand dst specified by the 1st operand and the result is stored in the destination operand dst The CY flag is subtracted from the least significant bit This instruction is mainly used for subtraction of two or more bytes e f the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe subtraction generates a borrow out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 fthe subtraction generates a borrow for bit 3 out of bit 4 the AC flag is set 1 In all other cases the flag is cleared 0 Description example SUBC A HL The HL register address contents and the CY flag are subtracted from the A register and the result is stored in the A register 58 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS AND And Logical Product of Byte Data Instruction format AND dst src Operation dst dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL HL byte nA HL B A saddr A HL C Note Exceptr Description Bit wise logical product is obtained from the destination operand d
10. 15 0 2 1 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 2 2 Program Status Word Configuration 7 0 14 User s Manual U12326EJ4VOUM CHAPTER 2 REGISTERS 1 2 3 4 5 6 Interrupt enable flag IE This flag controls the interrupt request acknowledgement operations of the CPU When IE 0 the IE flag is set to interrupt disable DI and interrupts other than non maskable interrupts are all disabled When IE 1 the IE flag is to interrupt enable El and interrupt request acknowledgement is controlled by an in service priority flag ISP an interrupt mask flag for various interrupt sources and a priority specification flag This flag is reset 0 upon Dl instruction execution or interrupt request acknowledgment and is set 1 upon execution of the EI instruction Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases Register bank select flags RBSO and RBS1 These are 2 bit flags used to select one of the four register banks In these flags the 2 bit information that indicates the register bank selecte
11. CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 3 8 Bit Operation Instructions The following are 8 bit operation instructions ADD 55 ADDC 56 SUB 57 SUBC 58 AND 59 OR 60 XOR 61 CMP 62 54 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS ADD Add Byte Data Addition Instruction format ADD dst src Operation dst CY dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL HL byte nA HL B saddr HL C Note Exceptr Description The destination operand dst specified by the 1st operand is added to the source operand src specified by the 2nd operand and the result is stored in the CY flag and the destination operand dst e If the addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe addition generates a carry out of bit 7 the CY is set 1 In all other cases the CY is cleared 0 fthe addition generates a carry for bit 4 out of bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example ADD CR10 56H 56H is added to the CR10 register and the result is stored in the CR10 register User s Manual U12326EJ4VOUM 55 CHAPTER 5 EXPLANATION INSTRUCTIONS ADDC Add with Ca
12. Description example HL Rightward digit rotation is executed with the memory contents specified by the A and HL registers HL 4 3 4 N NI Before Execution 1010 0011 1100 0101 After Execution 1010 0101 0011 1100 80 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Rotate Left Digit ROL4 3 Digit Rotation to the Left Instruction format ROL4 dst Operation lt 451 7 4 451 3 lt 451 7 4 lt dst s o Operand ROL4 HL Note Note Specify an area other than the SFR area as operand HL Description e The lower 4 bits of the A register and the 2 digit data 4 bit data of the destination operand dst are rotated to the left The higher 4 bits of the A register remain unchanged Description example ROL4 HL Leftward digit rotation is executed with the memory contents specified by the A and HL registers A HL 4 8 4 0001 0010 0100 1000 After Execution 0001 0100 1000 0010 User s Manual _U12326EJ4VOUM 81 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 8 BCD Adjust Instructions The following are BCD adjust instructions ADJBA 83 ADJBS 84 82 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADJBA Decimal Adjust Register for Addition Decimal Adjustment of Addition Result Instructi
13. Low addr High addr A HL A HL byte Data A HL B 0011011 A HL C 0011010 A byte o oO Data saddr byte Saddr offset A r 011 1 rA a 011 O ReRi Ro A saddr Saddr offset A addr16 Low addr High addr A HL A HL byte Data A HL B 0111011 A HL C 0111010 A byte Oo oOo Oo Data saddr byte Saddr offset A r 101 1 ReRi Ro r A 101 0 R2RPo A saddr Saddr offset A addr16 Low addr High addr A HL A HL byte Data A HL B 1011011 A HL C Oo Oo S oo Oo 1011010 User s Manual U12326EJ4VOUM 41 CHAPTER 4 INSTRUCTION SET Instruction Group 8 Bit Operation Note Except A 42 Mnemonic Operands A byte Operation Code B2 Data B3 saddr byte Saddr offset A r 110 12 Ro rA 110 ORR Po A saddr Saddr offset A laddr16 Low addr High addr A HL A HL byte O ojoloj o o j oi o Data A HL B ak 1101011 A HL C 11 0 1 0 1 0 A byte saddr byte A Saddr offset A r 111 1 ReRi Ro rA 111 ORR
14. CALLF 95 CALLT 96 BRK 97 RET 98 RETI 99 RETB 100 Stack manipulation instructions PUSH 102 POP 103 MOVW SP src 104 MOVW AX SP 104 User s Manual U12326EJ4VOUM APPENDIX INSTRUCTION INDEX BY FUNCTION Unconditional branch instruction BR 106 Conditional branch instructions BC 108 BNC 109 BZ 110 BNZ 111 BT 112 BF 113 BTCLR 114 DBNZ 115 CPU control instructions SEL RBn 117 NOP 118 119 DI 120 HALT 121 STOP 122 User s Manual U12326EJ4VOUM 125 APPENDIX INSTRUCTION INDEX IN ALPHABETICAL ORDER A H ADD 55 HALT 121 ADDC 56 ADDW 64 1 ADJBA 83 ADJBS 84 INC 71 AND 59 INCW 73 AND1 87 M B MOV 49 BC 108 MOVW 52 BF 113 MOVW AX SP 104 BNC 109 MOVW SP src 104 BNZ 111 MOV1 86 BR 106 MULU 68 BRK 97 BT 112 N BTCLR 114 BZ 110 NOP 118 NOT1 92 C CALL 94 CALLF 95 OR 60 CALLT 96 OR1 88 CLR1 91 CMP 62 P 66 POP 103 D PUSH 102 DBNZ 115 R DEC 72 DECW 74 RET 98 DI 120 RETB 100 DIVUW 69 RETI 99 ROL 77 E ROLC 79 ROLA 81 EI 119 ROR 76 RORC 78 80 126 User s Manual U12326EJ4VOUM APPENDIX INST
15. None Description The A register CY flag and AC flag are decimally adjusted from their contents This instruction carries out an operation having meaning only when the BCD binary coded decimal data is subtracted and the subtraction result is stored in the A register in all other cases the instruction carries out an operation having no meaning See the table below for the adjustment method f the adjustment result shows that the A register contents 0 the 2 flag is set 1 In all other cases the Z flag is cleared 0 Condition Operation lt CY 0 0 lt 01100000 lt 1 lt 0 lt 00000110 lt 0 lt 0 lt 01100110 lt 1 lt 0 84 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS 5 9 Bit Manipulation Instructions The following are bit manipulation instructions 86 AND1 87 OR1 88 XOR1 89 90 91 92 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOV1 Move Single Bit 1 Bit Data Transfer Instruction format MOV 1 dst src Operation dst src Operand Operand dst src Mnemonic Operand dst src CY saddr bit saddr bit CY CY sfr bit sfr bit CY CY A bit A bit CY CY PSW bit PSW bit CY CY HL bit HL bit CY Flag dst CY PSW
16. 0 to fas CALLF to fao User s Manual U12326EJ4VOUM 21 CHAPTER 3 ADDRESSING 3 1 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by the lower 5 bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC and branched When the CALLT addr5 instruction is executed table indirect addressing is performed Executing this instruction enables the value to be branched to all memory spaces referencing the address stored in the memory table of 40H to 7FH Illustration Instruction code 15 8 7 6 5 10 Effective address 000000000 fo ol 7 Memory Table 0 Low addr Effective address 1 High adar 15 8 7 0 PC 22 User s Manual U12326EJ4VOUM CHAPTER 3 ADDRESSING 3 1 4 Register addressing Function The register pair AX contents to be specified by an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration User s Manual U12326EJAVOUM 23 CHAPTER 3 ADDRESSING 3 2 Operand Address Addressing The following methods are available to specify the register and memory addressing to undergo manipulation during instruction execution 3 2 14 Implied addressing Function This addressing automatically specifies the addres
17. 1 0 1 PSW bit 0001111 HL bit 1 2 001 saddr bit Saddr offset sfr bit BeBiBo 1 0 1 Sfr offset A bit 1 1 O 1 PSW bit 0001111 HL bit 1828 001 16 Low addr High addr laddr11 faz o addr5 Stack Manipulation 44 SP sword 0001 1100 Low byte High byte SP AX 0001 1100 0001 1100 User s Manual U12326EJ4VOUM CHAPTER 4 INSTRUCTION SET Instruction Mnemonic Operands Operation Code Group B2 B3 Unconditional laddr16 Low addr High addr Branch addr16 jdisp AX 1001 1000 Conditional addr16 jdisp Branch addr16 jdisp addr16 jdisp addr16 jdisp saddr bit Saddr16 Saddr offset jdisp sfr bit addr16 O 1 1 Sfr offset A bit addr16 0 111 jdisp PSW bit Saddr16 0001 jdisp HL bit addr16 1 Bi Bo jdisp saddr bit addr16 0 Bo Saddr offset sfr bit addr16 0 Bo Sfr offset A bit addr16 0 Be Bi Bo
18. 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words in relative addressing the value is relatively transferred to the range between 128 and 127 from the start address of the following instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration 15 0 the next instruction of a BR instruction T 15 8 7 6 0 jdisp8 15 0 LL When S 0 a indicates all bits When 5 1 indicates all bits 1 20 User s Manual U12326EJ4VOUM CHAPTER 3 ADDRESSING 3 1 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL laddr16 or BR addr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instructions can be branched to all memory spaces The CALLF addr11 instruction is branched to the area of 0800H to OFFFH Illustration CALL addr16 BR laddr16 instruction 7 0 CALL or BR Low Addr High Addr 15 87 0 addr11 instruction 7 6 4 3
19. addr16 Flag bit ZPSW bit In all other cases Description fthe 1stoperand bit contents have been set 1 they are cleared 0 and branched to the address specified by the 2nd operand If the 1st operand bit contents have not been set 1 no processing is carried out and the subsequent instruction is executed When the 1st operand bit is PSW bit the corresponding flag contents are cleared 0 Description example BTCLR PSW 0 356H When bit 0 flag of PSW is 1 the CY flag is cleared to 0 and branched to address 0356H with the start of this instruction set in the range of addresses 02D4H to 03D3H 114 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Decrement and Branch if Not Zero DBNZ Conditional Loop R1 0 Instruction format DBNZ dst addr16 Operation dst dst 1 then PC PC b jdisp16 if dst R1 0 Operand Mnemonic Operand dst addr16 b Number of bytes addr16 addr16 saddr addr16 Description One is subtracted from the destination operand dst contents specified by the 1st operand and the subtraction result is stored in the destination operand dst e lf the subtraction result is not 0 data is branched to the address indicated with the 2nd operand addr16 When the subtraction result is 0 no processing is carried out and the subsequent instruction is executed The flag remains unchanged De
20. bit In all other cases Description Bit data of the source operand src specified by the 2nd operand is transferred to the destination operand dst specified by the 1st operand When the destination operand dst is CY or PSW bit only the corresponding flag is changed Description example MOV1 P3 4 CY The flag contents are transferred to bit 4 of port 3 86 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS AND1 And Single Bit 1 Bit Data Logical Product Instruction format AND1 dst src Operation dst dst src Operand Mnemonic Operand dst src CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit Description Logical product of bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand is obtained and the result is stored in the destination operand dst The operation result is stored in the CY flag because of the destination operand dst Description example AND1 CY FE7FH 3 Logical product of FE7FH bit 3 and the CY flag is obtained and the result is stored in the CY flag User s Manual U12326EJ4VOUM 87 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Or Single Bit 1 Bit Data Logical Sum OR1 Instruction format OR1 dst src Operation dst dst v src Operand Mnemonic Operand dst src CY saddr bit C
21. is 1 data is branched to 055CH with the start of this 112 instruction set in the range of addresses 04DAH to 05D9H User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS BF Branch if False Conditional Branch by Bit Test Byte Data Bit 0 Instruction format BF bit addr16 Operation PC PC b jdisp8 if bit 0 Operand Operand bit addr16 b Number of bytes BF saddr bit addr16 sfr bit addr16 A bit addr16 PSW bit addr16 HL bit addr16 Description e Ifthe 1st operand bit contents have been cleared 0 data is branched to the address specified by the 2nd operand addr16 If the 1st operand bit contents have not been cleared 0 no processing is carried out and the subsequent instruction is executed Description example BF 2 2 1549H When bit 2 of port 2 is 0 data is branched to address 1549H with the start of this instruction set in the range of addresses 14C6H to 15C5H User s Manual U12326EJ4VOUM 113 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if True and Clear BTCLR Conditional Branch and Clear by Bit Test Byte Data Bit 1 Instruction format BTCLR bit addr16 Operation PC PC b jdisp8 if bit 1 then bit 0 Operand Operand bit addr16 b Number of bytes BTCLR saddr bit addr16 sfr bit addr16 A bit addr16 PSW bit addr16 HL bit
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23. maskable interrupt acknowledgeable status is set by setting the interrupt enable flag IE to 1 Nointerrupts are acknowledged between this instruction and the next instruction e If this instruction is executed vectored interrupt acknowledgment from another source can be disabled For details refer to Interrupt Functions in the user s manual of each product User s Manual U12326EJ4VOUM 119 CHAPTER 5 EXPLANATION OF INSTRUCTIONS DI Disable Interrupt Interrupt Disabled Instruction format DI Operation IE 0 Operand None Description Maskable interrupt acknowledgment by vectored interrupt is disabled with the interrupt enable flag IE cleared 0 Nointerrupts are acknowledged between this instruction and the next instruction For details of interrupt servicing refer to Interrupt Functions in the user s manual of each product 120 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS HALT Pa HALT Mode Set Instruction format HALT Operation Set HALT Mode Operand None Description Thisinstruction is used to set the HALT mode to stop the CPU operation clock The total power consumption ofthe system can be decreased with intermittent operation by combining this mode with the normal operation mode User s Manual U12326EJ4VOUM 121 CHAPTER 5 EXPLANATION OF INSTRUCTIONS STOP M Stop Mode Set Instruction f
24. the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 3067 5800 Fax 01 3067 5899 NEC Electronics France S A Madrid Office Madrid Spain Tel 091 504 2787 Fax 091 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 User s Manual U12326EJ4VOUM NEC Electronics Hong Kong Ltd H
25. 058Y 780228 780308 780308Y 780924 and 780964 Subseries and uPD78011F 78012F 78070A 78070AY 780001 78P0914 780206 and 780208 Deletion of the following versions 78024 78044 and 78044A Subseries Addition of the table of all internal RAM spaces of each model CHAPTER 1 MEMORY SPACE Change of the format of external memory space table Deletion of all information except for information common to the Throughout 78 0 Series for individual product information refer to the user s manual of each product User s Manual U12326EJ4VOUM 123 APPENDIX INSTRUCTION INDEX MNEMONIC BY FUNCTION 8 bit data transfer instructions MOV 49 XCH 50 16 bit data transfer instructions MOVW 52 XCHW 53 8 bit operation instructions ADD 55 ADDC 56 SUB 57 SUBC 58 AND 59 OR 60 XOR 61 CMP 62 16 bit operation instructions ADDW 64 SUBW 65 66 Multiply divide instructions MULU 68 DIVUW 69 Increment decrement instructions INC 71 DEC 72 INCW 73 DECW 74 124 Rotate instructions ROR 76 ROL 77 RORC 78 ROLC 79 ROR4 80 ROLA 81 BCD adjust instructions ADJBA 83 ADJBS 84 Bit manipulation instructions 86 AND1 87 OR1 88 XOR1 89 90 91 NOT1 92 Call return instructions CALL 94
26. CHAPTER 5 EXPLANATION INSTRUCTIONS 5 10 Call Return Instructions The following are call return instructions CALL 94 CALLF 95 CALLT 96 BRK 97 RET 98 RETI 99 RETB 100 User s Manual U12326EJ4VOUM 93 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Call Subroutine Call 16 Bit Direct CALL Instruction format CALL target Operation SP 1 lt PC 3 h SP 2 lt PC 3 L SP SP 2 PC target Operand Operand target Description This is a subroutine call with a 16 bit absolute address or a register indirect address e The start address PC 3 of the next instruction is saved in the stack and is branched to the address specified by the target operand target Description example CALL 3059H Subroutine call to 3059H 94 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS CALLF Call Flag Subroutine Call 11 Bit Direct Specification Instruction format Operation Operand Operand target CALLF 11 Description CALLF Target SP 1 lt 2 5 2 lt PC 2 L SP lt SP 2 PC target This is a subroutine call which can only be branched to addresses 0800H to OFFFH The start address 2 of the next instruction is saved in the stack and is branched in the range of addresses 0800H to OFFFH Only the lower 11 bits of an address are specified with the higher 5
27. CTIONS SET1 Set Single Bit Carry Flag 1 Bit Data Set Instruction format SET1 dst Operation dst 1 Operand saddr bit sfr bit A bit PSW bit HL bit Flag dst PSW bit dst CY In all other cases Description The destination operand dst is set 1 When the destination operand dst is CY or PSW bit only the corresponding flag is set 1 Description example SET1 FE55H 1 Bit 1 of FE55H is set 1 90 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Clear Single Bit Carry Flag CLR1 1 Bit Data Clear Instruction format CLR1 dst Operation dst 0 Operand Mnemonic Operand dst saddr bit sfr bit A bit PSW bit HL bit dst PSW bit dst CY In all other cases Description The destination operand dst is cleared 0 When the destination operand dst is CY or PSW bit only the corresponding flag is cleared 0 Description example CLR1 P3 7 Bit 7 of port 3 is cleared 0 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Not Single Bit Carry Flag NOT1 1 Bit Data Logical Negation Instruction format NOT1 dst Operation dst dst Operand Description The CY flag is inverted Description example NOT1 CY The CY flag is inverted 92 User s Manual U12326EJAVOUM
28. Description The destination operand dst contents are incremented by only one e f the increment result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe increment generates a carry for bit 4 out of bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 e Because this instruction is frequently used for increment of a counter for repeated operations and an indexed addressing offset register the CY flag contents are not changed to hold the CY flag contents in multiple byte operation Description example INC B The B register is incremented User s Manual U12326EJ4VOUM 71 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement DEC Byte Data Decrement Instruction format DEC dst Operation dst dst 1 Operand Description The destination operand dst contents are decremented by only one If the decrement result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 If the decrement generates a carry for bit 3 out of bit 4 the AC flag is set 1 In all other cases the AC flag is cleared 0 Because this instruction is frequently used for decrement of a counter for repeated operations and an indexed addressing offset register the CY flag contents are not changed to hold the CY flag contents in multiple byte operation If dst is the B or C register or saddr and it is not desired to change the AC and CY fla
29. EMORY SPACE xg oen 12 1 1 Spats ee 12 1 2 Internal Program Memory Internal ROM Space serere 12 1 3 Vector Table Ar6a eere nenne A 12 1 4 CALLT Instruction Table Area eiit 12 1 5 CALLF Instruction Entry 12 1 6 Internal Data Memory Internal RAM Space eene enne 12 1 7 Special Function Register SFR 13 1 8 External Memory 1 13 1 9 IEBus Register eee c rara t nana gon mana natn n Cua ano aan nuncu Cas 13 CHAPTER 2 REGISTERS ek ea nose ui 14 2 1 ciel LIMEN cue eda 14 2411 Program Counter PC cri odora 14 21 2 Program status word PSW a cu reu adm kae 14 RE MELCdS4udugcdtgme 16 2 2 General Purpose Registers nerit recur 17 2 3 Special Function Registers SFRs esee een
30. EOH to FFFFH However the SFRs mapped at to FF1FH can be accessed with short direct addressing Operand format Special function register name 16 bit manipulatable special function register name even address only Description example MOV A When selecting PMO for sfr Instruction code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 20H sfr offset Illustration OP code sfr offset SFR Effective address 28 User s Manual U12326EJ4VOUM CHAPTER 3 ADDRESSING 3 2 6 Register indirect addressing Function Register indirect addressing addresses memory with register pair contents specified as an operand The register pair to be accessed is specified by the register bank selection flags RBSO and RBS1 and the register pair specification in instruction codes Operand format Description example MOV A DE When selecting register pair DE Instruction code 1 0 0 0 0 1 0 1 Illustration Memory address specified by register pair DE Contents of memory to be addressed are transferred 7 User s Manual U12326EJAVOUM 29 CHAPTER 3 ADDRESSING 3 2 7 Based addressing Function 8 bit immediate data is added to the contents of the HL register pair as a base register and the sum is used to address the memory The HL register pair to be accessed is in the register bank specified by the register bank select flag RBSO and RB
31. H and to FF1FH respectively The SFR area to FF1FH where short direct addressing is applied is a part of the entire SFR area Ports that are frequently accessed in a program a compare register of the timer event counter and a capture register of the timer event counter are mapped in the area FFOOH through FF1FH and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 See Illustration below Operand format Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data even address only Description example MOV 50 When setting saddr to and the immediate data to 50H Instruction code 0 0 1 0 1 OP code 0 0 1 1 0 0 30H saddr offset 0 1 1 O 50H immediate data Illustration OP code saddr offset Short direct memory Effective address When 8 bit immediate data is 20H to When 8 bit immediate data is to 1FH 1 0 User s Manual U12326EJ4VOUM 27 CHAPTER 3 ADDRESSING 3 2 5 Special function register SFR addressing Function A memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces to FFCFH and FF
32. N OF INSTRUCTIONS 5 2 16 Bit Data Transfer Instructions The following instructions are 16 bit data transfer instructions MOVW 52 XCHW 53 User s Manual U12326EJ4VOUM 51 CHAPTER 5 EXPLANATION OF INSTRUCTIONS M OVW Move Word Word Data Transfer Instruction format MOVW dst src Operation dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src rp word sfrp AX saddrp word AX rp sfrp word rp AX AX saddrp AX laddr16 saddrp AX laddr16 AX AX sfrp Note Only when rp BC DE or HL Description The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand Description example MOVW AX HL The HL register contents are transferred to the AX register Caution Only an even address can be specified An odd address cannot be specified 52 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS XCHW Exchange Word Word Data Exchange Instruction format XCHW dst src Operation dst o src Operand Operand dst src Note Only when rp BC DE or HL Description The 1st and 2nd operand contents are exchanged Description example XCHW AX BC The memory contents of the AX register are exchanged with those of the BC register User s Manual U12326EJ4VOUM 53
33. RUCTION INDEX MNEMONIC IN ALPHABETICAL ORDER S SEL RBn 117 SET1 90 STOP 122 SUB 57 SUBC 58 SUBW 65 X 50 XCHW 53 61 1 89 User s Manual U12326EJ4VOUM 127 MEMO 128 User s Manual U12326EJ4VOUM Although NEC has taken all possible steps essage to ensure that the documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Thank you for your kind support Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Fax 852 2886 9022 9044 Fax 65 250 3583 Korea Japan NEC Electronics Hong Kong Ltd NEC Semiconductor Technical Hotline Seoul Branch Fax 81 44 435 9608 Fax 82 2 528 4411 Taiwan NEC Electronics Taiwan Ltd Fax 886 2 2719 5951 would like to report the follow
34. Rotate Right ROR 3 Byte Data Rotation to the Right Instruction format ROR dst cnt Operation CY dst dsto dstm 1 dstm x one time Operand Operand dst cnt Description The destination operand dst contents specified by the 1st operand are rotated to the right just once The LSB bit 0 contents are simultaneously rotated to MSB bit 7 and transferred to the CY flag 7 0 LI 7 1 Description example ROR 1 The A register contents are rotated one bit to the right 76 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Rotate Left ROL Byte Data Rotation to the Left Instruction format ROL dst cnt Operation CY dsto lt dstz dsim 1 dstm x one time Operand Operand dst cnt Description The destination operand dst contents specified by the 1st operand are rotated to the left just once The MSB bit 7 contents are simultaneously rotated to LSB bit 0 and transferred to the CY flag CY 7 0 Ec Description example ROL A 1 The A register contents are rotated to the left by one bit User s Manual U12326EJ4VOUM 77 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right with Carr RORC Byte Data Rotation to the Right with Carry Instruction format RORC dst cnt Operation lt dsto dst lt CY dstm 1 lt dstm one time Operand Operand dst c
35. S1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bitis ignored This addressing can be carried out for the memory spaces Operand format Description example MOV HL 10H When setting byte to 10H Instruction code 1 0 1 0 1 1 1 0 3 2 8 Based indexed addressing Function The B or C register contents specified in an instruction word are added to the contents of the HL register pair as a base register and the sum is used to address the memory TheHL B and C registers to be accessed are registers in the register bank specified by the register bank select flag RBSO to RBS1 Addition is performed by expanding the B or C register as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format HL C Description example In the case of MOV A HL B Instruction code 1 0 1 0 1 0 1 1 30 User s Manual U12326EJAVOUM CHAPTER 3 ADDRESSING 3 2 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables addressing of the internal high speed RAM area only Description example In the ca
36. Saved to Stack Memory Interrupt and PUSH rp CALL CALLF and BRK instructions instruction CALLT instructions SP SP 3 SP 85 2 SP 5 2 SP 3 PC7 PCO Lower half SP 1 2 register pairs SP 1 2 PC7 PCO nd 2 PC15 PC8 B Upper half _ register pairs E 15 8 PE 1 PSW SP gt SP gt SP gt Figure 2 5 Data to Be Reset from Stack Memory POP rp RET instruction RETI and RETB instruction instructions sp SP gt 7 SP gt register pairs PC7 PCO Upper half SP 1 register pairs SP 1 PC15 PC8 SP 1 PC15 PC8 2 SP SP 2 SP 2 PSW SP SP 3 16 User s Manual U12326EJ4VOUM CHAPTER 2 REGISTERS 2 2 General Purpose Registers General purpose registers are mapped at particular addresses FEEOH to FEFFH of the data memory These registers consist of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H In addition that each register can be used as an 8 bit register two 8 bit registers in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of functional names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because ofthe 4 register bank configuration an efficient program can be created by switching between a regi
37. TIONS PUSH ee Push Instruction format PUSH src Operation When src rp When src PSW SP 1 SP 1 src 2 lt srcu SP lt SP 1 SP lt SP 2 Operand PUSH Description The data of the register specified by the source operand src is saved to the stack Description example PUSH AX AX register contents are saved to the stack 102 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS POP M Pop Instruction format POP dst Operation When dst rp When dst PSW dst SP dst SP lt SP 1 SP lt SP 1 lt 5 2 Operand Description Data is returned from the stack to the register specified by the destination operand dst When the operand is PSW each flag is replaced with stack data None of interrupts are acknowledged between the POP PSW instruction and the subsequent instruction Description example POP AX The stack data is returned to the AX register User s Manual U12326EJAVOUM 103 CHAPTER 5 EXPLANATION OF INSTRUCTIONS MOVW SP src Move Word MOVW AX SP Word Data Transfer with Stack Pointer Instruction format MOVW dst src Operation dst src Operand Mnemonic Operand dst src SP word SP AX Description This is an instruction to manipulate the stack pointer contents The source operand src specified by
38. X BC RP1 DE RP2 HL RP3 sfr Special function register symbolNete sfrp Special function register symbols 16 bit manipulatable register even addresses only Nete saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels even addresses only addri6 0000H to FFFFH Immediate data or labels Only even addresses for 16 bit data transfer instructions addr11 0800H to OFFFH Immediate data or labels addr5 0040H to 007FH Immediate data or labels even addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label RBn RBO to RB3 Note FFDOH to FFDFH are not addressable Remark Refer to the user s manual of each product for the symbols of special function registers 32 User s Manual U12326EJ4VOUM CHAPTER 4 INSTRUCTION SET 4 1 2 Description of operation column rrmoomo9oxr gt PSW A register 8 bit accumulator X register B register C register D register E register H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parent
39. Y 0 Bz Bi Bo Sfr offset A bit CY 1 B2B Bo PSW bit CY 0 B2 Bo 0001 1110 HL bit CY 1 B2B Bo CY saddr bit 0 B2 Bi Bo Saddr offset CY sfr bit 0 Bo Sfr offset CY A bit 1 B2B Bo CY PSW bit 0 Bo 0001 1110 CY HL bit e o Oo o o o o o o o o o co o o o O oilo ojo o o o o o oj o o o o o o o o oj o o o o o o io o o o Jo o o o o o o o o 1 B2B Bo User s Manual U12326EJ4VOUM 43 CHAPTER 4 INSTRUCTION SET Instruction Group Bit Manipulation Mnemonic Operands CY saddr bit Operation Code B2 0 0 1 B3 Saddr offset CY sfr bit 0 Bo Sfr offset CY A bit 1 B2B CY PSW bit 0 Bz Bo 0001 1110 CY HL bit 1 B2B Bo CY saddr bit 0 Bo Saddr offset CY sfr bit 0 Bo Sfr offset CY A bit 1 B2B CY PSW bit 0 0 1 0001 1110 CY HL bit 1 0 1 Saddr offset sfr bit 0 BeBiBo 10 1 Sfr offset A bit 1 B2B Bo
40. Y sfr bit CY A bit CY PSW bit CY HL bit Description The logical sum of bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand is obtained and the result is stored in the destination operand dst The operation result is stored in the CY flag because of the destination operand dst Description example OR1 CY P2 5 The logical sum of port 2 bit 5 and the CY flag is obtained and the result is stored in the CY flag 88 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Exclusive Or Single Bit 1 Bit Data Exclusive Logical Sum Instruction format dst src Operation dst dst v src Operand Mnemonic Operand dst src CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit Description The exclusive logical sum of bit data of the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand is obtained and the result is stored in the destination operand dst The operation result is stored in the CY flag because of the destination operand dst Description example XOR1 CY A 7 The exclusive logical sum of the A register bit 7 and the CY flag is obtained and the result is stored in the CY flag User s Manual U12326EJAVOUM 89 CHAPTER 5 EXPLANATION OF INSTRU
41. bit units 1 8 and 16 differ depending on the special function register type Each manipulation bit unit can be specified as follows e 1 bit manipulation Describes a symbol reserved by the assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified by an address e 8 bit manipulation Describes a symbol reserved by the assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified by an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address For details of the special function registers refer to the user s manual of each product Caution Do not access addresses to which SFRs not allocated an address is erroneously accessed the CPU may become deadlocked User s Manual U12326EJ4VOUM 19 CHAPTER 3 ADDRESSING 3 1 Instruction Address Addressing An instruction address is determined by program counter PC contents The PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing for details of each instruction refer to CHAPTER 5 EXPLANATION OF INSTRUCTIONS 3 1
42. bits fixed to 00001B The program size can be compressed by locating the subroutine at 0800H to OFFFH and using this instruction If the program is in the external memory the execution time can be decreased Description example CALLF 0C2AH Subroutine call to 2 User s Manual U12326EJ4VOUM 95 CHAPTER 5 EXPLANATION OF INSTRUCTIONS CALLT Call Table Subroutine Call Refer to the Call Table Instruction format CALLT addr5 Operation SP 1 lt 1 SP 2 1 SP lt SP 2 lt 00000000 addr5 1 PCL lt 00000000 addr5 Operand Operand addr5 CALLT addr5 Description This is a subroutine call for call table reference Thestartaddress 1 ofthe next instruction is saved in the stack and is branched to the address indicated with the word data of a call table the higher 8 bits of address are fixed to 00000000B and the next 5 bits are specified by addr5 Description example CALLT 40H Subroutine call to the word data addresses 0040H and 0041 96 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS BRK Break Software Vectored Interrupt Instruction format Operation Operand None BRK SP 1 PSW SP 2 lt 1 SP 3 lt 1 0 SP lt SP 3 lt PCL lt Description This is a software interrupt instruction
43. boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin handling related to the unused pins must be judged device by device related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function IEBus is a trademark of NEC Corporation Caution Purchase of I C components conveys a license under the Philips Patent Rights to use these components
44. cal Sum of Byte Data Instruction format XOR dst src Operation dst dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL HL byte nA HL B saddr HL C Note Exceptr A Description Thebit wise exclusive logical sum is obtained from the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and the result is stored in the destination operand dst Logical negation of all bits of the destination operand dst is possible by selecting for the source operand src with this instruction e If the exclusive logical sum shows that all bits are 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 Description example XOR L The bit wise exclusive logical sum of the A and L registers is obtained and the result is stored in the A register User s Manual _U12326EJ4VOUM 61 CHAPTER 5 EXPLANATION INSTRUCTIONS CMP Compare Byte Data Comparison Instruction format CMP dst src Operation dst src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL HL byte nA HL B saddr HL C Note Exceptr Description The source operand
45. d by SBL RBn instruction execution is stored Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When ISP z 0 vectored interrupt requests specified as low priority by the priority specification flag register PR are disabled for acknowledgment Actual acknowledgment for interrupt requests is controlled by the state of the interrupt enable flag IE Carry flag CY This flag stores an overflow or underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution User s Manual U12326EJ4VOUM 15 CHAPTER 2 REGISTERS 2 1 3 Stack pointer SP This is a 16 bit register that holds the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area Figure 2 3 Stack Pointer Configuration 15 0 The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Figures 2 4 and 2 5 Caution Since RESET input makes SP contents undefined be sure to initialize the SP before instruction execution Figure 2 4 Data to Be
46. der certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas El
47. e nnne 19 20 3 1 Instruction Address 55 20 3 1 1 Relative addressing 20 3 1 2 Immediate addressing 21 3 1 3 Table indirect addressing 22 3 1 4 Register addressing iin onerant REUS RAR 23 3 2 Operand Address Addressing 24 3 2 1 Implied addressing 24 3 2 2 Register addressing 25 3 2 3 Direct addressing 5 tini kic aca adn c c E FPE ER KR 26 3 2 44 Short direct addressing iren 27 3 2 5 Special function register SFR addressing eene 28 3 2 6 Register indirect addressing 29 3 2 7 Based 30 3 2 8 Based indexed addressing 30 3 2 9 31
48. ectronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 5 5 User s Manual 78 0 Series Instructions Common to 78K 0 Series Document No U12326EJ4VOUMOO 4th edition Date Published October 2001 CP K NEC Corporation 1995 Printed in Japan MEMO 2 User s Manual U12326EJ4VOUM NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW
49. ent but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers
50. f each product Caution Do not access addresses to which SFRs are not allocated an address is erroneously accessed the CPU may become deadlocked 1 8 External Memory Space This is an external memory space that can be accessed by setting the memory extension mode register This space can store program and table data and be assigned peripheral devices For details of the products in which an external memory space can be used refer to the user s manual of each product 1 9 IEBus Register Area registers that used to control the IEBus controller are allocated to the IEBus register area For details of the products that incorporate an IEBus controller refer to the user s manual of each product User s Manual U12326EJ4VOUM 13 CHAPTER 2 REGISTERS 2 1 Control Registers The control registers control the program sequence statuses and stack memory A program counter a program status word and a stack pointer are the control registers 211 Program counter PC The program counter is a 16 bit register that holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 2 1 Program Counter Configuration
51. g contents the DBNZ instruction can be used Description example DEC FE92H The contents at address FE92H are decremented 72 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Increment Word INCW Word Data Increment Instruction format INCW dst Operation dst dst 1 Operand Description The destination operand dst contents are incremented by only one Because this instruction is frequently used for increment of a register pointer used for addressing the Z AC and CY flag contents are not changed Description example INCW HL The HL register is incremented User s Manual U12326EJAVOUM 73 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Decrement Word DECW Word Data Decrement Instruction format DECW dst Operation dst dst 1 Operand Description The destination operand dst contents are decremented by only one Because this instruction is frequently used for decrement of a register pointer used for addressing the Z AC and CY flag contents are not changed Description example DECW DE The DE register is decremented 74 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS 5 7 Rotate Instructions The following are rotate instructions ROR 76 ROL 77 RORC 78 ROLC 79 ROR4 80 ROLA 81 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS
52. heses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacement value 4 1 3 Description of flag operation column Blank Unchanged Cleared to 0 Set to 1 Set cleared according to the result Previously saved value is restored User s Manual U12326EJ4VOUM 33 CHAPTER 4 INSTRUCTION SET 4 1 4 Description of number of clocks 1 instruction clock cycle is 1 CPU clock cycle fcPu selected by the processor clock control register PCC 4 1 5 Instructions listed by addressing type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROL4 PUSH POP DBNZ 34 User s Manual U12326EJAVOUM CHAPTER 4 INSTRUCTION SET 2nd Operand 1st Operand laddr16 HL byte HL B HL C addr16 laddr16 PSW HL HL byte HL B HL C C Note Exceptr A User s Manual U12326EJ4VOUM 35 CHAPTER 4 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand laddr16 1st Operand MOVWNete sfrp saddrp laddr16 SP Note Only when rp BC DE or HL 3 Bit manipulation i
53. immediate data corresponding to addr5 38 User s Manual U12326EJAVOUM CHAPTER 4 INSTRUCTION SET 4 2 2 Instruction code list Instruction Mnemonic Group 8 Bit Data Transfer Operands r byte Operation Code 0 Ro B2 Data B3 saddr byte 001 Saddr offset sfr byte 011 Sfr offset A r R2 Ri Ro LA Re Ri Ro A saddr 000 Saddr offset saddr A 010 Saddr offset A sfr 10 Sfr offset sfr A Sfr offset A addr16 Low addr High addr laddr16 A Low addr High addr PSW byte 0001 1110 Data A PSW 0001 1110 PSW A 0001 1110 A DE DE A A HL HL A A HL byte HL byte A A HL B HL B A A HL C HL C A Note Exceptr A A r A saddr Saddr offset A sfr 1 Sfr offset A addr16 Low addr High addr A DE A HL A HL byte Data A HL B 10001011 A HL C 10001010 User s Manual U12326EJ4VOUM 39 CHAPTER 4 INSTRUCTION SET Instruction Group 16 Bit Data Transfer Mnemonic Operands rp word Operation Code P1Po 0 B2 Low byte B3 High byte saddrp word Saddr offset Low byte High byte sfrp word Sfr offset Low byte High b
54. ing error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Clarity Technical Accuracy Organization Excellent Acceptable
55. jdisp PSW bit addr16 0 Bo 0001 1110 HL bit Saddr16 1 Bi Bo jdisp saddr bit addr16 0 Bo Saddr offset sfr bit addr16 0 Bo Sfr offset A bit addr16 0 Be Bi Bo jdisp PSW bit addr16 0 Bo 0001 1110 HL bit Saddr16 1 Be Bo 0 jdisp B addr16 jdisp C addr16 EF E jdisp saddr addr16 Saddr offset CPU RBn 1 1RBi1 RBoO 0 control 0001111 0001111 0001000 0000000 User s Manual U12326EJ4VOUM 45 CHAPTER 5 EXPLANATION OF INSTRUCTIONS This chapter explains the instructions of 78K 0 Series products Each instruction is described with a mnemonic including description of multiple operands The basic configuration of instruction description is shown on the next page For the number of instruction bytes and the instruction codes refer to the user s manual of each product and CHAPTER 4 INSTRUCTION SET respectively All the instructions are common to 78K 0 Series products 46 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS DESCRIPTION EXAMPLE Mnemonic Full name Move MOV Byte Data Transfer Mea
56. known Refer to APPENDICES B and C To check an instruction whose mnemonic is not known but whose general function is known Find the mnemonic in CHAPTER 4 INSTRUCTION SET and then check the detailed functions in CHAPTER 5 EXPLANATION OF INSTRUCTIONS To learn about the various kinds of 78K 0 Series product instructions in general Read this manual in the order of CONTENTS To learn about the hardware functions of 78K 0 Series products See the separate user s manuals Data significance Higher digits on the left and lower digits on the right Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeral representation BINARY XXXX or XXXXB Decimal XXXX Hexadecimal XXXXH User s Manual U12326EJAVOUM 7 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Common to 78K 0 Series Document Name Document No User s Manual Instructions This manual Application NoteNete Basic U12704E Basic U10121E Basic 010182 Note Some subseries may not be covered Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 8 User s Manual U12326EJ4VOUM CONTENTS CHAPTER 1 M
57. lag is set 1 In all other cases the 2 flag is cleared 0 fthe addition generates a carry out of bit 15 the CY flag is set 1 In all other cases the CY flag is cleared 0 e Asa result of addition the AC flag becomes undefined Description example ADDW AX ABCDH ABCDH is added to the AX register and the result is stored in the AX register 64 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS SU BW Subtract Word Word Data Subtraction Instruction format SUBW dst src Operation dst CY dst src Operand Operand dst src Description The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand and the result is stored in the destination operand dst and the CY flag The destination operand can be cleared to 0 by equalizing the source operand src and the destination operand dst e If the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe subtraction generates a borrow out of bit 15 the flag is set 1 In all other cases the CY flag is cleared 0 e Asa result of subtraction the AC flag becomes undefined Description example SUBW AX ABCDH ABCDH is subtracted from the AX register contents and the result is stored in the register User s Manual U12326EJAVOUM 65 CHAPTER 5 EXPLANATION OF INSTRUCTIONS
58. n code Operand format X D L H P and rp be described with absolute names RO to R7 RPO as well as function names X A D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instruction code O 1 1 0 0 0 1 0 Register specification code INCW DE When selecting the DE register pair for rp Instruction code 1 0 0 0 0 1 0 0 Register specification code User s Manual U12326EJAVOUM 25 CHAPTER 3 ADDRESSING 3 2 3 Direct addressing Function Direct addressing directly addresses the memory indicated by the immediate data in the instruction word Operand format addr16 Label or 16 bit immediate data Description example MOV A When setting 16 to Instruction code 1 0 0 0 1 1 1 OP code o 0 1 1 1 1 1 1 1 0 Illustration OP code addr16 lower addr16 upper Memory 26 User s Manual U12326EJ4VOUM CHAPTER 3 ADDRESSING 3 2 4 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word This addressing is applied to the 256 byte fixed space FE20H to FF1FH An internal high speed RAM and special function registers SFRs are mapped at FE20H to FEFF
59. n the range of addresses 0344H to 0443H 110 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Branch if Not Zero BNZ Conditional Branch with Zero Flag 2 0 Instruction format BNZ addr16 Operation PC PC 2 jdisp8 if Z 0 Operand Operand addr16 Description When 2 0 data is branched to the address specified by the operand When Z 1 no processing is carried out and the subsequent instruction is executed Description example CMP A 55H BNZ 0A39H Ifthe A register is not 0055H data is branched to OA39H with the start of this instruction set in the range of addresses 09B8H to 7 User s Manual U12326EJ4VOUM 111 CHAPTER 5 EXPLANATION OF INSTRUCTIONS BT Branch if True Conditional Branch by Bit Test Byte Data Bit 1 Instruction format Operation Operand Mnemonic Description fthe 1st operand bit contents have been set 1 data is branched to the address specified by the 2nd BT bit addr16 lt PC b jdisp8 if bit 1 Operand bit addr16 saddr bit addr16 b Number of bytes sfr bit addr16 A bit addr16 PSW bit addr16 HL bit addr16 operand addr16 If the 1st operand bit contents have not been set 1 no processing is carried out and the subsequent instruction is executed Description example BT FE47H 3 55CH When bit 3 at address FE47H
60. nd Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL A r A HL byte nA HL B saddr HL C Note Exceptr A Description The source operand src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand and the result is stored in the destination operand dst and the CY flag The destination operand can be cleared to 0 by equalizing the source operand src and the destination operand dst e If the subtraction shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe subtraction generates a borrow out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 fthe subtraction generates a borrow for bit 3 out of bit 4 the AC flag is set 1 In all other cases the flag is cleared 0 Description example SUB D A The register is subtracted from the D register and the result is stored in the D register User s Manual U12326EJ4VOUM 57 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Subtract with Carr SUBC y Subtraction of Byte Data with Carry Instruction format SUBC dst src Operation dst CY dst src CY Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL HL byte nA HL B
61. nd Operand dst src Mnemonic Operand dst src MOV byte A PSW saddr byte PSW A sfr byte A DE DE A rA A HL A saddr HL A saddr A A HL byte A sfr HL byte sfr A HL B A laddr16 HL B A laddr16 A A HL C PSW byte HL C A Note Exceptr Flag PSW byte and PSW other operand A operands combinations Description The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand e No interrupts are acknowledged between the MOV PSW byte instruction MOV PSW A instruction and the next instruction Description example MOV A 4DH 4DH is transferred to the A register User s Manual U12326EJAVOUM 49 CHAPTER 5 EXPLANATION INSTRUCTIONS XCH Exchange Byte Data Exchange Instruction format XCH dst src Operation dst lt gt src Operand Operand dst src Mnemonic Operand dst src XCH A r A HL A saddr A HL byte A sfr HL B laddr16 HL C A DE Note Exceptr Description The 1st and 2nd operand contents are exchanged Description example XCH A FEBCH The A register contents and address FEBCH contents are exchanged 50 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATIO
62. ning of instruction Instruction format MOV dst src Indicates the basic description format of the instruction Operation dst src Indicates instruction operation using symbols Operand Indicates operands that can be specified by this instruction Refer to 4 1 Operation for the description of each operand symbol Operand dst src Mnemonic Operand dst src PSW saddr HL A saddr A A HL byte Z PSW byte Z HL C A Flag Indicates the flag operation that changes by instruction execution Each flag operation symbol is shown in the conventions Conventions Description Unchanged Cleared to 0 Set to 1 Set or cleared according to the result Previously saved value is restored Description Describes the instruction operation in detail e The contents of the source operand src specified by the 2nd operand are transferred to the destination operand dst specified by the 1st operand Description example MOV A 4DH 4DH is transferred to the A register User s Manual U12326EJ4VOUM 47 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 1 8 Bit Data Transfer Instructions The following instructions are 8 bit data transfer instructions MOV 49 XCH 50 48 User s Manual U12326EJAV0UM CHAPTER 5 EXPLANATION INSTRUCTIONS M OV Move Byte Data Transfer Instruction format MOV dst src Operation dst src Opera
63. nstructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR 2nd Operand sfr bit saddr bit PSW bit HL bit addr16 1st Operand sfr bit saddr bit PSW bit HL bit 36 User s Manual _U12326EJ4VOUM CHAPTER 4 INSTRUCTION SET 4 Call instructions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ 2nd Operand laddr16 laddr11 addr5 addr16 1st Operand Basic Instructions Compound Instructions 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP User s Manual U12326EJ4VOUM CHAPTER 4 INSTRUCTION SET 4 2 Instruction Codes 4 2 1 Description of instruction code table r rp P e RO 0 AX 1 Ro 0 0 0 0 0 RB1 Tr Immediate data corresponding to bit Data 8 bit immediate data corresponding to byte Low High byte 16 bit immediate data corresponding to word Saddr offset 16 bit address lower 8 bit offset data corresponding to saddr Sfr offset sfr 16 bit address lower 8 bit offset data Low High addr 16 bit immediate data corresponding to addr16 jdisp Signed two s complement data 8 bits of relative address distance between the start and branch addresses of the next instruction to fao 11 bits of immediate data corresponding to addr1 1 to tao 5 bits of
64. nt Description The destination operand dst contents specified by the 1st operand are rotated just once to the right with carry 7 0 mE Description example RORC A 1 The A register contents are rotated to the right by one bit including the CY flag 78 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS ROLC Rotate Left with Carry Byte Data Rotation to the Left with Carry Instruction format ROLC dst cnt Operation lt 4517 dsto dstm 1 dstm x one time Operand Operand dst cnt Description The destination operand dst contents specified by the 1st operand are rotated just once to the left with carry 7 0 Description example ROLC A 1 The A register contents are rotated to the left by one bit including the CY flag User s Manual U12326EJAVOUM 79 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Rotate Right Digit ROR4 ipis Digit Rotation to the Right Instruction format dst Operation lt dst s o dst 7 4 lt 451 3 lt dst 7 4 Operand ROR4 HL Note Note Specify an area other than the SFR area as operand HL Description e The lower 4 bits of the A register and the 2 digit data 4 bit data of the destination operand dst are rotated to the right The higher 4 bits of the A register remain unchanged 7 43 0 N 43 0
65. office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions un
66. ollowing RAMs For details of these RAMs refer to the user s manual of each product 1 Internal high speed RAM Each 78K 0 Series product incorporates an internal high speed RAM In the 32 byte area FEEOH to FEFFH of these areas 4 banks of general purpose registers each bank consisting of eight 8 bit registers are allocated The internal high speed RAM can also be used as a stack memory 2 Buffer RAM There are some products in the 78K 0 Series to which buffer RAM is allocated This RAM is used to store the transfer receive data of serial interface channel 1 3 wire serial I O mode with automatic transfer receive function If not used in this mode the buffer RAM can also be used as an ordinary RAM area 12 User s Manual U12326EJ4VOUM 1 5 3 RAM for VFD display There are some products in the 78K 0 Series to which RAM for VFD display is allocated This RAM can also be used as an ordinary RAM area 4 Internal expansion RAM There are some products in the 78 0 Series to which internal expansion RAM is allocated 5 RAM for LCD display There are some products in the 78K 0 Series to which RAM for LCD display is allocated This RAM can also be used as an ordinary RAM area 1 7 Special Function Register SFR Area On chip peripheral hardware special function registers SFRs are allocated the area FFOOH to FFFFH for details of the special function registers refer to the user s manual o
67. on format Operation Operand None ADJBA Decimal Adjust Accumulator for Addition Description The A register CY flag and AC flag are decimally adjusted from their contents This instruction carries out an operation having meaning only when the BCD binary coded decimal data is added and the addition result is stored in the A register in all other cases the instruction carries out an operation having no meaning See the table below for the adjustment method f the adjustment result shows that the A register contents 0 the 7 flag is set 1 In all other cases the Z flag is cleared 0 Condition Operation to Ao lt 9 0 A lt 9 CY 0 lt lt 0 0 to 4 gt 100r CY 1 lt 011000008 lt 1 0 to Ao 2 10 0 to A4 lt 9 and CY 0 lt 000001108 CY 0 AC 1 to A4 2 9 or CY 1 lt 011001108 CY lt 1 AC lt 1 1 A4 lt 9 CY 0 lt A 00000110B 0 0 to 4 gt 100r CY 1 lt 011001108 lt 1 0 User s Manual U12326EJAVOUM 83 CHAPTER 5 EXPLANATION OF INSTRUCTIONS ADJ BS Decimal Adjust Register for Subtraction Decimal Adjustment of Subtraction Result Instruction format ADJBS Operation Decimal Adjust Accumulator for Subtraction Operand
68. ong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 NEC Electronics Taiwan Lid Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 11 6462 6810 Fax 11 6462 6829 J01 2 Major Revisions in This Edition Throughout Deletion of all information except for information common to the 78K 0 Series for individual product information refer to the user s manual of each product The mark shows major revised points User s Manual U12326EJ4VOUM Target Readers Purpose Organization How to Read This Manual Conventions INTRODUCTION This manual is intended for users who wish to understand the functions of 78K 0 Series products and to design and develop its application systems and programs This manual is intended to give users an understanding of the various kinds of instruction functions of 78 0 Series products This manual is broadly divided into the following sections CPU functions Instruction set Explanation of instructions It is assumed that readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers To checkthe details of the functions of an instruction whose mnemonic is
69. ormat STOP Operation Set STOP Mode Operand None Description This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system Power consumption can be minimized to only leakage current 122 User s Manual U12326EJ4VOUM APPENDIX REVISION HISTORY The following table shows the revision history of the previous editions The Applied to column indicates the chapters of each edition in which the revision was applied Major Revision from Previous Edition Applied to 2nd Addition of the following versions Throughout 78055 and 78P058 and uPD78018F 78044A 78054Y 78078 78083 78098 and 780208 Subseries Addition of the English documentation No to the related documents INTRODUCTION Addition of the IEBus register area uPD78098 Subseries only CHAPTER 1 MEMORY SPACE Addition of the description of the number of clocks when the CHAPTER 4 INSTRUCTION SET external ROM contains the program to the clock column Addition of Notes to the description of the ROR4 and ROL4 CHAPTER 5 EXPLANATION instructions in the rotate instruction OF INSTRUCTIONS Change of the operation of the ADJBA and ADJBS instructions in the BCD adjust instruction Addition of the following versions Throughout LPD78014H 78018FY 78044F 78044 78058F 78058FY 78064Y 78064B 78075B 78075BY 78078Y 78098B 780018Y 780024 780024Y 780034 780034Y 780058 780
70. ress specified by the operand When CY 0 no processing is carried out and the subsequent instruction is executed Description example BC 300H When CY 1 data is branched to 0300H with the start of this instruction set in the range of addresses 027FH to 037EH 108 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Branch if Not Carry BNC Conditional Branch with Carry Flag 0 Instruction format BNC addr16 Operation PC 2 8 if CY 0 Operand Operand addr16 Description When CY 0 data is branched to the address specified by the operand When CY 1 no processing is carried out and the subsequent instruction is executed Description example BNC 300H When CY 0 data is branched to 0300H with the start of this instruction set in the range of addresses 027FH to 037EH User s Manual U12326EJAVOUM 109 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch if Zero BZ i Conditional Branch with Zero Flag 2 1 Instruction format BZ addr16 Operation PC PC 2 jdisp8 if Z 1 Operand Operand addr16 Description e When Z 1 data is branched to the address specified by the operand When Z 0 no processing is carried out and the subsequent instruction is executed Description example DEC B BZ 3C5H When the B register is 0 data is branched to O3C5H with the start of this instruction set i
71. rry Addition of Byte Data with Carry Instruction format ADDC dst src Operation dst CY dst src Operand Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL A HL byte nA HL B A saddr A HL C Note Exceptr Description The destination operand dst specified by the 1st operand the source operand src specified by the 2nd operand and the CY flag are added and the result is stored in the destination operand dst and the CY flag The CY flag is added to the least significant bit This instruction is mainly used to add two or more bytes fthe addition result shows that dst is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe addition generates a carry out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 fthe addition generates a carry for bit 4 out of bit 3 the AC flag is set 1 In all other cases the AC flag is cleared 0 Description example 56 ADDC A A register contents and the contents at address HL register B register and the CY flag are added and the result is stored in the A register User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS SU B Subtract Byte Data Subtraction Instruction format SUB dst src Operation dst CY dst src Opera
72. rupt with the BRK instruction None of interrupts are acknowledged between this instruction and the next instruction to be executed NMIS flag is set to 1 by acknowledgment of a non maskable interrupt and cleared to 0 by the RETI instruction Caution When the return from non maskable interrupt servicing is performed by an instruction other than the RETI instruction the NMIS flag is not cleared to 0 and therefore no interrupts including non maskable interrupts except software interrupts can be acknowledged User s Manual U12326EJAVOUM 99 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Return from Break RETB Return from Software Vectored Interrupt Instruction format RETB Operation PC lt SP lt SP 1 PSW lt 5 2 lt SP 3 Operand None Description This is a return instruction from the software interrupt generated with the BRK instruction e The data saved in the stack returns to the PC and the PSW and the program returns from the interrupt service routine None of interrupts are acknowledged between this instruction and the next instruction to be executed 100 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS 5 11 Stack Manipulation Instructions The following are stack manipulation instructions PUSH 102 POP 103 MOVW SP src 104 MOVW AX SP 104 User s Manual U12326EJ4VOUM 101 CHAPTER 5 EXPLANATION OF INSTRUC
73. s of the registers that function as an accumulator A and AX in the general purpose register area Of the 78K 0 Series instruction words the following instructions employ implied addressing Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values targeted for decimal correction ROR4 ROL4 A register for storage of digit data that undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of the A register and X register is stored in AX In this example the A and AX registers are specified by implied addressing 24 User s Manual U12326EJ4VOUM CHAPTER 3 ADDRESSING 3 2 2 Register addressing Function Register addressing accesses a general purpose register as an operand The general purpose register to be accessed is specified by the register bank selection flags RBSO and RBS1 and the register specification codes Rn and RPn in the instruction codes Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified by 3 bits in the instructio
74. scription example DBNZ B 1215H The B register contents are decremented If the result is not 0 data is branched to 1215H with the start of this instruction set in the range of addresses 1194H to 1293H User s Manual U12326EJ4VOUM 115 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 14 CPU Control Instructions The following are CPU control instructions SEL RBn 117 NOP 118 119 DI 120 HALT 121 STOP 122 116 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS SEL RBn Select Register Bank Register Bank Selection Instruction format SEL RBn Operation 50 8851 lt n n 0 3 Operand Description Theregister bank specified by the operand RBn is made a register bank for use by the next and subsequent instructions RBn ranges from RBO to RB3 Description example SEL RB2 Register bank 2 is selected as the one for use by the next and subsequent instructions User s Manual U12326EJ4VOUM 117 CHAPTER 5 EXPLANATION INSTRUCTIONS NOP No Operation No Operation Instruction format NOP Operation no operation Operand None Description Only the time is consumed without processing 118 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS EI Enable Interrupt Interrupt Enabled Instruction format EI Operation IE 1 Operand None Description The
75. scription example MULU X TheA register contents and the X register contents are multiplied and the result is stored in the AX register 68 User s Manual U12326EJAVOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Divide Unsigned Word DIVUW 4 Unsigned Division of Word Data Instruction format DIVUW dst Operation AX quotient dst remainder lt AX dst Operand Description The AX register contents are divided by the destination operand dst contents and the quotient and the remainder are stored in the AX register and the destination operand dst respectively Division is executed using the AX register and destination operand dst contents as unsigned data However when the destination operand dst is 0 the X register contents are stored in the C register and AX becomes OFFFFH Description example DIVUW C register contents are divided by the C register contents and the quotient and the remainder are stored in the AX register and the C register respectively User s Manual U12326EJAVOUM 69 CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 6 Increment Decrement Instructions The following are increment decrement instructions INC 71 DEC 2 72 INCW 73 DECW 74 70 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Increment INC Byte Data Increment Instruction format INC dst Operation dst dst 1 Operand
76. se of PUSH DE Instruction code 1 0 1 1 0 1 0 1 User s Manual U12326EJAVOUM 31 CHAPTER 4 INSTRUCTION SET This chapter lists the instructions in the 78 0 Series instruction set The instructions are common to all 78K 0 Series products 4 1 Operation For the operation list for each product refer to the user s manual of each product 4 1 1 Operand identifiers and description methods Operands are described in the column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for details When there are two or more description methods select one of them Alphabetic letters in capitals and the symbols and are key words and are described as they are Each symbol has the following meaning Immediate data specification Absolute address specification Relative address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 4 1 Operand Identifiers and Description Methods Identifier Description Method r X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp A
77. src specified by the 2nd operand is subtracted from the destination operand dst specified by the 1st operand The subtraction result is not stored anywhere and only the Z AC and CY flags are changed e f the subtraction result is 0 the Z flag is set 1 In all other cases the Z flag is cleared 0 fthe subtraction generates a borrow out of bit 7 the CY flag is set 1 In all other cases the CY flag is cleared 0 fthe subtraction generates a borrow for bit 3 out of bit 4 the AC flag is set 1 In all other cases the flag is cleared 0 Description example FE38H 38H 38H is subtracted from the contents at address FE38H and only the flags are changed comparison of contents at address FE38H and the immediate data 62 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION OF INSTRUCTIONS 5 4 16 Bit Operation Instructions The following are 16 bit operation instructions ADDW 64 SUBW 65 66 User s Manual U12326EJ4VOUM 63 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Add Word Word Data Addition ADDW Instruction format ADDW dst src Operation dst CY dst src Operand Operand dst src Description The destination operand dst specified by the 1st operand is added to the source operand src specified by the 2nd operand and the result is stored in the destination operand dst fthe addition result shows that dst is 0 the 2 f
78. st specified by the 1st operand and the source operand src specified by the 2nd operand and the result is stored in the destination operand dst fthe logical product shows that all bits are 0 the Z flag is set 1 In all other cases the 2 flag is cleared 0 Description example AND 11011100 Bit wise logical product of FEBAH contents and 11011100B is obtained and the result is stored at FEBAH User s Manual U12326EJAVOUM 59 CHAPTER 5 EXPLANATION INSTRUCTIONS OR Or Logical Sum of Byte Data Instruction format OR dst src Operation dst dst v src Operand Mnemonic Operand dst src Mnemonic Operand dst src A byte A laddr16 saddr byte A HL HL byte nA HL B saddr HL C Note Exceptr Description e The bit wise logical sum is obtained from the destination operand dst specified by the 1st operand and the source operand src specified by the 2nd operand and the result is stored in the destination operand dst fthe logical sum shows that all bits are 0 the 2 flag is set 1 In all other cases the 2 flag is cleared 0 Description example OR A FE98H The bit wise logical sum of the A register and FE98H is obtained and the result is stored in the A register 60 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS Exclusive Or XOR Exclusive Logi
79. ster for normal processing and a register for processing upon interrupt generation for each bank Table 2 1 General Purpose Register Absolute Address Correspondence Table Bank Name Register Absolute Address Bank Name Register Absolute Address Functional Absolute Functional Absolute Name Name Name Name I I L D E B C A X H C A X O0O U mi UO ry Ty gt User s Manual U12326EJ4VOUM 17 CHAPTER 2 REGISTERS 18 FEFFH FEF8H FEF7H FEFOH FEEFH FEE8H FEE7H FEEOH FEFFH FEF8H FEF7H FEFOH FEEFH FEE8H FEE7H FEEOH Figure 2 6 General Purpose Register Configuration a Absolute names 16 bit processing RP3 RP2 RP1 RPO 15 0 b Functional names 16 bit processing e EM DE BC AX 15 0 User s Manual U12326EJ4VOUM 8 bit processing 8 bit processing CHAPTER 2 REGISTERS 2 3 Special Function Registers SFRs Unlike a general purpose register each special function register has a special function Special function registers are allocated in the 256 byte area FFOOH to FFFFH Special function registers can be manipulated like general purpose registers by operation transfer and bit manipulation instructions The manipulatable
80. the 2nd operand is stored in the destination operand dst specified by the 1st operand Description example MOVW SP FE1FH FE1FH is stored in the stack pointer 104 User s Manual U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS 5 12 Unconditional Branch Instruction The unconditional branch instruction is shown below BR 106 User s Manual U12326EJAVOUM 105 CHAPTER 5 EXPLANATION OF INSTRUCTIONS Branch BR Unconditional Branch Instruction format BR target Operation PC lt target Operand Mnemonic Operand target laddri6 AX addr16 Description This is an instruction to branch unconditionally The word data of the target address operand target is transferred to PC and branched Description example BR AX The AX register contents are branched as the address 106 User s Manual _U12326EJ4VOUM CHAPTER 5 EXPLANATION INSTRUCTIONS 5 13 Conditional Branch Instructions Conditional branch instructions are shown below BC 108 BNC 109 BZ 110 BNZ 111 BT 112 BF 113 BTCLR 114 DBNZ 115 User s Manual U12326EJ4VOUM 107 CHAPTER 5 EXPLANATION INSTRUCTIONS BC Branch if Carry Conditional Branch with Carry Flag CY 1 Instruction format BC addr16 Operation PC PC 2 jdisp8 if CY 1 Operand Operand addr16 Description When CY 1 data is branched to the add
81. tor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4 User s Manual U12326EJ4VOUM Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact
82. y patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconduc
83. yte AX saddrp Saddr offset saddrp AX Saddr offset AX sfrp Sfr offset sfrp AX Sfr offset Note 1 AX rp Note 1 rp AX AX addr16 Low addr High addr laddr16 AX Low addr High addr Note 1 AX rp 8 Bit Operation Notes 1 Only when rp BC DE or HL A byte Data saddr byte Saddr offset A r ak 000 1 ReRi Ro rA 000 Ro A saddr Saddr offset A laddr16 Low addr High addr A HL A HL byte 0 0 0 0 0 0 0 0 0 0 0 Data A HL B 000 1011 A HL C ak 000 1010 A byte Data saddr byte A Saddr offset Ar Note 2 010 1 ReRi Ro rA 010 Ro A saddr Saddr offset A laddr16 Low addr High addr A HL A HL byte Data A HL B 010 1011 A HL C 2 A 40 Gj 010 1010 User s Manual U12326EJ4VOUM CHAPTER 4 INSTRUCTION SET Instruction Group 8 Bit Operation Note Except A Mnemonic Operands A byte Operation Code B2 Data B3 saddr byte Saddr offset A r 001 1 ReRi Ro 001 Ro A saddr Saddr offset A addr16

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