USER`S MANUAL
Contents
1. QeOu23 212 Cexovr 6 480118 CI H 6 2 H 5 8 lt H bo 8 5 ee oe m 50 00 tt 6 1 1 2 6 onys CI 6 5 ast 001 553009 NU8 553228 wot 9t 9 5 037 44101138 sU e31INn8CI 6 9 s v a i CTE Dya essa att S3H91U1 JIGOW 008 553 09 E 2661 4240120 WOMIWV3 10 October 1992 XVME 113 Manual RAM ROM Memory Module UME DATA BUS BUFFERS gt 00 31 BUFFENSe 5 8 7 9 2 4 5 6 lt gt 8000 31 2 N EEE 5 8 BUFFEN PRET ETL 9 gagga p a 5 EE Ud 5 x i XVME 113 Schematic Sheet 8 of 9 10 IT 2 6 6 12245 TT 3WNX 11943 95 r UO DR X 4 4 13538555 g z lt lt 291193545 5 23815054 8 T 103d38N 8 83 8 482. Start the Clock Clear the Start Stop bit in Control Register Set the RESET bit in Control Register B Do not set the Counter Registers until RESET bit returns to 0 Set the Start Stop bit in Control Register B Follow the procedure below to set the RTC time with the clock stopped l Stop the RTC by clearing the Start Stop bit bit 0 of Control Register to 0 The clock will then be stopped but no registers will be affected Since the 64 Hz Counter Register is a read only register it must be reset with the RESET bit Reset 64 Hz Counter Register by setting the RESET bit bit of Control Register B to 1 Wait for the reset operation to conclude by polling the RESET bit until it has been reset to 0 The RTC automatically clears the RESET bit when the reset operation is complete Set the Seconds Counter through Year Counter Registers to the desired values Except for the Day of Week Counter Register these registers are encoded in BCD format Start the RTC by setting the Start Stop bit bit 0 of Control Register B to 1 3 11 Chapter 3 Real Time Clock 3 5 22 Setting Registers with the RTC Running If only one or a few of the date and time registers need to be set they can be set while the RTC is running The algorithm is more complic
3. TEST bit lt 0 ensure proper operation write 0 every time Wait 3 Seconds Time delay necessary for oscillator stabilization Set the counter registers e and alarm registers and e initialize the control registers desired The RTC chip has hardware means for resetting registers Therefore after power is first applied to the device all registers must be initialized 3 9 Chapter 3 Real Time Clock Follow the procedure below to initialize the RTC after initial power is applied 1 The TEST 3 of Control Register is undefined after initial power up Therefore calendar clock operation is also undefined Set the TEST bit to 0 before continuing with initialization 2 Delay for 3 seconds before continuing with initialization This time is required for oscillator stabilization within the RTC chip 3 Since interrupts from the RTC are not used on the 113 clear the bit 4 of Control Register A and bit 3 of Control Register A bits to 0 4 The Start
4. Clear Monitor the alarm time Enable only those alarm registers that are to used in the comparison Clear the Alarm Flag in Control Register A Follow the procedure below to setup and monitor the alarm function 3 14 1 Since interrupts are not used there is no need to be concerned with handling an interrupt from alarm function The AIE and CIE bits in Control Register A should always be written with 0 Determine which of the alarm registers needs to be used in the comparison For those registers set the desired alarm time and set ENB bit to 1 Clear the AF bit in Control Register to 0 Note To prevent the CF bit from being cleared as well set the CF bit to 1 for the write operation Monitor the AF bit in Control Register A until it becomes set to 1 When this occurs the alarm time has been reached The AF bit will remain set as long as the RTC time matches the alarm time The AF bit can be cleared by writing a 0 to it but will be set again immediately if the alarm condition is still met To avoid this either set the alarm time to a different time or clear all of the ENB bits of the alarm registers
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6. 9 THE LEADER INDUSTRIAL XVME 113 6U RAM ROM Flash Memory Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 964F Xycom Revision Record Revision Description Date Manual Released 9 92 Manual Updated incorporated PCN 178 11 94 Not Released Manual Updated revision level only 11 97 Manual Updated 2 98 Manual Updated 7 00 Trademark Information Brand or product names are registered trademarks of their respective owners Copyright Information This document is copyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information contained within this document is subject to change without notice Warning This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures European Union Directive 89 336 EEC requires that this apparatus comply with relevant ITE EMC standards EMC compliance demands that this apparatus is installed within a VME enclosure designed to contain electromagnetic radiation and that will provide protection for the apparatus with regard to electromagnetic
7. 113 Memory Module October 1992 3 4 6 1 Carry Flag CF The CF bit indicates that an internal carry has overlapped with a read from the 64 Hz Counter Register or a carry occurred from the Seconds Counter Register After each read operation the CF bit should be polled to ensure that the data read is valid If the CF bit is set after a read operation the data is not valid and must be read again Refer to the procedure for reading the RTC time in section 3 4 2 The CF bit can be reset by writing 0 to it during any period except the carry period A write 1 to this bit is invalid 3 4 6 2 Alarm Flag AF The AF bit indicates to the host processor that the time specified in the enabled alarm registers has been reached This bit will remain set as long as the corresponding counter registers match the alarm registers When the alarm condition is no longer true the AF bit will automatically be cleared to 0 The AF bit may be reset by writing a 0 to it during any period except the alarm period In other words writing a 0 to the AF bit while the alarm condition is still true will reset the bit to 0 but only momentarily The AF bit will be set again immediately due to the alarm condition A write of 1 to this bit is invalid 347 Control Register B RTC Register 1Fh NOTE The TEST bit should always be set to 0 User functions are not guaranteed if the TEST bit has been set to 1 The bits in this re
8. SCHEMATIC 2 10 2 3 6 1 2 5 6 7 8862 20 gt 2 5 6 8 80 0 31 2 5 2 5 6 RDD 2 5 PIN3 1D 2 5 PIN30_1D 1 2 1 PIN31CONMUX 1LO 3 CE1Be D 5 PINiLi 100 219 1 2 1 2 XVME 113 Schematic Sheet 4 of 9 C 6 113 October 1 Em 858828858 enanene ASAE 25525 1 October 1992 XVME 113 Manual RAMIROM Memory Module MEMORY BRNK 2 1 2 4 5 7 BR 2 20X2 2 4 5 8 BD 0 31 XLD PIN30_2D 2 XVME 113 Schematic Sheet 6 of 9 2 3 4 1 2 gt 8 11111113 2 PIN31CONMUX_2 D 2 i 75 4 a us 0 55 px C R 6 JO L 12245 IDUIS 19 5
9. 113 RAM ROM Memory Module October 1992 3 5 5 Application as a Long Term Timer The RTC can be used as a long term timer and will keep accurate track of the year month and day If used in this application setting the correct date is required The RTC will properly handle the number of days in each of the twelve months including leap years NOTE A year whose lower two digits are divisible by four is recognized as a leap year 3 15 APPENDIX VMEBUS CONNECTOR PIN DESCRIPTION A l VMEBUS SIGNAL IDENTIFICATION Table 1 on pages 1 through 5 shows the VMEbus Signal Identification Table 2 on page 6 shows the Backplane 1 pin assignments Table 1 VMEbus Signal Identification Signal Connector and Mnemonic Pin Number Signal Name and Description ACFAIL AC FAILURE Open collector driven signal which indicates that AC input to the power supply is no longer being provided or that the required input voltage levels are not being met INTERRUPT ACKNOWLEDGE IN Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknowledge cycle is in progress INTERRUPT ACKNOWLEDGE OUT Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge IACKOUT The IACKOUT signal indicates to the next board that an acknowledge cycle is in progress ADDRESS MODIFIER bits 0 5 Three state driven li
10. 113 RAM ROM Memory Module October 1992 Table 1 VMEbus Signal Identification Continued Connector and Pin Number Signal Name and Description BUS REQUEST 0 3 Open collector driven signals generated by Requesters These signals indicate that a DTB master in the daisy chain requires access to the bus DATA STROBE 0 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines 00 015 DATA TRANSFER ACKNOWLEDGE Open collector driven signal generated by a DTB slave The falling edge of this signal indicated that valid data is available on the data bus during a read cycle or that data has been accepted from the data bus during a write cycle DATA BUS bits 0 15 Three state driven bi directional data lines that provide a data path between the DTB master and slave GROUND A 3 Appendix VMEbus Description Signal Mnemonic LWORD RESERVED SERCLK SYSCLK A 4 Table A 1 VMEbus Signal Identification Continued Connector and Pin Number Signal Name and Description INTERRUPT ACKNOWLEDGE Open collector or three state driven signal from any master processing an interrupt request It is routed via the backplane to slot 1 where it is looped back to become s
11. 00 Closed 5 FLASH WR RD Open Closed 12V FLASH Read 12V FLASH Open Closed Write Read Factory Default Configuration if backup source is needed See Section 2 5 6 to configure backup source Jumpers 75 16 79 and are used to supply 12V to the programming pin VPP needed to program 12V FLASH If 5V FLASH is used or programming will not be done to 12V FLASH device the B position must be selected 2 14 113 RAM ROM Memory Module October 1992 Table 2 9 Bank 2 Memory Device Pinout Jumpers BANK 2 Tease SENE 5V FLASH WR RD Open Closed 12V FLASH RD 12V FLASH Open Closed Write Read Factory Default Configuration B if backup source is needed See Section 2 5 6 to configure backup source Jumpers 72 13 J7 and 18 are used to supply 12V to the programming pin VPP needed to program 12V FLASH If the 5V FLASH is used or programming will not be done to the 12 FLASH device the B position must be selected NOTE The XVME 113 does accept 5V FLASH if it conforms to the standard JEDEC pinout as shown in Figure 2 7 2 15 Chapter 2 Installation Figures 2 5 thru 2 7 show the memory chip pinouts for EPROM SRAM and FLASH EEPROM 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 128Kx8 256K x8 512K
12. 113 RAM ROM Memory Module October 1992 1 3 MODULE OPERATIONAL DESCRIPTION Figure 1 1 below shows an operational block diagram of the XVME 113 RAM ROM Memory Module POWER 4 0 0 picis d SYSFAIL MONITOR PATTER TO VMEbus MODULE VBU 16 x 32 NN PIN MEMORY SITE MEMORY SITE BANK 2 BANK 1 RMW 21 24 D32 D16 DOS EO UAT VMEbus CONFIGURATION MODULE PORT ADDRESS BUS DATA BUS amp CONTROLS SYSRESET VMEbus Figure 1 1 Operational Block Diagram 2 3 Chapter 1 Introduction 1 4 SPECIFICATIONS Table 1 1 lists the XVME 113 Memory Module s Hardware Specifications Table 1 1 XVME 113 Memory Module Hardware Specifications Characteristic Specification Maximum Memory Capacity 1 bank of 16 sites bank of 8 sites RAM 12 Mbytes Total EPROM 24 Mbytes Total FLASH 12 Mbytes Total EEPROM 12 Mbytes Total Device Sizes Supported RAM 128K by 8 up to 512K by 8 EPROM 128K by 8 up to 1024K by 8 FLASH 128K by 8 up to 512K by 8 EEPROM 128K by 8 up to 512K by 8 Device Speeds Supported 50 100 150 200 ns Power Requirements 5 V typ 9 A max Battery Rating 1 9 Amp hours Battery Life 2 0 years typ using a 628128 Hitachi RAM or equivalent device VMEbus COMPLIANCE Complies with VMEbus Specifications IEEE 1014 Rev C 1 A32 A24 D32 D16 D08 EO DTB Slave for memory banks
13. eg NOILIUBOO9IJNOO ASHOW3W 40103735 30103735 JANYA 2661 4290120 apoy 11 3WAX 6 12245 2102425 lI 3W X OII1UH3HOS 6 3193545 lt 1 06 4 0 oF 1198 ESN 62 13538545 Q 5 403098 4931198 2661 1240120 oww rr 3WAX nse 013 nan QT A 6835 veu 5 2122 EA 59132 54 raaro SERS 3 5 S as ase 810 95 S 507 750 E Eu che od AYLINDYID 7193545 13534545 3 05 Pr 2127 04083 3538555 CIN3 IIb 3545 1 lt 19012932 ngs 18 tH Sha we ant gt ki 5 81506 6 T P TENT lt 192214 Seats e 19212 eats e Ceuta e e 4 October 19 113 MEMORY BANK 1 equnene enunene 1 REPERT 8 1 on m 55
14. 3 4 3 Seconds Minutes Hour Counter Registers RTC Registers 03h 05h 07h These registers are used to set or read the RTC time of day using the 24 hour system Each of the registers is encoded in BCD format For example 59 seconds is expressed in the Seconds Counter Register as 01011001 Similar to the 64 Hz Counter Register an internal carry will occur in the Seconds Counter Register once each second The length of the internal carry is 125 us If the Seconds Counter Register is being read during this time the CF bit 7 of Control Register A will be set to 1 The data read during this time is not valid so the register must be read again Refer to the procedure for reading the RTC time in section 3 5 3 None of these registers is affected by RESET The Seconds Counter and Minutes Counter registers are affected by the 30 sec ADJ operation Refer to the description of these bits in Control Register B in section 3 4 7 3 Chapter 3 Real Time Clock 343 of Week Counter Register RTC Register 09h The Day of Week Counter Register is used to set or read the day of the week The day is encoded with a value from 0 to 6 according to the following chart SS Day of Week Mon Tue Wed Thu Fri Sat 3 44 Month and Year Counter Registers RTC Registers 0Bh 0Dh These registers are used to set or read the RTC calendar date Each of these registers is encoded in BCD form
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16. gt gt gt _ gt gt gt gt gt gt gt gt gt ORF OF Or OF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Open Logic Closed Logic 0 2 23 Chapter 2 Installation Table 2 11 Base Address Switch Options Continued Switch 7 VME Base Address in VME Short Address Space 1 A15 2 14 13 4 12 5 11 6 10 8000 8400H 8800H 8 00 9000 9400 9800 9C00H A000H A400H A800H B000H B400H B800H 000 400 C800H CC00H D000H D400H D800H DC00H E000H E400H E800H EC00H F000H F400H F800H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OOO ORR HH OOO OR HR HH OOOOH HHH OOO BROOCH HCOOH HEH OOH HCOOH FOR OR OH OR OH OH OH OH OH OH OH OH OH OH OHO NOTE Open Logic 1 Closed Logic 0 2 24 113 October 1992 2 5 9 3 Supervisory Non Privileged Mode Selection The XVME 113 RTC Configuration port can be configured to respond to Supervisory access only or to either Supervisory or non privileged accesses Switch 7 position 8 controls which configuration is selected as shown
17. 3 Closed No Data Access Will not respond to or 39H or 09H if in the extended address range Factory default configuration The two switch settings are independent of one another When both the data access select and program access select switch positions are closed the bank is disabled from VMEbus accesses 2 12 113 RAM ROM Memory Module October 1992 2 5 3 Memory Device Speed Two switch settings exist for each bank to define the speed of the memory devices Selections are 50 100 150 and 200 ns access times Table 2 7 lists the switches and speed definition for each device Table 2 7 Memory Device Speed Switch BANK 1 SWITCH 4 POSITION Lom y Closed Closed Closed Open Open Closed Open Open BANK 2 SWITCH 6 POSITION os Closed Closed Closed Open Open Closed Open Open XVME 113 1 factory default configuration VMEbus access timing is a function of the memory device speed of the bank being accessed Data strobe asserted to DTACK asserted will typically be 100 ns plus the chosen access time Data strobe negated to DTACK negated will typically be 40 ns 2 13 Chapter 2 Installation 2 5 4 Memory Device Type There are two switch settings and five jumpers per Bank on the XVME 113 that determine the device type These are listed in Tables 2 8 and 2 9 on the following page Table 2 8 Bank 1 Memory Device Pinout Jumpers BANK 1 C Fn
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19. Definitions Register Name Seconds Counter Minutes Counter Hours Counter 64 Hz Alarm Seconds Alarm Bits indicated are unused These bits unchanged during write operations and will always read 0 during read operations 113 RAM ROM Memory Module October 1992 3 4 REGISTER DESCRIPTIONS The functions of the bits in the RTC registers are described in detail in the following sections 34 1 64 Hz Counter RTC Register 01h The 64 Hz Counter Register is a read only register which can be used to gain access to time values with greater resolution than one second The bits in this register will toggle from 0 to 1 at the indicated frequency For example the 2 Hz bit bit 5 will change from 0 to 1 twice per second This register is clocked by an internal 128 Hz source An internal carry occurs each time the 128 Hz clock rolls over indicating that the data in the 64 Hz Counter Register is changing The length of the carry operation is 125 us If 64 Hz Counter Register is being read during this time the Carry Flag CF bit 7 of Control Register A will be set to 1 The data read during this time is not valid so the register must be read again Refer to the procedure for reading the RTC time in section 3 4 3 The 64 Hz Counter Register can only be reset using the RESET or 30 sec ADJ operations Refer to the description of these bits in Control Register B in section 3 4 7 3
20. Hz Counter Register to 00h to initialize the dividing circuit This operation is typically done with the counter stopped in order to set the RTC time and date before restarting the RTC After being written to 1 the RESET bit will remain set for 250 while the reset operation takes place The bit will then be reset to 0 automatically 3 4 7 5 Start Stop This bit is used to start and stop the RTC When 0 is written to this bit the RTC stops counting When a 1 is written to this bit counting begins or continues 3 8 113 RAM ROM Memory Module October 1992 3 5 PROGRAMMING PROCEDURES This section describes the programming procedures required for the RTC Included are procedures for initializing the RTC setting or reading the RTC using the alarm function and using the RTC as a long term timer 3 5 1 Power on Initialization The RTC on the XVME 113 must be initialized after power is first applied to the device Initialization is only required when the power is initially turned on As long as battery backup is enabled the RTC will not need to be initialized after the VMEbus system is powered up Follow the procedure for initializing the RTC registers as indicated in the flow chart and instructions below 11 eWhen power is first applied all registers are undefined
21. Stop bit bit 0 of Control Register B is undefined at power up This bit should be cleared to 0 to stop the clock in order for the time to be set 3 5 2 Time Setting Procedure There are two ways that the RTC time can be set If the date and time are to be set from scratch the clock should be stopped This is the easiest way for the RTC time to be set Alternatively RTC registers can be set while the clock is running Both methods are described in the following sections 3 5 2 1 Setting Time with RTC Stopped 113 RAM ROM Memory Module October 1992 If all of the date and time registers need to be set stopping the clock is the preferred method for initializing the RTC The procedure for setting the RTC time while it is stopped is described in the flow chart and instructions below Stop the Clock Reset the Clock Wait for Reset Set the counter registers and alarm registers as desired
22. to make sure that the chips are fully seated in the bottom of the sockets with no pins bent or out of alignment in the sockets 2 4 JUMPER AND SWITCH LIST Prior to installing the XVME 113 Memory Module it is necessary to configure several switch and jumper options Table 2 1 provides a list of all the switches and jumpers 2 4 Table 2 1 Switch and Jumper List Extended Address Upper Nibble Bank 1 2 Extended Address Lower Nibble Bank 1 2 VME Address Bank 1 Configuration Bank 1 VME Address Bank 2 Configuration Bank 2 Real Time Clock Config and SYSFAIL SYSRESET 777 VBU Bank 2 Program Flash Bank 2 Program Flash Bank 2 VCC or VBU Bank 1 Program Flash Bank 1 Program Flash Bank 1 Program Flash Bank 2 Program Flash Bank 2 Program Flash Bank 1 Program Flash Bank 1 5VSTBY Alternate Power Source Battery Alternate Power Source 113 RAM ROM Memory Module October 1992 2 5 JUMPER AND SWITCH DESCRIPTIONS The two memory banks are independently configurable via jumpers and switches to define six different memory module parameters e VME Address e Address Modifier Decode e Memory Device Speed e Memory Device Type e Memory Device Size e Memory Backup Power Source The Real Time clock configuration port is independently configurable via a switch for three different parameters Enable Disable RTC CONFIG PORT e Address e Address Modifier Decode The following subsec
23. x8 1024K x8 1M Bit 2M Bit 4M Bit 8M Bit Figure 2 5 EPROM Memory Chip Pinouts 128K x8 512K x8 1M Bit 4M Bit Figure 2 6 SRAM Memory Chip Pinouts 2 16 113 RAM ROM Memory Module October 1992 1 2 3 4 5 5 wi 8 128K x8 1M Bit 512K x8 4M Bit Figure 2 7 FLASH EEPROM Memory Chip Pinouts 2 5 5 Memory Device Size The XVME 113 contains two switch settings per Bank that determine the device size Table 2 10 shows the memory device size for Banks 1 and 2 Table 2 10 Bank 1 and Bank 2 Memory Device Size BANK 1 SWITCH 4 POSITION 128K x 8 Devices Closed Closed 256K x 8 Devices Closed Open 512K x 8 Devices Open Closed 1024K x 8 Devices Open Open BANK 2 SWITCH 6 POSITION 128K x 8 Devices Closed Closed 256K x 8 Devices Closed Open 512K x 8 Devices Open Closed 1024K x 8 Devices Open Open XVME 113 factory default configuration Chapter 2 Installation 2 5 6 Memory Backup Power During power loss CMOS RAM chips may have an alternative power source connected to retain the data stored Two alternative power sources are available the on board battery or the 5V STDBY signal from the VMEbus The following chart shows the jumper configuration for each option Alternative Power Source J12 None On Board Battery 3 6V On 5V STDBY 5 On 5V STDBY Factory default configuration If 5V STDBY voltage is equivalent to battery voltage of appro
24. A16 D16 D08 EO DTB Slave for Real Time Clock and configuration port 4 BUS GRANT INS are connected to their respective BUS GRANT OUTs IACKIN is connected to DOUBLE 6U Form Factor Supports RMW as well as UAT for memory banks 1 4 113 Memory Module October 1992 Table 1 2 lists the 113 Memory Module s Environmental Specifications Table 1 2 Memory Module Environmental Specifications Characteristic Specification Temperature Operating 0 to 65 C 32 to 149 F Non operating 40 to 85 C 40 to 185 F Humidity 5 to 95 RH non condensing Extreme low humidity conditions may require special protection against static discharge Altitude Operating Sea level to 10 000 ft 3048 m Non Operating Sea level to 50 000 ft 15240 m Vibration Operating 5 to 2000 Hz 015 peak to peak 2 5 g peak acceleration Non operating 5 to 2000 Hz 030 peak to peak 5 0 g peak acceleration Shock Operating 30 g peak acceleration 11 msec duration Non operating 50 g peak acceleration 11 msec duration Chapter 1 Introduction 1 6 Chapter 2 INSTALLATION 2 1 INTRODUCTION This chapter explains how to configure the XVME 113 Memory Module before installing the module into a VMEbus system Information on jumper and switch options and locations is also included 2 2 LOCATION OF COMPONENTS RELEVANT TO INSTALLATION The jumpers switches memory sockets and the
25. E 113 RAM ROM Memory Module has power down memory protection circuitry which prevents data from being written to memory when the power supply voltage falls below 4 65 volts The module also has the option of asserting SYSRESET under this condition Another option is to drive SYSFAIL when a low battery is detected on power up The XVME 1 13 is designed to be used with 8 16 and 32 bit VMEbus processor modules It supports read modify write RMW cycles as well as unaligned transfers UAT Chapter 1 Introduction 1 2 MANUAL STRUCTURE The purpose of Chapter One is to introduce the general specifications and functional capabilities of the XVME 113 Chapter Two will develop the various aspects of module installation and operation Chapter Three provides information on how to program the Real Time Clock RTC Chapter One A general description of the memory module including functional and environmental specifications and VMEbus compliance information Chapter Two Information covering switch jumper options memory chip and cardcage installation procedures readable port bit definitions and how to program the real time clock Chapter Three Focuses on programming the RTC as well as explaining the procedures for programming the various functions of the RTC Appendix A Backplane signal pin descriptions Appendix B Quick reference guide of jumper and switch configurations Appendix C Block diagram assembly drawing and schematics
26. PROGRAMMING 3 1 INTRODUCTION This chapter focuses on programming the Real Time Clock RTC It gives a complete description of each of the RTC registers as well as procedures for programming the various functions of the RTC The following is a list of Acronyms and Abbreviations used in this chapter ACRONYM AND ABBREVIATION LIST AIE Alarm Interrupt Enable AF Alarm Flag CIE Carry Interrupt Enable CF Carry Flag ENB Enable RTC Real Time Clock Chapter 3 Real Time Clock 3 2 REAL TIME CLOCK READABLE BANK INFORMATION ADDRESS MAP All writes and reads to the Real Time Clock are at odd memory locations D7 D0 The Real Time Clock uses 16 registers and the remaining odd memory locations in the 1K address space are shadowed on 32 byte blocks Table 3 1 shows the location of the registers The device type and size for the two banks are readable at even locations 015 08 in the same Short I O address space as the Real Time Clock This is readable only and is shadowed times Table 3 1 shows register addressing and Table 3 2 shows data bit definitions Table 3 1 Register Addressing Offset from Base Real Time Clock Configuration Register Address Configuration Reg RTC Register 1 Configuration Reg RTC Register 3 Configuration Reg RTC Register 5 Configuration Reg RTC Register 7 Configuration Reg RTC Register 9 Configuration Reg RTC Register B Configuration Reg RTC Register D Configuration Reg RTC
27. Register F Configuration Reg RTC Register 11 Configuration Reg RTC Register 13 Configuration Reg RTC Register 15 Configuration Reg RTC Register 17 Configuration Reg RTC Register 19 Configuration Reg RTC Register 1B Configuration Reg RTC Register 1D Configuration Reg RTC Register 1 Same as 00 Same as 01 gt 0 113 October 1992 Table 3 2 Data Definitions Bit Location 015 Memtypelb Determines Memory Type Bank 1 upper bit D14 Memtypela Determines Memory Type Bank 1 lower bit 00 01 5 10 FLASH EEPROM Determines Memory Size Bank 1 upper bit 013 Memsizelb Determines Memory Size Bank 1 lower bit 00 128K x 8 01 256K x 8 10 512K x 8 11 1024K 012 Memsizela x8 Determines Memory Type Bank 2 upper bit D11 Memtype2b Determines Memory Type Bank 2 lower bit 00 01 5 10 FLASH EEPROM D10 Memtype2a Determines Memory Size Bank 2 upper bit Determines Memory Size Bank 2 lower bit 00 128K x 8 01 256K x 8 10 512K x 8 11 1024 D9 Memsize2b x8 D8 Memsize2a D7 D0 Real Time Clock Bits 3 3 REGISTER MAP Table 3 3 on the following page shows the address map of the 16 RTC registers The registers are accessed on odd byte addresses beginning at the base address of the XVME 113 in the VMEbus Short I O space Chapter 3 Real Time Clock Table 3 3 RTC Register Map Bit
28. Specifications XVME 113 INSTALLATION Introduction Location of Components Relevant to Installation Installing Memory Chips on the XVME 113 Jumper and Switch List Jumper and Switch Descriptions Bank and Bank 2 Address Select Extended Standard Select Bank and Bank 2 Addressing Boundaries Bank 1 Address Configuration Example Address Modifier Decode Memory Device Speed Memory Device Type Memory Device Size Memory Backup Power SYSRESET Driver SYSFAIL Driver Addressing of RTC Configuration Port RTC Configuration Port Enable Disable VMEbus Options Supervisory Non Privilidged Mode Selection Installing the XVME 113 into a Cardcage REAL TIME CLOCK PROGRAMMING Introduction Real Time Clock Readable Bank Information Address Map Register Map Register Descriptions Programming Procedures VMEbus Connector Pin Description Quick Reference Guide Block Diagram Assembly Drawing Schematics PAGE 1 1 1 2 1 4 2 1 2 1 2 4 2 5 2 5 2 5 2 11 2 11 2 13 2 14 2 17 2 18 2 19 2 20 2 21 2 21 2 21 2 24 2 24 3 1 3 2 3 3 3 5 3 9 Table of Contents 2 Table of Contents FIGURE TABLE 1 1 2 1 2 2 2 3 2 4 2 5 2 6 2 7 1 1 2 1 2 2 2 3 2 4 2 6 2 7 2 8 TITLE Operational Block Diagram Location of Jumper Switches Sockets and Connectors 113 Memory Addressing 4 x Chip Size EPROM Memory Chip Pinouts SRAM Memory Chip Pinouts FLASH EEPROM Memory Chi
29. TC Registers 03h to OFh Poll the CF bit in Control Register A If the CF bit is 0 the read operation was successful and the time or date register data is valid If the CF bit is 1 carry has occurred and the procedure must be repeated The internal carry period lasts for a maximum of 125 Wait 125 before attempting the procedure again Restart the procedure by clearing the CF bit to 0 Step 2 3 13 Chapter 3 Real Time Clock 3 5 4 The RTC alarm function can be used to determine when the RTC time has reached a specified time without having to read the entire set of RTC registers The alarm time is specified by the user and when the RTC time reaches the alarm time the AF is set The alarm registers 64 Hz Seconds Minutes Hours Day of Week and Day each have an enable ENB bit which controls whether that register is used in the comparison Two or more alarm registers may be enabled RTC Alarm Function simultaneously The following flow chart and instructions demonstrate the procedure for setting up the RTC alarm function Clock Running e Set the alarm time and set appropriate ENB bits alarm registers
30. VMEbus P1 and P2 connectors on the XVME 113 Memory Module are illustrated in Figure 2 1 on the following page Chapter 2 Installation qmd 3 HHR o EM tittittit T 2 Dj ln uin 11414011111 _ 55 22 ma nm gt Figure 2 1 Location of Jumpers Switches Sockets and Connectors 2 2 113 October 1992 2 3 INSTALLING MEMORY CHIPS ON THE 113 previously mentioned there are a total of twenty four 32 pin sockets intended for use RAM EPROM FLASH and EEPROM devices on the XVME 113 Module Installing memory in any of the sockets requires setting the proper jumpers and installing the memory devices This procedure is detailed below NOTE Static precautions should be exercised when handling the memory chips especially the CMOS RAM chips With all power removed from the board locate the proper socket Refer to Figure 2 1 for the location of sockets and banks e Refer to the notched end of the memory chips as shown in Figure 2 2 Figure 2 2 Notched End of the Memory Chip 2 3 Chapter 2 Installation Line up the pins on each chip with the socket holes found at inside top of each socket location push each chip firmly and evenly into place Check
31. at For example the 25th day of the month would be encoded the Day Counter Register as 00100101 Only the last two digits of the year are used Leap years are automatically recognized Note A year whose last two digits are a multiple of four is recognized as a leap year 3 4 5 64 Hz Alarm Day Alarm Registers RTC Registers 11h through 1Bh These registers are used to set the time at which the RTC triggers an alarm condition Bit 7 of each of these registers is the register s enable ENB bit If an alarm register s ENB bit is set the RTC uses that register in its comparison to its corresponding counter register to determine if the alarm time has been reached Two or more alarm registers may be enabled at a time When the values in the counter registers match the corresponding values in the enabled alarm registers the alarm condition is met This can be thought of as a logical AND of the alarm registers that are enabled The RTC then sets the Alarm Flag AF bit in Control Register A Since interrupts from the RTC are not used on the XVME 113 the AF bit is the only indication to the host processor that the alarm time has been reached 3 4 6 Control Register A RTC Register 1Dh The only bits that are used in this register are the CF and the AF bits Since interrupts from the RTC are not used on the XVME 113 the Carry Interrupt Enable CIE and Alarm Interrupt Enable AIE bits are unused and should always be written as 0 3 6
32. ated involving verification of the write operations by checking the CF The procedure for setting the RTC time while it is running is described in the flow chart and instructions below 1 7 ES Clear CF Write to Counter Register Verify Write Operation Clear the Carry Flag in Control Register Poll CF bit in Control Register A Repeat for each register to be set Follow the procedure below to set the RTC time with the clock running 3 12 1 Clear CF bit Control Register to 0 Note prevent the AF bit being cleared as well set the AF bit to 1 for the write operation Set the desired time or date register by writing to the appropriate counter register RTC Registers 03h to OFh Poll the CF bit in Control Register A If the CF bit is 0 the write operation was successful and the time or date register has been set If the CF bit is 1 a carry has occurred and the procedure must be repeated The internal carry period lasts for a maximum of 125 Wait 125 before attempting the procedure again Restart the procedur
33. configuration NOTE XX000000 XX400000 XX800000 00000 128 8 256 8 512K x8 1024K x 8 Devices XX000000 XX800000 XX in the above table refers to the 2 upper nibbles of the VMEbus address They are only valid if bank 1 is configured for extended space 113 October 1992 2 5 1 2 Bank 1 and Bank 2 Addressing Bank 1 of the XVME 113 occupies a VMEbus address space of 16 times the memory chip size The bank must be assigned to a starting address boundary which is a multiple of 16 times the memory chip size Bank 2 of the XVME 113 occupies a VMEbus address space of 8 times the memory chip size The bank must be assigned to a starting address boundary which is a multiple of 8 times the memory chip size Figure 2 3 shows addressing for Bank 1 and Bank 2 16 x Device Size in Bytes Base Address lt x 16 x Device Size in Bytes 0 1 2 3 8 x Device Size in Bytes Base Address n x 8 x Device Size in Bytes Bank 2 0 1 2 3 Figure 2 3 Banks 1 and 2 Address Boundaries 2 9 Chapter 2 Installation 0 1 2 3 LONG WORD ADDRESS EVEN BYTE EVENBYTE ODD BYTE HIGH HIGH LOW LOW Base Address 16 x Device Size 4 Base Address 12 x Device Size Base Address 12 x Device Size 4 Base Address 8 x Device Size Base Addre
34. e by clearing the CF bit to 0 Step 1 3 5 3 Time Reading Procedure 113 RAM ROM Memory Module October 1992 The following flow chart and instructions demonstrate the procedure for reading the RTC time and date Reading the RTC time and date requires the use of the CF to validate the data read from the counter registers YES Clear Read the Counter Register Verify Read Operation 1 7 Clear the Carry Flag in Control Register Poll CF bit in Control Register A Repeat for all counter registers Follow the procedure below to read the RTC time and date 1 Since interrupts are not used there is need to be concerned with handling an interrupt a carry operation The CIE and bits in Control Register A should always be written with 0 Clear the CF bit in Control Register A to 0 Note To prevent the AF bit from being cleared as well set the AF bit to 1 for the write operation Read the desired time or date register by reading from the appropriate counter register R
35. e supplies 5 VDC to devices requiring 5V STDBY battery backup 5 VDC POWER Used by system logic circuits 1 32 1 32 1 32 28 1 13 32 12 VDC POWER Used by system logic circuits 10 31 12 VDC POWER Used by system logic circuits 1A 31 A 5 Appendix VMEbus Description BACKPLANE CONNECTOR 1 The following table lists the P1 pin assignments by pin number order The connector consists of three rows of pins labeled rows A B and C Table 2 P1 Pin Assignments Row A Row B Row C Signal Signal Signal Mnemonic Mnemonic Mnemonic 200 BBSY D01 BCLR D09 D02 ACFAIL D10 D03 BGOIN 204 BGOOUT D12 D05 BGIIN D13 D06 BGIOUT D14 D07 BG2IN D15 GND BG2OUT GND SYSCLK BG3IN SYSFAIL GND BG30UT BERR BRO SYSRESET DS0 BRI LWORD WRITE BR2 GND BR3 DTACK AMO GND AMI AS AM2 GND IACK GND IACKIN SERCLK 1 IACKOUT SERDAT 1 AMA GND A07 IRQ7 A06 IRQ6 A05 IRQ5 A04 IRQ4 A03 IRQ3 A02 IRQ2 A01 IRQI 5V STDBY 5V 3 6 APPENDIX QUICK REFERENCE GUIDE Tables B 1 B 2 and B 3 list the jumpers switch bits and their function Table B 1 Bank 1 Configuration Switches Bank 1 Switch 4 Position Bank 1 Supr Nonpriv Select 1 Supr Nonpriv Bank 1 Program Access 1 Respond to Prog Acc 0 Don t Respond Bank 1 Data Access 1 Respond to Data Acc 0 Don t Respond Standard Extend
36. ed Address Select Bank 1 0 Standard Add Select 1 Extended Add Select Bank 1 Speed Select Upper Bit 00 50 NS Access Bank 1 Speed Select Lower Bit 01 100 NS Access 10 150 NS Access 112200 NS Access Bank 1 Memory Type Upper Bit 00 EPROM Bank 1 Memory Type Lower Bit 01 SRAM 10 FLASH EEPROM Bank 1 Memory Size Upper Bit 00 128 x 8 Bank 1 Memory Size Lower 01 256K x 8 10 512K x 8 11 1024K x 8 Switch 3 is used to select A23 A20 for Bank 1 J4 is used to select VBU or VCC to the power pin pin 32 VCC A pos VBU B pos 75 16 19 and are used to supply 12 to the programming pin VPP needed to program FLASH If FLASH is not used or programming will not be done to the device select the A position 12V B position else A position Appendix Quick Reference Guide Table B 2 Bank 2 Configuration Switches Bank 2 Switch 6 Position Bank 2 Supr Nonpriv Select Supr 1 Supr Nonpriv Bank 2 Program Access 1 Respond to Prog Acc 0 Don t Respond Bank 2 Data Access 1 Respond to Data Acc 0 Don t Respond Stand Extended Address Select Bank 1 0 Standard Add Select 1 Extended Add Select Bank 2 Speed Select Upper Bit 00 50 NS Access Bank 2 Speed Select Lower Bit 01 100 NS Access 10 150 NS Access 11 200 NS Access Bank 2 Memory Type Upper Bit 00 EPROM Bank 2 Memory Type Lower Bit 01 SRAM 10 FLASH EEPROM Bank 2 Memory Size Upper Bit 00 128K x 8 Bank 2 Memory Size Lower Bi
37. gister are used to control the operation ofthe RTC It contains four defined bits which are used to test adjust reset start or stop the counter The other four bits may be employed by the user as read write bits to be used as RAM or flag bits Chapter 3 Real Time Clock 3 4 7 1 These bits may be used as RAM or as flag bits at the user s discretion These are readable writable bits which retain their state upon power down These bits may only be used if the TEST bit has been set to 0 3 4 7 2 TEST This bit is used to test the RTC at the factory and should always be set to 0 by the user s program Failure to do so will result in improper operation of the RTC 3 4 7 3 ADJ 30 Second Adjust This bit is used to execute the 30 second adjustment feature of the RTC which can be used to automatically synchronize the RTC to another clock source When 1 is written to this bit the Minutes Counter Register will be adjusted according to the value in the Seconds Counter Register If the Seconds Counter Register value is less than 30 the Minutes Counter Register is unchanged Otherwise a carry will occur in the Minutes Counter Register The 64 Hz Counter Register and the Seconds Counter Register are both reset to 00h After being written to 1 the ADJ bit will remain set for 250 us while 30 second adjust operation takes place The bit will then be reset to 0 automatically 3474 RESET This bit is used to reset the 64
38. immunity This enclosure must be fully shielded An example of such an enclosure is a Schroff 70 EMC RFI VME System chassis that includes a front cover to complete the enclosure The connection of nonshielded equipment interface cables to this equipment will invalidate EU EMC compliance and may result in electromagnetic interference and or susceptibility levels that violate regulations that apply to legal operation of this device It is the responsibility of the system integrator and or user to apply the following directions as well as those in the user manual that relate to installation and configuration All interface cables should include braid foil type shields Communication cable connectors must be metal with metal backshells ideally zinc die cast types and provide 360 degree protection about the interface wires The cable shield braid must be terminated directly to the metal connector shell Shield ground drain wires alone are not adequate VME panel mount connectors that provide interface to external cables e g RS 232 SCSI keyboard mouse etc must have metal housings and provide direct connection to the metal VME chassis Connector ground drain wires are not adequate Xycom Automation 750 North Maple Road Saline MI 48176 1292 734 429 4971 734 429 1010 fax 1 2 5 9 2 5 9 1 2 5 9 2 2 5 9 3 2 6 APPENDICES TITLE INTRODUCTION Overview Manual Structure Module Operational Description
39. in Table 2 12 Table 2 12 Privilege Options Switch 7 Bit 8 Privilege Mode Selected Corresponding Address Modifier Open Supervisory or Non Privileged 29H or 2DH Closed Supervisory Only 2DH only Factory default configuration 2 6 INSTALLING THE XVME 113 INTO A CARDCAGE CAUTION Do not attempt to install or remove any boards without first turning off the power to the bus and all related external power supplies Prior to installing a module you should determine and verify all relevant jumper configurations Check the jumper configuration with the diagram and lists in the manual To install a board in the cardcage perform the following steps 1 Make certain that the particular cardcage slot which you are going to use is clear and accessible 2 Center the board on the plastic guides in the slot so that the handle on the front panel is towards the bottom of the cardcage 3 Push the card slowly toward the rear of the chassis until the connectors are fully engaged and properly seated 2 25 Chapter 2 Installation It should not be necessary to use excess pressure of force to engage connectors If board does not properly connect with the backplane remove the module and inspect all connectors and guide slots for possible damage or obstructions 4 Once the board is properly seated tighten the two machine screws at the top and bottom of the front panel 2 26 Chapter 3 REAL TIME CLOCK
40. isable 1 Enable A14 Select for RTC Configuration Port O Disable 1 Enable A13 Select for RTC Configuration Port 0 Disable 1 Enable A12 Select for RTC Configuration Port 0 Disable 1 Enable A11 Select for RTC Configuration Port 0 Disable 1 Enable A10 Select for RTC Configuration Port 0 Disable 1 Enable Enable Disable RTC Configuration Port 0 Disable 1 Enable Supervisory Supvis Nonpriv 1 Supvis Nonpriv SYSRESET Enable 0 Dis SYSRESET 1 En SYSRESET SYSFAIL Enable 0 015 SYSFAIL 1 SYSFAIL 1 2 3 4 5 6 7 8 9 Appendix Quick Reference Guide Table B 5 shows the jumper configuration for battery backup options Table B 5 Jumper Configuration Alternative Power Supply None Battery 3 6V On 5V Standby 5V On 5V Standby Factory shipped configuraton Table B 6 Device Parameters For Memory Sites Banks 1 and 2 RAM Device Chosen Access Times Parameter Must be pass 5 me XVME 113 RAM ROM Memory Module October 1992 twe MIR mr aus SNES Qo touz Dout lt RS gt gt gt OY 29 SY 2 252521 OY 2909 A write occurs during overlap of a low 51 and a low WE write begins at latest transition among CSI going low and WE going low A write ends at the earlie
41. lot 1 IACKIN in order to start the interrupt acknowledge daisy chain INTERRUPT REQUEST 1 7 Open collector driven signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit transfer RESERVED Signal line reserved for future VMEbus enhancements This line must not be used A reserved signal which will be used as the clock for a serial communication bus protocol which is still being finalized A reserved signal which will be used as a transmission line for serial communication bus messages SYSTEM CLOCK A constant 16 MHz clock signal that is independent of processor speed or timing It is used for general system timing use 113 RAM ROM Memory Module October 1992 Table A 1 VMEbus Signal Identification Continued Connector Signal and Mnemonic Pin Number Signal Name and Description SYSFAIL SYSTEM FAIL Open collector driven signal that indicates that a failure has occurred in the system It may be generated by any module on the VMEbus SYSRESET SYSTEM RESET Open collector driven signal which when low will cause the system to be reset WRITE WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indicates a write operation 5 VDC STANDBY This lin
42. n switch 7 position 9 To disable the SYSRESET driver close switch 7 position 9 2 19 Chapter 2 Installation 2 5 8 SYSFAIL Driver A SYSFAIL driver is provided to assert SYSFAIL when low battery is detected at power up A low battery LED on the front panel will also light To enable the SYSFAIL driver open switch 7 position 10 To disable the SYSFAIL driver close switch 7 position 10 If the SYSFAIL driver is enabled and low battery is detected upon power up the SYSFAIL signal will be asserted by XVME 113 until cleared The SYSFAIL signal is cleared by any access to XVME 113 NOTE The low battery LED will remain on even if the SYSFAIL signal has been negated by an access to the XVME 113 2 20 113 RAM ROM Memory Module October 1992 2 5 9 Addressing of RTC Configuration Port A Real Time Clock is also provided and resides in the VME Short I O address space The device size and type for the two banks are readable in the same VME Short I O address space 2 5 9 1 RTC Configuration Port Enable Disable If the RTC Configuration port is not used the port can be disabled so that there will be no response to any addressing The chart below shows how to disable the port SWITCH 7 POSITION PORT BIT 7 Disable RTC Configuration Closed Enable RTC Configuration Open Factory default configuration 2 5 9 2 VMEbus Options The base address decoding scheme for the RTC Configuration port i
43. nes that provide additional information about the address bus such as size cycle type and or DTB master identification 0 5 ADDRESS STROBE Three state driven signal that indicates valid address is on the address bus 1 Appendix VMEbus Description Signal Mnemonic BGOIN BG2IN BGOOUT BG30UT A 2 Table A 1 VMEbus Signal Identification Continued Connector and Pin Number Signal Name and Description ADDRESS BUS bits 1 23 Three state driven address lines that specify a memory address ADDRESS BUS bits 24 31 Three state driven bus expansion address lines BUS BUSY Open collector driven signal generated by the current master to indicate that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the master if a higher level is requesting the bus BUS ERROR Open collector driven signal generated by a slave It indicates that an irrecoverable error has occurred and the bus cycle must be aborted BUS GRANT 0 3 IN Totem pole driven signals generated by the Arbiter or Requesters Bus Grant In and Out signal indicates to this board that it may become the next bus master BUS GRANT 0 3 OUT Totem pole driven signals generated by Requesters These signals indicate that a DTB master in the daisy chain requires access to the bus Mnemonic BRO BR3 200 015
44. p Pinouts Notched End of the Memory Chip TITLE XVME 113 Memory Module Hardware Specifications Memory Module Environmental Specifications Switch and Jumper List VME Base Address Select Bank 1 amp 2 Memory Device Size Bank 1 and Bank 2 Address Modifier Switches Memory Device Speed Switch Memory Device Pinout Jumpers Bank 1 Memory Device Pinout Jumpers Bank 2 Jumper Configuration for each Option PAGE 1 3 2 1 2 5 2 6 2 11 2 11 2 12 2 14 PAGE 1 4 2 2 2 3 2 4 2 7 2 9 2 10 2 15 Chapter 1 INTRODUCTION 11 INTRODUCTION The 113 RAM ROM Memory Module is double high VMEbus compatible board that can accommodate up to 12 Mbytes of RAM 24 Mbytes of EPROM 12 Mbytes of FLASH or 12 Mbytes of EEPROM The module is designed with an on board battery backup circuit to provide power to CMOS RAM devices in the event of a power failure A real time clock is also added as well as a readable port for the memory device size and type for each bank The XVME 113 has 24 32 pin JEDEC sockets which are divided into two separate memory banks Bank one contains 16 memory sites and bank two contains 8 memory sites Each bank is designed to employ memory devices of the same type and speed and each bank can be independently configured via jumpers and switches in terms of VME Address Address Modifier Decode Memory Device Speed Memory Device Type Memory Device Size Memory Backup Power Source The XVM
45. s such that the starting address for each I O Interface Block resides on a 1K boundary Thus the module base address may be set to any one of 64 possible 1 boundaries within the 64K Short I O Address Space The module base address is selected by using Switch 7 Bits 1 6 Figure 2 8 shows Switch 7 and how the individual switches 1 6 relate to these address bits 1 2 3 5 6 7 8 9 10 1 1 121 131 2 21 Chapter 2 Installation Figure 2 8 RTC Configuration Port Base Address Switches 2 22 113 RAM ROM Memory Module October 1992 When a switch is in the closed position i e when it is pushed in on the opposite end of the switch bank from the open label the corresponding base address bit will be logic 0 When a switch is set to the open position the corresponding base address bit will be logic 1 Table 2 11 shows a list of the 64 1K boundaries which can be used as module base addresses in the Short I O Address Space as well as the corresponding switch settings switches 1 6 from Switch 7 Table 2 11 Base Address Switch Options Switch 7 VME Base Address in VME Short Address Space eR gt gt gt gt gt gt gt gt gt gt Ree Re re lt gt gt gt gt
46. spond to program accesses When closed the module does not respond to program accesses The third switch setting is data access select When this switch is open the bank will respond to data accesses When closed the bank does not respond to data accesses Table 2 6 on the following page lists these switch settings and their definitions Chapter 2 Installation Table 2 6 Address Modifier Switches BANK 1 SWITCH 4 POSITION 1 Closed Supervisory only AM2 1 1 Open Supervisory amp non privileged AM2 no preference 2 Open Program Access Responds to address modifier codes or OAH if in the extended address range 2 Closed No program access Will not respond to or 3AH or OAH if in the extended range 3 Open Data Access Responds to address modifier codes 3DH or 39H ODH or 09H if in the extended address range 3 Closed No Data Access Will not respond to or 39H or 09H if in the extended address range BANK 2 SWITCH 6 POSITION 1 Closed Supervisory only AM2 1 1 Open Supervisory amp Non privileged AM2 no preference 2 Open Program Access Responds to address modifier codes or OAH if in the extended address range 2 Closed No Program Access Will not respond to or 3AH or OAH if in the extended address range 3 Open Data Access Responds to address modifier codes 3DH or 39H ODH or 09H if in the extended address range
47. ss 8 x Device Size 4 Base Address 4 x Device Size Base Address 4 x Device Size 4 Base Address BANK 1 BYTE 0 BYTE 1 BYTE 2 BYTE 3 LONG WORD ADDRESS EVENBYTE EVENBYTE ODD BYTE S HIGH HIGH LOW LOW Base Address 8 x Device Size 4 Base Address 4 x Device Size Base Address 4 x Device Size 4 Base Address Figure 2 4 shows the XVME 113 Memory Map 2 10 113 RAM ROM Memory Module October 1992 2 5 1 3 Bank 1 Address Configuration Example The following is an example of Bank 1 configuration with a VMEbus base address of 1E800000 in the extended address range Switch 1 1 Switch 2 Switch 3 8 Switch 4 Position 4 open NOTE If Bank 2 is used with Bank 1 in this configuration Bank 2 may be configured for either the standard or extended range However if the extended address range is used 1E must be used for Bank 2 s higher order byte 2 5 2 Address Modifier Decode The address modifier decode uses three switch settings for each bank 6 total The first switch setting is privilege select When the switch is closed the bank will respond only to supervisor accesses When open the bank will respond to supervisor and non privileged accesses During each access of a bank that bank s LED will momentarily light on the front panel The second switch setting is program access select When open the module will re
48. st transition among CSI going high and WE going high Twp is measured from the beginning of write to the end of write Tas is measured from the address valid at the beginning of write Twr is measured from the earliest of CS1 WE going high to the end of the write cycle During this period I O pins are in output state therefore the input signals of the opposite phase to the outputs must not be applied Figure B 1 Write Timing Waveform B 5 Appendix Quick Reference Guide Figure B 2 Read Timing Waveform APPENCIX BLOCK DIAGRAM ASSEMBLY DRAWING SCHEMATICS POWER piu SYSFAIL MONITOR BATTERY TO VMEbus MODULE You MEMORY SITE MEMORY SITE BANK 1 BANK 2 RMW A32IA24 03270160060 VMEbus INTERFACE is A16 016 003 CONFIGURATION ADDRESS BUS DATA BUS amp CONTROLS 5 STBY VMEbus Figure 1 XVME 113 Block Diagram Appendix Block Diagram Assembly Drawing Schematics zc Zum sess em Care 05 E ICA 0 1772 948 949 U41 uae u43 944 045 H H m H EE Y 38e I 0000000000 nir Figure C 2
49. t 01 256K x 8 10 512K x 8 11 1024K x 8 Switch 5 is used to select A23 A20 for Bank 2 J4 is used to select VBU or VCC to the power pin pin 32 VCC A pos VBU B pos J2 13 and 18 are used to supply 12V to the programming pin VPP needed for 12V FLASH to program If FLASH is not used or programming will not be done to device select the B position 12V A position else B position 113 RAM ROM Memory Module October 1992 Table B 3 Bit Location Switch Bit Bit Location Memtypelb Determines Memory Type Bank 1 upper bit Memtypela Determines Memory Type Bank 1 lower bit Memsizelb Determines Memory Size Bank 1 upper bit Memsizela Determines Memory Size Bank 1 lower bit Memtype2b Determines Memory Type Bank 2 upper bit Memtype2a Determines Memory Type Bank 2 lower bit D9 Memsize2b Determines Memory Size Bank 2 upper bit D8 Memsize2a Determines Memory Size Bank 2 lower bit 07 20 Real Time Clock Bits A switch bit will enable or disable access to this 1K short I O block Only 8 bit or 16 bit transfers are allowed to the real time clock Unaligned transfers or 32 bit transfers are not allowed and the XVME 113 will not respond if either one of those transfers is attempted A single ten position dip switch Switch 7 is used for the remaining configurations The bit description is shown in Table B 4 Table B 4 Switch 7 Configuration Switch 7 Position A15 Select for RTC Configuration Port 0 D
50. the other operating in the standard address space at the same time 113 October 1992 Hex switch 3 is used to select valid starting base address A23 21 for Bank 1 and Hex switch 5 is used to select the valid starting base address A23 A20 for Bank 2 Table 2 4 shows all Bank 1 address selections for each size memory and Table 2 5 on the following page shows all possible Bank 2 address selections for each memory device size Table 2 4 Bank 1 Address Selection BANK 1 Valid Starting Address Switch 3 128K x 8 256K x 8 512K x8 1024K x 8 Position Devices XX000000 XX000000 XX000000 XX000000 XX200000 XX400000 XX400000 XX600000 XX800000 XX800000 XX800000 XXA00000 00000 00000 00000 Factory default configuration 0 td D OU uU RUIN NOTE XX in the above table refers to the 2 upper nibbles of the VMEbus address They are only valid if bank 1 is configured for extended space 2 7 Chapter 2 Installation 2 8 Switch 5 Position m tm OU o0 0 Uu o t Table 2 5 Bank 2 Address Selection XX000000 XX100000 XX200000 XX300000 XX400000 XX500000 XX600000 700000 800000 900000 XXA00000 00000 00000 XXD00000 00000 XXF00000 Valid Starting Address XX000000 XX200000 XX400000 XX600000 XX800000 00000 XXC00000 00000 Factory default
51. tions examine these jumper and switch options in detail showing specifically when and how jumpers should be configured 2 5 1 Bank 1 and Bank 2 Address Select One hex switch exists for each bank to define the VME address A23 A21 for bank 1 A23 A20 for bank 2 Two hex switches exist that define the extended VME address A31 A24 and these two hex switches are shared between banks 1 and 2 2 5 1 1 Extended Standard Address Select One switch setting for each bank is used to select whether that bank will reside in the VMEbus standard or extended address space Table 2 2 below shows address selections for Bank 1 and Bank 2 Table 2 2 Extended Standard Address Selection Address Space Bank 1 Bank 2 Switch 4 Position 4 Switch 6 Position 4 Extended Address Space Open Factory default configuration 2 5 Chapter 2 Installation Hex switches 1 and 2 will be used to dial in extended address and high order address bits A31 A24 Table 2 3 shows hex switches 1 and 2 2 6 Table 2 3 Hex Switches 1 and 2 Extended Address Upper Hex Nibble Lower Hex Nibble NOTE If both banks reside in the extended address space these banks will share the same high order eight address bits A31 A24 since they both share SW1 and SW2 Since there are separate switch bit settings for selection between the standard or extended address range for each bank it is possible to have one bank operating in the extended memory address space and
52. ximately 3 6V select B If 5V STDBY voltage is equivalent to VCC voltage of approximately 5V select A 2 18 113 RAM ROM Memory Module October 1992 In order to achieve maximum battery life RAM chips must have a small data retention current Most static RAM suppliers have chips that guarantee very low data retention currents To calculate the typical battery life use the following equation Hours of battery life 1 900 000 n x IsB 22 where IsB the data retention current required by the particular RAM chips in micro amperes n the number of RAM chips selected to be battery backed Example Hitachi 628128LP 12 RAM chips have a typical IsB of 2uA Battery Life 1 900 000 27143 hours 3 1 years 24 x 2 22 Each bank can be individually configured to either have or not have backup battery power as shown by the jumper settings below Bank 1 Backup power J4B No backup power J4A Bank 2 Backup power No backup power If backup power is not needed for either bank 711 should be out 712 should be in A position If EPROM FLASH or EEPROM is installed in any bank the Vcc jumper J1A for Bank 2 and J4A for Bank 1 should be installed to prevent drawing current from the alternate power source 2 5 7 SYSRESET Driver SYSRESET driver is provided to assert SYSRESET when the power monitor circuitry detects that Vcc is less than 4 65V To enable the SYSRESET driver ope
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