Evaluation System User Manual
Contents
1. D Oo 7 gt S1 1 BLANKING AIS OFF 1 BLS DFF TXTS ALARMIN ON OFF 4 z AXTS 1 2 d 7 P 5 10K apa s3 1 16 i 15 2 f I 1 4 E I 1 5 I 1 6 7 10 RA 10K 2 SA 1 16 2 E T 1 15 3 E J 14 4 E I 13 5 I J 2 5 I 14 7 10 7 16 9 Figure 16 Demo Board Option Selection Switch Schematic ASTE AW AW NG NG NG NG w w a 24 TOM Z EXAR Mp NB NB a RTS2 IN RSYNC QUT RBMHZ IN REMHZ gt RS 50 Rg 50 SPARE XR T6164 65 66ES a RESET u RESET gt T at 40 POI SX sl 6l lt MT ues Ali 52. Present Tn Transniter Opt ss 1 N PCMIN Word 0 Programmed as 1 0 1 0 100 1 i er TEN jaw TT ON Transmit Time Slot 1 Programmed as Position 0 7 Receive Time Slot 1 Programmed as Position 0 7 benem Sector Unused Table 9 Dip Switch Preset Positions ALTE AV AV NG TOM 17 XR T6164 65 66ES lt aw rrm RETE TX2MHz T6166 Pin 20 FERE HAEHAE 2 m41 EX PCMIN T6166 Pin 19 pepe TX256kHz T6166 Pin 17 500 NS Div Hor 5 V Div Vert Figure 6 XR T6166 Transmitter side Waveforms RX2MHz T6166 Pin 5 PCMOUT Board Test Point TS1R T6166 Pin 23 RSYNC OUT Board BNC Connector LIRE 500 NS Div Hor 5 V Div Vert Figure 7 XR T6166 Receiver side Waveforms ELE EE CL E vv MEMNENNZZZZZZENEN o sa ahh nahi Bit Pattern 1100 1100 1010 1100 1010 1100 1010 1010 1100 Bit Value 0 1 1 0 1 0 1 0 0 1 Bit Position 06 07 03 D4 D5 De D7 Violation V V Figure 8 XR T6164 Transmitter Output Waveforms ASTE AW N NG w w w 18 2 EMAR TOM 72 EXAR XR T6164 65 66ES ens Pg AE yaga Og u WEY PCMIN TS1T 7 77 256 2 _
3. 41 J2 1 HH 6165 16 15 SAR ALARM PSS gt 14 4 5 S A PCMOUT 55 x 13 5 S 2 5 5 18 14 6 6 17 9 48 7 16 8 15 2 3 9 14 z 10 on 13 3 11 TAR ALARMIN 5 4 14 T A TTSEL 3 ia d 2 16 Fx Gii xX 1 O 1uF XR T6165 ALARM PCMOUT 28 16 5 SAR 52 15 5 14 BLS 13 RX2MHZ 2 BLANK U1 11 RXCKOUT 10 VDD 9 8 RXCK2MHZ TX2MHZ 7 TS1T PCMIN Fig 5 2 BDT BIT 5 13 TS2 TX256KHZ Hi6 4 14 TAR ALARMIN E 3 15 T A TTSEL 2 16 Hx x11 C1 O 1uF vec O 1uF 1 1 5 e 332 _ E Tx o P H 6 4 R3 5 t J2 ad 5 32 5 1 16 Tx 0 P 8 DIG 5 2 RX I P 5 3 ae 5 2 2e O D 4 N BIAS Ed i E 2 5 2 3 5 ae 1 5 2 20 4 O 4uF XR T6184 1 4 RX ALARM S R 44 I 5 5 8 G G TX I P N N D D A D Figure 20 XR T6164 LIU Daughter Board Schematic ALTE AV A N NG NG NG w w 27 TOM XR T6164 65 66ES Z EXAR memes Se 7 7 C1 2 3 4 5 6 9 0 1uF 63V 250 Dielectric Axial lead 0 1 Digi Key P4917 Spacing 1 C7 22uF 16V Electrolytic Cap Radial Lead Digi Key P5228 ND 5mm Dia 2mm Lead S
4. 5 s G WORDSYNC PCMOUT TS1R RXSYNC 9 Figure 9 Timing with Repetitive Word 0 L L TLILILILILILILILILILILILTLILILILILILI1 PCMIN 1 1 TS1T ac c gt TXSYNC WORDSYNC foe dps ded gi Bl up Eg gS E Enn PCMOUT TSIR Am eeu Vie EL RXSYNC a Figure 10 Frame 1 Timing with 4 Word Sequence SESE AV AV A AV NG w a TOM 19 XR T6164 65 66ES Z EXAR A P OF TX2MHZ LILI LI UU LULU LU LI LI LI MI LI UT LU LU I o TS1T DLL L eo LU TXSYNC a WORDSYNC PCMIN TX256kHz RX2MHZ PLU LU LLL LLU U qr qe TS1R RXSYNC PCMOUT Figure 11 Frame 2 Timing with 4 Word Sequence TX2MHZ LI LI LI LI LI LI LI MI LI LI LI LU LU LU LI LI LI LI Tit iji c Wai en PCMIN TXSYNC RX2MHZ ULU SE LL LIU lS EC EET UU PCMOUT 1 f L TL Figure 12 Frame 3 Timing with 4 Word Sequence TS1R RXSYNC ASTE AW AW TOM 20 72 EXAR XR T6164 65 66ES TX2MHZ PCMIN TS1T s IG eS ___ A __ x TX256kHz _ F TXSYNC a 7 rr r WORDSYNC RX2MHZ PCMOUT 1 TS1R 2 R
5. 4 e e 1 ee O T256 INT e e SU TSELD e es m A TSEL1 e em 2 lt TSEL2 e e e ez oe e TSEL3 6 e e e ON oo PE TSEL4 e 8 0 e e e e e e e co e e TX OUT e 1 2 D CD ch RCLK EXT aft INT jo ON 2 GND e gt s Z RsELOe e e B 2 20 gt 1 RSEL1e e e ov o er MIN Xu ALARM RSEL2 e e e e v RSEL3 e e e e 3 9 4 e e 9 RXCKOUT e e e e S e e imi e s BDT e e e 9 1 I z a e e 5 BIT 815 B J eorr je e e e e ees im BLS OFF e ON e 5 lt gt N o 2 i TXTS 16 e e 12 s cs gt ON e OFF lew a 5 r RXTS 1 2 e D OR e e e a BDR e e e E z e e e lt gt U1 m E BIR zi 5 S e o c e 6 e on PCMOUT e Tm e eg e e GND e e mo te m c mm eps 4 PS a a e ns e S e Rr ese nme e m 2 5 ee ee ee IN R8MHZ IN TSYNC OUT RSYNC OUT RTS2 IN IN Figure 1 Mother Board Component Marking MEE AW AV NG NG NG w w a TOM
6. TX2MHZ RSEL 0 4 RSEL 0 4 T T2565EL 5 WRDSEL TS4T AXCLKSEL CM CMINBL PEMIN DIPSW SCH RX2MHZ REMHZ EXCLK TS1R BEB IXSYN ERXSYN ESET TIMLOGIC SCH TS2T 2 Ji AXRNG 7 TXTIP BXTIP 2 5 TXHNG TXTIP _ATIP _ 3 6 4 5 3 TKANG 5 TRANG AXALM SIR SFR 2 1 _ RXRNG E E XR TB8164 LIU CONNECTOR 5 C7 5 a gt C1 c5 10uF O 1uF O 1uF O 1uF O 1uF O 1uF O 1uF Jo GND m 1 3 A 5 30 16 3 XR T6164 65 66ES 10 11 14 15 XR T616 SUB BOARD RXALM 7 5 BIT cs D BDR BIR e XR T6165 6166 TEST Figure 15 Demo Board Top Level Schematic SESE AW N NG NG NG a a 23 ALARMIN OR RKALM ALARM RXCKOUT BDT ETE CS BDR BIR POINTS TOM XR T6164 65 66ES lt aww 1 4 T256 EXT INT TSELO TSEL1 TSEL2 TSEL3 TSELA RXCLK EXT INT RSELO RSEL1 RSEL2 ISEL3 RSEL4
7. Reference Sur 1 C1 0 1 uF 63V 250 Dielectric Axial lead 0 1 Digi Key P4917 Spacing 1 1 22 Pin IC Socket 0 4 Spacing Digi Key ED 3422 ND Table 12 XR T6165 Daughter Board Parts List C NC 2 011 1 1 0 1 uF 63V 250 Dielectric Axial lead 0 1 Digi Key P4917 Spacing XR T6166 IC EXAR 28 Pin IC Socket 0 6 Spacing Digi Key ED 3628 ND Table 13 XR T6166 Daughter Board Parts List Magnetic Supplier Information Pulse Transpower Technologies Inc Telecom Product Group 24 Highway 28 Suite 202 P O Box 12235 Crystal Bay NV 89402 0187 San Diego CA 92112 Tel 702 831 0140 Tel 619 674 8100 Fax 702 831 3521 Fax 691 674 8262 ALTE AV AV NG NG NG NG w TOM 29 XR T6164 65 66E Z EXAR d S PP Notes ASTE AW AW NG NG w w TOM 30 72 EXAR XR T6164 65 66ES lt lt w mm Notes SESE AW AW N AV NG NG w w TOM 31 ALL 72 EXAR analog plus company EXAR Corporation 48720 Kato Road Fremont CA 94538 510 668 7000 Fax 510 668 7017 Worldwide Web Site http www exar com MEE LE NG NG NG MI AF TOM
8. Table 4 Dip Switch S2 Functions Table 5 Pattern Generator Bit Patterns Table 6 Dip Switch S1 Functions Table 7 BNC Connector Functions Table 8 Test Point Functions BOARD OPERATION Start up Procedure uu nne oe eet Waveform Measurements Operation With A Repetitive 4 Word Sequence Advanced Capabilities Receive Buffer Tests Transmit Buffer Tests Timing Alignment Tests Table 9 Dip Switch Preset Positions Figure 6 XR T6166 Transmitter side Waveforms Figure 7 XR T6166 Receiver side Waveforms Figure 8 XR T6166 Transmitter Output Waveforms Figure 9 Timing with Repetitive Word 0 Figure 10 Frame 1 Timing with 4 Word Sequence Figure 11 Frame 2 Timing with 4 Word Sequence Figure 12 Frame 3 Timing with 4 Word Sequence Figure 13 Frame 4 Timing with 4 Word Sequence Figure 14 Frame 5 Timing with 4 Word Sequence MEY
9. 55 5 15 QT PATTERN XR T5166 i mE 3 14 DIO 7 PCMIN H 12 GENERATOR TRANSMIT SIDE 3 tx sipe ANG 28 5 5 e _ 2 s X25BKHZ 1 TSEL VB DIR TX CLK out E ALARMIN Z 48 41 5 1 16 5 Em 15 IN 1 12 TSYNC DUT TRANSMIT 5 3 2 3 TIMING LOGIC S CLK M G LOGIC CL ROI 9 daea Vs CLK CLROUT S4 AXCLK EXT INT i ec Y 3 14 CLK OUT out RESET 55 RSEL1 RXBMHZIN 0 8 MUX RECEIVE RSEL2 2 o 5 RSELS 5 Ht A TIMING Loc s LS RSEL4 e He BSELIO 4 RSYNC OUT E E s x 1 16 i s S H5 B up Eta H 4 A 13 2 i RTS2 IN 5 N N 7 10 E G B L3 xR T6165 Sth KENE PCMOUT e AT E RECEIVE SIDE SB tu mx K P BBCAR R IP DYA SS dx uX x C L M ACO Figure 5 Demo Board Block Diagram MEE AW AV TOM 10 72 EXAR XR T6164 65 66ES Section Number Function and Name Selects Repetitive 1 or 4 OFF Repeats 8 Bit PCMIN Word 1 Pattern Set Word Sequence By S2 Repeats 32 Bit Sequence Composed of PCMIN Word 1 Followed By 3 Built in Words Selects 256 2 OFF External Transmit Clock Applied to Transmit Clock Source T256kHz IN Input Used Clock Generated Internally By Demo Board
10. 6 72 EXAR XR T6164 65 66ES AF AF J1 J2 le KS e 201 9 e 9 19 Dla T e bi e 2 92 e o e a o0 86 A mje P e e e e Ul Figure 2 XR T6165 Daughter Board Component Marking Jl D CU LJ x a M a e gt lt lt 20 gt lt di lt o 9 b o N o e D 2 o 2 2 o 2 4 e M 1 za 2 E amp 9 P 2 cy Ul e Figure 3 XR T6166 Daughter Board Component Marking e e e e Ce e 5 00 E 00 C4 LIU e Figure 4 XR T6164 LIU Daughter Board Component Marking ALTE AV AV NG NG NG NG w w TOM 7 XR T6164 65 66ES 2 EMAR AM NG w w ELECTRICAL DESCRIPTION This description refers to Figure 5 and Table 1 through Table 8 that are located at the end of this section Although the following discussion explicitly mentions the XR T6166 the general information given applies equally well to the XR T6165 N
11. AFP NG NG NG NG AF AF 3 Moo O O KO CO 2 0 1 0 1 0 1 cl l c G GO O NS O 14 14 14 15 15 15 16 16 17 18 18 18 19 19 20 20 21 21 TOM Table of Contents Continued iE AAA APA SCHEMATIC DIAGRAMS cece I nnn LIST OF MATERIALS ale tle Rn PIE Meee Figure 15 Demo Board Level Schematic Figure 16 Demo Board Option Selection Switch Schematic Figure 17 Demo Board Option Input Output Connector Schematic Figure 18 Demo Board Timing Logic Schematic Figure 19 XR T6165 and XR T6166 Daughter Board Schematic Figure 20 XR T6164 LIU Daughter Board Schematic Table 10 XR T6164 65 66 Mother Demo Board Parts List Table 11 XR T6164 LIU Daughter Board Parts List Table 12 XR T6165 Daughter Board Parts List Table 13 XR T6166 Daughter Board Parts List LEE AFP MB NG NG a a L 4 22 22 23 24 25 26 27 27 28 29 29 29 TOM 2 N the analog plus company XR T6164ES Evaluation System OVERVIEW This demo board is an evaluation system for the XR T6164 LIU Line Interface Unit and XR T6165 6166 Codirectional Digital Data Processor integrated circuits that simplifies both functional tests and comprehensive measurements on these devices Test equipment requir
12. Recovery Circuit T6166 Pin 22 Receiver Byte Deletion Flag Output T6166 Pin 25 Receiver Byte Insertion Flag Output T6166 Pin 26 in 28 PCMOUT Receiver PCM Data Output T6166 Pin 28 Circuit Ground WORD SYNC 2kHz Sync Signal Output for Pattern Generator 4 Word Sequence Table 8 Test Point Functions BOARD OPERATION This description refers to Table 9 and Figure 6 through Figure 14 which are located at the end of this section Start up Procedure Perform the following steps to operate the demo board 1 Preset the four dip switches in the positions indicated in Table 9 Connect TX OUT to RX IN RJ 11 connectors together with the short modular cable supplied with the board This operation loops the XR T6164 LIU transmitter line side output to receiver line side input ASTE AV AWA NG NG ASA 14 3 Power the board by connecting a regulated power supply capable of supplying 5V 5 at least 1 Ampere to the red 5V and black Ground banana jacks Waveform Measurements The board is now in operation and Figure 6 Figure 7 and Figure 8 are examples of some of the waveforms that may be observed Figure 6 shows the acquisition of a byte of 2 048MBT Sec data by XR T6166 transmit side While the transmit time slot TS1T is high the 2 048MHz transmit clock TX2MHZ clocks the 8 bit pattern 10101 0 0 1 into the serial data input PCMIN The clock data and time slot edges are all aligned since these si
13. MOUT data as WORD 0 through WORD 3 are sequentially applied to the PCMIN input To change the pattern generator from a 1 word to 4 word sequence place S3 section 1 in the ON position This operation is summarized below Figure 10 Frame 1 10101001 Sent 00000001 Received Figure 11 Frame2 10000000 Sent 00010000 Received Figure 12 Frame 3 00000001 Sent 10101001 Received Figure 13 Frame4 00010000 Sent 10000000 Received Figure 14 Frame 5 10101001 Sent 00000001 Received Thus for the loopbacked condition data applied to the PCMIN input arrives at the PCMOUT output two frames later This may be verified by oscilloscope measurements made using the delayed sweep and triggering from the WORD SYNC test point Advanced Capabilities Many different timing measurements may be made by applying externally generated clocks and timing signals to the demo board The frame sync reference signals TSYNC OUT and RSYNC OUT may be used to trigger external signal sources These outputs are buffered with a 74 00 gate but if more drive capability is required a regular TTL part may be easily substituted since the device is in a socket Receive Buffer Tests The XR T6166 transmitter and receiver sides may be operated at slightly different frequencies if an external 8 192MHz clock source is used for the receive timing logic Therefore the effects resulting from the receive buffer either becoming empty or overflowing may be o
14. O TM WU 1 a wes A TXTIP 3 TXANG E TX OUT O PAD RU 11 J15 O PAD CHXTIP 5 lt EXENE x HX INP RJ 41 Figure 17 Demo Board Option Input Output Connector Schematic ALTE AV AV N NG NG NG w w w 25 TOM XR T6164 65 66ES w w w 5 NC 5 04096 4 e 8 WORDO is TXEMHZ gt X34 510 13 US 4 2 3 E VETERE 5 REMHZ Jabke 2 TXSYNC gt RXCLKS L TSELS 8 TSELS E TSEL4 10 11 Saal 1 men 1 5 9 2 5 X1 7 5 WOHDSEL mE 5 9 BSEL1 7 10 RSEL2 11 BSELS 5 13 BSELA 10 11 13 XSYNC 1 TBMHZ Figure 18 Demo Board Timing Logic Schematic MEE AW AV NG NG NG NG w a aa 26 TS48 gt T M Z EXAR XR T6164 65 66ES AM 49
15. Used OFF Bit is a Logic 1 1 WORDS 1 4 2 T256 EXT INT Selects Transmit Time 3 Through 7 Slot 1 Position TXTS1 PGM 5 Bit Binary Code is Bu MESS 2 0 5 J Table 1 DIP Switch 53 Functions Section Number and Name Selects 8 192MHz OFF External Clock Applied to R8MHZ IN Input 1 Receive Clock Source Used RACES EXTANT Clock Generated Internally By Demo Board Used Selects Receive Time OFF Bit is a Logic 1 3 Through 7 Slot 1 Position RXTS1 5 Bit Binary Code is Bit is a Logic 0 Gennes Ti Table 2 Dip Switch 54 Functions SESE AW AV NG NG NG NG w w a TOM 11 XR T6164 65 66ES Z EXAR A SU OF Time Slot Dip Switch Setting S3 and S4 Position SELO SEL1 SEL2 SEL3 SEL4 Table 3 TXTS1 and RXTS1 Selection Options MEE AV AV NG NG w w w a TOM 12 72 EXAR XR T6164 65 66ES Section Number and Name 1 through 8 Programs 8 bit Sets Bit in PCMIN Word 1 Transmitter PCMIN WORD 0 PCMIN Word 1 Input Data to a High Level Logic 1 BIT PGM Sets Bit in PCMIN Word 1 Transmitter Input Data to a Low Level Logic 0 Table 4 Dip Switch S2 Functions Wes 190100 UserPragammabie win S2 Table 5 Pattern Generator Bit Patterns Section Number and Name Controls PCMOUT Data Receiver Data at PCMOUT Always Forced to all 1 Blanking Ones Condition AIS Signal Blanking AIS OFF SES TS TOP VIR Logic Normal Re
16. XSYNC Figure 13 Frame 4 Timing with 4 Word Sequence Tes yO EP Er E PEE Tq PCMIN 1 1 TS1T MEE ns ARR oe quo l s TXSYNC WORDSYNC RX2MHZ PCMOUT TSIR ee jai RXSYNC Figure 14 Frame 5 Timing with 4 Word Sequence SESE AV N NG NG NG NG w w A TOM 21 XR T6164 65 66ES Z EXAR lt SCHEMATIC DIAGRAMS XR T6166 socket daughter boards and Figure 20 is the XR T6164 LIU daughter board diagram Figure 15 through Figure 18 contain the mother board schematic diagrams Figure 15 is a top level diagram and Figure 16 Figure 17 and Figure 18 show the Option Selection Connections and Timing Logic details Table 10 through Table 13 list all components used in the respectively Figure 19 contains the XR T6165 and 6164 65 66 evaluation system LIST OF MATERIALS ASTE AW a NG NG w w w TOM 22 Z EXAR OPTION SELECTION ALARMINBI SLAPMIN TTSEL BHEL ATSEL ATSEL BLSOFF BLSOFF BLANKING BI BLANKING 010 71 010 71 TSEL 0 4 TSEL 9 4
17. Z2 EXAR XR T6164 65 66ES J AN Z December 1996 2 XR T6164 T6165 T6166 Evaluation System User Manual MEE LP NG NG A A AF TOM EXAR Corporation 48720 Kato Road Fremont CA 94538 510 668 7000 FAX 510 668 7017 XR T6164 65 66ES Z EXAR A NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im prove design performance or reliability EXAR Corporation assumes no responsibility for the use of any circuits de scribed herein conveys no license under any patent or other right and makes no representation that the circuits are free of patent infringement Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user s specific application While the information in this publication has been carefully checked no responsibility however is assumed for inaccuracies EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness Products are not authorized for use in such applications unless EXAR Corporation receives in writing assurances to its satisfaction that a the risk of injury or damage has been minimized b the user assumes all such risks c potential liability of EXAR Corporation is ad
18. bserved The XR T6166 data sheet should be consulted for more information regarding this buffer To use an TOM XR T6164 65 66ES 2 EMAR 49 A APA external clock place S4 section 1 RCLK in the EXT OFF position and connect a stable adjustable 8 192MHz source with a TTL compatible output to the R8MHz IN BNC connector Momentarily pressing the RESET switch S5 will now synchronize the transmit and receive timing logic counters and all control signals that are derived from them However if the external and internal clock sources are not exactly the same frequency synchronization will be lost and a receiver slip will ultimately occur Transmit Buffer Tests The effects of an empty or overflow condition in the XR T6166 transmit may be observed by operating the transmitter with an external 256kHz transmit clock To use an external clock place S3 section 2 T256 in the EXT OFF position and connect a stable adjustable 256kHz source with a TTL compatible 5096 duty cycle square wave output to the T256kHz IN BNC connector The frequency of this external source must be carefully adjusted to obtain the desired results Note that no initial synchronization is necessary because no transmit time slot to 256kHz transmit clock phase alignment is required AWCIYIGATHNI SS KKIIII AIIMN XK AW NG NG a AF A 16 Timing Alignment Tests Many different timing alignment tests are possible if a laboratory pulse generator with
19. ceiver Output Data Present at PCMOUT Level BLS Byte Lock Supervision Not Active Data at Controls Byte Lock 2 Supervision PCMOUT is Always Receiver Input Data BLS OFF ON Sets T6166 Pin 4 Logic Level BLS Byte Lock Supervision Active PCMOUT Blanked When AIS Received Provides Alarm Input Signal Sets T6166 Pin 16 Logic Level Violations Used for Octet Timing in Transmitter Output Signal are Inhibited Alarm Condition APM N ONOI Violations Used for Octet Timing are Present in Transmitter Output Signal Normal Operation Selects Receive Time Slot Receive Time Slot 1 Internally Generated On Demo Board Used Receive Time Slot 2 Applied To RTS2 In Input Logic Level Used Section Not Used Table 6 Dip Switch S1 Functions 5 RATS Te Sets T6166 Pin 27 Selects Transmit Time Transmit Time Slot 1 Internally Generated on Demo 3 Slot Board Used TXTS 1 2 Sets T6166 Pin 15 Transmit Time Slot 2 Externally Applied to TTS2 IN Logic Level Input Used SESE AV AV A AV w w Av TOM 13 XR T6164 65 66ES Z EMAR 49 AAA BNC Conn TTS2 IN RTS2 IN RSYNC OUT TSYNC OUT R8MHZ IN Signal Description T256kHz IN External 256kHz Transmit Clock Input Connected to T6166 Pin 17 SPARE Uncommitted Connector SPARE Uncommitted Connector Table 7 BNC Connector Functions Transmitter Byte Insertion Flag Output T6166 Pin 18 Clock Seek Output from Receiver Clock
20. d the push button reset switch S5 will initially synchronize the transmit and receive counters S5 is non functional when the on board oscillator clocks both counters Any of the 32 possible transmit and receive time slot positions are user selectable by binary coded settings on S3 and S4 respectively S3 also selects pattern generator sequence length and XR 6166 transmitter 256kHz clock source S4 also selects receive timing logic 8 192MHz clock source Table 1 and Table 2summarize S3 and S4 functions respectively Table 3 lists the binary settings for S3 and S4 for all 32 time slots Pattern Generator The pattern generator produces 8 bit bursts of data at a 2 048 MBT Sec rate This data which may be either a repetitive one word 8 bit or four word 32 bit sequence simulates the information that is taken from a PCM system buss and applied to the XR 6166 transmit side serial input PCMIN The pattern generator produces one user programmable word WORD 0 followed by three fixed words that are determined by PAL programming It operates by decoding transmit timing logic counter outputs anding this signal with the decoded signal that becomes the transmit time slot and then retiming the result with the 8 192MHz clock and a D type flip flop The option of sending either WORD 0 repetitively or the entire four word sequence repetitively is available Table 4 shows WORD 0 programming by S2 and Table 5 lists the bit patterns for all four w
21. ements are minimized because a built in pattern generator supplies PCM test data and all timing signals are derived from an on board crystal oscillator Board operation requires only a 5V power source and an oscilloscope for observing data and timing waveforms Mechanically the unit is a 5 75 by 7 75 inch mother board that accepts a pair of 2 inch by 2 inch daughter boards The mother board contains timing logic option selection switches and I O connections One daughter board has the socket for either the XR T6165 or the XR T6166 device while the other holds the complete XR T6164 LIU circuit Programmable logic devices PALS are used for all mother board logic to make the unit electrically as well as mechanically versatile y onos AV NG NG NG NG 5 MECHANICAL DESCRIPTION Figure 1 shows the mother board component marking Option selection dip switches are located along the front edge Directly behind them are five PALS that generate timing signals an 8 192MHz crystal oscillator module that provides system clock and a 74HCOO device that de bounces the RESET switch and buffers PCM frame sync outputs Daughter boards for the XR T6165 or XR T6166 IC socket and for the XR T6164 LIU are behind the PALS Figure2 Figure 3 and Figure 4 show daughter board component markings BNC connectors that are located along the mother board right edge are used for sync and timing signal outputs and for external clock inputs Two RJ 11 and a s
22. equately protected under the circum stances Copyright 1996 EXAR Corporation User Manual December 1996 Reproduction in part or whole without the prior written consent of EXAR Corporation is prohibited ASTE A NB NB NG NG NG TOM 2 Table of Contents w w OVERVIEW MECHANICAL DESCRIPTION Figure 1 Mother Board Component Marking Figure 2 XR T6165 Daughter Board Component Marking Figure 3 XR T6166 Daughter Board Component Marking Figure 4 XR T6164 LIU Daughter Board Component Marking ELECTRICAL DESCRIPTION Block level Overview Timing Generation Pattern Generator ccs a tae Get Men E RIPE E a in XR T6165 6166 Time Slot Selection and Alarm Control Demo Board Power Requirements Input Output Connections 64 KBT Sec Signal Connections BNC Connections un WG ccc E Test Points Figure 5 Demo Board Block Diagram Table 1 DIP Switch S3 Functions Table 2 Dip Switch S4 Functions Table 3 TXTS1 and RXTS1 Selection Options
23. external trigger adjustable delay between trigger and pulse output and adjustable output pulse width is available The basic procedure is to trigger the generator from TSYNC OUT or RSYNC OUT as required and then use the generator output to provide the transmit or receive time slot signal This externally generated time slot is applied by selecting time slot 2 with S1 and then feeding the signal directly into the XR T6166 through TTS2 IN or RTS2 IN as appropriate The generator trigger delay determines the time slot position and the output pulse width control sets the time slot width Although the internally generated time slot with ideal timing is not being used it is still present at the XR T6166 time slot 1 input Therefore it may be conveniently monitored with an oscilloscope and used as areference for adjusting the externally produced time slot position and width The effects of moving the time slot position relative to the XR T6166 transmit or receive 2 048MHz clock may now be investigated Note that since the pattern specified for WORD 0 1010100 1 has a one on each end it is useful when testing for dropped bits A pattern with a zero on each end should be used when testing for added bits TOM 72 EXAR XR T6164 65 66ES EN PEO Santen Option Selected 1 ON Normal Receiver Data at POMOUT Not AIS BLS Byte Lock Supervision Active OFF Transmit Time Slot 1 Selected x ON
24. gnals TOM Z EXAR XR T6164 65 66ES 49 49 w w which are derived from the transmit timing logic synchronous counters are all re timed by the 8 192MHz system clock The bottom trace in Figure 6 shows the 256kHz transmitter output clock TX256kHz As described in the timing logic section this clock does not have edge alignment with the other three waveforms because it is not retimed Note that there is not a phase alignment requirement constant but not a specific phase alignment is necessary between the 6166 transmitter input timing signals and output clock If this phase changes because of input or output clock frequency changes data slips will occur Figure 7 shows the XR T6166 receive side output process for a byte of 2 048MBT Sec data While the receive time slot TS1R is high the 2 048MHz receive clock RX2MHZ clocks the 8 bit pattern 1 0 1 0 1 0 0 1 out the serial data output PCMOUT Note that the relationship between the bottom trace RSYNC OUT and the receive time slot TS1R indicates that this time slot is in position O Figure 8 shows the 6164 LIU transmitter side bipolar output signal For this photograph the looped connection between TX OUT and RX INP was removed and TX OUT was terminated with 1200 The top trace which is TSYNC OUT represents one PCM frame therefore has a 125uS period The bottom trace shows the encoded bipolar signal that represents the repetitive 1 0101001 bit patte
25. iming signals for maximum versatility The transmit and receive time slot signals TS1T and TS1R are obtained by decoding the respective counter outputs and then using the 8 192MHz clock and a D type flip flop to re time the signal Thus these outputs are glitch free The transmit and receive clocks TX2MHZ and RX2MHZ come from a single counter output and are retimed to preserve alignment with the time slot edges The 256kHz transmit clock TX256kHz transmit frame sync TSYNC OUT receive frame sync RSYNC OUT and pattern generator WORD SYNC also come from single counter outputs but are not retimed because alignment with a MEE AW AV NG NG w w AF aa 8 time slot edge is not required Therefore these signals arrive one 8 192MHz clock period before the retimed signals The transmit counter is always clocked by the on board 8 192MHz crystal oscillator module However the receive counter may be clocked either by this oscillator or by an external 8 192MHz source The 2 input to 1 output receive clock multiplexer that is controlled by S4 section 1 does this selection Receive counter reset is performed through the 2 input to 1 output reset multiplexer When the on board oscillator is used to clock both counters the receive counter is synchronously reset every four PCM frames by the transmit counter CLROUT pulse Thus synchronization is automatically obtained between the two counters When an external receive clock source is use
26. iver input An unconnected RJ 45 jack that may be used for both input and output functions is also provided This jack may be easily connected as required since all eight pins are brought out to PC board pads BNC Connections Inputs for external clocks and timing signals as well as transmit and receive sync outputs are made through BNC connectors Two extra connectors are provided for use as needed Table 7 lists the connector functions Test Points Test points provide access to a number of different XR T6166 output signals and circuit ground Their functions are listed in Table 8 For convenience the test point signals are also connected to small PC board pads that are located under the XR T6166 daughter board TOM XR T6164 65 66ES Ay OF BLOCK DIAGRAM 2 EXAR B B D I T T 1 11
27. ords The distinctive patterns with a single one bit were chosen for words 1 2 and 3 because they make it easy to observe the delay through the looped back system on an TOM Z EXAR XR T6164 65 66ES lt oscilloscope This procedure is explained in more detail in the section on board operation XR T6165 6166 Time Slot Selection and Alarm Control The XR T6165 6166 contains internal 2 input to 1 output multiplexers that select one of two available transmit and receive time slot sources Both transmit and receive time slot 1 are generated on board while time slot 2 is obtained from an external source Also three transmit and receive alarms options are available Table 6 summarizes the functions controlled by S1 Demo Board Power Requirements A well regulated 5 0 5 V source of at least 1 Ampere is necessary for board operation Power connections are made through red 5 and black Ground banana jacks Input Output Connections 64 KBT Sec Signal Connections The LIU transmitter output and receiver input 64 KBT S signal connections are made through RJ 11 jacks located ALTE AW AW N AV NG NG w w 9 at the rear of the board The short jumper cable supplied with the board is used to connect the transmitter output to the receiver input during testing This jumper does not contain a twist like a modular telephone cord A standard modular cord will give a tip ring reversal between transmitter output and rece
28. ote that this device does not have the RXCKOUT CS BIR BDR BIT and BDT outputs that are present on the XR T6166 Consult the device data sheets for more detailed information on each part Block level Overview The block diagram given in Figure 5 outlines the major demo board functions It illustrates data and timing signal flow and shows option selection switch connections to the different functional blocks The top part of the diagram contains the transmit and the bottom part has the receive sides of the XR T6166 digital processor and XR T6164 LIU Signal flow is clockwise starting with the pattern generator The pattern generator supplies 8 bit bursts of 2 048MBT Sec serial PCM data to the XR T6166 transmitter PCMIN input The XR T6166 transmitter T R and T R outputs feed continuous dual rail 64 KBT Sec encoded data into the XR T6164 LIU The bipolar signal produced by the LIU transmitter is connected to the LIU receiver input by a short modular cable The LIU receiver output dual rail data is connected to the XR T6166 receiver S R and S R inputs The XR T6166 receiver PCMOUT output provides 8 bit bursts of 2 048 MBT Sec PCM data The signal at this test point may be observed on an oscilloscope Timing Generation Logic The timing generation logic uses synchronous counters clocked at 8 192MHz rate to produce all the control signals necessary for XR T6166 operation Separate counters are used for generating the transmit and receive t
29. pacing Panasonic NHE 4 R1 2 3 4 10K 2 10 Resistor Thick film Network Digi Key Q9103 ND Panasonic R5 10 2 21K 1 4 W 1 Resistor Digi Key 2 21KBKX ND R6 7 8 51 10 1 4 W 1 Resistor Digi Key 51 1BKX ND 1 2 3 4 8 Position Dip Switch Amp Digi Key A5308 ND SPDT Momentary Push Button Switch Digi Key CKN4014 ND C amp K 8125SD9ABE 8 Pin Header 0 42 Pins on Top End Digi Key S1041 36 ND Cut from 36 Pin Strip 16 Pin Header 0 42 Pins on Top End Digi Key S1041 36 ND Cut from 36 Pin Strip S5 1 2 3 4 15 2 3 4 5 6 1 J J J8 9 10 11 12 13 14 PC Board Mount Female BNC Connector NEWARK Part No 44F8494 KC 79 07 M06 wee 22V10 PAL RX2 Custom Programmed Part 22V10 PAL TX3 Custom Programmed Part SG 51P8 192MC 24 Pin IC Socket 0 3 Spacing esed 4 40 x 5 16 Screws for Spacers i Short Modular RJ 11 Cord to Loop Board U U U U U U X Table 10 XR T6164 65 66 Mother Demo Board Parts List ASTE AW AV TOM 28 72 EXAR XR T6164 65 66ES o T 4 C1 2 3 4 0 1uF 63V Z5U Dielectric Axial lead 0 1 Digi Key P4917 Spacing 3320 1 4 W 1 Resistor Digi Key 332BKX ND 4640 1 4 W 1 Resistor Digi Key 464BKX ND U1 J1 2 0 1 Bottom Entry Board Connector 8 Pin Digi Key WM3228 ND Molex 22 17 3082 Use 2 Sets for a 16 Pin Connector 1 1 16 Pin IC Socket Digi Key ED 3316 ND Table 11 XR T6164 LIU Daughter Board Parts List
30. pare RJ 45 modular connector for 64 KBT S I O connections and test points for XR T6165 6166 output signals are located on the board rear edge The test point signals are also present at small pads that are under the daughter boards Therefore any two of these signals may be easily connected with short jumper wires to the spare BNC connectors that are between the daughter boards Power connections are made through two banana jacks that are located on the board left edge TOM XR T6164 65 66ES lt aw OF ayog 0440 99 53 9191 4 2 1 I Y 220 Us QN9 B NO e e o 1 e e e CEN RXALM H e gt e e e 23019 e e eS e RX INP w D2 e 7 aS 03 e e e 59060009 9 04 e AU c ME SS pse e e 9 e 5 06 e e e e E zm e ES Dre e e e e 5 gt CD i ag HZ e RI on 25 o e 1 4 eo lt e B 15 me T WORDS 1
31. rn that was applied to the PCMIN input Annotation located on the picture below the bottom trace summarizes the coding process for each bit position and indicates the bipolar violations that are used for octet timing Figure9 is a timing diagram that contains more information than can be shown on a 4 trace oscilloscope It shows both the XR T6166 receive side PCMIN input data and the transmit side PCMOUT data for the repetitive 1 0 1 0 1 0 0 1 bit pattern Note that this fixed relationship exists between the XR T6166 receiver and transmitter because the demo board is operating in the mode where all timing is derived from the on board 8 192MHz oscillator With the exception of changing TS1R receive time slot 1 from position 0 to position 1 by placing S4 section 3 RSELO in the OFF position conditions for this diagram are the same as for the photographs described previously Although this diagram indicates the relationship between transmitting in time slot position 0 and receiving in time slot position 1 it provides no information about the delay through the ALTE AW AV NG NG NG a 15 loopedback system However this delay can be measured by using a repetitive 4 word sequence Operation With A Repetitive 4 Word Sequence A repetitive 4 word 32 bit sequence allows the measurement of the XR T6166 serial PCM input PCMIN to output PCMOUT delay The timing diagrams given in Figure 10 through Figure 14 show PCMIN and PC
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