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iVPX7225 Installation and Use manual

1. PERSPSER 23 INE Features PET 23 1 2 Standard Compliances 4 25 1 3 Mechanical Data er eee debeo 26 1 34 Air Cooled pe 26 1 3 2 Conduction Cooled 4 ene es m 27 1 4 Ordering Information 2 2 24 2 2 24 2 27 1 4 1 Supported Board Models 27 1 5 Product d ntification es na 29 2 Hardware Preparation and Installation 31 2 1 OVerview Cy 31 2 2 Unpacking Inspecting the Board 31 2 3 Environmental and Power Requirements 32 2 3 1 Environmental Requirements 32 2 3 2 Power Requirements ces teer rr ann 34 2 4 Installing the Accessories uu een en 34 2 4 1 Installing the XMC on Air Cooled Board 36 2 4 2 Installing the XMC on Conduction Cooled Board 37 2 4 3 RearTransition Module 40 2 5 Installing and Removing the 41 2 5 1 Installi
2. 112 7 1 5 FPGA Month Code Register 0x05 113 7 1 6 FPGA Year Code Register0x06 113 7 1 7 FPGA Reset Cause lt 0 08 113 7 1 8 Watchdog Control Register 0X09 115 7 1 9 Watchdog lt 0 0 116 7 1 10 Memory Write Protect 0 0 116 7 1 11 Power Good Status 1 Register 0x0C_ 118 7 1 12 Power Good Status 2 Register 0x0D 119 7 1 13 System Status Register OXOE cece nen 119 7 1 14 Misc 1 Control and Status Register 0x10 120 7 1 15 Misc 2 Control and Status Register 11 121 7 1 16 DIP Switch Status Register 0x14 _ 122 7 1 17 Misc Control and Status Register 0 15 123 7 1 18 Boot Control and Status 1 Register 0x16 124 7 1 19 Boot Control and Status 2 Register 0x17 125 7 1 20 PCIE Switch Control and Status 1 Register 0x18
3. 139 7 3 1 1 Received Buffer Register RBR 140 7 3 1 2 Transmitter Holding Register THR 140 7 3 1 3 Interrupt Enable Register 141 7 3 1 4 Interrupt Identification Register IIR 142 7 3 1 5 FIFO Control Register FCR 144 7 3 1 6 Line Control Register LCR 145 7 3 1 7 Modem Control Register MCR 147 7 3 1 8 Line Status Register LSR 148 7 3 1 9 Modem Status Register MSR 152 7 3 1 10 Scratch Register SCR 155 7 3 1 11 Programmable Baud Rate Generator 155 A Related Documentation 157 Emerson Network Power Embedded Computing Documents 157 2 Related 5 u ee een RR RR P ER sisa pa 158 Safety 160 Sicherheits hinweise s ann uyu ER Ea C REGE uq M IEEE 8 iVPX7225 Installation and Use 6806800511 7 Contents 8 iVPX7225 Installation and Use 68068
4. 143 FIFO Control Register FCR 144 Line Control Register LCR 145 Modem Control Register MCR 147 Line Status Register LSR 149 Modem Status Register MSR 153 iVPX7225 Installation and Use 6806800511 List of Tables Table 7 55 Table 7 56 Table 7 57 Table 7 58 Table 7 59 Table 7 60 Table A 1 Table A 2 Scratch Register LCR 4 155 Divisor Latch LSB Register DLL if DLAB 1 nu en 156 Divisor Latch MSB Register DLM if DLAB 1 156 Logical Device 0x74 Reserved 156 Logical Device 0x75 Reserved 156 Logical Device 0xFO Reserved Register 156 Emerson Network Power Embedded Computing Publications 157 amp de en a a ib ea 158 iVPX7225 Installation and Use 6806800511B 11 List of Tables 12 iVPX7225 Installation and Use 6806800S11B List of Figures Figure 1 1 IVPX7225 Air Cooled 26 Figure 1 2 iVPX7225 Conduct
5. 92 5 9 16 SIO Configuratio Me rte meh RR Re 93 5 9 17 ME Configuration uus ceed tere a 94 5 9 18 Thermal Configuration 95 5 9 19 Platform Thermal Configuration 96 5 9 20 Intel Rapid Start Technology lesse 98 5 9 21 IVPX7225 Menu use n d spantene aha ERES UU e Red E ERE nn 99 5 9 22 Security Menu ERR RE u 100 5 9 23 TPM Configuration devas e ee lex x Rr asna ne 102 5 9 24 Boot Menu 55 o epe obit MEG Rab UU Dean He 103 5 925 Exit Menu uu uu ee nine ee eu Eee e NO APER CR 104 5 10 BIOS POST Codes assise ee ee einer seen 105 iVPX7225 Installation and Use 680680051 1B Contents 5 11 Memory POST Codes 107 6 Maps and Registers yuru ul cian ses Pee ed 109 6 1 d Map MC 109 6 2 BIOS Memory Map a a le 109 T FPGA EA 111 2 1 FPGAREGISTENS suerte ed ans 111 7 1 1 Blade Revision Register 0 00 111 7 1 2 FPGA Major Revision Register 0x01 112 7 1 3 FPGA Minor Revision 1 lt 0 02 112 7 1 4 FPGA Date Code Register 0x04
6. Index Address 0x30 Access LPC R W Bit Description Default Logical Device Enable 0 disabled Currently selected device is inactive 1 enabled The currently selected device is enabled Reserved LPC R 136 iVPX7225 Installation and Use 6806800511 FPGA Registers Table 7 39 Logical Device Base IO Address MSB Register Index Address 0x60 Bit Description Default Access Logical Device Base IO Address MSB 5 LPC R W Table 7 40 Logical Device Base IO Address LSB Register Index Address 0x61 2 0 Bits 0 to 2 are read only Decode is on 8 Byte LPC R boundary Logical Device Base IO Address LSB Bits 3 to LPC R W 7 Registers 0x60 MSB and 0x61 LSB set the Logical Device Base IO for this logical device For example for Base IO address Ox3F8 the content of Register 0x60 is 0x03 and the content of Register 0 6115 OxF8 See table below for default IO addresses Table 7 41 Logical Device Common Decode Ranges Ox3F8 Ox3FF COMI Ox2F8 Ox2FF COM2 Ox2E8 Ox2EF COM3 iVPX7225 Installation and Use 6806800511 137 FPGA Registers Table 7 42 Logical Device Primary Interrupt Register Index Address 0x70 Bit Description Default Interrupt level is used for Primary Interrupt 0x0 0 1 0x2 0x3 0 4 0 5 0 6 0 7 0 8 0 9 no interrupt selected IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6
7. SYS CONL 10K PUto 3 3V AUX VPX PCIE FP1 LANE3 TXN PCIE FP1 LANE 3 TX P PCIE FP2 LANE 0 TXN GND PCIE FP2 LANE 0 TX P PCIE FP1 LANE 3 RX N PCIE FP1 LANE 3 RX P PCIE FP2 LANE 0 RX N GND PCIE FP2 LANE 0 RX P GND GND PCIE FP2 LANE 1 TXN PCIE FP2 LANE3 TXN PCIE FP2 LANE 1 TXP PCIE FP2 LANE 2 TXN PCIE FP2 LANE 3 TX P PCIE FP2 LANE 2 TX P GND PCIE FP2 LANE 1 PCIE FP2 LANE 3 RX N PCIE FP2 LANE 1 RX P PCIE FP2 LANE 2 RX N PCIE FP2 LANE 3 RX P PCIE FP2 LANE 2 RX P GND CRT BLUE GND CRT HSYNC CRT VSYNC GND CRT CLK CRT DATA GND IPMC1 SCL GND CRT GREEN GND USBO PEN GND CRT RED USBIN Reserved GPIO 0 PCH GPIO 17 GND GPIO 1 PCH GPIO 22 USBON GND USBOP USB2 N USB OCP L GPIO 2 PCH GPIO 6 GND GPIO 3 PCH GPIO 7 GPIO 4 PCH GPIO 68 GPIO 5 PCH GPIO 69 GND iVPX7225 Installation and Use 6806800S11B GPIO 6 PCH GPIO 70 GPIO 7 PCH GPIO 71 GND Table 3 5 P1 Connector Pinout continued Controls LEDs and Connectors Row G MRSTL 4 75K PU to 3 3V AUX VPX GND Row F ETH LANE 0 TXN Row ETH LANE 1 TXN ETH LANE 0 TXP Row D ETH LANE 1 TXP GND Row C Row B ETH LANE 1 RXN ETHLANEO RXN ETHLANEO RXP Row ETH LANE 1 RXP GND 1 The iVPX7225 PC
8. Bit Description Default LPC Access 2 Access 7 0 CPU Package Temperature Reading 0x00 R W In hexadecimal value 7 1 23 IPMC Inlet Temperature Sensor Status Register 0x1D Table 7 23 IPMC Inlet Temperature Sensor Status Register Ox1D Bit Description Default LPC Access I2C Access 2 Reserved 0 RO R 3 Reserved 0 RO R 128 iVPX7225 Installation and Use 6806800511 FPGA Registers Table 7 23 IPMC Inlet Temperature Sensor Status Register Ox1D continued Bit Description Default LPC Access I2C Access 5 meer fe LEE Ds mew 7 1 24 IPMCOutlet Temperature Sensor Status Register 0x1E Table 7 24 IPMC Outlet Temperature Sensor Status Register Bit Description Default LPC Access I2C Access re Je Tw o fw Reserved R Reserved RO Reserved RO Reserved 7 6 Reserved 7 1 25 FRAM Page Access Register 0x20 Table 7 25 FRAM Page Access Register 0x20 Bit Description Default LPC Access I2C Access FRAM Page Select 0x00 R W 0x0 Page 0 access first 64K block of FRAM to OxF Page 15 access last 64K block of FRAM iVPX7225 Installation and Use 6806800511 129 FPGA Registers Table 7 25 FRAM Page Access Register 0x20 continued Bit Description Default LPC Access 2 Access mem 7 1 26 VPXSystem Register 0x2
9. Ethernet Controllers Intel 82580 Ethernet Controller Ethernet control plane Optional Transition Mod Mini DisplayPort VGA USB 2 0 Ethernet Serial I2C ules GPIO SATA XMC IO write protect override switches 24 iVPX7225 Installation and Use 680680051 1B Introduction Table 1 1 Key Features of the iVPX7225 Features Description Other Features FPGA Watchdog Timer Trusted Platform Module TPM Intel vPro Technology capable supports Intel TXT VT and TPM VITA 46 11 system management IPMI V1 5 compliant Multiple 32 bit timers Temperature sensors Status and user LEDs Reset switch Locking ejector handles Configuration DIP switch Reset switch XMC site Gen 2 PCle support also provisioned for SATA sup port UEFI BIOS Designed for Draft 0 8 of VITA 46 11 system management for VPX 1 2 Standard Compliances The following table details the Standard Compliance information Table 1 2 Standard Compliances Standard Description FCC 47 CFR Part 15 Subpart B US ClassA EMC requirements ICES 003 Class A non residential VCCI CLASS A Japan EN55022 Class A EN55024 AS NZS CISPR 22 Class iVPX7225 Installation and Use 6806800511 25 Introduction 1 3 Mechanical Data The following table provides details about the Form factor and weight of both Air Cooled and Conduction Cooled Assemblies Table 1 3 Mechanical Data
10. IO Address Base Transmitter Holding Register THR Undef In FIFO mode writing to THR puts data to the top of the FIFO The data at the bottom of the FIFO is loaded to the shift register when it is empty iVPX7225 Installation and Use 68068005118 7 3 1 3 Interrupt Enable Register IER FPGA Registers This register enables four types of interrupts which independently activate the int signal and set a value in the Interrupt Identification Register Each of the four interrupt types can be disabled by resetting the appropriate bit ofthe IER register Similarly by setting the appropriate bits selected interrupts can be enabled Table 7 46 Interrupt Enable Register IER if DLAB 0 IO Address Base 1 Bit Description Receive data interrupt enable disable 1 receive data interrupt enabled 0 receive data interrupt disabled Default Access R W Transmitter holding register empty THRE interrupt enable disable 1 THRE interrupt enabled 0 THRE interrupt disabled Receiver line status interrupt enable disable 1 receiver line status interrupt enabled 0 receiver line status interrupt disabled R W R W Modem status interrupt enable disable 1 modem status interrupt enabled 0 modem status interrupt disabled Reserved iVPX7225 Installation and Use 680680051 1B R W 141 FPGA Registers 7 3 1 4 142 Interrupt Identification Register IIR
11. Month Code Register 0x05 Table 7 5 FPGA Month Code Register 0x05 Bit Description Default LPC Access 2 Access He wena fe 7 1 6 FPGA Year Code Register 0x06 Table 7 6 FPGA Year Code Register 0x06 Bit Description Default LPC Access I2C Access He penes fe 7 1 7 FPGA Reset Cause Register 0x08 Table 7 7 FPGA Reset Cause Register 0x08 Bit Description Default LPC Access 2 Access Reset due to power cycle 0 Reset not due to power cycle 1 Reset due to power cycle Reset due to watchdog timeout on BIOS boot failure 0 Reset not due to watchdog timeout 1 Reset due to watchdog timeout Reset due to watchdog timeout on OS failure 0 Reset not due to watchdog timeout 1 Reset due to watchdog timeout iVPX7225 Installation and Use 6806800511 113 FPGA Registers Table 7 7 FPGA Reset Cause Register 0x08 continued Bit Description Default LPC Access 2 Access Reset due to IPMC reset request 0 Reset not due to IPMC reset request 1 Reset due to IPMC reset request Reset due to front panel push button switch 0 Reset not due to front panel push button switch 1 Reset due to front panel push button switch Reset due to RTM front panel push button switch 0 Reset not due to RTM front panel push button switch 1 Reset due to RTM front panel push button switch Reset due to CPU Thermal T
12. Table 3 6 P2 Connector Pinout continued GND SATAP2TXN SATA P2 TX P Row A SATA P2 RX P DPD DON DPD DOP DPD D1N DPD D1 P GND ME HPD DPD D2N DPD D2 P DPDD3N DPD D3 P 10 ano DPDDATA DPDCIK DPDAUXN DPDAUXP GND P2XMC 12D 1 P2XMC 12D 1 P2XMC 12D 2 N P2 12D 2 P P2 XMC 12D 3N P2 XMC 12D 7N P2 XMC 12D 3 PIGND P2 XMC 12D 5 N P2 XMC 12D 7 PIGND P2 12D 4N P2 12D 4 PIGND P2XMC 12D 5 PIGND P2XMC 12D 6 N P2 XMC 12D 6 P P2 XMC 12D 8 N 2 XMC 12D 8 PIGND GND P2 12D 11N 2 12D 9 P2XMC 12D9P P2XMC 12D 11 P2 XMC 12D 10 P2 XMC 12D 10 GND P2 XMC 12D 12 P2 XMC 12D 12 GND P N XMC Connector The following tables detail the pinout of the on board connector XJ15 and X 16 Table 3 7 15 Connector Pinout 5V VPX PWR PEG L1 RX L1 RX 3 3V VPX PWR MRSTI 1K PD GND GND NC LO RX LO RX 5V VPX PWR 3 RX PEG RX 3 3V VPXPWR PEG L2 RX 12 RX NC 10K PU to ov VPX PWR 56 iVPX7225 Installation and Use 68068005S11B Table 3 7 15 Connector Pinout continued Controls LEDs and Connectors Pin Row F Row A 5V VPX PWR 15 RX L5 RX 3 3V VPXPWR PEG L4 RX 14 RX 7 5V VPX PWR 12V AUX 5 L4 PEG L7 RX PEG 17 RX 3 3V VPX PWR PEG 16 RX _L6_
13. Embedded Computing for Business Critical Continuity IVPX7225 Installation and Use P N 680680051 1B November 2013 EMERSON Network Power CopyRight 2013 Emerson Network Power All rights reserved Trademarks Emerson Business Critical Continuity Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co 9 2011 Emerson Electric Co All other product or service names are the property of their respective owners Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Java and all other Java based marks are trademarks or registered trademarks of Sun Microsystems Inc in the U S and other countries Microsoft Windows and Windows Me are registered trademarks of Microsoft Corporation and Windows is a trademark of Microsoft Corporation PICMG CompactPCI AdvancedTCA and the PICMG CompactPCI and AdvancedTCA logos are registered trademarks of the PCI Industrial Computer Manufacturers Group UNIX is a registered trademark of The Open Group in the United States and other countries Notice While reasonable efforts have been made to assure the accuracy of this document Emerson assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Emerson reserves the right to revise this document and to make changes from ti
14. Feature Air Cooled Conduction Cooled Form factor Per VITA 48 1 Per VITA 48 2 Weight 0 33 kg 0 75 Ib 0 39 kg 0 86 Ib 1 3 1 A Air Cooled The following figure shows an Air Cooled type iVPX7225 board Figure 1 1 iVPX7225 Air Cooled 26 iVPX7225 Installation and Use 6806800511B Introduction 1 3 2 Conduction Cooled The following figure shows a Conduction Cooled type iVPX7225 board Figure 1 2 7225 Conduction Cooled 1 4 Ordering Information 1 4 1 Supported Board Models The following table lists the variants that are available upon release of this publication As of the printing date of this manual this guide supports the board models listed below iVPX7225 Installation and Use 680680051 1B 27 Introduction Consult your local Emerson sales representative for the availability of other variants Table 1 4 Available Board Variants Order Number Description iVPX7225 02250822 3U VPX AIR COOLED DUAL CORE 2 5GHZ 3555LE 8GB DDR3 1 FP ENP2 iVPX7225 02250813L 3U VPX CONDUCTION DUAL CORE 2 5GHZ 3555LE 8GB DDR3 85 PITCH ENP3 iVPX7225 02250802 3U VPX AIR COOLED DUAL CORE 2 5GHZ 3555LE 8GB DDR3 8 FP ENP2 iVPX7225 RTM 3U VPX AIR RTM FOR iVPX7225 8 FACEPLATE iVPX7225 RTM 1 3U VPX AIR COOLED RTM FOR iVPX7225 1 FACEPLATE Table 1 5 Accessories Order Number Description SERIAL MINI D 30 W2400E01A Female to male micro mini DB 9to DB9 adapter cabl
15. HE Conf igurat ion gt Thernal Conf igurat ion gt ICC Conf iqurat ion gt Intel R Rapid Start Technology Setup Warning 76 iVPX7225 Installation and Use 6806800511B BIOS Boot Iten Specific Help gt Processor Configuration gt Peripheral Conf igurat ion gt HDD Conf igurat ion iRST Intel R Rapid gt Henory Conf igurat ion Start Technologu gt Systen flgent SR Conf igurat ion Conf igurat ion South Bridge Conf igurat ion gt Hetuork Conf igurat ion 1 Conf igurat ion gt SHBIOS Event Log HE Conf igurat ion gt Thernal Conf igurat ion gt ICC Conf igurat ion Setup Harning Setting itens on this screen to incorrect values nay cause the systen to nalfunct ion Setting the values on this menu particularly its sub menus with non default values may cause he board to not perform properly iVPX7225 Installation and Use 6806800511 77 BIOS 5 9 4 Processor Configuration Figure 5 4 Processor Configuration COM1 115200baud Tera Term VT Elle Edit Setup Control Window Help Processor Conf igurat ion Iten Specif ic Help Hunber of cores to Intel R HT Technologu Enabled enable in each CPU Flex Ratio Override Disabled processor package Dunanic FSB Suitching Enabled Enabled 0 Enabled Intel R DCA Disabled Linit Cpuid Haxinun value Disabled Enable for BIST Disabled Hachine Check Enabled Fast Strings Enabled Fast Break Snoop Enable
16. 680680051 1B Controls LEDs and Connectors 3 3 FrontPanel Connectors and LEDs The front panel provides the following connectors and LEDs Figure 3 3 X Air Cooled Front Panel Connectors and LEDs Figure 3 4 Conduction Cooled Front Panel Connectors and LEDs iVPX7225 Installation and Use 680680051 1B 51 Controls LEDs and Connectors The following table contains detailed description of default behavior user control options for these FP LEDs Table 3 3 Face Plate LEDs LED Color Description Red Amber IPMC controlled LED The LED state is controllable via the VITA46 11 LED commands By default IPMC locally turns on the LED1 when payload becomes activated or deactivated An IPMI OEM command is provided to override this behavior so that IPMC disables the local control behavior as described above IPMC controlled LED The LED state is controllable via the VITA46 11 LED commands By default IPMC locally turns off the LED2 when payload becomes activated or deactivated An IPMI OEM command is provided to override this behavior so that disables the local control behavior as described above IPMC controlled LED The LED state is controllable via the VITA46 11 LED commands By default IPMC locally turns on the LED3 when payload is not activated and turns off the LED3 when payload is activated IPMC will also set LED3 to be blinking locally during the de activation An IPMI OEM command is provide
17. Data Reading the modem Status Set Ready Ring status register Indicator Received Line Signal Detect FIFO Control Register FCR is a write only register that is located at the same address as the IIR IIR is a read only register FCR enables disables the transmitter receiver FIFOs clears the transmitter receiver FIFOs and sets the receiver FIFO trigger level Table 7 50 FIFO Control Register FCR IO Address Base 2 Bit Description FIFO enable disable 1 Transmitter and Receiver FIFO enabled 0 FIFO disabled Default Access Receiver FIFO reset 1 Bytes in receiver FIFO and counter are reset Shift register is not reset bit is self clearing 0 No effect Transmit FIFO reset 1 Bytes in receiver FIFO and counter are reset Shift register is not reset bit is self clearing 0 No effect Receiver Transmitter ready Not supported Reserved iVPX7225 Installation and Use 68068005118 FPGA Registers Table 7 50 FIFO Control Register FCR IO Address Base 2 Bit Description Default Access 7 6 Receiver FIFO interrupt trigger level 0 W 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 7 3 1 6 Line Control Register LCR In the Line Control Register LCR the system programmer specifies the format of the asynchronous data communications exchange The serial data format consists of a start bit logic 0 five to eig
18. GND GND NC GND PEG_L6_RX GND 5V VPX PWR NC NC NC NC NC XMC GAO GND GND NC GND GND 5V VPX PWR XMC_PRSNT_L 10K PU to 3 3V VPX PWR PEG 11 TX PEG L1 TX XMC_MBIST_L XMC 1 PEG LO TX 10 TX 5V VPX PWR L3 TX PEG L3 TX 3 3 AUX VPX PEG L2 TX 12 TX IPMC1 SDA GND GND GA2 GND GND 5V VPX PWR 15 TX L5 TX NC PEG L4 TX PEG L4 TX 17 NC PEG L6 TX PEG L6 TX 18 NC GND GND NC GND GND 19 NC XMC ROOTO XMC WAKE NC REFCLK REFCLK L L Table 3 8 16 Connector Pinout RowF RowE RowD Row Row B Row NC X8D OPT NC X8D OPT Pin 1 PLX TDI GND PLX TRST L P2XMC 12D 2P P2XMC 12D 2N ND IPMC TDI SATA RX SATA RX IPMC_TDO D D 5 G GN GN PLX TMS NC X8D OPT NC X8D OPT IPMC_TMS NC X8D OPT NC X8D OPT IPMC RST L P2XMC 12D 1P P2XMC 12D 1 N ETH TDI ND GND PLD TDI GND GND iVPX7225 Installation and Use 680680051 1B 57 Controls LEDs and Connectors Table 3 8 XJ16 Connector Pinout continued Pin RowF RowE RowD Row Row B Row 7 ETH TDO P2XMC12D4P P2XMC12D4N PLD P2XMC 12D3P P2XMC 12D3N 8 9 ETH TMS GND PLD TMS GND GND _ 2 12D6P P2XMC 12D6N PLD P2XMC 12D 5P P2XMC 12D5N SPI MOSI NC X8D OPT NC X8D OPT CPI TDO SATA
19. IRQ7 IRQ8 IRQ9 OxA IRQ10 OxB IRQ11 OxC IRQ12 OxD IRQ13 OxE IRQ14 OxF IRO15 Access LPC R W Reserved v g Aninterruptis activated by enabling this device offset 0x30 setting this register to a non NN value and setting any combination of bits 0 4 in the corresponding UART IER and the occurrence of the corresponding UART event i e Modem Status Change Receiver Line Error Condition Transmit Data Request Receiver Data Available or Receiver Time Out and setting the OUT2 bit in the MCR 138 iVPX7225 Installation and Use 6806800511 7 9 Registers UART Register Overview The UART units may be mapped via Super IO LPC bus Table 7 43 shows the registers and their addresses as offsets of a base address for one of the two UART units The state of the Divisor Latch Bit DLAB which is the MOST significant bit of the Serial Line Control Register SCR affects the selection of certain of the UART registers The DLAB bit must be set high by the system software to access the Baud Rate Generator Divisor Latches DLL and DLM Table 7 43 UART Register Overview LPCIO or Primary I O Address DLAB Bit value Description Receiver Buffer RBR Read Only Base 0 Base 0 Transmitter Holding THR Write Only Base 2 Interrupt Identification Register IIR Read Only Base 2 FIFO Control Register FCR Write Only Base 3 Line Control Regist
20. Reserved 126 iVPX7225 Installation and Use 68068005118 FPGA Registers Table 7 20 PCIE Switch Control and Status 1 Register 0x18 Bit Description Default LPC Access I2C Access Interrupt Output Ext 0 Interrupt asserted 1 Interrupt de asserted 7 Fatal Error Detection Ext RO 0 Fatal error detected 1 No fatal error detected 7 1 21 PCIE Switch Control and Status 2 Register 0x19 Table 7 21 PCIE Switch Control and Status 2 Register 0x19 1 Non transparent Mode Enable 0 NT mode enabled 1 NT mode disabled Non transparent PCI PCI Bridge Enable 1 0 NT PCI PCI bridge enabled 1 NT PCI PCI bridge disabled System SMBus Interface Enable 0 0 Interface enabled 1 Interface disabled 0 SSC crossing enabled 1 SSC crossing disabled Link Upconfigure Timer Enable 1 0 Timer enabled 1 Timer disabled Em iVPX7225 Installation and Use 6806800511 127 FPGA Registers Table 7 21 PCIE Switch Control and Status 2 Register 0x19 continued Bit Description Default LPC Access I2C Access 0 PLX bridge NT reset is asserted 1 PLX bridge NT reset is de asserted FPGA SMI Interrupt Request 1 R w 0 Interrupt is requested 1 Interrupt is not requested 1 KHz Clock Source Select 1 R W 1 2KHz selected to create 1Khz clock 7 1 22 CPU Package Temperature Reading Register 0x1C Table 7 22 CPU Package Temperature Reading Register Ox1C
21. Super IO Logical Device Number Register 134 Super IO Device Identification Register 134 Super IO Device Revision Register 134 Super IO LPC Control 135 Global Super IO SERIRQ and Pre divide Control Register 135 Logical Device Configuration Register Summary 136 Logical Device Enable Register 136 Logical Device Common Decode Ranges 137 Logical Device Base IO Address MSB Register 137 Logical Device Base IO Address LSB Register 137 Logical Device Primary Interrupt Register 138 UART Register Overview 139 Receiver Buffer Register RBR if DLAB 0 140 Transmitter Holding Register THR if DLAB 0 140 Interrupt Enable Register IER if DLAB O 141 UART Interrupt Priorities2 2 142 Interrupt Identification Register 142 Interrupt Identification Register Decode
22. 126 7 1 21 PCIE Switch Control and Status 2 Register 0x19 127 7 1 22 CPU Package Temperature Reading Register 0x1C 128 7 1 23 IPMC Inlet Temperature Sensor Status Register 0x1D 128 7 1 24 IPMC Outlet Temperature Sensor Status Register 129 7 1 25 FRAM Page Access Register 0X20 0 0 ccc cece cece een 129 7 1 26 VPX System Register 0x24 130 iVPX7225 Installation and Use 6806800511 Contents 7 1 27 POST Code Latch Register 0x28 131 7 1 28 BIOS Boot Status Register 0 2 131 7 2 Leo 131 7 2 1 Super IO Configuration Registers 132 7 2 1 1 Entering the Configuration State 132 7 2 1 2 Exiting the Configuration State 132 7 2 1 3 Configuration Mode ulus a ss rex tenete bere re ee hasa 133 7 2 1 4 SuperlO Configuration Registers 133 7 2 1 5 Global Control Configuration Registers 133 7 2 1 6 Logical Device Configuration Registers 136 7 3 VARTRegister Overview el ee ee 139 7 3 1 UART Registers 0
23. 4 nRS 70 5 5 IPCleiMitlaliZation REC 70 5 6 l ODevice Configuration 2 71 5 7 BOOP OPHONS sara ERR a I Deere 71 5 8 Rediraction erecti ree meer fel E 72 5 9 BIOS Setup Layout a a 72 5 9 1 MQ oce ne nk 73 3 9 2 BootFedtures ccs ar ee edd a 74 5 9 3 Advanced Menu scere reb E ln 76 5 9 4 Processor Configuration 78 5 9 5 Processor Power 80 596 HDD Configuration erste Remensi en qapaq 82 5 9 7 Memory Configuration 84 5 9 8 System Agent SA Configuration 85 5 9 9 Graphics Configuration 86 5 9 10 IGD ConfiqBration ann beredt aa ER ERA CUR Ree s 87 5 9 11 PEG Port Configuration u ee en 88 5 9 12 South Bridge Configuration 89 59 13 SB SB ConfIg ratiOn ees reme eee en deese bp aaa 90 5 9 14 SB Security Configuration 90 5 9 15 Network Configuration
24. 5 Table 3 6 Table 3 7 and Table 3 8 in Controls LEDs and Connectors Updated Table 2 2 on page 34 Updated Figure 4 1 on page 61 iVPX7225 Installation and Use 6806800511B 21 About this Manual 22 iVPX7225 Installation and Use 6806800S11B Introduction Chapter 1 1 1 Features The 30 iVPX7225 features the dual core 3rd generation 2 5 GHz Intel Core I7 3555LE Mobile Processor with integrated graphics and memory controller and the mobile Intel QM77 PCH chipset with leading edge I O functionality This high compute density platform offers both high speed fabric connectivity with PCI Express and Gigabit Ethernet control plane connectivity with data transfer rates up to 5Gbps On board memory includes 8GB DDR3L 1600 memory 4GB embedded USB flash and 1MB non volatile Ferroelectric Random Access Memory FRAM Additional connectivity includes three USB 2 0 ports two serial ports three SATA ports eight GPIO Display Port VGA and one XMC site for maximum flexibility Table 1 1 Key Features of the iVPX7225 Features Processor Chipset iVPX7225 Installation and Use 6806800511 Description Dual core 3rd generation Intel Core i7 3555LE 2 50 GHz 4MB Intel Smart Cache 25 W TDP Dual Channel DDR3 3L 1333 1600 memory controller One x16 Gen2 PEG port Bifurcated to support x8 capable Site and VPX PCIe data plane Intel QM77 PCH Eight PCI Express root controllers and 8 lanes Gen
25. Enabled Fast Break Interrupt Enable Enabled Thernal Interrupt delivery node Disabled Intel R Virtualization Technology Enabled Intel R Streaner Prefetcher Enabled 78 iVPX7225 Installation and Use 6806800511 COM1 115200baud Tera Term VT Elle Edit Setup Control Window Help Processor Conf igurat ion Iten Specific Help Dynanic FSB Suitching Enabled Processor Pouer Enabled XD Enabled Hanagenent Intel R DCR Disabled 2 Configuration Linit Cpuid Haxinun value Disabledl Enable for BIST Disabled Hachine Check Enabled Fast Strings Enabled Fast Break Snoop Enable Enabled Fast Break Interrupt Enable Enabled Thernal Interrupt delivery node Disabled Intel R Virtualization Technology Enabled Intel R Streaner Prefetcher Enabled Intel R Spatial Prefetcher Enabled HAIC State Support Enabled e Thenumber of processor cores and Intel Hyper Threading Technology can be limited to reduce thermal issue e Intel Virtualization Technology allows hardware support of Virtualization software such as virtual machine iVPX7225 Installation and Use 68068005118 79 BIOS 5 9 5 Processor Power Management Figure 5 5 Processor Power Management COM1 115200baud Tera Term VT File Edit Setup Control Window Help Processor Power Hanagenent Iten Specific Help Enab led Enable processor Boot Perfornance Hode Perfornancel perfornance states Turbo Hode nable P Statesl Turbo
26. LPC Access 2 Access Watchdog Re trigger Writing data OxAD re triggers watchdog 7 1 10 Memory Write Protect Register 0x0B Table 7 10 Memory Write Protect Register 0 0 Bit Description Default LPCAccess I2C Access Ethernet Controller SPI ROM R W RO 0 Device write is allowed unless protected by NVMRO 1 Device is write protected unless protection is overridden by RTM switch 116 iVPX7225 Installation and Use 68068005S11B FPGA Registers Table 7 10 Memory Write Protect Register OXOB continued Bit Description Default LPC Access I2C Access 1 FRAM R W RO 0 Device write is allowed unless protected by NVMRO 1 Device is write protected unless protection is overridden by RTM switch 2 IPMC User ROM R W RO 0 Device write is allowed unless protected by NVMRO 1 Device is write protected unless protection is overridden by RTM switch 3 NAND Flash Controller R W RO 0 Device write is allowed unless protected by 7 NVMRO 1 Device is write protected unless protection is overridden by RTM switch PCIE Switch SPI ROM R W RO 0 Device write is allowed unless protected by NVMRO 1 Device is write protected unless protection is overridden by RTM switch VPD ROM R W RO 0 Device write is allowed unless protected by NVMRO 1 Device is write protected unless protection is overridden by RTM switch 0 Device write is allo
27. MU 7 2 1 4 7 2 1 5 Configuration Mode The system sets the logical device information and activates desired logical devices trough the INDEX and DATA ports The desired configuration registers are accessed in two steps 1 Writethe index of the Logical Device Number Configuration Register i e 07 to the INDEX PORT and then write the number of the desired logical device to the DATA PORT 2 Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT If accessing the Global Configuration Registers Step 1 is not required The Super IO returns to the RUN State Only two states are defined Run and Configuration In the Run State the Super IO is always ready to enter the Configuration State Super IO Configuration Registers Address locations that are not listed are considered reserved register locations Reads to reserved registers may return non zero values Writes to reserved locations may cause system failure Global Control Configuration Registers The Super IO Global Registers lie in the address range 0x00 0x2F All eight bits of the ADDRESS Port are used for register selection All unimplemented registers and bits ignore writes and return zero when read The INDEX PORT is used to select a configuration register in the chip The DATA PORT is then used to access the selected register These registers are acces
28. ODT Stretch Error OxE4 Crosser Error iVPX7225 Installation and Use 68068005118 Maps and Registers 6 1 Flash Map The following table shows the mapping of the entire 8MB flash device and shows the various images that are stored in a specific address location Table 6 1 Flash Map med tengo es 0x00000000 0x00000FFF 0x00001000 Descriptor Region 0x00001000 0x00002FFF 0x00000000 GbE Region 0x00003000 0x004FFFFF 0x004FD000 ME Region 0x00500000 0x007FFFFF 0x00300000 BIOS Region 6 2 BIOS Memory Map The following table shows the BIOS Memory Map details Table 6 2 BIOS Memory Map Device Start End Length 53 Script 0x0009C000 0x0009FFFF 0x4000 Video ROM 0x000C0000 0x10000 SMBIOS Table 0x000E0000 0x000FFFFF 0x20000 Onboard IGD GTT 0x20000000 0x201FFFFF 0x200000 Onboard IGD I O 0x40004000 0x40004FFF 0x1000 PCI Address Space 0xC0000000 Starting at PCI MMIO 0 8000000 OxFBFFFFFF 0x4000000 FRAM Page OxFE800000 OxFESOFFFF 0x10000 I O APIC 0 00000 OxFECOOFFF 0x1000 EHCI HC OxFED08000 OxFEDOSFFF 0x1000 MCH OxFED10000 OxFED 1 9FFF 0 000 OxFED1C000 OxFEDIFFFF 0x4000 iVPX7225 Installation and Use 68068005118 109 Maps and Registers 110 Table 6 2 BIOS Memory Map continued Device Start Length End TP OxFED45000 OxFEDSFFFF 0x4B000 Local APIC OxFEE00000 OxFEEOOFFF 0x1000 BIOS Flash Device OxFF
29. R W DDSR indicates that the DSR input has changed state since the last time it was read by the CPU When DDSR is set and the modem status interrupt is enabled a modem status interrupt is generated 1 Change in state of DSR input since last read 0 No change in state of DSR input since last read Trailing edge of the ring indicator TERI R W detector TERI indicates that the RIZ input to the chip has changed from a low to a high level When TERI is set and the modem status interrupt is enabled a modem status interrupt is generated Not supported iVPX7225 Installation and Use 6806800511 153 FPGA Registers Table 7 54 Modem Status Register MSR continued IO Address Base 6 Bit Description Default Access Change in data carrier detect DDCD R W indicator DDCD indicates that the DCD input to the chip has changed state since the last time it was read by the CPU When DDCD is set and the modem status interrupt is enabled a modem status interrupt is generated Not supported Complement of the clear to send CTS R input When the Asynchronous Communications Element ACE is in diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 1 RTS Complement of the data set ready DSR R input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equaltothe MCR bit 0 DTR Complement of the ring indicator RIZ input R Wh
30. TX SATA TX GND GND 12 SPI MISO GND GND CPU TMS 3 SPIO CS L NC X8D OPT NC X8D OPT CPU TCK NC X8D OPT NC X8D OPT 4 SPI CS L GND GND CPU TRST L GND GND 5 SPI CLK 2 120 8 2 12D8N TDI P2XMC 12D 7P P2XMC 12D 7N 6 SPI HDR HOL GND DO L 17 SPI HDR HOL P2XMC 12D 10P P2XMC 12010 PCH_TMS P2XMC 12D P2XMC 12D9N DI_L N 8 SPI HDR PWR GND GND PCH_TCK GND GND 9 CORE PGOOD 2 12D 12P P2XMC 12D 12 VTT 2 12011 P2XMC 120 11 N N P I r 1 1 NOTICE Rows Fand of XJ16 are intended for use with a factory test These signals may conflict with certain XMC s Rear User IO signals A special iVPX7225 factory build option routes 8 additional Differential I O signals to P2 in lieu of Mini DP and SATA P2 Refer to the VITA 46 9 X8d Pattern 58 iVPX7225 Installation and Use 680680051 1B 3 6 Switches Controls LEDs and Connectors The following table details the available switches on the board Table 3 9 S1 Switch Settings ON OFF DEFAULT Use Saved BIOS Settings 1 51 1 LOAD BIOS Defaults 1 2 Select BIOS Flash 1 Ignored when 51 3 is OFF Stand alone Mode NoIPMI Select BIOS Flash 0 Ignored when S1 3 is OFF IPMCenabled Mode Reserved for Factory Use Reserved for Factory Use Figure3 5 Switch Location DIP Switch iVPX7225 Installation and Use 680680051 1
31. USB Port 1 Enable Disable Enabled USB Port 2 Enable Disable Enabled USB Port 8 Enable Disable Enabled HEI Pre Boot Driver Disabled xHCI Hode Disabled e Built in USB controllers and individual ports can be manually enabled or disabled Boot time can be improved by disabling unneeded USB controllers ports 5 9 14 SB Security Configuration 90 iVPX7225 Installation and Use 68068005118 BIOS Figure 5 14 SB Security Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help SB Security Conf ig Iten Specific Help PREISER Enable Disable the RTC Lock Enabled PCH GPIO Lockdoun BIUS Lock Disabled feature BIOS Region Protect Disabled SHH LOCK Enabled e be locked to BIOS default settings Users will not be able to modify GPIO configuration if GPIO Lockdown is enabled BIOS Lock and Region Protect prevents the user from upgrading the BIOS thus increases security If Lock is enabled it takes precedence over Region Protect since it locks the entire BIOS region Region Protect prevents the user from upgrading the BIOS but it will allow users to modify the BIOS Setup settings iVPX7225 Installation and Use 68068005118 91 BIOS 5 9 15 Network Configuration Figure 5 15 Network Configuration COM1 115200baud Tera Term VT Ele Edit Setup Control Window Help Hetuork Conf igurat ion Iten Specific Help This is used to LAN 2 OPROH Selecti
32. are fixed at 1000Mbit and cannot auto negotiate down to 10 100Mbit 4 2 SLT3 PAY 2F2U 14 2 3 Slot Profile gt Key Data Plane 2 Fat Pipes User Defined Control Plane 2 Ultra Thin Pipes iVPX7225 Installation and Use 6806800511 63 Functional Description 4 6 4 7 64 Figure4 3 SLT3 PAY TFTF2U 14 2 4 Slot Profile gt Key Data Plane 1 Fat Pipes Expansion Plane 8 Pairs User Defined Control Plane 2 Ultra Thin Pipes Key PCI Express iVPX7225 provides two x4 PCI E Gen 2 ports to the VPX backplane One of which can be configured as Non Transparent Bridge A PLX PEX8617 PCle Gen2 5 0 GT s switch is used to implement the VPX dual FAT Pipe CPU PEG Port 0 lanes 0 7 is the host port routed to the PEX From the factory PEX Port 3 is configured as a Non Transparent Bridge while PEX Port 1 is configured as a Transparent bridge The configuration is determined via EEPROM PEX Port 1 is routed as PCIE on P1 PEX Port 3 is routed as PCIE FP2 DP02 on P1 SATA iVPX7225 provides two SATA Gen 3 up to 6Gbit s ports and one SATA Gen 2 up to 3Gbit s port routed to the VPX backplane P1 connector and another SATA Gen 2 up to 3Gbit s port routed to the XMC RTM planar SATA connector 5 supports SATA Gen2 RTM Front panel e SATA connector supports SATA Gen2 and SATA Gen 3 The RTM planar SATA connector 4 is Gen3 capable iVPX7225 Installation and Use 6806
33. board and dispose properly v g Theboard is thoroughly inspected before shipment If any damage occurred during trans N portation or any items are missing please contact customer service immediately 2 3 Environmental and Power Requirements The following environmental and power requirements are applicable to the board 2 3 1 Environmental Requirements The environmental conditions must be tested and proven in the used system configuration These conditions refer to the surroundings of the board within the user environment vi Operating temperatures refer to the temperature of the air circulating around the board mt air cooled or the temperature of the card edge conduction cooled and not to the component temperature Toensurethatthe operating conditions are met adequate cooling is required within the shelf environment e Theenvironmental values given in the table below only apply to the board without any accessories If installing accessories their environmental requirements must also be taken into account 32 iVPX7225 Installation and Use 6806800511 Hardware Preparation and Installation NOTICE Product Damage e High humidity and condensation on the board surface causes short circuits Donot operate the board outside the specified environmental limits Make sure the board is completely dry and there is no moisture on any surface before applying power Table 2 1 Environmental Requirements Envir
34. device designed to meet the EN60950 1 requirements for Information Technology Equipment The use of the product in any other application may require safety evaluation specific to that application Only personnel trained by Emerson or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only factory authorized service personnel or other qualified service personnel is allowed to remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided Contact your local Emerson representative for service and repair to make sure that all safety features are maintained Emerson and our suppliers take significant steps to make sure that there are no bent pins on the backplane or connector damage to the boards prior to leaving the factory Bent pins caused by improper installation or by inserting boards with damaged connectors could void the Emerson warranty for the backplane or boards Use extreme caution when handling testing and adjusting this equipment and its components around dangerous
35. error 3 Framing Error FE indicator 0 R When FE is set it indicates that the received character did not have a valid set stop bit FE is cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO The ACE tries to resynchronize after a framing error To accomplish this it is assumed that the framing error is due to the next start bit The ACE samples this start bit twice and then accepts the input data 1 Framing error occurred 0 No framing error 150 iVPX7225 Installation and Use 6806800511 FPGA Registers Table 7 53 Line Status Register LSR continued IO Address Base 5 Bit Description Default Access 4 Break Interrupt BI indicator 0 R When Bl is set it indicates that the received data input was held low for longer than a full word transmission time A full word transmission time is defined as the total time to transmit the start data parity and stop bits Bl is cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO When a break occurs only one 0 character is loaded into the FIFO
36. is a third level L3 shared instruction data cache with up to 8 MB that is shared by all cores The BIOS enables the following processor features by default e Intel Hyper Threading HT Technology e Dynamic Front Side Bus FSB Switching Execute Disable XD Bit e Machine Check e Intel SpeedStep e Turbo Mode e CStates 5 3 Memory Initialization iVPX 7225 has a total of 8 GB of physical main memory where 3 GB is available the lower 4GB 32 bit address space for general use The upper 1GB of AGB address space is reserved for systems tables and PCI address space The BIOS sets the max TOLUD Top of Lower Usable DRAM to 3 GB by default iVPX7225 Installation and Use 680680051 1B 69 BIOS 5 3 1 5 3 2 5 3 3 5 3 4 5 4 5 5 Serial Presence Detect SPD iVPX7225 Serial Presence Detect SPD Option ROM Read Only Memory is integrated into the onboard Microchip MCP98243 Memory Module Temperature Sensors Though the iVPX7225 isa memory down configuration there are two such devices onboard to provide temperature data as well as the SPD function One device is connected to each memory channel Geographically both sensors are on the primary side of the PCB Memory Test The BIOS will execute a short memory test after the Read and Write Training ECC Support BIOS will always enable ECC support in the chipset DDR3 Refresh Rate BIOS support double data rate 3 synchronous DRAM with 1600 MHz me
37. microprocessor reads the LSR and there are no subsequent errors inthe FIFO If FIFO is not used bit always reads 0 1 HFO data error encountered 0 No FIFO error encountered 7 3 1 9 Modem Status Register MSR This 8 bit register provides the current state of the control lines from the modem or data set or a peripheral device emulating a modem to the processor In addition to this current state information four bits ofthe Modem Status register provide change information Bits 03 00 are set to a logic 1 when a control input from the Modem changes state They are reset to logic 0 when the processor reads the Modem Status register 152 iVPX7225 Installation and Use 6806800511 FPGA Registers When bits 0 1 2 or3 are setto logic 1 a Modem Status interrupt is generated if bit 3 of the Interrupt Enable Register is set Table 7 54 Modem Status Register MSR IO Address Base 6 Description Default Access Change in clear to send DCTS indicator R W DCTS indicates that the CTS input has changed state since the last time it was read by the CPU When DCTS is set autoflow control is not enabled and the modem status interrupt is enabled a modem status interrupt is generated When autoflow control is enabled DCTS is cleared no interrupt is generated 1 Change in state of CTS input since last read 0 No change in state of CTS input since last read Change in data set ready DDSR indicator
38. voltages that can cause injury or death iVPX7225 Installation and Use 6806800511 160 Safety Notes System Installation Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life Before touching the product make sure that your are working in an ESD safe environment or wear ESD wrist strap or ESD shoes Hold the product by its edges and do not touch any components or circuits Pin Damage Forcing the module into the system may damage connector pins Ifthe module hangs during insertion pull it out and insert it again Damage of the Product and Additional Devices and Modules Incorrect installation or removal of additional devices or modules damages the product or the additional devices or modules Before installing or removing additional devices or modules read the respective documentation and use appropriate tools Operation System Damage During the course of handling shipping and assembly pins mounting screws fans and other items can become loose or damaged Do not operate a damaged shelf this can cause damage to devices that interact with it System Overheating Cooling Vents Improper cooling can lead to blade and system damage and can void the manufacturer s warranty Always operate the blade in a configuration suitable for proper cooling Do not obstruct the ventilation of the system Keep any fresh air intakes of the syst
39. 005118 List of Tables Table 1 1 Key Features of the iVPX7225 23 Table 1 2 Standard Compliances 2 25 Table 1 3 Mechanical esta 26 Table 1 4 Available Board Variants 28 Table 1 5 Pee 30 NE 28 Table 2 1 Environmental Requirements 33 Table 2 2 Power Requirements ae 34 Table 3 1 Planar LEDS ce 49 Table 3 2 POST Code LEDs ll u ppp RE E be Ba 50 Table 3 3 Plate LEDS u usss AEE Duden DA aa 52 Table 3 4 PO Conriector PINOUT uento i ike a Rn 53 Table 3 5 Connector PINOUT uuv a 54 Table 3 6 P2 Connector PINOUT uuu s e Ote Paene 55 Table 3 7 X 15 G nnector PINOUT irse Ep Er a EY P Me des 56 Table 3 8 X 16 Corinector PINGUE 2 2 mr ee Rete a 57 Table 3 9 S Switch Settings s ae le ved 59 Table 6 1 gin 109 Table 6 2 BIOS Memory Map iiss ici kpbDER eR ee bassen 109 Table 7 1 Blade Revision Register 111 Table 7 2 FPGA Major Revision 1 lt 0 01 112 Table 7 3 FPGA Minor Revision 0 02 112
40. 0x17 Description Default LPC Access 2 Access Boot Flash Programming Enable 0 R W RO 0 Disable boot flash programming 1 Enable selected boot flash programming Note When enabled Current Flash Selection bit 1 indicates the current bank selection That means the bank that will be programmed When IPMI is disabled via on board DIP switch the boot FLASH bank selected in bit 6 or 7 of Boot Control and Status Register 1 0x16 is selected for programming Otherwise the current boot bank selected by IPMI is selected iVPX7225 Installation and Use 6806800511 125 FPGA Registers Table 7 19 Boot Control and Status 2 Register 0x17 continued Bit Description Default LPC Access 2 Access Current Flash Selection RO RO 0 Boot flash 0 is selected 1 Boot flash 1 is selected Note Current FLASH selected is indicated only when Boot Flash Programming Enable is set enabled Reserved 0 RO RO 7 1 20 PCIE Switch Control and Status 1 Register 0x18 Table 7 20 PCIE Switch Control and Status 1 Register 0x18 Description Default LPC Access I2C Access Upstream Port Select 00 Port 0 selected 01 Port 1 selected 10 Port 2 selected 11 Port 3 selected Non transparent Upstream Port Select 00 Port 0 selected 01 Port 1 selected 10 Port 2 selected 11 Port 3 selected Port Configuration Select 00 x4 x4 x4 x4 01 x8 x4 x4 10 x8 x4 x4 11
41. 0x90 0x91 0x92 0x93 SIO Silicon Platform 0x98 0x9C Platform OxAO On screen Splash OxBO Intel amp vPro MEBx TXT OxBA OxBF Winbond W25064 Flash OxB3 Access Intel amp IFFS Intel amp ICC 0 5 Internal Graphics 0xB6 Intel vPro Hotkey and Menu OxC1 0xC2 PCH Init 0xC9 PCH LPC USB OxCD I O Trap OxCE SATA Device ROM OxCF Dispatch OxFO OxFA Missing Architectural Protocol 106 iVPX7225 Installation and Use 6806800511 BIOS 5 11 Memory POST Codes Memory POST code progress can aid in debugging the problem ifthe BIOS boot process failed Below is a list of common areas where the Memory training process goes through Description Value s Training Progress Memory Mapping Training Ended Frequency Setting Write Training Ox2E 0x32 Read Training 0x31 0x32 Command Training 0x33 Memory Configuration 0x40 Configuration Error OxA5 Memory Mapping Error OxA8 Memory Receive Enable OxB1 Error DQS Read Error 0xB4 Write Error 0xB7 Write Flyby Error OxC1 Aggressive Training Error 0xC4 Read Aggressive Training 0xC7 Error iVPX7225 Installation and Use 6806800511 107 BIOS 108 Description Value s Write Aggressive Training OxCA Error Data Error Command Training Error Init I O Default Error ECC Error Memory Test Error
42. 2 PCIe max 5 0 GT s Utilization 1x4 port routed to GigE controller Six SATA Controllers Utilization 3 routed to the backplane one routed to the XMC Site 14 USB 2 0 host controllers Utilization 3 rear USB 1 embedded USB Flash Controller Three digital displays DP eDP HDMI DVI sDVO Utilization One 1 DP port DDPD routed to backplane One analog display CRT VGA SPI interface 2 CS LPC interface SMBus Programmable interrupt controller watchdog timer real time clock Gigabit Ethernet Controller 10 100 1000BASE T unused 23 Introduction Table 1 1 Key Features of the iVPX7225 Features Description Memory Soldered down 8GB dual channel DDR3L 1600 memory 4GB Channel with ECC User Flash NVRAM Mem 4GB embedded USB flash 1 MB FRAM NVRAM Boot Flash Memory Redundant UEFI BIOS in dual 8MB SPI flash devices Backplane I O Two 1000BASE BX KX Ethernet Ultra Thin Pipe control plane Two PCle x4 Gen2 Fat Pipe data plane Either PCle port may be configured to support Non Transparent bridging one NT port max One DisplayPort One VGA Three USB 2 0 Three SATA 2x Gen3 1x Gen2 Two RS 232 RS 422 RS 485 Eight PCH GPIO VITA 46 9 XMC IO Pattern X12d support SMBus IPMCI2C Selective Non Volatile Memory R W Overrides RTM control signals Front Panel I O Air cooled XMC Front I O Reset switch Status LEDs Conduction cooled Reset switch Status LEDs
43. 21 Table 7 22 Table 7 23 Table 7 24 Table 7 25 Table 7 26 Table 7 27 Table 7 28 Table 7 29 Table 7 30 Table 7 31 Table 7 32 Table 7 33 Table 7 34 Table 7 35 Table 7 36 Table 7 37 Table 7 38 Table 7 41 Table 7 39 Table 7 40 Table 7 42 Table 7 43 Table 7 44 Table 7 45 Table 7 46 Table 7 47 Table 7 48 Table 7 49 Table 7 50 Table 7 51 Table 7 52 Table 7 53 Table 7 54 10 Boot Control and Status 2 Register 0X17 125 PCIE Switch Control and Status 1 Register 0X18 126 PCIE Switch Control and Status 2 Register 0X19 127 CPU Package Temperature Reading Register 0x1C_ 128 IPMC Inlet Temperature Sensor Status Register Ox1D 128 IPMC Outlet Temperature Sensor Status Register 0x1E 129 FRAM Page Access 0 20 129 VPX System Register 0 24 130 POST Code Latch Register 0X28 131 BIOS Boot Status Register OX2C 131 Super IO Configuration Index Register 132 Super IO Configuration Data Register 132 Global Configuration Register Summary 133
44. 232 RS485 Mode Select 0 RS232 interface mode selected 1 65485422 interface mode selected UART Transceiver Enable 0 Transceiver disabled 1 Transceiver enabled 120 iVPX7225 Installation and Use 680680051 1B FPGA Registers Table 7 14 Misc 1 Control and Status Register 0x10 continued Description UART Transceiver Internal Loopback Enable 0 Loopback enabled 1 Loopback disabled Default LPC Access I2C Access VPX REFCLK Frequency Select 0 25 MHz 1 100MHz Reserved GDISCRETE1 Power Fail LED Blinking Sync Enable 0 Function disabled 1 Function enabled Reserved RO 7 1 15 Misc2 Control and Status Register 0x11 Table 7 15 Misc 2 Control and Status Register Ox11 Description Default LPC Access I2C Access USB Port Power Enable 0 Port power disabled 1 Port power enabled pomme I PCH USB Status 0 Over current indication 1 No Over current indication IPMC Watchdog NMI 0 NMI not due to IPMC watchdog reset 1 NMI due to IPMC watchdog reset iVPX7225 Installation and Use 6806800511 0 R W RO RO RO mec 121 FPGA Registers Table 7 15 Misc 2 Control and Status Register 0x1 1 continued Bit Description Default LPC Access I2C Access IPMC NMI R WITC RO 0 NMI not due to IPMC NMI 1 NMI due to IPMC NMI IPMC GP Signal Reserved for future User LED Enable 0 User power fa
45. 25 iVPX7225 Installation and Use 6806800511 37 Hardware Preparation and Installation 3 Install M2 0 screws as needed by XMC module 38 iVPX7225 Installation and Use 6806800511 Hardware Preparation and Installation 5 Re install XMC cover and screws iVPX7225 Installation and Use 6806800511 39 Hardware Preparation and Installation 2 4 3 40 Rear Transition Module The iVPX7225 RTM does not support hot swap you should remove power to the rear slot or system before installing the RTM module NOTICE Product Damage e Installing or removing the product while power is applied damages the product Power off the rack before installing or removing the product Product Damage e Only use injector handles for board insertion to avoid damage to the front panel and or PCB Deformation of the front panel can cause an electrical short or other board malfunction Board Malfunction Switches marked as reserved might carry production related functions and can cause the board to malfunction if their setting is changed Do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before board installation Installing the RTM 1 Turn off all equipment power and then disconnect the power cable from the power source Remove the chassis cover as instructed in the equipment user s manual
46. 25 Installation and Use 6806800511 67 Functional Description One GEN 2 SATA interface is also made available at the XMC Site XJ16 connector This interface is wired to PCH SATA Port 5 4 20 BootFirmware The boot firmware is capable of booting an image from the following Onboard NAND Flash USB attached hard flash drive SATA attached hard flash drive Ethernet network boot USB attached removable media such as CD DVD 4 21 Operating System iVPX7225 supports the following operating systems Fedora 17 Linux with 3 6 11 Kernel or later e WindRiver VxWorks 6 8 SMP or later iVPX7225 Installation and Use 6806800511 Chapter 5 5 1 Overview BIOS The iVPX7225 BIOS is the primary firmware that controls initialization and functional tests on all board components before hand over to the installed OS It is based on the Phoenix SecureCore Tiano Enhanced BIOS that follows the UEFI standard The BIOS is built upon the Chief River Platform Ivy Bridge Processor and Panther Point 2 M PCH and is supplemented with the Intel ME firmware 5 2 Processor Initialization The processor has two physical cores with two logical cores on each physical core totaling four visible cores Processor P2 will be selected as the BSP and all four cores will be activated during the DXE phase of BIOS Each core has a first level L1 32 KB instruction and 32 KB data cache and second level L2 256 KB shared instruction data cache There
47. 4 Table 7 26 VPX System Register 0x24 Bit Description Default LPC Access I2C Access MRST Mask 0 MRST input is not masked 1 MRST input is masked 0 NVMRO is cleared by backplane other boards to logic zero It will allow all programmable parts on the board to be read or written 1 NVMRO is set by backplane to logic one It will allow all programmable parts on the board to be read but may prohibit write depending upon override switch settings System Slot 0 Board is installed in system slot 1 Board is installed in non system slot Reserved MRST Masked Reset to Backplane 0 Masked reset is de asserted to the backplane 1 Masked reset is generated to the backplane SYS RST System Reset to Backplane 0 System reset is de asserted to the backplane 1 System reset is generated to the backplane 130 iVPX7225 Installation and Use 6806800511 FPGA Registers 7 1 27 POST Code Latch Register 0x28 Table 7 27 POST Code Latch Register 0x28 Bit Description Default LPC Access 2 Access 7 0 Latch and hold POST code data when 0x00 R WTC RO watchdog timer reset is asserted Register is cleared to all zero upon power on reset and when register is written with any data 7 1 28 BIOS Boot Status Register 0 2 Table 7 28 BIOS Boot Status Register 0x2C Writing pattern Ox5D indicates BIOS 0x00 R W booted successfully Register is c
48. 6806800511 123 FPGA Registers 7 1 18 Boot Control and Status 1 Register 0x16 Table 7 18 Boot Control and Status 1 Register 0x16 Bit Description Default LPC Access I2C Access 0 Actual Boot Flash the Board is 0 RO RO booted from 0 SPI Flash 0 1 SPI Flash 1 2 1 Last Boot Success Bits 0x0 RO RO 00 Initial value from cold reset 01 Last boot failed 10 Last boot successful 11 Don t care 4 3 Failover Count Bits 0x0 RO RO 00 Initial value from cold reset 01 First failover 10 Second fail over 11 Don t care Reserved 0 RO RO 6 Software Boot Flash 0 Select 0 R W RO 0 Software has not selected flash 0 for next boot 1 Software has selected flash 0 for next boot 7 Software Boot Flash 1 Select 0 R W RO 0 Software has not selected flash 1 for next boot 1 Software has selected flash 1 for next boot 124 iVPX7225 Installation and Use 680680051 1B FPGA Registers NOTICE When IPMI is disabled via on board DIP switch and Boot Flash Programming Enable bit 0 in Boot Control and Status Register 2 is enabled Software Boot Flash Select bits 6 and 7 can be used to select a FLASH bank for the purpose of programming the bank When IPMI is disabled via on board DIP switch reset of the board will force boot from the selected bank unless itis a power on reset 7 1 19 Boot Control and Status 2 Register 0x17 Table 7 19 Boot Control and Status 2 Register
49. 800511 Functional Description 4 8 4 9 4 10 4 10 1 4 10 2 USB iVPX7225 provides three USB 2 0 ports routed to the VPX backplane P1 connector via PCH USB ports 0 1 2 respectively These interfaces can be accessed via RTM The RTM on board mini USB connectors 2 and J3 and front panel USB connector J1 supports USB 2 0 Serial COM iVPX7225 provides two serial ports both configurable as RS232 422 485 to the VPX backplane The RTM front panel Micro Mini DB9 connector J7 provides access to COMO and planar header P701 provides access to COMI Video Two video interfaces one digital one analog are routed to the backplane The video interfaces can be accessed through the RTM The RTM planar mini DisplayPort connector 801 supports Display Port natively and can support DVI or HDMI through the use of active DP gt DVI or DP gt HDMI adapters The RTM front panel DE 15F connector provides VGA output Rear DisplayPort One DisplayPort digital display interface to the VPX backplane is provided VGA One VGA analog display interface to the VPX backplane is provided iVPX7225 Installation and Use 6806800511 65 Functional Description 4 11 4 12 4 13 4 14 4 15 GPIO iVPX7225 provides eight user defined GPIO pins routed from the PCH to the VPX backplane P2 connector SMBus The board supports a minimum of 2Kb VPD EEPROM attached to the PCH mastered SMBus Although available for VPD or g
50. B 59 Controls LEDs and Connectors 60 iVPX7225 Installation and Use 6806800511 Chapter 4 Functional Description 4 1 Block Diagram Figure4 1 iVPX7225 Block Diagram IPMC SM1 SM2 1 PCle X8 GEN2 X12 DIFFPAIR IVPX7225 DDR3 1600 PCle X8 GEN2 PCle X4 GEN2 DDR3 1600 PCle X4 GEN2 PCle X4 GEN2 1000BASE BX um TO PEX8617 4 4 SATA X N2 SATA X1 GEN3 TA X1 GEN VPX SATA X1 GEN2 SPI PLANE USB 2 0 P0 P1 USB 2 0 P2 USB 2 0 m oo GPIO X8 single ended VGA tO a DISPLAYPORT ooo UART COMO RS232 422 485 PARALLEL BUS UART COM 85232422485 SYS RTM Control iVPX7225 Installation and Use 680680051 1B 61 Functional Description 4 2 4 3 4 4 Processor iVPX7225 carries the Ivy Bridge MbI ECC BGA Dual Core LV 25W TDP processor The following list summarizes the features of the processor Dual core 3rd generation Intel Core i7 3555LE 2 50 GHz 4MB Intel Smart cache 25 W Dual DDR3 3L 1333 1600 memory controller 1600 in this application Gen3 PCI Express PCle PEG Port 2x8 Gen2 PCI E 5 0 GT s in this application x4 DMI interface to platform controller hub PCH Chipset iVPX7225 supports Intel QM77 PCH The following list summarizes the features ofthe chipset Eight PCI Express root controllers a
51. Board Malfunction e Switches marked as reserved might carry production related functions and can cause the board to malfunction if their setting is changed Do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before board installation iVPX7225 Installation and Use 6806800511 41 Hardware Preparation and Installation Removal To remove the board from the chassis reverse the procedure and press the red locking tabs air cooled to extract the board 42 iVPX7225 Installation and Use 6806800511 Hardware Preparation and Installation U 2 5 1 Installing Air Cooled iVPX7225 The following procedure details the steps in installing an Air Cooled iPVX7225 to the chassis 1 Insert IVPX7225 into chassis with handle point down Once handle teeth engage in chassis rails push handle upward to fully seat board to backplane Torque Panel screws iVPX7225 Installation and Use 680680051 1B 43 Hardware Preparation and Installation 2 5 2 Installing Conduction Cooled iVPX7225 Te following procedure details the steps in installing an Conduction Cooled iPVX7225 to the chassis 1 Remove handle screw 2 Install conduction cooled IVPX7225 into chassis pressing handle until flush with heat frame 44 iVPX7225 Installation and Use 6806800511 Hardware Preparation and Installation 3 Re
52. D00000 OxFFFFFFFF 0x300000 iVPX7225 Installation and Use 6806800511 FPGA Registers 7 1 FPGA Registers This section contains the description and details of the iVPX7225 FPGA local registers FPGA registers are mapped I O space 0x100 register offset for host access and at I2C address 0x71 for IPMC access v g Default values in the register descriptions below indicate the values after board power on N 7 7 1 1 Blade Revision Register 0x00 Table 7 1 Blade Revision Register Ox00 Bit Description Default LPC Access I2C Access Artwork Hardware Version 0x0 Rev 1 0 Ox1 Rev 1 1 0x2 Rev 1 2 0x3 Rev 1 3 Variant Type OxA Air cooled variant OxC Conduction cooled variant iVPX7225 Installation and Use 680680051 1B 111 FPGA Registers 7 1 2 Major Revision Register 0x01 Table 7 2 FPGA Major Revision Register 0 01 Bit Description Default LPC Access 2 Access 7 0 Major Version Register RO RO Incremented by one for each major release 7 1 3 FPGA Minor Revision Register 0x02 Table 7 3 FPGA Minor Revision Register 0x02 7 0 Minor Version Register Incremented by one for each minor release 7 1 4 FPGA Date Code Register 0x04 Table 7 4 FPGA Date Code Register 0x04 Bit Description Default LPC Access I2C Access He mene me mm 112 iVPX7225 Installation and Use 6806800511B FPGA Registers 7 1 5
53. Feet per Minute LPC Low Pin Count LV Low Version LVDS Low Voltage Differential Signaling MAC Medium Access Controller Mb Megabit s Mobile Processor MB Megabyte s Mbps Megabits per second ME Management Engine MHz Megahertz N A Not Applicable iVPX7225 Installation and Use 6806800511 17 About this Manual Abbreviation Description NAND Not AND NEBS Network Equipment Building System Non maskable Interrupt Non volatile Random Access Memory Original Equipment Manufacturer Operating System Printed Circuit Board Platform Controller Hub PCI Express Physical layer device e g for Ethernet Red Green Blue Restriction of Hazardous Substances Read only Memory ROM RS232 Recommended Standard 232C interface standard for serial communication RTC Real Time Clock Rx Receive line of a duplex serial communication interface SAS Serial Attached SCSI SATA Serial AT Attachment high speed serial interface standard for storage devices SDRAM Synchronous Dynamic Random Access Memory Serial Digital Video Out Serializer Deserializer Stock Keeping Unit A unique identifier for a distinct product variant that can be ordered System Management Interrupt SPD Serial Presence Detect 18 iVPX7225 Installation and Use 68068005118 About this Manual Abbreviation SPI TBD TDP TPM Description Serial Peripheral Interf
54. Gen X Auto Aluays Enable PEG Disabled PEG ASPH LOS And 111 ASPH LOs Disabled De enphasis Control 3 5 dB Gen3 Equalizat ion Enabled Gen3 Root Port Preset Gen3 Endpoint Preset 7 PEG Sanple Calibrate Ruto PEG Gen3 Equalizat ion Phase Disabled e Individual PEG port can be set to generation Il or II It is mainly for devices that have compatibility issues e PEGASPM and ASPM 105 can be set accordingly to PCle devices needs 88 iVPX7225 Installation and Use 6806800511 BIOS 5 9 12 South Bridge Configuration Figure 5 12 South Bridge Configuration COM1 115200baud Tera Term VT Hel File Edit Setup Control Window South Bridge Conf igurat ion Iten Specific Help Enable Disable SHBUS Port 80h Cycles Bus Device PCI Clock Run Logic Disabled HPET Support Enabled HPET Henoru Hap BRR FEDO00001 DeepSx Hode Disabled State After 63 State 50 Hat ive PCI Express Disabled gt SB PCI Express Conf ig SB USB Conf ig gt SB Serial IRQ Conf iq gt SB Security Conf ig iVPX7225 Installation and Use 6806800511 89 BIOS 5 9 13 SB USB Configuration Figure 5 13 SB USB Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help SB USB Conf igurat ion Iten Specific Help Enabled Control the USB EHCI EHCI2 Enabledl USB 2 0 functions USB Per Port Disable Control Enabled USB Port 0 Enable Disable Enabled
55. H supports a battery backed real time clock with 256 bytes of battery backed RAM The PCH maintains the time of the day and stores system data as long as the VBAT input remains above 2V at the iVPX7225 PCH RTC input In the event that the system does not provide a voltage at VBAT there is a diode protected 0 2F SuperCap C214 onboard the iVPX7225 RTM to maintain operation for short down times The steady state current draw from the iVPX7225 at VBAT is 6 uA In the event that VBAT is connected to 3 3V AUX atthe backplane the RTM SuperCap will discharge more quickly when 3 3V AUX is removed This is due to SYSRESET terminations present on the VPX backplane This could result in the loss of RTC and or system data stored in the iVPX7225 PCH battery backed RAM Refer to VITA 46 for additional information on the VBAT bussed signal 3 4 3 P2 Connector The following table provides the pinout of the P2 connector Table 3 6 P2 Connector Pinout Row G RowF Row Row D Row C GND B WPORL COMI RTS COM1 RTS TX PIGND COMO RX CTS COMO RX GND COMO RTS N COM1 RX CTSN COM1 RX CTS P GND Row COMO TX TXN GND ETHWPORL SW WP OR IPMC DEBUG IPMC DEBUG TXD RTM TX DIS GND 5 WP GND SATAPOTXN 5 GND SATAPORXN 5 ORL 6 GND SATAP1TXNSATAP1TXP GND SATA P1RXN SATAPIRXP GND iVPX7225 Installation and Use 6806800511 55 Controls LEDs and Connectors
56. Hode Pouer Linit Lock Enabled Long Poner Linit 0 Long Pouer Linit Tine 28 Short Pouer Linit 0 IR Current Linit 896 IGFA Current Linit 96 Energy Efficient Enable Enabled Configure TDP Boot Hode Doun Lock sett ing Disabled Custon Sett ing Disabled C States Enabled Extend C States Enabled 80 iVPX7225 Installation and Use 6806800511 BIOS COM1 115200baud Tera Term VT File Edit Setup Control Window Help Processor Conf igurat ion Iten Specific Help Dynanic FSB Suitching Enabled Processor Poner Enabled XD Enabled Hanagenent Intel R DCR Disabled Conf igurat ion Linit Cpuid Haxinun value Disabled Enable for BIST Disabled Hachine Check Enabled Fast Strings Enabled Fast Break Snoop Enable Enabled Fast Break Interrupt Enable Enabled Thernal Interrupt delivery node Disabled Intel R Virtualization Technology Enabled Intel R Streaner Prefetcher Enabled Intel R Spatial Prefetcher Enabled HAIC State Support Enabled e Intel SpeedStep allows the OS to adjust the processor speed based on its usage For example if the processor is idle then the processor speed is lowered to reduce power consumption and heat dissipation e Turbo Mode is an on demand processor performance that will allow the processor to run faster than the base operating speed e Cstates define what idle states the processor can be set during system power on Higher numbe
57. In order to minimize software overhead during data character transfers the UART prioritizes interrupts into four levels listed in the below table and records these in the Interrupt Identification Register The Interrupt Identification Register IIR stores information indicating that a prioritized interrupt is pending and the source of that interrupt Table 7 47 UART Interrupt Priorities2 Priority Level Interrupt Source 1 Highest Receiver Line Status One or more bits were set 2 Received Data is available In FIFO mode trigger level was reached in non FIFO mode RBR has data Receiver Time out occurred It happens in FIFO mode only when there is data in the receive FIFO but no activity for a time period Transmitter requests data In FIFO mode the transmit FIFO is half or more than half empty in non FIFO mode THR is read already Table 7 48 Interrupt Identification Register IIR IO Address Base 2 Bit Description Default Access Interrupt status bit R 1 no interrupt pending 0 interrupt pending Interrupt priority level and source R 11 Receiver line status 10 Receiver data available 01 Transmitter holding register empty 00 Modem status 3 Time Out Detected 0 R 0 No time out interrupt is pending 1 Character time out indication FIFO mode only iVPX7225 Installation and Use 68068005S11B Table 7 48 Interrupt Identification Register IIR FPGA Registers IO Addre
58. Odd parity Stick parity R W When bits 3 4 and 5 are set the parity bit is transmitted and checked as cleared When bits 3 and 5 are set and bit 4 is cleared the parity bit is transmitted and checked as set If bit 5 is cleared stick parity is disabled 1 Stick parity enabled 0 Stick parity disabled Break control bit R W Bit 6 is set to force a break condition i e condition where TXD is forced to the spacing cleared state When bit 6 is cleared the break condition is disabled and has no affect on the transmitter logic It only effects TXD 1 Break condition enabled 0 Break condition disabled 146 iVPX7225 Installation and Use 68068005118 7 3 1 7 Table 7 51 Line Control Register LCR continued FPGA Registers IO Address Base 3 Bit Description Divisor latch access bit DLAB Bit 7 must be set to access the divisor latches of the baud generator during a read or write Bit 7 must be cleared during a read or write to access the RBR THR or IER 1 Access to DLL and DLM registers 0 Access to RBR THR and IER registers Default Access R W Modem Control Register MCR This 8 bit register controls the interface with the modem or data set or a peripheral device emulating a modem Table 7 52 Modem Control Register MCR IO Address Base 4 Description Data terminal ready DTR output control 1 DTR output in low active s
59. Remove the filler panel s from the appropriate card slot s at the rear of the chassis if the chassis has a rear card cage Slide the top and bottom edge of the transition module into the rear guide rails of the chassis Ensure that the lever of the injector ejector is in the outward position iVPX7225 Installation and Use 680680051 1B Hardware Preparation and Installation 6 Slide the transition module into the chassis until resistance is felt 7 Movethe injector ejector lever in an inward direction 8 Verify that the transition module is properly seated and secure it to the chassis using the two screws located at the edges of the face plate 9 Connectthe appropriate cables to the transition module 2 5 Installing and Removing the Board This section describes the recommended procedure for installing the board in a chassis Make sure to read all warnings and instructions before installing the board The iVPX7225 does not support hot swap Remove power to the slot or system and make sure that the serial ports and switches are properly configured NOTICE Product Damage e Installing or removing the product while power is applied damages the product e Poweroffthe rack before installing or removing the product Product Damage e Only use injector handles for board insertion to avoid damage to the front panel and or PCB Deformation of the front panel can cause an electrical short or other board malfunction
60. Shift 1 enables or disables a device Del deletes an unprotected device 103 BIOS 5 9 25 Exit Menu Figure 5 25 Exit Menu COM1 115200baud Tera Term VT Eile Edit Setup Control Window Help Hain Advanced iP 47225 Secur itu oot Iten Specific Help Exit Discarding Changes Load Setup Defaults Equal to Fil save Load Opt inized Defaults all changes of all Discard Changes nenus then exit Save Changes setup conf igure driver Finally resets the systen autonat ically e Load Optimized Defaults will disable USB devices including USB keyboard Serial console will then need to be enabled to enter setup 104 iVPX7225 Installation and Use 6806800511 BIOS 5 10 BIOS POST Codes BIOS POST code progress can aid in debugging the problem if the BIOS boot process failed Below is a list of common areas where the BIOS boot process goes through Description Value s ACPI 0x20 0x23 AHCI 0x24 0x26 I O Thunk 0x27 Boot 0x28 Ox2E Console Splitter 0x31 Crisis Recovery 0x32 Disk I O 0x38 DXE 0x39 Embedded Controller Ox3B Error Log 0x3C Graphics Console 0x44 HDD Password 0x45 IDE 04B 0x4D IMPI 0x50 Keyboard Controller 0x52 0x54 Network Partition PCI Bus Runtime iVPX7225 Installation and Use 6806800511 105 BIOS Description Value s SCSI 0x68 0x6A USB Controller 0x82 0x84 CSM Ox8A 0x8F Flash Controller
61. T on DIHH Thernal Sensor Device Enable Enabled NOTE SODINHO is the PCH Tenp Read Enable Enabled z slot closer to CPU CPU Energy Read Enable Enabled CPU Tenp Read Enable Enabled CPU Tenp Read Enable Disabled TS On Dinn Enable Disabled Rlert Enable Lock Disabled HE SHBus Thernal Report ing Enabled HE SHBus Buffer Length 20 Thernal Reporting EC PEC Disabled I lo TS on The configuration can be modified to suit the board s thermal environment The passive trip point is set above the processor throttling temperature by default so that throttling is done by the hardware rather than OS iVPX7225 Installation and Use 6806800511 97 BIOS 5 9 20 Intel Rapid Start Technology Figure 5 20 Intel Rapid Start Technology COM1 115200baud Tera Term VT X1 Elle Edit Setup Control Window Help Intel R Rapid Start Technology Iten Specific Help Enable iRST e Enable Intel Rapid Start Technology to achieve a 6 seconds system resume from deep sleep SSD is needed to take full advantage of this feature 98 iVPX7225 Installation and Use 6806800511 BIOS 5 9 21 iVPX7225 Menu Figure 5 21 iVPX 7225 Menu COM1 115200baud Tera Term VT File Edit Setup Control Window Help Hain Advanced FPGA Version FPGA Build Date Blade Version Hrite Protect Status Reg Last Knoun Reset fict ive Boot Bank FPGA HISC 1 FPGA HISC 2 FPGA HISC 3 Hatchdog Regist
62. TA 46 11 System management for VPX draft Version 0 8 VITA 48 1 Mechanical Specification for Microcomputers Using REDI Air Cooling VITA 48 2 Mechanical Specifications for Microcomputers Using REDI Conduction Cooling Applied to VITA VPX VITA 65 0 OpenVPX System Specification Intel Intelligent Platform Management Interface Specification Version 1 5 PICMG Hardware Platform Management IPM Controller Firmware Upgrade Specification Rev 1 0 158 iVPX7225 Installation and Use 68068005118B Related Documentation iVPX7225 Installation and Use 68068005118 159 Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed during all phases of operation service and repair of this equipment You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment Emerson intends to provide all necessary information to install and handle the product in this manual Because of the complexity of this product and its various uses we do not guarantee that the given information is complete If you need additional information ask your Emerson representative This product is a Safety Extra Low Voltage SELV
63. Table 7 4 FPGA Date Code Register 0X04 112 Table 7 5 FPGA Month Code Register 0x05 113 Table 7 6 FPGA Year Code Register 0x06 113 Table 7 7 FPGA Reset Cause Register 0X08 113 Table 7 8 Watchdog Control Register 0x09 115 Table 7 9 Watchdog Re trigger Register Ox0A 116 Table 7 10 Memory Write Protect Register 0x0B 116 Table 7 11 Power Good Status 1 Register 0x0C _ 118 Table 7 12 Power Good Status 2 Register 0x0D 119 Table 7 13 System Status Register 0 0 119 Table 7 14 Misc 1 Control and Status Register 0x10 120 Table 7 15 Misc 2 Control and Status Register 0X11 121 Table 7 16 DIP Switch Status Register 0x14 122 Table 7 17 Misc 3 Control and Status Register 0x15 123 Table 7 18 Boot Control and Status 1 Register 0x16 124 iVPX7225 Installation and Use 6806800511 9 List of Tables Table 7 19 Table 7 20 Table 7
64. The next character transfer is enabled after RXD goes to the marking state for at least two Receiver CLK samples and then receives the next valid start bit 1 Full WORD transmission time exceeded 0 Normal operation 5 Transmit Holding Register Empty THRE 1 R indicator THRE is set when the THR is empty indicating that the ACE is ready to accept a new character If the THRE interrupt is enabled when THRE is set an interrupt is generated THRE is set when the contents of the THR are transferred to the TSR THRE is cleared concurrent with the loading of the THR by the CPU In the FIFO mode THRE is set when the transmit FIFO is empty it is cleared when at least one byte is written to the transmit FIFO 1 THR Transmit FIFO empty 0 THR Transmit FIFO contains data iVPX7225 Installation and Use 6806800511 151 FPGA Registers Table 7 53 Line Status Register LSR continued IO Address Base 5 Bit Description Default Access Transmitter Empty TEMT indicator TEMT bit is set when the THR and the TSR are both empty When either the THR or the TSR contains a data character TEMT is cleared In the FIFO mode TEMT is set when the transmitter FIFO and shift register are both empty 1 THR Transmit FIFO TSR empty 0 THR Transmit FIFO TSR contains data FIFO data error In the FIFO mode LSR7 is set when there is at least one parity framing or break error in the FIFO It is cleared when the
65. V WA ERG MR ER es ale on 65 4 10 Video vs va EH e A AD RR dts 65 4 10 1 Rear DisplayPort 65 2 10 2 VGA cate Dee E oce Eod de o RE bb d oae ebbe 65 A AMNECION PECES 66 4 12 ONIBUS MCCC 66 4 13 BOOEFIaSD e eee e es 66 4 14 NAND Flash Bee a ak 66 4 15 FRAN rte e mn Bean RR e eT ce Rca EA 66 4 16 Trusted Platform Module 67 4 17 Real Time Clock n eee E PRESE en UE np nd 67 4 18 Watchdog Timer DUREE 67 4 19 XMESUpportk ea ea en 67 4 20 Boot FIFIDWiaEe usa saksa seede eh ua Ue ak 68 4 2 Op ratirigiSysStem udo ess RET ead E apr 68 IDEEN D Su nid EA UOS du 69 Sl OI m 69 5 2 Processor Initialization 69 5 3 Memory Initialization ek a eR hendene 69 iVPX7225 Installation and Use 68068005118 Contents 5 3 1 Serial Presence Detect SPD 70 5 3 2 Memory Test 2 SUE RR US 70 5 3 3 ECCSUDDOTE dee aa ea eu HC HU OC P EV 70 5 3 4 DDR3 Refresh 70 5
66. a Term VT File Edit Setup Control Window Help Boot Features Iten Specific Help Um Selects Pouer on Quick Boot Disabled state for HunLock Diagnostic Splash Screen Disabled Diagnostic Sunnary Screen Disabled BIOS Level USB Enabledl USB Legacu Enabled Console Redirect ion Enabled Terninal Tupe Baudrate Flou Control Continue C R after POST Rllou Hotkey in 4 resune Disabled UEFI Boot Enabled Legacy Boot Enabled Boot in Legacy Video Hode Disabled e Quick Boot will disable splash logo during the BIOS start up in order to improve boot time e Console redirection applies to all COM ports when enabled e Continuous Boot Retry allows the board to keep attempting to boot all bootable devices with system reset until an OS is loaded If Internal Shell is enabled in the boot menu then Internal Shell will always be loaded iVPX7225 Installation and Use 6806800511 75 BIOS 5 9 3 Advanced Menu Figure 5 3 Advanced Menu COM1 115200baud Tera Term VT File Edit Setup Control Window Help 7225 Security Boot Exit Iten Specific Help gt Silicon Infornat ion gt ACPI Conf igurat ion Select Language gt Processor Conf iqurat ion gt Peripheral Conf igurat ion HDD Conf igurat ion gt Henory Conf igurat ion gt Systen Agent SR Conf igurat ion gt South Bridge Conf igurat ion Hetuork Conf igurat ion gt 0 1 Conf iqurat ion SHBIOS Event Log
67. ace To be defined Thermal Design Power Trusted Platform Module Tx Transmit line of a duplex serial communication interface UART Universal Asynchronous Receiver Transmitter USB VID VPD VT XCVR XDP Universal Serial Bus Voltage Identification for Intel CPUs Vendor Product Data Intel amp Virtualization Technology A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions VT provides a foundation for widely deployed virtualization solutions and enables more robust hardware assisted virtualization solution Transceiver Run control Debug Port XMC Switched Mezzanine Card Conventions The following table describes the conventions used throughout this manual Notation 0x00000000 Description 0 through F for example used for addresses and offsets 0b0000 bold Screen Same for binary numbers digits are 0 and 1 Used to emphasize a word or commands in body text Courier Bold Used to characterize user input and to separate it from system output iVPX7225 Installation and Use 6806800511 Typical notation for hexadecimal numbers digits are Usedforon screen output and code related elements About this Manual Notation Description Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables
68. and keys text Notation for software buttons to click on the screen and parameter description Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided A could result in death or serious injury XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Indicates a hazardous situation which if not avoided may result in minor or moderate injury XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Indicates a property damage message XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX i AS l 3OOO00000000000000000 00000000000000000 000000000000t No danger encountered Pay attention to important i XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX information 20 iVPX7225 Installation and Use 6806800511 About this Manual Summary of Changes This manual has been revised and replaces all prior editions 6806800511 November 2013 Updated Table 3 4 Table 3
69. anual You can obtain electronic copies of Emerson Network Power Embedded Computing publications by contacting your local Emerson sales office For released products you can also visit our Web site forthe latest copies of our product documentation 1 Visit http www emersonnetworkpower com embeddedcomputing 2 Under Resources click Technical Documentation 3 Enterthe manual you are looking for in the search engine Use either the publication number or the complete name of the product to search for available manuals Table A 1 Emerson Network Power Embedded Computing Publications Document Title Publication Number iVPX7225 Control IPMI Programmer s Reference 6806800508 iVPX7225 Quick Start Guide 6806800514 iVPX7225 Safety Notes 6806800515 iVPX7225 Quick Start Guide 6806800536 iVPX7225 RTM Installation and Use 6806800535 iVPX7225 RTM Safety Notes 6806800537 iVPX7225 Installation and Use 68068005118 157 Related Documentation A 2 Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 2 Specifications Organization Document VITA 46 0 VPX Base Standard VITA 46 9 PMC XMC Rear I O Fabric Signal Mapping 3U 6U VPX Modules Standard VI
70. ard that is being developed as the successor to DDR2 SDRAM DMI Direct Media Interface Extension of the standard PCI Express specification with special commands features added to mimic the legacy Hub Interface DC coupled LN DisplayPort DRAM Dynamic Random Access Memory DVI Digital Visual Interface ECC Error Correction Code EEPROM Electrically Erasable Programmable Read Only Memory Electro magnetic Compatibility EMI Electro magnetic Interference Emerson s ENP2 Ruggedization Level Emerson s ENP4 Ruggedization Level Electro static Discharge Field Programmable Gate Array FSB Front side Bus FWH Firmware Hub Gb Gigabit s GB Gigabyte s GbE Gigabit Ethernet Gigabits per second Gigabits per second Gen1 PCI Express Generation 1 supporting 2 5 GT s Gen2 PCI Express Generation 2 supporting 5 0 GT s 16 iVPX7225 Installation and Use 6806800511 About this Manual Abbreviation Description GHz Gigahertz GPIO General Purpose Input Output GT s Gigatransfers per second HD High Definition HDMI High Definition Multimedia Interface I O Input Output 2 Inter Integrated Circuit Bus 2 wire serial bus and protocol ICT In circuit Test IF Interface IPMC Intelligent Plattorm Management Controller KB Kilobyte s Kb Kilobits s L2 Cache Level 2 Cache L3 Cache Level 3 Cache LAN Local Area Network LED Light emitting Diode LFM Linear
71. ault configuration of COMO is 0x3F8 IRQ4 Default configuration of COM1 is Ox2F8 IRQ3 Each COM port defaults to RS 232 with a date rate of 115200 8 n 1 Boot Options The BIOS can boot to any of the following devices and as specified in the boot ordering e USB Devices onboard or external e Hard Disk Solid State Device SSD e Network PXE Boot e internal EFI Shell iVPX7225 Installation and Use 6806800511 71 BIOS 5 8 Redirection Console redirection is enabled by default This makes it possible to configure the BIOS Setup Menus via the console even if there is no VGA display present The default setting of the serial console is set to Serial Protocol RS 232 Terminal Type ANSI BAUD rate 115200 bps 5 9 BIOS Setup Layout This section displays several useful features of the BIOS Setup menu and its various sub menus The features that can be selected are also displayed 72 iVPX7225 Installation and Use 680680051 1B BIOS TT pm 5 9 1 Main Menu This section displays several useful features of the BIOS Setup menu and its various sub menus Figure 5 1 Menu W COM1 115200baud Tera Term VT The features that can be selected are also displayed iVPX7225 Installation and Use 6806800511 73 BIOS 5 9 2 Boot Features Figure 5 2 Boot Features 74 iVPX7225 Installation and Use 6806800511 BIOS COM1 115200baud Ter
72. bled 1 enabled Logical devices participate in interrupt generations SERIRQ Mode LPC R 1 Continuous Mode UART Clock pre divide LPC R W 00 divide by 1 01 divide by 8 10 divide by 26 CLK is 48 MHz 11 Reserved Note the UART clock is fixed at 48MHz The default value should not be changed Reserved LPC R iVPX7225 Installation and Use 6806800511 135 FPGA Registers 7 2 1 6 Logical Device Configuration Registers Use to access the registers that are assigned to each logical device The Super IO supports three logical units and has three sets of logical device registers The two logical devices are UART 1 Logical Number 4 UART 2 Logical Number 5 and UART 3 Logical Number 6 A separate set bank of control and configuration registers exists for each logical device and is selected with the Logical Device Number Register The INDEX PORT is used to select a specific logical device register These registers are then accessed through the DATA PORT The Logical Device registers are accessible only when the SIO is in the Configuration state Table 7 37 Logical Device Configuration Register Summary Index Address Description 0x30 Enable 0x60 Base IO Address MSB 0x61 Base IO Address LSB 0x70 Primary Interrupt Select 0x74 Reserved 0x75 Reserved OxFO Reserved The logical register addresses are shown in the tables below Table 7 38 Logical Device Enable Register
73. ce combination can be set to AHCI IDE or RAID to fit the user s needs SATA Device Type can be set to HDD or SSD to set specific hard drive performance 83 BIOS 5 9 7 Memory Configuration Figure 5 7 Memory Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help Henory Conf igurat ion Iten Specific Help uto Haxinun Henory TOLUD Frequency Select ions Support in Mhz Henory Scranbler HRC FastBoot Force ColdReset Exit Hode Fast Exit Pouer Hode Auto Scranbler Seed Generation Off Disabled Henory Renap Enabled Channel DIHH Control Enable both DIH Channel B DIHH Control Enable both DIH MRC FastBoot allows the BIOS to skip certain memory testing during POST 84 iVPX7225 Installation and Use 6806800511 BIOS 5 9 8 System Agent SA Configuration Figure 5 8 System Agent SA Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help Systen Agent SR Conf igurat ion Iten Specific Help Displays and provides gt Intel R YT for Directed 1 0 YT d option to change the gt Braphics Conf igurat ion DHI Settings gt PEG Port Conf igurat ion Debug Alig Disabled n Above 46 HHIO BIOS assignment Disabled iVPX7225 Installation and Use 6806800511 85 BIOS 5 9 9 Graphics Configuration Figure5 9 Graphics Configuration COM1 115200baud Tera Term VT File Edit Setup Cont
74. chen und die Herstellergarantie ung ltig werden lassen Arbeiten mit dem Baord sollten immer in einer eigens gekuehlten und konfigurierten Umgebung erfolgen Behindern Sie nicht die Bel ftung des Systems Achten Sie darauf dass alle Luftzugaenge des Systems komplett frei sind Stellen Sie sicher dass die zufuehrende Luft nicht mit heissen Gasen von andered Geraeten vermischt wird Stellen Sie ausserdem sicher das alle Steckplaetze im System entweder mit Boards Filler blades oder Dummy Boards belegt sind Besch digung des Systems Hohe Luftfeuchtigkeit und Kondensat auf den Oberfl chen der Produkte kann zu Kurzschl ssen f hren Betreiben Sie die Produkte nur innerhalb der angegebenen Grenzwerte f r die relative Luftfeuchtigkeit und Temperatur und stellen Sie vor dem Einschalten des Stroms sicher dass sich auf den Produkten kein Kondensat befindet Erweiterung und FRU Austausch Besch digung des Produktes Verbogene Stecker oder lose Teile k nnen das Produkt die Backplane oder andere Systemkomponenten besch digen Pr fen Sie das Produkt und die Backplane vor dem Einabau sorgf ltig auf verbogene Stecker und lose Teile Verletzungsgefahr W hrend des Betriebs k nnen Oberfl chen an den K hlk rpern oder anderen Komponenten sehr hei werden Um Verletzungen durch Verbrennung zu vermeiden ber hren Sie w hrend der Arbeit keine Komponenten oder K hlk rper auf dem Produkt Fassen Sie das Produkt an den Handles und der Fron
75. counter is immediately loaded This prevents long counts on initial load Access to the Divisor latch can be done with a word write The UART CLK is the CLK UART 48 2 input divided by the pre divider set by the Super IO Configuration Register Offset 0x29 The baud rate of the data shifted in out of the UART is given by Baud Rate UART CLK 16X Divisor For example if the pre divider is 26 the UART CLK is 1 8461538 When the divisor is 12 the baud rate is 9600 A Divisor value of 0 in the Divisor Latch Register is not allowed iVPX7225 Installation and Use 6806800511 155 FPGA Registers Table 7 56 Divisor Latch LSB Register DLL if DLAB 1 IO Address Base Division Latch LSB DLL Cold Reset 0 R W Table 7 57 Divisor Latch MSB Register DLM if DLAB 1 IO Address Base 1 Description Default Access Divisor Latch MSB DLM Cold Reset 0 Table 7 58 Logical Device 0x74 Reserved Register Index Address Base 0x74 Reserved 0x04 LPC R Table 7 59 Logical Device 0x75 Reserved Register Index Address Base 0x75 Access Description Default Table 7 60 Logical Device Reserved Register Index Address OxFO Reserved LPC R 156 iVPX7225 Installation and Use 6806800511 Related Documentation OM A 1 Emerson Network Power Embedded Computing Documents The publications listed below are referenced in this m
76. d to override this behavior so that IPMC disables the local control behavior as described above Refer iVPX7225 Control via IPMI Programmer s Reference manual for detailed information about OEM commands The following connectors are available in the front panel e Aircooled XMCFront I O Reset switch Status LEDs e Conduction cooled Reset switch Status LEDs 52 iVPX7225 Installation and Use 68068005118 Controls LEDs and Connectors 3 4 Backplane Connectors The board provides the PO P1 and P2 backplane connectors 3 4 1 PO Connector The following table provides the pinout of the PO connector Table 3 4 PO Connector Pinout 5V VPX PWRISV VPX PWR GAP L GA L 3 i B GA L 0 JTAG_ TCK MC_RST_L DNP REF CLK NIREF P GND 25Mhz 25Mhz iVPX7225 Installation and Use 6806800511 53 Controls LEDs and Connectors 3 4 2 54 P1 Connector The following table provides the pinout of the P1 connector Table 3 5 P1 Connector Pinout Row G GDISCRET E1 GND Row F GND PCIE FP1 LANE 1 TXN GND Row PCIE FP1 LANE 0 TX N PCIE FP1 LANE 1 TXP PCIE FP1 LANE 2 TXN Row D PCIE FP1 LANE 0 TX P GND PCIE FP1 LANE 2 TX P Row C GND PCIE FP1 LANE 1 GND Row B PCIE FP1 LANE 0 RX N PCIE FP1 LANE 1 RX P PCIE FP1 LANE 2 RX N Row PCIE FP1 LANE 0 RX P GND PCIE FP1 LANE 2 RX P
77. e 712 inches 28 iVPX7225 Installation and Use 6806800511 Introduction 1 5 Product Identification The following graphic shows the location of the serial number label of the iVPX7225 main board Figure 1 3 _ Serial Number Label Location TETEN PRE Or TOES iVPX7225 Installation and Use 680680051 1B 29 Introduction Ui i l 30 iVPX7225 Installation and Use 6806800511 Chapter 2 Hardware Preparation and Installation 2 1 2 2 Overview This chapter describes e Instructions for inspecting the board Requirements that have to be observed when using the board e Installation and removal instructions Unpacking and Inspecting the Board Read all notices and cautions prior to unpacking the product Damage of Circuits Before touching the board or electronic components make sure that you are working in an ESD safe environment Shipment Inspection To inspect the shipment perform the following steps 1 Verify that you have received all items of your shipment which includes the following but are not limited to e Printed Quick Start Guide and Safety Notes iVPX7225 board Any optional items ordered iVPX7225 Installation and Use 680680051 1B 31 Hardware Preparation and Installation 2 Check for any damage If there is some damage report immediately to customer service 3 Remove the desiccant bag shipped together with the
78. e exchanging the battery or super capacitor 162 iVPX7225 Installation and Use 680680051 1B Safety Notes Environment Environmental Damage Improperly disposing of used products may harm the environment Always dispose of used products according to your country s legislation and manufacturer s instructions iVPX7225 Installation and Use 6806800S11B 163 Sicherheitshinweise Dieses Kapitel enth lt Hinweise die potentiell gef hrlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind Beachten Sie unbedingt in allen Phasen des Betriebs der Wartung und der Reparatur des Systems die Anweisungen die diesen Hinweisen enthalten sind Sie sollten au erdem alle anderen Vorsichtsma nahmen treffen die f r den Betrieb des Systems innerhalb Ihrer Betriebsumgebung notwendig sind Wenn Sie diese Vorsichtsma nahmen oder Sicherheitshinweise die an anderer Stelle diese Handbuchs enthalten sind nicht beachten kann das Verletzungen oder Sch den am System zur Folge haben Emerson ist darauf bedacht alle notwendigen Informationen zum Einbau und zum Umgang mit dem System in diesem Handbuch bereit zu stellen Da es sich jedoch bei dem System um ein komplexes Produkt mit vielf ltigen Einsatzm glichkeiten handelt k nnen wir die Vollst ndigkeit der im Handbuch enthaltenen Informationen nicht garantieren Falls Sie weitere Informationen ben tigen sollten wenden Sie sich bitte an die f r Sie zust ndige Gesch ftsstelle von E
79. em enclosure completely clear Ensure that any fresh air supply is not mixed with hot exhaust from other devices Ensure that all system slots are populated with either blades filler blades or dummy blades iVPX7225 Installation and Use 6806800511 161 Safety Notes Product Damage High humidity and condensation on surfaces cause short circuits Do not operate the product outside the specified environmental limits Make sure the product is completely dry and there is no moisture on any surface before applying power Expansion and FRU Replacement Product Damage Bent pins or loose components can cause damage to the product the backplane or other system components Carefully inspect the product and the backplane for both pin and component integrity before installation Personal Injury During operation hot surfaces may be present on the heat sinks and components of the product To prevent injury from hot surfaces do not touch any of the exposed components or heat sinks on the product when handling Use the handle and face plate when removing the product from the enclosure External Battery or Super Capacitor Data Loss If the external battery or super capacitor does not provide enough power anymore RTC is initialized and the data in the NVRAM is lost Data Loss Exchanging the battery or super capacitor always results in data loss of the devices which use the battery as power backup Back up affected data befor
80. en iVPX7225 Safety Notes Summary 68068005118 8 Sicherheitshinweise System Installation Betrieb Besch digung von Schaltkreisen Elektrostatische Entladung und unsachgem er Ein und Ausbau des Produktes kann Schaltkreise besch digen oder ihre Lebensdauer verk rzen Bevor Sie das Produkt oder elektronische Komponenten ber hren vergewissern Sie sich da Sie in einem ESD gesch tzten Bereich arbeiten Sch den an Steckern Wenn Sie das Modul mit Gewalt installieren k nnen die Anschlussstifte in den Steckern besch digt werden Falls sich das Modul w hrend der Installation verkantet ziehen Sie es wieder heraus und f hren Sie sie erneut ein Besch digung des Produktes und der Zusatzmodule Fehlerhafter Ein oder Ausbau von Zusatzmodulen f hrt zu Besch digung des Produktes oder der Zusatzmodule Lesen Sie deshalb vor dem Ein oder Ausbau von Zusatzmodulen die Dokumentation und benutzen Sie angemessenes Werkzeug Besch digung des Systems W hrend des Transportes Zusammenbaus und dem Umgang mit dem System k nnen sich Schrauben L fter oder andere Teile l sen oder besch digt werden Nehmen Sie ein besch digtes System nicht in Betrieb Sonst k nnen andere Einrichtungen die mit dem System kommunizieren besch digt werden berhitzung des Systems L ftungs ffnungen iVPX7225 Installation and Use 68068005118 9 Sicherheitshinweise Unzureichende L ftung kann Sch den an Blades und am System verursa
81. en the ACE is in the diagnostic test mode LOOP MCR4 1 this bitis equal to the MCR bit 2 OUT1 Not supported Complement of the data carrier detect R DCD input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bitis equal to the MCR bit 3 OUT2 Not supported 154 iVPX7225 Installation and Use 6806800511 FPGA Registers 7 3 1 10 Scratch Register SCR 7 3 1 11 This 8 bit read write register has no effect on the UART It is intended as a scratchpad register for use by the programmer Table 7 55 Scratch Register LCR IO Address Base 7 Description Default Scratch Register SCR Cold Reset 0 The scratch register is an 8 bit register that is intended for the programmer s use as a scratch pad in the sense that it temporarily holds the programmer s data without affecting any other ACE operation Programmable Baud Rate Generator The UART contains a programmable Baud Rate Generator that is capable of taking the UART CLK input and dividing it by any divisor from 1 to 2 16 1 The output frequency of the Baud Rate Generator is 16 times the baud rate Two 8 bit latches store the divisor in a 16 bit binary format These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud Rate Generator If both Divisor Latches are loaded with 0 the 16X output clock is stopped Upon loading either of the Divisor latches a 16 bit baud
82. eneral use this EEPROM is not programmed by the factory IPMC FRU Data is used in lieu of Vital Product Data in this application Boot Flash iVPX7225 provides two SPI Flash devices each capable of storing Flash Descriptor Intel ME firmware and BIOS images The SPI Flash devices support a clock rate of up to 50 MHz The SPI Flash devices are programmed to contain identical boot images for Crisis Recovery purposes in the event the primary boot image is inadvertently corrupted NAND Flash iVPX7225 supports a 4 GB of on board user NAND Flash It is designed to support 8GB for future factory builds The NAND Flash is accessible via PCH USB Port8 and the SiliconMotionSM3252 High Speed USB 2 0 Flash Memory Controller FRAM The board provides a 1 MB reset power cycle persistent indefinitely writable storage The FRAM is controlled by the iVPX7225 FPGA and is accessible via PCH LPC interface FRAM is mapped as 64k byte window in system I O space at OXFE800000 FRAM pages are selected via an FPGA register iVPX7225 Installation and Use 68068005118 Functional Description 4 16 4 17 4 18 4 19 Trusted Platform Module iVPX7225 provides a Version 1 2 Compatible Trusted Platform Module The TPM is implemented with Atmel AT97SC3204 Real Time Clock This board supports a battery backed real time clock The PCH contains a Motorola MC146818B compatible real time clock with 256 bytes of battery backed RAM The real time cloc
83. er LCR Base 4 Base 5 Base 6 Base 7 Modem Control Register MCR Line Status Register LCR Read Only Modem Status Register Read Only Scratch Pad Register SCR gt Base Division Latch LSB DLL Base 1 Division Latch MSB DLM 7 3 1 Registers DLAB 0 iVPX7225 Installation and Use 6806800511 139 FPGA Registers 7 3 1 1 7 3 1 2 140 Received Buffer Register RBR In non FIFO mode this register holds the character received by the UART s Receive Shift Register If fewer than eight bits are received the bits are right justified and the leading bits zeroed Reading the register empties the register and resets the Data Ready DR bit in the Line Status Register to zero Other error bits in the Line Status Register are not cleared In FIFO mode this register latches the value of the data byte at the top of the FIFO Table 7 44 Receiver Buffer Register RBR if DLAB 0 IO Address Base Default Access Description Receiver Buffer register RBR Transmitter Holding Register THR This register holds the next data byte to be transmitted When the Transmit Shift Register becomes empty the contents of the Transmit Holding Register are loaded into the shift register and the transmit data request bit in the Line Status Register is set to one Table 7 45 Transmitter Holding Register THR if DLAB 0
84. er Value Hatchdog Tineout Boot xi Iten Specif ic Help Enable or disable Hatchdog after POST Secur itu Lin Cooled 1 0 oo 0x9 83 4F F I isab led Disabled e Thislists some FPGA register values of interest e Watchdog after POST setting allows the Watchdog timer to cover the OS boot e Watchdog Timeout can be set to 1 2 4 or 8 minutes iVPX7225 Installation and Use 680680051 1B 99 BIOS 5 9 22 Security Menu Figure 5 22 Security Menu COM1 115200baud Tera Term VT File Edit Setup Control Window Help Hain Advanced 7225 Security Boot Exit Iten Specific Help Supervisor Passuord is Cleared User Passuord is Cleared Set or clear the Supervisor account 5 passuord Supervisor Hint String Set User Passuord ans User Hint String Hin passuord length 11 fluthent icate User on Boot Disabled HDD Securitu Status Ho HDD detected Trusted Platform Hodule TPH 100 iVPX7225 Installation and Use 6806800511 BIOS Hain fidvanced Set Supervisor Passuord Supervisor Hint String Set User Passuord User Hint String 1 Hin passuord length fiuthent icate User on Boot HDD Securitu Status Ho HOD detected Trusted Platform Hodule TPH TPH Support Enabled When a supervisor password is configured password entry is required before entering setup After configuring a supervisor password a
85. ht data bits an optional parity bit and one or two stop bits logic 1 The LCR has bits for accessing the Divisor Latch and causing a break condition The programmer also read the contents of the Line Control Register The read capability simplifies system programming and eliminates the need for separate storage in system memory Table 7 51 Line Control Register LCR IO Address Base 3 Bit Description Default Access Serial character WORD length R W 00 5 bits 01 6 bits 10 7 bits 11 8 bits Stop bit length R W 1 1 5 stop bits for 5 bit WORD length 1 2 stop bits for 6 7 and 8 bit WORD length 0 1 stop bit for any serial character WORD length iVPX7225 Installation and Use 6806800511 145 FPGA Registers Table 7 51 Line Control Register LCR continued IO Address Base 3 Bit Description Default Access Parity enable disable R W When bit 3 is set a parity bit is generated in transmitted data between the last data WORD bit and the first stop bit In received data if bit 3is set parity is checked When bit 3 is cleared no parity is generated or checked 1 Parity enabled 0 Parity disabled Parity even odd R W When parity is enabled and bit 4 is set even parity an even number of logic ones in the data and parity bits is selected When parity is disabled and bit 4 is cleared odd parity an odd number of logic ones is selected 1 Even parity 0
86. il and POST Code LEDs off 1 Normal functions of user power fail and POST Code LEDs On 7 1 16 DIP Switch Status Register 0x14 Table 7 16 DIP Switch Status Register 0x14 Description Default LPC Access I2C Access Standalone Mode RO 0 Board is in standalone mode IPMI is disabled 1 IPMI is enabled 1 TBSWAP Boot Bank Switch Ext RO 0 Board will boot from Flash 1 bank B upon power on if IPMC is not present bit 0 is zero 1 Board will boot from Flash 0 bank A upon power on if IPMC is not present bit O is zero 2 Load Default BIOS Ext RO 0 Load BIOS defaults 1 Use saved BIOS settings 7 3 Reserved 0 RO 122 iVPX7225 Installation and Use 680680051 1B FPGA Registers 7 1 17 Misc 3 Control and Status Register 0x15 Table 7 17 Misc 3 Control and Status Register 0x15 Bit Description RTM Presence Status 0 RTM is not present 1 RTM is present XMC 0 XMC root complex enabled 1 XMC root complex disabled XMC MBIST 0 XMC MBIST on going 1 XMC MBIST completed Default LPC Access I2C Access WAKE 0 XMC wake requested 1 No wake request XMC PRSNT 0 XMC is not present 1 No wake request FPGA Control Registers Block Write Protect 0 Not write protected 1 Write protected CPU PCIE Bifurcation Control 0 x8 x4 x4 1 x8 x8 Reserved iVPX7225 Installation and Use
87. install handle screw and torque wedge locks to 0 7 N M 6 Ib in Re install Torque handle screw wedgelocks iVPX7225 Installation and Use 680680051 1B 45 Hardware Preparation and Installation C 46 iVPX7225 Installation and Use 6806800511 Controls LEDs and Connectors 3 1 Board Layout Chapter 3 The following graphics show the location of the main board components Figure3 1 Main Board Components Top View Intel XDP connector Intel Processor DDR3 Ivy Bridge chips Intel Chipset PantherPoint U52 Designated In et T tu 0102 Designated 5 ensor Outlet Temperature XMC Sensor connectors ene Switch 1 Controller PCIE Switch TPM iVPX7225 Installation and Use 6806800S11B 47 Controls LEDs and Connectors Figure3 2 Board Components Bottom View NAND D23 D7 D14 D8 D16 D9 D17 D10 D18 D11 Flash Controller FPGA FRAM DDR3 chips RS232 422 485 48 iVPX7225 Installation and Use 68068005118 Controls LEDs and Connectors 3 2 Planar LEDs 3 2 1 Debug LEDs iVPX7225 provides two debug LEDs on the secondary side of the PCB The following table details the LED status descriptions Table 3 1 Planar LEDs Power Fail LED Red Persistently OFF All onboard power supplies are good and stable The RefDes D7 power OK signal SYS PWROK is also asserted Persistently ON At least one onboard power s
88. ion Reserved RO 7 1 13 System Status Register OxOE Table 7 13 System Status Register OXOE Description Default LPC Access I2C Access CPU CATERR 0 CPU catastrophic error 1 No CPU catastrophic error CPU THERMTRIP 0 CPU thermal trip indication 1 No CPU thermal trip indication 0 CPU processor hot indication 1 No CPU processor hot indication PCH S5 Sleep Indication 0 SLP 55 sleep signal asserted 1 SLP 554 sleep signal de asserted CPU PROCHOT iVPX7225 Installation and Use 6806800511 119 FPGA Registers Table 7 13 System Status Register continued Bit Description Default LPC Access I2C Access PCH S4 Sleep Indication 0 SLP 54 Sleep signal asserted 1 SLP 54 Sleep signal de asserted 3 Sleep Indication 0 SLP S3 sleep signal asserted 1 SLP 534 sleep signal de asserted PCH Suspend Well Sleep Indication 0 SLP SUS sleep signal asserted 1 SLP_SUS sleep signal de asserted PCH Active Sleep Well Sleep Indication 0 SLP A sleep signal asserted 1 SLP A sleep signal de asserted 7 1 14 Misc 1 Control and Status Register 0x10 Table 7 14 Misc 1 Control and Status Register Ox10 Bit Description Default LPC Access I2C Access COMO RS232 RS485 Mode Select 0 RS232 interface mode selected 1 RS485 422 interface mode selected COM UART RS
89. ion Cooled 27 Figure 1 3 Serial Number Label Location 29 Figure 3 1 Main Board Components Top 47 Figure 3 2 Main Board Components Bottom View 48 Figure 3 3 Air Cooled Front Panel Connectors LEDS 51 Figure 3 4 Conduction Cooled Front Panel Connectors LEDs 51 Figure 3 5 DIP Switch L cation erre ER en RR 59 Figure 4 1 iVPX7225 61 Figure 4 2 SLT3 PAY 2F2U 14 2 3 Slot Profile 63 Figure 4 3 SLT3 PAY 1F1F2U 14 2 4 Slot Profile 64 Figure 5 1 Main Ment MEE 73 Figure 5 2 tusuq E EN ER DRE ed 74 Figure 5 3 Advanced Men nee A 76 Figure 5 4 Processor Configuration 78 Figure 5 5 Processor Power Management 80 Figure 5 6 HDD Configuration 24 82 Figure 5 7 Memory Configuration an se een 84 Figure 5 8 System Agent SA Configuration 85 Figure 5 9 Graphics Configurati
90. isable Intel Management Engine 94 iVPX7225 Installation and Use 6806800511B BIOS 5 9 18 Thermal Configuration Figure 5 18 Thermal Configuration COM1 115200baud Tera Term VT Eile Edit Setup Control Window Help Thermal Conf igurat ion Iten Specif ic Help CPU Thernal gt Platforn Thernal Conf igurat ion Conf igurat ion Subnenu iVPX7225 Installation and Use 68068005118 95 BIOS 5 9 19 Platform Thermal Configuration Figure5 19 Platform Thermal Configuration COM1 115200baud Tera Term VT EE File Edit Setup Control Window Help Platform Thermal Conf igurat ion Iten Specific Help Configure CRT PSY and Critical Trip Point fict ive Trip Point Hi Fan itoat ically based Active Trip Point Lo Fan on values reconnended Passive Trip Point in BUG s Thernal Passive TC1 Value Report ing for Thermal Passive 2 Value 5 Hanagenent settings Passive TSP Value Set to Disabled for nanual conf igurat ion PCH Thermal Device Thermal Sensor Device Enable Enabled PCH Tenp Read Enable Enabled CPU Energy Read Enable Enabled CPU Tenp Read Enable Enabled CPU Read Enable Disabled 96 iVPX7225 Installation and Use 680680051 1B BIOS COM1 115200baud Tera Term VT File Edit Setup Control Window Help Platform Thermal Configuration Iten Specif ic Help Passive TSP Value 10 Enable tenprature reporting for slots PCH Thernal Device Z uith
91. k maintains the time of day and stores system data The RTC operates on a 32 768 KHz crystal The VPX VBAT input of the iVPX7225 provides a means to maintain operation when main power is removed In the event that a battery voltage is not provided at VBAT there is a diode protected 0 2F SuperCap C214 onboard the iVPX7225 RTM to maintain operation for short down times The steady state current draw at VBAT is 6 uA The minimum hold up voltage is 2V Other features include two lockable memory ranges for protection of passwords and or other system security information as well as a data alarm for scheduling wake up events Watchdog Timer The watchdog timer WDT uses an FPGA watchdog implementation with a programmable timeout 16 milliseconds to 8 minutes The watchdog may be enabled or disabled via BIOS setup or by software The BIOS disables the watchdog timer by default A timeout event causes a board reset A PCH integrated WDT is also available for use by software This timeout interval is not configurable via BIOS setup XMC Support iVPX7225 hosts one XMC site The XMC site supports an XMC add on card A single x8 or 2x4 configurable PCI E Gen 2 root port routed from the CPU PEG Port 1 x8 or Ports 1 amp 2 2x4 lanes 8 15 to the 15 connector is used The board supports XMC add on cards with PCI E link widths of x1 x2 x4 or x8 The board also supports XMC add on cards with PCI E Gen 1 and Gen 2 speeds iVPX72
92. leared to 0x00 upon platform reset 7 2 FPGASIO iVPX7225 Installation and Use 6806800511 131 FPGA Registers 72 14 7 2 1 2 132 Super IO Configuration Registers After a LPC Reset PCI_RST_ is asserted or Power Up Reset the Super IO is in the Run Mode with the UART units disabled They may be configured using the LPC IO Address Range SIW INDEX and DATA by placing the Super IO into Configuration Mode The BIOS uses these configuration addresses to initialize the logical devices at POST The INDEX and DATA addresses are effective only when the Super IO is in the Configuration State When the Super IO is not in the Configuration State reads return OxFF and write data is ignored Table 7 29 Super IO Configuration Index Register Address Ox4E Index Configuration Index OxFF LPC R W Table 7 30 Super IO Configuration Data Register LPC I O Address Ox4F Access LPC R W Description Default Entering the Configuration State The device enters the Configuration State by the following contiguous sequence 1 Write 80H to Configuration Index Port 2 Write 86H to Configuration Index Port Exiting the Configuration State The device exits the Configuration State by the following contiguous sequence 1 Write 68 to Configuration Index Port 2 Write 08 to Configuration Index Port iVPX7225 Installation and Use 68068005118 FPGA Registers 7 2 1 3
93. me to time in the content hereof without obligation of Emerson to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to a Emerson website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Emerson It is possible that this publication may contain reference to or information about Emerson products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Emerson intends to announce such Emerson products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Emerson Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Contact Address Emerson Network Power Embedded Computing Lilienthalstr 15 85579 Neubiberg Munich Germany Contents 6 About this Manual nun een 15
94. merson Das Produkt wurde entwickelt um die Sicherheitsanforderungen f r SELV Ger te nach der Norm EN 60950 1 f r informationstechnische Einrichtungen zu erf llen Die Verwendung des Produkts in einer anderen Anwendung erfordert eine Sicherheits berpr fung f r diese spezifische Anwendung Einbau Wartung und Betrieb d rfen nur von durch Emerson ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef hrt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschlie lich dazu das Wissen von Fachpersonal zu erg nzen k nnen dieses jedoch nicht ersetzen Halten Sie sich von stromf hrenden Leitungen innerhalb des Systems fern Entfernen Sie auf keinen Fall die Systemabdeckung Nur werksseitig zugelassenes Wartungspersonal oder anderweitig qualifiziertes Wartungspersonal darf die Systemabdeckung entfernen um Systemkomponenten zu ersetzen oder andere Anpassungen vorzunehmen Installieren Sie keine Ersatzteile oder f hren Sie keine unerlaubten Ver nderungen am System durch sonst verf llt die Garantie Wenden Sie sich f r Wartung oder Reparatur bitte an die f r Sie zust ndige Gesch ftsstelle von Emerson So stellen Sie sicher dass alle sicherheitsrelevanten Aspekte beachtet werden Gehen Sie mit u erster Vorsicht vor bei der Handhabung Pr fung und Einstellung dieser Anlagen und deren Komponenten bezueglich gef hrliche Spannungen die zu Verletzungen oder zum Tod f hren koenn
95. mory speed Refresh rate is programmed to DDR3 specifications Reset The BIOS can trigger a soft or warm reset by writing the reset control register RST CNT OxCF9 with 0x04 soft reset or 0x06 hard reset Global reset can also be done by writing OxOE PCle Initialization BIOS supports PCI Express Specification 2 1 and will enumerate all the bridges and devices connected from the processor to PCH PCle interface e Memory Controller Host to PCl Bridge VID 8086 DID 0104 e PCI to PCI Bridge VID 8086 DID 0101 e Integrated Graphics Controller VID 8086 DID 0116 e Universal Serial Bus USB Controller VID 8086 DID 1C2D iVPX7225 Installation and Use 68068005S11B BIOS 5 6 5 7 e PCI to PCI Bridge VID 8086 DID 1C10 e Universal Serial Bus USB Controller VID 8086 DID 1C26 e Bridge VID 8086 DID 1C43 e Mass Storage Controller VID 8086 DID 1C03 e System Management Bus VID 8086 DID 1C22 e PEX8617 PCI to PCI Bridge VID 10B5 DID 8617 e 82580 Ethernet Gigabit Controller VID 8086 DID 1516 IIO Device Configuration The iVPX7225 has two serial ports routed to the backplane COMO and COM are also accessible via Rear Transition Module RTM COMO is located on the RTM front panel A micro miniDB9 to DB9 adapter cable may be used to connect to a standard port COMI is accessible via RTM planar header P701 By default BIOS ConsolelO is re directed to both COMO and COMI Def
96. nd 8 lanes Gen2 PCle max 5 0 GT s Six SATA controllers two supporting 6Gbps transfer rate 14 USB host controllers USB 2 0 in this application Three digital displays DP eDP HDMI DVI sDVO One analog display CRT VGA SPI interface 2 CS LPC interface SMBus Programmable interrupt controller watchdog timer real time clock Gigabit Ethernet controller 10 100 1000BASE T Native Gbe Controller unused in this application System Memory The iVPX7225 includes 8GB ECC protected DDR3L 1600 Industrial Grade memory 4GB Channel The iVPX7225 is produced a ruggedized memory down configuration for more demanding operating environments iVPX7225 Installation and Use 68068005S11B 4 5 Functional Description B Ethernet Interfaces iVPX7225 provides two 1000BASE BX ports that are routed to the VPX backplane for operation as Ultra Thin Pipes per VITA 65 SLT3 PAY 2F2U 14 2 3 and SLT3 PAY 1F1F2U 14 2 4 slot profiles Ethernet is implemented using an Intel 82580 Gigabit Ethernet controller onboard the iVPX7225 PCH PCIe Port 0 lanes 1 4 configured as x4 is routed to the 82580 When accessed through RTM in a non switch backplane configuration dual PHYs onboard the iVPX7225 RTM convert these control plane interfaces to 1000BASE T These are accessible at the dual RJ 45 RTM planar connector J101 NOTICE Because the Ethernet interface to the backplane is 1000Base BX the associated 1000Base T ports on the RTM
97. nd removal can damage circuits or shorten their life Before touching the board or electronic components make sure that you are working in an ESD safe environment Product Damage e Inserting or removing modules with power applied may result in damage to module components Before installing or removing additional devices or modules read the documentation that came with the product iVPX7225 Installation and Use 6806800511 35 Hardware Preparation and Installation 2 4 4 Installing the XMC on Air Cooled Board Read all notices and follow these steps to install an XMC on Air Cooled iVPX7225 1 Remove XMC bezel Remove XMC bezel Remove screws 2 Install air cooled XMC module With the XMC mating connectors properly aligned apply minimal pressure to the XMC module over the connectors until the XMC module is seated to iVPX7225 Install XMC screws as shown below Install top screws Install bottom screws 36 iVPX7225 Installation and Use 6806800511B Hardware Preparation and Installation 2 4 2 Installing the XMC on Conduction Cooled Board Read all notices and follow these steps to install an XMC on the Conduction Cooled iVPX7225 1 Remove 7 screws and XMC cover Remove cover Remove 7 screws 7 2 Install conduction cooled XMC module With the XMC mating connectors properly aligned apply minimal pressure to the XMC module over the connectors until the XMC module is seated to iVPX72
98. nd transferred into the RBR or the FIFO DR is cleared by reading all of the data in the RBR or the FIFO 1 New data received 0 No new data Overrun error OE indicator R When OE is set it indicates that before the character in the RBR was read it was overwritten by the next character transferred into the register OE is cleared every time the CPU reads the contents of the LSR If the FIFO mode data continues to fill the FIFO beyond the trigger level an overrun error occurs only afterthe FIFO is full and the next character has been completely received in the shift register An overrun error is indicated to the CPU as soon as it happens The character in the shift register is overwritten but it is not transferred to the FIFO 1 Overrun error occurred 0 No overrun error iVPX7225 Installation and Use 68068005118 149 FPGA Registers Table 7 53 Line Status Register LSR continued IO Address Base 5 Bit Description Default Access 2 Parity Error PE indicator 0 R When PE is set it indicates that the parity of the received data character does not match the parity selected in the LCR bit 4 PE is cleared every time the CPU reads the contents of the LSR In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the CPU when its associated character is at the top of the FIFO 1 Parity error occurred 0 No parity
99. ng Outside Plant J Services Connectivity u Embedded Power J Power Switching amp Control Site Monitoring B DC Power Systems Integrated Cabinet Solutions Precision Cooling I Surge amp Signal Protection Emerson Business Critical Continuity Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co All other product or service names are the property of their respective owners 2013 Emerson Electric Co
100. ng Air Cooled 7225 2 43 2 5 2 Installing Conduction CoolediVPX7225 44 3 Controls LEDs and Conhectors nare ser a 47 Bel Board EVI MED 47 3 2 PlanarbEDS rs ie rareste 49 Debug dees e etre 49 3 2 2 POST Code EDS Ta a a ho 50 3 3 Front Panel Connectors and LEDs 51 3 4 Backplane Connectors 53 3 4 1 PO Connector aars Ge sake aie dad ee E pee RR E Eb dia 53 iVPX7225 Installation and Use 6806800511 Contents 3 4 2 ee UR aU ERR a 54 3 4 3 P2 CONNEC coe ius er EE eae eg ee Ree ete Weed whe REE ETE See eee 55 3 5 IXAMC COMMEGION 2 2 5 5 saus ua ss ne Lese ee kalla 56 3 6 SWItches ETR SER ERE 59 4 Functional Description u a u e a E uss 61 4 1 Block Diagram L usuyasa eem ee eese Ie aos est oce 61 4 2 PIOCesSOLu oer teer daw re 62 43 Chipseb 62 4 4 System Memory ua bara bes eR ae e M ida en 62 4 5 Eth rnetlnterlaces kb Wess pov rere 63 4 6 REIEXPFESS TTE EET 64 TEMERE 64 425 USB rv T 65 49 Serial COM
101. oduct standard compliances mechanical data and ordering information e Hardware Preparation and Installation outlines the installation requirements hardware accessories switch settings and installation procedures e Controls LEDs and Connectors describes external interfaces of the board This includes connectors and LEDs e Functional Description includes a block diagram and functional description of major components of the product BIOS provides information on the BIOS Setup Utility e Maps and Registers provides information on the product s memory maps e FPGA Registers provides information about the FPGA registers e Related Documentation provides a listing of related product documentation manufacturer s documents and industry standard specifications e Safety Notes summarizes the safety instructions in the manual e Sicherheitshinweise is a German translation of the Safety Notes chapter Abbreviations This document uses the following abbreviations Abbreviation Description Indication for LOW active signals 2LM Two Level Maintenance BIOS Basic Input Output System BOM Bill of Material CFM Cubic Feet per Minute COM Serial V 24 V 28 compliant interface iVPX7225 Installation and Use 6806800511 15 About this Manual Abbreviation Description Central Processing Unit CRT Cathode Ray Tube DR Double Data Rate DDR3 Double Data Rate 3 SDRAM is the name of the new DDR memory stand
102. of CPU and I O loads including exercising memory local and backplane PCle traffic SATA Gigabit Ethernet FRAM and USB Maximum Power Calculated worst case power based on device TDP and is not expected to be reached under normal operation A CPU intensive workload could encroach upon this value All power requirements are specified with no XMC populated in the XMC site The XMC site draws power directly from the VPX backplane No onboard regulation In the absence of an XMC the iVPX7225 draws no power from the VPX 3 3V VS2 rail However the 3 3V Total power specified above includes a VS2 contribution due to the presence of an RTM in the test configuration The RTM draws 3 3V predominantly from VS2 One can therefore estimate the iVPX7225 3 3V AUX power consumption by subtracting the iVPX7225 RTM 3 3V power consumption from the total The iVPX7225 3 3V AUX power consumption is fairly static at 2 3W Refer iVPX7225 RTM IU Manual for the RTM power consumption specifications Installing the Accessories The following sections contains procedures on how to install the accessories on the iVPX7225 board NOTICE Proper alignment of the XMC connector is essential to prevent damage to the XMC module and or to the mating XMC connector on the iVPX7225 iVPX7225 Installation and Use 6806800511 Hardware Preparation and Installation Damage of Circuits Electrostatic discharge and incorrect installation a
103. on 2 2 86 Figure 5 10 IGD Configuration net ETE Rd 87 Figure 5 11 PEG Port Configuration prt enter 88 Figure 5 12 South Bridge Configuration 89 Figure 5 13 SB USB Configuration su oco rr e e 90 Figure 5 14 SB Security Configuration 91 Figure 5 15 Network Configuration 2 92 Figure 5 16 SIO Configuration ne 93 Figure 5 17 ME Configuration use ae 94 Figure 5 18 Thermal Configuration seen 44d ee ee an 95 Figure 5 19 Platform Thermal Configuration 96 Figure 5 20 Intel Rapid Start Technology 98 Figure 5 21 IVPX 7225 Menu ceux ner dada une ee ia bene 99 Figure 5 22 MENU ipia een E PEE a PER ends 100 Figure 5 23 TPM Configuration u u ee ae ie 102 Figure 5 24 Boot Menu issus Ree q pee de betes e e OI EE E tae ea 103 Figure 5 25 Exit Menu m 104 iVPX7225 Installation and Use 68068005118 13 List of Figures 14 iVPX7225 Installation and Use 680680051 1B About this Manual Overview of Contents This manual is divided into the following chapters and appendices e Introduction gives an overview of the features of the pr
104. on Enabled select LAN 1 OPROH LAN 3 OPROH Selection Enabled for quick boot ASF Support Disabled nininal conf igurat ion e LAN I refers to Onboard LAN 1 Intel GE Slot 0400 e LAN 2 refers to Onboard LAN 2 Intel GE Slot 0401 LAN 3 refers to XMC LAN e Disabling LAN OPROMs can improve boot time 92 iVPX7225 Installation and Use 680680051 1B BIOS 5 9 16 SIO Configuration Figure 5 16 SIO Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help 10 Conf igurat ion Iten Specific Help Enab ledi This option controls UART1 Hode R5 232 the Onboard WARTI Onboard UART2 Enabled Address Hhen URRT2 Hode RS 232 enabled UARTI uses Onboard UARTS Enabled na Ox3F8h and e UART1 COMO refers to the RTM DB 9 connector e UART2 COM1 refers to RTM onboard header e UART3 refers to the IPMC host interface UART1 and UART2 can be configured for either RS 232 or RS 422 RS 485 compatibility iVPX7225 Installation and Use 68068005118 93 BIOS 5 9 17 MEConfiguration Figure 5 17 ME Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help HE Conf igurat ion Iten Specific Help HE FH Version 8 1 0 1265 Enable Disable HE Firnuare Intel R HE SHB firnuare Intel R Hanagenent Enab led Engine HE FH Doungrade Disabled HE Debug Event Service Disabled HDES for BIOS Disabled HE IFR Feature Enabled Users can enable d
105. onmental Parameter Air Cooled Conduction Cooled Cooling Method Forced Air Conduction Operating Temperature 40 C to 71 C 40 C to 71 card edge Storage Temperature 50 C to 100 50 C to 100 C Vibration Sine 10 min Axis 5G 15 to 2000 HZ Vibration Random 1 Hr Axis 0 04g2 Hz 15 to 2000 Hz 0 1g2 Hz 15 to 2000 Hz 8GRMS 3 12GRMS Shock 30g 11ms 40g 11ms Humidity to 9575 RH non condensing to 9575 RH non condensing 1 Ambient temperature at sea level without PMC XMCs installed while maintaining gt 80 CPU performance lt 20 frequency down step or duty cycle throttling 2 Measured at card edge without PMC XMCs installed while maintaining gt 80 CPU performance lt 20 frequency down step or duty cycle throttling 3 Flat 15 1000Hz 6db octave 1000Hz 2000Hz MIL STD 810F Figure 514 5C 17 4 3db octave 15 300Hz Flat 1g2 300 1000Hz 6db octave 1000Hz 2000Hz MIL STD 810F Figure 514 5C 8 iVPX7225 Installation and Use 6806800511 33 Hardware Preparation and Installation 2 4 34 Power Requirements The following table contains the Power requirements Table 2 2 Power Requirements Voltage Rail Minimum Power Typical Power Maximum Power am pa Minimum Power Representative of running Linux a pure text mode No X11 No GNOME resting idle the Linux login prompt Typical Power Representative of running a mixture
106. rip 0 Reset not due to CPU Thermal trip signal 1 Reset due to CPU Thermal trip signal 7 Reset due to XDP DBR 0 R WTC RO 0 Reset not due to XDP DBR 1 Reset due to XDP DBR 114 iVPX7225 Installation and Use 68068005118 FPGA Registers 7 1 8 Watchdog Control Register 0x09 Table 7 8 Watchdog Control Register 0x09 Default I2C Access OxF Bit Description LPC Access Length of Watchdog Timer The read access will not show the correct data until write data is loaded into watchdog timer to load set bit 5 1 during write 0000 16ms 0001 0010 0011 0100 32 ms 64 ms 128 ms 256 ms 0101 512ms 0110 1s 0111 1000 1001 1010 2s 4s 8s 16s 1011 32s 1100 1 min 1101 1110 1111 2 min 4 min 8 min 4 Watchdog Enable 1 0 Watchdog disabled 1 Watchdog enabled It is also auto enabled after power on reset and soft reset iVPX7225 Installation and Use 6806800511 115 FPGA Registers Table 7 8 Watchdog Control Register 0x09 continued Bit Description Default LPC Access 2 Access Watchdog Load Timer 0 Don t load watchdog timer 1 Load watchdog timer Watchdog NMI Status 0 NMI not asserted 1 NMI asserted Reserved 7 1 9 Watchdog Re trigger Register Table 7 9 Watchdog Re trigger Register Bit Description Default
107. rol Window Help Graphics Conf igurat ion Iten Specific Help ol Enable Disable the Prinary Display Selection Auto Internal Graphics Size 2 Device This has no Aperture Size effect if external DYKT Pre Rllocated graphics are present DYKT Total Gfx Hen Render Standbu 160 Thermal Control Disabled GT Turbo Hode Control Disabled gt IGD Conf iqurat ion e Graphics settings can be set for performance needs 86 iVPX7225 Installation and Use 6806800511 BIOS 5 9 10 IGD Configuration Figure 5 10 IGD Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help IGD Conf igurat ion Iten Specif ic Help Select the Video 160 LCD Panel Type VBIOS Default Device act ivated IGD Panel Scaling Auto during POST This IGD Portrait Hode Auto has no effect if Inverter Connect ion Internal external graphics are GHCH BLC Control Inverted present BIR Auto Spread Spectrun clock Chip Off 160 TY Control BIOS default 160 TY2 Control BIOS default 160 Active 11 1405 Panel Color Depth 18 Bit iVPX7225 Installation and Use 6806800511 87 BIOS 5 9 11 PEGPort Configuration Figure 5 11 Port Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help PEG Port Conf iqurat ion Iten Specific Help Rut ol Conf igure PEGO PEG1 Gen amp Auto B D1 FO Speed PEG2 Gen Ruto PEG3
108. rs mean deeper sleep to almost power off iVPX7225 Installation and Use 6806800511 81 BIOS 5 9 6 Configuration Figure 5 6 HDD Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help HDD Configuration Iten Specific Help Enab ledh Enable Disable SATA Interface Conbinat ion RHCT flgaressive Link Pouer Enabled gt Softuare Feature Hask Conf igurat ion Serial ATA Port is ESRTR Port Mot Installed Hot Plug Enabled External Port Disabled Port Topology Cablellp SATA Device Type Hard Disk 071 Serial ATA Port 1 is ESATA Port Not Installed Hot Plug Enabled External Port Enabled Port Topologu Cablellp SATA Device Type Hard Disk Dril v 82 iVPX7225 Installation and Use 680680051 1B BIOS R COM1 115200baud Tera Term VT HDD Configuration Hot Plug External Port Port Topology SATA Device Type Serial ATA Port 1 is ESATA Port Hot Plug External Port Port Topology SATA Device Type Serial ATA Port 4 is ESATA Port Hot P lug External Port Serial ATA Port 5 Hot Plug iVPX7225 Installation and Use 680680051 1B File Edit Setup Control Window Help Iten Specific Help Enabled Disabled CableUp Hard Disk Dril m Installed Enabled Cablellp Hard Disk Dril Hot Installed Enabled Enabled Hot Installed Disabled REISEN Configure systen to treat the Port as internal or external Interfa
109. sible only in the Configuration Mode Table 7 31 Global Configuration Register Summary Index Address Description 0x07 Super IO Logical Device Number 0x20 Super IO Device ID 0x21 Super IO Device Revision iVPX7225 Installation and Use 6806800511 133 FPGA Registers 134 Table 7 31 Global Configuration Register Summary Index Address Description Super IO LPC Control Table 7 32 Super IO Logical Device Number Register Index Address 0x07 Description Default Logical Device Number LPC R W 0x04 Logical Device 4 UART 1Serial Port 1 0x05 Logical Device 5 UART 2 Serial Port 2 0x06 Logical Device 6 UART 3Serial Port 3 A write to this register selects the current logical device This allows accessto the control and configuration registers for each logical device Table 7 33 Super IO Device Identification Register Index Address 0x20 Table 7 34 Super IO Device Revision Register Index Address 0x21 Bit Description Default Device Revision iVPX7225 Installation and Use 68068005118 FPGA Registers Table 7 35 Super IO LPC Control Register Index Address 0x28 Bit Description Default Access LPC Bus Wait States LPC 1 Long wait states sync 6 Reserved LPC R Index Address 0x29 Description Default Access SERIRQ enable LPC R W 0 disabled Serial interrupts disa
110. ss Base 2 Bit Description Default Access 5 4 Reserved FIFO Mode Enable bits 00 Default mode 01 Reserved 10 Reserved 11 FIFO mode Table 7 49 Interrupt Identification Register Decode Interrupt ID Interrupt Set Reset Function 3 0 Priority Source 0b0001 None No Interrupt is pending 0b0110 1 Receiver Overrun Error Parity LineStatus Error Framing Error Break Interrupt Reset Control Reading the Line Status Register 0b0100 2 Received Non FIFO mode Data Receive Buffer is full Available FIFO mode Trigger level was reached 0b1100 Character FIFO Mode only At Timeout least 1 character is in indication receiver FIFO and there was no activity for a time period Non FIFO mode Reading the Receiver Buffer Register FIFO mode Reading bytes until Receiver FIFO drops below trigger level or setting RESETRF bit in FCR register Reading the Receiver FIFO or setting RESETRF bit in FCR register iVPX7225 Installation and Use 6806800511 143 FPGA Registers 7 3 1 5 144 Table 7 49 Interrupt Identification Register Decode Interrupt ID Interrupt Set Reset Function 3 0 Priority Type Source Reset Control 0b0010 3 Transmit Non FIFO mode Reading the IIR Register FIFO Data Transmit Holding if the source of the Request Register Empty interrupt or writing into the Transmit Holding Register 0b0000 4 Modern Clear to Send
111. tate 0 DTR output in high state Default Access R W Request to send RTS output control 1 RTS output in low active state 0 RTS output in high state User output control signal OUT 1 1 OUT1 output in high state 0 OUT1 output in low state Not supported R W R W User output control signal OUT2 1 OUT2 output in high state 0 OUT2 output in low state Not supported R W iVPX7225 Installation and Use 6806800511 147 FPGA Registers 7 3 1 8 148 Table 7 52 Modem Control Register MCR continued IO Address Base 4 Bit Description Default Access Local loop back diagnostic control R W When loop back is activated Transmitter TXD is set high Receiver RXD is disconnected Output of Transmitter Shift register is looped back into the receiver shift register input Modem control inputs are disconnected Modem control outputs are internally connected to modem control inputs Modem control outputs are forced to the inactive high levels 1 Loop back mode activated 0 Normal operation Autoflow control enable AFE R W 1 Autoflow control enabled auto RTS and auto CTS or auto CTS only enabled 0 Autoflow control disabled Reserved R Line Status Register LSR This register provides status information to the processor concerning the data transfers Bits 5 and 6 are showing information about the transmitter sec
112. tblende an wenn Sie es aus dem System herausnehmen iVPX7225 Installation and Use 68068005118 Sicherheitshinweise Externe Batterie or Super Kondensator Datenverlust Wenn die externe Batterie oder super Kondensator nicht mehr genug Energie zur Verfuegung stellen wird der RTC initializierd und die Daten in der PCH Batterie backed RAM sind verloren Das kommt auch vor jedesmal wenn das Board aus dem System entfernd wird und oder wenn das System kein VBAT zur Verfuegung stellt und das RTM ist nicht installiert Datenverlust Austausch der Batterie oder super Kondensator verursacht immer einen Datenverlust der Komponente die diese Batterie als Engergie Backup benutzen Daten sollten gesichert werden bevor die Batterie oder super Kondensator ausgetauscht wird Environment Umweltverschmutzung Falsche Entsorgung der Produkte schadet der Umwelt Entsorgen Sie alte Produkte gem der in Ihrem Land g ltigen Gesetzgebung und den Empfehlungen des Herstellers iVPX7225 Installation and Use 680680051 1B 11 Sicherheitshinweise 12 iVPX7225 Installation and Use 680680051 1B HOW TO REACH LITERATURE AND TECHNICAL SUPPORT For literature training and technical assistance and support programs visit www emersonnetworkpower com embeddedcomputing Emerson Network Power www emersonnetworkpower com embeddedcomputing The global leader in enabling Business Critical Continuity Power Systems Embedded Computi
113. tion The rest of the bits contain information about the receiver In non FIFO mode three of the LSR register bits parity error framing error and break interrupt show the error status of the character that has just been received In FIFO mode these three bits of status are stored with each received character in the FIFO LSR shows the status bits of the character at the top of the FIFO When the character at the top of the FIFO has errors the LSR error bits are set and are not cleared until software reads LSR even if the character in the FIFO is read and a new character is now atthe top of the FIFO iVPX7225 Installation and Use 68068005118 FPGA Registers Bits one through four are the error conditions that produce a receiver line status interrupt when any of the corresponding conditions are detected and the interrupt is enabled These bits are not cleared by reading the erroneous byte from the FIFO or receive buffer They are cleared only by reading LSR In FIFO mode the line status interrupt occurs only when the erroneous byte is at the top of the FIFO If the erroneous byte being received is not at the top of the FIFO an interrupt is generated only after the previous bytes are read and the erroneous byte is moved tothe top of the FIFO Table 7 53 Line Status Register LSR IO Address Base 5 Description Default Access Receiver data ready DR indicator R DRis set whenever a complete incoming character has been received a
114. upply is failing Blinking 0 25 seconds ON 0 25 seconds OFF Board has power shut down but also indicates that all the onboard power supplies are up and stable This will also indicate that the board is waiting for the platform reset signal PLT RST to de assert User LED Bicolor Green is persistently ON Indicates that the platform reset signal RefDes D23 Yellow PLTRST L is de asserted and the board starts to boot up Green Green is blinking Indicates that the CPU signal is asserted The CPU has reached its maximum junction temperature If PROCHOT is persistently asserted the Green LED will blink in a periodic manner 0 25 seconds ON 0 25 seconds OFF Yellow is ON Indicates that the on board NAND Flash or SATA device is being accessed example OS is booting up from these devices Yellow is blinking 0 25 seconds ON 0 25 seconds OFF Indicates that the CPU THERMTRIP signal is asserted and the CPU will stop all execution Green and Yellow are alternately blinking Indicates the CPU has experienced a catastrophic error and cannot continue to operate iVPX7225 Installation and Use 6806800511 49 Controls LEDs and Connectors 3 2 2 POST Code LEDs The 8 bit POST Code value is flashed on an array of 8 amber LEDs on the secondary side of the PCB The following table lists bit assignments Table 3 2 POST Code LEDs Bit RefDes 50 iVPX7225 Installation and Use
115. user password may also be configured Certain critical features are protected from modification when setup is entered with the user password e IfAuthenticate User on Boot is enabled either supervisor or user password will be required to launch a boot option iVPX7225 Installation and Use 6806800511 101 BIOS 5 9 23 TPM Configuration Figure 5 23 TPM Configuration COM1 115200baud Tera Term VT File Edit Setup Control Window Help Security Conf iqurat ion Current State Enabled and fict ivated io Change Boot Heasurenents Disabled Iten Specif ic Help Enact TPH Rct ion Note Host TPH actions require TPH to be Enabled to take effect e TPMis enabled but will need to have an action set based on the user s needs 102 iVPX7225 Installation and Use 68068005118 BIOS 5 9 24 Boot Menu Figure 5 24 Boot Menu COM1 115200baud Tera Term VT File Edit Setup Control Window Help Hain Advanced 7225 Security Iten Specific Help Boot Priority Order 2 ATA HODO 3 4 5 6 8 9 10 11 12 ATA HDD1 ATA HDD4 ONBOARD LAN 1 IBA GE Slot 0400 1404 ONBOARD LAN 2 IBA GE Slot 0401 1404 Other HDD USB HOD USB CD USB FDD SHC LAN Internal Shell iVPX7225 Installation and Use 680680051 1B Keys used to or configure devices and v arrous Select a device and nove the device up or domn
116. wed unless protected by NVMRO 1 Device is write protected iVPX7225 Installation and Use 6806800511 117 FPGA Registers 7 1 11 Power Good Status 1 Register 0 0 Table 7 11 Power Good Status 1 Register 0 0 Bit Description Default LPC Access I2C Access 3 3V PS Power Good indication 0 3 3V PS power failure 1 3 3V PS power good indication 1 8V PS Power Good indication 0 1 8V PS power failure 1 1 8V PS power good indication 1 5V PS Power Good indication 0 1 5V PS power failure 1 1 5V PS power good indication 1 0V PS Power Good indication 0 1 0V PS power failure 1 1 0V PS power good indication 0 VIT PS power failure 1 VTT PS power good indication VSA PS Power Good indication 0 VSA PS power failure 1 VSA PS power good indication GFX Core PS Power Good indication 0 GFX Core PS power failure 1 GFX Core PS power good indication Core PS Power Good indication 0 Core PS power failure 1 Core PS power good indication 118 iVPX7225 Installation and Use 6806800511 VTT PS Power Good indication FPGA Registers 7 1 12 Power Good Status 2 Register OXOD Table 7 12 Power Good Status 2 Register OxOD Description Default LPC Access I2C Access 5V PS Power Good Indication Ext RO 1 5V PS power good indication 2 5V PS Power Good Indication 0 2 5V PS power failure 1 2 5V PS power good indicat

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