GR712 Development Board User Manual
Contents
1. 213 HDR2X6 228 9 eee eode jun JPTO mim 3 330u 5 ig am 3 2 8 9 5 AE s 330R R201 gc 1OncisE 15 Yi 5 por one 9 9 769k 8 e SORRIA EE 405 12 5 4989141 P R131 LJ el 8 Rs 5 mad z E 8 ma EC 9 e 8 LII re BEAD ws 22282 ied 55586 BEAD NF im HE 5 29 8 CR x 23 e 688 seinan 1 a dd sad pi eco JT Ns E e E RASE 8194 US 4708 on XR 22k 5 EEFE 271 a C72 RTA 22222 zi 5 ES XD ae 88822 000003 celcesesese ee 82822 88888 ses ee eco ee eco eco eco eco E 54 lememsusueusususususucs THOR 5 Dspolvo4d Ill 5 s 8 3 3 x 229 m emcee 0147 mm Cium mH 8 0 8 31 su 10n 40n 10n 18 10 qp ES 3002. 39 GR712 Development Board GAISLER User Manual 01 01 00c Gaisler Research Generic UART ver 0x1 irq 2 apb 80000100 80000200 baud rate 38461 DSU mode FIFO debug 02 01 00d Gaisler Research Multi processor Interrupt Ctrl ver 0x3 80000200 80000300 03 01 011 Gaisler Research Modular Timer Unit ver 0 0 irq 8 apb 80000300 80000400 16 bit scaler 4 32 bit timers divisor 48 04 01 02 Gaisler Research SPI Controller ver 0 2 irg 13 80000400 80000500 depth 16 no slave select lines Maximum word length 32 bits 05 01 081 Gaisler Research bus multiplexer ver 0x0 apb 80000500 80000600 06 01 087 Gaisler Research General purpose registers ver 0x0 80000600 80000700 07 01 043 Gaisler Research 5 5 Master ver 0x0 irq 16 80000700 80000800 2 slaves 16 bit words 09 01 01a Gaisler Research General purpose I O port ver 0x0 apb 80000900 80000a00 0a 01 01a Gaisler Research General purpose I O port ver 0x0 80000 00 80000b00 0 01 028 Gaisler Research Wrapper for I2C master ver 0 1 28 80000 00 80000400 0d 01 02c Gaisler Research Clock gating unit ver 0x0 apb 80000d00 80000e00 GRMON did NOT enable clocks during initialization 0 01 052 Gaisler Research status register ver 0 0 1 8000000 80001000 01 01 00c Gaisler Research
3. a ce 11 PES RTT 12 232 PAS a ee 12 233 12 2 3 4 Expansion Connector sise 13 2 4 Switch Matrix for 0 eene 13 2 5 CAN INETTAC T 16 2 5 1 Configuration of Bus Termination 16 2 5 2 Configuration of Slew Rate 17 26 LVDS Interfaces 17 2 6 1 SPW interface 0 00 2 arse nnns 17 ENSSPMESIUIGBu 18 2 7 RS422 Interfaces for UART and functions 19 2 7 1 RS422 Transmitter CirCullS u a runi cda ci ei ipa agus 20 2 1 2 R9422 Receiver carcer cr i wakana 20 2 8 21 29 21 2210 EI CE 22 211 22 2 42 Serial Interface mM 24 2 13 Debug Support Unit DSU Serial Interface 24 2 14 Oscillators and Clock 25 2 14 1 d 25 2 14 2 SPW_CLK 25 2 14 3 Ethernet 0 0 0 6
4. 37 Table 4 10 J7 SPW 4 interface CONNECTIONS 37 Table 4 11 SPW 5 interface enne 38 Table 4 12 Expansion connector 39 Table 4 13 410 RJ45 ETHERNET 21 0 40 Table 4 14 Expansion connector J11 40 Table 4 15 J12 ASIC Connector 0 41 Table 4 16 J13 Dual MIL STD 1553 interface 41 Table 4 17 J14 POWER External Power 41 Table 4 18 SODIMM socket J15 0 0 5 nennen 42 Table 4 19 J16 RS422 Transmitter 0 02 0 0 10 6 43 Table 4 20 J17 RS422 Transmitter 0 0 0 0 1 6 43 Table 4 21 J18 RS422 Receiver 002 0 0 0 0 n eene nnne 43 Table
5. 34 Figure 3 3 GRMON Line ut 35 Figure 4 1 PCB Assembly VIGW 53 Figure 4 2 PCB Assembly VIBW eius serre 52 Figure 4 3 PCB Connector POSITIONS Fx anse ages een 53 Figure 4 4 GR712 Assembly a einen nt lente ed 54 Gaisler August 2014 Rev 0 11 GAISLER REVISION HISTORY 7 GR712 Development Board User Manual Revision Date Page Description 0 1 2011 01 24 New document 0 2 2011 02 03 52 13 54 2 Changed DSU BREAK switch to not used 83 Updated figures 0 3 2011 02 24 Various small edits 0 4 2011 03 29 30 Corrected GRMON command 0 5 2011 07 22 2 6 2 Added additional text to describe setting SpW Clock Divisor Registers 0 6 2011 10 03 52 13 Added mention of FT2232 chip for USB JTAG Interface Table 4 1 Corrected JTAG connector type for J12 Mini USB Table 4 15 Corrected pin names for J12 Mini USB 0 7 2012 02 22 82 3 3 Added note about maximum SDRAM clock speed 82 12 Corrected references to jumper JP1 and its pinning Table 4 36 0 7a 2012 02 23 Table 3 1 Correct defaults for JP1 JP2 0 8 2013 01 21 3 Removed i option as not compatible with latest versions of grmon grmon2 0 9 2013 08 28 RD 5 amp Added refere
6. SES 895 SES 5 E E 7 525 n lese E Bs Dae 222222 9 E TECH AKT akg A Bs TETEN x ES 2 8 ER B e 5 1 5 Es o E usa y ERO B g GR712 PQ240 Mee 9 ours E x 8 gl seu El EU 470R Big Fe 225228 Bs em Rea a RI070R B T 845 gs 28 g s 3 168 9 8 R189 9 ti 8 51901021 H I6 41708 E 88 Eu 40k eet ie 133 R181 XXE Er B ui 33R 33R 338 338 33R 33R 392 u gg GD OED EI EIS c g g 285888 175 C32 6152 5 SR E D 9 i T5 088 lo 1266650 ce Bi wee 47 III 959 je 652522 ot SN ES 5 n 88 8 mee g 8 8 P mE e zd 0 0 5 9 P 5 allg Ta 8 5 3 8 8 8 8 8 3 10 8 8 8 E Bs c Be 8 8 8 8 e o 5 5 5 E 2 e cso ems Toon ET E 10 100n ge E Du 85 OW gu Sad PE ma TE28F640 3
7. 2 8 TRANSCEIVER t E Figure 2 8 Block Diagram of the CAN interface 2 5 1 Configuration of Bus Termination The CAN interfaces on the board can be configured for either end node or stub node operation by means of the jumpers JP78 and JP79 for interface 1 and 2 respectively as shown in Figure 2 9 For normal end node termination with a nominal 120 Ohm insert jumpers in position 1 3 However if a split termination is desired if required for improved EMC performance insert the jumpers in positions 1 2 and 3 4 For stub nodes if termination is not required do not install any jumpers Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual R40 DGND 22 3V3 100n CANTXA 414 TXD CANH J2A CANRXA 8 SPLIT D9P DUAL a 8 gt sm CANL R42 043 lt SN65HVD230 2 2 DGND DGND Note For this device signal is defined as STANDBY 1 i e ENABLE 0 NF Change resistor if slope control is required 1 CHASSIS OR default gt 1Mbps operation L 10kOhm gt 154 45 Termination resistors are 200mW rating DGND For end node termination 120 Ohm nominal insert jumpers 1 3 If split termination is desired for improved EMC performance insert jumpers 1 2 and 3 4 For stub nodes if termination is not required do not install jumpers Figure 2 9 Transceiver and Termination Configuration one
8. 25 2 14 4 MIL STD 1553 Interface Clock 25 2 15 Power Supply and Voltage Regulation 26 2 16 Ethernet ntemace a dm nl eco UU D Dt Deu 26 2 17 MIL STD 1553 27 2 18 Other Interfaces and 1 1 00 1000 28 UE 28 2 18 2 Reset Circuit and 0 1 444 28 218 3 Watchd0og TN 28 2 18 4 JTAG Interfac u 29 2 18 5 2C Interfaces uoce 29 2186 coe c er Ute be ee reb evade 29 SETTING UP AND USING THE 31 INTERFACES AND CONFIGURATION 36 4 1 List of Front Back Panel 14 ener nnns 36 Aeroflex Gaisler AB August 2014 Rev 0 11 GR712 Development Board GAISLER User Manual 4 2 List of Oscillators Switches and 5 48 4 97 LIST ON 49 Gaisler August 2014 Rev 0 11 5 GR
9. Gaisler August 2014 Rev 0 11 GAISLER 35 3 SETTING UP AND USING THE BOARD The default status of the Jumpers on the boards is as shown in Table 3 1 For the meaning of the various jumpers refer to Table 4 38 and RD 1 Jumper Jumper Setting Comment JP1 Installed 3 5 and 4 6 Connects to RS232 interface JP2 Installed 3 5 and 4 6 Connects TX1 RX1 to RS232 interface JP3 JP66 Installed 1 2 to connect User sets these jumpers according to which configuration all signals as GPIO and interfaces are to be used See section2 4 JP67 No connections Not normally used JP68 Not defined JP69 Not defined JP70 Installed 1 2 and 3 4 10k pull ups enabled 2 interface JP71 Not installed Install 1 2 to allow 54 to act as SPI chip select of on board SPI chip JP72 Not installed Only required for Direct Coupling JP73 Not installed Only required for Direct Coupling JP74 Not installed Only required for Direct Coupling JP75 Not installed Only required for Direct Coupling JP76 Installed 1 2 3 4 5 6 7 8 Only remove if on board RAM and FLASH is to be disabled JP77 Not installed Only install if PROM writing is to be disabled JP78 Installed 1 3 End stub termination enabled see section 2 5 1 JP79 Installed 1 3 End stub termination enabled see section 2 5 1 JP80 Installed 1 2 Can be used as curre
10. Loog GR712 PQ240 Bi R a ow bee bs SORO RREI Deo qas 8 TORO RB ORO RO 8 73 5 e Q co 4 S009 e honaxe PS7 K 215 66 45 z 184 i TORO R ORO ROS i H 55 pe JPT9 zr c 88 1085885 106689 8 C 88 d A 52 0 4 EJ PTS 9 HDR2X2 o P z g 8 E 3 amp CE AE 33 a 2 55 FES FC 3 g 5 Am N s _ e 8 8 M 5 Elo M 5 5 gc dm 30 8 2 E 8 8 3 5 Sw 3 aololg S 3 TBD MHz y li 1 Ty 20 5 jo NNEGTOR m m 22 45 28 0 EN 5 o aN So dn 946 0 0 0 3 is D a 160 x Figure 4 3 Connector Positions Gaisler August 2014 Rev 0 11 58 GAISLER GR712 Development Board User Manual Tours HHHH S60 S6y2780 Wd GR712 Evaluation Boa z m nni nmm ia Figure 4 4 GR712 Assembly Photo August 2014 Rev 0 11 Aeroflex Gaisler AB
11. 229 SWMX11 In RS422 RX 5 TCACT1 188 SWMX31 In 65422 RX 11 2 176 SWMX39 In 65422 RX 15 165 SWMX46 In 65422 19 TCACT4 143 SWMX57 In 65422 RX 21 TCRFAVLO 193 SWMX26 In RS422 RX 8 TCRFAVL1 183 SWMX34 In RS422 RX 12 TCRFAVL2 173 SWMX42 In RS422 RX 16 TCRFAVL3 160 SWMX51 In 65422 RX 20 TCRFAVL4 144 SWMX56 In 65422 RX 22 Table 2 5 List of TMTC Signals Aeroflex Gaisler August 2014 Rev 0 11 2 GAISLER User Manual 2 12 Serial Interface RS232 The GR712 BOARD provides RS232 interface circuits and connectors for two Serial interfaces with TXD RXD pins This interface shares the TXO RX0 TX1 RX1 pin pairs with the RS422 interface and therefore it is necessary to set jumpers JP1 and JP2 to select either RS422 Install jumpers 1 3 2 4 RS232 jumpers 3 5 and 4 6 Refer to Schematic RD 1 The front panel connector type for the UART interfaces is a Female D Sub 9 pin type with a standard pin out for serial links Gaisler August 2014 Rev 0 11 GAISLER User Manual SUB D 9 pin Female TXD GR712RC 55232 5232 DRIVER INTERFACE ASIC RECEIVERS RXD Figure 2 14 Serial interface 2 13 Debug Support Unit DSU Serial Interface The GR712 BOARD provides a interface for Debug and control of the processor by means of a host terminal via the DSU JTAG link t
12. G G P Ht H B B B B Use command grlib gt flash info sys Intel style 8 bit flash on D 31 24 Intel MT28F640J3 Manuf Device Device ID Oadcffffc6019e49 User ID 1x 8 Mbyte Vendor Gais Gais Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gais Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gais Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gais Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gais Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl Gaisl 8 Mbyte total 8 0x00000000 ler ler er er er er er er ler er er er er er er ler er er er er er er ler er er er er er er ler er er er er er er er er er Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc Researc to print a detailed report of T D O D DO 5 D D D n D PD D 2004 2010 Aeroflex Gaisler all rights reserved go to http www gaisler com attached cores Figure 3 1 GRMON Listing 1 info flash family 1 flash size 64 Mbit erase regions 1 erase blocks 64 Aeroflex Gaisler AB August 2014 Rev 0 11 GA
13. 3 3V SDDQM6 pulled high SDDQN7 pulled high DGND nc nc nc nc 3 3V nc nc nc nc DGND SDSCL pulled high 43 3V SODIMM socket J15 Pin out August 2014 Rev 0 11 GAISLER Gaisler FUNCTION ASIC pin 49 CONNECTOR PIN TXOP TX1P TX2P TX3P TX4P TX5P TX6P TX7P TX8P TX9P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GR712 Development Board User Manual FUNCTION TXON TX1N TX2N TX3N TX4N 5 TX6N TX7N TX8N TX9N Table 4 19 16 RS422 Transmitter Pairs FUNCTION ASIC pin CONNECTOR PIN TX10P TX11P TX12P TX13P TX14P TX15P TX16P TX17P TX18P TX19P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNCTION TX10N TX11N TX12N TX13N TX14N TX15N TX16N TX17N TX18N TX19N Table 4 20 J17 RS422 Transmitter Pairs FUNCTION ASIC pin CONNECTOR PIN RX2P RX3P RX4P RX5P RX6P RX7P RX8P RX9P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNCTION RXON RX1N RX2N RX3N RX4N RX5N RX6N RX7N RX8N RX9N Table 4 21 J18 RS422 Receiver Pairs FUNCTION ASIC pin CONNECTOR PIN RX10P RX11P R
14. 52 STCNPPS2N GPIO_40 STCNSYNC STCNSYNC GPIO_41 SPICLK SLO SLO SPICLK GPIO_42 SPIMOSI SLCLK SLCLK SPIMOSI GPIO_43 TCCLK3 GPIO_44 TCD3 GPIO_45 SDCAS SDCASN SDCASN SDCASN GPIO_46 SDRAS SDRASN SDRASN SDRASN GPIO_47 TCACT3 GPIO_48 SPIMISO TCRFAVL3 SLI SLI SPIMISO 49 SDWEN SDWEN SDWEN SDWEN GPIO_50 SDDQM 2 SDDQM 2 SDDQM 2 SDDQM 2 GPIO 51 SDDQM 3 SDDQM 3 SDDQM 3 SDDQM 3 GPIO 52 GPIO 53 TCRFAVL4 GPIO_54 I2CSDA TCCLK4 I2CSDA I2CSDA I2CSDA GPIO 55 I2CSCL TCD4 I2CSCL I2CSCL I2CSCL GPIO 56 CB 8 CB 8 CB 8 CB 8 GPIO 57 CB 9 CB 9 CB 9 CB 9 GPIO 58 CB 10 CB 10 CB 10 CB 10 GPIO 59 CB 11 CB 11 CB 11 CB 11 GPIO 60 CB 12 CB 12 CB 12 CB 12 GPIO 61 CB 13 CB 13 CB 13 CB 13 GPIO 62 CB 14 CB 14 CB 14 CB 14 GPIO 63 CB 15 CB 15 CB 15 CB 15 Figure 2 6 Switch Matrix and Interface Functions __ Gaisler August 2014 Rev 0 11 GAISLER User Manual As can be seen from Figure 2 6 five basic interface configurations are defined for the GR712RC device GEOCPU Processor for GEO applications CF1 TMTC Processor for TMTC applications CF2 LEOCPU Processor for LEO applications CF3 INSTR CTRL A Instrument Controller type 4 INSTR CTRLB Instrument Controller type B If not otherwise used can be defined as a standard general purpose for user defined use In order to be able to configure the GR712 BOARD
15. 64 pins General Purpose Port on 0 1 headers some shared with other functions 20 RS422 Transmit pairs on 0 1 headers 28 5422 Receive pairs 0 1 headers Additionally on board headers and components provide access to the following functions features Dual MIL STD 1553B communication interface 2 interface with on board Real Time Clock and user connections on 0 1 header SPI interface with on board Temperature measurement and user connections on 0 1 header Large number of header and jumper connections for configuration of the board Push Button for RESET LED indicators for POWER ERRORN WATCHDOG and PROM_BUSY References RD 1 GR712 BOARD_schematic pdf Schematic RD 2 GR712 BOARD assy drawing pdf Assembly Drawing RD 3 GR712RC Dual Core Leon3FT SparcV8 Processor Datasheet RD 4 GRT712RC Dual Core Leon3FT SparcV8 Processor User Manual Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual 1 3 1 4 RD 5 GR MEZZ Technical Note Technical Note about Mezzanine connectors Handling ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges ESD When handling or installing the unit observe appropriate precautions and ESD safe practices When not in use store the unit in an electrostatic protective container or bag When co
16. 8 No connect 4 No connect 9 No connect 5 GND Ground Table 4 3 lower connector UART 1 Serial Interface RS232 connections Pin Name Comment 1 No connect 6 GND Ground 2 1 1 Dominant Low 7 CAN1_H CAN Dominant High 3 GND Ground 8 No connect 4 No connect 9 5 CANSHD1 Shield Table 4 4 J2A upper connector CANBUS 1 interface connections Gaisler August 2014 Rev 0 11 42 GR712 Development Board GAISLER User Manual Pin Name Comment 1 No connect 6 Ground 2 1 Dominant Low 7 Dominant High 3 Ground 8 No connect 4 9 5 CANSHDO Shield Table 4 5 J2B lower connector CANBUS 0 interface connections Pin Name Comment 1 DINO Data In ve 6 DINO Data In ve 2 SINO Strobe In ve 7 SINO Strobe In ve 3 SHIELD Inner Shield 8 SOUTO Strobe Out ve 4 SOUTO Strobe Out ve DOUTO Data Out ve DOUTO Data Out ve Table 4 6 J3 SPW 0 interface connections Pin Name Comment 1 DIN1 Data In ve 6 DIN1 Data In ve 2 SIN1 Strobe In ve 7 SIN1 Strobe In ve 3 SHIELD Inner Shield 8 SOUT1 Strobe Out ve 4 SOUT1 Strobe Out ve 9 DOUT1 Data Out ve 5 DOUT1 Data Out ve Table 4 7 J4 SPW 1 interface connections
17. EROFLEX AISLER GR712 Development Board User Manual AEROFLEX GAISLER AB Rev 0 11 2014 08 08 GAISLER User Manual Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable However no responsibility is assumed by Aeroflex Gaisler AB for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Aeroflex Gaisler AB Aeroflex Gaisler AB tel 46 31 7758650 Kungsgatan 12 fax 46 31 421407 EROF LEX 411 19 G teborg sales gaisler com Sweden www aeroflex com gaisler GAISLER Copyright 2014 Aeroflex Gaisler All information is provided as is There is no warranty that it is correct or suitable for any purpose neither implicit nor explicit Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual TABLE OF CONTENTS 1 INTRODUCTION 7 1 1 OE RM 7 1 2 ECEE tT 8 1 29 Handlifig uni 9 1 4 9 ELECTRICAL DESIGN u L u a 10 2 1 GRV PRC ASIC ed ass 10 MEE ne 11 MEMON
18. 50 000MHz 5 OSC_SPW DIL8 socket for user installed SPW Clock Oscillator 3 3V Y1 XTAL_RTC 32 768 2 crystal for 2 Real Time Clock Table 4 33 List and definition of Oscillators Name Function Description D1 POWER 3 3V Power indicator D2 ERRORN Leon processor in ERROR mode D3 PROM_BUSY Prom Write Erase in Progress D4 WDOG Watchdog indicator Table 4 34 List and definition of PCB mounted LED s Name Function Description 51 RESET Push button RESET switch S2 Not used Not used Table 4 35 List and definition of Switches Gaisler August 2014 Rev 0 11 53 GR712 Development Board User Manual Type Description 2X3 pin 0 1 Header Connects signals to RS422 or RS232 circuits 2X3 pin 0 1 Header Connects UART1 signals to RS422 or RS232 circuits 2X6 2mm Header Configuration jumper for SWMX3 pin 2X6 2mm Header Configuration jumper for SWMXA pin 2X6 2mm Header Configuration jumper for SWMXS pin 2X6 2mm Header Configuration jumper for SWMX6 pin 2X6 2mm Header Configuration jumper for SWMX7 pin 2X6 2mm Header Configuration jumper for SWMX8 2X6 2mm Header Configuration jumper for SWMX9 2X6 2mm Header Configuration jumper for SWMX10 pin 2X6 2mm Header Configuration jumper for 5 11 2X6 2mm Header Configuration jumper for SWMX12 pin 2X6 2mm Header Configu
19. DGN DGN DGN DGN DGN DGN Q OUD D D Table 4 25 J22 PIO Header Pin out FUNCTION ASIC pin CONNECTOR PIN GPIO20 1 2 GPIO21 3 4 GPIO22 5 6 GPIO23 7 8 GPIO24 9 10 GPIO25 11 12 GPIO26 13 14 GPIO27 15 16 GPIO28 17 18 GPIO29 19 20 FUNCTION DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN Q UD UD Table 4 26 J23 Header Pin out August 2014 Rev 0 11 GAISLER Aeroflex Gaisler AB 51 FUNCTION ASIC pin CONNECTOR PIN GPIO30 1 2 GPIO31 3 4 GPIO32 5 6 GPIO33 7 8 GPIO34 9 10 GPIO35 11 12 GPIO36 13 14 GPIO37 15 16 GPIO38 17 18 GPIO39 19 20 FUNCTION DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN Table 4 27 J24 PIO Header Pin out FUNCTION ASIC pin CONNECTOR PIN GPIO40 1 2 GP1041 3 4 GPIO42 5 6 GPIO43 7 8 44 9 10 GPIO45 11 12 GPIO46 13 14 GPIO47 15 16 GPIO48 17 18 GPIO49 19 20 FUNCTION DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN Table 4 28 J25 PIO Header Pin out FUNCTION ASIC pin CONNECTOR PIN GPIO50 1 2 GP1051 3 4 GPIO52 5 6 GPIO53 7 8 GPIO54 9 10 GPIO55 11 12 GPIO56 13 14 G
20. SPW CLK DIL8 SOCKET Ethernet 50 MHz PHY ETH_RMIICLK SMD 24 MHz 1553_CK Figure 2 16 Clock Distribution Scheme 2 14 2 SPW CLK The SPWCLK can be derived from either the MAIN CLK a separate socketed on board crystal oscillator or can be injected on a SMA coaxial connector on the board 2 14 3 Ethernet Clock A dedicated 50MHz SMD oscillator is provided for the Ethernet Controller and PHY circuit see section 2 16 2 14 4 MIL STD 1553 Interface Clock A dedicated 24 0MHz SMD oscillator is provided for the MIL STD 1553 interface logic in the ASIC Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual 2 15 Power Supply and Voltage Regulation The board operates from a single 5V DC power supply input On board regulators generate the following voltages 3 3V for the GR712RC I O voltage memory chip and other peripherals 1 8V for GR712RC Vcore voltage REGULATOR Vcore 1 8V for GR712 core REGULATOR JP80 3V3asic 3 3V for GR712 3 3V EXTERNAL POWER J14 POWER SUPPLY REGULATED 2 1mm JACK 5V gt 1A CENTRE PIN VE Figure 2 17 Power Regulation Configuration Both the voltages 5V and 3 3V are provided to the memory expansion interface making feasible that user defined mezzanine boards can use these voltages The Jumpers JP80 and JP81 provide Current measurement points for monitoring and measurem
21. and will not operate when the GR712RC is clocked at 96 MHz using the 2x48 MHz DLL mode To operate the SDRAM run the device at 48 MHz from X1 or at 80 MHz using the supplied 80 MHz oscillator in X2 2 3 4 Expansion Connector To make it feasible for users to define peripherals mapped in the processor I O space and implement mezzanine boards which could be connected to this Development Board in a similar manner to the other GR Development Boards the memory bus signals of the GR712 processor are connected to a 120 pin AMP connector AMP 5 177984 5 J9 and 60 pin connector 5 177984 2 J11 Table 4 12 and Table 4 14 list the signals and their pin numbers for these connectors Figure 2 5 shows the pin numbering scheme as implemented on the expansion connector 5 HDR2X10 Tdi 6 t s 31 w rn CONNECTOR 60X2 CONNECTOR 30x2 1 w PIN1 60 PIN1 30 Figure 2 5 Mezzanine Connector Pin Number Ordering Please note that this pin ordering does not match exactly the pin ordering which you will find on the Tyco part datasheets for the Mezzanine board mating connectors The reason for this is explained in more detail in the Technical Note RD 5 Therefore please take care when designing your own mezzanine boards to take account of this pin ordering If there is any confusion you have any
22. is given in the GRMON Users Manual and associated documentation Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER 37 GR712 Development Board User Manual richard hp2510p sudo grmon grmon linux ftdi ramws 1 u GRMON LEON debug monitor v1 1 44 professional version Copyright C For latest updates Comments or bug reports to support gaisler com This debug version will expire on 1 8 2011 JTAG chain GR712RC Device ID 0 712 GRLIB build version 3696 initialising detected frequency Component SPARC V8 Processor SPARC V8 Processor HB Debug JTAG TAP R Ethernet MAC atCAN controller RSPW2 Spacewire RSPW2 Spacewire RSPW2 Spacewire RSPW2 Spacewire RSPW2 Spacewire Link RSPW2 Spacewire Link ctel MIL STD 1553 BRM CSDS Telecommand Decoder CSDS Telemetry Encoder LINK master Memory Controller HB APB Bridge EON3 Debug Support Unit HB APB Bridge OC CAN controller AHB static ram Generic APB UART Multi processor Interrupt Ctrl Modular Timer Unit SPI Controller CAN bus multiplexer General purpose registers ASCS Master General purpose port General purpose port AMBA Wrapper for OC I2C master Clock gating unit AHB status register Generic APB UART Generic APB UART Generic APB UART Generic APB UART Generic APB UART Modular Timer Unit Link Link Link Link 3 5 uy G G G gt Gy G
23. when defined for TMTC ASCS16 SLNK and SATCAN functionality RS422 signal levels are also required on a number of interfaces The board therefore provides transmitter and receiver circuits for 20 RS422 Transmitter Pairs 28 RS422 Receiver pairs Since defining individual connector types for each combination of interfaces while maintaining flexibility would lead to unmanageable complexity on the board the RS422 signals are instead simply routed to a set of standard 0 1 pin headers If the connector type and pin out interfaces is known an appropriate wire harness can be easily defined to accommodate the desired connector types 2 7 1 RS422 Transmitter Circuits Each transmitter pair is connected to an 3 3V RS422 Transmitter circuit as shown in Figure 2 12 Some of the TMTC interface types require series 100 Ohm resistors for source series termination of the interface This can be provided on an individual basis for the transmitter pairs by means of series resistors installed on the board close to the transmitter circuits If source series termination is not required then zero ohm resistors should be installed for the RS422 transmitter interfaces 3V3 oO Rd 1 2 117 IO 14 6 06 a 3 R118 OR TXON T 1 6 R119 OR TXIP SUTE 5 8120 OR TXIN TX2 oore OR TOP Sure D RIZ OR DON 15 EN 4 Rc OR TP EM ABEN GUTD 222 124 08 C DEN 6 R88 U
24. 4 22 J19 RS422 Receiver 0 0 10 nene nne 43 Table 4 23 J20 RS422 Receiver 0 2 1 01 44 Table 4 24 J21 PIO Header Pin 0 0 0 0 11 a rennen nennen 44 Table 4 25 J22 PIO Header Pin 0 0 0 0 a 44 Table 4 26 J23 PIO Header Pin 0 0 0 4 m m enne nennen rennen nennen 44 Table 4 27 J24 PIO Header Pin 0 0 1 1 0 mmm nennen nnn innen 45 Table 4 28 J25 PIO Header Pin 02 2 010 4 em nennen rennen nennen 45 Table 4 29 J26 PIO Header Pin 0 1 1 2 0 emen nennen nennen 45 Table 4 30 J27 PIO Header Pin 0 1 0 1 0 45 Table 4 31 J30 POWER External Power 46 Table 4 32 J31 SPW 400 0 0 a 46 Table 4 33 List and definition of 2 1 40 enne 46 Table 4 34 List and definition o
25. Gaisler August 2014 Rev 0 11 5 GAISLER User Manual Pin Name Comment 1 DIN2 Data In ve 6 DIN2 Data In ve 2 SIN2 Strobe In ve 7 SIN2 Strobe In ve 3 SHIELD Inner Shield 8 SOUT2 Strobe Out ve 4 SOUT2 Strobe Out ve 9 DOUT2 Data Out ve 5 DOUT2 Data Out ve Table 4 8 J5 SPW 2 interface connections Pin Name Comment 1 DIN3 Data In ve 6 DIN3 Data In ve 2 SIN3 Strobe In ve 7 SIN3 Strobe In ve 3 SHIELD Inner Shield 8 SOUT3 Strobe Out ve 4 SOUT3 Strobe Out ve 9 DOUT3 Data Out ve 5 DOUT3 Data Out ve Table 4 9 46 SPW 3 interface connections Pin Name Comment 1 DIN2 Data In ve 6 DIN4 Data In ve 2 SIN4 Strobe In ve 7 SIN4 Strobe In ve 3 SHIELD Inner Shield 8 SOUT4 Strobe Out ve 4 SOUT4 Strobe Out ve 9 DOUT4 Data Out ve 5 DOUT4 Data Out ve Table 4 10 7 SPW 4 interface connections Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual Pin Name Comment 1 DIN5 Data In ve 6 DIN5 Data In ve 2 SIN5 Strobe In ve 7 SIN5 Strobe In ve 3 SHIELD Inner Shield 8 SOUT5 Strobe Out ve 4 SOUT5 Strobe Out ve 9 DOUT5 Data Out ve 5 DOUT5 Data Out ve Table 4 11 J8 SPW 5 interface connections Aeroflex Gaisler AB August 2014 Rev
26. Generic UART ver 0x1 17 apb 80100100 80100200 baud rate 3846 02 01 00c Gaisler Research Generic APB UART ver 0x1 irg 18 apb 80100200 80100300 baud rate 3846 03 01 00c Gaisler Research Generic APB UART ver 0x1 irg 19 apb 80100300 80100400 baud rate 3846 04 01 00c Gaisler Research Generic APB UART ver 0x1 irq 20 80100400 80100500 baud rate 3846 05 01 00c Gaisler Research Generic APB UART ver 0x1 irg 21 apb 80100500 80100600 baud rate 3846 06 01 038 Gaisler Research Modular Timer Unit ver 0x1 7 apb 80100600 80100700 8 bit scaler 2 32 bit timers divisor 48 grlib gt lo Desktop gr test leon3 samples stanford section text at 0x40000000 size 54288 bytes section data at 0x4000d410 size 2080 bytes total size 56368 bytes read 278 symbols entry point 0x40000000 grlib gt run Starting Perm Towers Queen 50 50 1 Nonfloating point composite is Floating point composit 762 6 kbit s 5 Intmm Mm Puzzle Quick Bubble z 66 850 183 38 111 e is 744 Program exited normally grlib Aeroflex Gaisler AB Figure 3 3 GRMON Listing 3 FFT 867 Tree 217 August 2014 Rev 0 11 GAISLER GR712 Development Board User Manual 4 INTERFACES AND CONFIGURATION 4 1 List of Front Back Panel Connectors Name Function T
27. Pins for external BREAK switch JP87 DLL BP 1X2 pin 0 1 Header Install jumper to Bypass internal PLL circuit JP88 SPW OSC 1X2 pin 0 1 Header Connects also as SPW JP89 FP LEDS 4x2 pin 0 1 Header Header to connect to front panel LED s Table 4 38 List and definition of PCB Jumpers part 3 for details refer to schematic RD 1 Aeroflex Gaisler August 2014 Rev 0 11 GAISLER User Manual
28. board SPI circuit Table 4 37 List and definition of PCB Jumpers part 2 for details refer to schematic RD 1 Aeroflex Gaisler AB August 2014 Rev 0 11 55 GR712 Development Board GAISLER User Manual Name Function Type Description JP72 BUSO 1X2 pin 0 1 Header Install for MIL STD 1553A direct coupling JP73 BUSOB 1X2 pin 0 1 Header Install for MIL STD 1553A direct coupling JP74 BUS1 1X2 pin 0 1 Header Install for MIL STD 1553A direct coupling JP75 BUS1B 1X2 pin 0 1 Header Install for MIL STD 1553A direct coupling JP76 RAM_BANK 4x2 pin 0 1 Header Header for configuration of ROM RAM bank select JP77 PROM_WR 1X2 pin 0 1 Header Install to Disable PROM writing JP78 CAN_TERMO 2x2 pin 0 1 Header Header for configuration of Termination of CANO i f JP79 CAN TERM1 2x2 pin 0 1 Header Header for configuration of Termination of JP80 I3V3 2 pin 0 1 Header Measure point for 3 3V current Link normally installed JP81 I1V8 2 pin 0 1 Header Measure point for 1 8V current Link normally installed JP82 JP RESET 1X2 pin 0 1 Header Pins for external RESET switch JP83 WD EN 1X2 pin 0 1 Header Jumper to enable Watchdog to cause board reset JP84 CLK CONFIG 1X3 pin 0 1 Header Connects either X1 to X2 oscillator to Main oscillator JP85 PROM EDAC 1X2 pin 0 1 Header Install to pull pin HIGH to enable PROM EDAC JP86 JP BREAK 1X2 pin 0 1 Header
29. doubts please do not hesitate to contact info pender ch Additional dimensional data or Gerber layout information can be provided if required to aid in the layout of the User s mezzanine board Switch Matrix for I O The programmable switch matrix inside the GR712RC device allows the same pin to be used for different interface functions Figure 2 6 shows the multiple interface functions which are assigned to the Switch Matrix I O pins on the GR712RC device Different interface types are grouped and highlighted by colour For the definition and explanation of the pin names please refer to the Data Sheet for the GR712RC Device RD 3 Aeroflex Gaisler AB August 2014 Rev 0 11 15 GR712 Development Board GAISLER User Manual JUMPERPOS 12 34 56 D 7 8 9 10 F 11 12 CFO 2 CF4 GPIO GEO CPU TM TC LEO CPU STRCTLA INSTRCTLB U1B UART TX0 UART TX0 UART TX0 UART TX0 UART TXO UART_RXO UART UART UART RXO 2 UART TX1 UART TX1 UART TX UART TX1 UART TX1 1 GPIO 0 UART_RX1 UART RX1 UART RX1 UART 1 UART GPIO 1 UART 2 UART 2 UART TX2 UART TX2 UART TX2 GPIO 2 2 UART RX2 UART RX2 UART RX2 UART RX2 GPIO 3 UART TX3 UART TX3 UART TX3 UART TX3 UART TX3 GPIO 4 UART RX3 UART RX3 UART RX3 UART RX3 UART RX3 GPIO 5 UART 4 TMDO UART TX4 UART TX4 TX4 GPIO 6 UART RX4 TMCLKI UART RX4 UAR
30. easy connection to ribbon cable or other external interfaces If defined as inputs the GPIO will have a default value of 1 high due to the Pull up resistor but can be set to low by inserting a jumper over the corresponding Header pins Note that GPIO 31 0 correspond to the GR712RC pin function GPIO1 31 0 GPIO 63 32 correspond to the GR712RC pin function GPIO2 31 0 2 18 2 Reset Circuit and Button standard Processor Power Supervisory circuit TPS3705 or equivalent is provided on the Board to provide monitoring of the 3 3V power supply rail and to generate a clean reset signal at power up of the Unit To provide a manual reset of the board a miniature push button switch is provided on the Main PCB for the control Additionally connections are provided to an additional off board push button RESET switch if this is required 2 18 3 Watchdog The GR712RC ASIC includes a Watchdog timer function which can be used for the purpose of generating a system reset in the event of a software malfunction or crash On this development board the WDOGN signal is connected as shown in the Figure 2 21 to the Processor Supervisory circuit To utilise the Watchdog feature it is necessary to appropriately set up and enable the Watchdog timer Please consult the GR712RC User Manual RD 4 for the correct register locations and details Gaisler August 2014 Rev 0 11 GAISLER U
31. functions This board therefore has a large number of configuration features in order to be able to exercise and configure the functions of the device Figure 1 1 GR712 Development Board Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual 1 2 The PCB contains the following main items as detailed in section 2 of this document GR712RC ASIC Memory SRAM 80 Mbit 1 bank x 2Mword x 40 bit typ 10ns optional second bank is not fitted as standard e SDRAM SODIMM socket up to 64Mword x 48 bit with 512Mbyte module e FLASH 64Mbit 8M x 8 bit typ 90ns additional memory options possible via memory expansion connector Power Reset Clock and Auxiliary circuits Interface circuits required for the features listed below The interface connectors on the Front edge of the board provide Two Serial UART interface RS232 with D9 Sub female connectors Ethernet 10 100Mbit RMII interface with RJ45 jack e DSU interface Two CAN bus interfaces ISO 11898 with D9 Sub male connectors Two dedicated Spacewire interfaces MDM9S connectors Four optional Spacewire interfaces MDM9S connectors To enable convenient connection to the interfaces the connector types and pin outs are compatible with the standard connector types for these types of interfaces The interface connectors on the Back edge of the board provide 5V input power connector
32. perform software download and debugging on the processor a link from the Host computer to the DSU interface of the board is necessary A connection to the DSU of the board can be made using a JTAG cable from the Host PC to the JTAG connector on the front of the PCB To perform program download and software debugging on the hardware it is necessary to use the Gaisler Research GRMON debugging software installed on a host PC as represented in Figure 2 15 Note that it is necessary to use the PRO version of GRMON as the GR712RC ASIC incorporates FT features It is not possible to use evaluation version of GRMON with this ASIC Please refer to the GRMON documentation for the installation of the software on the host PC Linux or Windows and for the installation of the associated hardware dongle Starting GRMON with the command grmon ftdi freq 48 will establish a link to the DSU and will initialise the processor registers and timers In the example shown in Figure 3 1 a connection is being made with GRMON over the JTAG interface Where 48 is is the clock frequency of the main processor oscillator Typing the command flash will reported the detected Flash Prom memory configuration and info sys will provide more information on the processors registers and internal cores as shown in Figure 3 3 Program download and debugging can be performed in the usual manner More information on the usage commands and debugging features of GRMON
33. 0 11 GR712 Development Board GAISLER User Manual FUNCTION ASIC pin CONNECTORPIN ASIC pin FUNCTION DGND 1 120 DGND 2 119 5V DGND 3 118 DGND 12V 4 117 12V DGND 5 116 DGND 12V 6 115 12V DGND 7 114 DGND D15 40 8 113 16 D31 D7 52 9 112 26 D23 3 3V 10 111 3 3V DGND 11 110 DGND D14 41 12 109 030 06 53 13 108 27 022 013 42 14 107 20 029 05 54 15 106 32 021 012 43 16 105 21 028 04 55 17 104 33 020 011 44 18 103 22 027 03 56 19 102 34 019 3 3V 20 101 3 3V DGND 21 100 DGND D10 45 22 99 D26 D2 57 23 98 35 D18 09 46 24 97 24 025 D1 58 25 96 36 D17 D8 49 26 95 25 24 DO 59 27 94 37 D16 DGND 28 93 DGND DGND 29 92 DGND 3 3V 30 91 3 3V DGND 31 90 DGND 22 87 32 89 85 A23 A20 92 33 88 88 A21 18 97 34 87 95 19 16 98 35 86 99 17 A14 89 36 85 96 A15 A12 82 37 84 86 A13 A10 80 38 83 81 11 74 39 82 77 9 3 3V 40 81 3 3V DGND 41 80 DGND A6 72 42 79 73 AT 4 68 43 78 71 5 A2 64 44 77 65 A3 AO 62 45 76 63 Al WRITEN 107 46 75 120 READ OEN 126 47 74 108 IOSN ROMSNO 101 48 73 ROMSN1 3 3V 49 72 3 3V 3 3V 50 71 3 3V DGND 51 70 DGND 3 3V 52 69 111 RAMOEN 3 3V 53 68 111 RAMOEN RAMSN1 110 54 67 111 RAMOEN RAMSNO 109 55 66 111 RAMOEN RWEN 112 56 65 112 RWEN RWEN 112 57 64 112 RWEN BRDYN 113 58 63 118 BEXCN RESETN 59 62 CLK DGND 60 61 DGND Table 4 12 Expansion connector J9 Pin out see also section 2 3 4 Aeroflex Gaisler AB August
34. 1 Header Pin connections for 5422 RX pairs 20 to 29 J21 GPIO 9 0 20 pin 0 1 Header Pin connections for PIO signals 0 to 9 J22 GPIO 19 10 20 pin 0 1 Header Pin connections for PIO signals 10 to 19 J23 GPIO 29 20 20 pin 0 1 Header Pin connections for PIO signals 20 to 29 J24 GPIO 39 30 20 pin 0 1 Header Pin connections for PIO signals 30 to 39 J25 GPIO 49 40 20 pin 0 1 Header Pin connections for PIO signals 40 to 49 J26 GPIO 59 50 20 pin 0 1 Header Pin connections for PIO signals 50 to 59 J27 GPIO 66 60 20 pin 0 1 Header Pin connections for PIO signals 60 to 66 J28 I2C USER 12 pin 0 1 Header Pin connections for User I2C interface J29 SPI USER 4 pin 0 1 Header Pin connections for User SPI interface J30 POWER IN Mate N Lok 4pin Alternative power input for 4 pin IDE style connector J31 SPW_CLK SMA SPW Clock Monitor or Injection Table 4 1 List of Connectors Aeroflex Gaisler AB August 2014 Rev 0 11 41 GR712 Development Board GAISLER User Manual Pin Name Comment 1 No connect 6 No connect 2 TXD 0 Transmit pin 7 No connect 3 RXD 0 Receive pin 8 No connect 4 No connect 9 No connect 5 GND Ground Table 4 2 J1A upper connector 0 Serial Interface RS232 connections Pin Name Comment 1 No connect 6 No connect 2 TXD 1 Transmit pin 7 No connect 3 RXD 1 Receive pin
35. 195 3 45 195 0 rir 5 L qe 2724273 338 1829 56 T 5 T 4 33 55 B 8 E E z 5 gt 535 5 166 0 5 5 mx LI 3 3 5 BERE En d ETSI to 18 ki 5 148 5 2 5 E 5 88 50 O82 ORO OO xs m TBD MHz 8 5 5 5 s s s e s E El D amp O CEO ORO CRO CR CRO CRO 5 ue 3 8 8 8 8 K z 133 5 e cm E cur ETT eT eT ele eX x CAS RE RCD D Cep 7 17 val lava hovel laa Te eral sls sisi sus sis ss sia a 8 7 EALAR CE DESC axe led 118 5 e CEL Ve PCr Te 7 7 _ 4 nonae horde 110 90 7 HOR2X6 P38 HOR2X6 8 25 MOMS AAN o ie ess horaxe JPq0 esos 2 ORO RB P ORO a ORO e TORO fede N 11 us oes BBE 2616 5 88 5 8 epe DGIO aie OO QC 8
36. 2 g8 20 RP39 3 s o 2 of 5 8 2 E ss gt e af 2S0 U CE GEE eee m x sor zi L3 PB SWITcI PB SWIToI e J9 CONNECTOR 60X2 5 Figure 4 2 Assembly View Gaisler August 2014 Rev 0 11 GAISLER User Manual e gt 1 e 42 5 94 0 16 43 ke gt 205 35 33 nap HORIS iom 199 80 4 Ge Ja z
37. 2014 Rev 0 11 GAISLER User Manual Pin Name Comment 1 TPFOP Output ve 2 TPFON Output ve 3 TPFIP Input ve 4 TPFOC Output centre tap 5 No connect 6 TPFIN Input ve 7 TPFIC Input centre tap 8 No connect Table 4 13 J10 RJ45 ETHERNET Connector FUNCTION ASIC pin CONNECTOR PIN FUNCTION DGND 1 60 CB6 5 2 59 141 CB7 CB4 9 3 58 8 CB5 CB2 11 4 57 10 CB3 15 5 56 12 6 55 7 54 8 53 9 52 DGND 10 51 DGND 3 3V 11 50 3 3V 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 DGND 20 41 DGND 3 3V 21 40 3 3V 22 39 23 38 24 37 25 36 26 35 27 34 28 33 29 32 DGND 30 31 DGND Table 4 14 Expansion connector J11 Pin out see also section 2 3 4 Gaisler August 2014 Rev 0 11 GAISLER User Manual Pin Name Comment 1 VDD 5V from external device 2 DM Data Minus 3 DP Data Plus 4 DGND Ground Table 4 15 J12 ASIC JTAG Connector over USB Pin Name Comment 1 BUS 0 BUS 0 positive 6 GND Ground 2 BUS 0B BUS 0 negative 7 No connect 3 No connect 8 No connect 4 BUS 1 BUS 1 positive 9 GND Ground 5 BUS 1B BUS 1 negative Table 4 16 J13 Dual MIL STD 1553 interface connections Pin Name Comment 45V Inner Pin 5V typically TBD VE GND Outer Pin Return T
38. 30 22k DS34LV87 RS422 3V3 Figure 2 12 RS422 TX configuration 2 7 2 RS422 Receiver Circuits Each receiver pair is connected to an 3 3V RS422 Receiver circuit as shown in Figure 2 13 In the default configuration none of the receiver pairs are provided with any form of termination However this can be added on an individual basis Either an AC or simple resistive termination can be installed Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual U35 DS34LV86 RS422 3 OUT RX1 3 MEM X 51 Gute Ro 11 4 ABEN 12 4 CIDEN R133 3V3 Figure 2 13 RS422 Receiver Configuration 2 8 UART s The GR712RC ASIC incorporates a IP core which implement standard serial UART functionality The interface to this core consists of the following as listed in Table 2 2 These signals are defined to have RS422 voltage levels and share connector as shown in the last column of the table Name Pin Direction Function UARTTXO 41 SWMXO Transmit 0 65422 0 UARTTX1 3 SWMX2 Out Transmit 1 65422 1 UARTTX2 21 SWMX4 Out Transmit 2 65422 TX 2 UARTTX3 1 SWMX6 Out Transmit 3 RS422 TX 3 UARTTX4 240 SWMX8 Transmit 4 65422 TX 4 UARTTX5 239 SWMX10 Out Transmit 5 RS422 TX 5 UARTRXO 238 SWMX1 In Receive 0 RS422 RX 0 UARTRX1 233 SWMX3 In Receive 1 RS422 RX 1 UARTRX2 232 SWMX
39. 5 2 65422 RX 2 UARTRX3 231 SWMX7 In Receive 3 RS422 RX 3 UARTRX4 230 SWMX9 In Receive 4 RS422 RX 4 UARTRX5 229 SWMX11 In Receive 5 65422 RX 5 Table 2 2 List of UART Signals 2 9 ASCS16 The GR712RC ASIC incorporates a IP core which implements ASCS16 STR functionality The interface to this core consists of the following as listed in Table 2 3 These signals are defined to have RS422 voltage levels and share connector pin as shown in the last column of the table Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual Name Pin Direction Function Shares A16DASA 226 SWMX14 In 85422 6 A16DASB 225 SWMX15 In RS422 RX 7 A16MCS 179 SWMX36 Out RS422 TX 8 A16HS 178 SWMX37 Out RS422 TX 9 A16DCS 175 SWMX40 5422 10 A16MAS 174 1 SWMX41 Out RS422 TX 11 A16ETR 202 SWMX21 Out 5422 7 Table 2 3 List of ASCS16 Signals 2 10 SLINK The GR712RC ASIC incorporates a IP core which implements SLINK 6 2 serial port functionality The interface to this core consists of the following as listed in Table 2 4 These signals are defined to have RS422 voltage levels and share connector as shown in the last column of the table Name Pin Direction Function Shares SLI 160 SWMX51 In RS422 RX 20 SLO 169 SWMX44 Out RS422 TX 12 SLSYNC 203 SWMX20 R
40. 712 Development Board GAISLER User Manual LIST OF TABLES Table 2 1 SpaceWire Clock Divisor Resistors 18 Table 2 2 List of UART 1 soiree Rd a UT 20 Table 2 3 20 Table 2 4 List or SLINK Sins u Ee pepe eo eda Maa 21 Table 2 5 List of TMTC Signals 21 Table 3 1 Default Status 29 Table 4 1 List of 1 enm anne 34 Table 4 2 J1A upper connector 0 Serial Interface RS232 connections 35 Table 4 3 J1B lower connector UART 1 Serial Interface RS232 connections 35 Table 4 4 J2A upper connector CANBUS 1 interface 35 Table 4 5 J2B lower connector CANBUS O interface 36 Table 4 6 J3 SPW 0 interface connections 200 201 eene 36 Table 4 7 SPW 1 interface 1 11 2 00 0 rennen 36 Table 4 8 45 SPW 2 interface connections 10 emere rne nnne 37 Table 4 9 J6 SPW 3 interface
41. ISLER 38 write buffer region 0 32 bytes 64 blocks of 128 Kbytes grlib gt info sys 00 01 053 Gaisler Research ahb master 0 Gaisler Research ahb master 1 Gaisler Research ahb master 2 Gaisler Research GR Ethernet MAC ahb master 3 irq 14 80000e00 80000f00 Gaisler Research SatCAN controller master 4 irg 14 ahb fff20000 20100 Gaisler Research GRSPW2 Spacewire master 5 irq 22 80100800 80100900 Gaisler Research GRSPW2 Spacewire master 6 irq 23 80100900 80100a00 Gaisler Research GRSPW2 Spacewire master 7 irq 24 80100 00 80100500 029 Gaisler Research GRSPW2 Spacewire master 8 irq 25 80100b00 80100c00 Gaisler Research GRSPW2 Spacewire master 9 irq 26 80100c00 80100d00 029 Gaisler Research GRSPW2 Spacewire master 10 irq 27 80100d00 80100e00 er Research Actel MIL STD 1553 BRM ver 0x0 master 11 irg 14 ahb fff00000 01000 Gaisler Research CCSDS Telecommand Decoder ahb master 12 irq 14 ahb fff10000 fff10100 Gaisler Research CCSDS Telemetry Encoder ahb master 13 irq 29 apb 80000500 80000c00 Gaisler Research SLINK master ahb master 14 irq 13 apb 80000800 80000900 Gaisler Research FT Memory Controller ahb 00000000 20000000 ahb 20000000 40000000 ahb 40000000 80000000 apb 80000000 80000100 8 bit prom 8 0x00000000 32 bit static ram 1 8192 kbyte 8 0x40000000 Gaisler Research AHB APB Bridge ver 0x0 ahb 80000000 80100000 Gaisler Research LEON3 De
42. MMU Bl k 10 100 E 7 AMBA AHB AMBA APB Memory Controller Encoder amp Decoder Figure 2 1 GR712RC ASIC Block Diagram The GR712RC ASIC is packaged in a 240 pin 0 5mm pitch Ceramic Quad Flatpack and is soldered on to the PCB Details of the interfaces operation and programming of the GR712RC ASIC is given in the GR712 Datasheet RD 3 and User Manual RD 4 Figure 2 2 GR712RC ASIC Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual 2 2 Block Diagram The GR712 BOARD provides the electrical functions and interfaces as represented in the block diagram Figure 2 3 POWER GR712RC ASIC PROGRAMMABLE SWITCH MATRIX SDRAM SODIMM CONFIGURATION JUMPERS JTAG MIL STD RS422 SPI amp UART GPIO DSU SPW 4553 2 NETPHY RS232 wW YYY wW MEMORY EXPANSION JTAG 2x 4x 2x 2x TMTC 10 100 Mb 2xRS232 64x DSU SPW SPW CAN MIL 1553 SLINK ETHERNET UART GPIO ASCS16 SATCAN Figure 2 3 Block Diagram of GR712 BOARD The Main PCB is of standard Double Eurocard format 233 35 x 160mm and can be used stand alone on the bench top simply using an external 5V power supply The board is compatible with mounting in a 6U Compact PCI rack if a suitable front panel is mounted 2 3 Memory The memory configuration installed on the board is shown in the figure below comprising of 80Mb
43. PIO57 15 16 GPIO58 17 18 GPIO59 19 20 FUNCTION DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN Table 4 29 J26 PIO Header Pin out FUNCTION ASIC CONNECTOR PIN GPIO60 1 mH 2 GPIO61 3 4 GPIO62 5 6 GPIO63 7 8 GPIO64 9 10 GPIO65 11 12 GPIO66 13 14 nc 15 16 nc 17 18 nc 19 20 DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN Table 4 30 J27 Header Pin out oO D OU DU OUD UU Oo oo D OUD oO UD uu FUNCTION oOo D D UD GR712 Development Board User Manual August 2014 Rev 0 11 EROFLEX 52 GR712 Development Board GAISLER User Manual Pin Name Comment 1 5V 5V typically TBD 2 GND Ground 12V 12V Not used 4 GND Ground Table 4 31 J30 POWER External Power Connector Pin Name Comment centre SPWCLK Clock outer GND Ground Table 4 32 J31 SPW Clock 4 2 List of Oscillators Switches and LED s Name Function Description x1 OSC_MAIN Oscillator for main ASIC clock SMD type 3 3V 48MHz X2 OSC_USER Alternative User oscillator for main ASIC clock DIL8 socket 3 3V X3 OSC_1553 Oscillator for 1553 interface functions 24 0MHz X4 OSC_ETH Oscillator for Ethernet PHY transceiver SMD type 3 3V
44. S422 6 SLCLK 166 SWMX45 Out 65422 13 Table 2 4 List of SLINK Signals 2 11 TMTC GR712RC ASIC incorporates IP core which implements TMTC functionality The interface to this core consists of the following as listed in Table 2 5 These signals are defined to RS422 voltage levels and share connector pin as shown in the last column of the table Aeroflex Gaisler AB August 2014 Rev 0 11 EROFLEX 24 GR712 Development Board GAISLER User Manual Name Pin Direction Function Shares TMDO 232 SWMX8 Out RS422 TX 4 TMCLKO 230 SWMX10 Out RS422 TX 5 TMCLKI 231 SWMX9 In 65422 RX 4 Gaisler August 2014 Rev 0 11 EROFLEX 25 GR712 Development Board GAISLER User Manual Name Pin Direction Function Shares TCDO 225 SWMX15 In 65422 RX 7 TCD1 189 SWMX30 In RS422 RX 10 TCD2 177 SWMX38 In 65422 RX 14 TCD3 164 SWMX47 In 65422 RX 18 TCD4 142 1 SWMX58 In 65422 RX 24 TCCLKO 226 SWMX14 In 65422 RX 6 TCCLK1 192 SWMX27 65422 9 TCCLK2 182 SWMX35 In 65422 13 Gaisler August 2014 Rev 0 11 26 GR712 Development Board GAISLER User Manual Name Pin Direction Function Shares TCCLK3 165 SWMX46 In 65422 RX 17 TCCLK4 143 SWMX57 In 65422 RX 23
45. T UART_RX4 GPIO 7 UART_TX5 TMCLKO UART TX5 UART TX5 UART TX5 GPIO 8 UART RX5 TCACTO UART RX5 RX5 UART RX5 GPIO 9 SPWTXS 4 SDCSN 0 5 5 SDCSN 0 GPIO 10 SPWTXD 4 SDCSN 1 SDCSN i SDCSN SDCSN 1 GPIO 11 SPWRXS 4 TCCLKO A16DASA GPIO 12 SPWRXD 4 TCDO A16DASB GPIO 13 SPWTXS 2 SPWTXS 2 CANTXA SPWTXS 2 GPIO 14 SPWTXD 2 SPWTXD 2 CANTXB SPWTXD 2 GPIO 15 SPWRXS 2 SPWRXS 2 CANRXA SPWRXS_2 GPIO_16 SPWRXD_2 SPWRXD_2 CANRXB CANRXB SPWRXD_2 17 SPWTXS SPWTXS 3 SLSYNC SLSYNC SPWTXS_3 18 SPWTXD 3 SPWTXD 3 A16ETR SPWTXD 3 GPIO 19 SPWRXS 3 SPWRXS 3 SPWRXS 3 GPIO 20 SPWRXD 3 SPWRXD 3 SPWRXD 3 GPIO 21 SPWTXD 5 SDDQM 0 SDDOM 0 SDDQM 0 SDDOM 0 GPIO 22 SPWTXS 5 SDDQM 1 SDDQOM 1 SDDQM 1 SDDQM GPIO 23 SPWRXS 5 TCRFAVLO STCNEXO STCNEXO GPIO 24 SPWRXD 5 TCCLK1 STCNEX1 STCNEX1 GPIO_25 1553RXENA STCNCLK1M STCNCLK1M RMTXDO GPIO 26 1553TXA STCNMRK1 STCNMRK1 RMTXD1 GPIO 27 1553RXA TCD1 STCNEX2 STCNEX2 RMRXDO GPIO 28 1553RXNA 1 STCNCLS1M STCNCLS1M RMRXD1 GPIO_29 1553TXNA STCNMRK2 STCNMRK2 RMTXEN GPIO_30 1553TXINHA STCNMRK3 STCNMRK3 GPIO_31 1553RXB TCRFAVL1 STCNTODIN STCNTODIN RMCRSDV 32 1553RXNB 2 STCNTOD2N STCNTOD2N RMINTN GPIO_33 1553RXENB A16MCS RMMDIO GPIO_34 1553TXB 16 5 RMMDC GPIO_35 1553CLK TCD2 RMRFCLK GPIO_36 TCACT2 STCNPPS1N STCNPPS1N GPIO_37 1553TXNB A16DCS GPIO_38 1553TXINHB A16MAS GPIO_39 TCRFAVL2 5
46. W TXS0 P SPW TXS0 3 OoOo SPW_TXSO_N SPW 8 5 SPW_IXS1 6 11 SPW TXS1 P SPW TDO P 9 0 s Eg SPW TXS1 N SPW TXD1 10 SPW_TXD1 P 2 129 SPW TXD N q CHASSIS LVDS0 en 22 EN SPWSHDO 9 R181 DGND NE le DGND 2 27 Pa DS90LV048A SPW RXD1 P 1 RXSO RP48A 15 2 SPW RXSO P SEO EE SE s SPW_RXSO_N 52 SPW RXS1 RP48B 14 3 SPW RXS1 P T NEEE x u H 2 x 338 SPW N N SEW TXSIB 8 2 SPW RXDO RP48C 11 6 SPW RXDO P P 9 L s 51 SPW RXDi RP48D 10 7 SPW RXD1 P 7 2 N 338 OEA N A SPW_RXDI N R176 46 a a CHASSIS LVDS1 AG a T 2 s SPWSHD1 N a R182 NE 10k NE DIN 100R DGND Figure 2 10 Transceiver and Termination of the SPW interfaces 2 of 6 interfaces shown Aeroflex Gaisler August 2014 Rev 0 11 GAISLER User Manual At power up or reset of the board the SpaceWire Clock Divisor Registers values are cleared to zero except the following bits which are taken from the GPIO inputs bits 8 amp 0 are set by the state of GPIO 34 bits 9 amp 1 are set by the state of GPIO 37 bits 10 amp 2 are set by the state of GPIO 40 bits 11 8 are set by the state of GPIO 42 On the GR712 BOARD resistors can be installed in order to set
47. X12P RX13P RX14P RX15P RX16P RX17P RX18P RX19P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FUNCTION RX10N RX11N RX12N RX13N RX14N RX15N RX16N RX17N RX18N RX19N Table 4 22 J19 RS422 Receiver Pairs August 2014 Rev 0 11 GAISLER Aeroflex Gaisler AB 50 FUNCTION ASIC CONNECTOR PIN RX20P 1 2 RX21P 3 4 RX22P 5 6 RX23P 7 8 RX24P 9 10 RX25P 11 12 RX26P 13 14 RX27P 15 16 nc 17 18 nc 19 20 GR712 Development Board User Manual FUNCTION RX20N RX21N RX22N RX23N RX24N RX25N RX26N RX27N nc nc Table 4 23 J20 RS422 Receiver Pairs FUNCTION ASIC pin CONNECTOR PIN GPIOO 1 2 GPIO1 3 4 GPIO2 5 6 GPIO3 7 8 GPIO4 9 10 GPIO5 11 12 GPIO6 13 14 GPIO7 15 16 GPIO8 17 18 GPIO9 19 20 FUNCTION DGN DGN DGN DGN DGN DGN DGN DGN DGN DGN OUD D Table 4 24 J21 PIO Header Pin out FUNCTION ASIC pin CONNECTOR PIN GPIO10 1 2 GPIO11 3 4 GPIO12 5 6 GPIO13 7 8 GPIO14 9 10 GPIO15 11 12 GPIO16 13 14 GPIO17 15 16 GPIO18 17 18 GPIO19 19 20 FUNCTION DGN DGN DGN DGN
48. X7 JP8 SWMX8 JP9 SWMX9 JP10 SWMX10 JP11 SWMX11 JP12 SWMX12 JP13 SWMX13 JP14 SWMX14 JP15 SWMX15 JP16 SWMX16 JP17 SWMX17 JP18 SWMX18 JP19 SWMX19 JP20 SWMX20 JP21 SWMX21 JP22 SWMX22 JP23 SWMX23 JP24 SWMX24 JP25 SWMX25 JP26 SWMX26 JP27 SWMX27 JP28 SWMX28 JP29 SWMX29 JP30 SWMX30 JP31 SWMX31 JP32 SWMX32 JP33 SWMX33 JP34 SWMX34 JP35 SWMX35 Gaisler AB Table 4 36 List and definition of PCB Jumpers part 1 for details refer to schematic RD 1 August 2014 Rev 0 11 54 GR712 Development Board GAISLER User Manual Name Function Type Description JP36 SWMX36 2X6 2mm Header Configuration jumper for SWMX36 pin JP37 SWMX37 2X6 2mm Header Configuration jumper for SWMX37 pin JP38 SWMX38 2X6 2mm Header Configuration jumper for SWMX38 pin JP39 SWMX39 2X6 2mm Header Configuration jumper for SWMX39 pin JP40 SWMX40 2X6 2mm Header Configuration jumper for SWMX40 pin JP41 SWMX41 2X6 2mm Header Configuration jumper for SWMX41 pin JP42 SWMX42 2X6 2mm Header Configuration jumper for SWMX42 pin JP43 SWMX43 2X6 2mm Header Configuration jumper for SWMX43 pin JP44 SWMX44 2X6 2mm Header Configuration jumper for SWMX44 pin 45 SWMX45 2X6 2mm Header Configuration jumper for SWMX45 pin 46 SWMX46 2X6 2mm Header Configuration jumper for SWMX46 pin JP47 SWMX47 2X6 2mm Header Configurat
49. able 4 17 J14 POWER External Power Connector Aeroflex Gaisler August 2014 Rev 0 11 GAISLER FUNCTION ASIC PIN 48 CONNECTOR PIN GR712 Development Board User Manual ASIC PIN FUNCTION DGND D31 D30 D29 D28 3 3V D27 D26 D25 D24 DGND SDDQM3 SDDQM2 3 3V A2 A3 A4 DGND D23 D22 D21 D20 3 3V D19 D18 D17 016 DGND nc nc SDCLKO 43 3V SDRASN SDWEN SDCSNO SDCSN1 nc DGND nc nc 3 3V D15 D14 D13 D12 DGND D11 D10 D9 D8 3 3V 10 DGND 11 12 3 3V SDDQM1 SDDQMO DGND D7 D6 D5 D4 3 3V D3 D2 D1 DO DGND SDSDA pulled high 3 3V Table 4 18 Aeroflex Gaisler AB 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 OAN 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DGND CB7 CB6 CB5 CB4 3 3V CB3 CB2 DGND SDDQMO SDDQM5 pulled high 3 3V 5 A6 DGND nc nc nc nc 3 3V nc nc nc nc DGND nc nc pulled high 3 3V SDCASN SDCKE1 pulled high 17 14 SDCLK1 DGND nc nc 3 3V nc nc nc nc DGND nc nc nc nc 43 3V A9 A15 SBAO DGND A16 A13
50. bug Support Unit ahb 90000000 a0000000 LEON3FT SPARC V8 Processor 01 01 053 LEON3FT SPARC V8 Processor 02 01 01c AHB Debug JTAG ver 0x0 03 01 01 0 0 04 01 080 ver 0 0 05 01 029 Link ver 0 0 06 01 029 Link ver 0x0 07 01 029 ver 0 0 08 01 Link ver 0x0 09 01 029 ver 0 0 01 ver 0x0 0b 01 072 151 0 01 031 0d 01 030 0e 01 02f ver 0 1 00 01 054 ver 1 01 01 006 02 01 004 ver 0 2 ver 0x0 ver 1 GR712 Development Board User Manual ver 0x0 ver 0x0 AHB trace 256 lines 32 bit bus CPU 0 win 8 hw CPU 1 win 8 03 01 006 ahb 06 01 019 irg ahb icache 4 4 icache 4 4 Gaisler Research Bridge 80100000 Gaisler Research OC CAN controller 5 fff30000 cores 2 07 01 050 ahb apb Gaisler Research a0000000 80100000 hwbp 2 stack pointer 0x407ffff0 bp 2 itrace 256 V8 mul div srmmu lddel 1 4 kbyte 32 byte line lru 4 kbyte 16 byte line lru itrace 256 V8 mul div 4 kbyte 32 byte line lru 4 kbyte 16 byte line lru ver 0x0 GRFPU srmmu lddel 1 80200000 ver 0 1 fff31000 FT AHB static ram a0100000 80100100 ver 0x12 256 kbyte AHB ram 8 0xa0000000 Figure 3 2 GRMON Listing 2 Aeroflex Gaisler August 2014 Rev 0 11
51. connected to an 12 pin 0 1 header on the board The SPI Chip Select pin is provided by an otherwise unused GPIO pin Since the same pin is not available in all configurations multiple GPIO pins are provided on the 12 pin header and the User should choose an appropriate pin The GR712 BOARD provides an on board AD7841 Temperature monitor circuit as an example SPI circuit The Chip Select for this device is provided by GPIO54 Aeroflex Gaisler AB August 2014 Rev 0 11 4 GAISLER User Manual JP70 Install jumpers 1 2 and 3 4 to provide pull ups on 2 signals ga Be SCL 12 3V3 SDA DGND HDR2X2 Header for external 2 functions Note These are 3 3V level signals Buffer necessary if 5V compatibility required C18 peno 33 100n Yi 32 768k 3V3 77 95 109 4 5T SCL VB 7 gt SDA GND sesNp C20 DS1672 SUPERCAP 2 Real Time Clock chip with power backup DGND Figure 2 22 2 Interface Configuration SPIMOSI SPICSN AD7814ART DGND 2 HDR1X2 Install to enable example SPI device AD7814 is SPI Temperature Monitor GPIO54 SPI I F SPICLK SPI lt SPIMISO SPIMOSI GPIO41 SPIMOSI GPI010 3V3 9 10 11 12 98953 HDR2X6 Figure 2 23 SPI Interface Configuration
52. edance design rules and matched trace lengths 100 Ohm Termination resistors for the LVDS receiver signals are mounted on the board close to the receiver Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER 19 GR712 Development Board User Manual The pin out and connector types for these Spacewire interfaces conform to the Spacewire standard as shown in Figure 2 10 The inner shield pin pin3 of the connector is connected to DGND via a 10kohm resistor 2 6 2 SPWCLK Configuration options on the board jumpers crystal socket and SMA coaxial connector allow this Spacewire clock to be provided from the following sources Dedicated SPWCLK oscillator if appropriate Oscillator X5 is mounted in socket and jumper JP88 is not installed Main processor oscillator X1 if jumper JP88 is installed External clock input via SMA connector J31 X5 and JP88 not installed The default configuration is that the clock is supplied by the Main processor oscillator X1 and jumper JP88 is installed Do not install jumper JP88 if an oscillator is installed in X5 socket as this will unintentionally connect the outputs of oscillator X1 and Oscillator 5 together 3V3 100 Ohm Differential traces Matched lengths U24 J3 B DS90LV047A MDM9S SPW RXDOP 1 SPW TXDO SPW P SP RDO 222 16 SPW_TXDO_N SPW RXS0 P 2 UT1 N SEW RXSD N SPW TXSO 3 14 SP
53. ent of the current consumption of the GR712RC ASIC 2 16 Ethernet Interface The GR712RC ASIC device incorporates a Ethernet controller with support for RMII interface and the GR712 Development Board has a National Semiconductor DP83848 10 100Mbit s Ethernet PHY transceiver and RJ45 connector are on board For more information on the registers and functionality of the Ethernet MAC PHY device please refer to the data sheet for the DP83848 device 50 MHz oscillator dedicated for this device is provided on the board The interrupt output of the Ethernet interface is connected to the SWMX35 input to the GR712RC ASIC This can be disabled by removing 5 if necessary Gaisler August 2014 Rev 0 11 GAISLER 2 ETH RXD 1 0 2 ETH_TXD 1 0 ETH TXEN ETH CRS DV GR712RC ETH MDIO ETH MDC ETH MDINT ETHERNET RMII PHY GR712 Development Board User Manual Figure 2 18 Block diagram of Ethernet RMII Interface 2 17 MIL STD 1553 Interface The board implements a Dual MIL STD 1553 interface with a 3 3V Transceiver and Transformer circuits as shown in Figure 2 20 Since there are various standard connectors defined for the connection to MIL STD 1553 bus and because of limited PCB area it has instead been decided to implement a D9 Female connected for the connector on the board as this can be most easily adapted to suit the user s desired connec
54. f PCB mounted 46 Table 4 35 List and definition of 0 2 20 4 e eee 46 Table 4 36 List and definition of PCB Jumpers part 1 A7 Table 4 37 List and definition of PCB Jumpers part 2 48 Table 4 38 List and definition of PCB Jumpers 3 49 Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual LIST OF FIGURES Figure 1 1 GR 12 Development Board orne 7 Figure 2 1 GR712RC ASIC Block Diagram amende ma 10 Figure 2 2 GR712RC set ie ee tn 10 Figure 2 3 Block Diagram 5 12 2 iR A REX Ra 11 Figure 2 4 On Board Memory Configuration 12 Figure 2 5 Mezzanine Connector Pin Number 13 Figure 2 6 Switch Matrix and Interface Functions 14 Figure 2 7 Configuration JUR Dele o 15 Figure 2 8 Block Diagram of the CAN interface 16 Figure 2 9 Transceiver and Termination Configuration one of 2 interfaces shown 17 Figure 2 10 Transceiver and Termination of the SPW interfaces 2 of 6 interfaces sh
55. has mounted as standard one FLASH memory bank made up of one Intel JS28F640J3 FLASH device This device is a 64Mbit 8Mbyte x 8 bit device typically with 90ns access times The data bus width to the Flash memory is 8 bits wide Note that the PROM width and PROM EDAC conditions are set by the state of the GPIO 3 and GPIO 1 pins at power up of the Processor These pins are provided with pull down resistors to set the default mode to 8 bit with no EDAC If EDAC operation of the Flash Prom is desired then jumper JP85 should be installed to pull up GPIO 1 If measuring the state of the GPIO pins please take into account the effect of these pull down resistors Conversely if an external signal is connected to the GPIO 3 and GPIO 1 pins this may override the expected state of the pin at power up For more information on the PROM width and PROM EDAC settings refer to the Memory Configuration documentation in the GR712RC User Manual RD 4 2 3 3 SDRAM Standard PC133 SDRAM can be installed by means of an 144 pin SO DIMM socket on board The SO DIMM provides 64 bit wide data paths However in the standard Leon model only 32 data bits of the SDRAM are used plus 16 additional data bits for the RS EDAC memory bits Aeroflex Gaisler AB August 2014 Rev 0 11 a GAISLER User Manual 2 4 Therefore nominally only half the capacity of the SO DIMM will be available Note the SDRAM interface is limited to 80 MHz
56. ion jumper for SWMX47 pin JP48 SWMX48 2X6 2mm Header Configuration jumper for SWMX48 pin JP49 SWMX49 2X6 2mm Header Configuration jumper for SWMX49 pin JP50 SWMX50 2X6 2mm Header Configuration jumper for SWMX50 pin JP51 SWMX51 2X6 2mm Header Configuration jumper for SWMX51 pin JP52 SWMX52 2X6 2mm Header Configuration jumper for SWMX52 pin JP53 SWMX53 2X6 2mm Header Configuration jumper for SWMX53 pin JP54 SWMX54 2X6 2mm Header Configuration jumper for SWMX54 JP55 SWMX55 2X6 2mm Header Configuration jumper for SWMX55 pin JP56 SWMX56 2X6 2mm Header Configuration jumper for SWMX56 pin JP57 SWMX57 2X6 2mm Header Configuration jumper for SWMX57 pin JP58 SWMX58 2X6 2mm Header Configuration jumper for SWMX58 pin JP59 SWMX59 2X6 2mm Header Configuration jumper for SWMX59 pin JP60 SWMX60 2X6 2mm Header Configuration jumper for SWMX60 pin JP61 SWMX61 2X6 2mm Header Configuration jumper for SWMX61 pin JP62 SWMX62 2X6 2mm Header Configuration jumper for SWMX62 JP63 SWMX63 2X6 2mm Header Configuration jumper for SWMX63 pin JP64 SWMX64 2X6 2mm Header Configuration jumper for SWMX64 pin JP65 SWMX65 2X6 2mm Header Configuration jumper for SWMX65 pin JP66 SWMX66 2X6 2mm Header Configuration jumper for SWMX66 pin JP67 SPARE RS422 4 pin 0 1 Header Header providing access to Spare RS422 signals JP68 Not used JP69 Not used JP70 I2C PULLUP 2X2 pin 0 1 Header Install pull ups I2C signals JP71 SPI CSN 1X2 pin 0 1 Header Enable Disable on
57. it of SRAM memory organised as 1 bank x 2Mword x 40 bits wide a second SRAM bank can be installed on the PCB but is not fitted as standard 64Mbit of Flash PROM organised as 1 bank x 8 Mword 8 bits wide e SODIMM socket to allow up to 64Mword x 48 bit SDRAM to be installed with 512Mbyte module Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual Additionally in order to allow users to install alternative memory configurations or devices all the signals of the memory interface are connected to memory expansion connectors The expansion connectors allow mezzanine boards to be added similar to those developed for the existing GR CPCI development boards 32 16 SDRAM BANKO SODIMM GR712RC cT M Sia Re BANK1 MEMORY EXPANSION CONNECTOR CONTROL Figure 2 4 On Board Memory Configuration 2 3 1 SRAM GR712 BOARD is laid out with two SRAM memory banks but only has one bank mounted as standard Each bank is made up of five CY7C1069AV33 These devices are 16Mbit 2Mbyte x 8 bit devices with 10 or 12 ns access times The five devices provide 32 8 bit wide SRAM memory paths allowing EDAC operation These memory banks are mapped as RAMBANKO and RAMBANK1 In case the user wishes to disable the on board memory this can be done by removing the jumpers JP76 on the PCB 2 3 2 FLASH The GR712 BOARD
58. nce document and information on expansion connector pin 2 3 4 numbering Added clarification for jumper numbering lettering 0 10 2013 10 23 Figure 2 6 Corrected Jumper position labels for expansion connector pin numbering Table 3 1 Correct typo Default frequency is 48MHz amp 4 33 0 11 2014 08 08 1 3 Removed spurious third paragraph Table 3 1 Changed default status of JP88 to not installed since a separate 100 2 oscillator X5 is installed for SPW_CLK Changed default state of JP84 to 2 3 to use 80MHz oscillator in X2 Aeroflex Gaisler August 2014 Rev 0 11 GAISLER User Manual 1 1 INTRODUCTION Overview This document describes the GR712 Development Board The purpose of this equipment is to provide developers with a convenient hardware platform for the evaluation and development of software for the Aeroflex Gaisler GR712RC Dual Core Leon3FT SparcV8 Processor The GR712RC is LEONSFT Fault Tolerant architecture custom ASIC for Aerospace applications The GR712 BOARD comprises a custom designed PCB in a Double Eurocard format 233 5 x 160mm making the board suitable for stand alone bench top development or suitable for mounting in a housing The principle interfaces and functions are accessible on the front and back edges of the board The GR712RC chip incorporates an internal programmable switch matrix which means that the same input output pin can be used for multiple
59. nfiguring the jumpers on the board or connecting disconnecting cables ensure that the unit is in an un powered state ATTENTION prevent damage to board please ensure that the correct power supply and power supply polarity is used with the board Abbreviations ASIC Application Specific Integrated Circuit DIL Dual In Line ESD Electro Static Discharge FT Fault Tolerant GEO Geostationary Earth Orbit GPIO General Purpose Input Output Input Output IP Intellectual Property LEO Low Earth Orbit LVDS Low Voltage Digital Signalling MUX Multiplexer PCB Printed Circuit Board RMII Reduced Media Independent Interface RS Reed Solomon SMD Surface Mount Device SPW Spacewire TMTC Telemetry Telecommand Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual 2 2 1 ELECTRICAL DESIGN GR712RC ASIC The GR712RC ASIC is an advanced system on a chip with advanced interface protocols dedicated for high reliability Rad Hard space aeronautics and military applications The GR712RC incorporates a dual core LEON3 FT SPARC V8 processor architecture and its internal block diagram is represented in Figure 2 1 In order to reduce the number of pins required on the device an internal programmable switch matrix allows the same pin to be used for difference interface functions IEEE 754 LEON3FT FPU SPARC V8 um 4x4kB 4x4kB D cache Ethernet
60. nt measure point for 3 3V supply to ASIC JP81 Installed 1 2 Can be used as current measure point for 1 8V supply to ASIC JP82 Not installed Connections only required if External RESET switch is required JP83 Not installed Prevents Watchdog time out from resetting board Install to allow Watchdog to reset board JP84 Installed 2 3 Uses Oscillator in socket X2 as main clock JP85 Not installed Install to pull pin HIGH to enable PROM EDAC JP86 Not installed Connections only required if External DSU Break switch is required JP87 Not installed Only install for internal PLL to be bypassed JP88 Not installed A separate 100 MHz osc is installed in X5 for SPW_CLK JP89 Not used Only used if a CPCI front panel would be installed Table 3 1 Default Status of Jumpers Switches Aeroflex Gaisler AB August 2014 Rev 0 11 GR712 Development Board User Manual GAISLER User Manual To operate the unit stand alone on the bench top connect the 5 power supply to the Power Socket J14 at the back of the unit The POWER LED should be illuminated indicating that the 3 3V power is active Upon power on the Processor will start executing instructions beginning at the memory location 0x00000000 which is the start of the PROM If the PROM is empty or no valid program is installed the first executed instruction will be invalid and the processor will halt with an ERROR condition with the ERROR LED illuminated To
61. o the GR712RC ASIC as represented in Figure 2 15 The connection to the board is via the Mini USB connector J12 and the translation between USB and JTAG signals of the ASIC is performed via a FT2232H Hi Speed Dual USB UART FIFO IC 2232 JTAG USB CONVERTER JTAG I F GR712RC TERMINAL COMPUTER ASIC Figure 2 15 Debug Support Unit connections On this chip there is no DSUEN signal so the DSU is always enabled to allow processor control and program debugging via the DSU link On this chip there is no DSUACT signal to indicate the DSU operation state On this chip there is no DSUBREAK signal Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual 2 14 Oscillators and Clock Inputs The oscillator and clock scheme for the GR712 BOARD is shown in Figure 2 16 2 14 1 Main Clock The main oscillator for the GR712RC ASIC is a 48 MHz Crystal oscillator This oscillator is an SMD oscillator soldered on to the board If a different user defined main operating frequency is required this can be achieved by installing a 4 pin 3 3V DIL8 style oscillator in socket X2 on the board and moving jumper JP84 A zero delay buffer circuit CY2305 is used to distribute the MAINCLK MEMORY EXPANSION CONNECTOR L MAIN CLK 48 MHz 2 DELAY T BUFFER SMD GR712 TBD MHz ASIC DIL8 SOCKET SDCLK SDRAM MODULE COAX CONNECTOR TBD MHz
62. of 2 interfaces shown 2 5 2 Configuration of Slew Rate The SN65HVD230 transceiver device used on the board has the facility to set the device into STANDBY mode by connecting an active high external signal to pin 8 of the device However this board this is tied to permanently to enable the CAN bus Transceivers A further feature provided by the SN65HVD230 device is the capability to adjust the transceiver slew rate This can be done by modifying the values of resistors connected to pin 8 of the transceivers The default value of 0 ohms is compatible with 1Mbps operation From the data sheet the following resistor values give the following slew rates 10kOhm gt 15V us 100kOhm gt 2V us 2 6 Spacewire LVDS Interfaces The GR712RC ASIC provides six Spacewire interfaces which are routed to connectors of the the board Two interfaces SPW 0 and SPW 1 are dedicated Spacewire interfaces The four remaining interfaces SPW 2 SPW5 are available if the Switch matrix is suitably configured 2 6 1 SPW interface circuit Each Spacewire interface consists of 4 LVDS differential pairs 2 input pairs and 2 output pairs as shown in the figure below As the Spacewire interface to the GR712RC ASIC is LVTTL 3 3V logic LVDS driver and receiver circuits are required on the PCB to interface between the ASIC and the external interface The PCB traces for the LVDS signals on the GR712 BOARD are laid out with 100 Ohm differential imp
63. own 18 Figure 2 11 SPW Clock Divisor Configuration 19 Figure 2 12 RS422 TX configuration 20 Figure 2 13 RS422 Receiver Configurations 21 Figure 2 14 Serial interface ua rat 24 Figure 2 15 Debug Support 24 Figure 2 16 Clock Distribution Schemes dune 25 Figure 2 17 Power Regulation Configuration a 26 Figure 2 18 Block diagram of Ethernet RMII 27 Figure 2 19 MIL STD 1553 Transceiver and Transformer circuit 27 Figure 2 20 PIO interface configuration 28 Figure 2 21 Watchdog configuration 29 Figure 2 22 12 Interface Configuration ie Sinusite 30 Figure 2 23 SPI Interface Configuration 30 Fig re 3 1 GRMON Listing M MO nie Niort 33 Figure 3 2 GRMON Listing 25 dde
64. ration jumper for SWMX13 pin 2X6 2mm Header Configuration jumper for SWMX14 pin 2X6 2mm Header Configuration jumper for SWMX15 pin 2X6 2mm Header Configuration jumper for SWMX16 pin 2X6 2mm Header Configuration jumper for SWMX17 pin 2X6 2mm Header Configuration jumper for SWMX18 pin 2X6 2mm Header Configuration jumper for SWMX19 pin 2X6 2mm Header Configuration jumper for SWMX20 pin 2X6 2mm Header Configuration jumper for SWMX21 pin 2X6 2mm Header Configuration jumper for SWMX22 pin 2X6 2mm Header Configuration jumper for SWMX23 pin 2X6 2mm Header Configuration jumper for SWMX24 pin 2X6 2mm Header Configuration jumper for SWMX25 pin 2X6 2mm Header Configuration jumper for 5 26 pin 2X6 2mm Header Configuration jumper for SWMX27 pin 2X6 2mm Header Configuration jumper for SWMX28 pin 2X6 2mm Header Configuration jumper for SWMX29 pin 2X6 2mm Header Configuration jumper for SWMX30 pin 2X6 2mm Header Configuration jumper for SWMX31 pin 2X6 2mm Header Configuration jumper for SWMX32 pin 2X6 2mm Header Configuration jumper for SWMX33 pin 2X6 2mm Header Configuration jumper for SWMX34 pin 2X6 2mm Header Configuration jumper for SWMX35 pin GAISLER 4 3 List of Jumpers Name Function JP1 SWMXO amp 1 JP2 SWMX2 JP3 SWMX3 4 SWMX4 JP5 SWMX5 JP6 SWMX6 JP7 SWM
65. ser Manual BOARD MOUNTED LED RESETN POWER ON GR712RC ASIC RESET JUMPER CIRCUIT JP83 Figure 2 21 Watchdog configuration Also to allow the WDOGN signal to generate a system reset it is necessary to install the Jumper JP83 see Figure 2 21 For software development it is often convenient or necessary to disable the Watchdog triggering in order to be able to easily debug without interference from the Watchdog operation In this case the Jumper JP83 should be in the removed When the watchdog triggers the Watchdog LED will illuminate but a system reset will not occur 2 18 4 JTAG interface The JTAG signals form the ASIC are connected to an FT2232HL interface chip This chip provides a conversion to a standard USB interface on the front edge of the board J12 Special drivers in the GRMON debug software are able to communicate with this chip in order to enable a standard USB connection on a host computer to be used to perform the DSU Debug over the JTAG link of the ASIC 2 18 5 I2C interface As shown in Figure 2 22 the 12C interface pins of the GR712RC ASIC are connected to an 4 pin 0 1 header on the board and Jumper JP70 allows pull up resistors to be installed if the interface configuration requires them The GR712 BOARD provides an on board DS1672 Real Time Clock circuit as an example 2 circuit 2 18 6 SPI interface As shown in Figure 2 23 the SPI interface pins of the GR712RC ASIC are
66. these pins by means of either a pull up logic 1 or a pull down logic resistor as shown in the figure below The Pads for the Pull down resistors are on the top side of the PCB and the pads for the Pull up resistors are on the bottom side of the PCB The default when delivered is that the pull down resistors are mounted Note that elsewhere on the board each GPIO already has a weak pull up 47 resistor to ensure that the pins are not unintentionally left floating The value of the pull down resistor must be selected to be sufficiently strong to override the effect of this pull up VCC VCC Li 47k pull up pull up 4k7 pull down DGND Figure 2 11 SPW Clock Divisor Configuration Resistors GPIO Pin ASIC Pull down Pull up Comment pin name Resistor Resistor GPIO 34 SWMX37 R212 R221 R212 4k7 is fitted as default GPIO 37 SWMX40 R211 R220 R211 4k7 is fitted as default GPIO 40 SWMX43 R210 R219 R210 4k7 is fitted as default GPIO 42 SWMX45 R209 R218 R209 4k7 is fitted as default Table 2 1 SpaceWire Clock Divisor Resistors 2 7 RS422 Interfaces for UART and TMTC functions The GR712RC ASIC provides up to six UART interfaces each with RXD TXD pin pairs 3 3V TTL levels For these interfaces RS422 transmitter receiver have been defined Aeroflex Gaisler AB August 2014 Rev 0 11 GAISLER User Manual Additionally
67. to operate in all these configurations each Switch Matrix pin on the GR712RC ASIC is connected to a 12 pin 2mm pitch header as represented in Figure 2 7 Figure 2 7 Configuration Jumpers If the pin is to be used as a General Purpose pin the jumper would be inserted in the position 1 2 If the pin is to be used for configuration type the jumper would be inserted in the position 3 4 and so on Please note that on the silkscreen printing on the actual PCB the jumper positions are marked with the letters to which correspond as follows 1 2 3 4 C 5 6 7 8 E 9 10 F 11 12 In this simple manner the interface can freely flexibly configured but the User must take care to ensure that the jumpers are set in the correct position to suit the interface functions they require Gaisler August 2014 Rev 0 11 GAISLER User Manual 2 5 CAN Interface The board provides the electrical interfaces for two CAN bus interfaces as represented in the block diagram Figure 2 8 The CAN bus transceiver IC s on this board are SN65HVD230 devices from Texas Instruments which operate from a single 3 3V power supply The connector interfaces are male DSUB 9 connectors adhering to the standard pin out for this type of interface ref Table 4 5 And Table 4 4 CAN 2 8 TRANSCEIVER t 2 9 l 14 gt
68. tor configuration 1553TXINHA lt 28 VDDA 1553TXA 1553 1553RXA 1553RXNA BUSA BUSA 2 GNDA O 2 o USA HI 1573PSI z 8050 3 BUSOB DGND 3V3 C22 C24 100n 10u DGND Insert Jumpers for MIL STD 1553A direct coupling JP73 1 2 55R IW Ratio 1 2 5 for Short Stub Direct coupling 825 Zo 70R ns Connection to BUS_A Ratio 1 1 79 for Long Stub coupling Zo 70R NE Install R27 R28 08 and remove R25 R26 for Long Stub Coupling BUS 08 Figure 2 19 MIL STD 1553 Transceiver Transformer circuit one of two interfaces shown Gaisler August 2014 Rev 0 11 GAISLER User Manual 2 18 Other Interfaces and Circuits 2 18 1 GPIO The 64 general Purpose Input Output signals of the ASIC 3 3V LVTTL voltage levels are connected to a set of 0 1 pitch pin headers on the board thus allowing easy access to these signals A series protection resistor of 470 Ohm is included on each signal and weak pull ups 47k are provided on each of the signals lines on the PCB PULL UP 47k GR712RC m GPIO 63 0 ASIC 1 SERIES x64 Figure 2 20 PIO interface configuration Each GPIO signal has a corresponding ground pin on the pin header thus allowing
69. ype Description upper UART 0 D9 S Female Connections for Serial UART 10 RS232 J1B lower UART 1 D9 S Female Connections for Serial UART 1 RS232 upper CANBUS 0 Dual D9 P male Connections for CANBUS 0 interface J2B lower CANBUS 1 Dual D9 P male Connections for CANBUS 1 interface J3 SPW 0 MDMS9 S female LVDS connections for Spacewire Interface 0 SPW 1 MDMS9 S female LVDS connections for Spacewire Interface 1 J5 SPW 2 MDMS9 S female LVDS connections for Spacewire Interface 2 J6 SPW 3 MDMS9 S female LVDS connections for Spacewire Interface 3 J7 SPW 4 MDM 9 S female LVDS connections for Spacewire Interface 4 J8 SPW 5 MDMS9 S female LVDS connections for Spacewire Interface 5 J9 MEM I O 5177984 5 Memory I O connector 120 pin 0 8mm pitch J10 ETHERNET RJ45 10 100Mbit s Ethernet Connector J11 GEN 5177984 2 General I O connector 80 pin 0 8mm pitch J12 JTAG USB Mini AB JTAG signal interface over USB J13 MIL STD 1553 D9 P male Dual MIL STD 1553 interface J14 POWER IN 2 1mm center ve 5V DC power input connector J15 SODIMM 144 pin SODIMM Socket for SODIMM SDRAM module J16 TX 9 0 20 pin 0 1 Header Pin connections for RS422 TX pairs 0 to 9 J17 TX 19 10 20 pin 0 1 Header Pin connections for RS422 TX pairs 10 to 19 J18 RX 9 0 20 pin 0 1 Header Pin connections for RS422 RX pairs 0109 J19 RX 19 10 20 pin 0 1 Header Pin connections for 5422 RX pairs 10 to 19 J20 RX 27 20 20 pin 0
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