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ADV8005 Hardware Reference Manual (Rev. 0)

1. N 30 2 1 6 deed VER RERUM EAR EARS ERE 31 21 7 MOE 32 2 1 8 Mode Q 33 2159 gt Mode 81i n RET OR HERRERA DOE NC RM DID RH a es ena 24 10 9 ENTRIES 2 1 11 10 Picture in Picture PiP External OSD Less Than 720p 2 1 12 11 PIP External OSD Greater Than or Equal To 720p seen 2 1 13 Mode 12 Dual Zone OSD ir ien p nene ee eR 38 Rev 0 Page 2 of 326 06 707 2 E TA Mode 13 7 OSD from HDMI RK ed e ente te ete eate 39 2 1 15 14 Handling Triple Inputs esee tenente ntt 40 2 2 ADV8005 Top Level Overview aede ie de tei ten I edd aseo 40 2 2 1 5 Video 40 2222 Digital Video Inpultza iecore ERR e TE rte 44 2221 Vid o TIL INPUT 44 22222 SEXOSDSDEEIDDpUt 45 2 2 23 45 22 2 4 lt Areatment ot Unused 47 22255 9
2. DDR2 Memory Interface Build Scale OSD sD Gomi Video Output 1 Muxing ea Muxing 720p Input Exosd T dary 24 bit Muxing econdary Input c 43 Bin dur Formatting A m En 4 i 720p v QU Secondary Video 7 5 VSP 36 bit E Primary 4 Progressive tof Input Liye y Data 8 an sed Port Formatting x it 7 Encoder CSC amp ACE Y 4 720 S 1 720p Video 30 from Format Encoder Transceiver 8 CSC KE Figure 19 ADV8005 Mode 9 Configuration Mode 9 is used in cases where no processing is required on the input video This can be passed directly to the output No access to external DDR2 memory is required in this case Rev 0 Page 35 of 326 06 707 2 1 11 Mode 10 Picture Picture PiP External OSD Less Than 720p Mode 10 should be used if e OSD data is input via the EXOSD TTL 24 bit input port e OSD data input via the EXOSD TTL 24 bit input port is less than 720p Mode 10 PiP External OSD 720p DDR2 Memory Interface f Output VSP Muxing 1080p PiP 480p Video Secondary 4 from Data Decoder 7 Formatting LS 1080p PiP p Pi Seconda vt B 5 v 36 bit 2 Input Loe Y
3. BKSV HDCP Receiver Key Selection Vector Refer to HDCP documentation BNR Block Noise Reduction CEC Consumer Electronics Control CP Component Processor CSC Color Space Converter Conversion CSync Composite Synchronization CTS Cycle Time Stamp CUE Color Upsampling Error CVBS Composite Video DCM Decimation DDR Double Data Rate DDFS Direct Digital Frequency Synthesizer DE Data Enable DID Identification Word DLL Delay Locked Loop DMA Direct Memory Access DNR Digital Noise Reduction DPP Data Preprocessor DSD Direct Stream Digital DST Direct Stream Transfer DUT Device Under Test designate the ADV8005 unless stated otherwise DVD Digital Video Disc DVI Digital Visual Interface EAV End of Active Video ED Enhanced Definition ENC Encoder EQ Equalizer FFS Field Frame Scheduler FRC Frame Rate Conversion Converter HBR High Bit Rate HD High Definition HDCP High Bandwidth Digital Content Protection HDMI High Definition Multimedia Interface HDTV High Definition Television HEAC HDMI Ethernet and Audio Channels HEC HDMI Ethernet Channel HPA Hot Plug Assert HPD Hot Plug Detect HSync HS Horizontal Synchronization Integrated Circuit ISRC International Standard Recording Code 25 Inter IC Sound Inter Integrated Circuit KSV Key Selection Vector LLC Line Locked Clock LOFP Low profile Quad Flat Package LSB Least Significant Bit L PCM Linear Pu
4. 166 36 1 Functional Description ene eeu ne eee nene 167 3 7 Progressive to Interlaced Conversion esseeeeeeeee teet nente tente tente nennen teniente 169 On Sereen Display 170 4 1 Introduction dx sc deese sag e T D EE T EO E P DR ER t C E ROI LIE ER IPs 170 4 1 8 170 412 OSD System Application Diagram 170 41 3 Typical OSD Component SIZES eren r n E E E EP ERR EEUU EORR 171 4 2 Architecture OyVerview iu s e aS ee e D 171 42 1 Introduction E 171 4 2 2 Level Dia grati stasesscsssiscaschsezaseassossenossuscassaseasersseva avosayadacondnas EE Aa EAEE AEO AAE Aae ARRETE EEEE 171 423 OSD Blom ini gis see A a cea REUS 172 ADA XEXternal Alpha A A A eR A 173 4 2 55 Gru M D 173 42 5 1 OSD Cote Region Definitii sssi Ne EROR 173 42 52 OSD ColorSpace EEEE A 175 4 2 6 OSD m et 4 2 7 ODE eC 42 8 1 050 Master Slave SPI Interface ue nocte e ta l pie ERAT IO SEDE T T NES MEE OC aU TA SEHR 42 82 SPISlave
5. pu Channel gt 1 1 svsp inp sel 3 0 OSD Blend 2 9 y sd enc inp sel 3 0 Secondary Input Channel External RX Input Channel OSD The following registers are used to configure the video routed through the ADV8005 Figure 25 ADV8005 Digital Core Muxing Rev 0 Page 41 of 326 06 707 txl inp sel 3 0 IO Map Address 0x1A03 7 4 This signal is used to select the video source for the HDMI Tx1 Function tx1 inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Primary VSP 0x02 From Ptol Converter 0x03 From Internal OSD Blend 1 0x04 From Secondary VSP Ptol Converter 0x05 From Secondary Input Channel 0x06 From RX Input 0x07 From Internal OSD Blend 2 tx2 inp sel 3 0 IO Map Address 0x1A03 3 0 This signal is used to select the video source for the HDMI T2 Function tx2 inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Primary VSP 0x02 From Ptol Converter 0x03 From Internal OSD Blend 1 0x04 From Secondary VSP Ptol Converter 0x05 From Secondary Input Channel 0x06 From RX Input 0x07 From Internal OSD Blend 2 hd enc inp sel 3 0 IO Map Address 0x1A04 7 4 This signal is used to select the video source for the HD encoder When using the encoder in SD only mode this signal must be set to the same value as sd enc inp sel Function hd en
6. Figure 80 8005 External Sync Mode Block Diagram 3 6 1 Functional Description ADV8005 compares the phase difference between the MAS VS and the internally generated VS out as shown in Figure 80 The phase difference is measured using a fixed crystal clock running at 27MHz The phase difference between the input and output VS signals constitutes an error which must be reduced to zero in order for the outputs to be locked together This is achieved by varying the output clock in order to change the period of the output VS Once the error is reduced to 0 the output video and timing will be locked to the external master This locking process take from 0 5 seconds As the external master sync will always be present and stable this will constitute a start up condition and once locked will remain locked If the input video source is changed at a future time this will not disrupt the relationship between the external master sync and output timing The video output will be locked to within 2 Xtal clock cycles of the externally provided master sync In the worst case scenario where 4k2k is being output on a 297MHz clock the potential pixel difference is 22pixels For 1080p outputs this variation drops to 11 pixels This difference between outputs can be eliminated using a small FIFO Note that this resynchronisation block will also eliminate any cable delay differences between different ADV 8005 systems It is
7. R 288 Interrupt Duration cse ER NARNIA UU 288 81 227 Storing Masked Interr pts esce ERUNT ERR IRI ER UR ERU RR po ERU ERES EAS 289 82 Serial Vid o Rx Interrupts 289 82 1 Introduction 822 nterruptArchitecture Overvie Woo ete t 292 82221 c Multiple IntetFUpUEVebts dece eremo ee ee tee 293 8 23 Serial Video Interrupts Validity Checking Process esee te tetettnnententntentente nte tentenennenne 293 8 3 5 Secti n 293 83 1 Interrupt Architecture Overview etr te eed 294 8 4 Msn cR 294 8 41 Introducti n 294 8 42 Interrupt Architect re Overview soe ERE RUD ERIS pe ERE EE 294 84 3 HDMI Polarity 295 Appendix A ene PCB Layout Recommendations Analogue Digital Video Interface Outputs csceesessesssessesssesessesseessessessssssessesssessessesscssessssssssessscsssssssessesssssnessesssessesseessessesses 296 External DOR Memory Requiremberits EGRE SH PRAE Pe 296 Power SupplycBYpassing ix RE RET tte he General Digital Inputs and
8. Function aud input mode 1 0 Description 00 default Single mode 01 Dual mode TX1 with I2S stream TX2 with SPDIF stream 10 Dual mode TX1 with SPDIF stream TX2 with I2S stream 11 Dual mode TX1 with SPDIF stream 1 TX2 with SPDIF stream 2 Table 56 HDMI Tx Supported Audio Input Modes from Audio Input Pins PinNaud input mode 1 0 0 1 2 3 Single Mode Dual Mode 1 Dual Mode 2 Dual Mode 3 Tx1 Tx2 Tx1 Tx2 Tx1 Tx2 Tx1 Tx2 DSD CLK DSD CLK DSD CLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK SCLK SCLK SCLK SCLK SCLK AUD 0 DSD 0 SPDIF DSD O SPDIF SPDIF SPDIF SPDIF AUD IN 1 DSD 1 12S 0 DSD 1 12S 0 1250 1250 AUD 1 21 50 2 125 1 50 2 125 1 1251 1251 AUD INI 3 50 3 125 2 50 3 125 2 1252 1252 AUD IN A 50 4 125 3 50 4 125 3 1253 1253 AUD 1 5 DSD 5 LRCLK DSD 5 LRCLK LRCLK LRCLK SPDIF 6 11 2 Audio from Serial Video Rx On the ADV8003 it is possible to route audio packets directly from the Serial Video Rx to the HDMI Tx To achieve passthrough of audio from the Serial Video Rx to the HDMI Tx the following bit in the HDMI Tx must be configured rx aud packet sel TX2 Map Address OxFA40B 0 This bit is used to select the source of audio packet data routed into the HDMI transmitter Rev 0 Page 218 of 326 06 707 Function rx aud packet sel Description 0 default Get audio packet from external audio pins 1 Get audio packet from internal audio receiver The datapath can be ena
9. Rev 0 Page 119 of 326 06 707 0 12 bit 4 4 4 YCbCr 4 1 8 bit 4 4 4 YCbCr 3 2 12 bit 4 2 2 YCbCr 4 3 8 bit 4 2 2 YCbCr 2 3 2 3 PVSP Video Output Module Figure 57 shows the structure of the PVSP VOM The direction arrow inside Figure 57 does not capture the real processing order inside the VOM but gives a clear overview of each processing block Video Output Module VOM Noise Reduction Block Mosquito Random CUE Sharpness Correction De interlacer Output Video Port ropper d Pixel UnPacker Read from DDR2 Figure 57 PVSP Video Output Module The VOM has the following main features e Pixel unpacker this module reads the field frame from external memory and unpacks memory words to video pixel information e VOM cropper crops the image read from external memory e De interlacer converts interlaced video to progressive video CUE correction filtering for Color Upsampling Error e Noise reduction removes random mosquito and block noise e Detail and edge sharpness enhancement e Scaler scales video to target resolution e Output port generates output timing and output video Register update protection is provided in the ADV8005 Refer to Section 3 4 for more details regarding how to update the various VSP registers pvsp lock vom Primary VSP Address OxE828 3 This bit
10. pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 pvsp lock vom 0 pvsp update vom 1 De assert pvsp enable ffs 1 dat pvsp enable vim 1 pvsp upcate vom pvsp enable vom 1 pvsp update vom 0 Configure all registers for VOM pvsp enable ffs 1 except display port output pvsp enable vim 1 timing registers pvsp enable vom pvsp update vom 0 Assert pvsp enable ffs 1 pvsp enable vim 1 pvsp update vom pvsp enable vom 1 pvsp lock vom 0 pvsp update vom 1 Figure 72 VOM Set Protocol Flowchart Figure 72 shows the process for the VOM set protocol for the PVSP This is exactly the same for the SVSP with the appropriate registers replaced 3 4 5 Free Access Protocol The free access protocol allows the user to configure all VSP registers regardless of the current configuration of the device This can be seen in Figure 73 Start Configure register End Rev 0 Page 159 of 326 06 707 Figure 73 Free Access Protocol 3 5 HORIZONTAL PRE SCALER A Horizontal Pre Scaler HPS has been implemented on the ADV8005 to extend the scaling functions of the ADV8005 The PVSP and SVSP are limited in the pixel clock frequencies and line lengths which they can handle The HPS block has been designed for scaling between determined video formats as follows 1 Down conversion of video standards with pixel clocks greater than 162MHz and or more than 2048 pixels line Typical use wou
11. 06 707 HDMI R W Register Name Packet Byte No Map Address OxE3DC gamut mdata pb 0 25 PB24 OxE3DD gamut mdata pb 0 26 PB25 OxE3DE m gamut mdata pb 0 27 PB26 OxE3DF gamut mdata pb 0 28 PB27 As defined by the HDMI 1 3 specifications The Gamut Metadata packet registers are considered valid if pkt det gamut is set to 1 refer to Section 8 2 2 for more details gamut irq next field HDMI RX Map Address OxE250 4 This bit is used to set the NEW GAMUT MDATA RAW interrupt to detect when the new contents are applicable to next field or to indicate that the Gamut packet is new This is done using header information of the gamut packet Function gamut irq next field Description 0 default Interrupt flag indicates that Gamut packet is new 1 Interrupt flag indicates that Gamut packet is to be applied next field 5 11 CUSTOMIZING PACKET INFOFRAME STORAGE REGISTERS The packet type value of each set of packet and InfoFrame registers in the Serial Video Rx InfoFrame Map is programmable This allows the user to configure the ADV8005 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the Serial Video Rx port Note Writing to any of the following packet ID registers also clears the corresponding InfoFrame packet detection bit avi packet id 7 0 HDMI RX Infoframe Map Address 0xE3E0 7 0 This control is used to set the AVI InfoFrame ID Function avi packet id 7
12. sere 6 10 6 MPEG InfoFrame 6 10 7 Gamit Metadata eese en oe ette etude oe diee tiee ie ee ia etie eA Audio SEU cese eet GELT Audio ATChIteCt re 218 6 11 2 Audio from Serial Video Rx iere e e 218 6 113 Audio Configuratiob eese t ERI OR ERREUR c te 6 11 3 1 I uu 6 11 3 2 SPDIF Audio 6 11 3 3 DSD AUdIO ces 6 11 3 4 HBR 6 11 4 CTS Parameters 6 11 4 1 IN Paramelerz MM 6 11 4 2 GTS Param eters 6 11 43 Recommended Expected CTS Values a i es 230 6 11 55 Audio Sample Packets o Renee ee D bite 232 6 1L6 Audio InfoErame 236 6 11 7 ACP Packet 6 11 8 ISRC Packet 6 12 EDID Handlihg ix irme tome ape i Hp Uo dr p dU P E E 240 6 123 Reading the csi RH ORE CERRAR HOS CHRONO MIRROR HEREDES 240 6 12 25 EDID Def MUONS en 240 6 12 3 Additional Segments 1 tte i 240 Rev 0 Page 6 of 326 6 12 4 edid tries Control eene e d en oett e neenon 241 6 12 5 EDID Reread ER RR DUREE E 241
13. Function di bnr enable Description 0 default Disable BNR 1 Enable BNR di bnr edge offset 7 0 Primary VSP 2 Map Address OxE98D 7 0 This signal is used to configure the BNR processing ability Function di bnr edge offset 7 0 Description 0x32 Recommended setting for low level BNR 0x64 Recommended value for mid level BNR 0x96 Recommended value for high level BNR di bnr disable local detect Primary VSP 2 Map Address 0xE987 3 This signal is used to configure the BNR processing ability Function di bnr disable local detect 0 1 default Description Recommended setting for high level BNR Recommended setting for low mid level BNR di bnr scale global vert 2 0 Primary VSP 2 Map Address OxE98B 7 5 This signal is used to configure the BNR processing ability Function di bnr scale global vert 2 0 Description 0101 default Recommended setting for low mid level BNR 0110 Recommended setting for high level BNR di bnr scale global hori 2 0 Primary VSP 2 Map Address OxE98B 4 2 This signal is used to configure the BNR processing ability Rev 0 Page 127 of 326 06 707 Function di bnr scale global hori 2 0 Description 0101 default Recommended setting for low mid level BNR 0110 Recommended setting for high level BNR di bnr global strength gain 3 0 Primary VSP 2 Map Address 0xE988 7 4 This signal is used to configure the BNR process
14. 7 0 Address 7 0 Address OxEGGF 7 0 This signal is used to set the start address of field frame buffer 6 Software should arrange memory space properly avoiding conflict between different buffers Function svsp fieldbuffer6 addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 6 3 3 1 5 Frame Latency Depending on the format being input to the ADV8005 and the output required from the SVSP different resolutions will have different frame latencies This is due to the increased processing required on scaling different types of video data This has a certain impact in that the audio will have to be delayed by the same amount Table 30 lists frame latencies in different cases for various resolutions Rev 0 Page 142 of 326 Table 30 Frame Latency Normal Mode Output iFrame Rate 50 Hz 59 94 60 Hz 23 97 24 Hz 25 30 Hz Input Frame Rate Timing 576p 720p 1080 480 720 1080 720p 1080p 720p 1080p p 50 Hz 576p 0 1 1 3 2 0 1 1 3 0 1 1 4 0 1 1 4 720p 1080p 59 94 60 Hz 480p 0 1 1 3 0 1 1 3 0 1 1 4 0 1 1 4 720p 1080p 23 97 24 25 30 2 720 1080 0 1 0 8 0 1 0 8 0 1 1 3 0 1 1 3 1 x x means x x times the input video frame 2 A B means frame latency is not a fixed value it varies between A and B UG 707 When crop or album mode is enabled frame latency will be different from that listed in Table 30 In this case the user
15. A3 12 0 09 4 2 0 2 65C scale Rev 0 Page 86 of 326 06 707 Equation 7 Secondary Input CSC Channel A Output 1 12 0 NET B2 12 0 Cs B3 12 0 4096 4096 4096 Equation 8 Secondary Input CSC Channel B Output B _ BA 12 2 CSC scale C n AS CHEL y pg 212 01 cc E C4 12 a FOSC scale Equation 9 Secondary Input CSC Channel C Output The CSC on the secondary input channel is illustrated in Figure 44 exosd csc mode 4096 exosd al In A x Out A exosd a3 The video inputs A In B and In C connected by default to and B Refer to Table 12 more information The default routing can be changed by adjusting the value ofexosd swap bus ctrl 2 0 Figure 44 Secondary Input Channel CSC Table 12 Default Secondary Input Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In A R Cr In B G Y In C B Cb The 1 to to B3 and to C3 coefficients are used to scale the primary inputs A4 B4 and C4 are added as offsets Floating point coefficients must be converted into 120 bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range 1 1 or 4096 4095 The dynamic range of the CSC is 0 1 for unipolar signals B or 0 5
16. lt lt SVSP_SCAL_OUT_WIDTH SVSP_DP_DECOUNT Figure 68 VOM Output Dimensions svsp_dp_video_h_start 10 0 Secondary VSP Map Address 0xE62E 7 0 Address OxE62F 7 5 This signal is used to set the horizontal start position where the output video of scaler is placed Function svsp dp video h start 10 0 Description 0x000 default Default OxXXX Horizontal start position of output port svsp dp video v start 10 0 Secondary VSP Map Address 0xE630 7 0 Address 0xE631 7 5 This signal is used to set the vertical start position where the output video of scaler is placed Function svsp dp video start 10 0 Description 0x000 default Default OxXXX Vertical start position of output port svsp dp margin color 23 0 Secondary VSP Map Address 0xE643 7 0 Address 0 644 7 0 Address 0xE645 7 0 This signal is used to set the default color in output video in YUV colorspace Rev 0 Page 153 of 326 06 707 Function svsp dp margin color 23 0 Description 0x000000 Default 0 Default color in YUV colorspace svsp dp output blank Secondary VSP Map Address OxE642 5 This bit is used to force the colour output of the Secondary VSP If this register is set to 1 the output of the Secondary VSP is forced to the used defined color in dp margin color Function svsp dp output blank Description 0 default Not Output default Color 1 Output
17. CSC amp ACE 50 Encoder 480p Video from Serial Data _ Transceiver Mg Formatting R amp CSC Figure 14 ADV8005 Mode 4 Configuration Mode 4 places the OSD blend block before the PVSP The output of the PVSP is then input to both the SVSP and the PtoI converter The OSD is overlaid on all output formats In addition high performance PVSP processing is performed on all outputs which can improve video quality at all resolutions While blending the OSD on the incoming video the OSD can be scaled to the necessary resolution of the incoming video using the OSD scaler In the example in Figure 14 the input resolution is taken to be 480p The OSD is downscaled blended and passed to the PVSP which scales to 1080p The advantage of configuring the ADV8005 core in this way is that by including the PVSP on multiple data path additional processing can be included on other outputs also In Figure 14 three different formats 1080p 1080i and 720p can be generated Rev 0 Page 30 of 326 2 1 6 Mode 5 Mode 5 should be used if U6 707 e Two separate upscaled resolutions are required e De interlacing is not required OSD is required on both output formats OSD rendered at a single set resolution 720p DDR2 Memory i Interface Build Primar
18. G6 G5 G4 G3 G2 G1 Table 88 YCbCr Input Formats 8 8 10 12 24 30 36 30 1 ye 16 20 24 BIT 2t EM BIT SDR BIT BIT BIT SD SD SD amp BITDDR 10 BITDDR 12BITDDR eph sp sp sp SDR 225 SDR SDR SDR R 4 2 2 4 2 2 4 2 2 A SDR Es 4 2 2 gen 4 2 2 4 2 2 4 2 2 44 44 44 EAT BE 4 4 4 2 2 2 4 4 42 42 42 4 2 2 2 Cloc Cloc Cloc Cloc Cloc Cloc k k k k k k Rise Fall Rise Fall Rise Fall YCbCr Colourspace OSD OSD 50 OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD _ DE DE DE DE DE DE _DE DE OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD vs VS VS VS 9 VS VS vs VS VS VS VS VS VS _ VS OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD OSD _ OSD OSD OSD GL CL CL CL CL CL CL CL _CL K CLK _CLK CLK K K K K K K K K K K K K OSD 5 _IN 2 9 3 OSD 5 _IN 2 8 2 OSD 5 _IN 2 7 5 1 OSD 5 b 2 e T L o T osp 5 L IN1 5 In 9 P OSD 5 4 8 OSD 5 _INA 3 7 OSD 5 _INA 2 6 OSD 5 _INA 1 5 NE
19. Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb7 Cr7 Cb6 Cr6 Cb5 Cr5 Cb4 Cr4 Cb3 Cb2 Cr2 Cb1 Cr1 Cb0 Y9 Y8 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb9 Cr9 Cb8 Cr8 Cb7 Cr7 Cb6 Cr6 Cb5 Cr5 Cb4 Cr4 Cb3 Cb2 Cr2 Cb1 Cr1 Cb0 Y11 Y10 Y9 Y8 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb1 1 Cr 11 Cb1 0 10 Cb9 Cr9 Cb8 Cr8 Cb7 Cr7 Cb6 Cr6 Cb5 Cr5 Cb4 Cr4 Cb3 Cr3 Cb2 Cr2 Cb1 Cr1 Cr6 Cr5 Cr4 Cr2 Cr1 Cro Y7 Y6 Y5 4 2 1 7 Cr 6 5 9 8 7 Cb 2 Cb 0 Y2 11 Y2 10 Y2 Y2 Y2 Cr 1 Cr 1 Cr 9 Cr5 Cr4 Cr2 Cr1 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO Cb9 Cr6 Cr5 Cr4 Cr2 Cr1 Y6 Y5 Y4 Y3 Y2 Y1 YO Cb4 Cb6 Cb8 2 cre z z z z z z lcps z z Cb5 Cb7 Cre 2 7 C7 7 2 7 2 2 2 097 7 93 95 617 z Cb2 Cb4 Cb6 7
20. rx vs inf cks err edge raw st mb2 clr Edge sensitive Used to indicate if there was an error with the vendor specific InfoFrame rx ms inf cks err edge raw st mb2 clr Edge sensitive Used to indicate if there was an error with the MPEG source InfoFrame rx spd inf cks er r edge raw st mb2 clr Edge sensitive Used to indicate if there was an error with a SPD InfoFrame rx avi inf cks err edge raw st mb2 clr rx deepcolor chn 9 edge raw st mb2 clr Edge sensitive Edge sensitive Used to indicate if there was an error with the AVI InfoFrame Used to indicate if the incoming video is deep color The exact mode can be determined by reading the DEEP COLOR MODE register rx tmds clk chng edge raw st mb2 clr Edge sensitive Used to indicate if the incoming TMDS clock has changed frequency rx pkt err edge raw st mb2 clr Edge sensitive Used to indicate if there was an error with any HDMI packet rx gamut mdata pckt edge raw st mb2 clr Edge sensitive Used to indicate if a gamut metadata packet was detected rx isrc2 pckt edg eraw st mb2 clr Edge sensitive Used to indicate if an ISRC2 packet was detected rx pckt eraw st mb2 clr Edge sensitive Used to indicate if an ISRC1 packet was detected rx vs info frm e dge raw st mb2 clr rx ms info frm e dge raw st mb2 clr Edge sensitive Edge sensitive Used to indicate if a vendor specific InfoF
21. 0 5 for bipolar signals Bipolar signals Pr Pb must be offset to mid range Equations with a dynamic range larger than 1 need to be scaled appropriately using the mode 1 0 control To achieve a coefficient value of 1 0 for any given coefficient exosd_csc_mode 1 0 should be set high and the coefficient should be programmed to a value of 0 5 Otherwise the largest value would be 4095 4096 0 9997 While this value could be interpreted as 1 it is recommended to use the value of 0 5 and set the exosd mode 1 0 bits for maximum accuracy The CSC configurations for common modes are provided in Table 13 Rev 0 Page 87 of 326 06 707 Table 13 Secondary Input Channel CSC Common Configuration Coefficients Color Space Conversion HDTV YCbCr x0C53 0 0800 0 0000 0 1906 0 1 56 0 0800 OxOE85 Ox18BE limited to RGB limited x2 ade 0x0000 0 1 1 Ox1DDC 0 04 0 HDTV YCbCr 0 0700 0 0000 10 1 6 0 005 0 0188 0 0800 0 07 10 007 limited to SDTV YCbCr HDTV YCbCr OxOSEB 0 0000 10 1 58 Ox1FDE 0 01 9 0 0950 limited to SDTV YCbCr full HDTV YCbCr 0 0 OxOEOD 0 0000 0 0000 0 0100 0 0000 OxODBC OxOEOD 0 0100 full to SDTV YCbCr limited SDTV YCbCr OxOAF8 0 0800 0 0000 0 1 84 Ox1A6A 0 0800 OxODDE limited to RGB limited 1 0 csc mode HDTV YCbCr limited to RGB full 0 0 0 limited 0 0 0 SDTV YCbCr
22. 1 B Secondary Input Channel p inp chan sel osd blend inp sel 3 0 RX Input Channel OSD Blend 20 7 8 y 5 Primary Input gt tdi 13 0 OSD x1 inp sel 3 0 Video TTL Input 9 Secondary 2 Input Secondary VSP gt Primary Inout Channel 4 EXOSD TTL Input Channel Secondary Input Channel Primary VSP RX Input Channel P PtoI 26 s inp chan sel 0 osd blend inp 2 sel 3 0 OSD Blend 1 9 Secondary Secondary Input Channel Primary Input Channel gt Ptol Progressive to OSD plena Serial Video OSD Blend 1 Interlaced 2 inp sel 3 0 Channel Secondary Input Channel Input Channe 7 Primary Input HD b M p2i inp sel 3 0 Primary VSP Ptol OSD Blend io Primary Input Channel Primar Secondary gt OSD Blend 1 USE y Secondary Input gt Secondary Input Channel 1 J en 22 P pvsp inp sel 3 0 hd enc inp sel 3 0 ps N SD Primary Input Channel Secondary Primary Input Channel Blend 2 2 VSP Primary VSP Encoder Primary VSP Raw OSD OSD Blend 1 0 Secondary Input gt 25 Se conca RX Input Channel
23. 5 x Kee ddr yc swap 1 Figure 34 DDR Mode and Chroma Swap exosd ddr yc swap IO Map Address 0x1B6A 0 This bit is used to swap the Luma Y and Chroma C data in DDR modes By default Y is expected on the rising edge of the clock Function exosd ddr yc swap Description 0 default Y on rising edge of clock 1 C on rising edge of clock exosd ddr edge sel IO Map Address 0x1B6A 3 This bit is used to select which edge the first sample of DDR data is latched on Rev 0 Page 57 of 326 06 707 Function exosd ddr edge sel Description 0 default Posedge data first 1 Negedge data first Using the pixel clock as a reference ADV8005 expects the Y sample on a rising edge and then a chroma sample on the falling edge When exosd_ddr_yc_swap is set ADV8005 expects a chroma sample on the rising edge and the Y sample on the falling edge exosd_swap_cb_cr_422 can be used to swap the order of the chroma data By default ADV8005 expects a sequence of Cb Cr Cb Cr When exosd_swap_cb_cr_422 is set ADV8005 expects a sequence of Cr Cb Cr Cb exosd_swap_cb_cr_422 IO Map Address 0x1B69 7 This bit is used to swap the order of the C data when decoding 4 2 2 data Function exosd swap cb cr 422 Description 0 default Cb Cr decoding 1 Cr Cb decoding exosd ps444 r444 conv is used to convert from pseudo 444 video data to real 444 All processing occu
24. enabled Function pvsp rnrbuf1 addr 31 Description 0 0x002F7600 Default OxXXXXXXXX Start address of RNR buffer 1 3 2 3 8 Mosquito Noise Reduction The second type of noise reduction algorithm implemented in the ADV8005 is the mosquito noise reduction MNR The MNR block selectively removes ringing artifacts introduced into highly compressed MPEG video data For the best results this block should be enabled when the input video is not being scaled due to the fact that it is easier to identify and remove compressed artifacts at lower resolutions can support both interlaced and progressive input video It can be enabled or disabled by di mnr enable As with the RNR block a certain amount of control is provided to the user This can be controlled using di level 1 0 di enable Primary VSP Map Address 0xE84C 5 This bit is used to enable mosquito noise reduction MNR Function di mnr enable Description 0 default Disable MNR 1 Enable MNR di mnr level 1 0 Primary VSP Map Address OxE84F 3 2 This signal sets the MNR level Function di mnr level 1 0 Description 00 N A 01 Low 10 default Middle 11 High To get better image performance register di th min 3 0 can be used to set the MNR level di th min 3 0 Primary VSP 2 Map Address 0xE917 7 4 This signal is used to set the strength of the mosquito noise reduction MNR The larger the value
25. pvsp dp vsynctime 9 0 Primary VSP Map Address 0xE862 1 0 Address OxE863 7 0 This signal is used to set the vertical synchronous time duration of output timing This register s value will be used while pvsp autocfg output vid is 0 Function pvsp dp vsynctime 9 0 Description 0x000 default Default OxXXX Vsync width of output timing pvsp_dp_vbackporch 9 0 Primary VSP Map Address 0xE864 1 0 Address 0xE865 7 0 This signal is used to set the vertical back porch duration of output timing This register s value will be used while pvsp_autocfg_output_vid is 0 Function pvsp dp vbackporch 9 0 Description 0x000 default Default OxXXX Vertical back porch of output timing pvsp dp vpolarity Primary VSP Map Address OxE869 0 This bit is used to set the polarity of output Vsync This register s value will be used while pvsp autocfg output vid is 0 Function pvsp dp vpolarity Description 0 default Low 1 High pvsp dp hpolarity Primary VSP Map Address 0 869 This bit is used to set the polarity of output Hsync This register s value will be used while pvsp autocfg output vid is 0 Rev 0 Page 132 of 326 06 707 Function pvsp dp hpolarity Description 0 default Low 1 High Table 26 Output Port Configuration Settings for Example Output Resolutions Output Timing decount hfrontporch HSync hbackporch activeline Vfrontporch VSync
26. vs packet id 7 0 Description Packet type value of packet stored in InfoFrame Map Address 0x54 to Packet type value of packet stored in InfoFrame Map Address 0x54 to acp packet id 7 0 HDMI RX Infoframe Map Address OxE3EF 7 0 This control is used to set the ACP Packet ID Function acp packet id 7 0 Description Packet type value of packet stored in InfoFrame Map Address 0x70 to Ox8B Packet type value of InfoFrame stored in InfoFrame Map Address 0x70 to 0 8 isrcl packet id 7 0 HDMI RX Infoframe Map Address OxE3F2 7 0 This control is used to set the ISRC1 Packet ID Function isrc1 packet id 7 0 Description Packet type value of packet stored in InfoFrame Map Address Ox8C to 7 Packet type value of InfoFrame stored in InfoFrame Map Address Ox8C to 7 isrc2 packet id 7 0 HDMI RX Infoframe Map Address OxE3F5 7 0 This control is used to set the ISRC2 Packet ID Function isrc2 packet id 7 0 Description 1XXXXXXX Packet type value of packet stored InfoFrame Map Address 0xA8 to 0xC3 Packet type value of InfoFrame stored in InfoFrame Map Address 8 to 0xC3 gamut packet id 7 0 HDMI Infoframe Map Address 0xE3F8 7 0 This control is used to set the Gamut Metadata Packet ID Functi
27. Figure 76 Using the HPS to Downscale the 4 2 video If the horizontal resolution of the video stream after the HPS is 1920 or less pixels it is also possible to route the video through the PVSP HPS 1280x1600 1080p 60 VESA 2 1 Downsample 2560x1600 Figure 77 Using the HPS to downscale to downscale to less than 1920 horizontal pixels 3 5 2 HPS Upscaling When upscaling video streams with pixel clocks greater than 162MHz or with horizontal resolutions larger than 1920 pixels but smaller than 3840 to video modes with pixel clocks greater than 162MHz the input video has to be routed to the HPS followed by the PVSP E g VESA 2048x1152 162MHz to 4K VESA 2560x1600 Reduced Blanking 268 2 to 4K HPS 1280x1600 VESA 2 1 Downsample 2560x1600 Figure 78 HPS Upscaling When processing video standards with pixel clocks greater than 162MHz and more than 3840 pixels lines a combination of HPS SVSP and PVSP is required Typical use would be converting between different timings e g 4K 24 to 4 24 SMPTE It is not possible however to do frame rate conversions between 4K modes 4kx2k 24 2 1 Downsample Figure 79 HPS scaling for inputs with more than 3840 pixels per line 3 5 3 Using the HPS for converting between 3D to 2D Video formats Other usage scenario of the HPS is the conversion from certain 3D modes to its 2D equivalent The 3D modes which require making use of the HPS are the ones with pixels clocks gr
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29. o 205 8 B x EX 892 the les tea lu Piet E 5 5 ee vr PT 5 2 2 S Figure 6 ADV8005 Functional Block Diagram Rev 0 Page 21 of 326 06 707 1 3 PROTOCOL FOR MAIN PORT The system controller initiates a data transfer by establishing a start condition defined by a high to low transition on SDA while SCL remains high This transition indicates that an address data stream will follow peripherals respond to the start condition and shift the next eight bits 7 bit address and R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse This is known as an acknowledge bit other devices withdraw from the bus at this point and maintain an idle condition In the idle condition the device monitors the SDA and SCL lines for the start condition and the correct transmitted address The R W bit determines the direction of the data A logic 0 on the LSB of the first byte means that the master will write information to the peripheral A logic 1 on the LSB of the first byte means that the master will read information from the peripheral The ADV8005 has a single 8 bit slave address All register maps within the ADV8005 can be accessed through this address through 16 bit addressing and 8 bit data registers The ADV8005 acts as a standard slave device on the bus It interprets t
30. DAC OUTPUT BNC OUTPUT 06398 087 Figure 136 Example of Output Filter for HD 4x Oversampling o CIRCUIT FREQUENCY RESPONSE 0 24n zib 30 MAGNITUDE dB 21 20 18n E 90 T PHASE Degrees 15n 5 3 120 3 12 i A 1 m GROUP DELAY Seconds 180 60 6n E 210 3n 86 1M 10M 100M 1G 5 FREQUENCY Hz 8 Figure 137 Output Filter Plot for SD 16x Oversampling Rev 0 Page 286 of 326 CIRCUIT FREQUENCY RESPONSE 480 18n 400 MAGNITUDE dB 16n 320 14n 240 GROUP DELAY Seconds 12n 160 dB b GAIN 10n 80 8n 6n 80 80 90 1M 10M 100M FREQUENCY Hz 4n 160 2n 240 ig 9 Figure 138 Output Filter Plot for ED 8x Oversampling CIRCUIT FREQUENCY RESPONSE I MAGNITUDE dB 200 Degrees 120 10 GROUP Seconds 20 GAIN dB 8 30 40 50 PHASE Degree 1 o 10 FREQUENCY MHz Figure 139 Output Filter Plot for HD 4x Oversampling Rev 0 Page 287 of 326 200 06398 089 06398 090 U6 707 06 707 8 INTERRUPTS The ADV8005 has a comprehensive set of interrupt registers located in the IO Map and HDMI Main Maps of
31. Digital output N A Digital output Digital output Digital input Digital input N A N A N A N A N A N A N A N A N A N A N A Rev 0 Page 308 of 326 06 707 Location T16 T17 T20 T21 T22 T23 U1 U2 U3 04 07 08 09 010 011 012 013 014 015 017 02 02 02 02 V1 2 v3 V4 V2 v2 2 N 2 w N w W4 Mnemonic GND GND Description if Unused HPD_TX2 HDMI Tx2 Float this pin GND TX2_0 HDMI Tx2 Float this pin TX2 0 HDMI Tx2 Float this pin P 10 Digital video Float this pin as it is disabled by default input P 11 Digital video Float this pin as it is disabled by default input P 12 Digital video Float this pin as it is disabled by default input P 13 Digital video Float this pin as it is disabled by default input GND GND GND GND GND R TX2 GND TX2_C TX2 C GND PVDD6 P 5 GND HDMI Tx2 GND HDMI Tx2 HDMI Tx2 Digital video input Digital video input Digital video input Digital video e HDMI Tx2 HDMI Tx2 Digital video input Digital video input Digital video input Digital video Digital Power Supply 1 8 V HDMI Tx PLL Power Supply 1 8 V This pin is a voltage regulator output Connect a decoupling capacitor between this pin and ground Connect this pin to ground through a 4 7 resistor Connect
32. Field Frame B ffer Addressiand ertt nte onte 109 3 245 Frame Laven Cor cR X 111 32565 Game e 112 sodes 113 3 2 1 8 Freezing Output Video 114 3 2 1 9 Progressive Cadence Detection RI Re ERREUR ne RESERVE ERREUR eee 114 322 PVSP Video Input Module eerte toe ttti Fe Ree Ee OR 116 3 221 VIM n 116 32 292 118 3 22223 Sealer Interpolation 118 3 2 2 4 55 S 119 CA ENIM CUI ERRE CORON COT 119 3 2 3 PVSP Video Output 120 2 Pixel 121 ano WS 1 121 3 2 3 3 M 122 3 23 4 IRI EINER 123 32 35 Cadence Detection M H 123 3 236 125 3 2 3 7 Random Noise Reduction 125 32 3 8 Mosquito Noise Reduction 126 3 2 3 9 NOISE REAUCHON D
33. This bit is used to enable sharpness control Function di sharpness enable Description 0 default Disable sharpness 1 Enable sharpness pvsp srscal scale gain 11 0 Primary VSP Map Address 0xE891 7 0 Address OxE892 7 4 This signal is used to control the sharpness level Function 5 srscal scale gain 11 0 Description 0x000 default Sharpness level 3 2 3 11 Scaler The last block before the VOM output is the scaler which is used to scale the input video to the desired resolution This is very flexible and can support arbitrary resolution conversion and independently scale the input video horizontally and vertically The ADI proprietary scaler algorithms also allow improved performance in the scaling of the input video which improves many common issues associated with scaling video data such as saw tooth edge blurring and ringing The ADV8005 scaler employs contour based interpolation techniques to provide sharp edges and crisp details on high resolution content The embedded compression noise reduction will eliminate mosquito noise and block artifacts The contour based interpolation scaler is capable of upscaling input video formats from 4801 to 4k x 2k formats these include 4k x 2k 30 Hz 4k x 2k 25 Hz 4k x 2k 24 Hz and 4k x 2k 24 Hz Rev 0 Page 128 of 326 06 707 SMPTE When the automatic scaler algorithm selection is enabled the contour based interpolation scaler is used for upscaling and downscal
34. VID VID CL VID VID VID VID CL CL CL vi LK CIK K K CLEK K K K K z Table 89 Alpha Blending Input Formats Alpha Format 0 0 0 1 0 2 0 3 0 4 0 5 0x6 0 7 0 8 0 9 OxA OxB OxC OxD OxE OSD DE Z 2 2 7 2 2 2 2 2 Z 2 2 2 2 OSD VS Z Z 2 2 2 2 2 2 2 2 2 2 2 OSD CLK 2 2 7 7 2 2 2 2 2 Z Z Z OSD IN 23 2 2 2 2 2 2 2 Z Z Z A7 2 Z OSD IN 22 2 2 2 2 2 2 2 2 2 2 2 6 2 2 OSD IN 21 Z 2 2 2 2 Z Z Z Z Z A5 2 2 OSD IN 20 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 OSD IN 19 2 2 2 2 2 2 2 2 2 2 Z A3 2 05 IN 18 2 2 2 2 2 2 2 2 Z 2 2 2 2 Rev 0 320 of 326 06 707 7 5 4 2 1 0 A7 A6 A5 4 2 1 0 1 0 7 5 4 2 1 0 A7 A6 A5 4 A7 A6 A5 A7 A6 A5 4 2 7 5 4 2 1 0 A7 A6 A5 4 7 5 4 2 1 0 2 1 0 OSD 17 OSD IN 16 OSD IN 15 OSD IN 14 OSD IN 13 OSD IN 12 OSD IN 11 OSD IN 10 OSD IN 9 OSD IN 8 OS
35. chg inj ch1 3 0 TX2 Map Address 0xF481 3 0 Binary control of charge injection for data channel 1 with LSB cap value of 77fF chg inj ch2 3 0 TX2 Main Address 0xF482 7 4 Binary control of charge injection for data channel 2 with LSB cap value of 77fF chg inj dk 3 0 2 Main Map Address 0xF482 3 0 Binary control of charge injection for clock channel with LSB cap value of 77fF 6 16 ENABLING AND DISABLING THE HDMI TMDS OTUPUTS The clock and data predriver controls are used to enable or disable the current switching outputs from the ADV8005 HDMI Tx pre en ch0 TX2 Main Map Address OxF480 3 Enable data channel 0 Function pre en chO Description 1 default Enabled 0 Disabled pre en ch1 TX2 Map Address OxF480 2 Enable data channel 1 Function pre en ch1 Description 1 default Enabled 0 Disabled pre en ch2 TX2 Map Address OxF480 1 Enable data channel 2 Rev 0 Page 247 of 326 06 707 Function pre en ch2 Description 1 default Enabled 0 Disabled pre en clk TX2 Main Map Address 0xF480 0 Enable clock channel Function pre en clk Description 1 default Enabled 0 Disabled To disable a TMDS output it is recommended to follow this sequence l Disable the charge injection for the channel 2 Disable the predriver for the channel To enable a TMDS output the opposite sequence should be followed 1 Enable the predriver for the
36. svsp dp hfrontporch 11 0 Secondary VSP Map Address 0xE634 7 0 Address 0xE635 7 4 This signal is used to set the horizontal front porch duration of output timing This register s value will be used while svsp autocfg output vid is 0 Function svsp dp hfrontporch 11 0 Description 0x000 default Default OxXXX Horizontal front porch of output timing svsp_dp_hsynctime 9 0 Secondary VSP Map Address 0xE636 7 0 Address 0xE637 7 6 This signal is used to set the Hsync duration of output timing This register s value will be used while svsp autocfg output vid is 0 Function svsp dp hsynctime 9 0 Description 0x000 default Default OxXXX Hsync width of output timing Rev 0 Page 151 of 326 06 707 svsp dp hbackporch 9 0 Secondary VSP Map Address 0xE638 7 0 Address 0xE639 7 6 This signal is used to set the horizontal back porch duration of output timing This register s value will be used while svsp autocfg output vid is 0 Function 5 5 dp hbackporch 9 0 Description 0x000 default Default OxXXX Horizontal back porch of output timing svsp dp activeline 10 0 Secondary VSP Map Address 0xE63A 7 0 Address 0 63 7 5 This signal is used to set the active line number of output timing This register s value will be used while autocfg output vid is 0 Function svsp dp activeline 10 0 Description 0x000 default Default OxXXX Active lines of output timing svs
37. 0 default Input 1 Output The SPI interface be reset using spi reset 4 2 8 2 SPI Slave Interface The ADV8005 SPI slave interface serial port 1 is used by the MCU to send the OSD data to the DDR2 and to configure the OSD registers Note that the SPI functions provided within the ADI libraries will automatically take care of any SPI transfer between the MCU and ADV8005 Hence the information in this section is provided just so the user can configure the MCU SPI master to match the ADV8005 SPI slave interface and get both of them to communicate properly Apart from this setup the user should not try to access any other SPI register map with the exception of the timer SPI registers since all the OSD SPI communication is handled through the provided ADI firmware The SPI slave can support the following modes e CPOL 0 0 CPOL 0 CPHA 1 e CPOL 1 CPHA 0 CPOL 1 CPHA 1 Figure 89 shows the effect that these settings may have on the data Rev 0 Page 183 of 326 06 707 CS1 CPOL CPHA 50 t b Le 0 1 500 1 L s 1 501 L_ L 1 1 SCK1 L L b Device Address 9 Sub Address lt Data gt lt Data in 1 gt most 76 5 4 32107
38. 00 TO 0 400 TO OxF300 TO OX18 0x1A 0 OxE9FF OxE6FF OxEOFF OxE2FF OxE3FF OxE4FF OxF3FF a x1BFF L SDA H 4 M4 MH M M 9 Pt 0 00 TO OxEEO0 TO 0 000 TO OxF200 TO OxF400 TO OxF600 TO OxF800 TO 0 00 TO 0 TO OxECFF OxEEFF OxFOFF OxF2FF OxF4FF OxF6FF OxF8FF OxFAFF OxFBFF Tx1 MAIN Tx1 EDID Tx1 CEC Tx1 UDP Tx2 MAIN Tx2 EDID Tx2 CEC Tx2 UDP Tx2 TEST MAP MAP MAP MAP MAP MAP MAP MAP MAP Figure 7 Register Map Architecture 09803 021 It is possible to use the subaddresses auto increment feature which allows data to be accessed from the starting subaddress A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without having to update Rev 0 Page 22 of 326 all the registers U6 707 Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations these cause an immediate jump to the idle condition During a given SCLK high period the user should issue only one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADV8005 does not issue an acknowledge and returns to the idle condition If the user exceeds the highest subaddress in auto increment mode the fol
39. 0x03B gv 0x093 bu 0x248 and 0 1 0 Rev 0 Page 263 of 326 06 707 If the ED HD manual CSC matrix adjust feature is enabled and another input standard such as ED is used the scale values for gy gu gv bu and rv must be adjusted according to this input standard color space The user should consider that the color component conversion may use different scale values For example SMPTE 293M uses the following conversion Y 1 402 G Y 0 714Pr 0 344Pb B Y 1 773Pb The programmable CSC matrix is used for external ED HD pixel data and is not functional when internal test patterns are enabled 7 4 10 1 Programming the CSC Matrix If the user needs to manually provide the coefficients for the CSC matrix for ED HD this procedure is followed Enable the ED HD manual CSC matrix adjust feature matrix prog en Set the output to RGB yuv out Disable sync on YPrPb Reg 0xE435 Bit 2 Enable sync RGB optional Reg 0 402 Bit 4 ous The gy value controls the green signal output level the bu value controls the blue signal output level and the rv value controls the red signal output level 7 4 11 SD Luma and Color Scale Control When enabled the SD luma and color scale control feature can be used to scale the SD Y Cb and Cr output levels This feature can be enabled using scale ycbcr en This feature affects all SD output signals regardless of the encoder output that is CVBS Y C
40. 2 0 0390 0 0000 0 0043 oxoF26 0 1 44 0 036 0 0 0 082 0 1893 Ox1F3F 0 0800 0 0367 0 0 71 0 0 0 082 0 1926 Ox1EAC 0 0800 0 04 9 0 0965 OxODBC 0 0000 0 0000 0 0100 0 0000 OxODBC XO6FF 0 19 6 0 1 5 0 0800 0 02 9 0 09 0 0x0 loxoerF 0 1 24 0x1EDD 0 0800 0 0418 0 080 0 0000 0 0000 0 1 6 0 0000 0 0950 0 0000 0 0000 0 0000 0 0000 0 0800 0 97 326 06 707 OxOE85 0 18 0x087C 0 1 77 OxO7EB 0 007 0 08 0x031F OxOEOD 0 0100 OxODDE 0x1913 0x081A 0 1 0x0826 0x1F78 0 091 Ox1F6E 0x0397 0x004D 0x082D 0 0800 0 082 0 0800 OxODBC 0 0100 OxO6FF 0 0800 OxO6FF 0 0800 0x0950 0 1 6 0 0800 0 0000 06 707 2 2 13 Position and Phase Information The ADV8005 can measure picture position and sample quality information and record these in on chip registers This information can be read and used by the software on an external MCU to program the optimum sampling clock frequency and phase for an external Video AFE when it is sampling a VGA type input signal VIDEO SOURCE MONITOR ADV8005 EVAL BOARD Figure 48 Autoposition and Phase Block Diagram SYSTEM SOFTWARE ANALOG FRONT END DEVICE e g ADV7850 Figure 49 Autoposition and Phase Implementation Using System Firmware The autophase block withi
41. 5 8 SYNCSIGNAL POLARITY READBACKS These signals are used to indicate the polarity of the synchronization signals input to the Serial Video Rx input dvi hsync polarity HDMI RX Map Address 0xE205 5 Read Only This bit is a readback to indicate the polarity of the HSync encoded in the input stream Function dvi hsync polarity Description 0 default 1 The HSync is active low The HSync is active high gt Data Enable b gt 35 e HSYNC a Total number of pixels per line d HSync width in pixel unit Active number of pixels per line c HSync front porch width in pixel unit e HSync back porch width in pixel unit Figure 93 Horizontal Timing Parameters dvi vsync polarity HDMI RX Map Address 0xE205 4 Read Only This bit is a readback to indicate the polarity of the VSync encoded in the input stream Rev 0 Page 192 of 326 06 707 Function dvi vsync polarity Description 0 default The VSync is active low 1 The VSync is active high gt b gt 2 2 Data Enable t 2 4 2 HSYNC C gt gt lt gt VSYNC Total number of lines in field 0 Unit is in half lines Actives number of lines in field 0 Unit is in lines VSync front porch width in field 0 Unit is in half lin
42. 6 13 HDCP Handling eee ee te tee et RR PRU 242 6 13 1 No Upstream Devices iiti C ERE EH EH EN RECHERCH S 242 6 132 Multiple Sinks and No Upstream Devices sese tentent entente tente te teen 243 6 13 3 Software Implementation c co po CERRO ER RD BUE EN UN RR RU E ee 244 6134 AV Mute EE 246 6 14 Return d int eni 246 615 Charge Injection Settings concede receive rdv geo dd vene bv 247 6 16 Enabling and Disabling the HDMI TMDS 247 6 17 HDMI TX Source Termination neither ana 248 618 HDMLACR Packet Transmission aai tritt nier E Rer ete e ERR eoi be be b tue ele Ue S 249 Video Encoder Introduction to the ADV8005 eee esee esee entente 250 7 1 250 7 2 Input Configuration 2 c o o eh dre a e a d e eod tet o ee 250 7 3 Output Comfsuration 253 7 4 Additional Design Features eee apre RAP EU A die E Ao ibt dete 254 TAN Output Oversaim pling eite gerer ERR DRE DIRE ri BER 254 7 4 2 Subcarrier Frequency Lock SFL Mode eese tentent entente tentent tn entente nente tentenennenne 255 7 4 3 SD FF RW Synchron
43. Address Ox1ACE 4 This bit is used to control the output enable manual override for spil sclk Function 5 11 sclk oe man en Description 0 Auto 1 default Manual override Rev 0 Page 181 of 326 06 707 spi2 cs man en IO Map Address OX1ACE 3 This bit is used to control the output enable manual override for 2 cs Function Spi2 cs oe man en Description 0 Auto 1 default Manual override spi2 miso oe man en IO Map Address OX1ACE 2 This bit is used to control the output enable manual override for spi2 Function spi2 miso oe man en 0 1 default spi2 mosi oe man en IO Map Address OXLACE 1 Description Auto Manual override This bit is used to control the output enable manual override for spi2 mosi Function 5 2 mosi en Description 0 Auto 1 default Manual override spi2 sclk oe man en IO Map Address Ox1ACE 0 This bit is used to control the output enable manual override for 2 sclk Function Spi2 sclk oe man en Description 0 Auto 1 default Manual override For the majority of functions the SPI ports can be left in automatic mode If using the SPI ports in manual mode the direction of the various pins can be configured using the following bits spil cs oe man IO Map Address Ox1ACD 7 This bit is used to control the output enable for spil chip select Function Sspil cs oe
44. Controlere riais RERO oce cet eee SE 147 3 3 2 5 7 147 xpHCMENU CONTOCR 148 3 3 3 SVSP Video Output Module 149 333 15 PixelUtipacketz c ss te HR NN 149 23 522 MOM Cropper ARR t ERE TREES HERRERA Etienne rae ee e WEE a d 150 3 3 3 3 Output 151 32 34 lt 154 313 3 55 Progressive to Interlaced Converter iS ERUIT NN ER 154 3 4 VSP Register Access 155 Rev 0 Page 4 of 326 3 4 1 Bootup Protocol 3 4 2 Reboot Protocol 343 Gentle Reb ot Protocol tete cae 158 IAA Set Protocol i saco REP E NERVES 159 2 45 Free Access Protocol 159 3 5 Horizontal Pre scaler 3 5 SARS 3 52 Edu 3 53 Using the HPS for converting between 3D to 2D Video formats ettet 163 3 5 4 by Side Full eue M 165 3 5 5 3D Sideby Side Full ene ete oe ente ee ea ice re a e i es 166 3 6 External Sync Mode
45. D D D D D D P 33 Digital video Float this pin as it is disabled by default input D D D D D D D D D GN GN GN GN GN GN GN GN GN GND cp feon OOO ooo iy E ND ND ND ND ND ND ND ND ND ND ND TX1_C HDMI Tx1 Float this pin TX1 C HDMI Tx1 Float this pin P 28 Digital video Float this pin as it is disabled by default input P 29 Digital video Float this pin as it is disabled by default input HPD TX1 HDMI Tx1 Float this pin P 30 Digital video Float this pin as it is disabled by default input P 31 Digital video Float this pin as it is disabled by default input D GN GND Ground Pin Type N A N A N A N A N A N A N A N A N A N A N A N A Digital output N A Digital output Digital output Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO N A N A N A N A N A N A N A N A N A N A N A Analog input 5V Tol N A Digital output Digital output Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO N A N A N A N A Rev 0 Page 306 of 326 06 707 Location M11 M12 M13 M1 M15 M16 M17 M2 M2 BK 2 N M2 w N1 N2 N3 N4 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N2 o N2 c N22 N23 P1 P2 P3 P4 P7 P8 Mnemonic Description if Unused S olola Z
46. DAC outputs thus resulting in reduced BOM costs Table 70 shows the various oversampling rates supported in the ADV8005 encoder core Two PLLs are used for oversampling the analog output video depending on the mode When SD modes only are being output PLL1 is used for output oversampling When HD modes only are being output PLL2 is used for output oversampling In dual modes where both SD and HD formats are being output PLL1 and PLL2 are both used for SD and HD video respectively Encoder Map Address OxE400 1 This bit is used to control the PLL and oversampling This control allows the internal PLL 1 circuit to be powered down and the oversampling feature to be switched off By default this is disabled setting this bit to 0 enables this feature Function pll pdn Description 0 PLLOn 1 default PLL Off Table 70 Output Oversampling Modes and Rates Input Mode PLL and Oversampling Control Oversampling Mode and Rate Register OxE401 Register 400 Bit 1 Bits 6 4 SD only p 3983 SD only y 55 ED only p ED only g HD only a_i HD only SD and ED SD 2x and ED 8x SD and ED 5 16 8 SD and HD SD 2x and HD 4x SD and HD SD 169andHD 4 ED only at 54 MHz ED only at 54 MHz 1x ED only at 54 MHz 0 ED only at 54 MHz 8x 7 4 2 Subcarrier Frequency Lock SFL Mode The ADV8005 encoder core be used in Subcarrier Fre
47. Description 0 default Input 1 Output spil miso oe man IO Map Address 0x1ACD 6 This bit is used to control the output enable for spil master in slave Function spil miso man 0 default 1 Description Input Output spil mosi oe man IO Map Address 0x1ACD 5 This bit is used to control the output enable for spil master out slave in Function spi1 mosi oe man Description 0 default Input 1 Output spil sclk oe man IO Map Address 0x1ACD 4 This bit is used to control the output enable for spil serial clock Rev 0 Page 182 of 326 06 707 Function 5 11 sclk oe man Description 0 default Input 1 Output spi2 cs oe man IO Map Address 0x1ACD 3 This bit is used to control the output enable for spi2 chip select Function Spi2 cs oe man Description 0 default Input 1 Output spi2 miso oe man IO Map Address 0x1ACD 2 This bit is used to control the output enable for spi2 master in slave Function 5 12 miso man Description 0 default Input 1 Output spi2 mosi oe man IO Map Address Ox1ACD 1 This bit is used to control the output enable for spi2 master out slave in Function spi2 mosi oe man Description 0 default Input 1 Output spi2 sclk man IO Map Address 0x1ACD 0 This bit is used to control the output enable for spi2 serial clock Function Spi2 sclk oe man Description
48. Figure 50 8005 Auto Phase Software Flow Chart Rev 0 Page 99 of 326 06 707 Hur Acfree Start Hor Sync H Back Perch Har spac Time Banter H Rijt Banter 1 HorzontalAcive Viden 1 L e HuriznnislAndesmhleVilen 5 5 4 HSymc _ i Ver Sac ime T 1 1 1 1 1 1 1 1 1 1 1 1 Vist 1 BLANKING ADDRESSABLE VIDEO d PA 60 CAP 7e Y TM Lem V 4 Ver Sh VSync Figure 51 Graphics Video Timing Parameters Similar to the autophase the auto position block is designed to tune the ADC sampling clock frequency in a device with an analog front end To carry it out the block will analyse the graphics input and return the top bottom left and right pixel vacancy numbers This information along with the input standard format can then be used to adjust the ADC sampling clock frequency Figure 51 shows the timing parameters for graphics inputs It returns the number of pixels from e End of HSync to the start of active video e End of Active video to start of HSync The autoposition also returns the number of lines from e End of VSync to start of active video e End of active video to start of VSync The readbacks are updated with every VSync period It is required that the input to t
49. VIM Cropper The VIM cropper block is used to define a sub window within the given input resolution This cropped image becomes the video which is processed by the PVSP The following registers are used to define this sub window e pvsp vim crop enable e pvsp vim crop h start 10 0 e pvsp vim crop v start 10 0 e pvsp vim crop width 10 0 e pvsp vim crop height 10 0 To enable cropper block in VIM pvsp vim crop enable should be asserted pvsp vim crop enable Primary VSP Map Address 0xE883 6 This bit is used to enable the VIM crop Function pvsp vim crop enable Description 0 default Disable VIM Crop 1 Enable VIM Crop Figure 56 shows the correlation between this cropped image and the input video Input Video VSP3D VIM CROP V START Cropped Image VSP3D VIM CROP START VSP3D VIM CROP HEIGHT VSP3D VIM CROP WIDTH Rev 0 Page 116 of 326 Figure 56 VIM Crop Dimensions pvsp vim crop h start 10 0 Primary VSP Map Address 0 832 2 0 Address 0xE833 7 0 This signal is used to set the horizontal start position of the VIM cropper U6 707 Function pvsp vim crop h start 10 0 Description 0x000 default Default 0 Horizontal start position of VIM input pvsp vim crop v start 10 0 Primary VSP Map Address 0xE834 2 0 Address 0xE835 7 0 This signal is used to set the vertical start position of the VIM cro
50. YPrPb and RGB scale ycbcr en Encoder Map Address OxE487 0 This bit is used to enable the SD luma and colour scale control feature Function scale ycbcr en Description 1 Enabled 0 default Disabled When enabled three 10 bit registers SD Y scale SD Cb scale and SD Cr scale control the scaling of the SD Y Cb and Cr output levels The SD Y scale register contains the scaling factor used to scale the Y level from 0 0 to 1 5 times its initial level The SD Cb scale and SD Cr scale registers contain the scaling factors used to scale the Cb and Cr levels from 0 0 to 2 0 times their initial levels respectively The registers needed to scale the outputs are contrast 9 0 cb scale 9 0 and scale 9 0 contrast 7 0 IO Map Address 0x1A2B 7 0 This register is used to adjust the contrast value for Y channel This register uses 1 7 notation Function contrast 7 0 Description 0x00 Gain of 0 0x80 Unity gain OxFF Gain of 2 cb scale 9 0 Encoder Map Address OxE49E 7 0 Address 0xE49C 3 2 This signal is used to set the SD Cb scale value Rev 0 Page 264 of 326 06 707 cr scale 9 0 Encoder Map Address 0 49 7 0 Address OxE49C 5 4 This signal is used to set the SD Cr scale value To use this function the values to be written to these 10 bit registers are calculated using the following equation Y Cb or Cr Scale Value Scale Factor x 512 For example if Scale Factor 1 3 Y Cb o
51. default 256 fs 10 384 fs 11 512 fs mclk en TX2 Map Address 0xF40B 5 This bit is used to select the audio master clock that is used by the audio block Function mclk en 0 default 1 Description Use internally generated MCLK Use external MCLK Table 57 Valid Configuration for audio mode 1 0 audio input sel Value audio mode Value Corresponding Configuration Options 0b010 ObOx DSD in raw mode 061 DSD in SDIF 3 mode 0b011 0600 HBR input as 4 streams with Bi Phase Mark BPM encoding 0601 HBR input as 4 stream without BPM encoding 0b10 HBR input as 4 stream without BPM encoding 0b11 HBR input as 1 stream without BPM encoding Table 58 Audio Input Format Summary Input Output audio input audio mode 125 format Audio Clock Pins Encoding ADV8005 Format Packet Type sel Value Value Value Input Input Pin Signal Mapping 0b000 ObXX 0b00 I2S 3 0 SCLK Normal AUD_IN 4 0 Standard Audio LRCLK AUD_IN 5 125 Sample SCLK Packet MCLK 0b000 ObXX 0b01 125 3 0 Normal AUD_IN 4 0 Right Audio LRCLK AUD_IN 5 justified Sample lt Packet MCLK 0b000 ObXX 0b10 125 3 0 Normal AUD IN 4 0 Left justified Audio LRCLK AUD IN 5 Sample SCLK Packet MCLK 0b000 ObXX 0b11 I2S 3 0 SCLK Normal AUD_IN 4 0 AES3 direct Audio LRCLK AUD IN 5 Sample lt Packet MCLK Rev 0 Page
52. it is recommended to use the value of 0 5 and set the scaling factor 1 0 bits for maximum accuracy The CSC configurations for common modes are provided in Table 18 Table 18 HDMI Tx CSC Common Configuration Coefficients Rev 0 Page 96 of 326 Color Space Conversion HDTV YCbCr limited to RGB limited HDTV YCbCr limited to RGB full HDTV YCbCr limited to SDTV YCbCr limited HDTV YCbCr limited to SDTV YCbCr full HDTV YCbCr full to SDTV YCbCr limited SDTV YCbCr limited to RGB limited SDTV YCbCr limited to RGB Full SDTV YCbCr limited to HDTV YCbCr limited SDTV YCbCr limited to SDTV YCbCr full SDTV YCbCr full to HDTV YCbCr limited RGB limited to HDTV YCbCr limited RGB limited to SDTV YCbCr limited RGB limited to RGB full RGB full to HDTV YCbCr limited RGB full to SDTV YCbCr limited RGB full to RGB limited Identity Matrix Output Input 1 0 csc_mode a 0 0800 0 0000 0 1906 0 1 56 0 0800 0x04AD 0 0000 loxiciB loxiDDC 0 04 0 x07DD 0 0000 0 1 6 0 0058 0 0188 0 0800 0 0000 0 1 58 1 0 01 9 0 0950 0x0 0 0 00 0 0000 0 0000 0 0100 0 0000 lOxODBC dd 0 0800 0 0000 0 1 84 Ox1A6A 0 0800 0 04 0 0000 0 1 81 0 1 0 04 0 0000 0 0099 oxiF99 0 1 56 0 0800 ep 0 0000 0 0000 oxiF6E 0 0000 0 0950 0
53. limited to HDTV YCbCr 0 0x0833 0 0000 0x0099 Ox1F99 Ox1E56 0 0800 0 0826 0x1F78 limited SDTV YCbCr 0 0 091 0 0000 0 0000 Ox1F6E 0 0000 0 0950 0 091 Ox1F6E limited to SDTV YCbCr full SDTV YCbCr x2 0x039D 0 0000 0 0043 OxOF26 0 1 44 0x036F 0x0397 0 0040 full to HDTV YCbCr limited RGB limited 0 0 0 082 0x1893 Ox1F3F 0 0800 0 0367 0 0 71 0x082D 10 0800 to HDTV YCbCr limited RGB limited 0 0 0 082 0 1926 Ox1EAC 0 0800 0 04 9 0 0965 0 082 10 0800 to SDTV YCbCr limited 0 OxODBC 0 0000 0 0000 0 0100 0 0000 0 OxODBC 0 0100 to RGB full RGB full to 0 0 HDTV YCbCr 0 RGB limited XO6FF 0 19 Ox1F5B 0 0800 0 02 9 0 09 OxO6FF 0 0800 limited RGB full to xO OxO6FF 0 1 24 Ox1EDD 0 0800 0 0418 0 080 OxO6FF 0 0800 SDTV YCbCr limited RGB full to 0 1 0 0950 0 0000 0 0000 0 1 6 0 0000 0 0950 0x0950 Ox1F6B Rev 0 Page 88 of 326 SDTV YCbCr 2 0 0669 0 04 0 0000 0 1 81 Ox1CBC OxO4AD 0x081A Ox1BA9 limited to RGB full x1 x1 x1 x1 x1 x1 1 06 707 Color Space B2 B3 BA C1 C2 Conversion RGB med PP Identity Matrix Ox1 0 0800 0 0000 0 0000 0 0000 0 0000 0 0800 0 0000 0 0000 0 0000 0 0000 Output Input 2 2 12 3 RX Input Channel CSC csc_mode The CS
54. pvsp dp output blank Primary VSP Map Address OxE869 2 This bit is used to force the colour output of the Primary VSP This If this bit is set to 1 the output of Primary VSP is forced to the user defined color in pvsp dp margin color Function pvsp dp output blank Description 0 default Not output default color 1 Output default Color 3 2 3 14 Demo Function ADV8005 supports automatically splitting the display window to demo several processing functions of ADV8005 pvsp_demo_window_enable can be used to enable the demo function pvsp_demo_window_enable Primary VSP Map Address 0xE87E 7 Enables demo window Function pvsp_demo_window_enable Description 0 default Disable demo window 1 Enable demo window pvsp_demo_window_use_lower_screen can be used to set the position of the demo window If this bit is set to 1 the lower half display window is used for certain processing function otherwise the upper half display window is used pvsp demo window use lower screen Primary VSP Map Address 0 87 6 This bit is used to enable a demo mode on the lower half of the screen If this bit is set to 1 the lower half display window will be used for certain processing functions otherwise the upper half display window will be used Function pvsp demo window use low Description er screen 0 default Use upper half screen as demo window 1 Use lower half screen as demo window The following regis
55. the panorama function can be enabled using m scaler panorama en In effect this stretches the left and right most sides of the input video to fill the output resolution This method keeps the original ratio in the centre of the screen Figure 60 explains the panorama mode scaling feature imm 1920 mM 720 SERERE 480 1080 Input video Input video stretched scaled normally Panorama position Figure 60 Panorama Scaling Feature m scaler panorama en Primary VSP Map Address OxE850 0 This bit enables panorama scaling for the VOM scaler Function m scaler panorama en Description 0 default Disable VOM panorama 1 Enable VOM panorama The position from which the output video becomes stretched is controlled using m scaler panorama pos 11 0 This allows the user to control the width of the sides of the output image Refer to Figure 60 for more details m scaler panorama pos 11 0 Primary VSP Map Address 0xE851 3 0 Address 0xE852 7 0 This signal is used to define the width of the output video frame which is not stretched when panorama mode is enabled but rather is scaled properly The maximum value of this register is set by di crop width pvsp scal out width pvsp di crop height pvsp scal out width 2 This register sets half the width of the output frame which is to be scaled normally By default this register is set to
56. 0 lt INPUT VIDEO HORIZONTAL RESOLUTION 1 e 0 lt vim crop v start 12 0 lt INPUT VIDEO VERTICAL RESOLUTION 1 e svsp vim crop h start 12 0 svsp vim crop width 12 0 lt INPUT VIDEO HORIZONTAL ACTIVE PIXELS Rev 0 Page 145 of 326 06 707 e svsp vim crop v start 12 0 svsp vim crop height 12 0 lt INPUT VIDEO VERTICAL ACTIVE PIXELS 3 3 2 2 Scaler The size of the active image being sent to the SVSP is configured using svsp vim crop height 12 0 and svsp vim crop width 12 0 as mentioned in Section 3 3 22 The output of the SVSP scaler can be set using svsp vim scal out height 10 0 svsp vim scal out width 10 0 or it can be automatically set per svsp autocfg output vid 7 0 These registers should be set to the resolution of the output video svsp scal out enable Secondary VSP Map Address OxE662 5 This bit is used to enable manually setting scaler output resolution Function svsp man scal out enable Description 0 default Disable 1 Enable svsp vim scal out height 10 0 Secondary VSP Map Address 0xE624 7 0 Address 0xE625 7 5 This signal is used to set the output vertical resolution of scaler in the VIM Function svsp vim scal out height 10 Description 0 0x000 default Default OxXXX Output height of VIM scaler svsp vim scal out width 10 0 Secondary VSP Map Address 0xE622 7 0 Address 0xE623 7 5 This signal is used to set the o
57. 0 to 1 for 10 times consecutively Function edid reread Description 0 default No action 1 Request the EDID HDCP controller to read the EDID 6 13 HDCP HANDLING 6 13 1 One Sink and No Upstream Devices The ADV8005 has a built in controller the Tx EDID HDCP controller which handles HDCP transmitter states including handling downstream HDCP repeaters To activate HDCP from a system level the host controller needs to set hdcp desired to 1 and frame encryption en to 1 This informs the ADV8005 that the video stream it outputs should be encrypted The ADV8005 takes control from there and implements all the remaining tasks defined by the HDCP 1 4 specification Before sending audio and video the BKSV of the downstream sink should be compared with the revocation list which is compiled by managing System Renewability Messages SRMs provided on the source content for example DVD Blue ray Disc and the bksv flag int interrupt bit should be cleared After the HDCP link is established between the ADV8005 and the downstream sink the system controller should monitor the status of HDCP by reading enc on every two seconds The Tx EDID HDCP controller error interrupt will activate and hdcp error int will be set to 1 if there is an error relating to the controller The meaning of the error can be determined by checking hdcp controller 3 0 bksv flag int TX2 Main Map Address OxF497 6 This bit is used to readback and control th
58. 01 2 0 8192 to 8190 10 4 0 16384 to 16380 11 4 0 16384 to 16380 The characteristic equations for the primary input CSC are provided in Equation 4 Equation 5 and Equation 6 AI 12 0 A2 12 0 Ln A3 12 0 4096 4096 4096 Equation 4 Primary Input CSC Channel A Output Out 4 12 o g 2 5 scale BII2 0 212 0 8312 0 4096 4096 4096 Equation 5 Primary Input CSC Channel B Output Out B 2 4 12 2 CSC _scale _ _ p 212 01 oS Je C4 12 a 63 Equation 6 Primary Input CSC Channel C Output The CSC on the primary input channel is illustrated in Figure 43 vid csc mode vid a1 va vid a4 In A vid a2 In B x 3 Figure 43 Primary Input Channel CSC The video inputs A In B and In C are connected by default to and B Refer to Table 10 for more information The default routing can be changed by adjusting the value of vid swap bus ctrl 2 0 Rev 0 Page 84 of 326 06 707 Table 10 Default Primary Input Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In A R Cr In B G Y In B Cb The A1 to to B3 and to C3 coefficients are used to scale the primary inputs A4 B4 and C4 are added as offsets Floating point coefficients
59. 0600000000 Data Byte 15 OxF3F3 R W spare4_pb16 7 0 0b00000000 Data Byte 16 OxF3F4 R W spare4_pb17 7 0 0b00000000 Data Byte 17 OxF3F5 R W spare4_pb18 7 0 0b00000000 Data Byte 18 OxF3F6 R W spare4_pb19 7 0 0b00000000 Data Byte 19 OxF3F7 R W spare4_pb20 7 0 0b00000000 Data Byte 20 OxF3F8 R W spare4_pb21 7 0 0b00000000 Data Byte 21 OxF3F9 R W spare4_pb22 7 0 0b00000000 Data Byte 22 OxF3FA R W spare4 pb23 7 0 0600000000 Data Byte 23 OxF3FB R W spare4 pb24 7 0 0600000000 Data Byte 24 OxF3FC R W spare4 pb25 7 0 0600000000 Data Byte 25 OxF3FD R W spare4_pb26 7 0 0b00000000 Data Byte 26 OxF3FE R W spare4_pb27 7 0 0b00000000 Data Byte 27 6 7 SYSTEM MONITORING 6 7 1 General Status and Interrupts The ADV8005 utilizes both interrupts and status bits to indicate the status of internal operations and errors in the Tx core These interrupt and status are listed in Table 50 Table 51 and Table 52 Refer to Section 8 4 for details on the use of Tx interrupts Table 50 HDMI Tx Interrupt Bits in HDMI Tx Map Register OXEC96 Bit Name Bit Position Description 1 Second LSB When set to 1 indicates that HDCP EDID state machine transitioned from state 3 to state 4 Once set it remains high until it is cleared by setting it to 1 hdcp authenticated int edid ready int 2 When set to 1 it indicates that EDID has been read from Rx and is available in Packet Map Once set it remains high until it i
60. 0800 MN 0 04 0 0000 0 1 81 0 1 0 04 0 0000 0 0099 oxiF99 0 1 56 0 0800 ep 0 0000 0 0000 oxiF6E 0 0000 0 0950 0 2 0x039D 0 0000 0 0043 0 0 26 0 1 44 0 036 0 0 0 082 0 1893 Ox1F3F 0 0800 0 0367 0 0 71 0 0 0 082 0 1926 Ox1EAC 0 0800 0 04 9 0 0965 OxODBC 0 0000 0 0000 0 0100 0 0000 OxODBC 0 0 OxO6FF 0 19 6 Ox1F5B 0 0800 0 02 9 0 09 0 0 OxO6FF 0 1 24 OxTEDD 0 0800 0 0418 0 080 0 1 0 0950 0 0000 0 0000 Ox1F6B 0 0000 0 0950 Identity matrix Ox1 0 0800 0 0000 0 0000 0 0000 0 0000 0 0800 0 91 326 06 707 OxOE85 0 18 0x087C 0 1 77 OxO7EB 0 007 0 08 0x031F OxOEOD 0 0100 OxODDE 0x1913 0x081A 0 1 0x0826 0x1F78 0 091 Ox1F6E 0x0397 0x004D 0x082D 0 0800 0 082 0 0800 OxODBC 0 0100 OxO6FF 0 0800 OxO6FF 0 0800 0x0950 0 1 6 0 0800 0 0000 06 707 2 2 12 4 TTL Output CSC Models of ADV8005 which provide TTL output now have a CSC in that path allowing for example theTTL output video to be converted to RGB The TTL output CSC has the same structure as the primary input CSC but it is limited to a maximum pixel clock frequency of 162MHz For higher pixels rates the HDMI TX should be used The CSC must be manually configured for each color space conversion The CSC on the TTL output
61. 126 3 2 3 10 Sharpness Enhancements M 128 3 2 3 11 128 3 2 3 12 130 3 2 3 13 131 3 2 3 14 ME 134 3 2 3 15 Progressive to Interlaced Converter e e e aia e MR HERR eet eene eie diete 135 3 2 3 16 Automatic Contrast Enhancemenitissssssisssssssssarsscssossssssorsssssossssesscesssssssssescavecsuscescsuscesctssensssavsrsssavenssenecthecssethecsserhocnscchectscenestsssrene 136 3 3 Secondary VIP 136 Introduction to S VSP ran e T A T 136 3 3 11 EM i ori cL COE d 138 3 3 12 Customized Input Output Video Format 140 3 313 Frame NUMO E P P9 141 3 14 Frame Buffer Address and 126 141 3 3 1 5 Frame Latency 3 3 1 6 Freezing Output 144 3 2322 SVSP Video Input Module VIM 144 3 3214 VIM Croppes M 144 BBD DS 29 8 2220 EE AEAEE H M 146 3 3 2 3 Scaler Interpolation iiit sE AEREE AA 146 332A VIM Miscellaneous
62. 172 of 326 06 707 OSD Scaler Input Video 1 Output Video 1 Alpha Blending Figure 83 OSD Scaler and Blending Top Level Diagram 4 2 4 External Alpha Blending The ADV8005 features an external alpha blend input which is shared with the input pixel port The external alpha blend can only be used in conjunction with the EXOSD input This allows the option to specify an external alpha blend value for the EXOSD TTL input channel The options for routing the external alpha blend value are outlined in Table 89 The external alpha blend function is enabled via SPI 4 2 5 OSD Core The OSD core generates the internal data for the OSD display It accesses the DDR2 memory through a DMA controller to load the required resources reg osd enable is used to enable the OSD core on the ADV8005 reg osd enable OSD Address 0 00 0 The enable bit of OSD core Function reg osd enable Description 0 Disables OSD core 1 Enables OSD core osd reset is used to reset the whole OSD core 084 reset IO Address OXIAFD 1 This register bit resets the OSD core Function osd reset Description 0 Default 1 Resets OSD core 4 2 5 1 OSD Core Region Definition Rev 0 Page 173 of 326 06 707 region defines an area on the plane as shown in Figure 84 The regions are derived from the OSD components defined in the Blimp OSD software and therefore contain the differen
63. 2 7 0 OxEE34 7 0 byte 2 bksv10 byte 3 7 0 OxEE35 7 0 byte 3 bksv10 byte 4 7 0 OxEE36 7 0 byte 4 11 bksv11 byte 0 7 0 OxEE37 7 0 byte 0 bksv11 byte 1 7 0 OxEE38 7 0 byte 1 bksv11 byte 2 7 0 OxEE39 7 0 byte 2 bksv11 byte 3 7 0 OxEE3A 7 0 byte 3 bksv11 byte 4 7 0 OxEE3B 7 0 byte 4 12 bksv12 byte 0 7 0 OxEE3C 7 0 byte 0 bksv12 byte 1 7 0 OxEE3D 7 0 byte 1 bksv12 byte 2 7 0 OxEE3E 7 0 byte 2 bksv12 byte 3 7 0 7 01 byte 3 bksv12 byte 4 7 0 OxEE40 7 0 byte 4 The BKVS interrupt bit bksv flag int set to 1 should be cleared by setting bksv flag int to 1 after each set of BKSVs is read To check when authentication is complete the system should monitor hdcp controller state 3 0 and wait until this field reaches the value or state 4 At this time the last host controller should be used to compare the BKSV list read from the sink with the revocation list Once the host controller has verified none of the BKSVs read from the sink are revoked the ADV8005 can be configured to send content down to the sink bksv_count 6 0 2 Main Map Address 0xF4C7 6 0 Read Only This signal is used to specify the total number of downstream HDCP devices Function bksv count 6 0 Description XXXXXXX Total number of downstream HDCP devices 6 13 3 Software Implementation Figure 108 shows a block diagram of HDCP software implementation for all cases using the ADV8005 Tx HDCP EDID controller state machin
64. 3 g 8 o a o g 9 S S g S 9 o gt w S 8 8 9 gt 2 2 3 3 3 lt 9 E 8 83 9 g 8 8 E 8 8 8 5 al 8 8 2 b 5 5 E 5 QO Q O O O O lt gt gt 9 gt lt gt DDR2 CONTROLLER INTERF ACE f AUDIO DATA CAPTURE _ HDCP AND EDID DDCi SCL mn CONTROLLER PUN DDC2 SDA RX_1P AUTO HPD TX1 1NO POSITION TX2 RX 2 AUTO PHASE HDCP 2 RECEIVER 504 ENCRYPTION RX CPO uk OSD VIDEO CN 325 BEEND HDMI Tx 4 2 2 lt 4 4 4 TX1_0 120 HPDQ 86 VIDEO DATA cot TX RX_5VO CAPTURE LOR SPACE TMDS TX CONVERTER OUTPUTS TX1 2 2 P 35 0 TX1 DIGITAL Y Y Y TX 6 VIDEO DE INTERLACER VIDEO SCALING AND VSO CAPTURE oo AND CADENCE ENHANCEMENT FRAME RATE GENERATION HDCP AND DETECTION CONVERSION ENCRYPTION DEO 265 255 RANDOM 8o MOTION SCALES BITMAP OSD TX2 04 PCLK DETECTION NOISE CONTROLLER HDMI Tx 4 2 2 4 4 4 2 0 REDUCTION AND VIDEO DATA coL Nance TX2 1 55 x CAPTURE TMDS TX2 1 050 HS 225 LOW ANGLE MOSQUITO SCALER x OUTPUTS 2 2 SCALER 2 2 E PROCESSING REDUCTION TX2 C DEO osp vipeo 325 2 6 BLOCK OSD_CLK CAPTURE 89 CADENCE NOISE 15573 E 050 14121 AND DETECTION REDUCTION CONVERTER FORMATTING P
65. 4 This signal is used to set the adaptive filter gain 2 for the ED HD standard This is value B Function fil resp bb 3 0 Description 0000 default Gain B O 0001 Gain B 1 0111 Gain B 7 1000 Gain B 8 1110 Gain B 2 1111 Gain B 1 fil resp cb 3 0 Encoder Map Address 0xE45A 7 4 This signal is used to set the adaptive filter gain 3 for the ED HD standard This is value B Function fil resp cb 3 0 Description 0000 default Gain B O 0001 Gain B 1 0111 Gain B 7 1000 Gain B 8 1110 Gain B 2 1111 Gain B 1 fil resp ca 3 0 Encoder Map Address OxE45A 3 0 This signal is used to set the adaptive filter gain 3 for the ED HD standard This is value A Rev 0 Page 275 of 326 06 707 Function fil resp ca 3 0 Description 0000 default Gain AO 0001 Gain A 1 0111 Gain 7 1000 Gain 8 1110 Gain A 2 1111 Gain A 1 7 4 18 3 ED HD Adaptive Filter Modes Two adaptive filter modes are available mode A and mode B Mode A is used when the ED HD adaptive filter mode control is set to 0 In this case filter B LPF is used in the adaptive filter block In addition only the programmed values for Gain B in the ED HD sharpness filter gain register and ED HD adaptive filter Gain 1 Gain 2 and Gain 3 registers are applied when needed The Gain A values are fixed and cannot be changed Mode B is used when ED HD adaptive filter mode control is set to 1 In this mode a cascade
66. 4 7 resistor DDR DMIO DDR interface Float this pin DDR DMI 3 DDR interface Float this pin DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 29 DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 31 DDR A 12 DDR interface Float this pin DDR A 6 DDRinterface Floatthis pin DDR DQ 12 DDR interface Connect this pin to ground through a 4 7 resistor DDR DOS 1 DDR interface Connect this pin to ground through a 4 7 resistor DDR DO 8 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 13 DDR interface Connect this to ground through a 4 7 resistor DDR DO O DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 5 DDR A 3 DDRinterface Floatthis pin DDR interface Connect this pin to ground through a 4 7 resistor DDR DOS 0 DDRinterface Connectthis pin to ground through a Rev 0 Page 311 of 326 Pin Type Digital output N A Digital output N A Digital output Digital output N A Bi directional digital IO N A Digital output Digital output N A N A Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Digital output Bi directional digital IO Digital output Bi directional digital IO Bi directional digital IO Digital output Digital output Digital output Digital output Digital out
67. 53 5761200 540 55 480 240 56 or 57 4801240 58 or 59 VGA 200 SVGA 201 XGA 202 WXGA 203 VESA timing SXGA 204 WXGA 2 205 UXGA 206 WXGA 3 207 WUXGA 208 U6 707 pvsp dp hfrontporch pvsp dp hsynctime dp hbackporch pvsp dp activeline dp vfrontporch dp vsynctime dp vbackporch pvsp dp hpolarity pvsp dp vpolarity vout fr and dp 4kx2k mode to set output video Function pvsp autocfg output vid 7 0 Description 0x10 default OxXX Default 1080p 60 Output timing VID Rev 0 Page 107 of 326 06 707 Table 20 lists the supported output video timings and the corresponding VID 59 94 23 97 Hz timings have the same VID as the corresponding 60 24 Hz timing in the table Table 20 PVSP Supported Output Video Timing and VID Video Timing VID 640x480p60 1 720x480p60 20r3or 140r 15 35 or 36 720 1440 x240p60 8 9 720 2880 x240p60 120r 13 1280x720p60 4 1920x1080p 16 720x576p50 17 or 18 or 29 or 30 or 37 or 38 1280x720p50 19 720x288p50 23 or 24 or 27 or 28 1920x1080p50 31 1920x1080p24 32 1920 1080 25 33 1920 1080 34 720 100 41 576p100 42 or 43 720p120 47 480p120 48 or 49 576p200 52 or 53 480p240 56 or 57 4kx2k 30 Hz 112 4kx2k 25 Hz 113 Akx2k 24 Hz 114 Akx2k 24 Hz SMPTE 115 VGA 200 SVGA 201 XGA 202 WXGA 2
68. 7 0 0b00000000 Data Byte 25 OxF3DD R W spare3 byte26 7 0 0600000000 Data Byte 26 Rev 0 Page 209 of 326 U6 707 06 707 Test Map Address Access Type Register Name Default Value Byte Name OxF3DE R W spare3_byte27 7 0 0b00000000 Data Byte 27 Table 49 Spare Packet 4 Configuration Register Packet Map Address Access Type Register Name Default Value Byte Name OxF3E0 R W spare4_header0 7 0 0600000000 Header Byte 0 OxF3E1 R W spare4_header1 7 0 0b00000000 Header Byte 1 OxF3E2 R W spare4_header2 7 0 0b00000000 Header Byte 2 OxF3E3 R W spare4_pb0 7 0 0b00000000 Data Byte 0 OxF3E4 R W spare4_pb1 7 0 0b00000000 Data Byte 1 OxF3E5 R W spare4_pb2 7 0 0b00000000 Data Byte 2 OxF3E6 R W spare4 pb3 7 0 0600000000 Data Byte 3 OxF3E7 R W spare4 pb4 7 0 0600000000 Data Byte 4 OxF3E8 R W spare4 pb5 7 0 0600000000 Data Byte 5 OxF3E9 R W spare4 pb6 7 0 0600000000 Data Byte 6 OxF3EA R W spare4 pb7 7 0 0600000000 Data Byte 7 OxF3EB R W spare4 pb8 7 0 0600000000 Data Byte 8 OxF3EC R W spare4_pb9 7 0 0b00000000 Data Byte 9 OxF3ED R W spare4_pb10 7 0 0b00000000 Data Byte 10 OxF3EE R W spare4_pb11 7 0 0b00000000 Data Byte 11 OxF3EF R W spare4_pb12 7 0 0b00000000 Data Byte 12 R W spare4 pb13 7 0 0600000000 Data Byte 13 OxF3F1 R W spare4 pb14 7 0 0600000000 Data Byte 14 OxF3F2 R W spare4 pb15 7 0
69. 7 3640 0000 0010 0x02 0 036096 0000 0001 0x01 0 018096 0000 0000 0x00 0 000096 Reset value nominal 11111111 OxFF 0 018096 1111 1110 OxFE 0 036096 1100 0010 0xC2 7 364096 1100 0001 0 1 7 382096 1100 0000 0xCO 4 008 7 5000 7 4 17 Gamma Correction Generally gamma correction is applied to compensate for the nonlinear relationship between the signal input and the output brightness level as perceived on a CRT It can also be applied wherever nonlinear processing is used Gamma correction uses the function Signalovr Signalm where y is the gamma correction factor Gamma correction is available for SD and ED HD video For both variations there are twenty 8 bit registers used to program the Gamma Correction Curve A and Gamma Correction Curve B Gamma correction is performed on the luma data only The user can choose one of two correction curves Curve A or Curve B Only one of these curves can be used at a time The shape of the gamma correction curve is controlled by defining the curve response at 10 different locations along the curve By altering the response at these locations the shape of the gamma correction curve can be modified Between these points linear interpolation is used to generate intermediate values Considering that the curve has a total length of 256 points the 10 programmable locations are at the following points 24 32 48 64 80 96 128 160 192 and 224 The following
70. 7 4 R W 0b0000 Bits 7 4 of Data Byte 5 OxEC5A 7 0 R W 0600000000 Data Byte 6 OxEC5B 7 0 R W 0600000000 Data Byte 7 OxEC5C 7 0 R W 00000000 Data Byte 8 OxEC5D 7 0 R W 00000000 Data Byte 9 7 0 R W 00000000 Data Byte 10 OxEC5F 7 0 R W 00000000 Data Byte 11 OxEC60 7 0 R W 00000000 Data Byte 12 OxEC61 7 0 R W 00000000 Data Byte 13 OxEC62 7 0 R W 00000000 Data Byte 14 OxEC63 7 0 R W 00000000 Data Byte 15 0 64 17 0 R W 00000000 Data Byte 16 OxEC65 7 0 R W 00000000 Data Byte 17 OxEC66 7 0 R W 00000000 Data Byte 18 OxEC67 7 0 R W 00000000 Data Byte 19 OxEC68 7 0 R W 00000000 Data Byte 20 OxEC69 7 0 R W 00000000 Data Byte 21 OxEC6A 7 0 R W 00000000 Data Byte 22 OxEC6B 7 0 R W 00000000 Data Byte 23 OxEC6C 7 0 R W 00000000 Data Byte 24 OxEC6D 7 0 R W 00000000 Data Byte 25 OxEC6E 7 0 R W 00000000 Data Byte 26 OxEC6F 7 0 R W 00000000 Data Byte 27 The MPEG InfoFrame is defined in the latest CEA 861 specification Currently the specification does not recommend using this InfoFrame The transmission of MPEG InfoFrames can be enabled by setting the mpeg_pkt_en bit When the transmission of MPEG InfoFrames is enabled the ADV8005 transmits an MPEG InfoFrame once every two video fields Table 54 provides a list of registers that can be used to configure MPEG InfoFrames mpeg_pkt_en TX2 Main Map Address 0xF440 5 This bit is used to enable the MPEG Packet Rev 0 Page 215 of 326 0
71. Bus Y N Encoder Port ormatting 480p OSD r CSC amp y Y only 720p Video r 720 5 Serial 720p Encoder Transceiver Video Formatting amp 5 24 Figure 20 ADV8005 Mode 10 Configuration Mode 10 is used to support the external input of either part of or the complete OSD from another device for example an MCU With support for HS VS DE and CLK the external OSD input can also be used to input video data Using mode 10 the external OSD bus can be used to support picture in picture PiP with two video streams In this mode the input from the EXOSD TTL 24 bit input port is written into DDR2 memory and read back by the OSD core as a region of the OSD This region is then blended with input video Rev 0 Page 36 of 326 06 707 2 1 12 Mode 11 PIP External OSD Greater Than or Equal To 720p Mode 11 should be used if e OSD data is input via the EXOSD TTL 24 bit input port e OSD data input via the EXOSD TTL 24 bit input port is greater than or equal to 720p Mode 11 is used to support the external input of either part of or the complete OSD from another device for example an MCU With support for HS VS DE and CLK the external OSD input can also be used to input video data Using mode 10 the external OSD bus can be used to support picture in picture PiP with two video streams The difference between mode 10 and mode 11 is the resolution of the incoming video mo
72. Byte 13 0x51 R W acp pb14 7 0 0600000000 Data Byte 14 0x52 R W acp pb15 7 0 0600000000 Data Byte 15 0x53 R W acp_pb16 7 0 0b00000000 Data Byte 16 0x54 R W acp_pb17 7 0 0b00000000 Data Byte 17 0x55 R W acp pb18 7 0 0600000000 Data Byte 18 0x56 R W acp_pb19 7 0 0b00000000 Data Byte 19 0x57 R W acp pb20 7 0 0600000000 Data Byte 20 0x58 R W acp_pb21 7 0 0b00000000 Data Byte 21 0x59 R W pb22 7 0 0600000000 Data Byte 22 Ox5A R W acp pb23 7 0 0600000000 Data Byte 23 Ox5B R W acp pb24 7 0 0600000000 Data Byte 24 0 5 R W pb25 7 0 0600000000 Data Byte 25 0x5D R W acp_pb26 7 0 0b00000000 Data Byte 26 Ox5E R W acp_pb27 7 0 0b00000000 Data Byte 27 1 As defined in the latest CEA 861 specification 6 11 8 If the Supports AI bit in the Vendor Specific Data Block VSDB of the sink EDID is set at 1 the International Standard Recording Code ISRC Packet ISRC packets 1 and 2 can be transmitted The ADV8005 can be configured to transmit ISRC packet by setting isrc_pkt_en to 1 When the transmission of an ISRC packet is enabled the ADV8005 transmits an ISRC packet once every two video fields Table 66 and Table 67 provide the list of registers that can be used to configure ISRC packets isrc_pkt_en 2 Map Address OxF440 3 This bit is used to enable the ISRC Packet Function isrc_pkt_en Description 0 default Disabled 1 Enabled Table 66 ISRC1 Packet Configuration
73. Curve A A5 Point 96 OxE449 ED HD Gamma Curve A A6 Point 128 OxE44A ED HD Gamma Curve A A7 Point 160 OxE44B ED HD Gamma Curve A A8 Point 192 0 44 ED HD Gamma Curve A9 Point 224 OxE44D Table 78 ED HD Gamma Curve B Curve Type Point Register Address ED HD Gamma Curve B BO Point 24 OxE44E ED HD Gamma Curve B B1 Point 32 OxE44F ED HD Gamma Curve B B2 Point 48 OxE450 ED HD Gamma Curve B B3 Point 64 OxE451 ED HD Gamma Curve B B4 Point 80 OxE452 ED HD Gamma Curve B B5 Point 96 OxE453 ED HD Gamma Curve B B6 Point 128 OxE454 ED HD Gamma Curve B B7 Point 160 OxE455 ED HD Gamma Curve B B8 Point 192 OxE456 ED HD Gamma Curve B B9 Point 224 OxE457 Rev 0 Page 271 of 326 06 707 To select between both the A and B curves for the ED HD gamma correction the gamma curve b hdtv must be programmed gamma curve b hdtv Encoder Map Address OxE435 4 This bit is used to select the gamma correction curves for ED HD video data Function gamma curve b hdtv Description 0 default Gamma Correction Curve A 1 Gamma Correction Curve B 7 4 17 2 SD Gamma Correction To enable the gamma correction curves for SD standards gamma en must be programmed gamma en Encoder Map Address OxE488 6 This bit is used to enable the gamma correction curves for SD video data Function gamma en Description 1 Enabled 0 default Disabled The SD gamma correction curves a
74. D 35 24 Middle D 23 12 and Bottom D 11 0 This register allows the user to swap the order of these three data channels Rev 0 Page 51 of 326 06 707 Function vid swap bus ctrl 2 0 Description 000 default D 35 24 D 23 12 D 11 0 001 D 35 24 D 11 0 D 23 12 010 D 35 24 D 23 12 D 11 0 011 D 23 12 D 35 24 D 11 0 100 D 11 0 D 35 24 D 23 12 101 D 11 0 D 23 12 D 35 24 110 D 23 12 D 11 0 D 35 24 111 D 35 24 D 23 12 D 11 0 The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing Once a DDR mode is selected using vid format sel 4 0 the order of the luma and chroma data can be configured using vid ddr yc swap In DDR modes the luma is expected on the rising edge of the pixel clock Setting this bit to 1 swaps the luma and chroma samples and places the chroma sample C on the rising edge and the luma sample Y on the falling edge Refer to Figure 30 for more information The edge on which each sample of DDR data is latched into the part can be specified using vid ddr edge sel ddr yc swap 0 Xv Xe Xe d c yc swap 1 Figure 30 DDR Mode Luma and Chroma Swap vid ddr yc swap IO Map Address 0x1B4A 0 This bit is used to swap the Luma Y and Chroma C data in DDR modes By default Y is expected on the rising edge of the clock Function vid ddr yc swap Description 0 defaul
75. DNR sharpness mode Refer to Figure 127 Rev 0 Page 278 of 326 DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET CORING GAIN DATA CORING GAIN BORDER NOISE SIGNAL PATH SUBTRACT Y DATA SIGNAL IN INPUT THRESHOLD RANGE FROM ORIGINAL SIGNAL FILTER OUTPUT THRESHOLD MAIN SIGNAL PATH DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET DNR SHARPNESS MODE CORING GAIN DATA CORING GAIN BORDER NOISE SIGNAL PATH INPUT FILTER BLOCK FILTER ADD SIGNAL OUTPUT Y DATA THRESHOLD THRESHOLD INPUT RANGE FROM ORIGINAL SIGNAL 3 DNR oUT Figure 127 SD DNR Block Diagram FILTER OUTPUT THRESHOLD MAIN SIGNAL PATH 06398 078 U6 707 In DNR mode if the absolute value of the filter output is smaller than the threshold it is assumed to be noise A programmable amount coring gain border coring gain data of this noise signal is subtracted from the original signal In DNR sharpness mode if the absolute value of the filter output is less than the programmed threshold it is assumed to be noise Otherwise if the level exceeds the threshold now identified as a valid signal a fraction of the signal coring gain border coring gain data is added to the original signal to boost high frequency components and sharpen the video image In MPEG systems it is common to process the video information in blocks of 8 pixels x 8 pixels for MPEG2 systems or 16 pixels x 16 pixels for MP
76. DVDD_DDR gt Filter PVDDI p Filter gt PVDD2 gt Filter PVDD3 gt Filter PVDD5 Fiter PVDD DDR Figure 145 Power Supply Design Rev 0 Page 299 of 326 TPSS gt 20msee 1 Figure 146 Power Supply Sequence Rev 0 Page 300 of 326 APPENDIX B U6 707 UNUSED PIN LIST Location Mnemonic Type Description if Unused Pin Type 1 OSD 2 DINI7 OSD video Float this pin as it is disabled by default Bi directional digital IO input A2 OSD DE OSD video Float this pin as it is disabled by default sync A3 OSD CLK EXT CLK OSD video Float this pin as it is disabled by default sync Float this pin as it is disabled by default A5 AUD IN 2 Float this pin as it is disabled by default Float this pin as it is disabled by default A7 ARC2 OUT Audio output Connectthis pin to ground through a 4 7 resistor A8 MOSI1 Serial port Float this pin as it is disabled by default control A9 SCK2 Serial port Float this pin as it is disabled by default control Serial port Float this pin as it is disabled by default control A11 RESET Miscellaneous This pin must be connected digital A12 XTALN This pin must be connected digital A4 AUD IN 1 A6 AUD 51 A10 52 miscellaneous digital A13 PVDD2 PLL Digital Supply Voltage 1 8 V A16 CVDD1 Comparator Supply Voltage 1 8 V Bi directional digital IO Bi directi
77. Data Byte 12 OxF2DO R W spare1 pb13 7 0 0600000000 Data Byte 13 OxF2D1 R W spare1 pb14 7 0 0600000000 Data Byte 14 OxF2D2 R W spare1 pb15 7 0 0600000000 Data Byte 15 OxF2D3 R W spare1 pb16 7 0 0600000000 Data Byte 16 0 204 R W spare1 pb17 7 0 0600000000 Data Byte 17 OxF2D5 R W spare1 pb18 7 0 0600000000 Data Byte 18 OxF2D6 R W spare1 pb19 7 0 0600000000 Data Byte 19 OxF2D7 R W spare1 pb20 7 0 0600000000 Data Byte 20 OxF2D8 R W spare1 pb21 7 0 0600000000 Data Byte 21 OxF2D9 R W spare1 pb22 7 0 0600000000 Data Byte 22 OxF2DA R W spare1 pb23 7 0 0600000000 Data Byte 23 OxF2DB R W spare1 pb24 7 0 0600000000 Data Byte 24 OxF2DC R W spare1 pb25 7 0 0600000000 Data Byte 25 OxF2DD R W spare1 pb26 7 0 0600000000 Data Byte 26 OxF2DE R W spare1_pb27 7 0 0b00000000 Data Byte 27 Table 47 Spare Packet 2 Configuration Register Packet Map Access Type Register Name Default Value Byte Name Address OxF2E0 R W spare2_hb0 7 0 0b00000000 Header Byte 0 OxF2E1 R W spare2_hb1 7 0 0b00000000 Header Byte 1 OxF2E2 R W spare2_hb2 7 0 0b00000000 Header Byte 2 OxF2E3 R W spare2 pb0 7 0 0600000000 Data Byte 0 OxF2E4 R W spare2_pb1 7 0 0b00000000 Data Byte 1 OxF2E5 R W spare2 pb2 7 0 0600000000 Data Byte 2 OxF2E6 R W spare2 pb3 7 0 0600000000 Data Byte 3 OxF2E7 R W spare2 pb4 7 0 0600000000 Data Byte 4 OxF2E8 R W spare2 pb5 7 0 0600000000 Data Byte 5 OxF2E9 R W spare2 pb6 7 0 0600000000 Data Byte 6 OxF2EA R W spare2 pb7 7 0 0600000000 Data Byte 7 O
78. Data Byte 19 0 237 R W mpeg pb20 7 0 0600000000 Data Byte 20 0 238 R W mpeg pb21 7 0 0600000000 Data Byte 21 OxF239 R W mpeg pb22 7 0 0600000000 Data Byte 22 OxF23A R W mpeg pb23 7 0 0b00000000 Data Byte 23 OxF23B R W mpeg pb24 7 0 0600000000 Data Byte 24 0 23 R W mpeg pb25 7 0 0600000000 Data Byte 25 OxF23D R W mpeg pb26 7 0 0b00000000 Data Byte 26 OxF23E R W mpeg pb27 7 0 0600000000 Data Byte 27 1 As defined in the latest CEA 861 specification 6 10 7 Gamut Metadata The Gamut metadata packet GMP contains the sources Gamut boundary description It is defined in the latest HDMI specification The contents of the GMP can be set via the Packet Map registers listed in Table 55 The user can enable the transmission of GMP to the downstream sink by setting the gm pkt en bit When the transmission of GMP is enabled the ADV8005 transmits a GMP once every two video fields The ADV8005 transmits the GMP data starting 400 pixel clock cycles after the leading edge of VSync In order to avoid corrupting the GMP data during transmission it is recommended that the user synchronizes all writes to the GMP registers so that the write begins 512 pixel clock cycles after the VSync leading edge The VSync interrupt of the ADV8005 should be used to synchronize this timing Figure 97 illustrates this timing requirement Rev 0 Page 216 of 326 06 707 gm pkt en TX2 Map Address OxF440 2 This bit is used to
79. Descriptor InfoFrame Function spd pkt en 0 default 1 Description Disabled Enabled Table 45 SPD InfoFrame Configuration Register Packet Map Access Type Register Name Default Value Byte Name Address OxF200 R W spd hb0 7 0 0600000000 Header Byte 0 OxF201 R W spd hb1 7 0 0500000000 Header Byte 1 OxF202 R W spd hb2 7 0 0600000000 Header Byte 2 OxF203 R W spd pb0 7 0 0600000000 Data Byte 0 OxF204 R W spd pb1 7 0 0600000000 Data Byte 1 OxF205 R W spd pb2 7 0 0600000000 Data Byte 2 OxF206 R W spd pb3 7 0 0600000000 Data Byte 3 0 207 R W spd pb4 7 0 0600000000 Data Byte 4 OxF208 R W spd pb5 7 0 0600000000 Data Byte 5 OxF209 R W spd pb6 7 0 0600000000 Data Byte 6 OxF20A R W spd pb7 7 0 0600000000 Data Byte 7 OxF20B R W spd pb8 7 0 0600000000 Data Byte 8 OxF20C R W spd pb9 7 0 0600000000 Data Byte 9 OxF20D R W spd pb10 7 0 0600000000 Data Byte 10 OxF20E R W spd pb11 7 0 0600000000 Data Byte 11 OxF20F R W spd pb12 7 0 0600000000 Data Byte 12 OxF210 R W spd pb13 7 0 0600000000 Data Byte 13 Rev 0 Page 206 of 326 Packet Map Access Type Register Name Default Value Byte Name Address OxF211 R W spd pb14 7 0 0600000000 Data Byte 14 OxF212 R W spd pb15 7 0 0600000000 Data Byte 15 OxF213 R W spd_pb16 7 0 0b00000000 Data Byte 16 OxF214 R W spd_pb17 7 0 0b00000000 Data Byte 17 OxF215 R W spd pb18
80. Figure 105 Audio Clock Regeneration Figure 105 illustrates the overall system architecture model used by HDMI Rxs for audio clock regeneration The HDMI source determines the Rev 0 Page 229 of 326 06 707 fractional relationship between the video clock and an audio reference clock 128 fs and passes the numerator and denominator that fraction to the sink across the HDMI link The sink may then recreate the audio clock from the TMDS clock by using a clock divider and a clock multiplier The relationship between the two clocks is shown in Equation 23 N 128 f frups CTS Equation 23 Relationship Between Audio Reference and TMDS Clocks The source determines the value of the numerator N as specified in the HDMI specification Typically this value N is used in a clock divider to generate an intermediate clock that is slower than the 128 fs clock by the factor The source typically determines the value of the denominator Cycle Time Stamp CTS by counting the number of TMDS clocks in each of the 128 fs N clocks 6 11 4 1 N Parameter N is an integer number and is calculated using Equation 24 with the recommended optimal value shown in Equation 25 which approximately equals N for coherent audio and video clock sources Table 60 to Table 62 can be used to determine the value of N For non coherent sources or sources where coherency is not known Equation 24 Equation 25 and Equation 26 should be used 128 f5 1500Hz lt N
81. Figure 141 and Figure 142 provide a graphical example of what how edge and level sensitive interrupts operate INT Output xxx RAW xxx ST Interrupt path for level sensitive Interrupts CHANGE Internal DETECTION HOLD UNTIL APPLY E Status Flag SAMPEING Rising and CLEARED MASK Falling edge xxx CLR xxx MB1 i OR CLR 1 Interrupt path for edge CHANGE sensitive Interrupts Internal SAMPLING DETECTION HOLD UNTIL APPLY Pulse Flag ia CLEARED MASK Rising edge yyy RAW ST Figure 140 Level and Edge Sensitive Raw Status and Interrupt Generation AVI infoFrame Detection Internal Flag AVI INFO RAW AVI INFO ST No AVI Said InfoFrame el Detected AVI INFO CLR AVI INFO CLR set to 1 set to 1 lt lt lt Time taken by the CPU to clear AVI INFO ST Time taken by the CPU to clear AVI INFO ST Figure 141 AVI INFO RAW and AVI INFO ST Timing Rev 0 Page 290 of 326 06 707 New AVI InfoFrame Detection Internal Pulse Flag AVI InfoFrame with new content detected 8 amp M Time 2 xtal periods NEW AVI INFO RAW NEW AVI INFO ST NEW AVI INFO CLR setto 1 Time taken by the CPU to clear NEW AVI INFO ST Figure 142 AVI INFO RAW and NEW AVI IN
82. H START SVSP VOM CROP HEIGHT lt gt SVSP VOM CROP WIDTH Figure 67 VOM Crop Dimensions svsp vom crop h start 10 0 Secondary VSP Map Address 0xE626 7 0 Address 0 627 7 5 This signal is used to set the horizontal start position of the VOM cropper Function svsp vom crop h start 10 0 Description 0x000 default Default OxXXX Horizontal start position of VOM cropper svsp vom crop v start 10 0 Secondary VSP Map Address 0xE628 7 0 Address 0 629 7 5 This signal is used to set the vertical start position of the VOM cropper Function svsp vom crop v start 10 0 Description 0x000 default Default OxXXX Vertical start position of VOM cropper svsp vom crop width 10 0 Secondary VSP Map Address 0xE62A 7 0 Address 0xE62B 7 5 This signal is used to set the width of the VOM cropper Rev 0 Page 150 of 326 06 707 Function svsp vom crop width 10 0 Description 0x000 default Default OxXXX Width of VOM cropper input svsp vom crop height 10 0 Secondary VSP Map Address 0xE62C 7 0 Address OxE62D 7 5 This signal is used to set the height of the VOM cropper Function svsp vom crop height 10 0 Description 0x000 default Default OxXXX Height of VOM cropper input Note The following restrictions apply to the values at which these registers can be set e All registers should contain even values e 0 lt svsp_vom_crop_
83. HDMI Rx is connected to the HDMI transmitter vsync int vsync int en Used to flag the falling edge on a VSync signal Rev 0 Page 294 of 326 06 707 Interrupt Description edid ready int edid ready int en Used to indicate if the HDMI Rx EDID is ready for reading hdcp authenticated int hdcp authenticated int en Used to indicate if the HDCP protocol has been authenticated ri ready int ri ready int en Used to indicate if the HDCP Ri is ready hdcp error int hdcp error int en Used to indicate if a HDCP error has occurred bksv flag int bksv flag int en Used to indicate if the BKSV flag is set 8 4 3 HDMI Tx Interrupt Polarity This register is used to configure various logical operations which are available to the user when using the HDMI Tx interrupts tx int pol 1 0 IO Map Address 0x1A76 1 0 This signal is used to control the TX interrupt polarity Function tx int pol 1 0 Description 00 default Tx interrupt is logical AND of Tx1 Tx2 interrupts 01 Tx interrupt is inverted logical AND of Tx1 Tx2 interrupts 10 Tx interrupt is logical OR of Tx1 Tx2 interrupts 11 Tx interrupt is inverted logical OR of Tx1 Tx2 interrupts Rev 0 Page 295 of 326 06 707 APPENDIX A PCB LAYOUT RECOMMENDATIONS The ADV8005 is a high precision high speed mixed signal device It is important to have a well laid out PCB board in order to achieve the maximum performance from the part The fo
84. IO Map Address 0x1B96 7 0 This register is used to specify the VIC relative to CEA 861 Function rx in id 7 0 Description 0x06 861 VIC 6 480160 2x 0x07 861 VIC 7 480160 2x 0x08 861 VIC 8 240p60 2x 0x09 861 VIC 9 240p60 2x 0x15 861 VIC 21 576150 2x 0x16 861 VIC 22 576150 2x 0x17 861 VIC 23 288p50 2x 0x18 861 VIC 24 288p50 2x The ADV8005 can output a large number of video formats including many common graphics resolutions To enable the PVSP and SVSP cores to output these frequencies the output timing clocks must first be programmed The output clocks for both the PVSP and SVSP are shown in Figure 37 Primary VSP Primary 5 clock Secondary VSP Secondary VSP clock Rev 0 Page 64 of 326 06 707 Figure 37 PVSP SVSP Output Clock Configure For the PVSP and SVSP the correct clocks must be configured manually This can be done using the DPLL period registers which allows the user to program the sampling rate for the appropriate output format by The equation for calculating this value is provided in Equation 1 1 64 x12 x 27MHz Equation 1 Calculating DPLL Phase Period dpll phase _ period Once the dpll_phase_period is calculated Equation 2 is used to calculate the dpll_clock_period t lock 222 clock period dpll phase period Equation 2 Calculating DPLL Clock Period whe
85. Interrupts store unmasked irqs IO Map Address 0x1A69 7 This bit is used to specify whether the HDMI status flags for any HDMI interrupt should be triggered regardless of whether the mask bits are set This bit allows an HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without triggering an interrupt on the interrupt pin The status is stored until the clear bit is used to clear the status register and allows another interrupt to occur Function store unmasked irqs Description 0 default Do not store triggered interrupts 1 Store triggered interrupts 8 2 SERIAL VIDEO RX INTERRUPTS 8 2 1 Introduction This section describes the interrupt support provided for the Serial Video Rx on the ADV8005 The Serial Video Rx interrupts are ORd together and connected to the ADV8005 INT2 pin The ADV8005 Serial Video Rx interrupt architecture provides the following types of bits e Raw bits e Status bits e Interrupt mask bits e Clear bits Raw bits are defined as being either edge sensitive or level sensitive The following compares an edge sensitive interrupt and a level sensitive interrupt to demonstrate the difference level_sensitive_int_raw IO Address Read Only This readback indicates the raw status of the level sensitive interrupt This bit is set to one when a condition occurs and is reset to 0 when the condition is no longer apparent Function level s
86. Manual override To increase the noise immunity of the ADV8005 ARC Rxs it is recommended to enable the input hysteresis block on both blocks via Rev 0 Page 246 of 326 06 707 txl arc bias hyst adj andtx2 arc bias hyst adj txl arc bias hyst adj IO Map Address 0x1A88 1 This bit is used to control the addition of hysteresis to the TX1 ARC Function tx1 arc bias hyst adj Description 0 default Normal 1 ADD hysteresis tx2 arc bias hyst adj IO Map Address Ox1A8A 1 This bit is used to control the addition of hysteresis to the TX2 ARC Function tx2 arc bias hyst adj Description 0 default Normal 1 ADD hysteresis 6 15 CHARGE INJECTION SETTINGS The clock and data charge injection controls are used to tune the strength of an AC coupled driver on the outputs from the ADV8005 Tx This driver is used to boost the ramp rate on the output waveform helping to open the eye particularly at higher transmission speeds The charge injection settings used in the ADV8005 software driver are optimized for the evaluation board and may require adjustment for end user systems The three data channels should be configured to the same value charge injection setting The clock charge injection value may require adjustment to a separate value to meet rise fall time requirements chg inj ch0 3 0 2 Main Map Address 0xF481 7 4 Binary control of charge injection for data channel 0 with LSB cap value of 77fF
87. Map OxF400 OxFAFF HDMI Tx2 EDID Map OxF600 OxF6FF HDMI Tx2 UDP Map 0 00 OxFAFF HDMI Tx2 Test Map OxFBOO OxFBFF While this chapter only references one instance of each HDMI Tx Map the controls referenced are valid for both HDMI Tx1 and HDMI Tx2 register maps The same register bits and controls as per Table 42 apply for both transmitters 6 1 GENERAL CONTROLS To operate the HDMI Tx core it is necessary to monitor the Hot Plug Detect HPD signal from the downstream sink and power up the Tx Rev 0 Page 203 of 326 06 707 core after the appropriate HPD becomes high To power up the Tx core system pd must be programmed to 0 when the _ 1 pin is high The status of the pin is provided via hpd state Some registers cannot be written to when the signal on the TXx input pin is low When the level on the TXI pin goes from high to low some registers will be reset to their default value The best method to determine when the level of the signal on the TXx pin is high is to use the interrupt system An interrupt can be enabled to notify level change on the _ pin refer to section 8 for more details regarding the ADV8005 interrupts The ADV8005 also features a rx sense state status bit which can be used to detect the presence of TMDS clock terminations from the sink If the ADV8005 detects a voltage level higher than 1 8 V on the clock lines of its TMDS output port rx
88. Output Module If this bit is set to 1 the VOM is enabled to read video data from external memory process it and then output it Function pvsp enable vom Description 0 default Disable VOM 1 Enable VOM Also if using the PVSP the FFS must be enabled using enable ffs This informs the hardware of the various conversions that must be performed Field frame buffers in external memory are managed by the FFS which decides which field frame buffer should be used by the VIM to store input video data The FFS also decides which field frame buffer should be read back by VOM to process In the case of interlaced video the FFS informs the VOM if the input video is the even field or the odd field The PVSP utilizes a frame repeat drop mechanism to implement FRC which is also managed by the FFS pvsp enable ffs Primary VSP Address 0 828 0 This bit is used to control the Field Frame Scheduler FFS If this bit is set to 1 the FFS is enabled and the VIM and VOM are scheduled by the FFS which means the Primary VSP is in operating mode If this bit is set to 0 the Primary VSP is in idle mode Function pvsp enable ffs Description 0 default Disable FFS FRC 1 Enable FFS FRC 3 2 1 1 Autoconfiguration Each block inside VIM and VOM be automatically configured to reduce the configuration complexity Two registers pvsp autocfg input vid 7 0 and autocfg output vid 7 0 should be set
89. R W isrc1_pb20 7 0 0b00000000 Data Byte 20 OxF278 R W isrc1_pb21 7 0 0b00000000 Data Byte 21 OxF279 R W isrc1_pb22 7 0 0b00000000 Data Byte 22 OxF27A R W isrc1_pb23 7 0 0b00000000 Data Byte 23 OxF27B R W isrc1_pb24 7 0 0b00000000 Data Byte 24 OxF27C R W isrc1_pb25 7 0 0b00000000 Data Byte 25 OxF27D R W isrc1_pb26 7 0 0b00000000 Data Byte 26 OxF27E R W isrc1_pb27 7 0 0b00000000 Data Byte 27 As defined in the latest CEA 861 specification Table 67 ISRC2 Packet Configuration Registers Rev 0 Page 239 of 326 Packet Map Access Type Field Name Default Value Byte Name Address OxF280 R W isrc2 hbO 7 0 0600000000 Header Byte 0 OxF281 R W 2 hb1 7 0 0500000000 Header Byte 1 OxF282 R W isrc2 hb2 7 0 0600000000 Header Byte 2 OxF283 R W isrc2_pbO 7 0 0b00000000 Data Byte 0 OxF284 R W isrc2_pb1 7 0 0b00000000 Data Byte 1 OxF285 R W isrc2_pb2 7 0 0b00000000 Data Byte 2 OxF286 R W isrc2_pb3 7 0 0b00000000 Data Byte 3 OxF287 R W isrc2 pb4 7 0 0600000000 Data Byte 4 OxF288 R W isrc2 pb5 7 0 0600000000 Data Byte 5 OxF289 R W isrc2 pb6 7 0 0600000000 Data Byte 6 OxF28A R W isrc2 pb7 7 0 0600000000 Data Byte 7 OxF28B R W isrc2 pb8 7 0 0600000000 Data Byte 8 OxF28C R W isrc2 pb9 7 0 0600000000 Data Byte 9 OxF28D R W isrc2 pb10 7 0 0600000000 Data Byte 10 OxF28E R W isrc2 pb11 7 0 0600000000 Data Byte 11 OxF28F R W isrc2 pb12 7 0 0600000000 Dat
90. Registers Rev 0 Page 238 of 326 Packet Map Access Type Field Name Default Value Byte Name Address OxF260 R W isrc1_hbO 7 0 0b00000000 Header Byte 0 OxF261 R W isrc1_hb1 7 0 0b00000000 Header Byte 1 OxF262 R W isrc1_hb2 7 0 0b00000000 Header Byte 2 OxF263 R W isrc1_pbO 7 0 0b00000000 Data Byte 0 OxF264 R W isrc1_pb1 7 0 0b00000000 Data Byte 1 06 707 Packet Map Access Type Field Name Default Value Byte Address OxF265 R W isrc1_pb2 7 0 0b00000000 Data Byte 2 OxF266 R W isrc1_pb3 7 0 0b00000000 Data Byte 3 OxF267 R W isrc1_pb4 7 0 0b00000000 Data Byte 4 OxF268 R W isrc1_pb5 7 0 0b00000000 Data Byte 5 OxF269 R W isrc1_pb6 7 0 0b00000000 Data Byte 6 OxF26A R W isrc1_pb7 7 0 0b00000000 Data Byte 7 OxF26B R W isrc1_pb8 7 0 0b00000000 Data Byte 8 OxF26C R W isrc1_pb9 7 0 0b00000000 Data Byte 9 OxF26D R W isrc1_pb10 7 0 0b00000000 Data Byte 10 OxF26E R W isrc1_pb11 7 0 0b00000000 Data Byte 11 OxF26F R W isrc1_pb12 7 0 0b00000000 Data Byte 12 OxF270 R W isrc1_pb13 7 0 0b00000000 Data Byte 13 OxF271 R W isrc1_pb14 7 0 0b00000000 Data Byte 14 OxF272 R W isrc1_pb15 7 0 0b00000000 Data Byte 15 OxF273 R W isrc1_pb16 7 0 0b00000000 Data Byte 16 OxF274 R W isrc1_pb17 7 0 0b00000000 Data Byte 17 OxF275 R W isrc1_pb18 7 0 0b00000000 Data Byte 18 OxF276 R W isrc1_pb19 7 0 0b00000000 Data Byte 19 OxF277
91. Reset Strategy 10 Map IO Map IO Map Tx Main Map Tx Main Map Event Event txl reset 0x1AFC 7 main_reset system_pd OxEC98 4 Tx Hot Plug Reset Pin OxF498 4 0x00 OxFF Reset Reset Reset Reset Reset 6 3 HDMI DVI SELECTION The HDMI Tx core supports the transmission of both HDMI and DVI streams The type of stream the ADV8005 transmits is set via hdmi dvi sel en In DVI transmission mode no packets will be sent and all registers relating to packets and InfoFrames will be disregarded The current transmission mode can be confirmed by reading hdmi dvi sel hdmi dvi sel en TX2 Main Map Address OxFA4AF 2 This bit is used to enable the output mode control Function hdmi dvi sel en Description 0 Automatic 1 default Output mode set by hdmi dvi sel hdmi dvi sel TX2 Main Map Address 0xF4AF 1 This bit is used to control the output mode DVI or HDMI Function hdmi dvi sel Description 0 default DVI 1 HDMI 6 4 AVMUTE The AV mute status is sent to the downstream sink through the general control packet One purpose of the AV mute is to alert the sink of a change in the TMDS clock so the sink can mute audio and video while the TMDS clock it receives is unstable Setting AV mute also pauses HDCP encryption so the HDCP link between the HDMI Tx and the sink is maintained while the TMDS clock is not stable Note that AV mute is not sufficient as a means to hide protected content
92. SPI Data Extraction occae e n reset LEGE EH EHE EUH 75 pM WEE QIEPLCUPIr de 75 229 RESOUS E 76 2 2 10 Image Processing Colorimetry Breakdown sese eene tententtetenttentententententententensenttente 78 2 21 0468 ERN 79 29212 ColorSpace wera E A act aie cel ee ee OE 83 2 2 12 1 Primary Input Channel 83 2 2 12 2 Secondary 86 2 2 12 3 Input Channel CSC 2 2 12 4 TET Ee QUtput led 2 2 12 5 HDMI Transmitter M H 95 2 2 13 Position and Phase Information eese entente ntes tenente entente tentent tenente nte n senten ten 98 2 2 14 ADV8005 Silicon 103 2 2 15 System Configuratio 103 Vide Signal Proc ssiNhi A 105 3 1 fenore 105 3 2 Primary VSP 105 ntrod ctionto PVSP AEAEE O ORE 105 OOO 106 3 2 1 2 Customized Input Output Video Format Configuration cccccesssesseesssesssessseesssesseesseesseessseessessesssssesseessssesseesssessesesseessseessees 108 32 13 Bield Pramie Butfer Numbers E 109 Rev 0 Page 3 of 326 06 707 5247
93. Section 6 8 indicates that a 256 byte EDID read has been completed and the EDID content can be read from the EDID Map edid segment 7 0 2 Main Map Address OxF4C4 7 0 This register is used to set the segment of the EDID read from the downstream receiver Function edid segment 7 0 Description XXXXXXXX User programmed EDID segment value 6 12 2 EDID Definitions Extended EDID E EDID supports up to 256 segments A segment is a 256 byte segment of EDID data containing one or two 128 byte EDID blocks A typical HDMI sink will have only two EDID blocks and so will only use segment 0 The first EDID block is always a base EDID structure defined in the VESA EDID specifications the second EDID block is usually the CEA extension defined in the CEA 861 specification The ADV8005 has a single memory location used to store EDID and HDCP information read from the downstream sink During HDCP repeater initialization the EDID data read from the sink is overwritten with HDCP information which is also read from the sink The sink EDID is not reread after HDCP initialization The user can request the ADV8005 to rebuffer an EDID segment by using the edid_reread control 6 12 3 Additional Segments The EDID block 0 byte number 0x7E tells how many additional EDID blocks are available If byte 0x7E is greater than 1 additional EDID segments will need to be read If there is more than one segment the second block that is block 1 is requi
94. These registers should be set to the resolution of the output video Refer to Figure 59 for more details pvsp man scal out enable Primary VSP Map Address OxE883 3 This bit is used to enable the manual setting of pvsp scal out width and pvsp scal out height Function pvsp man scal out enable Description 0 default Disable manually setting Scaler output resolution 1 Enable manually setting M Scaler output resolution pvsp scal out height 12 0 Primary VSP Map Address OxE846 4 0 Address OxE847 7 0 This signal is used to set the output vertical resolution of scaler in the VOM Function 5 scal out height 12 0 Description 0x000 default Default 0 Output height of VOM scaler pvsp scal out width 12 0 Primary VSP Map Address 0 844 4 0 Address 0xE845 7 0 This signal is used to set the output horizontal resolution of scaler in the VOM Function 5 out width 12 0 Description 0x000 default Default 0 Output width of VOM scaler Rev 0 Page 129 of 326 06 707 Image before Scaler in Scaled Image Scaler gt VOM PVSP DI CROP HEIGHT PVSP SCAL OUT HEIGHT PVSP DI CROP WIDTH 22 2 gt PVSP SCAL OUT WIDTH Figure 59 VOM Scaler Dimensions 3 2 3 12 Panorama Mode If the scaled video has a different aspect ratio to the original and the horizontal scaling factor is larger than the vertical
95. This signal is used to set the horizontal start position of the VOM cropper Function pvsp_di_crop_h_start 10 0 Description 0x000 default Default OxXXX Horizontal start position of VOM cropper input pvsp di crop v start 10 0 Primary VSP Map Address OxE83E 2 0 Address 0 83 7 0 This signal is used to set the vertical start position of the VOM cropper Function pvsp di crop v start 10 0 Description 0x000 default Default OxXXX Vertical start position of VOM cropper input pvsp di crop width 10 0 Primary VSP Map Address OxE840 2 0 Address 0xE841 7 0 This signal is used to set the width of the VOM cropper Function pvsp di crop width 10 0 Description 0x000 default Default OxXXX Width of VOM cropper input pvsp di crop height 10 0 Primary VSP Map Address 0xE842 2 0 Address 0xE843 7 0 This signal is used to set the height of the VOM cropper Function pvsp di crop height 10 0 Description 0x000 default Default 0 Height of VOM cropper input Note The following restrictions apply to the values to which these registers can be set 0 lt pvsp di crop h start 10 0 lt HORIZONTAL RESOLUTION OUTPUT BY VIM 1 0 lt pvsp di crop v start 10 0 lt VERTICAL RESOLUTION OUTPUT BY VIM 1 pvsp di crop h start 10 0 pvsp di crop width 10 0 lt HORIZONTAL RESOLUTION OUTPUT BY VIM pvsp di crop v start 10 0 pvsp di crop height 10 0
96. XC MSB xX MSB X MSB X MSB 1 LSB lt MSB extended MSB extended 32 Clock Slots 32 Clock Slots 4 gt gt Figure 101 Timing for Right Justified I2S Stream Input to ADV8005 LEFT RIGHT MSB LSB MSB LSB 32 Clock Slots 32 Clock Slots gt lt gt LRCLK SCLK DATA LRCLK SCLK DATA 6 11 3 2 SPDIF Audio Figure 102 Timing for Left Justified 125 Stream Input to 8005 U6 707 Figure 104 Timing for I2S Stream in Left or Right Justified and 32 bit Modes LEFT RIGHT LSBig lt MSBien 15 MSByight 15 16 Clock Slots 16 Clock Slots lt gt Figure 103 Timing for 125 Stream in 32 bit Mode LEFT RIGHT P4 LSB LSB 16 Clock Slots 16 Clock Slots gt gt lt The ADV8005 can receive two channel LPCM or encoded multichannel audio up to a 192 kHz sampling rate via the SPDIF input interface The detected sampling frequency for the SPDIF input stream can be read via the sf 3 0 field It is possible to set the sampling audio sampling frequency of the input SPDIF stream This is done by setting audio sampling freq sel to 1 When audio sampling freq seli
97. and vs for frame tracking Function pvsp frtrk mas mode en Description 0 default Frame track input 1 Frame track external master hs vs External Sync Mode Summary External sync locking mode is only needed for applications where the ADV8005 is required to lock its output timing to an externally provided source Applications where the ADV8005 ADV8003 output is required to be locked to the input timing do not require this functionality These applications e g video wall can use phase locked frame track mode to achieve this functionality The output will be locked within 2xtal clocks after an initial lock time of 5 seconds svsp frtrk mas mode en IO Map Address 0x1B99 0 This bit enables the use of external master hs and vs for frame tracking Function svsp frtrk mas mode en Description 0 default Frame track input 1 Frame track external master hs vs mp2i frtrk mas fld IO Map Address 0x1B97 1 This bit select whether the input field information from the mas vs and mas hs is tracked by the mp2i block or not The control signal pvsp frtrk mas mode en must also be enabled for this bit to take effect Function mp2i frtrk mas fld Description 0 default Disable tracking of input master field 1 Enable tracking of input master field sp2i frtrk mas fld IO Map Address 0x1B99 1 This bit selects whether the input field information from the mas vs and mas hs is tracked b
98. appearing as a window within another or two inputs routed to two outputs Several common modes of operation are defined to assist the user to quickly integrate the ADV8005 into a system Refer to Section 2 for more details 1 1 3 Video Signal Processor The motion adaptive de interlacer in the ADV8005 offers excellent edge detection and ultra low angle performance The per pixel de interlacing algorithm used delivers excellent performance which can be seen with specialist test patterns on facial features like eyebrows or on shirt collars This algorithm decides on whether an area of an image is moving or not and then applies the appropriate de interlacing approach accordingly The de interlacer can also determine when interlaced video originated as progressive and can reconstruct the original frames Low Angle 4 Detail Processing Enhance Cadence i Detection Ji Colour Enhance pa Detection Ji Noise Correction De interlacer j Enhance ae ee ee ee eee ee ee ce mm mm Figure 3 8005 Video Processing The ADV80038005 features dual scalers referred to as Primary Video Signal Processor PVSP and the Secondary Video Signal Processor SVSP The PVSP uses a contour based interpolation scaler which can upscale from 480i to 4k x 2k The PVSP can ar
99. be used in the end system application The Blimp OSD software tool covers the full design flow involved in delivering a complex bitmap based OSD from initial graphics design through to outputting the files required for integration into the system application Blimp OSD abstracts the user from the OSD hardware so a detailed description of the OSD hardware is not provided For more information on the OSD design flow and Blimp OSD software refer to the Blimp OSD software tool user manual 4 1 1 Features e Fulldesign flow covered by Blimp OSD software user does not need to worry about the OSD hardware e OSD maximum resolution of 4096 3840 e Pixel by pixel alpha blending e Dual video paths through the OSD blend block to support dual zone OSD display e Eight hardware timers which provide added functionality for OSD or system tasks e Programmable blending effect of OSD and background video e Programmable priority of regions e Uniform programmable transparent color in the OSD e OSD video input and output format 36 bit RGB e Support for main 3D video format timings e High performance scaling quality with 8 bit horizontal and vertical video scaler e Arbitrary resolution conversion e Support vertical horizontal scaling order change e Support progressive to interlaced conversion e Anti alias mode for downscaling e OSD data range control 4 1 2 OSD System Application Diagram Figure 81 provides a typical application diagram for usin
100. because the content is still sent even when AV mute is enabled use AV mute e Enable the GCP by setting gc pkt en to 1 Rev 0 Page 205 of 326 06 707 e Toset AV mute clear clear avmute that is clear avmute 0 and set set avmute that is set avmute 1 e Toclear AV mute clear set avmute that is set avmute 0 and set clear avmute clear avmute 1 Note that setting both set avmute and clear avmute is not a valid configuration set avmute TX2 Main Map Address 0xF44B 6 This bit is used to control the SET AVMUTE signal Function set avmute Description 0 default Set SET AVMUTE to 0 1 Set SET AVMUTE to 1 dear avmute TX2 Main Map Address 0xF44B 7 This bit is used to control the CLEAR AVMUTE signal Function clear avmute Description 0 default Set CLEAR AVMUTE to 0 1 Set CLEAR AVMUTE to 1 6 5 SOURCE PRODUCT DESCRIPTION INFOFRAME The Source Product Description SPD InfoFrame contains the vendor name and product description The transmission of SPD InfoFrames is enabled by setting en to 1 When this bit is set the HDMI Tx section transmits one SPD packet once every two video fields An application of this packet is to allow the sink to display the source information using an OSD This information is in a 7 bit ASCII format Refer to CEA 861 specification for more detail spd pkt en TX2 Main Map Address OxF440 6 This bit is used to enable the Source Product
101. can be determined using rb chip id 16 rb chip id 16 IO Map Address 0x1AD3 0 Read Only Readback of Macrovision enabled disabled Function rb chip id 16 Description 0 default Rovi Enabled 1 Rovi Disabled 2 2 15 System Configuration When configuring a system featuring an HDMI Rx and ADV8005 the following sequences for HDMI Tx and encoder are recommended For HDMI Tx 1 Configure the HDMI Rx ADV7850 2 Wait until the ADV8005 Serial Video Rx achieves lock 3 Wait 100 ms 4 Configure the VSP 5 Wait 1 field frame 6 Configure the HDMI Tx For the encoder 1 Configure the HDMI Rx ADV7850 2 Wait until the ADV8005 Serial Video Rx achieves lock 3 Wait 100 ms 4 Configure the VSP 5 Wait 250 ms 6 Configure the encoder Rev 0 Page 103 of 326 06 707 Rev 0 Page 104 of 326 06 707 3 VIDEO SIGNAL PROCESSING 3 1 INTRODUCTION The primary function of the ADV8005 is high performance video processing such as motion adaptive de interlacing flexible scaling and frame rate conversion as well as additional video processing such as noise reduction CUE correction and aspect ratio panorama scaling This section details the registers used to control the Video Signal Processing VSP hardware The three constituent sections of the ADV8005 video processor are the PVSP SVSP and the PtoI converter These hardware blocks are completely independent of each other and can be place
102. channel 2 Enable the required charge injection for the channel In summary the charge injection should only be enabled while the predriver is also enabled 6 17 HDMITX SOURCE TERMINATION When an ADV8005 HDMI Tx output is connected to a sink device the capabilities of the sink devices receiver must first be considered If the sink device is limited to receiving a maximum TMDS clock frequency less than or equal to 165 MHz the source termination must be disabled in the ADV8005 Tx connected to that sink device If the sink device can receive a TMDS clock frequency above 165 MHz then the TMDS clock frequency of the ADV8005 HDMI Tx connected to that sink will dictate what source termination settings are used In this case the Tx source termination settings must be configured as follows e ADV8005 Tx source termination disabled if the ADV8005 Tx TMDS clock frequency is less than or equal to 165 MHz e ADV8005 Tx source termination enabled if the ADV8005 Tx TMDS clock frequency is greater than 165 MHz Therefore for 4k x 2k Tx source termination should be enabled on the ADV8005 HDMI Tx output To disable the source termination a manual over ride must be enabled The manual over ride value is an open circuit if the control is set to 0 Figure 109 provides an overview of the ADV8005 HDMI Tx source termination requirements Rev 0 Page 248 of 326 TX OUTPUT PORT CONNECTED TO SINK DEVICE CAN SINK DEVICE RECEIVE TMDS CLK F
103. channel can be enabled using the ttl out csc enable control The CSC mode on the TTL output channel can be configured using ttl out mode 1 0 J The CSC mode is used to define the fixed point position of the CSC coefficients which are located after ttl out mode 1 0 in the IO Map for the TTL output channel 4096 ttl out csc mode ttl out a4 In A Out A Figure 46 TTL Output Channel CSC ttl out csc enable IO Map Address 0x1BBO 7 This bit is used to enable the ttl output channel CSC Function ttl out csc enable Description 0 default CSC disable 1 CSC enable ttl out csc mode 1 0 IO Map Address 0 1 0 6 5 This signal is used to specify the CSC mode for the ttl output channel CSC The CSC mode sets the fixed point position of the CSC coefficients including a4 b4 c4 and offsets Function ttl out csc mode 1 0 Description 00 default 1 0 4096 to 4095 01 2 0 8192 to 8190 10 4 0 16384 to 16380 11 4 0 16384 to 16380 ttl out a1 12 0 IO Map Address Ox1BB0 4 0 Address 0x1BB1 7 0 This signal is used to specify the ttl out channel CSC coefficient A1 ttl out a2 12 0 IO Map Address 0x1BB2 4 0 Address 0x1BB3 7 0 This signal is used to specify the ttl out channel CSC coefficient A2 Rev 0 Page 92 of 326 06 707 ttl 3 12 0 IO Map Address 0x1BB4 4 0 Address 0x1BB5 7 0 This signal is used to specify the ttl out channel CS
104. colour 7 0 and cb colour 7 0 are used to program the output color of the internal ED HD test pattern generator whether it is the lines of the crosshatch pattern or the uniform field test pattern They are not functional as color controls for external pixel data input hdtv tp en Encoder Map Address 0xE431 2 This bit is used to enable the ED HD test pattern generator Rev 0 Page 261 of 326 06 707 Function hdtv tp en Description 0 default ED HD test pattern off 1 ED HD test pattern on The values for the luma Y and the color difference Cr and Cb signals used to obtain white black and saturated primary and complementary colors conform to the ITU R BT 601 4 standard Table 73 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA 770 2 770 3 Reg 0x30 Bits 1 0 00 hdtv flat tp Encoder Map Address 0xE431 3 This bit is used to select the pattern used by the internal test pattern generator Function hdtv flat tp Description 0 default Hatch 1 Field frame y colour 7 0 Encoder Map Address 0xE436 7 0 This register is used to control the ED HD test pattern Y level cr colour 7 0 Encoder Map Address 0xE437 7 0 This register is used to control the ED HD test pattern Cr level cb colour 7 0 Encoder Map Address 0xE438 7 0 This register is used to control the ED HD test pattern Cb level Table 73 S
105. could be downloaded into the system SPI flash FLASH System MEM Controller C PU memory through for example the USB or RSR232 port of the MCU This mode can be enabled using the spi_loop_through mode which controls the mux shown in Figure 88 Rev 0 Page 180 of 326 06 707 Config Register OSD CORE SPI Master 4 FLASH System MEM Controller CPU DDR2 Memory Figure 88 SPI Loopback Enabled so MCU Can Program SPI Flash By default the SPI ports are set in manual mode for the SPI which means the SPI pins are tristated input To make the SPI ports operational the following register bits must be configured to automatic mode spil cs oe man en IO Map Address 0x1ACE 7 This bit is used to control the output enable manual override for spil cs Function Sspil cs oe man en Description 0 Auto 1 default manual override spil miso oe man en IO Map Address OX1ACE 6 This bit is used to control the output enable manual override for spil Function spil miso man en Description 0 Auto 1 default Manual override spil mosi oe man en IO Map Address 0x1ACE 5 This bit is used to control the output enable manual override for spil_mosi Function mosi man en Description 0 Auto 1 default Manual override spil sclk oe man en IO Map
106. data into the external memory to save memory bandwidth The down scaler in the VIM should only be enabled when horizontal downscaling is needed which means that the number of horizontal output active pixels should be less than the number of horizontal input active pixels When album mode is enabled the specified active output video width should be the album width If the horizontal resolution of the PVSP output timing is less than the input timing the horizontal down scaler can be enabled to reduce the load on the external DDR2 memory This horizontal down scaler input resolution is defined by the vim crop width 10 0 register and the output resolution is defined by the pvsp vim d out width 10 0 register To enable the horizontal down scaler pvsp vim d scal enable should be set to 1 pvsp vim d scal enable Primary VSP Map Address OxE883 5 This bit is used to enable the VIM down scaler Function pvsp vim d scal enable Description 0 default Disable VIM down scaler 1 Enable VIM down scaler pvsp vim d scal out width 10 0 Primary VSP Map Address 2 0 Address OxE83B 7 0 This signal is used to set the output video width of the down scaling scaler in the VIM The input video width is set by register pvsp vim crop width If VIM crop is not enabled pvsp vim crop width is auto configured by pvsp autocfg input vid which is the same with input video s horizontal resolution Funct
107. default Nothing done 1 Pseudo 444 to Real 444 conversion vid hs pol vid vs pol vid de pol and vid fld pol configure the polarity of the input video timing signals These must be set depending on the polarity of the upstream IC If active low these register can be left at their default If these signals from the upstream IC are active high their polarity can be inverted vid hs pol IO Map Address 0x1B49 3 This bit is used to set the polarity of the input HS timing signal Function vid hs pol Description 0 default Input HS polarity does not change 1 Input HS polarity gets inverted vid vs pol IO Map Address 0x1B49 2 This bit is used to set the polarity of the input VS timing signal Function vid vs pol Description 0 default Input VS polarity does not change 1 Input VS polarity gets inverted vid de pol IO Map Address 0x1B49 1 This bit is used to set the polarity of the input DE enable signal Function vid de pol Description 0 default Input DE polarity does not change 1 Input DE polarity gets inverted vid fld pol IO Map Address 0x1B49 0 This bit is used to set the polarity of the input Field FLD timing signal Function vid fld pol Description 0 default Input FLD polarity does not change 1 Input FLD polarity gets inverted vid hs vs mode is used to select the method by which the input video will be synchronized This may be required when the ADV8005 i
108. default Phase error 1 Frequency error 2 2 5 DDR2 Interface The ADV8005 uses DDR2 memory to enable the de interlacer scaler and OSD features The DDR2 interface on ADV8005 is designed to meet the JESD79 2F standard 2 2 5 1 DDR2 Configuration The controls described in this section are used to configure the ADV8005 DDR2 memory interface The first three bits configure the DDR2 memory interface for the external memory configuration The sdram_size 3 0 sets the memory size of the attached memory or memories For example if using 256 Mb memory sdram size 3 0 should be set to 0001 If using 2 Gb memory sdram size 3 0 should be set to 0100 The word size 3 0 and burst length 2 0 fields must also be configured depending on whether there are single or multiple memories connected to the ADV8005 If there is a single DDR2 memory word size 3 0 and burst length 2 0 should be set for a 32 bit word size and bursts of 8 If there are dual DDR2 memories word size 3 0 and burst length 2 0 should be set for a 64 bit word size and bursts of 4 ADV8005 is configured for dual 512 Mb memories with a 64 bit word size and bursts of 4 sdram size 3 0 IO Map Address 0x1A5B 7 4 This signal is used to specify the SDRAM size values other than those specified here are reserved Function sdram size 3 0 Description 0001 individual SDRAM is 256Mbit 0010 default individual SDRAM is 512Mbit 0011 individual SDRAM is 1Gbit 0100 individua
109. default Color 3 3 3 4 DDR Bypass Mode In the case where the SVSP is being used to upscale or downscale between 1080p and 720p external DDR2 memory is not required Internal line buffers allow the user to convert between these two resolutions while maintaining the full external memory bandwidth for both the PVSP and OSD The DDR bypass mode provided in the SVSP can be manually enabled disabled using svsp ddr bypass DDR2 bypass mode can be automatically configured using autocfg input vid 7 0 and svsp autocfg output vid 7 0 If the DDR bypass mode is to be set manually svsp man set ddr bypass must be set to 1 Note This option is only available to the user when scaling between two resolutions which have the same frame rate svsp man set ddr bypass Secondary VSP Address 0 662 0 This bit is used to enable manually setting DDR bypass If this bit is set to 1 SVSP will bypass DDR while ddr bypass is 1 or not bypass DDR while svsp ddr bypass is 0 Function svsp man set ddr bypass Description 0 default Disable 1 Enable svsp ddr bypass Secondary VSP Map Address OxE649 7 This bit is used to bypass external memory This register s value will be used while svsp set ddr bypass is 1 Function svsp ddr bypass Description 0 default Not bypass external memory 1 Bypass external memory 3 3 3 5 Progressive to Interlaced Converter in SVSP The Ptol converter block in the SVSP is used to con
110. digital IO Bi directional digital IO N A Digital input Digital input Digital input N A Digital input N A Digital output N A N A N A Digital output Digital output Digital output N A N A N A Rev 0 Page 302 of 326 06 707 Location C20 C21 C22 C23 D1 D2 D3 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 019 020 021 022 023 E1 E2 Mnemonic Type Description if Unused Serial Video Rx Inputs Analog Supply 3 3 V Serial Video Rx Inputs Analog Supply 3 3 V DAC5 Analog video Float this pin output DAC6 Analog video Float this pin output OSD video input miscellaneous digital OSD IN 16 EXT DIN O OSD IN 17 EXT DIN 1 OSD video input miscellaneous digital Float this pin as it is disabled by default Float this pin as it is disabled by default OSD IN 18 EXT DIN 2 OSD video input miscellaneous Float this pin as it is disabled by default GND digital GND DVDD IO Digital Interface Supply 3 3 V MCLK Float this pin as it is disabled by default This pin must be connected Serial port Float this pin as it is disabled by default control Miscellaneous Connectthis to ground through a digital 4 7 resistor INT2 Miscellaneous Connectthis pin to ground through a digital 4 7 resistor DVDD IO Digital Interface Supply 3 3 V digital RTERM Se
111. directional digital IO N A N A N A N A N A N A N A N A N A N A N A N A N A N A N A Bi directional digital IO Rev 0 Page 304 of 326 06 707 Location H2 H3 H4 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H2 H2 H22 H2 w J2 J3 J4 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J20 J21 J22 J23 K2 K3 Mnemonic Type Description if Unused NNNM 222111 OSD IN 2 OSD video Float this pin as it is disabled by default input OSD 1 31 OSD video Float this pin as it is disabled by default input OSD 41 OSD video Float this pin as it is disabled by default input qp ND ND ND GND G G G G G Go Go 0 0 TX1 24 HDMI Tx1 Float this pin TX1_2 HDMI Tx1 Float this pin D HS Digital video Float this pin as it is disabled by default sync Digital video Float this pin as it is disabled by default sync OSD_HS Digital video Float this pin as it is disabled by default sync OSD IN 0 OSD video Float this pin as it is disabled by default input wo cp 201111 cp amp Oooo i Gp amp Oooo i E ao amp cp amp wp amp cp feon qp Cd ND ND ND ND ND ND ND ND ND ND ND ND ND E GND GND ND ND 5 Digital video Float this pin as it is disabled by defaul
112. enable the Gamut Metadata Packet Function gm pkt en Description 0 default Disabled 1 Enabled Falling edge oflast DE of last field VSync Rising edge of first DE of next field t sending DES window 400 pixel f N clocks a E Initiate 12 change after 512 clocks Figure 97 PC Write Timing if GMP Data Table 55 Gamut Metadata Packet Configuration Registers Packet Map Access Field Name Default Value Byte Name1 Address OxF2A0 R W gmp_hb0 7 0 0b00000000 Header Byte 0 OxF2A1 R W gmp hb1 7 0 0600000000 Header Byte 1 OxF2A2 R W gmp hb2 7 0 0600000000 Header Byte 2 OxF2A3 R W gmp pbO 7 0 0600000000 Data Byte 0 OxF2A4 R W gmp_pb1 7 0 0b00000000 Data Byte 1 OxF2A5 R W gmp pb2 7 0 0600000000 Data Byte 2 OxF2A6 R W gmp pb3 7 0 0600000000 Data Byte 3 OxF2A7 R W pb4 7 0 0600000000 Data Byte 4 OxF2A8 R W gmp pb5 7 0 0600000000 Data Byte 5 OxF2A9 R W gmp pb6 7 0 0600000000 Data Byte 6 OxF2AA R W gmp pb7 7 0 0600000000 Data Byte 7 OxF2AB R W gmp pb8 7 0 0600000000 Data Byte 8 OxF2AC R W gmp pb9 7 0 0600000000 Data Byte 9 OxF2AD R W gmp pb10 7 0 0600000000 Data Byte 10 OxF2AE R W gmp pb11 7 0 0600000000 Data Byte 11 OxF2AF R W gmp pb12 7 0 0600000000 Data Byte 12 OxF2A0 R W gmp pb13 7 0 0600000000 Data Byte 13 OxF2A1 R W gmp pb14 7 0 0600000000 Data Byte 14 OxF2A2 R W gmp pb15 7 0 0600000000 Data
113. encoder Six high speed NSV 3 3 V 12 bit video DACs provide support for worldwide composite CVBS S Video Y C and component YPrPb RGB analog outputs in standard definition SD enhanced definition ED or high definition HD video formats It is also possible to enable the ADV8005 video encoder to work in simultaneous mode where both an SD and ED HD format are being output Note The video encoder variants of the ADV8005 are the ADV8005KBCZ 8A and the ADV8005KBCZ 8N The variants of ADV8005 with no encoder are the ADV8005KBCZ 8B and the ADV8005KBCZ 8B 1 1 8 Digital Video Output Video can be output from the ADV8005 via the flexible TTL port Reusing up to 36 of the flexible TTL port pins means that video can be routed in and out of the ADV8005 without using a useful cost reduction in systems which utilize FPGA interconnects e g 30 bit TTL input and 30 bit TTL output allowing 1080p 10 bit input and output The possible configurations of the TTL output port are captured in Table 90 and Table 91 The video TTL output port has a manually programmable CSC Rev 0 Page 18 of 326 06 707 1 2 MAIN FEATURES OF THE ADV8005 1 2 1 Video Signal Processor 1 2 1 1 Primary VSP e 12 bit internal processing e Fixed frame latency capability e Input timing up to 1080p e Output timing up to 4k x 2k e Input output format YCbCr at 4 4 4 e Motion adaptive de interlacing with motion detection e Ultra low angle interpolation o
114. explanation of the SPD InfoFrame fields Table 36 SPD InfoFrame Registers InfoFrame Access Register Name Byte Map Address Type R W Packet Type Value OxE3E7 spdifver InfoFrame version number OxE3E8 spd_inflen InfoFrame length OxE32A R spdinfpb 01 Checksum OxE32E R opan pb os DataByte4 055336 R DataByte T2 0 330 R sp ifpbo20 DataByte To 056345 R se itpbo28 DataByte27 As defined by the EIA CEA 861 specifications The Source Product Descriptor SPD InfoFrame registers are considered valid if the following two conditions are met e spd infoframe det is 1 e spd inf cksum err is 0 This condition only applies if always store infis set to 1 Rev 0 Page 196 of 326 06 707 5 9 5 MPEG Source InfoFrame Registers Table 37 provides a list of readback registers available for the MPEG InfoFrame Refer to the EIA CEA 861 specifications for a detailed explanation of the MPEG InfoFrame fields Table 37 MPEG InfoFrame Registers InfoFrame Access Register Name Byte Map Address Type OxE3E9 R W Packet Type Value OxE3EA ms_infvers InfoFrame version number OxE3EB InfoFrame length 0 346 R Checksum 0 3 R msifpbos DataByte4 055552 R DataByte12 0 53 ms inf pb O 14 Data Byte 13 As defined by th
115. fieldbuffer2 addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 2 svsp fieldbuffer3 addr 31 0 Secondary VSP Map Address OxE60C 7 0 Address 0xE60D 7 0 Address OxEGOE 7 0 Address OxEGOF 7 0 This signal is used to set the start address of frame buffer 3 Software should arrange memory space properly avoiding conflict between different buffers Function svsp fieldbuffer3 addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 3 svsp fieldbuffer4 addr 31 0 Secondary VSP Map Address 0xE664 7 0 Address 0xE665 7 0 Address 0xE666 7 0 Address 0xE667 7 0 This signal is used to set the start address of field frame buffer 4 Software should arrange memory space properly avoiding conflict between different buffers Function svsp fieldbuffer4 addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 4 svsp fieldbuffer5 addr 31 0 Secondary VSP Map Address 0xE668 7 0 Address 0xE669 7 0 Address OxE66A 7 0 Address OxEG66B 7 0 This signal is used to set the start address of field frame buffer 5 Software should arrange memory space properly avoiding conflict between different buffers Function svsp fieldbuffer5 addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 5 svsp fieldbuffer6 addr 31 0 Secondary VSP Map Address 0xE66C 7 0 Address
116. follows PVSP This is the main scaler of the ADV8005 and contains many of the signal processing functions This block performs motion adaptive de interlacing as well as scaling ACE FRC cadence detection CUE correction RNR BNR and MNR PVSP utilizes the external DDR2 memory for such processes as FRC de interlacing and RNR Refer to Section 3 2 for more details on the PVSP SVSP This is the secondary scaler in the ADV8005 and is useful when providing an additional output resolution The input to this block can only be progressive This means an input format can only be connected to the SVSP if it is progressive or if it has been de interlaced by the PVSP block Refer to Section 3 3 for more details on the SVSP OSD Blend This block overlays the generated OSD on the incoming video signal from the Serial Video input lines or from the video TTL port This is determined by an alpha factor as to how transparent the OSD will be Depending on the source of the OSD data from an external OSD solution or DDR2 memory this is then synchronized with the incoming video signal If the generated resolution is the same as the video the OSD is simply overlaid on the video If both are at different resolutions the OSD scaler will first scale the OSD data to match the incoming video Refer to Section 3 for more details on the OSD Progressive to Interlaced The ADV8005 has two progressive to interlaced PtoI blocks one of these is included as part of t
117. gm es N Port Formatting gr c CSC amp ACE STEEP D 720p Video RX SD from Serial Data Encoder Transceiver Video Formatting 480i OSD Only i n amp CSC Figure 18 8005 Mode 8 Configuration Mode 8 is similar to mode 7 in that OSD is not overlaid on the input video but rather output as the OSD video on its own This may be required when HDMI video from an upstream IC is copy protected as in Figure 18 but the OSD is still required on the analog outputs In this mode the input format is 720p from an external video transceiver and passed to the OSD blend As the OSD is generated at the same resolution as the input video they are just blended This is then passed to the PVSP where it is upscaled and sent to both HDMI transmitters If this data is copy protected this cannot be passed to the analog outputs The OSD on its own however can be passed directly to these outputs In the example in Figure 18 the OSD is scaled down to 480p and passed through the block and sent out on the SD encoder The difference between mode 7 and mode 8 is very similar to the difference between modes 2 and 4 Ideally the video and OSD should be scaled separately and then blended Rev 0 Page 34 of 326 06 707 2 1 10 Mode 9 Bypass Mode 9 should be used if input video is to be passed straight to the output with no video processing Mode 9 Bypass
118. includes a high speed digital to analog video encoder available with and without Rovi content protection Six high speed Noise Shaped Video 5 12 bit video DACs provide support for composite CVBS S video and component YPrPb RGB analog outputs in either SD ED or HD video formats up to 1080p In addition simultaneous SD and ED HD formats are supported 216 MHz SD Rev 0 Page 14 of 326 06 707 and ED and 297 MHz HD oversampling ensures that external output filtering is not required The final option to output video from the ADV8005 is the TTL interface which allows up to 36 of the pins to be reconfigured as outputs This facilitates the output of up to 1080p 12 bit deep color from the ADV8005 to an FPGA without the requirement of an expensive FPGA based HDMI phy The ADV8005 supports all common consumer formats as outlined in the EIA 861 specification and many common professional output formats as outlined in the VESA specification The part supports the I2C and SPI protocols for communication with the system microcontroller Note There are four options within the ADV8005 family of parts each with different capabilities but all in the same CSPBGA 425 package These are described in Table 1 Table 1 Available Features Within ADV8005 Family of ICs Maximum HDMI Tx Analog TTL Part Number Max Speed Resolution Outputs Outputs Rovi VSP OSD Out ADV8005KBCZ 4k x 2k at 30 Hz 8 2 Six 12 bit DACs Yes 2 Yes Yes 8A
119. is supplied to DAC 3 Function dac3 sel 2 0 Description 0 CVBS or Black Burst 1 Luma 2 default Chroma 3 Y G 4 Pb B 5 Pr R dac4 sel 2 0 Encoder Map Address 0xE42A 2 0 This signal selects the data that is supplied to DAC 4 Function dac4 sel 2 0 Description 0 CVBS or Black Burst 1 Luma 2 Chroma 3 default Y G 4 Pb B 5 Pr R dac5 sel 2 0 Encoder Map Address OxE42B 6 4 This signal selects the data that is supplied to DAC 5 Function dac5 sel 2 0 Description 0 CVBS or Black Burst 1 Luma 2 Chroma 3 Y G 4 default Pb B 5 Pr R dac6 sel 2 0 Encoder Map Address OxE42B 2 0 This signal selects the data that is supplied to DAC 6 Function dac6 sel 2 0 Description 0 CVBS or Black Burst 1 Luma 2 Chroma 3 Y G 4 Pb B 5 default Pr R 7 4 ADDITIONAL DESIGN FEATURES This section outlines the various design features of the encoder which can be used to improve the overall video quality and the ADV8005 performance in a system Many of these functions are optional and should be set depending on a user s application 7 4 1 Output Oversampling Rev 0 Page 254 of 326 06 707 The ADV8005 encoder core includes two on chip phase locked loops PLLs that allow oversampling of SD ED and HD video data Oversampling effectively increases the bandwidth of the output video data which means that expensive analog filters are not needed at the
120. is used both by the audio Rx and the pixel rep Other values reserved Function i2s_sf 3 0 0000 default 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 subpktO 1 src 2 0 TX2 Main Map Address OxF40E 5 3 Description 44 1kHz Do not use 48kHz 32kHz Do not use Do not use Do not use Do not use 88 2kHz Do not use 96kHz Do not use 176 4kHz Do not use 192kHz Do not use This signal is used to specify the source of sub packet 0 left channel Function subpktO 1 src 2 0 Description 000 default 125101 left channel 001 125101 right channel 010 125111 left channel 011 I2S 1 right channel 100 125121 left channel 101 I2S 2 right channel 110 125 3 left channel 111 I2S 3 right channel subpktO r src 2 0 TX2 Map Address OxFA40E 2 0 This signal is used to specify the source of sub packet 0 right channel Function subpktO src 2 0 Description 000 001 default 010 011 100 101 110 111 125101 left channel I2S 0 right channel 12S 1 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 125 3 left channel I2S 3 right channel subpktl 1 src 2 0 TX2 Main Map Address OxF40F 5 3 This signal is used to specify the source of sub packet 1 left channel Rev 0 Page 223 of 326 06 707 Function subpkt1 src 2 0 Description 000 001 010
121. is used to lock the Video Output Module VOM If the Primary VSP is running and this bit is set to 1 the VOM will be locked to a current register setting to display the last frame The Primary VSP registers can be configured safely in this state All new register settings will be updated after this bit is set back to 0 Function pvsp lock vom Description 0 default Unlock VOM 1 Lock VOM Rev 0 Page 120 of 326 06 707 Note This register should be used only as part of the gentle reboot protocol Refer to Section 3 4 3 for more details pvsp update vom Primary VSP Map Address OxE828 4 This bit is used to control the updating of the VOM Registers the VOM can be updated only when update vom is asserted To modify registers in the VOM pvsp update vom should be de asserted The registers can then be modified pvsp update vom should then be asserted to let the VOM use the updated register value in the next frame This procedure will guarantee the correctness of the VOM configuration Function pvsp update vom Description 0 Do not update VOM 1 default Update VOM Note Refer to Section 3 4 for more details on configuring the PVSP registers 3 2 3 1 Pixel Unpacker The pixel unpacker in the VOM is very similar to that in the VIM It is used to convert external memory words into video pixel YCbCr data Pixels in external memory have the following four different data formats the same as those set by the
122. latency measuring 1 Enable frame latency measuring pvsp rb frame latency 2 0 Primary VSP Map Address 0xE870 6 4 Read Only This signal is used to indicate the real time vsync latency Function pvsp rb frame latency 2 0 Description OxXXX number of frame latency pvsp_rb_hsync_latency 11 0 Primary VSP Map Address 0xE875 7 0 Address 0xE876 7 4 Read Only This signal is used to indicate the real time Hsync latency Function pvsp rb hsync latency 11 0 Description OxXXX number of hsync latency pvsp rb max latency 14 0 Primary VSP Map Address 217 0 Address OxESF3 7 1 Read Only This signal is used to record the maximum frame latency Function pvsp rb max latency 14 0 Description OxXXX Maximum of frame latency pvsp_rb_min_latency 14 0 Primary VSP Map Address 0 8 4 7 0 Address 0 8 5 7 1 Read Only This is signal is used to record the minimum frame latency Function pvsp_rb_min_latency 14 0 OxXXX Description Minimum of frame latency 3 2 1 6 Game Mode Frame latency should be as small as possible for gaming applications PVSP supports a game mode which has nearly zero frame latency latency less than 5 lines To enable the game mode of PVSP pvsp bypass ddr mode should be asserted pvsp bypass ddr mode Primary VSP Map Address 0xE84D 5 This bit is used to enable game mode for the Primary VSP Rev 0 Page 112 of 326 06 707 Func
123. locations are fixed and cannot be changed 0 16 240 and 255 Rev 0 Page 269 of 326 06 707 From the curve locations 16 to 240 the values at the programmable locations and therefore the response of the gamma correction curve should be calculated to produce the following result XDESIRED Xixpur where Xpesirep is the desired gamma corrected output xinput is the linear input signal y is the gamma correction factor To program the gamma correction registers the 10 programmable curve values are calculated using Equation 29 E Y 225 240 16 16 240 16 Equation 29 Gamma Correction Calculation where is the value to be written into the gamma correction register for point on the gamma correction curve n 24 32 48 64 80 96 128 160 192 or 224 yis the gamma correction factor For example setting y 0 5 for all programmable curve data points results in the following values ya 8 224 5 x 224 16 58 16 224 gt x 224 16 76 32 224 5 x 224 16 101 48 224 5 x 224 16 120 64 224 5 x 224 16 136 80 224 5 224 16 150 yus 112 224 55 x 224 16 174 Jio 144 224 5 x 224 16 195 176 224 5 x 224 16 214 ya 208 224 x 224 16 232 yn yas yso y Where the sum of each equation is rounded to the nearest integer these must then all be converted to hex The gamma curves in Figure 120 an
124. lowest quality of the converted formats Rev 0 Page 26 of 326 480i Video from Decoder OSD rendered at a single set resolution 720p U6 707 Input E xosd Muxing Secondary 24 bit Data Input A Formatting Port ME 4 amp CSC A Video aN 36 bit 2 Input L Do Port Formatting CSC amp ACE Se i y Data 1 Formatting RX amp CSC DDR2 Memory Interface HDMI Tx1 HDMI Tx2 HD Encoder Encoder famam SD 1080p 1080i 720p OSD 480i Figure 11 ADV8005 Mode 1 Configuration Mode 1 places the PVSP after the input block The output from this block is then sent to the SVSP or the PtoI converter The OSD blend block can then be placed after the SVSP block In the example in Figure 11 the input resolution is taken to be 480i This is then passed through the PVSP where it is converted to 1080p using motion adaptive de interlacing This can then be passed straight to the output to the PtoI converter or alternatively to the SVSP and OSD blend The example output formats generated using this mode are 720p with OSD 1080p and 1080i The input SD format of 480i can also be passed to the SD encoder Rev 0 Page 27 of 326 06 707 2 1 3 Mode 2 Mode 2 should be used if e Three separate output formats are required e Additional processing BNR RNR and so on is require
125. lt 128 fS 300Hz Equation 24 Restriction for N Value 128 fs 1000Hz Equation 25 Optimal N Value 6 11 4 2 CTS Parameter The CTS value is an integer number that satisfies Equation 26 7 TMDS CLK CTS ond 128 f Equation 26 Relationship Between N and CTS 6 11 4 3 Recommended N and Expected CTS Values The recommended values of N for several standard pixel clocks are given in Table 60 to Table 62 The ADV8005 has two modes for CTS generation Manual mode Manual mode is selected by setting cts sel to 1 In manual mode the user can program the CTS number directly into the chip via the cts manual 19 0 field Manual mode is good for coherent audio and video where the audio and video clocks are generated from the same crystal thus CTS should be a fixed number Automatic mode Automatic mode is selected by setting cts sel to 0 In automatic mode the chip computes the CTS based on the actual audio and video rates The result can be read from the cts internal 19 0 field Automatic mode is good for incoherent audio or video where there is no simple integer ratio between the audio and video clock The 20 bit n value used by the Tx core of the ADV8005 can be programmed in the n 19 0 field cts sel TX2 Main Map Address 0xF40A 7 This bit is used to specify whether CTS is automatically or manually set Function cts sel Description 0 default Automatic CTS Use the internally generated CTS value 1 Manual CTS Use the CTS p
126. must be converted into 120 bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range 1 1 or 4096 4095 The dynamic range of the CSC is 0 1 for unipolar signals G B or 0 5 0 5 for bipolar signals Bipolar signals Pr Pb must be offset to mid range Equations with a dynamic range larger than 1 need to be scaled appropriately using the vid mode 1 0 control To achieve a coefficient value of 1 0 for any given coefficient vid mode 1 0 should be set high and the coefficient should be programmed to a value of 0 5 Otherwise the largest value would be 4095 4096 0 9997 While this value could be interpreted as 1 it is recommended to use the value of 0 5 and set the vid mode 1 0 bits for maximum accuracy The CSC configurations for common modes are provided in Table 11 Table 11 Primary Input Channel CSC Common Configuration Coefficients Color Space Conversion HDTV YCbCr 0x0C53 0 0800 0 0000 0x19D6 0 1 56 0 0800 OxOE85 0x18BE limited to RGB limited HDTV YCbCr 0 2 0 0734 0x04AD 0 0000 0x1C1B 10 100 0x04AD 0x087C 0 1 77 limited to RGB full HDTV YCbCr 0 0700 0 0000 Ox1F6C 0 005 0 0188 0 0800 OxO7EB 0x007B limited to SDTV YCbCr limited HDTV YCbCr 0 1 OxOSEB 0 0000 0 1 58 Ox1FDE 0 01 9 0 0950 Ox08FA 0x031F limited to SDTV YCbC
127. number word length 3 0 TX2 Main Map Address 0xF414 3 0 This signal is used to set the Channel Status Audio Word Length Refer to the IEC 60958 3 specification Function word length 3 0 Description 0000 default Not specified 0001 Not specified 0010 16 bits 0011 20 bits 0100 18 bits 0101 22 bits 0110 Reserved 0111 Reserved 1000 19 bits 1001 23 bits 1010 20 bits 1011 24 bits 1100 17 bits 1101 21 bits 1110 Reserved 1111 Reserved Rev 0 Page 233 of 326 06 707 channel status 1 0 2 Map Address 0xF412 7 6 This signal is used to set the Channel Status bits 1 0 Set to 0500 as specified in IEC60958 3 Refer to IEC60958 3 specification Function channel status 1 0 Description XX Channel status bits 0 and 1 Table 63 PS Channel Status ADV8005 Register Map Location of Fixed Value ChannelStatus Channel Status Bit Name Main Map Bit Location or Fixed Main Map Bit Name or Fixed Bit Value Value 0 Consumer use 0 12 6 channel status 0 1 Audio sample word OxEC12 7 channel status 1 2 Copyright OxEC12 5 cr bit 3 Emphasis OxEC12 2 a info 0 4 Emphasis OxEC12 3 a info 1 5 Emphasis OxEC12 4 a info 2 6 Mode 0 0 7 Mode 0 0 8 Category code OxEC13 0 category code 0 9 Category code OxEC13 1 category code 1 10 Category code OxEC
128. of filter A and filter B is used Both settings for Gain A and Gain B in the ED HD sharpness filter gain register and ED HD adaptive filter Gain 1 Gain 2 and Gain 3 registers become active when needed The mode is selected using adapt bc adapt bc Encoder Map Address OxE435 6 This bit is used to select the adaptive filter mode Function adapt bc Description 0 default Mode A 1 Mode B 7 4 18 4 ED HD Sharpness Filter and Adaptive Filter Application Examples Sharpness Filter Application The ED HD sharpness filter can be used to enhance or attenuate the Y video output signal The register settings in Table 80 are used to achieve the results shown in Figure 123 Input data is generated by an external signal source The reference in the table can be matched with the appropriate scope plot Table 80 ED HD Sharpness Control Settings for Figure 123 Register Register Setting Reference OxE400 OxE401 OxE402 OxE430 OxE431 0 440 0 440 0 440 0 440 0 440 0 440 1 See Figure 123 Rev 0 Page 276 of 326 06 707 b wD c E 1 x 500 4 00 CH1 500mV 4 00ys CH1 5 500mV 4 0045 9 99978 ALL FIELDS REFA 500 4 00us 9 99978ms ALLFIELDS Figure 123 ED HD Sharpness Filter Control with Different Gain Set
129. output timing Rev 0 Page 131 of 326 06 707 pvsp dp hsynctime 11 0 Primary VSP Map Address OxE85A 3 0 Address OxE85B 7 0 This signal sets the Hsync duration of output timing This register s value will be used while pvsp autocfg output vid is 0 Function pvsp dp hsynctime 11 0 Description 0x000 default Default OxXXX Hsync width of output timing pvsp dp hbackporch 11 0 Primary VSP Map Address 0xE85C 3 0 Address OxE85D 7 0 This signal is used to set the horizontal back porch duration of output timing This register s value will be used while pvsp_autocfg_output_vid is 0 Function pvsp_dp_hbackporch 11 0 Description 0x000 default Default OxXXX Horizontal back porch of output timing pvsp dp activeline 11 0 Primary VSP Map Address 0xE85E 3 0 Address OxES5F 7 0 This signal is used to set the active line number of output timing This register s value will be used while pvsp_autocfg_output_vid is 0 Function pvsp_dp_activeline 11 0 Description 0x000 default Default OxXXX Active lines of output timing pvsp dp vfrontporch 9 0 Primary VSP Map Address 0 860 1 0 Address 0xE861 7 0 This signal is used to set the vertical front porch duration of output timing This register s value will be used while pvsp_autocfg_output_vid is 0 Function pvsp dp vfrontporch 9 0 Description 0x000 default Default OxXXX Vertical front porch of output timing
130. section Rev 0 Page 178 of 326 ADV8005 Hardware Reference Manual 4 2 8 1 Overview It is possible to access the DDR2 and OSD SPI registers in one of two ways e ADV8005 SPI master interface serial port 2 can pull in resource data to DDR2 memory from an external SPI flash memory as shown in Figure 86 e system MCU SPI master can write OSD data into DDR2 memory using the ADV8005 SPI slave interface serial port 1 as shown in Figure 87 Config Register OSD CORE SPI 12 A o ES FLASH System DDR2 Memory MEM Controller CPU Figure 86 Data Loaded from SPI Flash Through ADV8005 SPI Master Interface Rev 0 Page 179 of 326 06 707 OSD CORE Config Register cm SPI Master DDR2 Memory Figure 87 MCU as SPI Master Sending OSD Data Through ADV8005 SPI Slave Interface Additionally the system MCU SPI master can program the external flash by looping SPI commands through the SPI slave serial port 1 and the SPI master serial port 2 interfaces connected in a chain In this mode the OSD core just passes through MOSI SS and SCLK signals from the MCU to the flash Note that the system MCU is responsible for any error protection in this mode as shown in Figure 88 This option can be useful during the final debug stage of the OSD in which the OSD design
131. significant bit of a number is referred to as Bit O VDCY Bit field representation covering bit X to Y of a value or a field V OxNN Hexadecimal base 16 numbers are preceded by the prefix Ox ObNN Binary base 2 numbers are preceded by the prefix Ob NN Decimal base 10 are represented using no additional prefixes or suffixes REGISTER ACCESS CONVENTIONS Mode Description R W Memory location has read and write access R Memory location has read access only A read always returns 0 unless specified otherwise Memory location has write access only ACRONYMS AND ABBREVIATIONS This is a list of common acronyms and abbreviations found in Analog Devices Hardware Manuals Acronym Abbreviation Description ACP Audio Content Protection ACR Audio Clock Regeneration ADC Analog to Digital Converter AFE Analog Front End AGC Automatic Gain Control Ainfo HDCP register Refer to HDCP documentation AKSV HDCP Transmitter Key Selection Vector Refer to HDCP documentation An 64 bit pseudo random value generated by HDCP cipher function of device A ARC Audio Return Channel AUD IN Audio Input Pin AVI Auxiliary Video Information Aux Auxiliary Bcaps HDCP register Refer to HDCP documentation Rev 0 Page 9 of 326 06 707 Acronym Abbreviation Description BGA Ball Grid Array
132. specification Rev 0 Page 232 of 326 06 707 Function cr bit Description 0 default Copyright asserted 1 Copyright not asserted info 2 0 TX2 Main Map Address 0xF412 4 2 This signal is used to set the Channel Status Emphasis information Refer to the IEC 60958 3 specification Function a info 2 0 Description 000 default 2audio channels without pre emphasis 001 2 audio channels with 50 15uS pre emphasis 010 Reserved for 2 audio channels with pre emphasis 011 Reserved for 2 audio channels with pre emphasis 100 111 Reserved acc 1 0 TX2 Main Map Address OxF412 1 0 This signal is used to set the Channel Status Clock Accuracy information Refer to the IEC 60958 3 specification Function acc 1 0 Description 00 default level Il normal accuracy 1000 x 10 6 01 level 1 high accuracy 50 x 10 6 10 level Ill variable pitch shifted clock 11 Reserved category code 7 0 TX2 Main Map Address 0xF413 7 0 This register is used to set the Channel Status Category Code Refer to the IEC 60958 3 specification Function category code 7 0 Description 00000000 default Default value XXXXXXXX Channel Status category code source number 3 0 TX2 Main Map Address 0 414 7 4 This signal is used to set the Channel Status source number Function source number 3 0 Description 0000 default Default value XXXX Channel Status source
133. still be displayed on analog output for example to indicate system status or to recover the system from an error like state In this mode the input format is 720p from an external video transceiver this could also come from the Video TTL input if video is from an upstream HDMI IC and is passed to the PVSP This is upscaled blended with the 1080p OSD data and sent to both HDMI transmitters Because this may be copy protected this cannot be passed to the analog outputs The OSD on its own however can be passed directly to these outputs In the example in Figure 17 the OSD is scaled down to 480p and passed to the HD encoder Rev 0 Page 33 of 326 06 707 2 1 9 Mode 8 Mode 8 should be used if e HDMI input video is copy protected e Additional processing is required on the new output formats e OSD is required on multiple outputs e OSD and video scaling are to be kept separate Mode 8 OSD rendered at a single set resolution 720p DDR2 Memory Interface Build OSD Video Prima Output Txi 55 Muxing 1080p OSD EX 1080p Exosd oj 5 Muxing Secondary 24 bit Data Input gt r Formatting cy SS Tx Port 7 8 CSC M 1080p OSD v Ws Secondary eee VSP Video 7 TUE Y 480p Progressive to 480i 36 bit 27 Primary Ny Interlaced HD NEN Data Input Le 4
134. that the rest of the bits within this register perform the same operation as for timerl but for the other seven timers i e bit 1 controls timer2 bit 2 controls timer3 etc they are not included here for readability reasons timerl reset SPI Device Address 0x0B TIMER Address 0 04 0 Timer 1 Reset Rev 0 Page 175 of 326 06 707 Function timer1 reset Description 0 Not reset 1 Reset Enabling this reset will clear the timer cnt and timer irq cnt registers Note that the rest of the bits within this register perform the same operation as for but for the other seven timers that is bit 1 controls timer2 bit 2 controls timer3 and so on they are not included here for readability reasons timerl loop mode SPI Device Address 0x0B TIMER Address 0x05 0 Timer 1 Mode Control Function timer1 loop mode Description 0 One time mode 1 Infinite mode When working in one time mode after the interval is reached the timer will stop by itself that is there is no need to set timer enable to disabled When working in infinite mode timer keep result should be set to 0 Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers that is bit 1 controls timer2 bit 2 controls timer3 and so they are not included here for readability reasons timerl keep result SPI Device Address 0x0B TIMER Address 0 06 0
135. the ADV8005 can be set via the audio mode 1 0 field The audio sampling frequency must be set via the audioif sf 2 0 field Note the DSD clock input to SCLK has a frequency that is 64 times the audio sampling frequency programmed in the audioif sf 2 0 field Refer to Table 58 for additional details on the DSD modes supported by the ADV8005 Table 59 Valid Configuration for audioif sf 2 0 Address B8 Main Address 0x74 4 2 audio input sel Value audioif sf Value Options Corresponding Configuration 06010 05000 Not DSD Audio 0b010 0b001 DSD Audio 64x32 kHz 0b010 DSD Audio 64x44 1 kHz 0b011 DSD Audio 64x48 kHz 0b100 DSD Audio 64x88 2 kHz 0b101 DSD Audio 64x96 kHz 0b110 DSD Audio 64x176 4 kHz 0b111 DSD Audio 64x192 kHz 6 11 3 4 HBR Audio The ADV8005 uses an HBR audio packet to transmit across the TMDS link compressed audio streams conforming to IEC 61937 and with high bit rate that is bit rate higher than 6 144 Mbps The ADV8005 can be configured to receive an HBR stream by setting audio input sel 2 0 to 05011 The use of one or four input stream s with or without biphase mark BPM encoding can be selected via the audio mode 1 0 field Note that an audio master clock input through the pin MCLK IN is always required for the BPM encoding modes For HBR mode the audio sampling frequency must be set via the audioif sf 2 0 field papb sync can be toggled from 0 to 1 to synchronize th
136. the Primary Input Channel Function inp chan sel 1 0 Description 00 default Video TTL input P 35 0 01 EXOSD TTL Input OSD 23 01 10 48 bit TTL input OSD_IN 11 0 and P 35 0 for 3GHz interleaved TTL 11 Reserved vid format sel 4 0 IO Map Address 0x1B48 4 0 This signal is used to select the input format for the video data Function vid format sel 4 0 Description 0x00 1 x 8 bit bus SDR 4 2 2 0x01 1 x 10 bit bus SDR 4 2 2 0x02 1 x 12 bit bus SDR 4 2 2 0x03 2 x 8 bit buses SDR 4 2 2 0x04 2x 10 bit buses SDR 4 2 2 0x05 2 x 12 bit buses SDR 4 2 2 0x06 3 x 8 bit buses SDR 4 4 4 P 35 28 P 23 16 P 11 4 0x07 3x 10 bit buses SDR 4 4 4 P 35 26 P 23 14 P 11 2 0x08 default 3 x 12 bit buses SDR 4 4 4 0x09 1 x 8 bit bus DDR 4 2 2 Ox0A 1x 10 bit bus DDR 4 2 2 OxOB 1x 12 bit bus DDR 4 2 2 OxOC 3x8 bit buses SDR 4 4 4 P 23 0 OxOD 2x3x8 bit interleaved buses SDR 4 4 4 OxOE 2 x 2 x 8 bit interleaved buses SDR 4 2 2 OxOF 2x2x 10 bit interleaved buses SDR 4 2 2 0x10 2 2 12 bit interleaved buses SDR 4 2 2 0x11 3 x 10 bit buses SDR 4 4 4 P 29 0 0x12 3 x 7 bit buses SDR 4 4 4 for external alpha blend 0x13 3 10 bit buses SDR 4 4 4 OSD_IN 23 0 and P 35 30 vid swap bus ctrl 2 0 IO Map Address 0x1B48 7 5 This signal is used to control the video input pixel bus The input pixel bus is 36 bits wide and is divided into three data channels Top
137. the VOM display module work 4K x 2K mode This register s value will be used while autocfg output vid is 0 Function pvsp dp 4kx2k mode en Description 0 default Not in 4K x 2K mode 1 In 4K x 2K mode pvsp data clipping en Primary VSP Map Address OxE84E 3 This bit is used to limit the output data within range of 16 235 Function pvsp data clipping en Description 0 default Not limit output data 1 Limit output data pvsp man dp timing enable Primary VSP Map Address OxE883 0 This bit is used to enable the manual setting of the display port s timing Function pvsp man dp timing enable Description 0 default Disable manually setting output timing 1 Enable manually setting output timing pvsp dp decount 12 0 Primary VSP Map Address OxE856 4 0 Address 0xE857 7 0 This signal is used to set the DE duration of output timing This register s value will be used while pvsp autocfg output vid is 0 Function pvsp dp decount 12 0 Description 0x000 default Default OxXXX Data enable count of output timing pvsp dp hfrontporch 11 0 Primary VSP Map Address 0 858 3 0 Address 0xE859 7 0 This signal is used to set the horizontal front porch duration of output timing This register s value will be used while pvsp autocfg output vid is 0 Function pvsp dp hfrontporch 11 0 Description 0x000 default Default OxXXX Horizontal front porch of
138. the coring gain border in Digital Noise Reduction DNR mode the values in brackets apply Function dnr coring gain a 3 0 Description 0000 default No gain 0001 11 16 1 8 0010 42 16 2 8 0011 3 16 3 8 0100 14 16 4 8 0101 15 16 5 8 0110 16 16 6 8 0111 17 16 7 8 1000 18 16 1 7 4 19 2 Coring Gain Data dnr coring gain b 3 0 is the gain factor applied to the luma data inside the MPEG pixel block In DNR mode the range of gain values is 0 to 1 in decrements of 1 8 This factor is applied to the DNR filter output that lies below the set threshold range The result is then subtracted from the original signal In DNR sharpness mode the range of gain values is 0 to 0 5 in increments of 1 16 This factor is applied to the DNR filter output that lies above the threshold range The result is added to the original signal Figure 128 explains the difference between SD DNR border gain and data gain APPLY DATA APPLY BORDER CORING CORING GAIN exxxxxxojoxxxxxxo i 4 OFFSET CAUSED OXXXXXXOlOXXXXXXO BY VARIATIONS IN INPUT TIMING DNR27 TO DNR24 0x01 Figure 128 SD DNR Offset Control 06398 079 dnr coring gain b 3 0 Encoder Map Address 0xE4A3 3 0 This signal is used to configure the coring gain data in Digital Noise Reduction DNR mode the values in brackets apply Function dnr coring gain b 3 0 Description 0000 default No ga
139. the user Configuring this manually allows the user to have very flexible control over the external DDR memory These programmed field buffers or frame buffers are allocated by setting the following registers pvsp fieldbuffer0 addr 31 0 pvsp fieldbufferl addr 31 0 fieldbuffer2 addr 31 0 pvsp fieldbuffer3 addr 31 0 fieldbuffer4 addr 31 0 pvsp fieldbuffer5 addr 31 0 and pvsp fieldbuffer6 addr 31 0 The value programmed into each of these registers is determined by Equation 19 active video widthxactive video height 1 PVSP IS I TO P Equation 19 Calculating External Memory Field Buffers field sizes xbytes per pixel where Rev 0 Page 109 of 326 06 707 5 15 I TO P indicates whether the input timing is interlaced or progressive interlaced 1 progressive 0 bytes per pixel indicates the number of bytes required to store each pixel refer to Table 23 for more details on the number of bytes required per pixel For example for an input video resolution of 720p Equation 19 would yield the following field size Field size 720 x 1280 x4 3686400 The following values would then need to be programmed to the above registers pvsp_fieldbuffer0_addr 31 0 0 pvsp fieldbufferl addr 31 0 38400 3686400 in hex pvsp fieldbuffer2 addr 31 0 70800 7372800 in hex Note The default value of the field frame buffer is set for a 1080p input If the maximum supported video is 1080p there i
140. this case the user can use the following methods to measure frame latency Rev 0 Page 111 of 326 06 707 pvsp rb frame latency 2 0 and pvsp rb hsync latency 11 0 are read only registers Their values are real time frame and HSync latency between input and output video Frame latency may vary within a range the pvsp rb max latency 14 0 readback register indicates the maximum frame latency while pvsp rb min latency 14 0 indicates the minimum frame latency If pvsp frc latency measure en is set to 0 pvsp rb max latency 14 0 and pvsp rb min latency 14 0 are cleared If asserting frc latency measure en the PVSP will monitor the values pvsp rb frame latency 2 0 pvsp rb hsync latency 11 0 then record their maximum and minimum values pvsp rb max latency 14 0 pvsp rb min latency 14 0 Both of these signals are 15 bits wide the highest 3 bits are the frame latency and the lowest 12 bits are the HSync latency Note that it will take several seconds for PVSP to find the maximum and minimum frame HSync latency In a normal case not game mode the PVSP s input video and output video latency are consistent pvsp frc latency measure en Primary VSP Map Address OxESFO0 6 This bit is used to enable frame latency measuring The results are recorded in rb max latency and pvsp rb min latency Function pvsp frc latency measure e Description n 0 default Disable frame
141. this pin to ground through a 4 7 resistor Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default Pin Type N A N A Analog input N A Digital output Digital output Digital input Digital input Digital input Digital input N A N A N A N A N A N A N A N A N A N A N A Digital output N A Digital output Digital output Digital input Digital input Digital input Digital input N A N A Bi directional digital IO Bi directional digital IO Digital input Digital input Digital input Digital input Rev 0 Page 309 of 326 06 707 Location W20 W22 W23 Y1 Y2 Y w Y4 Y Y Y N OV Y10 Y11 Y12 Y13 Y1 Y15 Y16 Y17 A Y18 Y19 Y2 Y2 Y2 Y2 AA 2 N Ui lt OV Description if Unused p 11 00 TEST3 Miscellaneous Floatthis pin digital PVDD6 Power HDMI Tx PLL Power Supply 1 8 V This pin is a voltage regulator output Connect a decoupling capacitor between this pin and ground AVDD3 HDMI Analog Power Supply 1 8 V Float this pin Digital video Float this pin as it is disabled by default input P 1 Digital video Float this pin as it is disabled by default input DDR D
142. this protocol All registers except output video timing registers can be accessed pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 Start pvsp lock vom 0 pvsp update vom 1 pvsp enable ffs 1 pvsp enable vim 0 Disable VIM pvsp enable vom 1 pvsp lock vom 0 pvsp update vom 1 Lock VOM pvsp enable ffs 1 pvsp enable vim 0 pvsp enable vom 1 pvsp lock vom 1 pvsp update vom 1 Disable FFS pvsp enable ffs 0 pvsp enable vim 0 pvsp enable vom 1 pvsp lock vom 1 pvsp update vom 1 Configure all registers except display port output timing pvsp enable ffs 0 registers pvsp enable vim 0 pvsp enable vom 1 pvsp lock vom 1 pvsp update vom 1 Enable FFS pvsp enable ffs 1 pvsp enable vim 0 pvsp enable vom 1 pvsp lock vom 1 pvsp update vom 1 Enable VIM pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 pvsp lock vom 1 pvsp update vom 1 Unlock VOM pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 Figure 71 Gentle Reboot Protocol Flowchart pvsp lock vom 0 pvsp update vom 1 Figure 71 shows the process for the gentle reboot protocol for the PVSP This is exactly the same for the SVSP with the appropriate registers replaced Rev 0 Page 158 of 326 06 707 3 4 4 Set Protocol The VOM set protocol is used to configure the VOM The registers in the VOM can be accessed without affecting the output video timing
143. to 2 which indicates the input resolution is 720x480 but the actual resolution is 718x478 the user can manually set svsp autocfg input vid 7 0 to be 0 and set the input resolution through the following three registers svsp man input res Secondary VSP Map Address 0 663 4 This bit is used to enable manual configuration of input resolution Function svsp man input res Description 0 default Disable manual configuration of input resolution 1 Enable manual configuration of input resolution svsp vin h 12 0 Secondary VSP Map Address 0xE616 7 0 Address OxE617 7 3 This signal is used to set the horizontal resolution of the input video This register s value will be used while svsp man input res is 1 or svsp autocfg input vid is 1 Function svsp vin h 12 0 Description 0x000 default Default OxXXX Horizontal resolution of input video svsp vin v 12 0 Secondary VSP Map Address 0 618 7 0 Address 0xE619 7 3 This signal is used to set the vertical resolution of the input video This register s value will be used while svsp_man_input_res is 1 or svsp_autocfg_input_vid is 1 Rev 0 Page 140 of 326 06 707 Function svsp vin v 12 0 Description 0x000 default Default OxXXX Vertical resolution of input video Similarly if the output timing is not in the SVSP output format table the output format needs to be set manually The detailed configuration instruction is given in the SVSP VOM
144. to auto increment register addresses to allow the user to do consecutive reads from the registers on the ADV8005 By default this is set to 1 which means that a read from a particular address in the ADV8005 increments the read pointer to the next register map address read auto inc en IO Map Address 0x1AFC 0 This register is used to auto increment I2C addresses in the device for consecutive reads Function read auto inc en Description 0 No auto increment of I2C address for consecutive reads 1 default Auto increment of I2C address for consecutive reads 2 2 SPI Loop Through The ADV8005 SPI ports can be put in loop through mode for programming the external SPI flash that may be connected to the ADV8005 master SPI port if an OSD design is to be used Refer to Section 4 2 8 for more information spi loop through IO Map Address 0x1AB6 5 This bit is used to enable SPI loop through mode In loop through mode Serial Port 1 SCK1 MOSI1 MISO1 and CS1 is connected to the Serial Port 2 SCK2 MOSD MISO2 CS2 Rev 0 Page 73 of 326 06 707 Function spi loop through Description 0 default Regular SPI mode 1 SPI slave clock routed to SPI master clock output 2 2 8 VBI Data Insertion ADV8005 supports VBI data such as CGMS WSS and CCAP insertion into the video stream through either the ancillary data input Y channel input of 36 bit data bus or the SPI compatible slave input 5 VBI_MOSI
145. to make the auto configuration work The 59 94 23 97 Hz timings have the same VID as the corresponding 60 24Hz timing in Figure 20 pvsp autocfg input vid 7 0 Primary VSP Map Address OxE881 7 0 This register is used to set the input timing VIC If this register is 0 PVSP will use values in registers of pvsp vin pvsp vin v pvsp is i to p and pvsp vin fr to set input video Function pvsp autocfg input vid 7 0 Description 0x06 default Default 480i 60 OxXX Input timing VID Table 19 PVSP Supported Input Video Timing and VID Video Timing VID CEA 640x480p60 1 Rev 0 Page 106 of 326 pvsp autocfg output vid 7 0 Primary VSP Map Address OxE882 7 0 This register is used to set the output timing VIC If this register is 0 PVSP will use values in registers of pvsp decount Video Timing VID 720x480p60 20r3or 14 15 or 35 or 36 720x240p60 8 9 120r 13 1280 720 60 4 1920 1080160 5 720 480160 60r70r 100r 11 1920x1080p 16 720x576p50 17 or 18 or 29 or 30 0r 37 or 38 1280x720p50 19 1920x1080i50 20 720 576150 21 or 22 or 25 or 26 720x288p50 23 or 24 or 27 or 28 1920x1080p50 31 1920x1080p24 32 1920x1080p25 33 1920x1080p30 34 1080i50 even 39 1080i100 40 720p100 41 576p100 42 or 43 576i100 44 or 45 1080i120 46 720p120 47 480p120 48 or 49 480i120 500r 51 576p200 52 or
146. tracking for the SVSP If tracking is to be used in frame rate conversion mode video in id 7 0 autocfg output vid 7 0 PVSP and svsp autocfg output vid 7 0 SVSP should also be set pvsp track en IO Map Address 0x1A44 6 This bit is used to enable tracking of the frequency error to reduce the number of dropped repeated frames for the Primary VSP Function pvsp track en Description 0 default Do not adjust for frequency difference between input and output vertical sync 1 Adjust for frequency difference between input and output vertical sync svsp track en IO Map Address 0x1A44 2 This bit is used to enable tracking of the frequency error to reduce the number of dropped repeated frames for the Secondary VSP Function svsp track en Description 0 default Do not adjust for frequency difference between input and output vertical sync 1 Adjust for frequency difference between input and output vertical sync pvsp err sel IO Map Address Ox1A4E 3 This bit is used to choose between phase locked loop and frequency locked loop for the Primary VSP frame tracking mode Function pvsp err sel Description 0 default Phase error 1 Frequency error svsp err sel IO Map Address Ox1A4F 3 This bit is used to choose between phase locked loop and frequency locked loop for the Secondary VSP frame tracking mode Rev 0 Page 67 of 326 06 707 Function svsp err sel Description 0
147. 0 Page 12 of 326 06 707 HDMI Licensing and LLC High Definition Multimedia Interface Revision 1 4a March 4 2010 Digital Content Protection DCP LLC High bandwidth Digital Content Protection System Revision 1 3 December 21 2006 CEA CEA 861 E A DTV Profile for Uncompressed High Speed Digital Interfaces Revision E September 11 2007 ITU ITU R BT 656 4 Interface for Digital Component Video Signals in 525 Line and 625 Line Television Systems Operating at the 4 2 2 Level of Recommendation ITU R 601 February 1998 ITU ITU R BT 601 5 Studio encoding parameters of digital television for standard 4 3 and widescreen 16 9 aspect ratios December 1995 ITU ITU R BT 709 5 Parameter values for the HDTV standards for production and international programme exchange April 2002 CENELEC EN 50157 Part 1 Domestic and similar electronic equipment interconnection requirements AV link CENELEC EN 50157 Part 2 1 Domestic and similar electronic equipment interconnection requirements AV link CENELEC EN 50157 Part 2 2 Domestic and similar electronic equipment interconnection requirements AV link CENELEC EN 50157 Part 2 3 Domestic and similar electronic equipment interconnection requirements AV link Rev 0 Page 13 of 326 06 707 1 INTRODUCTION TO THE ADV8005 1 1 OVERVIEW The ADV8005 is a video signal processor VSP with TTL and Serial Video inputs that de interlace and scale input video gener
148. 0 SPI Device Address 0x0B TIMER Address 0x22 7 0 Address 0x23 7 0 Address 0x24 7 0 Address 0x25 7 0 Timer 7 interval unit is ms timer8 interval 31 0 SPI Device Address Ox0B TIMER Address 0x26 7 0 Address 0x27 7 0 Address 0x28 7 0 Address 0x29 7 0 Timer 8 interval unit is ms timerl cnt 31 0 SPI Device Address 0x0B TIMER Address 0x2A 7 0 Address 0x2B 7 0 Address 0x2C 7 0 Address 0x2D 7 0 Read Only Timer 1 value unit is ms timer2 cnt 31 0 SPI Device Address 0x0B TIMER Address Ox2E 7 0 Address Ox2F 7 0 Address 0x30 7 0 Address 0x31 7 0 Read Only Timer 2 value unit is ms timer3 cnt 31 0 SPI Device Address 0x0B TIMER Address 0x32 7 0 Address 0x33 7 0 Address 0x34 7 0 Address 0x35 7 0 Read Only Timer 3 value unit is ms timer4 cnt 31 0 SPI Device Address 0x0B TIMER Address 0x36 7 0 Address 0x37 7 0 Address 0x38 7 0 Address 0x39 7 0 Read Only Timer 4 value unit is ms timer5 cnt 31 0 SPI Device Address 0x0B TIMER Address 0x3A 7 0 Address 0x3B 7 0 Address 0x3C 7 0 Address 0x3D 7 0 Read Only Timer 5 value unit is ms timer6 cnt 31 0 SPI Device Address 0 0 TIMER Address Ox3E 7 0 Address Ox3F 7 0 Address 0x40 7 0 Address 0x41 7 0 Read Only Timer 6 value unit is ms Rev 0 Page 177 of 326 06 707 timer7 cnt 31 0 SPI Device Address 0x0B TIMER Address 0x42 7 0 Address 0x43 7 0 Address 0x44 7 0 Address 0x45 7 0 Read O
149. 0 04 0 0000 lox1C81 0x0833 0 0000 0 0099 0 1 99 0 1 56 0 0800 Ox1CBC 0 04 ee 0 0000 0 0000 oxiF6E 0 0000 0 0950 0 0000 0 0043 0 0 26 0 1 44 0 036 0x1893 0 0800 0 0367 0 0871 0x1926 1 0 0800 0 04 9 0 0965 0 0 0 0x0000 OxODBC 0 0000 0 0000 0 0100 Rev 0 94 of 326 OxOE85 0 18 0x087C 0 1 77 OxO7EB 0 007 0 08 0x031F OxOEOD 0 0100 OxODDE 0x081A 0x0826 0x1F78 0x1913 Ox1BA9 0 091 0 1 6 0 0397 0x004D 0 0820 0 0800 0 082 0 0800 OxODBC 0x0100 06 707 Color Space Conversion RGB full to OxO6FF 0 19 6 Ox1F5B 0 0800 OxO2E9 0 09 Ox1A9B 0 06 0 0800 HDTV YCbCr limited RGB full to OxO 0 06 0 1 24 Ox1EDD 0 0800 0 0418 0 080 Ox1B5C 0 06 0 0800 SDTV YCbCr limited RGB Um 0 1 0 0950 0 0000 0 0000 0 1 6 0 0950 0x0000 0 0950 0 1 6 ident EE 0 1 0x0800 0 0000 0 0000 0 0000 0 0800 0 0800 0 0000 Output Input 2 2 12 5 HDMI Transmitter CSCs Both of the HDMI transmitters feature an any to any CSC The CSC register controls for HDMI Tx are described here the same controls co exist in the HDMI Tx2 Main Map for the HDMI Tx2 CSC The CSC must be manually configured for each color space conversion The HDMI Tx CSC output can be enabled using the c
150. 0 Description Packet type value of packet stored in InfoFrame Map Address 0x00 to Ox1B Packet type value of InfoFrame stored InfoFrame Map Address 0x00 to 0 18 spd packet id 7 0 HDMI RX Infoframe Map Address 0xE3E6 7 0 This control is used to set the Source Product Descriptor InfoFrame ID Function spd packet id 7 0 Description Packet type value of packet stored in InfoFrame Map Address 2 to 0x45 Packet type value of InfoFrame stored InfoFrame Map Address 2 to 0x45 aud packet id 7 0 HDMI RX Infoframe Map Address OxE3E3 7 0 This control is used to set the Audio InfoFrame ID Function aud packet id 7 0 Description Packet type value of packet stored in InfoFrame Map Address Ox1C to 0x29 Packet type value of InfoFrame stored InfoFrame Map Address Ox1C to 0x29 ms packet id 7 0 HDMI RX Infoframe Map Address OxE3E9 7 0 This control is used to set the MPEG Source InfoFrame ID Function ms packet id 7 0 Description Packet type value of packet stored in InfoFrame Map Address 0x46 to 0x53 Packet type value of InfoFrame stored InfoFrame Map Address 0x46 to 0x53 vs packet id 7 0 HDMI RX Infoframe Map Address 0xE3EC 7 0 This control is used to set the Vendor Specific InfoFrame ID Rev 0 Page 201 of 326 06 707 Function
151. 0 OxF3C1 R W spare3_header1 7 0 0600000000 Header Byte 1 OxF3C2 R W spare3 header2 7 0 0600000000 Header Byte 2 OxF3C3 R W spare3_byte0 7 0 0b00000000 Data Byte 0 OxF3C4 R W spare3_byte1 7 0 0b00000000 Data Byte 1 OxF3C5 R W spare3_byte2 7 0 0b00000000 Data Byte 2 OxF3C6 R W spare3_byte3 7 0 0b00000000 Data Byte 3 OxF3C7 R W spare3 byte4 7 0 0600000000 Data Byte 4 OxF3C8 R W spare3_byte5 7 0 0b00000000 Data Byte 5 OxF3C9 R W spare3_byte6 7 0 0b00000000 Data Byte 6 OxF3CA R W spare3_byte7 7 0 0b00000000 Data Byte 7 OxF3CB R W spare3_byte8 7 0 0b00000000 Data Byte 8 OxF3CC R W spare3_byte9 7 0 0b00000000 Data Byte 9 OxF3CD R W spare3_byte10 7 0 0b00000000 Data Byte 10 OxF3CE R W spare3 byte11 7 0 0600000000 Data Byte 11 OxF3CF R W spare3_byte12 7 0 0b00000000 Data Byte 12 OxF3D0 R W spare3_byte13 7 0 0b00000000 Data Byte 13 OxF3D1 R W spare3_byte14 7 0 0b00000000 Data Byte 14 OxF3D2 R W spare3_byte15 7 0 0b00000000 Data Byte 15 OxF3D3 R W spare3_byte16 7 0 0b00000000 Data Byte 16 OxF3D4 R W spare3_byte17 7 0 0b00000000 Data Byte 17 OxF3D5 R W spare3_byte18 7 0 0b00000000 Data Byte 18 OxF3D6 R W spare3 byte19 7 0 0600000000 Data Byte 19 OxF3D7 R W spare3_byte20 7 0 0b00000000 Data Byte 20 OxF3D8 R W spare3_byte21 7 0 0b00000000 Data Byte 21 OxF3D9 R W spare3_byte22 7 0 0b00000000 Data Byte 22 OxF3DA R W spare3 byte23 7 0 0600000000 Data Byte 23 OxF3DB R W spare3_byte24 7 0 0b00000000 Data Byte 24 OxF3DC R W spare3_byte25
152. 0 7 0 byte 1 bksv3 byte 2 7 0 OxEE11 7 0 byte 2 bksv3 byte 3 7 0 OxEE12 7 0 byte 3 bksv3 byte 4 7 0 OxEE13 7 0 byte 4 4 bksv4 byte 0 7 0 OxEE14 7 0 byte 0 bksv4 byte 1 7 0 OxEE15 7 0 byte 1 bksv4 byte 2 7 0 OxEE16 7 0 byte 2 bksv4 byte 3 7 0 OxEE17 7 0 byte 3 bksv4 byte 4 7 0 OxEE18 7 0 byte 4 5 bksv5 byte 0 7 0 OxEE19 7 0 byte 0 bksv5 byte 1 7 0 OxEE1A 7 0 byte 1 bksv5 byte 2 7 0 OxEE1B 7 0 byte 2 bksv5 byte 3 7 0 OxEE1C 7 0 byte 3 bksv5 byte 4 7 0 OxEE1D 7 0 byte 4 6 bksv6 byte 0 7 0 OxEE1E 7 0 byte 0 bksv6 byte 1 7 0 OxEE1F 7 0 byte 1 bksv6_byte_2 7 0 OxEE20 7 0 byte 2 bksv6 byte 3 7 0 OxEE21 7 0 byte 3 bksv6 byte 4 7 0 OxEE22 7 0 byte 4 7 bksv7 byte 0 7 0 OxEE23 7 0 byte 0 bksv7 byte 1 7 0 OxEE24 7 0 byte 1 bksv7 byte 2 7 0 OxEE25 7 0 byte 2 Rev 0 Page 243 of 326 06 707 KSV Number Field Name Register Addresses bksv7 byte 3 7 0 OxEE26 7 0 byte 3 bksv7 byte 4 7 0 OxEE27 7 0 byte 4 8 bksv8 byte O 7 0 OxEE28 7 0 byte 0 bksv8 byte 1 7 0 OxEE29 7 0 byte 1 bksv8 byte 2 7 0 OxEE2A 7 0 byte 2 bksv8 byte 3 7 0 OxEE2B 7 0 byte 3 bksv8 byte 4 7 0 OxEE2C 7 0 byte 4 9 bksv9 byte 0 7 0 OxEE2D 7 0 byte 0 bksv9 byte 1 7 0 OxEE2E 7 0 byte 1 bksv9 byte 2 7 0 OxEE2F 7 0 byte 2 bksv9 byte 3 7 0 OxEE30 7 0 byte 3 bksv9 byte 4 7 0 OxEE31 7 0 byte 4 10 bksv10 byte O 7 0 OxEE32 7 0 byte 0 bksv10 byte 1 7 0 OxEE33 7 0 byte 1 10 byte
153. 0 which means that all the input frame will be stretched It is therefore recommended that this register is set by the user before enabling the panorama function Rev 0 Page 130 of 326 06 707 Function m scaler panorama pos 11 0 Description 0x000 default Default 0 Width of not stretched image 3 2 3 13 Output Port This section details the configuration registers for the final block of the PVSP VOM The primary purpose of the output port is to generate the output video timing and output the video data Refer to Table 26 for the register settings for the common CEA video formats that are supported by the ADV8005 The output setting can be automatically configured using the setting of pvsp autocfg output vid 7 0 If the output configuration needs to be set manually pvsp man dp timing enable must be set to 1 and autocfg output vid 7 0 must be set to 0 Refer to Figure 61 for more information When using manual configuration of the output timing format pvsp dp 4kx2k mode en needs to be manually enabled when outputting 4k x 2k series timings and should be disabled for other timing formats If a limited range of output must be provided pvsp data clipping en should be enabled Otherwise this register should be disabled A limited range indicates the output is clipped to 16 235 range for each data channel of pixel pvsp dp 4kx2k mode en Primary VSP Map Address OxE869 4 This bit is used to make
154. 000 0 0000 0 0800 0 0800 0 0000 output input 2 2 12 2 Secondary Input Channel CSC The CSC must be manually configured for each color space conversion The CSC on the secondary input channel can be enabled using the exosd_csc_enable control This CSC can run at pixel clock frequencies up to 162MHz The CSC mode on the secondary input channel can be configured using exosd csc mode 1 0 The CSC mode is used to define the fixed point position of the CSC coefficients which are located after exosd mode 1 0 in the IO Map for the secondary input channel Reference configuration scripts to configure the secondary input channel CSC are provided with the evaluation software exosd csc enable IO Map Address 0x1B50 7 This bit is used to enable the Secondary Input Channel CSC Function exosd csc enable Description 0 default CSC disable 1 CSC enable exosd csc mode 1 0 IO Map Address 0x1B50 6 5 This signal is used to specify the CSC mode for the Secondary Input Channel CSC The CSC mode sets the fixed point position of the CSC coefficients including a4 b4 c4 and offsets Function exosd csc mode 1 0 Description 00 default 1 0 4096 to 4095 01 2 0 8192 to 8190 10 4 0 16384 to 16380 11 4 0 16384 to 16380 The characteristic equations for the secondary input CSC are provided in Equation 7 Equation 8 and Equation 9 Ap2 0 5 212 01
155. 01010 5 240 1999 10351 30 5 240 1999 10351 30 1 001 01011 SMPTE274 1998 1 1080P 60 OR SMPTE274 1998 2 1080P 60 1 001 01100 SMPTE274 1998 3 1080P 50 01101 SMPTE274 1998 4 10801 30 OR SMPTE274 1998 5 10801 30 1 001 01110 5 274 1998 6 10801 25 01111 5 274 1998 7 1080 30 5 274 1998 8 1080 30 1 001 10000 5 274 1998 9 1080 25 10001 5 274 1998 10 1080 24 5 274 1998 11 1080 24 1 001 10011 SMPTE295 1997 10801 25 10100 5 295 1997 1080 50 10110 ITU R 709 5 11521 50 For the SD encoder the input standard can be configured using sd enc ip mode 1 0 If using the SD encoder the SD standard can also be set using the automatic mode which is configured using sd autodetect en If manually setting this SD standard the automatic mode must be disabled When using the encoder in an SD only mode it is required that sd enc inp sel 3 0 and hd enc inp sel 3 0 are set to the same format sd enc ip mode 1 0 Encoder Map Address OxE480 1 0 This signal is used to select the SD standard Function sd enc ip mode 1 0 Description 00 default NTSC 01 PAL B D G H I 10 PALM 11 PAL sd autodetect en Encoder Map Address 0xE487 5 This bit is used to enable the encoder section to auto detect the input standard Function sd autodetect en Description 1 Enabled 0 default Disabled When enabled sd autodetect s
156. 03 arid SXGA 204 WXGA 2 205 UXGA 206 WXGA 3 207 WUXGA 208 If overscan crop or album mode is being used the required blocks must be configured manually by enabling the corresponding enable bits such as pvsp vim crop enable to enable the VIM crop block 3 2 1 2 Customized Input Output Video Format Configuration If the input timing is not in the PVSP input format table customized input format needs to be set manually If the input resolution has a variation with regard to standard timing for example if pvsp autocfg input vid 7 0 is set to 2 which indicates the input resolution is 720x480 but the actual resolution is 718x478 the user can manually set pvsp autocfg input vid 7 0 to 0 and set the input resolution through the following three registers pvsp man input res Primary VSP Map Address OxE884 5 This bit is used to enable the manual configuration of the input resolution Rev 0 Page 108 of 326 06 707 Function pvsp man input res Description 0 default Disable manual configuration of input resolution 1 Enable manual configuration of input resolution pvsp vin h 10 0 Primary VSP Map Address OxES2E 2 0 Address OxE82F 7 0 This signal is used to set the horizontal resolution of the input video This register s value will be used while input res is 1 or pvsp autocfg input vid is 0 Function pvsp vin h 10 0 Description 0x000 default Default OxXXX Horizontal
157. 0x 14 109417 0001110b 0001110b into twos complement 1110010b 0x72 setup 6 0 Encoder Map Address 0xE4A1 6 0 This signal is used to specify the SD brightness value Table 75 Sample Brightness Control Values Setup Level NTSC with Pedestal Setup Level NTSC Without Pedestal Setup Level PAL Brightness Control Value setup 6 0 22 5 IRE Ox1E 15 IRE OxOF 7 5 IRE 0x00 IRE 7 5 IRE 7 5 IRE 0x71 Values in the range of Ox3F to 0x44 may result in an invalid output signal NTSC WITHOUT PEDESTAL 100 IRE 1 icm 7 5 IRE 0 IRE TE UI 7 5 NO SETUP US SETUP NEGATIVE SETUP E VALUE ADDED VALUE ADDED VALUE ADDED 8 Figure 118 Examples of Brightness Control Values 7 4 15 Double Buffering Double buffered registers are updated once per field Double buffering improves overall performance because modifications to register settings are not made during active video but take effect prior to the start of the active video on the next field This can be enabled for both SD and ED HD using db en and db en hdtv respectively 7 4 15 1 ED HD Doubling Buffering db en hdtv Encoder Map Address 0xE433 7 This bit is used to enable the double buffering on the appropriate ED HD registers Function db en hdtv Description 0 default Cb after falling edge of HSYNC 1 Cr after falling edge of HSYNC Double buffering can be activated on the following ED HD functions the ED HD ga
158. 0x62 7 0 Address 0x63 7 0 Address 0x64 7 0 Address 0x65 7 0 Read Only The number of times the timer 7 interrupt was generated timer8 irq cnt 31 0 SPI Device Address 0 0 TIMER Address 0x66 7 0 Address 0x67 7 0 Address 0x68 7 0 Address 0x69 7 0 Read Only The number of times the timer 8 interrupt was generated 4 2 7 OSD Scaler The ADV8005 OSD core contains an arbitrary resolution conversion scaler This scaler performs a scaling function if the OSD resolution inside the DDR2 memory is different from the output video If the output video is interlaced the OSD scaler can change the progressive OSD data to interlaced data for blending As mentioned in Section 4 2 3 the OSD scaler also guarantees the correct synchronization of OSD data and input video data 4 2 8 OSD Master Slave SPI Interface ADV8005 OSD requires an external DDR2 memory and some configuration done to the OSD SPI registers in order to work OSD data can be written to the DDR2 memory on startup by the ADV8005 In addition to dynamically configure the OSD configuration registers need to be controlled Note that all this configuration is taken care of by Blimp OSD and the firmware so a detailed explanation of the DDR2 SPI interface is not provided For this reason this section covers only top level information enable disable muxing configuration of the OSD through the IO Map registers The SPI slave hardware interface is also described in this
159. 1 c 3 Cb1 2 z 2 7 7 gt 1 2 z2 cs 3 Cb1 2 7 7 7 z Z z 7 gt lt 473 2 c2 3 1 1e 2 7 2 2 2 3 In Cri o p P3 2 2 2 gt z2 z o 21 1 9 2 2 2 2212 4 xxm we 5 95 ce z ox 2 Cri 8 2 2 2 1 32 z o c oa 2 2 2 212 2 4 9 9 Gs z z 2 7 27 z 7 2 212 z z ienj es z 2 2 2 2 2 eet ce 2 7 Rev 0 Page 318 of 326 Z 2 Z Cb11 Cr11 Y 11 Cb10 Cr10 Y 10 Cb9 Cr 9 Y9 Cb8 Cr 8 Y8 Cb7 Cr 7 Y7 Cb6 Cr 6 Y6 Cb5 Cr 5 Y5 Cb4 Cr 4 4 Cb3 Cr 3 Y3 Cb2 Cr 2 Y2 Cb1 Cr 1 Y1 Cb0 Cr 0 Y0 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb7 Cb6 Cb5 Cr5 Y9 Y8 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb9 Cr9 Cb8 Cr8 Cb7 Cr7 Y11 Y10 Y9 Y8 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb1 1 Cr 11 Cb1 0 Cr 10 Cb9 Cr9 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb7 Cb6 Cb5 Y9 Y8 Y7 Y6 Y5 YA Y2 Y1 YO Cb9 Cb8 Cb7 Cr2 Cr1 Y11 Y10 Y9 Y8 Y7 Y6 Y5 YA Y3 Y2 Y1 YO Cb1 1 Cb1 0 Cb9 Rev 0 Page 319 of 326
160. 1 YCbCr 4 2 2 8b Rev 0 Page 148 of 326 06 707 3 3 3 SVSP Video Output Module Video Output Module VOM VOM Cropper Pixel Unpacker Write to DDR2 Figure 66 SVSP Video Output Module VOM Figure 66 shows the structure of the VOM in the SVSP This is a much simpler structure than that of the VOM in the PVSP The SVSP VOM offers the following functions e unpacker reads field frame from external memory and unpacks memory word to video pixel information e VOM cropper reads cropped images from external memory e Output port generates output timing and output video Register update protection is provided in the ADV8005 Refer to Section 3 4 for more details regarding the update of the various VSP registers svsp lock vom Secondary VSP Map Address OxE610 4 This bit is used to lock the Video Output Module If the Secondary VSP is running and this bit is set to 1 the VOM will be locked to the current register setting to display the last frame The Secondary VSP registers can be configured safely in this state All new register settings will be updated after this bit is set back to 0 Function svsp lock vom Description 0 default Unlock VOM 1 Lock VOM Note This register should be used only as part of the gentle reboot protocol Refer to Section 3 4 3 for more details svsp update vom Secondary VSP Map Address OxE610 3 Registers related to the VOM can be updated only when this
161. 1 uF capacitor should be connected from the pin to AVDD2 7 6 2 Video Output Buffer and Optional Output Filter video buffer is necessary on the DAC outputs to match the 3000 output impedance of the ADV8005 encoder output to the 750 input impedance of the sink device ADI produces a range of op amps suitable for this application for example the AD8061 For more information about line driver buffering circuits refer to the relevant op amp datasheet An optional reconstruction anti imaging low pass filter LPF may be required on the ADV8005 encoder processor DAC outputs if the part is connected to a device that requires this filtering The filter specifications vary with the application The use of 16x SD 8x ED or 4x HD oversampling can remove the requirement for a reconstruction filter altogether Refer to Section 7 4 1 for more details on output oversampling For applications requiring an output buffer and reconstruction filter the ADA4430 1 ADA4411 3 and ADA4410 6 integrated video filter buffers should be considered Table 82 Output Filter Requirements Application Oversampling Cutoff Frequency MHz Attenuation 50 dB at MHz SD 20 5 SD 209 5 ED 14 5 ED 203 5 HD 1x gt 30 44 25 Rev 0 285 of 326 06 707 06398 085 Figure 134 Example of Output Filter for SD 16x Oversampling 06398 086 Figure 135 Example of Output Filter for ED 8x Oversampling
162. 13 2 category code 2 11 Category code OxEC13 3 category code 3 12 Category code 0 1 3 4 category_code 4 13 Category code OxEC13 5 category code 5 14 Category code OxEC13 6 category code 6 15 Category code OxEC13 7 category code 7 16 Source number OxEC14 4 source number 0 17 Source number 0 14 5 source number 1 18 Source number OxEC14 6 source number 2 19 Source number OxEC14 7 source number 3 20 Channel number See Figure 106 See Figure 106 21 Channel number See Figure 106 See Figure 106 22 Channel number See Figure 106 See Figure 106 23 Channel number See Figure 106 See Figure 106 24 Sampling frequency 0 1 5 4 i2s sf O 25 Sampling frequency OxEC15 5 i2s sf 1 26 Sampling frequency OxEC15 6 i2s_sf 2 27 Sampling frequency OxEC15 7 i2s sf 3 28 Clock accuracy OxEC12 0 clk_acc 0 29 Clock accuracy OxEC12 1 acc 1 30 Not defined 0 0 31 Not defined 0 0 32 Word length OxEC14 0 word length 0 33 Word length OxEC14 1 word length 1 34 Word length OxEC14 2 word length 2 35 Word length OxEC14 3 word length 3 36 Original sampling frequency 0 0 37 Original sampling frequency 0 0 38 Original sampling frequency 0 0 39 Original sampling frequency 0 0 40 CGMS A 0 0 41 CGMS A 0 0 42 191 Not defined 0 0 Rev 0 Page 234 of 326 06 707 Figure 106 shows how the channel number bits 20 to 23 are set based on the layout bit and bit sample present spX which indicates if subpacket X contains a
163. 198 5102 Gamut Metadata Packets ERO ERO ERE RE ERE ERO cues eee RENI ES 200 5 11 Customizing Packet InfoFrame Storage Registers esee 201 5 12 SHDMES ction Reset Strategy e IO REIP UON 202 6 HDMI Irans mittens 203 6 1 Gerieral Controls b e E E 203 6 2 E E DETE ite E A EEEN SOE E E AO E 205 6 3 HDMI DY Selection 205 6 4 6 5 Source Product Description InfoFrame eese tentent tenter ttt tentent 206 6 6 Spare Packets and VSI S ppOtrt RR Ea A Re eles Eee eds 207 6 7 ysrangulei rro 210 671 GerneralStatus 210 6 8 EDID HDCP Controller Status pre e e ter prenne 211 6 9 EDID HDCP Gontroller Error Codes rtr eret ctrca oett oreet onde 211 6 10 Video Setup 6101 lero iwi G 212 6102 Video Mode Detection pete TRE E EY ERN ERE YEAR EE 212 6 10 3 Pixel Repetitioncs Ue Rm E A C 213 6 10 4 Video Related Packets and InfoFrames eese tenente a EA A entente tente n tentent 214 6 10 5 AVI InfoFrame
164. 1A02 3 This bit is used to enable the TTL video output Function ttl vid out en Description 0 default Disable TTL output 1 Enable TTL output ttl sel 2 0 IO Map Address 0x1A02 2 0 This signal is used to select the video source for the TTL video output Rev 0 Page 46 of 326 06 707 Function ttl out sel 2 0 Description 0x00 default From Primary Input Channel 0x01 From Primary VSP 0x02 From Ptol Converter 0x03 From Internal OSD Blend 1 0x04 From Secondary VSP Ptol Converter 0x05 From Secondary Input Channel 0x06 From RX Input 0x07 From Internal OSD Blend 2 osd str 1 0 IO Map Address 0x1BA7 1 0 This signal is used to control the drive strength for the video output clock signal Function osd clk drv str 1 0 00 default 01 10 11 Description Minimum Medium low x2 Medium high x3 Maximum x4 osd dout drv str 1 0 IO Map Address 0x1BA3 1 0 This signal is used to control the drive strength for the video output data and sync signals Function 054 dout str 1 0 Description 00 default Minimum 01 Medium low x2 10 Medium high x3 11 Maximum x4 2 2 2 4 Treatment o f Unused TTL Inputs ADV8005 allows the TTL pins to be powered down when unused removing the need for external pulldowns on many unused I O pins Note The TTL pins are powered down by default each of these pins must be powered up to use them Unused pins s
165. 2 This bit is used to enable disable closed caption data extraction on the even field Function even en Description 0 default Disable closed caption data extraction on even field 1 Enable closed caption data extraction on even field cgms anc en IO Map Address 0x1A4C 1 This bit is used to enable disable CGMS data extraction on the even field Function cgms anc en Description 0 default Disable CGMS data extraction on even field 1 Enable CGMS data extraction on even field wss anc en IO Map Address 0x1A4C 0 This bit is used to enable disable WSS data extraction on the even field Function WSS anc en Description 0 default Disable WSS data extraction on even field 1 Enable WSS data extraction on even field anc delay 1 0 IO Map Address 0x1A4D 1 0 This bit is used to set the delay on ancillary data in vsyncs The interlaced input delay will be in fields and the progressive delay will be in frames Decoded data is firstly transferred onto input vsync and then output vsync this will be the base delay with a setting of 0 Every increment above this adds one input vsync delay did a 7 0 IO Map Address 0x1A4A 7 0 This register is used to specify the value of the DID sent in the ancillary stream with VBI decoded data sdid a 7 0 IO Map Address 0x1A4B 7 0 This register is used to specify the value of the SDID sent in the ancillary stream with VBI decoded data 2 2 9 Resets Th
166. 2 2 2 2 2 2 2 2 2 4 2 2 2 Z R5 R7 R9 2 2 7 2 2 2 2 5 7 7 Z B3 Z Z Z Z Z Z R4 R6 R8 2 2 2 2 2 2 2 Z Z Z 2 Z B2 Z Z 2 2 p 2 5 R7 2 2 2 2 2 2 E Z Z 2 2 2 B1 7 7 7 7 2 R2 R4 R6 2 2 2 2 2 2 2 Z Z 7 2 2 BO 2 2 2 2 2 2 R1 R3 R5 2 2 2 2 2 2 i Z Z 2 R9 2 2 Z Z Z 2 2 Z RO R2 R4 Z Z Z Z Z 2 Z Z Z R8 2 Z Z Z Z Z 2 2 R1 R3 2 2 Z 2 2 Z P Z Z rA R7 2 2 2 Z 2 RO R2 2 2 Z 2 2 2 2 2 2 R6 2 2 2 2 2 2 2 2 2 R1 2 2 2 2 2 2 Z b 2 2 2 R5 E Z Z Z Z 2 2 2 2 2 RO 2 2 2 2 2 2 2 2 2 2 R4 2 2 Z Z Z 2 2 zZ G7 G9 G11 2 2 2 7 2 R7 2 Z 2 R6 Z 2 2 2 2 2 2 G6 G8 G10 2 2 2 2 2 R6 7 2 R2 R5 2 2 2 2 2 2 G5 G7 G9 74 2 2 2 2 R5 E 2 Z Z R1 R4 7 2 2 2 2 2 Z G4 G6 G8 Z 2 2 2 2 R4 2 Z Z RO R3 2 2 2 2 2 2 G3 G5 G7 2 2 2 2 2 ps 2 2 2 G9 R2 2 E 2 2 2 2 G2 G4 G6 2 2 2 2 7 2 R2 E 2 2 G8 R1 Z 2 2 2 2 2 G1 G3 G5 2 2 2 2 2 2 R1 P 2 2 2 G7 RO 2 2 2 2 2 Z GO G2 G4 Z Z Z 2 2 Z RO E Z Z Z G6 2 2 Rev 0 Page 315 of 326 06 707 1 5 15 1 4 14 1 3 P 13 1 2 P 12 1 1 1 0 7 B6 G1 GO B9 B8 G3 2 2 G2 2 G1 2 7 GO 2 2 11 2 2 10 2 2 Rev 0 Page 316 of 326 G7 G6 G5 G4 G3 G2 G5 G4 G3 G2 G1 GO
167. 2 3 6 CUE Correction Color Upsampling Error CUE correction is implemented using a filter which removes the jagged edges caused by the artifacts introduced by the incorrect upsampling of MPEG 2 video data in 4 2 0 format to the 4 2 2 4 4 4 formats supported by DVD players The CUE correction function can be enabled or disabled by di cue enable di cue enable Primary VSP Map Address 0xE84D 0 This bit is used to enable CUE correction Function di cue enable Description 0 Disable CUE correction 1 default Enable CUE correction 3 2 3 7 Random Noise Reduction There are several noise reduction algorithms in the ADV8005 that help with the reduction of common sources of video noise The random noise reduction RNR block reduces the random noise which may be introduced in analog broadcasting or capturing It employs a temporal recursive algorithm to stabilize the static regions while just processing the luma channel Users can configure the register parameters to adjust the algorithm according to their preference The amount level of RNR can be configured using di rnr level 1 0 RNR supports both interlaced and progressive input It can be enabled or disabled using di rnr enable di rnr enable Primary VSP Map Address 0xE84C 4 This bit is used to enable random noise reduction RNR Function di rnr enable Description 0 default Disable RNR 1 Enable RNR di rnr level 1 0 Primary VSP Map Address OxE84F 1 0
168. 2 Y6 IN 5 Cb1 Cr1 Cb3 Cr3 Cb5 Cr5 Cb5 Yi Y5 OSD IN 4 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb4 YO 4 OSD IN 3 7 Cb1 Cr1 Cb3 Cr3 Cb3 Cb9 OSD IN 2 7 Cb0 CrO Cb2 Cr2 Cb2 Cb8 Y2 Rev 0 Page 324 of 326 06 707 5 515 535548 NNNNNNNNNNNN N gt gt 8S 000000000 0 5 8 8 39925B8mNNNNNIN N NN ON ON ON ON ON ON ON ON N e I BS AN NONON NN NON ON ON ON ON ON 55 oNNNNNNNNNNNSN NNNNNNNNNNN NNNNNNNNNNNNN NN ON N N NN INE N NWN N OSD_IN 1 OSD_IN O VID_CLK Rev 0 Page 325 of 326 06 707 NOTES refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors HDMI the HDMI logo and High Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions
169. 220 of 326 06 707 Input Output audio input audio mode I2s format Audio ClockPins Encoding ADV8005 Format Packet Type _sel Value Value Value Input Input Pin Signal Mapping 0b001 0b00 ObXX SPDIF Biphase AUD IN O IEC60958 or Audio Mark MCLK 61937 Sample Packet 0b010 Ob1X ObXX DSD 5 0 SCLK Normal AUD IN 5 0 DSD DSD Packet SCLK 0b010 0b1X ObXX DSD 5 0 SCLK SDIF 3 AUD IN 5 0 DSD DSD Packet SCLK 0b011 0500 ObXX 12513 0 MCLK Biphase AUD IN 4 0 61937 Packet Mark MCLK 0b011 0601 0600 12S 3 0 SCLK Normal AUD_IN 4 0 Standard HBR Packet SCLK 125 MCLK 0b011 0b01 0b01 I2S 3 0 SCLK MCLK Normal AUD IN 4 0 Right HBR Packet SCLK justified MCLK 0b011 0b01 0b10 12513 0 SCLK Normal AUD IN 4 0 Left justified HBR Packet SCLK MCLK 0b011 0b01 0b11 12513 0 SCLK Normal AUD IN 4 0 AES3 Direct HBR Packet MCLK SCLK MCLK 0b011 0b10 ObXX SPDIF MCLK Biphase AUD IN O 61937 Packet Mark MCLK 0b011 0611 0600 SPDIF SCLK Normal AUD 0 Standard HBR Packet MCLK SCLK 125 MCLK 0b011 0b11 0b01 I2S 3 0 SCLK Normal AUD IN 4 0 Right HBR Packet SCLK Justified MCLK 0b011 0b11 0b10 12513 0 SCLK Normal AUD IN 4 0 Left HBR Packet SCLK Justified MCLK 0b011 0b11 0b11 I2S 3 0 MCLK Normal AUD IN 4 0 61937 Packet MCLK 1 Optional signal 6 11 3 1 I2S Audio ADV8005 can re
170. 2215 995 Ground R TX1 HDMI Tx11 Float this pin PVDD5 Power HDMI Tx PLL Power Supply 1 8 V This pin is a voltage regulator output Connect HEAC 1 4 HDMI Tx1 Connect this pin to ground through a 4 7 resistor HEAC 1 HDMI Tx1 Connect this pin to ground through a 4 7 resistor P 24 Digital video Float this pin as it is disabled by default input P 25 Digital video Float this pin as it is disabled by default input GN GN GN GN GN GN GN a decoupling capacitor between this pin and ground P 26 Digital video Float this pin as it is disabled by default input P 27 Digital video Float this pin as it is disabled by default input D D D D D D D D D D D D D D NC Do Not Float this pin e ea 2 22122 eno 7 6 QD 6 e ea e OJO 22 2 HDMI Tx PLL Power Supply 1 8 V This pin is a voltage regulator output Connect a decoupling capacitor between this pin PVDD5 Power and ground AVDD3 Power HDMI Analog Power Supply 1 8 V No connect Connect this pin to ground P 20 Digital video Float this pin as it is disabled by default input P 21 Digital video Float this pin as it is disabled by default P 22 Digital video Float this pin as it is disabled by default P 23 Digital video Float this pin as it is disabled by default DVDD Power Digital Power Supply 1 8 V GND G
171. 2k 4kx2k 50 Hz 576i 0 3 1 3 0 3 1 3 0 3 1 4 0 3 1 4 1080i 576p 0 3 1 3 0 3 1 3 0 3 1 4 0 3 1 4 720 1080 59 94 60 Hz 480i 0 3 1 3 0 3 1 3 0 3 1 4 0 3 1 4 1080i 480p 0 3 1 3 0 3 1 3 0 3 1 4 0 3 1 4 720p 1080p 23 97 24 25 30 720 1080 03 08 0 3 0 8 0 3 1 3 0 3 1 3 Hz The following functions are not supported In low latency mode Rev 0 Page 113 of 326 06 707 e Motion adaptive de interlacing autodisabled e Cadence detection autodisabled e Random noise reduction autodisabled e correction autodisabled pvsp_frc_low_latency_mode Primary VSP Map Address 0xE84D 2 This bit is used to enable low latency mode Function pvsp_frc_low_latency_mode Description 0 default Disable low latency mode 1 Enable low latency mode 3 2 1 8 Freezing Output Video It is possible to freeze the output video from the PVSP by disabling the VIM This can be achieved by setting pvsp_enable_vim to 0 3 2 1 9 Progressive Cadence Detection The ADV8005 PVSP supports multiple different types of cadence detection Progressive cadence detection is another feature supported by ADV8005 when the input video is 60 Hz and the output video is 24 Hz An example of progressive cadence detection would involve the ADV8005 detecting a pull down ratio of 3 2 for 60 Hz video and reconverting this to its original film content at 24 Hz This would allow the video to be output at 24 Hz and therefore be displ
172. 3 en TX2 Test Map Address 2 This bit is used to enable the Spare Packet 3 Function spare pkt3 en Description 0 default Disabled 1 Enabled spare pkt4 en TX2 Test Map Address 1 This bit is used to enable the Spare Packet 4 Function spare pkt4 en Description 0 default Disabled 1 Enabled Rev 0 Page 207 of 326 06 707 Table 46 Spare Packet 1 Configuration Register Packet Map Access Type Register Name Default Value Byte Name Address OxF2CO R W 5 1 hbO 7 0 0500000000 Header Byte 0 OxF2C1 R W spare1_hb1 7 0 0b00000000 Header Byte 1 OxF202 R W spare1_hb2 7 0 0b00000000 Header Byte 2 OxF2C3 R W spare1 pb0 7 0 0600000000 Data Byte 0 0 2 4 R W spare1 pb1 7 0 0600000000 Data Byte 1 OxF2C5 R W spare1 pb2 7 0 0600000000 Data Byte 2 OxF2C6 R W spare1 pb3 7 0 0600000000 Data Byte 3 OxF2C7 R W spare1 pb4 7 0 0600000000 Data Byte 4 OxF2C8 R W spare1 pb5 7 0 0600000000 Data Byte 5 OxF2C9 R W spare1 pb6 7 0 0600000000 Data Byte 6 OxF2CA R W spare1 pb7 7 0 0600000000 Data Byte 7 OxF2CB R W spare1_pb8 7 0 0b00000000 Data Byte 8 OxF2CC R W spare1_pb9 7 0 0b00000000 Data Byte 9 OxF2CD R W spare1 pb10 7 0 0600000000 Data Byte 10 OxF2CE R W 5 1 pb11 7 0 0600000000 Data Byte 11 OxF2CF R W spare1 pb12 7 0 0600000000
173. 4 0x08 3 12 bit buses SDR 4 4 4 0x09 1x8 bit DDR bus 4 2 2 0x0A 1 10 bit DDR bus 4 2 2 OxOB 1x 12 bit DDR bus 4 2 2 OxOC default 3x8 bit buses 4 4 4 exosd swap bus ctrl 2 0 IO Map Address 0x1B68 7 5 This signal is used to control the external OSD input pixel bus The input pixel bus is 24 bits wide and is divided into three data channels Top D 23 16 Middle D 15 8 and Bottom D 7 0 This register allows the user to swap the order of these three data channels Function exosd swap bus ctrl 2 0 Description 000 default D 23 16 D 15 8 D 7 0 001 D 23 16 D 7 0 D 15 8 010 D 23 16 D 15 8 D 7 0 011 D 15 8 D 23 16 D 7 0 100 D 7 0 D 23 16 D 15 8 101 D 7 0 D 15 8 D 23 16 110 D 15 8 D 7 0 D 23 16 111 D 23 16 D 15 8 D 7 0 The input formatter also has a number of controls which can be used to provide extra flexibility in terms of data processing Once a DDR mode is selected using exosd format sel 4 0 the order of the luma and chroma data can be configured using exosd ddr yc swap In DDR modes the luma is expected on the rising edge of the pixel clock Setting this bit to 1 swaps the luma and chroma samples and places the chroma sample C on the rising edge and the luma sample Y on the falling edge Refer to Figure 30 for more information The edge on which each sample of DDR data is latched into the part can be specified using ddr edge sel ddr yc swap 0
174. 5 2 2 4 1 PVSP Output Timing The following registers are programmed for the PVSP Rev 0 Page 65 of 326 06 707 pvsp vid clk period 33 0 IO Map Address 0x1A3A 1 0 Address Ox1A3B 7 0 Address 0x1A3C 7 0 Address 0x1A3D 7 0 Address Ox 1A3E 7 0 This register is used to set the open loop period of the DPLL section This should be programmed based on the value calculated from the given equations pvsp vid clk update IO Map Address 0x1A3A 4 This bit is used to trigger the open loop period to be captured in the DPLL A low to high transition triggers the action Function pvsp vid clk update Description 0 default Do not update open loop period 1 Update open loop period in DPLL For example the following procedure updates the PVSP DPLL clock period 1A 1A39 0A Put the DPLL into ADV8005 scaler mode 1A 1A3B XX Configure DPLL clock period setting 1A 1A3C XX Configure DPLL clock period setting 1A 1A3D XX Configure DPLL clock period setting 1A 1A3E XX Configure DPLL clock period setting 1A 1A3A 80 Recommended setting 1A 1A3A 90 Recommended setting Once configured the clock in Figure 37 is programmed for operation 2 2 4 2 SVSP Output Timing The following registers are programmed for the SVSP svsp vid clk period 33 0 IO Map Address Ox1A3F 1 0 Address 0x1A40 7 0 Address 0x1A41 7 0 Address 0x1A42 7 0 Address 0x1A43 7 0 This signal is used to set the open loo
175. 6 Recommended Write 1A 1 13 Recommended Write 1 1 01 Recommended Write Rev 0 Page 72 of 326 06 707 1A 1AA2 25 Recommended Write 1A 1AA3 ID Recommended Write 1A 1AA4 81 Recommended Write 1A 1AA5 81 Recommended Write 1AA7 53 Recommended Write 1A 1 8 B4 Recommended Write 1A 1AB2 02 Recommended Write 1A 1AFE 08 Recommended Write The result of the DDR2 loopback test is given by the lbk test done and test result bits test done IO Map Address 0x1AE1 0 Read Only This bit is used to readback the DDR2 loopback test has completed Function test done Description 0 default Test not complete 1 Loopback test finished test result IO Map Address 0x1AE1 1 Read Only This bit is used to readback the DDR2 loopback test error result Function test result Description 0 default No error detected 1 Errors detected The following are possible failures that could cause the DDR2 loopback test to fail e Address or control or clock open or short all bit lines failing e Single DQ open or short to ground or supply single bit line failing on both positive and negative edges e Short between DQ lines two bit lines failing routing in adjacent resistors of resistor pack DQS or DM open or short eight DQ lines failing e Timing transfer problem one or more bit lines failing 2 2 6 Auto Increment read_auto_inc_en is used
176. 6 720x240p60 80r9or 120r 13 1280x720p60 4 CEA 1920x1080p 16 720x576p50 17 or 18 or 29 or 30 or 37 or 38 1280x720p50 19 720x288p50 23 or 24 or 27 or 28 1920x1080p50 31 1920x1080p24 32 Rev 0 Page 138 of 326 Video Timing VID 1920x1080p25 33 1920x1080p30 34 720 100 41 576 100 42 or 43 720p120 47 480p120 48 or 49 576p200 52 or 53 480p240 56 or 57 VGA 200 SVGA 201 XGA 202 WXGA 203 VESA timing SXGA 204 WXGA 2 205 UXGA 206 WXGA 3 207 WUXGA 208 Note The SVSP does not support the following formats 7 1280x720p 23 97 24 Hz CEA VIC 60 8 1280x720p 25 Hz CEA VIC 61 9 1280x720p 29 97 30 Hz CEA VIC 62 svsp_autocfg_output_vid 7 0 Secondary VSP Map Address 0xE661 7 0 This register is used to set the output timing VIC If this register is 0 SVSP will use values in registers of svsp_dp_decount svsp_dp_hfrontporch svsp_dp_hsynctime svsp_dp_hbackporch svsp_dp_activeline svsp_dp_vfrontporch svsp_dp_vsynctime svsp_dp_vbackporch svsp_dp_hpolarity svsp_dp_vpolarity and svsp_vout_fr to set output video Function UG 707 svsp autocfg output vid 7 0 Description 0x00 default OxXX Custom output video Output timing VIC Table 29 lists all the supported video timings and their VID The 59 94 23 97 Hz timings have the same VID as the corresponding 60 24 Hz timing in the table Table 29 SVSP Supported Output V
177. 6 707 Function mpeg pkt en Description 0 default Disabled 1 Enabled Table 54 MPEG InfoFrame Configuration Registers Packet Map Access Type Field Name Default Value Byte Address 0 220 R W mpeg hb0 7 0 0500000000 Header Byte 0 OxF221 R W mpeg_hb1 7 0 0b00000000 Header Byte 1 OxF222 R W mpeg_hb2 7 0 0b00000000 Header Byte 2 OxF223 R W mpeg_pb0 7 0 0b00000000 Data Byte 0 OxF224 R W mpeg_pb1 7 0 0b00000000 Data Byte 1 OxF225 R W mpeg_pb2 7 0 0500000000 Data Byte 2 0 226 R W mpeg pb3 7 0 0b00000000 Data Byte 3 OxF227 R W mpeg pb4 7 0 0500000000 Data Byte 4 0 228 R W mpeg pb5 7 0 0500000000 Data Byte 5 0 229 R W mpeg_pb6 7 0 0b00000000 Data Byte 6 OxF22A R W mpeg pb7 7 0 0500000000 Data Byte 7 OxF22B R W mpeg pb8 7 0 0600000000 Data Byte 8 OxF22C R W mpeg pb9 7 0 0600000000 Data Byte 9 OxF22D R W mpeg pb10 7 0 0500000000 Data Byte 10 OxF22E R W mpeg pb11 7 0 0600000000 Data Byte 11 OxF22F R W mpeg pb12 7 0 0500000000 Data Byte 12 0 230 R W mpeg pb13 7 0 0600000000 Data Byte 13 OxF231 R W mpeg_pb14 7 0 0600000000 Data Byte 14 OxF232 R W mpeg_pb15 7 0 0600000000 Data Byte 15 OxF233 R W mpeg_pb16 7 0 0600000000 Data Byte 16 OxF234 R W mpeg_pb17 7 0 0600000000 Data Byte 17 0 235 R W mpeg pb18 7 0 0600000000 Data Byte 18 0 236 R W mpeg pb19 7 0 0600000000
178. 615 7 6 5 4 76 S 4 2 0 4 4 L lt Dummy byte gt Data gt Delay Mode MISO1 7 6 5 41 3 2 1 0 H Data out 0 Data out 1 lt No Delay Mode I lt MISO1 7181514131211191716151413121119 4 4 L Figure 89 SPI Slave Interface Timing and Data Format The CPOL CPHA can be configured through the registers described below spi slave cpol IO Map Address 0x1A14 3 This bit is used to select the SPI slave clock polarity Function spi slave cpol Description 0 Idle state clock is low 1 default Idle state clock is high spi slave cpha IO Map Address 0x1A14 2 This bit is used to select the SPI slave clock phase Function spi slave cpha Description 0 Negedge used 1 default Posedge used As can be seen from Figure 89 the LSB bit of the device address sets whether the access is read or write The SPI subaddress is an 8 bit field and the data is also 8 bits wide with MSB sent first and LSB last The SPI slave readback has both delay mode and no delay mode and it is controlled by the following SPI register slave delay mode SPI Device Address 0x0A Address 0x85 0 SPI slave read data MISO1 output delay mode Function slave delay mode Description 0 No delay 1 Delay 8 clocks 8 bits dummy data In no delay mode counting from the last rising edge of SCK1 send su
179. 7 0 0600000000 Data Byte 18 OxF216 R W spd_pb19 7 0 0b00000000 Data Byte 19 OxF217 R W spd_pb20 7 0 0b00000000 Data Byte 20 OxF218 R W spd_pb21 7 0 0b00000000 Data Byte 21 OxF219 R W spd_pb22 7 0 0b00000000 Data Byte 22 OxF21A R W spd pb23 7 0 0600000000 Data Byte 23 OxF21B R W spd pb24 7 0 0600000000 Data Byte 24 OxF21C R W spd pb25 7 0 0600000000 Data Byte 25 OxF21D R W spd_pb26 7 0 0b00000000 Data Byte 26 OxF21E R W spd pb27 7 0 0600000000 Data Byte 27 UG 707 6 6 SPARE PACKETS AND VSI SUPPORT The user may configure the ADV8005 to send any type of packets or InfoFrames via the spare packets controls and associated configuration registers ADV8005 features four such spare packets that can be enabled via the 0 spare pktl en spare pkt3 en and spare pkt4 en controls bits When a spare packet is enabled the Tx transmits one of these enabled spare packets once every two video fields These spare packets allow the ADV8005 to support the transmission of three Vendor Specific InfoFrames VSI as follows VSI Video VSI AUDIO and VSI HDMI spare pktO en TX2 Main Map Address OxF440 0 This bit is used to enable the Spare Packet 1 Function spare pktO en Description 0 default Disabled 1 Enabled spare pktl en TX2 Main Map Address OxF440 1 This bit is used to enable the Spare Packet 2 Function spare pkt1 en Description 0 default Disabled 1 Enabled spare pkt
180. 7 cre C4 cre Cb2 che 7 2 2 2 2 z c 6 4 616 chs z Cbi Cb3 Cb5 7 CH crs 5 7 Z 2 2 2 2 5 91 01810155 cbs cha z Cb2 2 2 cro C2 Cbo 7 2 7 7 7 z 0 4 SFO 912 614 z 7 z cn 2 7 7 271272 2712 83 72 3 7 cho rom 2 2 2 co c2 7 z nz z z 2 12 2 72 2 2 Cre Cr 1 2 2 2 21 212 212 z zicoi t zz 11 cbo 7 Cb0 Cra Cr 0 2 2 z1 z o0 2 o z gt 7 91 00 z z VID VID D VID VID VID VID VID VID VID VID VID VID VID VID VID VID DE E DE DE DE DE DE DE DE DE DE DE DE DE DE DE DE DE DE DE z VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID HS S HS Hs HS HS 8 Hs HS HS HS HS HS HS HS HS 7 VID VID V VID VID VID VID VID VID VID VID VID VID VID VID VID VID vs S vs vs VS 8 vs vs vs vs vs VS 8 8 vs VS z VID VID VID VID VID VID VID VID VID
181. 8005 Capabilities with Different Memory Sizes U6 707 1Gbx2 512 Mbx2 1Gbx1 512 Mbx1 0 0 wa pm p ww d E py Umemupememm E S ww dL E Supported Supported Not Supported E oe MEE MEE b 2 111111 2 Single DDR2 Memory Configuration If using a single DDR2 memory the number of field buffers must be reduced from seven default to four when performing de interlacing and scaling on 720p 10801 and 1080p inputs This is achieved by enabling intra field interpolation and setting pvsp ex mem data format 1 0 to indicate 16 bit 4 2 2 Next pvsp frc low latency mode must be enabled Finally the field buffers addresses in DDR2 must be reassigned as follows OxE800 31 0 pvsp fieldbuffer0 addr 31 0 5184000 OxE804 31 0 pvsp fieldbufferl addr 31 0 9331200 OxE808 31 0 pvsp fieldbuffer2 addr 31 0 13478400 OxE80C 31 0 fieldbuffer3 addr 31 0 17625600 OxE810 31 0 pvsp fieldbuffer4 addr 31 0 21772800 OxE814 31 0 pvsp fieldbuffer5 addr 31 0 25920000 OxE889 31 0 pvsp fieldbuffer6 addr 31 0 27578880 Rev 0 Page 71 of 326 06 707 2 2 5 4 DDR2 Loopback Test The ADV8005 features a DDR2 loopback test block to allow testing of the ADV8005 DDR2 interface When the loopback test block is enabled it controls the comman
182. 8028 31250 25 2 6272 28000 12544 28000 25088 28000 27 6272 30000 12544 30000 25088 30000 27 1 001 6272 30030 12544 30030 25088 30030 54 6272 60000 12544 60000 25088 60000 54 1 001 6272 60060 12544 60060 25088 60060 74 25 1 001 17836 234375 35672 234375 71344 234375 74 25 6272 82500 12544 82500 25088 82500 148 5 1 001 8918 234375 17836 234375 35672 234375 148 5 6272 16500 12544 16500 25088 16500 Other 6272 Measured 12544 Measured 25088 Measured Table 62 Recommended N and Expected CTS Values for 48 kHz and Multiples 48 kHz 96 kHz 192 kHz Pixel Clock MHz N CTS N CTS N CTS 25 2 1 001 6864 28125 13728 28125 27456 28125 25 2 6144 25200 12288 25200 24576 25200 27 6144 27000 12288 27000 24576 27000 27 1 001 6144 27027 12288 27027 24576 27027 54 6144 54000 12288 54000 24576 54000 Rev 0 Page 231 of 326 06 707 54 1 001 6144 54054 12288 54054 24576 54054 74 25 1 001 11648 140625 35672 140625 46592 140625 74 25 6144 74250 12288 74250 24576 74250 148 5 1 001 5824 140625 17836 140625 23296 140625 148 5 6144 148500 12288 148500 24576 148500 Other 6144 Measured 12288 Measured 24576 Measured 6 11 5 Audio Sample Packets By setting audioif cc 2 0 to a value greater then 2 that is 3 channel or more the eight channel audio packet format will be used The I2S can be routed to different subpackets using the following fields e subpktO src e subpktO src
183. 88 720x576p 720 1440 E A Olo ojo A E 21 R O 91 N A a m p 6 o o En o w o o o oo oo R N N on 2 of 92 e TM A 288 220 4 24 0 8 0 288 576 48 252 0 4 32 0 E hv A o Gio m M 720 1440 x576i 720x480p Prog 239 76 239 240 874 76 720x480p Prog 239 76 125 239 m 14 240 874 76 E 240 37 76 2 0 240 37 76 2 0 The following standards are NOT supported Int Pr og 80p 120 0 0 0 80p 0 0 0 TS N 22 A 276 5 N A 3 5 5 3D Side by Side Full The following 3D standards need to go through the a being converted to a 2D mode Int Pr og 80p 120 0 0 0 80p 5 0 0 0 3 6 EXTERNAL SYNC MODE Using the ADV8005 external sync mode it is possible to resynchronise multiple ADV8005 output video streams to an external sync input The outputs from multiple ADV8005 devices will be locked to 3 Xtal clock cycles where the Xtal clock will be 27 MHz When the ADV8005 is in external sync mode the output video timing will be locked to an externally provided master sync signal MAS
184. 9 scale Equation 18 HDMI Tx CSC Channel C Output The CSC in each of the HDMI Txs is illustrated in Figure 44 csc scaling factor 5 a4 4 Out A Figure 47 HDMI Tx CSC The video inputs A In B and In C are connected by default to and B Refer to Table 17 for more information The default routing cannot be changed for the HDMI Tx CSCs Table 17 Default HDMI Tx Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In A R Cr In B G Y In B Cb The 1 to to B3 and to C3 coefficients are used to scale the primary inputs A4 B4 and C4 are added as offsets Floating point coefficients must be converted into 120 bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range 1 1 or 4096 4095 The dynamic range of the CSC is 0 1 for unipolar signals B or 0 5 0 5 for bipolar signals Bipolar signals Pr Pb must be offset to mid range Equations with a dynamic range larger than 1 need to be scaled appropriately using the scaling factor 1 0 control To achieve a coefficient value of 1 0 for any given coefficient csc scaling factor 1 0 should be set high and the coefficient should be programmed to a value of 0 5 Otherwise the largest value would be 4095 4096 0 9997 While this value could be interpreted as 1
185. ANALOG DEVICES ADV8005 Hardware Reference nae One Technology Way 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com ADV8005 Functionality and Features Advantiv NatureVue Advanced Television Solutions Video Upconversion and Enhancement by Analog Devices by Analog Devices PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS Rev 0 Page 1 of 326 06 707 TABLE OF CONTENTS Understanding the ADV8005 Hardware Manual cscsssssssssssssscsscssssssscsssssssssssssssesesssssssssssssesessessesessesseseuseseeseasesees 9 Description of the Hardware eet tene DD t GR RH ER TR RP taceat inte ee ET 9 Disclaimer A E E E de ii ine Ue dere tie A 9 Trademark and Service Mark Notice Number Notations eret proe po opi IR IR de d NITORE I eT Uri door piedi t ae ine tede err gie nad Register Access CONVENHONS idee eir eng eh e tid e e EE ut e hi pri a 9 Acronyms and Abbreviations ete ede ete etu s Rd Re re 9 Field Function Description eO ta ed eei e EROR e ee 12 occu bats 13 1 Introduction to the ADVS8005 en aeterni 14 1 1 Overview Li Digital Video Inp tz ine E ette e D ERR DR e Perret 15 1 1 2 Flexible Digital Core tte rta RR S ERR ENSURE IEE
186. BDO 5 This bit is used to control the input path enable for the DE pin Function de ie Description 0 default input path disable 1 input path enable ie IO Map Address Ox1BDO 4 This bit is used to control the input path enable for the SFL pin Function sfl ie Description 0 default input path disable 1 input path enable hs osd ie IO Map Address Ox1BDO 2 This bit is used to control the input path enable for the osd HS pin Function hs osd ie Description 0 default input path disable 1 input path enable de osd ie IO Map Address 0 1 This bit is used to control the input path enable for the osd DE pin Function de osd ie Description 0 default input path disable 1 input path enable audio pins ie 6 0 IO Map Address 0x1BD1 6 0 This bit is used to control the input path enable for the audio pins Function audio pins ie 6 0 Description 0 default input path disable 1 input path enable arcl pin ie IO Map Address 0x1BD2 7 This bit is used to control the input path enable for the ARC 1 pin Rev 0 Page 48 of 326 06 707 Function arc1 pin ie Description 0 default input path disable 1 input path enable arc2 pin ie IO Map Address 0x1BD2 6 This bit is used to control the input path enable for the ARC 2 pin Function arc2 pin ie Description 0 default input path disable 1 input path
187. Byte 15 OxF2A3 R W gmp pb16 7 0 0600000000 Data Byte 16 OxF2A4 R W gmp_pb17 7 0 0600000000 Data Byte 17 OxF2A5 R W gmp pb18 7 0 0600000000 Data Byte 18 OxF2A6 R W gmp pb19 7 0 0600000000 Data Byte 19 Rev 0 Page 217 of 326 06 707 Packet Field Name Default Value Byte Name1 Address OxF2A7 R W gmp pb20 7 0 0b00000000 Data Byte 20 OxF2A8 R W gmp pb21 7 0 0b00000000 Data Byte 21 OxF2A9 R W gmp pb22 7 0 0b00000000 Data Byte 22 OxF2AA R W gmp pb23 7 0 0b00000000 Data Byte 23 OxF2AB R W gmp pb24 7 0 0b00000000 Data Byte 24 OxF2AC R W gmp pb25 7 0 0b00000000 Data Byte 25 OxF2AD R W gmp pb26 7 0 0b00000000 Data Byte 26 OxF2AE R W gmp pb27 7 0 0b00000000 Data Byte 27 1 As defined in the latest HDMI specification 6 11 AUDIO SETUP 6 11 1 Audio Architecture The ADV8005 is capable of receiving audio data 125 SPDIF DSD or High Bit Rate HBR formats When the input audio is captured from the audio input pins it is then converted into audio packets for transmission over the HDMI output interface The ADV8005 HDMI and TX2 process audio input streams independently the following bits select which audio format is expected the audio pins aud input mode 1 0 IO Map Address 0x1A08 7 6 This signal is used to select the audio input mode
188. C coefficient A3 ttl out a4 12 0 IO Map Address Ox1BB6 4 0 Address 0x1BB7 7 0 This signal is used to specify the ttl out channel CSC coefficient A4 ttl b1 12 0 IO Map Address 0x1BB8 4 0 Address Ox1BB9 7 0 This signal is used to specify the ttl out channel CSC coefficient ttl out b2 12 0 IO Map Address 0x1BBA 4 0 Address OxIBBB 7 0 This signal is used to specify the ttl out channel CSC coefficient B2 ttl out b3 12 0 IO Map Address Ox1BBC 4 0 Address 0x1BBD 7 0 This signal is used to specify the ttl out channel CSC coefficient B3 ttl out b4 12 0 IO Map Address Ox1BBE 4 0 Address Ox1BBF 7 0 This signal is used to specify the ttl out channel CSC coefficient B4 ttl out c1 12 0 IO Map Address 0x1BC0 4 0 Address 0x1BC1 7 0 This signal is used to specify the ttl out channel CSC coefficient ttl c2 12 0 IO Map Address 0x1BC2 4 0 Address 0x1BC3 7 0 This signal is used to specify the ttl out channel CSC coefficient C2 ttl c3 12 0 IO Map Address 0x1BC4 4 0 Address 0x1BC5 7 0 This signal is used to specify the ttl out channel CSC coefficient C3 ttl c4 12 0 IO Map Address 0x1BC6 4 0 Address 0x1BC7 7 0 This signal is used to specify the ttl out channel CSC coefficient C4 The characteristic equations for the secondary input CSC are provided in Equation 10 Equation 11 and Equation 12 2 0 5 A202 0 4312 0 4096 4096 Y 4096 Equati
189. C must be manually configured for each color space conversion The CSC on the RX input channel can be enabled using the rx enable control This CSC can run at 297MHz and provides color space conversion for UHD video formats The CSC mode on the RX input channel can be configured using rx mode 1 0 The CSC mode is used to define the fixed point position of the CSC coefficients which are located after rx mode 1 0 in the IO Map for the RX input channel Reference configuration scripts to configure the RX input channel CSC are provided with the evaluation software rx csc enable IO Map Address 0x1B70 7 This bit is used to enable the RX input channel CSC Function rx csc enable Description 0 default CSC disable 1 CSC enable rx mode 1 0 IO Map Address 0x1B70 6 5 This signal is used to specify the CSC mode for the RX input channel CSC The CSC mode sets the fixed point position of the CSC coefficients including a4 b4 c4 and offsets Function rx csc mode 1 0 Description 00 default 1 0 4096 to 4095 01 2 0 8192 to 8190 10 4 0 16384 to 16380 11 4 0 16384 to 16380 The characteristic equations for the secondary input CSC are provided in Equation 10 Equation 11 and Equation 12 A Im 4412 0 aec 4096 E 4096 5 4096 Equation 10 RX Input CSC Channel A Output 842 2
190. CR FF RW synchronization control bit can be used for nonstandard input video This is in fast forward or rewind modes In fast forward mode the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines fields is reached In rewind mode this sync signal usually occurs after the total number of lines fields is reached Conventionally this means that the output video has corrupted field signals because one signal is generated by the incoming video and another is generated when the internal line field counters reach the end of a field When the VCR FF RW sync control is enabled dvd r 1 the line field counters are updated according to the incoming VSync signal and when the analog output matches the incoming VSync signal This control is available in all slave timing modes except slave mode 0 dvd r Encoder Map Address OxE482 5 This bit is used to enable the SD VCR FF RW sync feature Function dvd r Description 1 Enabled 0 default Disabled 7 4 4 Vertical Blanking Interval The ADV8005 encoder core is able to accept input data that contains VBI data such as CGMS WSS VITS in SD ED and HD modes If VBI is disabled VBI data is not present at the output and the entire VBI is blanked These control bits are valid in all master and slave timing modes In order to enable this feature vbi data en is set to 1 For the SMPTE 293M 525p standard VBI data can be insert
191. CU and the timer which generated it can be found out by polling the timer registers These timers can be configured through the Timer register map This map is only accessible through the SPI slave interface address OxOB For more information on the SPI slave interface refer to Section 4 2 8 2 The registers used to configure the timers are described below sys clock freq 23 0 SPI Device Address 0x0B TIMER Address 0x00 7 0 Address 0x01 7 0 Address 0x02 7 0 System clock frequency unit is KHz the default value is 157 5 MHz Function sys clock freq 23 0 Description 0x02673C Default OxXXXXXX System Clock Frequency This register is used to generate a 1 KHz pulse which all eight timers are based on to measure a 1 ms interval If the system clock frequency is changed this register can be changed to guarantee the 1 KHz accuracy It is also possible to modify this register if a smaller time interval than 1115 needs to be measured For example The default value of sys clock freq is 0x0278D0 that is 162000 162 MHz If it is changed to 16200 the minimum interval will be 0 1 ms If it is changed to 1620 the minimum interval will be 0 01ms timerl enable SPI Device Address 0x0B TIMER Address 0x03 0 Timer 1 Enable Function timer1 enable Description 0 Disables 1 Enables Once the timer is enabled disabling this bit will stop the counting and it will be resumed when enabling back this bit Note
192. D IN 7 OSD IN 6 OSD IN 5 OSD IN 4 OSD IN 3 OSD IN 2 OSD OSD 0 P 35 P 34 P 33 P 32 P 31 P 30 29 28 27 26 25 24 23 22 21 20 19 18 Rev 0 Page 321 of 326 06 707 7 5 4 2 1 0 1 0 2 1 0 2 1 0 A7 A6 A5 4 7 5 4 2 1 0 P 17 P 16 P 15 P 14 P 13 P 12 P 11 A3 A2 A1 0 10 P 9 P 8 p P 6 P 5 PA P 3 2 1 P 0 VID DE VID HS VID VS VID CLK Rev 0 Page 322 of 326 06 707 Table 90 RGB TTL Output Formats E i 24 BIT SDR 4 4 4 30 BIT SDR 4 4 4 36 BIT SDR 4 4 4 OSD_DE DE OUT DE OUT DE OUT OSD VS VS OUT VS OUT VS OUT OSD HS HS OUT HS OUT HS OUT OSD CLK CLK OUT CLK OUT CLK OUT OSD_IN 23 R6 R8 R10 OSD IN 21 R5 R7 R9 OSD IN 20 R4 R6 R8 OSD IN 19 R3 R5 R7 OSD IN 18 R2 R4 R6 OSD 17 R1 R3 R5 OSD IN 16 RO R2 R4 OSD IN 15 G7 R1 R3 OSD IN 14 G6 RO R2 OSD IN 13 G5 G9 R1 OSD IN 12 G4 G8 RO OSD IN 11 G3 G7 G11 OSD IN 10 G2 06 G10 OSD IN 9 G1 G5 G9 OSD IN 8 Go G4 G8 OSD
193. D encoder not used 1A 1A05 00 Input to ADV8005 to both Primary and Secondary VSP 1A 1A06 02 Progressive to Interlaced converter not used output from Primary VSP to OSD blend Rev 0 Page 43 of 326 06 707 These four register writes configure the hardware blocks in the ADV8005 in mode 3 More registers will need to be configured depending on the input and desired video standards 2 2 2 Digital Video Input The ADV8005 has three means of receiving video the video TTL input and the EXOSD TTL input which constitute the flexible 60 bit TTL input port and the Serial Video Rx Each of the TTL inputs can be connected to one of the input channels the primary input channel or the secondary input channel The Serial Video Rx is always connected to the RX input channel Each channel features a dedicated input formatter color space converter CSC and dither block The primary input channel also features an automatic contrast enhancement ACE control The ADV8005 input channels are illustrated in Figure 26 Figure 27 and Figure 28 Primary Input Channel Video TTL Input Data AV Code 5 uium EXOSD TTL Input Video TTL Input EXOSD TTL Input OSD IN 11 0 P 35 0 Contrast csc Brightness ACE Saturation 48 bit to 24 bit onversion Primary Input Channel Output Figure 26 Video TTL Input Channel Secondary Input Channel Data AV Code Secondary Input Rotate Detect Channel Video Out
194. E Ie GRE de 16 12522 Video Signal PrOCEsSOE ise n pe ER qe t nter ee ettet etit pte us 16 LA Bitmap On Screen Display 17 11 5 External DDR Mernotyi osea eere He Rr NIU IUe R RI I RENNES I Ee 18 1 1 62 HDMITIransmitter ERE SERERE TANTA 18 Lp NXideoEncodetz ees 18 LES OP ode eere 18 1 2 Main Features of the 8005 1 tante aai eee d edet e be ena etie 19 1 2 1 Video Signal Processor EZI Primary VSP ceps 1 2 1 2 Horizontal Pre Scaler 12113 Secondary 19 1 2 2 O1 B A NORRA AN 19 L2 3 Video Encoder ene A RA AR EN ON I D REI NE D EYE 20 12 4 TEranSL 1 2 5 Additional Features 1 3 Protocol for Main Port 1 4 GConfiguring the AD V8005 Heb He Ran ea E LIH SERRE E FAEERE AR 23 2 ADV8005 Top Level 24 2 1 ADV8005 Modes of Operation idt te 25 2 1 Selecting t tete ens 26 2 1 2 unu 26 2 1 3 Mode2 unen IM ELS LN D LUC 28 2 1 4 HU 29 2 1 5 MO GA
195. EGI systems block size control DNR can be applied to the resulting block transition areas that are known to contain noise Generally the block transition area contains two pixels It is possible to define this area to contain four pixels border area It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset The digital noise reduction registers are three 8 bit registers They are used to control the DNR processing To enable the SD DNR feature dnr en must be programmed dnr en Encoder Map Address OxE481 7 This bit is used to enable the SD Digital Noise Reduction DNR function Function dnr en Description 1 Enabled 0 default Disabled 7 4 19 1 Coring Gain Border dnr coring gain a 3 0 is the gain factor applied to border areas refer to Figure 133 for more information on border areas In DNR mode the range of gain values is 0 to 1 in decrements of 1 8 This factor is applied to the DNR filter output that lies below the set threshold range Rev 0 Page 279 of 326 06 707 The result is then subtracted from the original signal In DNR sharpness mode the range of gain values is 0 to 0 5 in increments of 1 16 This factor is applied to the DNR filter output that lies above the threshold range The result is added to the original signal dnr coring gain a 3 0 Encoder Map Address 0xE4A3 7 4 This signal is used to configure
196. Equation 22 would yield the following field size Field size 1280 x 720 x2 1843200 where no bytes per pixel indicates the number of bytes required to store each pixel Refer to Table 23 for more details of the number of bytes required to store each pixel of data svsp fieldbuffer0 addr 31 0 Secondary VSP Map Address 0xE600 7 0 Address 0xE601 7 0 Address 0xE602 7 0 Address 0xE603 7 0 This signal is used to set the start address of frame buffer 0 Software should arrange memory space properly avoiding conflict between different buffers Function svsp fieldbuffero addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 0 svsp_fieldbuffer1_addr 31 0 Secondary VSP Map Address 0xE604 7 0 Address 0xE605 7 0 Address 0xE606 7 0 Address 7 7 01 This signal is used to set the start address of frame buffer 1 Software should arrange memory space properly avoiding conflict between different buffers Rev 0 Page 141 of 326 06 707 Function svsp fieldbuffer1 addr 31 0 Description 0x00000000 Default OxXXXXXXXX Start address of frame buffer 1 svsp fieldbuffer2 addr 31 0 Secondary VSP Map Address 0xE608 7 0 Address 0xE609 7 0 Address 7 0 Address OxEGOB 7 0 This signal is used to set the start address of frame buffer 2 Software should arrange memory space properly avoiding conflict between different buffers Function svsp
197. FO ST Timing All raw bits have corresponding status bits The status bits always work in the same manner whether the raw bit is edge or level sensitive Status bits have the following characteristics e Enabled by setting the corresponding interrupt mask bit e Always latched and must be cleared by the corresponding clear bit For a given interrupt when the interrupt mask bit is set the interrupt status bit goes high and an interrupt is generated on the INT2 pin if the interrupt raw bit changes state To return the interrupt status bit to low the interrupt clear bit must be set The status bits interrupt mask bit and clear bits for level sensitive int and edge sensitive int are described here for completeness level sensitive int st IO Address Read Only This readback indicates the latched status of the level sensitive int raw signal This bit is only valid if enabled via the corresponding INTI interrupt mask bit Once set this bit remains high until the interrupt is cleared level sensitive int clr Function level sensitive int st Description 0 level sensitive int raw did not change state 1 level sensitive int raw changed state edge sensitive int st IO Address Read Only This readback indicates the latched status for edge sensitive int raw This bit is only valid if enabled via the corresponding INT1 interrupt mask bit Once set this bit remains high until the interrupt is cleared via edge sensitive int
198. ID Sharpness Filt r Mode Hein eR Hertha tee ete tee oie E 7 4 18 2 ED TID Adaptive Filters TERM H 7 4 18 3 ED HD Adaptive Filte Modes 7 4 18 4 ED HD Sharpness Filter and Adaptive Filter Application Examples seen 276 TANS SD Digital Noise Reduction RUN 278 Rev 0 Page 7 of 326 U6 707 06 707 7 4 19 1 s cM MEE 7 4 19 2 Coring 2 7 4 19 3 7 4 19 4 nid c mM 7 4 19 5 512 UOEETTM 7 4 19 6 DNR Input Select Control 7 4 19 7 DNR 7 4 19 8 7 4 19 9 SD Active Video Edge Control c cscescssssssesssessssesssesssesseessssssssessesssessssesseesssessssesscsseessssssseesssessseessesseessesessesssessesesseesseesseessnseese 283 7 5 Vertical Blanking Interval 5 pete rt et oma dd a e id d tee egeo ete 284 7 6 DAG Contigurations 285 76 15 Voltage Reference 285 7 6 2 Video Output Buffer and Optional Output 285 8 Interrupts 8 1 Interrupt M
199. IN 7 B7 G3 G7 IN 6 B6 G2 G6 OSD IN 5 B5 G1 G5 OSD INA B4 Go G4 OSD_IN 3 B3 B9 G3 OSD IN 2 B2 B8 G2 OSD_IN 1 B1 B7 G1 OSD IN O BO B6 Go P 35 2 B5 B11 P 34 2 B4 B10 P 33 2 B3 B9 2 B2 B8 2 B1 B7 2 BO B6 z 2 B5 2 2 B4 2 2 B3 2 2 B2 2 2 B1 2 2 BO 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 Rev 0 Page 323 of 326 06 707 17 N NNNNNNNNNNNNNNNNN N NNNNNNNNNNNNNNNNN NNNNNNNNNNNNNNNN N SN Table 91 YCrCb TTL Output Formats AL 24 BIT SDR 4 2 2 30 BIT SDR 4 44 36 BIT SDR 4 4 4 DE OUT DE OUT DE OUT DE OUT DE OUT DE OUT VS OUT VS OUT VS OUT VS OUT VS OUT VS OUT HS OUT HS OUT HS OUT HS OUT HS OUT HS OUT CLK OUT OUT CLK OUT CLK OUT CLK OUT Y9 11 Cr crit OSD IN 22 Y10 Cr8 Cro OSD IN 21 7 Y Cro OSD IN 20 Y6 Y8 cra Cr6 Cr8 OSD IN 19 Y5 Y7 Cra OSD IN 18 4 Y6 cre Cr Cr6 OSD IN 17 Y5 Cra OSD IN 16 Y2 4 Cro cre 050 IN 15 Yi 7 Cri Cia OSD IN 14 YO Y2 Y6 Cro cre OSD IN 13 2 Yi Y5 Y Cri OSD IN 12 2 YO y4 Y8 Cro OSD_IN 11 Cb7 Cr7 Cb9 Cro Cb11 Cr11 7 Yt OSD IN 10 Cb6 Cr6 Cb8 Cr8 Cb10 Cr10 Y2 Y6 Y10 OSD IN 9 Cb5 Cr5 Cb7 Cr7 Cb9 Cr9 Yi Y5 OSD IN 8 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8 YO y4 Y8 1 7 Cb3 Cr3 Cb5 Cr5 Cb7 Cr7 Cb7 Y3 Y7 OSD IN 6 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Cb6 Y
200. Interface iei eee IHNEN 42 8 3 SPI Master 4 2 9 OSDInitialization eee iatis tig ete i e Des Serial Video Receiver I M 5 1 PEV 5 2 TMDS Clock Activity D tection 5 3 Clock and Data Termination Control 54 EXACT 5 5 Deep Color Mode Support 5 6 Video PIERO ain tet Red e Mal dpa Ae AE e ee SL avi RR 5 7 Pixel Repetition a e d so das ta ede eade ee eae 5 8 Sync Signal Polarity Readbacks 5 9 InfoFrame Registers e s ede o o ie 5 9 1 InfoFrame Collection Mode 592 InfoFrame Checksum Error 5 93 AVI Into Frame Registers e e i e tees Rev 0 Page 5 of 326 U6 707 06 707 5 94 SPD InfoErame ener eene eer Ren RON 5 9 5 MPEG Source InfoFrame Registers 5 9 6 Vendor Specific InfoFrame Registers sssssssssssssesessesssessessesssessesssssessesssssssssesssessessesssessessssssessesssessesssssessessesseesess 197 5 10 Packet curi 198 50 15
201. L input and output buses HS VS DE and the TTL clock are output on the following pins e OSD IN 23 0 P 3524 e OSD HS e VS e DE e OSD_CLK The video data can be output at pixel frequencies to 162 MHz Only single data rate video is supported on the TTL output bus it is not possible to clock video out on the rising and falling edge of the TTL output clock Rev 0 Page 45 of 326 output format ttl out sel Primary Input Channel Secondary Input Channel RX Input Channel Primary v SP BIT Secondary VSP SELECTION 2 ZEROING OSD Blend 1 OSD Blend 2 POSSIBLE DATA SOURCES 162MHz MAX TTL Clock OUTPUT REGISTER Figure 29 TTL Output Block Diagram The following registers are used to control the TTL outputs ttl_ps444_in IO Map Address 0x1A01 0 This bit is used to select the video type sent to the TTL output format block Function 35 0 HS VSDE ttl ps444 in Description 0 default Input to TTL output block is real 4 4 4 1 Input to TTL output block is pseudo 4 4 4 ttl format 3 0 IO Map Address 0x1A02 7 4 This signal is used to specify the TTL output format Function ttl op format 3 0 Description 0011 2x8 bit buses SDR 4 2 2 0100 2x 10 bit buses SDR 4 2 2 0101 2x 12 bit buses SDR 4 2 2 0110 3x8 bit buses SDR 4 4 4 0111 default 3x 10 bit buses SDR 4 4 4 1000 3x 12 bit buses SDR 4 4 4 ttl vid out en IO Map Address 0x
202. MIS du MM 51 2 2 2 6 Primary Input eU HERR 51 2 2 2 7 Secondary Input Channel 56 2 2 2 8 60 2 2 3 Updither Configuration retener ente etui 60 DOAN fClock GontiguratiObus osse p ERI EH EDGE E GERE RERERRNEU ERUIT cats a DITE 61 2 242 PVSP Output 1 M 2 24 2 5 5 Output Timing n 2 274 3 Frane Tracking 2 2 5 2 INEA EUN 68 2225 x DDR ComPig uration ss 68 2 2 5 2 DDR2 Bandwidth and Memory Selection c cccsssesssssesssessseessesssessssesssesseessssesssessesssseesssessesesseessuessssesssesseeesseesseesseessseessessseesseeey 69 225 3 Single DDR2 Memory 71 2 2 5 4 DDR LOOpDACk Lest 72 22 6 EC zAuto Incremento 73 2 27 SPELoop Lhicugh eund dentutmene eem a eet d ete ea 73 2 2 8 Data Insertion cccecsesssssssssseeseeseeseeseencssesseseseessesecnessesucsuesessecseeseenecucsucsucsecseesseseeucsucsucsucseeseenecscencsucsueseeseeneeneeneenees 74 2 28 1 Extraction Overview 74 2 2822 Ancillary Data EXtraCtion OO 74 228 3
203. Module VSDP Vendor Specific Data Block VSP Video Signal Processor Processing VSync VS Vertical Synchronization XTAL Crystal Oscillator Rev 0 Page 11 of 326 U6 707 06 707 FIELD FUNCTION DESCRIPTION The function of a field is described in a table preceded by the bit name a short function description the IPC map the register location within the PC map and a detailed description of the field Refer to Error Reference source not found for more details The detailed description consists of e Fora readable field the values the field can take Fora writable field the values the field can be set to I2C location of the field in big endian format MSB first LSB last Read Write Access for field The name of the field In this example the field is called deep_color_mode and is 2 bits long deep c lor mode 1 0 HDMI RX Map Address OxE20B 7 6 Read Only Detailed description A readback of the deep color mode information extracted from the general control packet of the field Function deep color mode 1 0 Description 00 8 bits per channel 01 10 bits per channel 10 12 bits per channel 11 16 bits per channel not supported Values the field can be set to or take These values are in binary Default value format if not preceded by Ox and in indicated by hexadecimal format if preceded by Figure 1 Field Description Format Rev
204. ND Ground 5 5 5 o o o c c c e e Pin Type N A N A N A N A N A N A N A Digital output N A Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO N A N A N A N A N A N A N A N A N A N A N A Digital output N A N A Digital input Digital input Digital input Digital input Digital input N A N A Rev 0 Page 307 of 326 06 707 Location P9 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 22 23 1 R2 R3 R4 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 Mnemonic Type Description if Unused P 16 Digital video Float this pin as it is disabled by default input P 17 Digital video Float this pin as it is disabled by default input P 18 Digital video Float this pin as it is disabled by default input P 19 Digital video Float this pin as it is disabled by default input P 14 Digital video Float this pin as it is disabled by default input Digital video Float this pin as it is disabled by default input GND GND Ground Pin Type N A N A N A N A N A N A N A N A N A Digital output N A Digital output Digital output Digital input Digital input Digital input Digital input N A N A N A N A N A N A N A N A N A N A N A
205. NFIGURATION Once the input to the encoder section has been configured the user can configure the output of the encoder DACs Depending on the input mode specified by the func mode 2 0 register the DAC outputs can be configured accordingly using dacl sel 2 0 to sel 2 0 It is important to note that if the func mode 2 0 signal is set to simultaneous mode then DACs 1 3 can only output the ED HD signals of YPbPr or RGB and 4 6 can only output the SD signals of CVBS or black burst luma or chroma It is possible to multiplex any of the ED HD signals out on any of the DACs 1 to 3 in simultaneous mode Similarly it is possible to multiplex any of the SD signals out on any of the DACs 4 to 6 It should also be noted that to enable the DAC outputs from the NON ROVI ADV8005 part ADV8005KBCZ 8N 00h must be written to Encoder map register 0 4 0 dacl sel 2 0 Encoder Map Address 0 429 6 4 This signal selects the data that is supplied to DAC 1 Function dac1_sel 2 0 Description 0 default CVBS or Black Burst 1 Luma 2 Chroma 3 Y G 4 Pb B 5 Pr R dac2_sel 2 0 Encoder Map Address 0xE429 2 0 This signal selects the data that is supplied to DAC 2 Rev 0 Page 253 of 326 06 707 Function dac2 sel 2 0 Description 0 CVBS or Black Burst 1 default Luma 2 Chroma 3 Y G 4 Pb B 5 Pr R dac3 sel 2 0 Encoder Map Address OxE42A 6 4 This signal selects the data that
206. OP HEIGHT SVSP CROP WIDTH Figure 64 VIM Crop Dimensions svsp vim crop h start 12 0 Secondary VSP Map Address OxE61A 7 0 Address 1 7 3 Sets the horizontal start position of the VIM cropper Function svsp vim crop h start 12 0 Description 0x000 default Default OxXXX Horizontal start position of VIM cropper input svsp_vim_crop_v_start 12 0 Secondary VSP Map Address 0xE61C 7 0 Address 0xE61D 7 3 This signal is used to set the horizontal start position of the VIM cropper Function svsp_vim_crop_v_start 12 0 Description 0x000 default Default OxXXX Vertical start position of VIM cropper input svsp_vim_crop_width 12 0 Secondary VSP Map Address 0xE61E 7 0 Address 0xE61F 7 3 This signal is used to set the input width of the VIM cropper Function svsp_vim_crop_width 12 0 Description 0x000 default Default OxXXX Width of VIM cropper input svsp vim crop height 12 0 Secondary VSP Map Address 0xE620 7 0 Address 0xE621 7 3 This signal is used to set the input height of the VIM cropper Function svsp vim crop height 12 0 Description 0x000 default Default OxXXX Height of VIM cropper input Note The following limitations apply to the values that can be programmed in these registers e Register values programmed must be even numbers e 0 lt vim crop h start 12
207. OS 2 DDRinterface Connectthis pin to ground through a 4 7 resistor mp Ground 00 00 DDR DQ 23 DDR interface Connect this pin to ground through a 4 7 resistor DVDD DDR DDR Powr DDR DDR Interface Supply 1 8V DDR Interface Supply 1 8V 1 8 V DDR DDR Connect this pin to ground through a 4 7 resistor mop eo 00000000 uo se 0 DDR DQ 9 DDR Interface Connect this pin to ground through a 4 7 resistor DVDD DDR DDR Interface Supply 1 8 V DDR DO 14 DDRinterface Connectthis pin to ground through a 4 7 resistor UNSER SNNT DDR 6 DDRinterface Connectthis pin to ground through a 4 7 resistor PVDD DDR DDR Interface PLL Supply 1 8 V oo a DDR DO 18 DDR interface Connect this pin to ground through a 4 7 resistor wp 80 200000 DDR DOS 2 DDR interface Connect itis pin to ground through a 4 7 resistor DDR DO 26 DDR interface Connect this pin to ground through a 4 7 resistor DVDD DDR DDR Interface Supply 1 8 V DDR DOSI3 DDR interface Connect this pin to ground through a 4 7 resistor NC GND For New ADV8005 Designs Float this pin For Designs That Must Maintain Pin Type Digital output N A N A Digital output Digital input Digital input Bi directional digital IO N A Bi directional
208. OSD 5 _INA 0 4 NE 5 4 OSD Z 2 2 2 Rev 0 Page 317 of 326 OSD 4 Cb7 Cb9 1 Cr vaz vaz vas 7 1 2 2 z 9 11 2112121211111111211 21 2 z OSD 4 Cb8 0 Cr 6 vas vis F 6 0 2 2 z 106 08 10 zz 2 2 2 7 7 7 z Ye 4 OSD Cb5 Cb7 Cb9 5 2 2 2 ee er Los 2 x 7 7 7 7 7 2 u7 u3 z yo Ys 4 SD Cb4 Cb6 Cb8 4 2 2 2 cre ce 7 7 7 2 7 7 Zo Yor 4 OSD Cb3 Cb5 Cb7 3 2 2 2 o5 7 7 7 7 7 7 7 2 c7 Y Wm ce Cb2 Cb4 Cb6 2 2 2 2 ce 2 2 7 7 2 2 2 2 2 coe Wee 813854 ces Y2 4 OSD Cbi Cb3 Cb5 1 2 2 7 cs ce z 7 7 7 2 2 2 2 YSE o 4 OSD Cb2 Cb4 0 z 2 2 co cre cra 212 7 7 Z 4 Z 2 Z coe M PRU 2 b vo 3 SD Cb1 Cb3 cn 11 13 9 JN3 2 2 2 z on 7 cb2 3 OSD Cb2 ue 4 8 JN2 z 2 2 21600 6 2 2111 11121112 11 2 7 7 612 21 z cbt 3 OSD Cb1 Cb1 11 7 2 2 2 z Cbo Cbo e 6 2 2 2 oo 2122 12 212 212 2 6 4 212 2 z 3 Cr1 Cb1 5 7 7 7 oce 1 z z zi iz z iz zi sl w97 099 4 z z 3 Cr1 Cb1 Cb 6 Cb 1 4 34 z 7 2 211121 21 2 2 21 2 12 212 3310121
209. Outputs RTA and Load Value Selection Encoder Component Placement tee en nene ies eie en ette qn e unen denies tete ets HDMI Transmitter Component Placements nagsisisi tiennie i Peta ee ede ve aee RR ee ede eee ana 298 Power Supply Design and Sequencing ten 298 Appendix B Unused Pin List E Pixel Input and Output Formats re cda t ee ve Ped avi ee E RV tee RN ye ee A uH RR An EAR Eee 313 Revision History 6 14 Revision 0 Initial Version Rev 0 Page 8 of 326 06 707 UNDERSTANDING THE ADV8005 HARDWARE MANUAL DESCRIPTION OF THE HARDWARE MANUAL This manual provides a detailed description of the functionality and features supported by the ADV8005 DISCLAIMER The information contained in this document is proprietary of Analog Devices Inc ADI This document must not be made available to anybody other than the intended recipient without the written permission of ADI The content of this document is believed to be correct If any errors are found within this document or if clarification is needed contact the authors at ATV_VSP_Apps analog com TRADEMARK AND SERVICE MARK NOTICE The Analog Devices logo is a registered trademark of Analog Devices Inc All other brand and product names are trademarks or service marks of their respective owners NUMBER NOTATIONS Notation Description bit N Bits are numbered in little endian format that is the least
210. Page 185 of 326 06 707 Function spi master cpol Description 0 default Idle state clock is low 1 Idle state clock is high spi master cpha IO Map Address 0x1A14 0 This bit is used to select the SPI master clock phase Function Spi master cpha Description 0 default Negedge used 1 Posedge used 4 2 9 OSD Initialization To configure 8005 to use the OSD the following writes are required 0x1A14 0x0C SPI mode select 0 1 0 00 SPI bus enable 0 1 0 10 Configure OSD HW int Further SPI writes are required but these are controlled through the OSD Rev 0 Page 186 of 326 06 707 9 SERIAL VIDEO RECEIVER The Serial Video Rx on the ADV8005 can receive video data at rates of up to 3 GHz This allows support for video formats ranging from SD to 4k x 2k 24Hz 1080p120Hz and 1080p60 3D The Serial Video Rx on the ADV8005 can receive video data at rates of up to 2 25 GHz This allows support for video formats ranging from SD to 1080p 60Hz 12 bit It is designed for chip to chip connection only and as such does not offer any DDC lines to facilitate HDCP or EDID operations Deep Colour To ADV8005 RX C Conversion Digital Core 0 Packet RX 1 Packet InfoFrame 2 Processor Memory Figure 91 Functional Block Diagram of ADV8005 Serial Video Rx This section outlines the various registers available to the user in the register map w
211. REQUENCIES GREATER THAN 165MHz NO IS TX OUTPUTS TMDS CLK FREQUENCY GREATER THAN 165MHz TX OUTPUT PORT SOURCE TERMINATION OFF TX OUTPUT PORT SOURCE TERMINATION ON Figure 109 ADV8005 Tx Source Termination Requirements 6 18 HDMI ACR PACKET TRANSMISSION UG 707 A mode has been added to the HDMI Tx to ensure more efficient transmission of audio samples in 176 4 kHz and 192 kHz modes This ensures ACR packets can get sent more frequently on the ADV8005 for these modes than is the case for the equivalent modes on the ADV8003 arc eff tran en TX2 Main Map Address OxF447 0 When enable it ensures more efficient transmission of ARC packets and audio samples in 176 4kHz and 192kHz modes This ensures ACR packets can get sent at the right rate 1ms Function arc eff tran en Description 0 1 default ARC packet efficient transmision disable ARC packet efficient transmition enable Rev 0 Page 249 of 326 06 707 1 VIDEO ENCODER INTRODUCTION TO THE ADV8005 7 1 INTRODUCTION The ADV8005 encoder core consists of six high speed Noise Shaped Video NSV 12 bit video DACs which provide support for composite CVBS S Video Y C and component YPrPb RGB analog outputs in standard definition SD enhanced definition ED or high definition HD video formats Simultaneous SD and ED HD input and output modes are supported The ADV8005 encoder processor provides t
212. ROGRAMMABLE HDTV FILTERS SHARPNESS AND 050 1 23 16 EXT DIN 7 0 DETAIL CUE ENHANCE CORRECTION MENT 12 BIT DACI COLOR SPACE CONVERSION PROCESSOR o OSD IN 11 0 ADAPTIVE FILTER E 12 BIT 050 1 15 13 CONTROL 2 pace 219 DAC VBI x SPI SLAVE TO VBI au INSERTION PROGRAMMABLE 12 8 IN ENCODER LUMINANCE SYNC XTALN CLOCK BLOCK ak FILTERS INSERTION 21 2 XTALP GENERATION gu 4 _ SINICOS 5 INTO 6 1 1 0 OSD ENCODER CHROMINANCE MODULA gt x 12 81 4 pacs INTI TOP LEVEL VSP HDMI Tx FILTERS DAC5 INT2 5 CONTROL REGISTER MAPS 12 BIT MASTER 4 1 PACE ERAT TIMING ARC PORT a GENERATION SPI 2 REFERENCE BLOCK VBI DATA SERVICE SUBCARRIER AND POWER MASTER SLAVE INSERTION FREQ LOCK x AND CABLE MANAGEMENT DETECTION lt O O 0Q 0Q 0Q0 0 0 0 OO m s 2292222 55 nmmm 5554 582008 8 2 3 85 8 8 2 55595555 mmm 58 PPDPP 2227 00586 gt P Q 2 858 8 06000 221221
213. SCs support formats such as RGB YUV and YCbCr The front end CSCs on the primary input channel secondary input channel and RX input channel run at a maximum clock rate of 162 MHz The back end CSCs in HDMI Tx1 and HDMI Tx2 operate at a maximum input clock rate of 300 MHz 2 2 12 1 Primary Input Channel CSC The CSC must be manually configured for each color space conversion The CSC on the primary input channel can be enabled using the vid csc enable control This CSC can run at 297 MHz and provides color space conversion for UHD video formats The CSC mode on the primary input channel can be configured using vid mode 1 0 The CSC mode is used to define the fixed point position of the CSC coefficients which are located after vid mode 1 0 in the IO Map for the primary input channel Rev 0 Page 83 of 326 06 707 Reference configuration scripts to configure the primary input channel CSC are provided with the evaluation software vid csc enable IO Map Address 0x1B30 7 This bit is used to control the Primary Input Channel CSC Function vid csc enable Description 0 default CSC disable 1 CSC enable vid csc mode 1 0 IO Map Address 0x1B30 6 5 This signal is used to specify the CSC mode for the Primary Input Channel CSC The CSC mode sets the fixed point position of the CSC coefficients including a4 b4 c4 and offsets Function vid csc mode 1 0 Description 00 default 1 0 4096 to 4095
214. This signal sets the RNR level Function di rnr level 1 0 Description 00 N A 01 Low 10 default Middle 11 High For the RNR feature to operate two buffers in external memory must be allocated to store video information which will be used for noise reduction purposes The addresses of these two buffers can be set in the pvsp_rnrbuf0_addr 31 0 and pvsp rnrbufl addr 31 0 registers The size of each buffer should be larger than BUF SIZE which can be calculated as shown in Equation 21 RNR BUF SIZE byte active _ video _ width x active input video height Equation 21 Calculating RNR Buffers Note Using RNR will use external memory bandwidth which may impact on other features such as OSD image storage as well as de interlacing pvsp_rnrbuf0_addr 31 0 Primary VSP Map Address 0xE820 7 0 Address OxE821 7 0 Address 0 822 7 0 Address 0xE823 7 0 Sets the start address of random noise reduction information buffer 0 RNR buffers are needed only when random noise reduction is enabled Rev 0 Page 125 of 326 06 707 Function pvsp rnrbufO addr 31 Description 0 0x000F D200 Default OxXXXXXXXX Start address of RNR buffer 0 pvsp rnrbufl addr 31 0 Primary VSP Map Address 0xE824 7 0 Address 0xE825 7 0 Address 0xE826 7 0 Address 0xE827 7 0 Sets the start address of random noise reduction information buffer 1 RNR buffers are needed only when random noise reduction is
215. Timer 1 result control Function timer1 keep result Description 0 Does not keep timer counter value after timer done 1 Keep timer counter value after timer done Note that the rest of the bits within this register perform the same operation as for but for the other seven timers that is bit 1 controls timer2 bit 2 controls timer3 and so on they are not included here for readability reasons timerl irq en SPI Device Address 0 0 TIMER Address 0x07 0 Timer 1 interrupt enable Function timer1 irq en Description 0 Disable 1 Enable Note that the rest of the bits within this register perform the same operation as for but for the other seven timers that is bit 1 controls timer2 bit 2 controls timer3 and so on they are not included here for readability reasons timerl clr irq SPI Device Address 0x0B TIMER Address 0x08 0 Clears the timer 1 interrupt after writing 1 to this bit Note these are not self clearing bits the user just needs to write 1 to this bit and it will clear the timer flag and timer irq cnt registers Even if timer is already set at 1 it will not clear the timer interrupt and flag until the user writes 1 to it Note that the rest of the bits within this register perform the same operation as for timer1 but for the other seven timers i e bit 1 controls timer2 bit 2 controls timer3 etc they are not included here for readability r
216. VIM The VOM pixel unpacker is configured in the same way as the VIM pixel unpacker e 12 bit 4 4 4 YCbCr e 10 bit 4 4 4 YCbCr e 12 bit 4 2 2 YCbCr 8 bit 4 2 2 YCbCr Data format details are described in pvsp_ex_mem_data_format 1 0 3 2 3 2 VOM Cropper The VOM cropper is similar to the VIM cropper with the exception that it uses the VOM set protocol while the VIM cropper uses the gentle reboot protocol refer to Section 3 4 Using the VIM cropper can reduce the external memory bandwidth required for scaling in cases where bandwidth is a concern If not the VOM cropper should be used The following registers are used to configure the VOM cropper e pvsp di crop enable e pvsp di crop h start 10 0 e pvsp di crop v start 10 0 e pvsp di crop width 10 0 e pvsp di crop height 10 0 To enable cropper in VOM pvsp di crop enable should be asserted pvsp di crop enable Primary VSP Map Address OxE883 4 This bit is used to enable the VOM crop Function pvsp di crop enable Description 0 default Disable VOM Crop 1 Enable VOM Crop Figure 58 shows the function of the VOM cropper Rev 0 Page 121 of 326 06 707 Video Image in External Memory VSP3D DI CROP V START Cropped Image VSP3D DI CROP H START VSP3D DI CROP HEIGHT I VSP3D_DI_CROP_WIDTH Figure 58 VOM Crop Dimensions pvsp di crop h start 10 0 Primary VSP Map Address 0xE83C 2 0 Address 0xE83D 7 0
217. VS Rev 0 Page 166 of 326 06 707 This master signal must be provided to the MAS VS ball The polarity of this sync signal is assumed to be active high and will default to this operation mas vs ie mas hs and mas clk ie are used to enable the respective external sync pins Assumptions for operating in this mode e external sync provided to the ADV8005 will be a CEA 861 or VESA compliant VSync Non standard timing will NOT be supported that is extra or fewer pixels lines or frames than specified in the standard Note that the VS and HS are assumed to be active high e The sync signals supported will be VS and HS Note that HS is optional and only required if interlaced output is required In this case the HS position with respect to the VS will be used to determine the output field required If only progressive outputs are required then the HS may be omitted and VS alone will suffice to lock the output e The external timing provided should match the output video standard programmed For example if 1080i60Hz is to be output from the ADV8005 PVSP and locked to external timing then a 60 Hz Vsync signal should be provided on the MAS VS pin and a 33 750 kHz HSync should be provided on the MAS HS pin In this case the pvsp autocfg output vid 7 0 should be set to 5 O EXT ODD FLD FIELD DETECT DATA PVSP 36 0 DE PVSP HS PVSP PVSP CLK FRAME TRACK CLK GEN vs uas L J PVSP CLK PERIOD
218. Y Random Noise Scaling and Frame Rate Conversion YUV Scaler 1 Scaler 2 Frame Rate Converter OSD Y Generation RGB Bitmap OSD Controller OSD Scaler Figure 41 8005 Image Processing Colorimetry Breakdown 2 2 11 AV Codes Embedded end of active video EAV and start of active video SAV timing codes are supported on the TTL inputs of the ADV8005 AV code information is embedded into the pixel data and is transmitted using a standard 4 byte synchronization pattern A synchronization pattern is sent immediately before and after each line during active picture and retrace The following video formats are supported automatically for AV code insertion e 480160 e 576150 e 240 60 e 288 50 e 480p60 e 576p50 e 720p60 720p50 1080160 1080150 e 1080 60 e 1080 50 e 640x480 e SVGA 800x600 e 1027x768 e WXGA 1280x768 e SXGA 1280x1024 e WXGA 1360x768 e UXGA 1600x1200 e 1366 768 e WUXGA 1900x1200 Rev 0 Page 79 of 326 06 707 number of CEA formats are not supported automatically for AV codes 1920x1080p 23 97 24 Hz CEA VIC 32 1920x1080p 25 Hz CEA VIC 33 1920x1080p 29 97 30 Hz CEA VIC 34 1280x720p 23 97 24 Hz CEA VIC 60 1280x720p 25 Hz CEA VIC 61 1280x720p 29 97 30 Hz CEA VIC 62 Qv Ou m These formats can be supported following the manual configuration mode o
219. a Byte 12 OxF290 R W isrc2 pb13 7 0 0600000000 Data Byte 13 OxF291 R W isrc2 pb14 7 0 0600000000 Data Byte 14 0 292 R W isrc2 pb15 7 0 0600000000 Data Byte 15 OxF293 R W isrc2 pb16 7 0 0600000000 Data Byte 16 06 707 Packet Access Field Default Value Byte Name Address OxF294 R W isrc2 pb17 7 0 0600000000 Data Byte 17 OxF295 R W isrc2 pb18 7 0 0600000000 Data Byte 18 OxF296 R W isrc2 pb19 7 0 0600000000 Data Byte 19 0 297 R W isrc2 pb20 7 0 0600000000 Data Byte 20 OxF298 R W isrc2 pb21 7 0 0600000000 Data Byte 21 OxF299 R W isrc2 pb22 7 0 0600000000 Data Byte 22 OxF29A R W isrc2 pb23 7 0 0500000000 Data Byte 23 OxF29B R W isrc2 pb24 7 0 0600000000 Data Byte 24 OxF29C R W isrc2 pb25 7 0 0600000000 Data Byte 25 OxF29D R W isrc2 pb26 7 0 0600000000 Data Byte 26 OxF29E R W isrc2 pb27 7 0 0600000000 Data Byte 27 As defined in the latest CEA 861 specification 6 12 EDID HANDLING 6 12 1 Reading the EDID The Tx core of the ADV8005 features an EDID HDCP controller which can read the EDID content of the downstream sink through the DDC lines TXDDC SCL and TXDDC SDA This EDID HDCP controller begins buffering segment 0 of the downstream sink EDID once the sink HPD is detected and the Tx core of the ADV8005 is powered up The system can request additional segments by programming the EDID segment pointer edid segment 7 0 edid ready int refer to
220. addr 31 0 Primary VSP Map Address 0xE80C 7 0 Address OXE80D 7 0 Address OxESOE 7 0 Address OxESOF 7 0 This signal is used to set the start address of field frame buffer 3 Software should arrange memory space properly avoiding conflict between different buffers Function pvsp fieldbuffer3 addr 31 0 Description 0 01 00 Default OxXXXXXXXX Start address of field frame buffer 3 pvsp fieldbuffer4 addr 31 0 Primary VSP Map Address 0xE810 7 0 Address OxE811 7 0 Address 0xE812 7 0 Address OxE813 7 0 This signal is used to set the start address of field frame buffer 4 Software should arrange memory space properly avoiding conflict between different buffers Rev 0 Page 110 of 326 06 707 Function pvsp fieldbuffer4 addr 31 0 Description 0x02495A00 Default OxXXXXXXXX Start address of field frame buffer 4 pvsp fieldbuffer5 addr 31 0 Primary VSP Map Address 0xE814 7 0 Address 0xE815 7 0 Address OxE816 7 0 Address 0xE817 7 0 This signal is used to set the start address of field frame buffer 5 Software should arrange memory space properly avoiding conflict between different buffers Function pvsp_fieldbuffer5_addr 31 0 Description 0x02C7EA00 Default OxXXXXXXXX Start address of field frame buffer 5 pvsp_fieldbuffer6_addr 31 0 Primary VSP Map Address 0xE889 7 0 Address OxE88A 7 0 Address 0 88 7 0 Address OxE88C 7 0 This signal is used to set
221. al OR of VSP OSD interrupts 11 VSP interrupt is inverted logical OR of VSP OSD interrupts 8 4 HDMITX CORE 8 4 1 Introduction This section describes the interrupt support provided for the HDMI Tx cores of the ADV8005 The HDMI Tx interrupts are ORd together and connected to the ADV8005 pin The ADV8005 HDMI Tx interrupt architecture provides the following types of bits e Interrupt status clear bits e Interrupt mask bits The interrupt status clear bits are dual purpose when an interrupt event or condition occurs if the interrupt mask bit is set the status bit gets latched to 1 The interrupt can only be cleared by writing a value of 1 to the status clear bit The interrupts mask bits are used to selectively activate an interrupt bit on the interrupt out pin INT 1 The interrupt output pin is active when one or more interrupts bits are set and their corresponding interrupt mask bit is also set Note that any given mask bit does not affect its corresponding interrupt bit but only affects the level on the interrupt output pin INT 1 The enables for all the HDMI transmitter interrupts are described below 8 4 2 Interrupt Architecture Overview The following is a complete list of HDMI Tx interrupts and their descriptions Table 86 HDMI Tx Interrupts Interrupt Description hpd int hpd int en Used to indicate the HDMI transmitter is connected to an HDMI Rx rx sense int rx sense int en Used to detect if an
222. al Video Rx and HDMI Tx are these interrupts are accessed through the SPI interface These interrupts are not documented in detail as they are handled transparently to the user by the Blimp OSD software tool Interrupts from this section are output on the INTO pin for use by the system microcontroller Rev 0 Page 293 of 326 06 707 8 3 1 Interrupt Architecture Overview The following three interrupts are required by the VSP and OSD section Table 85 VSP and OSD Interrupts Interrupt Description OSD CFG DONE Used to indicate to the system controller that the configuration within the ADV8005 RAM memories has completed DMA Used to indicate to the system controller that the current DMA operation has taken place DMA RAM IRQ Used to indicate to the system controller that the DMA hardware block can be read from written to by SPI TIMER IRQ Used to indicate to the system controller that a timer has expired ANIM DONE Used to indicate to the system controller that an animation has completed The following controls are available to the user for indicating interrupts on the VSP and OSD interrupts vsp int pol 1 0 IO Map Address 0x1A76 3 2 This signal is used to control the VSP interrupt polarity Function vsp int pol 1 0 Description 00 default VSP interrupt is logical AND of VSP OSD interrupts 01 VSP interrupt is inverted logical AND of VSP OSD interrupts 10 VSP interrupt is logic
223. al output by a downstream sink The ADV8005 can process the HEAC signal output by the downstream sink in only common mode The ARC Rxs are powered up by default but can be powered down using the tx1 arc powerdown and tx2 arc powerdown bits The ARC pins are disabled by default and must be manually enabled to configure the ADV8005 to output ARC audio The pins can be manually enabled by setting both arc pins oe man and arc pins oe man en to 1 The SPDIF signal extracted by the ARC Rx be output on the 1 OUT and ARC2 OUT pins txl arc s end hpd and tx2 arc s end hpd must both be left at the default value 1750 at all times regardless of whether single ended or common mode ARC is being received tx1 arc powerdown IO Map Address 0x1A87 7 This bit is used to powerdown the TX1 ARC block Function tx1 arc powerdown Description 0 default Power up ARC 1 Power down ARC tx2 arc powerdown IO Map Address 0x1A89 7 This bit is used to powerdown the TX2 ARC block Function tx2 arc powerdown Description 0 default Power up ARC 1 Power down ARC arc pins oe man IO Map Address 0x1ACA 7 This bit is used to control the output enable for ARC outputs Function arc pins oe man Description 0 default Input 1 Output arc pins oe man en IO Map Address 0x1ACB 7 This bit is used to control the manual override for ARC outputs Function arc pins oe man en Description 0 default Auto 1
224. ample Color Values for EIA 770 2 EIA770 3 ED HD Output Standard Selection Sample Color Y Value Cr Value Cb Value White Black To ui Red Green Blue Yellow Cyan Magenta 7 4 9 Color Space Conversion Matrix The input to the encoder block on the ADV8005 should always be in a YCbCr color space If an RGB color space is present at the input pins the CSC on the I O block of the ADV8005 can be used to convert it to YCbCr It is possible however to convert from YCbCr to an RGB stream in the encoder The encoder output color space can be programmed using yuv out yuv out Encoder Map Address OxE402 5 This bit is used to select the output colour space for the encoder Function yuv out Description 0 RGB component outputs 1 default YPrPb component outputs 7 4 10 ED HD Manual CSC Matrix Adjust Feature Rev 0 Page 262 of 326 06 707 The ED HD manual CSC matrix adjust feature provides custom coefficient manipulation for the YPbPr to RGB CSC and is used in ED and HD modes only matrix prog en can be used to enable this feature matrix prog en Encoder Map Address OxE402 3 This bit is used to enable the manual mode for the ED HD colour space converter Function matrix prog en Description 0 default Automatic Mode 1 Manual Mode Normally there is no need to enable this feature because the CSC matrix automatically performs the CSC based on the input mode chosen ED or HD and the outpu
225. and VBI CS When using the SPI compatible slave input for VBI insertion a reduced set of video input formats are supported on the EXOSD input due to the shared pins The VBI data is decoded and supplied to the encoder for output in the video data stream The supported VBI standards are the following e WSS 625i e CCAP 525i and 6251 e CGMS 5251 e CGMS 525p e CGMS 625p 2 2 8 1 Extraction Overview VBI data can be supplied to the ADV8005 through two separate interfaces If there is a pixel bus input from the front end decoder then the VBI data may be provided via an ancillary data stream encoded into the video data If a pixel bus is not available the VBI data can be sent via the dedicated SPI interface Refer to Figure 40 for an overview of this architecture vbi_src 1 SPI 0 ANC SPI Master ccap even data ccap out ccap even dv ccap ext out Ancillary 40 data Ancillary Data dd d Data To Encoder Extractor 12222 00207 Dela y cgms wss out sd cgms wss data spi rx dv 7 0 muxed vid in cgms wss dv cgms wss out hd vid rx clk data in 11 4 N N 33 x x o 5 Figure 40 VBI Data Extraction Block Diagram 2 2 8 2 Ancillary Data Extraction The ancillary data which is encoded in either nibble mode or byte mode is extracted from the input data stream on the Y channel and the VBI data is retrieved Th
226. and does not contain all the processing elements of the PVSP The structure of the SVSP comprises FFS VIM and VOM blocks Input to the SVSP can only be in progressive format The SVSP has the following features Image cropping e Scaling e FRC e Ptol conversion The image cropping function is the same as that provided in the PVSP and like the PVSP there is an image cropper in both the VIM and the VOM of the SVSP In the SVSP only the VIM is capable of scaling video data This means that the VIM of the SVSP can support vertical resolution scaling as well as horizontal resolution scaling The SVSP is also capable of performing FRC which is controlled by the FFS of the SVSP The FFS in the SVSP provides the same functionality as the FFS in the PVSP A PtoI converter which can be used to convert the incoming video standard from progressive to interlaced is also included as part of the SVSP Like game mode in PVSP SVSP can also support bypass DDR mode Using this mode the SVSP can convert between 1080p and 720p without using external memory This allows the user to perform a simple conversion which does not use external memory bandwidth However FRC is not supported in this case The SVSP be simply bypassed by setting svsp bypass to 1 Note The input to the SVSP can only be progressive video Therefore interlaced video must be routed through the de interlacer in the PVSP before being routed to the SVSP The PVSP output can also
227. ate and blend a bitmap based on screen display OSD and output the blended video using one or more of the part s outputs dual HDMI transmitters and a 6 DAC encoder with SD and HD support The ADV8005 has three video inputs the video TTL input the EXOSD TTL input and the Serial Video receiver Rx The combined video TTL input and EXOSD input constitute the flexible 60 bit TTL input port The 60 bit TTL input port can be arranged in a variety of fashions to accept one input video stream for example a 48 bit 3 GHz input video stream from ADV7619 or two input video streams for example a 36 bit input video stream from ADV7844 and a 24 bit input video stream from an external OSD generator Once the data is received the video TTL and EXOSD inputs can be connected to either the primary input channel or the secondary input channel From these input channels the video data can be sent to the internal video processing blocks for example primary VSP or secondary VSP The Serial Video Rx is connected to the RX input channel The Serial Video Rx accommodates inter chip transfer of data over an HDMI compatible interface for example from an HDMI Rx such as ADV7850 or transceiver such as ADV7623 The ADV8005 does not support EDID or DDC activity on this port The motion adaptive de interlacer in the ADV8005 provides excellent edge detection and excellent ultra low angle performance Per pixel motion adaptive de interlacing is used for n
228. ated OSD e OSD can be overlaid in the main 3D video format timings e Blimp OSD software tool and provided ANSI C libraries cover the full design flow of any OSD Rev 0 Page 19 of 326 06 707 1 2 3 Video Encoder e Six NSV 12 bit video DACs e Compliant with all common SMPTE formats e Multiformat video output support o NTSC M PAL B D G H I M N PAL 60 support o Composite CVBS and S Video Y C component YPrPb RGB SD ED and HD e Macrovision Rev 7 1 11 SD and Rev 1 2 ED compliant e Simultaneous SD and ED HD operation 1 2 4 1 4 Transmitter e 3GHzvideo output ADV8005KBCZ 8A 8N models only e Incorporates HDMI v 1 4 with Deep Color x v Color o Content Type Bits o Audio Return Channel Support o support e Supports standard S PDIF for stereo LPCM compressed audio up to 192 kHz e Six channel uncompressed LPCM 125 audio up to 192 kHz e Six channel DSD audio inputs 1 2 5 Additional Features e and position detection e External Sync Timing mode employing Master clock horizontal sync and vertical sync inputs Rev 0 Page 20 of 326 06 707 o o o 8 p
229. atively interlaced input video for example a live sport broadcast where still parts of the image are reconstructed from information on both the odd and even fields and moving parts of the image are interpolated by an advanced interpolation algorithm The de interlacer can also recognize when interlaced input video originally came from progressive content for example 24 Hz movie content or 30 Hz documentary content and reconstructs the original frames Dual video scalers allow the ADV8005 to support two different output resolutions on its outputs for example 1080p60 on HDMI Tx1 and 720p on HDMI 2 and the HD encoder The primary VSP PVSP in the ADV8005 is capable of upscaling from 480i to 4k x 2k formats The secondary VSP SVSP in the ADV8005 is used to provide a second output resolution to accommodate dual zone systems The ADV8005 is also capable of downscaling a single 4Kx2K input to 1080p or lower using a combination of a Horizontal Pre Scaler HPS and the SVSP Also available in the ADV8005 are image enhancing features such as random noise reduction RNR mosquito noise reduction MNR and block noise reduction BNR detail enhancement and automatic contrast enhancement ACE The ADV8005 features an internal bitmap based OSD generator capable of generating OSDs of up to 4k x 2k External solutions can also be implemented and fed into the ADV8005 for blending with the main video A bitmap based OSD is an advanced form of OSD display whic
230. ayed at the highest image quality possible Conversions from slower to higher frame rates are achieved by repeating certain frames Similarly conversions from higher to lower frame rates are achieved by dropping some frames Care has to be taken with repeating and dropping frames so that the quality of the video is not impacted A simple example of frame rate conversion is outlined in Figure 54 This example involves converting the input video at a rate of 24 fps to 30 fps These two frame rates have a ratio of 4 5 for every 4 frames of input video there must be 5 frames of output video This example uses a cadence detection of 3 2 pull down which means that for every second frame of video data an extra field of video information will be displayed F1 F2 24fps A F1 F2 F4 2 3 2 Figure 54 2 3 Frame Rate Conversion Progressive cadence detection can be enabled by setting register pcadence_enable to 1 pcadence_enable Primary VSP Map Address 0xE84D 1 This bit is used to enable progressive cadence detection Rev 0 Page 114 of 326 Function U6 707 pcadence enable Description 0 1 default Disable progressive cadence detection Enable progressive cadence detection Rev 0 Page 115 of 326 06 707 3 2 2 PVSP Video Input Module Video Input Module VIM Input Video VIM Horizontal Cropper Down Scaler Pixel Packer Write to DDR2 Figure 55 PVSP Video Input Module 3 2 2 1
231. baddress to the first falling edge of SCK1 send out MISO1 there are about 10 system clock delays Assuming the 5 1 is 50 duty cycle only when 5 1 is slower than system clock 20 162 MHz 20 8 1 MHz can no delay mode work normally If SCK1 is slower than 6 MHz no delay mode can be set The ADV8005 features an analog antiglitch used to reject glitches on SCK1 SPI slave There are three modes of operation of this filter bypass 2 ns glitch rejection and 5ns glitch rejection The 2 ns glitch rejection mode should be used for clock frequencies between 10MHz and Rev 0 Page 184 of 326 06 707 40 MHz The 5 ns glitch rejection mode should be used for clock frequencies of less than 10 MHz spi filter en IO Map Address 0x1A2C 7 This bit is used to enable the SPI anti glitch filter Function spi filter en Description 0 default Anti glitch filter disable 1 Anti glitch filter enable spi filter sel IO Map Address 0x1A2C 6 This bit is used to select the response of the SPI anti glitch filter Function spi filter sel Description 0 default 2ns glitch rejection 1 5ns glitch rejection 4 2 8 3 SPI Master Interface The ADV8005 SPI master interface serial port 2 is used by the ADV8005 to read the OSD binary file output by Blimp OSD from an external SPI flash memory and to copy it to the DDR2 memory Note that the library of functions provided by ADI will take care of this process the information i
232. be sent to the SVSP as a progressive input svsp bypass Secondary VSP Map Address OxE649 6 This bit is used to bypass the Secondary VSP Function svsp bypass Description 0 default Not bypass Secondary VSP 1 Bypass Secondary VSP Similarly if using the SVSP the VIM and VOM must be enabled This be done by enabling svsp enable vim and enable vom Rev 0 Page 137 of 326 06 707 svsp enable vim Secondary VSP Map Address OxE610 6 This bit is used to control the Video Input Module VIM If this bit is set to 1 the VIM is enabled to write packed input video data into the defined external frame buffer While the Secondary VSP is running if this bit is set to 0 the output video stream will be frozen Function svsp enable vim Description 0 default Disable VIM 1 Enable VIM svsp enable vom Secondary VSP Map Address OxE610 5 This bit is used to control the Video Output Module If this bit is set to 1 the VOM is enabled to read video data from external memory process it and then output it Function svsp enable vom Description 0 default Disable VOM 1 Enable VOM If using the SVSP the FFS must be enabled using svsp enable ffs so that the hardware knows the various conversions that must be performed The use of field frame buffers in external memory is managed by the FFS which decides which frame buffer should be used by the VIM to store input video data Th
233. bit ADV8005KBCZ 4k x 2k at 30 Hz 8 Six 12 bit DACs Yes Yes 8N bit ADV8005KBCZ 8B 4k x 2k at 30 Hz 8 No bit ADV8005KBCZ 8C 3 Gbps 4k x 2k at 30 Hz 8 2 No N A 2 Yes No bit Note that ADV8005KBCZ 8A and ADV8005KBCZ 8N functionality is described throughout this manual figures functional blocks and so on Some sections of this manual are not relevant to the ADV8005KBCZ 8B and ADV8005KBCZ 8C as they do not include those blocks If a section is not relevant to a particular generic this is indicated in the introduction to that section 1 1 1 Digital Video Input Video data can be input into the ADV8005 in a number of ways The flexible 60 bit TTL input port can be configured for dual video inputs video TTL input and EXOSD TTL input for a single video input interleaved TTL data from an ADV7619 or for a single video input and an external alpha channel The 60 bit TTL input port is extremely flexible and can be configured into a number of different arrangements for more information refer to Table 87 and Table 88 Video can also be input into the ADV8005 via the Serial Video Rx which can be used for device to device interconnect for example a serial video link between the ADV7850 and the ADV8005 or a serial video link between the ADV7623 and the ADV8005 Using such front end devices located before the ADV8005 allows the audio to be extracted and processed in a DSP before being reinserted into the ADV8005 aft
234. bit is set to 0 new register settings will be updated by VOM in next frame after this bit is set back to 1 Function svsp update vom Description 0 default Do not update VOM 1 Update VOM 3 3 3 1 Pixel Unpacker The pixel unpacker in the VOM of the SVSP is similar to that in the VOM of the PVSP The pixel unpacker is used to convert external memory words 128 bits into video pixel YCbCr 8 8 8 bit data Pixels in external memory can have the following two different data formats which are the same as those set by the VIM This is configured in the same way as the VIM 24 bit YCbCr e 16 bit YCbCr 4 2 2 Data format details are described in svsp_ex_mem_data_format 1 0 Rev 0 Page 149 of 326 06 707 3 3 3 2 VOM Cropper The VOM cropper is also very similar to the cropper in the VOM of the PVSP The following registers are used to configure the VOM cropper e svsp vom crop enable e svsp vom crop h start 10 0 e svsp vom crop v start 10 0 e svsp vom crop width 10 0 e svsp vom crop height 10 0 The function of the VOM cropper can be seen in Figure 67 To enable the cropper in the SVSP VOM vom crop enable should be asserted svsp vom crop enable Secondary VSP Map Address OxE662 1 This bit is used to enable the VOM crop Function svsp vom crop enable Description 0 default Disable 1 Enable Video Image in External Memory SVSP VOM CROP V START Cropped Image SVSP VOM CROP
235. bitrarily upscale between 480p and 4k x 2k and down scale between 1080p and 480p The advanced scaling algorithm used in the ADV8005 eradicates many common problems associated with scaling video such as ringing and jagged or blurred edges Using a combination of the Horizontal Pre Scaler HPS Rev 0 Page 16 of 326 06 707 and the SVSP the ADV8005 can downscale from 4k x 2k to 1080p The PVSP be employed to further scale the downscaled 4k x 2k content When using the PVSP as the primary scaler the SVSP can also be used to provide a second lower resolution output format The PVSP and SVSP can be connected in parallel or in series The ADV8005 features a number of video enhancement controls such as detail enhancement block noise reduction mosquito noise reduction and random noise reduction Block and mosquito noise are related to the compression of video for transmission or encoding onto a DVD or BD disc Random noise is related to noise picked up during the transmission of video The automatic contrast enhancement feature offered by the ADV8005 intelligently stretches the brightness of an image to enhance the dark areas without saturating the dark areas Note that the dual scaler variants of the ADV8005 are the following e ADV8005KBCZ 8A 8N e ADV8005KBCZ 8C The single scaler variants of the ADV8005 are the following e ADV8005KBCZ 8B 1 1 4 Bitmap On Screen Display The ADV8005 incorporates an OSD core capable of generating an
236. ble the manual bypass for the up dither Setting this bit enables the bypass to be used Function rx ud bypass man en Description 0 default 1 Manual bypass disable Manual bypass enable rx ud bypass man IO Map Address 0x1B8A 1 This bit is used to bypass the up dither block Function rx ud bypass man Description 0 default Disable bypass 1 Enable bypass rx swap bus ctrl 2 0 IO Map Address 0x1B88 7 5 This signal is used to configure the order of the input video bus Function rx swap bus ctrl 2 0 Description 000 default D 35 24 D 23 12 D 11 0 001 D 35 24 D 11 0 D 23 12 010 D 35 24 D 23 12 D 11 0 011 D 23 12 D 35 24 D 11 0 100 D 11 0 D 35 24 D 23 12 101 D 11 0 D 23 12 D 35 24 110 D 23 12 D 11 0 D 35 24 111 D 35 24 D 23 12 D 11 0 Refer to Section 2 2 12 3 for more information on the CSC controls for the RX input channel 2 2 3 Updither Configuration Rev 0 Page 60 of 326 06 707 The block on each of the input channels can be used to increase the bit width of the incoming video This is useful if the output video must be a certain bit depth and the input video is below this level Updither can increase color richness and reduce the effects of quantization rounding and truncation which may have been induced on the video data The updither block can be used in a situation where the video input to the ADV8005 is in 8 bit form and m
237. bled per Tx so that one Tx can receive audio from 125 lines and one from the Serial Video Rx Alternatively both Txs can receive audio from the Serial Video Rx or from the audio input pins Along with setting rx aud packet sel the mclk ratio 1 0 must be set to 00 and mclk en must be set to 1 The audio InfoFrame is not transferred internally from the serial video Rx to the HDMI Tx This needs to be done by software 6 11 3 Audio Configuration The audio input sel 2 0 audio mode 1 0 and 125 format 1 0 fields must be used to configure the Tx core according to the incoming audio input Refer to Figure 98 to Figure 104 for more information on the audio timing formats There is a manual control to set the audio sample packet layout to be 0 or 1 using the ext layoutand layout sel controls ext layout TX2 Main Map Address OxF44A 3 This bit is used to set the external audio layout value Function ext layout Description 0 default Dual channel 1 Multi channel layout sel TX2 Main Map Address 0xF44A 2 This bit is used to select the audio layout value Function layout sel Description 0 default Internal layout 1 External layout audio input sel 2 0 TX2 Main Map Address OxF40A 6 4 This signal is used to specify the audio mode when the input format of the audio is specified Function audio input sel 2 0 Description 000 default 125 001 SPDIF 010 One Bit Audio DSD 011 High Bit Rat
238. both the Serial Video Rx and HDMI transmitters These interrupts can be used to indicate certain events in the Serial Video Rx section OSD and VSP and also the HDMI Tx The ADV8005 features several interrupt controllers which handle three separate interrupt signals These three interrupt signals are available on the interrupt pins INTO and INT2 There is one interrupt available for the Serial Video Rx inputs which is available for use on the interrupt INT2 pin There is a shared interrupt available for both HDMI transmitters on INTI There is also an interrupt pin made available to be used for a number of interrupts in the OSD core These are available on INTO Note The dual transmitter variants of ADV8005 are ADV8005KBCZ 8A ADV8005KBCZ 8N and ADV8005KBCZ 8C The single transmitter variant of ADV8005 is ADV8005KBCZ 8B Any references to interrupts relating to HDMI Tx2 are not applicable to these parts 8 1 INTERRUPT PINS The ADV8005 features three dedicated interrupt pins INTO INT1 and INT2 These pins can be configured as open drain or standard IO pads and can be configured as outputs or inputs By default they are set to standard TTL inputs The following registers are used for setting these pins int pin od en 2 0 IO Map Address 0x1ACC 2 0 This signal is used to select whether the interrupt pins are configured as TTL or as open drain INTO is linked to the OSD interrupts INTI is linked to the HDMI TX interrupts and INT2 i
239. c inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Primary VSP 0x02 From Ptol Converter 0x03 From Internal OSD Blend 1 0x04 From Secondary VSP Ptol Converter 0x05 From Secondary Input Channel 0x06 From RX Input 0x07 From Internal OSD Blend 2 sd enc inp sel 3 0 IO Map Address 0x1A04 3 0 This signal is used to select the video source for the SD encoder When using the encoder in SD only mode enc inp sel must be set to the same value as this signal Function sd enc inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Primary VSP 0x02 From Ptol Converter 0x03 From Internal OSD Blend 1 0x04 From Secondary VSP Ptol Converter 0x05 From Secondary Input Channel 0x06 From RX Input 0x07 From Internal OSD Blend 2 svsp inp sel 3 0 IO Map Address 0x1A05 7 4 This signal is used to select the video source for the Secondary VSP Rev 0 Page 42 of 326 06 707 Function svsp inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Internal OSD Blend 1 0x02 From Primary VSP 0x03 From Internal OSD OSD only no blend 0x04 From Secondary Input Channel 0x05 From RX Input 0x06 From Horizontal Prescaler pvsp inp sel 3 0 IO Map Address 0x1A05 3 0 This signal is used to select the video source for the Primary VSP Function pvsp inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 F
240. can use the following controls to measure frame latency svsp_rb_frame_latency 2 0 and svsp_rb_hsync_latency 11 0 are read only registers Their values are real time frame and HSync latency between input and output video Frame latency may vary within a range the svsp rb max latency 14 0 readback register indicates the maximum frame latency while rb min latency 14 0 indicates the minimum frame latency If svsp frc latency measure en is set to 0 rb latency 14 0 and svsp rb min latency 14 0 are cleared If asserting frc latency measure en SVSP monitors values in svsp rb max latency 14 0 and svsp rb min latency 14 0 and then records the maximum and minimum values of them in the svsp rb max latency 14 0 and svsp rb min latency 14 0 registers which are both 15 bits wide The highest three bits are the frame latency and the lower 12 bits are the HSync latency Users should note that it will take several seconds for the SVSP to find the maximum and minimum frame HSync latency In a normal case not game mode the SVSP s input video and output video latency is consistent svsp frc latency measure en Secondary VSP Map Address OxE662 2 This bit is used to enable measuring frame Hsync latency Function svsp frc latency measure en Description 0 default Disable 1 Enable svsp rb frame latency 2 0 Secondary VSP Map Address 0xE6F2 7 5 Read Only This signal is used to readback
241. ce Connect this pin to ground through a 4 7 resistor DDR DOSIO DDR interface Connect this pin to ground through a 4 7 resistor Connect this pin to ground through a DDR DQ 4 DDR Type DDR interface Description if Unused 4 7 resistor Pin Type Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital input Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO 1 Sensitive node Careful layout is important The associated circuitry should be kept as close as possible to the ADV8005 Rev 0 Page 312 of 326 06 707 APPENDIX C PIXEL INPUT AND OUTPUT FORMATS Rev 0 Page 313 of 326 Table 87 RGB Input Formats 12 8 10 12 16 20 24 24 30 36 30 21 30 apveoos BIT Br 1 2 on ar BIT BIT BIT SD SD SD SD SD SD SD SD SD amp BITDDR 10 BIT DDR 12 BIT DDR SD SD 50 PUN Re ee ee 4 2 2 4 2 2 4 2 2 R SD SD SD SD NAME
242. ceive up to four stereo channels of 125 audio at up to 192 kHz sampling rate The number of 125 channels the Tx processes can be selected with audioif cc 2 0 The selection of the active I2S channels is done via the i2s en 3 0 field The audio sampling frequency of the input stream must be set appropriately via the i2s sf 3 0 field This value is used along with the VIC to determine the pixel repetition factor that the Tx core applies to the video data refer to Section 6 10 3 The value programmed in 128 sf 3 0 is also used to be sent across the TMDS output link in the channel status data information contained in the Audio Sample packets The placement of I2S channels into the Audio Sample subpackets defined in the HDMI specification can be specified in the following fields subpktO 1 src subpktO src subpktl 1 src subpktl r src subpkt2 1 src subpkt2 r src subpkt3 1 src Rev 0 Page 221 of 326 06 707 subpkt3 src When these fields are set to their default values all I2S channels are placed in their respective position for example 1250 left channel in channel 0 left position 253 right channel in channel 3 right position and so on but this mapping is completely programmable if desired The ADV8005 can receive standard 125 left justified right justified and direct AES3 stream formats with a sample word width between 16 bits and 24 bits The format of the input 125 stream is set via 125 format 1 0 while the audio sam
243. circuitry by setting dis cable det rst to 1 This avoids holding the Rx section in reset filt 5v det timer 6 0 HDMI RX Map Address OxE256 6 0 This bit is used to set the timer for the digital glitch filter on the HDMI 5 V detect inputs The unit of this parameter is 2 clock cycles of the ring oscillator 47ns The input must be constantly high for the duration of the timer otherwise the filter output remains low The output of the filter returns low as soon as any change in the 5 V power signal is detected Rev 0 Page 187 of 326 06 707 Function filt 5v det timer 6 0 Description 1011000 default Approximately 4 2us XXXXXXX Time duration of 5 V deglitch filter The unit of this parameter is 2 clock cycles of the ring oscillator 47ns dis cable det rst HDMI RX Map Address OxE248 6 This bit is used to disable the reset effects of cable detection It should be set to 1 if the 5 V pins are unused and left unconnected Function dis cable det rst Description 0 default Resets the HDMI section if the 5 V input pin is inactive 1 Do not use the 5 V input pins as reset signal for the HDMI section 5 2 TMDS CLOCK ACTIVITY DETECTION The ADV8005 Serial Video Rx provides circuitry to monitor TMDS clock activity and also the type of data on the Rx input lines System software can poll these registers and configure the ADV8005 as required rb rx tmds clk det and tmds pll locked can be used to determine i
244. clr Function edge sensitive int st Description 0 edge sensitive int raw not changed state 1 edge sensitive int raw changed state level sensitive int clr IO Address Self Clearing This control is used to clear the level sensitive int st bits This is self clearing bit Function level sensitive int clr Description 0 No function 1 Clear level sensitive int st Rev 0 Page 291 of 326 06 707 edge sensitive int IO Address Self Clearing This control is used to clear the edge sensitive int raw and edge sensitive int st bits This is a self clearing bit Function edge sensitive int clr Description 0 No function 1 Clear edge sensitive int raw and edge sensitive int st level sensitive int mb2 IO Address 0xXX 0 This control is used to set the INT2 interrupt mask for the level sensitive int interrupt When set when the level sensitive interrupt event triggers and an interrupt is generated on INT2 Function level sensitive int mb2 Description 0 Disable level sensitive int detection interrupt for INT2 1 Enable level sensitive int detection interrupt for INT2 edge sensitive int mb2 IO Address This control is used to set the INT2 interrupt mask for the edge sensitive int interrupt When set a new edge sensitive interrupt event will cause edge sensitive int st to be set and an interrupt will be generated on INT2 Function
245. core features an EDID HDCP controller which handles EDID extraction from the downstream sink This EDID HDCP controller also handles HDCP authentication with downstream sink The tasks that the Tx EDID HDCP controller performs are described in Section 6 12 and Section 6 13 The current state of the Tx EDID HDCP controller can be read from the hdcp controller state 3 0 status field hdcp controller state 3 0 TX2 Main Map Address 0xF4C8 3 0 Read Only This signal is used to readback the state of the EDID HDCP controller Function hdcp controller state 3 0 Description 0000 default In Reset No Hot Plug Detected 0001 Reading EDID 0010 In Idle state Waiting for HDCP Request 0011 Initializing HDCP 0100 HDCP enabled 0101 Initializing HDCP Repeater 0110 1111 Reserved 6 9 EDID HDCP CONTROLLER ERROR CODES If an HDCP authentication occurs between the ADV8005 and the downstream sink the ADV8005 can trigger an interrupt to notify this error to the user or the controling CPU The EDID HDCP controller will then report the HDCP error code via the status field hdcp controller error 3 0 The error code is only valid when the error int interrupt bit is set to 1 The last error code will remain in the HDCP EDID controller error field even when the interrupt is cleared hdcp controller error 3 0 TX2 Main Map Address 0xF4C8 7 4 Read Only This signal is used to readback the error code when the HDCP controller error
246. ction The video mode detection feature can inform the user of the CEA 861 defined Video Identification Code VIC of the video being input to the Tx core as well as some additional formats If a CEA 861 format is detected the VIC is contained in vic detected 5 0 Some additional CEA 861 formats are contained in aux vic detected 2 0 For some standards for which the VIC cannot be detected the user needs to configure the following registers e The aspect ratio set via the aspect ratio bit is used to distinguish between CEA 861 video timing codes where the aspect ratio is the only difference Rev 0 Page 212 of 326 06 707 e For240p and 288p modes the number of total lines can be selected in the progressive mode info 1 0 field e The VIC detected is also affected by the pixel repetition see Section 5 7 for more details The detected VIC is sent in the AVI InfoFrames unless pixel repetition is applied to the video stream transmitted by the ADV8005 When pixel repetition is applied to the video data the VIC sent in the AVI InfoFrame may be different as the VIC is automatically determined by the ADV8005 To override the VIC detection the pixel repetition mode must be set to manual by setting pr value manual 1 0 to 0510 or 0511 The desired VIC is then set The Tx core can support non CEA 861 formats but the VIC will not be automatically detected for these formats In this case the VIC should manually be set to the value 0 vic d
247. custom OSDs and emulate them before integrating them into their system abstracting the design task from the underlying OSD hardware For more details on the operation of the external OSD design and system techniques refer to the Blimp OSD documentation Rev 0 Page 17 of 326 06 707 1 1 5 External DDR2 Memory DDR2 Interface Motion Frame Rate Bitmap OSD Adaptive Conversion Data De interlacer Figure 5 External DDR2 Memory Interface External DDR2 memory is required for motion adaptive de interlacing Frame Rate Conversion FRC and OSD bitmap overlay ADV8005 supports various memory options using one or two DDR2 memories of various sizes 1 Gb maximum For full processing capabilities two DDR2 memories are required which use data transfers up to 250 MHz Refer to Section 3 for more details on the operations using the external DDR2 memory 1 1 6 HDMI Transmitter The ADV8005 features two HDMI v1 4b transmitters The transmitters feature an audio return channel ARC which allows a Sony Philips Digital Interface SPDIF audio connection between the source and sink Each transmitter features an on chip MPU with an master to perform HDCP operations and EDID operations Note The dual transmitter variants of the ADV8005 are ADV8005KBCZ 8A ADV8005KBCZ 8N and ADV8005KBCZ 8C The single transmitter variant of the ADV8005 is the ADV8005KBCZ 8B 1 1 7 Video Encoder The ADV8005 features a high speed digital to analog video
248. d explanation of the ISRC packet fields Table 39 15 1 Packet Registers InfoFrame R W Register Name Packet Byte No Map Address OxF2 R W isrc1 packet id 7 0 Packet Type Value OxF3 R isrc1_header1 HB1 OxF4 R isrc1_header2 HB2 0 8 R isrc1_pb_0_1 PBO 0 8 1 pb 0 2 PB1 Ox8E R isrc1 pb 0 3 PB2 Ox8F R isrcl pb 0 4 PB3 0x90 R isrc1 pb 0 5 PBA 0x91 R 51 1 pb 0 6 PB5 0x92 R isrc1 pb 0 7 PB6 0x93 R isrcl pb 0 8 PB7 0x94 R 5 1 0 9 PB8 0x95 R isrc1 pb 0 10 PB9 0x96 R pb 0 11 PB10 0x97 R isrc1 pb 0 12 PB11 0x98 R 1 pb 0 13 PB12 0x99 R isrc1 pb 0 14 PB13 0 9 5 1 pb 0 15 PB14 Ox9B R 5 1 pb 0 16 PB15 0 9 51 1 pb 0 17 PB16 Rev 0 Page 198 of 326 As defined by the HDMI 1 4 specifications InfoFrame R W Register Name Packet Byte No Map Address Ox9D R 1 pb 0 18 PB17 Ox9E R 5 1 pb 0 19 PB18 Ox9F R pb 0 20 PB19 OxAO R 5 1 pb 0 21 PB20 0 1 isrc1 pb 0 22 PB21 OxA2 R 5 1 0 23 22 0 R isrc1_pb_0_24 PB23 0 4 5 1 pb 0 25 PB24 0 5 5 1 pb 0 26 PB25 OxA6 R isrc1_pb_0_27 PB26 OxA7 R isrc1_pb_0_28 PB27 The ISRCI packet registers are considered valid if the ISRC1 packet edge RAW interrupt is set to 1 rx_isrcl_pckt_edge_raw IO Map Address 0x1AFB 4 Read Only UG 707 T
249. d Figure 121 are examples only any user defined curve in the range from 16 to 240 is acceptable 300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 250 2 SIGNAL OUTPUT g 200 z lt 0 5 5 150 tc tc 100 lt lt SIGNAL INPUT 9 50 0 0 50 100 150 200 250 3 LOCATION 8 Figure 120 Signal Input Ramp and Signal Output for Gamma 0 5 Rev 0 Page 270 of 326 GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR 300 VARIOUS GAMMA VALUES GAMMA CORRECTED AMPLITUDE 0 100 150 LOCATION 250 06398 072 Figure 121 Signal Input Ramp and Selectable Output Curves 7 4 17 1 ED HD Gamma Correction enable the gamma correction curves for ED HD standards gamma en hdtv must be programmed gamma en Encoder Map Address 0xE435 5 This bit is used to enable the gamma correction curves for ED HD video data U6 707 Function gamma en hdtv Description 0 default Disabled 1 Enabled The ED HD gamma correction curves are provided in Table 77 and Table 78 Table 77 ED HD Gamma Curve A Curve Type Point Register Address ED HD Gamma Curve A Point 24 OxE444 ED HD Gamma Curve A A1 Point 32 OxE445 ED HD Gamma Curve A A2 Point 48 OxE446 ED HD Gamma Curve A A3 Point 64 OxE447 ED HD Gamma Curve A A4 Point 80 OxE448 ED HD Gamma
250. d av split code IO Map Address 0x1B6B 2 This bit is used to control how AV codes are decoded replicated on or split across all channels Function exosd av split code Description 0 default Replicated av codes on all channels 1 AV codes split across all buses exosd av codes rep man en IO Map Address Ox1B6B 1 This bit is used to control the enable for AV source codes AV codes rep man is used instead of the auto based on the input video format Function exosd av codes rep man en Description 0 default AV codes replicated based on internal flag 1 Use i2c bit exosd av codes rep man IO Map Address Ox1B6B 0 This bit is used to specify if the AV codes are replicated not Codes replicated 4 4 4 FF FF FF 00 00 00 00 00 00 Codes not replicated FF 00 00 AV Function exosd av codes rep man Description 1 AV codes are replicated 0 default AV codes are not replicated The updither feature the ADV8005 can be used to randomize quantization error preventing large scale patterns such as color banding in images Refer to Section 2 2 3 for more information on the updither block The updither block on the secondary input channel can be controlled via the exosd ud bypass man and exosd ud bypass man en bits By default the manual bypass is disabled which means that the updither block cannot be bypassed The updither block configuration is outlined in Sec
251. d below dcfifo level 2 0 HDMI Map Address 0xE21C 2 0 Read Only This signal is a readback to indicate the distance between the read and write pointers Overflow and underflow will read as level 0 The ideal centered functionality will read as 0b100 Function dcfifo_level 2 0 Description 000 default FIFO has underflowed or overflowed 001 FIFO is about to overflow 010 FIFO has some margin 011 FIFO has some margin 100 FIFO perfectly balanced 101 FIFO has some margin 110 FIFO has some margin 111 FIFO is about to underflow dcfifo_locked HDMI RX Map Address 0xE21C 3 Read Only This bit is a readback to indicate if the Video FIFO is locked Function dcfifo_locked Description 0 default Video FIFO is not locked Video FIFO had to resynchronize between previous two Vsyncs 1 Video FIFO is locked Video FIFO did not have to resynchronize between previous two Vsyncs dcfifo_recenter HDMI RX Map Address 0xE25A 2 Self Clearing This bit is used as a reset to recenter the Video FIFO This is a self clearing bit Rev 0 Page 190 of 326 06 707 Function dcfifo recenter Description 0 default Video FIFO normal operation 1 Video FIFO to re centre dcfifo kill dis HDMI RX Map Address OxE21B 2 This bit is used to control whether or not the Video FIFO output is zeroed if there is more than one resynchronization ofthe pointers within 2 FIFO cycles This behavior can be disable
252. d in various configurations within the ADV8005 Access to an external DDR2 memory can be required for the PVSP and SVSP to operate correctly The PVSP needs access to external DDR2 memory in every mode except game mode While the SVSP uses external DDR2 memory for the majority of operations in the case of down converting from 1080p to 720p with the same frame rate no external memory is required and all conversions can take place in internal line memories PtoI converter does not need access to external DDR2 memory 3 2 PRIMARY VSP 3 2 1 Introduction to PVSP Primary VSP FFS Figure 53 ADV8005 PVSP Figure 53 shows the structure of the PVSP which comprises three sections the Video Input Module VIM the Video Output Module and a controller referred to as the Field Frame Scheduler FFS The VIM is used to capture input video data which it then writes to external DDR2 memory The VIM is also capable of cropping input video data and performing horizontal downscaling Before the VIM writes video data to external memory it first packs the video into the appropriate data formats In game mode VIM will send packed 128 bit words to VOM directly instead of writing them into external memory The VOM is used to read data from external memory format this data into 12 bit pixels perform various functions on this data scaling de interlacing and so on and then output this video from the PVSP Many of the PVSP vi
253. d on the new output formats e OSD is required on multiple outputs e OSD and video scaling are to be kept separate Mode 2 OSD rendered at a single set resolution 720p DDR2 Memory Interface Build Scale 5 720p 58 HDMI Video Primary Secondary Output Muxing VSP VSP Muxing 1080p OSD 720p 1 Input E Muxing Secondary Data i e 4 Formatting nw 2353 2 12 8082 77 4 1080 08D we Progressive to 1080i _ es Interlaced 480i Video 36 bit H x HD from Input Y Data Decoder EU Formatting B Encoder 720p OSD Sou EE 3 I EE 4 60 S Encoder ideo S Formatting RX ORE 480i l Figure 12 ADV8005 Mode 2 Configuration Mode 2 places the PVSP after the input block The output from this is sent to the OSD which is in turn sent to the SVSP or converter This mode is very similar to mode 4 except that the OSD position has swapped with the PVSP The primary reason is that in this case the OSD data is not overlaid on the incoming video data and then scaled but rather scaled and then overlaid Scaling the video and OSD separately may improve the quality of the video input to the SVSP If it is possible it is better to scale video and OSD separately and then blen
254. d rather than scaling both together The example in Figure 12 takes a 480i video signal and scales this to 1080p This is then overlaid with OSD data scaled to 1080p This example can generate three different output formats 720p 1080i and 1080p as well as outputting the input SD standard of 480i Rev 0 Page 28 of 326 06 707 2 1 4 Mode 3 Mode 3 should be used if e Two separate upscaled resolutions are required e De interlacing is not required e OSD is required on one resolution only preferably the higher resolution output Mode 3 OSD rendered at a single set resolution 720p DDR2 Memory Interface Build OSD HDMI Tx1 Video Primary 1080p OSD Muxing VSP Input HDMI Exosd 24 bit Muxing Secondary 2 3 Data zu m 720 Input Formatting A 4 amp CSC if 47 YN Secondary 2 E o ideo 5 Y y 36 bit Primary 24 Encoder Input LEM Data mv 1080p OSD Port Formatting CSC 8 ACE y 4 x 4 SD 480p Video 4 from Data 180 Formatting amp CSC a Figure 13 ADV8005 Mode 3 Configuration Both the PVSP and SVSP work in parallel in this mode As the OSD is only on one data path it will only be displayed at a single resolution As shown in the example in Figure 13 the input to the SVSP must be a pro
255. d with this bit Function dcfifo kill dis Description 0 default FIFO output set to zero if more than one resynchronization is necessary during two FIFO cycles 1 FIFO output never set to zero regardless of how many resynchronizations occur dcfifo kill not locked HDMI RX Map Address OxE21B 3 This bit control is used to control whether or not the output of the Video FIFO is set to zero when the video PLL is unlocked Function dcfifo kill not locked Description 0 FIFO data is output regardless of video PLL lock status 1 default FIFO output is zeroed if video PLL is unlocked The DCFIFO is programmed to reset itself automatically when the video PLL transitions from unlocked to locked Note that the video PLL transition does not necessarily indicate that the overall system is stable dcfifo reset on lock HDMI RX Map Address OxE21B 4 This bit is used to enable the reset re centering of video FIFO on video PLL unlock Function dcfifo reset on lock Description 0 Do not reset on video PLL lock 1 default Reset FIFO on video PLL lock 5 7 PIXEL REPETITION In HDMI mode video formats with TMDS rates below 25 Mpixels s require pixel repetition in order to be transmitted over the serial video link When the ADV8005 receives this type of video format it discards repeated pixel data automatically based on the pixel repetition field available in the AVI InfoFrame When hdmi pixel repetition 3 0 is non zero vi
256. ddress 0x1BE4 7 0 Address 0x1BE5 7 0 Address Ox1BEG 7 0 Read Only This signal is used to indicate the statistical result for the phase in AUTO PH SCAN Auto Phase Scan Number This signal is valid when AUTO PH READ READY is HIGH auto po en IO Map Address 0x1BE7 7 This bit is used to enable the auto position detection block Function auto po en Description 0 default Disabled 1 Enabled vid blank blanking area IO Map Address 0x1B49 5 This bit is used to specify the blanking area that is blanked to avoid the filters mistakenly interpreting data in the blanking area Function vid blank blanking area Description 1 default Blanking area is blanked 0 Blanking area data passes through rx blank blanking area IO Map Address 0x1B89 7 This bit is used to specify the blanking area that is blanked to avoid the filters mistakenly interpreting data in the blanking area Function rx blank blanking area Description 1 0 default Blanking area is blanked Blanking area data passes through auto po noise thr 9 0 IO Map Address 0x1BE7 1 0 Address Ox1BE8 7 0 This signal sets the noise threshold minimum value for the sum of the three channels R G and B to differentiate the active pixels from the blank pixels For example if blank value for RGB is 16 the noise threshold should be larger than 48 rb auto po 1 edg lock flag IO Map Address Ox1BE9 1 Read Only This bit ind
257. de 11 can support incoming video of 720p or greater In this mode the input from EXOSD 24 bit input port is routed to the SVSP where it is scaled before being written into DDR2 memory The OSD core then reads back the data as one OSD region and blends this region with input video Mode 11 PiP External OSD 2 720p OSD rendered at a single set resolution 480p DDR2 Memory 480 Interface Build cale 05 480 ben Secondary VSP py HDMI Video Primary Output Txi Muxing VSP Muxing 1080p PiP Input 720p Video Exosd Mining H from 24 bit Decoder Input gt s 2 ne Port 1080p PiP E Y Video SER 4 M Primary eed 2 Data mp Input Port Formatting 1080p PiP CSC amp ACE 720 1 RX from 4 Serial Data i Encoder Transceiver Formatting amp CSC Figure 21 8005 Mode 11 Configuration Rev 0 Page 37 of 326 06 707 2 1 13 Mode 12 Dual Zone OSD Mode 12 should be used if OSD output is required in dual zones Mode 12 PiP External OSD 720p OSD rendered at a single set resolution 480p DDR2 Memory Interface Build Scale 050 480 55 Configurable O N HDMI Video Primary Output Txi Muxi
258. de 6 Mode 6 should be used if e Two separate upscaled resolutions are required e De interlacing is not required e OSD is required on one resolution only preferably the lower upscaled resolution output Input 720 8 Exosd 24 bit Muxing External FPGA A NM 2 Video v 480p Video 36 bit pe from Input Y Decoder Serial Video RX d DDR2 Memory Interface I Secondary Data Formatting amp CSC Primary Data Formatting CSC amp ACE RX Data Formatting amp CSC Primary VSP S econdary VSP 720p Output Muxing HDMI Tx2 HD Encoder SD Encoder Figure 16 ADV8005 Mode 6 Configuration 1080p 1080p 720p OSD Mode 6 places the OSD blend block after the SVSP Both the PVSP block and SVSP work in parallel in this mode As the OSD is only on one data path it will only be displayed at a single resolution As shown in the example in Figure 16 the input to the SVSP must be a progressive format Therefore this mode can only be used when the input is progressive It can be seen from Figure 16 that the same output formats can be generated in this mode However due to the change in location of the OSD blend block the OSD can only be generated on a single output resolution Note De int
259. de and two adaptive filter modes 7 4 18 1 ED HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 122 the ED HD sharpness filter must be enabled sharp en set to 1 and the ED HD adaptive filter must be disabled adapt en set to 0 SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 216 AE 8 514 ALB 5 INPUT a SIGNAL Se STEP lt T 1 2 a 5 BN 9 lt L FREQUENCY MHz 0 2 4 6 8 1 12 FILTER A RESPONSE Gain Ka FILTER B RESPONSE Gain Kb FREQUENCY MHz FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka 3AND Kb 7 Figure 122 ED HD Sharpness and Adaptive Filter Control Block 06398 073 To enable the ED HD sharpness filter the following bit must be written to sharp en Encoder Map Address 0xE431 7 This bit is used to enable the ED HD sharpness filter on the luma data By default this is set to 0 which means the filter is disabled Function sharp en Description 0 default Disabled 1 Enabled Likewise the adaptive filter must be disabled by writing to the following bit adapt en Encoder Map Address 0xE435 7 This bit is used to enable the ED HD adaptive filter Function adapt en Description 0 default Disabled 1 Enabled To select one of th
260. default 011 100 101 110 111 125101 left channel I2S 0 right channel 12S 1 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 125 3 left channel I2S 3 right channel subpktl src 2 0 TX2 Main Map Address OxFA40F 2 0 This signal is used to specify the source of sub packet 1 right channel Function subpkti1 src 2 0 000 001 010 011 default 100 101 110 111 Description 125101 left channel 125101 right channel I2S 1 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 125 3 left channel I2S 3 right channel subpkt2 1 src 2 0 TX2 Main Map Address 0xF410 5 3 This signal is used to specify the source of sub packet 2 left channel Function subpkt2 src 2 0 Description 000 001 010 011 100 default 101 110 111 subpkt2 r src 2 0 TX2 Main Map Address 0xF410 2 0 125101 left channel 125101 right channel 12S 1 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 125 3 left channel 125131 right channel This signal is used to specify the source of sub packet 2 right channel Function subpkt2 r src 2 0 Description 000 001 010 011 100 101 default 110 111 125101 left channel 125101 right channel I2S 1 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 12S 3 left channel I2S 3 right chan
261. deo pixel data is discarded and the pixel clock frequency is divided by hdmi pixel repetition hdmi pixel repetition 3 0 HDMI Map Address 0xE205 3 0 Read Only This signal is a readback to provide the current HDMI pixel repetition value decoded from the AVI Infoframe received The HDMI receiver automatically discards repeated pixel data and divides the pixel clock frequency appropriately as per the pixel repetition value Function hdmi pixel repetition 3 0 Description 0000 default 1x 0001 2x 0010 3x 0011 4x 0100 5x 0101 6x 0110 7x 0111 8x 1000 9 1001 10 1010 1111 Reserved Rev 0 Page 191 of 326 06 707 derep n override HDMI Map Address OxE241 4 This bit is used to allow the user to override the pixel repetition factor derep n is then used instead of hdmi pixel repetition 3 0 to discard video pixel data from the incoming HDMI stream Function derep n override Description 0 default Automatic detection and processing of pixel repeated modes using the AVI infoframe information 1 Enables manual setting of the pixel repetition factor as per DEREP N 3 0 derep n 3 0 HDMI RX Map Address 0xE241 3 0 This signal is used to set the derepetition value if derep_n_override is set to 1 Function derep n 3 0 Description 0000 default DEREP N 1 indicates the pixel and clock discard factor XXXX DEREP_N 1 indicates the pixel and clock discard factor
262. deo processing functions are implemented in the VOM In game mode the VOM will use data from the VIM instead of reading data from external memory The FFS is used to schedule and control the interaction between the VIM external DDR2 memory and the VOM Field frame buffer scheduling field polarity management and FRC management are all implemented in the FFS The PVSP can be bypassed by setting pvsp bypass pvsp bypass Primary VSP Map Address 0xE829 7 This bit is used to bypass the Primary VSP If this bit is set to 1 the input video to the Primary VSP will be directly bypassed to the output port Rev 0 Page 105 of 326 06 707 Function pvsp bypass Description 0 default Not bypass Primary VSP 1 Bypass Primary VSP The VIM and VOM must be enabled if using the PVSP This can be done by enabling the pvsp enable vim and pvsp enable vom bits This must be done regardless of the video conversions being performed pvsp enable vim Primary VSP Map Address OxE828 1 This bit is used to control the Video Input Module VIM If this bit is set to 1 the VIM is enabled to write packed input video data into defined external field frame buffer While the Primary VSP is running if this bit is set to 0 the output video stream will be frozen Function pvsp enable vim Description 0 default Disable VIM 1 Enable VIM pvsp enable vom Primary VSP Map Address OxE828 2 This bit is used to control the Video
263. digital IO z A Bi directional digital IO z A Digital output A Digital output Digital output Digital output A Bi directional digital IO z z z z z A Bi directional digital IO zZ A Bi directional digital IO Bi directional digital IO 2 2 Bi directional digital IO z Bi directional digital IO z A Bi directional digital IO z A Rev 0 Page 310 of 326 06 707 Location AA9 AA10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 5 gt AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Mnemonic Type Description if Unused be Grounded DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 11 DVDD DDR DDR Interface Supply 1 8 V DDR DM 1 DDRinterface Floatthis pin ND DDR DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 21 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 19 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 17 DDR interface Connect this pin to ground through a 4 7 resistor DDR DM 2 DDR interface Float this pin DDR DQ 30 DDRinterface Connect this pin to ground through a
264. dress 0x87 Bit 4 1 Function peak 3 0 Description 0000 default 4dB 0100 OdB 1000 4dB The chroma filters support several different frequency responses including six low pass responses a CIF response and a QCIF response These can be configured using chroma filter sel 2 0 chroma filter sel 2 0 Encoder Map Address 0xE480 7 5 This signal is used to configure the chroma filters for SD data Rev 0 Page 259 of 326 06 707 Function chroma filter sel 2 0 Description 000 default 1 3MHz 001 0 65MHz 010 1MHz 011 2MHz 100 Reserved 101 Chroma CIF 110 Chroma QCIF 111 3MHz In addition to the chroma filters listed with chroma filter sel 2 0 there is an SSAF filter that is specifically designed for the color difference component outputs Pr and Pb This filter has a cutoff frequency of 2 7 MHz and a gain of 40 dB at 3 8 MHz Refer to Figure 115 for more details To enable this filter wide uv filt should be set to 1 EXTENDED SSAF PrPb FILTER MODE 0 10 20 B z 30 o 40 50 60 8 1 2 3 4 5 6 5 FREQUENCY MHz 8 Figure 115 PrPb SSAF Filter wide uv filt Encoder Map Address OxE482 0 This bit is used to enable the SSAF filter for PrPb SD data Function wide uv filt Description 1 default Enabled 0 Disabled If this filter is disabled one of the chroma filters shown in Table 72 can be selected and used for th
265. driver Failure to follow these recommended settings will result in the part not operating to its optimum performance Figure 9 Read and Write Sequence Rev 0 Page 23 of 326 1 i i 1 06 707 2 ADV8005 LEVEL CONTROL ADV8005 DDR2 Memory Interface s TUER HDMI Output Td Muxing 9 24 bit JN HDMI PR VSP YCbCr 4 4 4 Input and Output Tx2 Input N EEA sa Port ob d Primary osp Core b VSP OSD scaler Deinterlacer External OSD X 4 Scaler Internal OSD a HD 36 bit Video enhanc 27 Encoder Video SEMEN Port Secondary 4 VSP SD Serial Scaler Progressive io Encoder Video_ E Interlaced i 1 RX P 4 X d Figure 10 ADV8005 Simplified Block Diagram A simplified block diagram of the ADV8005 can be seen in Figure 10 Video can be routed through the ADV8005 in a number of ways for example the OSD can be blended before the PVSP to display the OSD on all outputs the OSD can be blended before the output to display the OSD on a single output This has been divided into several modes of operation which are recommended by Analog Devices These modes of operation are documented in Section 2 1 and outline the most practical modes in which to configure the ADV8005 The four main processing blocks of the ADV8005 are described as
266. ds sent to the DDR2 controller of the ADV8005 and generates pseudo random data and addresses using a defined protocol The controller first writes a programmable number of random 32 bit words to the external memory The same number of reads are then performed from the written addresses The readback is compared with the pseudo random data generated to check if there are any errors The results are available via readback Loopback Test Logic 512Mb x16 External DDR2 Mem 32 bit data 16 bit data DDR2 address address Controller control control 32 bit data 16 bit data 512M x16 External DDR2 Mem Figure 39 DDR2 Loopback Test Architecture two memory DDR2 loopback test is initialized and started via the following writes 1A 1A5B 22 Recommended Write 1A 1A5F 00 Recommended Write 1A 1A61 06 Recommended Write 1A 1 13 Recommended Write 1AA1 01 Recommended Write 1A 1AA2 25 Recommended Write 1A 1 ID Recommended Write 1A 1 481 Recommended Write 1A 1AA5 81 Recommended Write 1A 1AA7 53 Recommended Write 1AA8 B4 Recommended Write 1A 1 08 Recommended Write 1A 1 0 10 Recommended Write 1A E649 40 Recommended Write A single memory DD2 loopback test is initialized and started via the following writes 1A 1 5 22 Recommended Write 1A 1A5C 20 Recommended Write 1A 1 5 80 Recommended Write 1A 1A5F 00 Recommended Write 1A 1A61 0
267. e 4 2 4 2 4 2 4 2 4 2 4 2 4 4 4 4 4 4 D sss PR 4 4 4 4 4 4 e eese ue 4 44 42 42 42 AE RB BOE Cloc Cloc Cloc Cloc Cloc Cloc k k k k k k Rise Fall Rise Fall Rise Fall OSD IN 2 OSD IN 2 OSD IN 2 1 OSD IN 2 OSD IN 1 OSD IN 1 OSD IN 1 OSD IN 1 OSD IN 1 OSD IN 1 OSD IN 1 OSD IN 1 2 OSD IN 1 1 OSD IN 1 0 OSD IN 9 OSD 8 OSD IN 7 OSD 6 AIT AID BL BID BIO BIO O1 2 011 AO OH O1 O1 OM TIN 1 00 oo OSD IN 5 Ec ej N N TENET Rev 0 Page 314 of 326 G3 G2 G1 GO B7 B6 B5 N R2 R1 RO B6 B5 B4 G7 G6 G5 G4 G3 G2 G1 06 707 OSD IN 4 7 2 2 2 2 2 2 7 2 2 2 7 2 4 2 2 7 7 B3 GO OSD_IN 3 Z Z Z Z Z Z Z Z Z Z Z 7 2 B3 2 2 2 2 2 9 OSD IN 2 2 2 2 Z Z Z Z 2 2 7 2 2 2 2 2 Z OSD IN 1 2 Z 2 2 2 Z 2 2 Z Z 2 2 2 2 2 B1 2 2 OSD 1 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BO d Z Z 2 Z 2 2 2 Z R7 R9 R11 Z 2 2 2 2 2 2 2 2 2 2 2 5 2 2 2 2 2 2 R6 R8 R10 2 2 2
268. e E 4096 E 4096 4096 Equation 11 Input CSC Channel B Output Ou AS EISE y pg 212 01 cc C4 12 a 2 CSC scale Equation 12 RX Input CSC Channel C Output The CSC on the RX input channel is illustrated in Figure 44 Rev 0 Page 89 of 326 06 707 csc mode Out A Figure 45 RX Input Channel CSC The video inputs A In B and In C are connected by default to R and B For more information please see Table 14 The default routing be changed by adjusting the value of rx swap bus ctrl 2 0 Table 14 Default RX Input Channel CSC Signal Routing Input Channel Default RGB Routing Default YCbCr Routing In A R Cr In B G Y In B Cb The 1 to to B3 and to C3 coefficients are used to scale the primary inputs A4 B4 and C4 are added as offsets Floating point coefficients must be converted into 120 bit fixed decimal format then converted into binary format using twos complement for negative values and can only be programmed in the range 1 1 or 4096 4095 The dynamic range of the CSC is 0 1 for unipolar signals G B or 0 5 0 5 for bipolar signals Bipolar signals Pr Pb must be offset to mid range Equations with a dynamic range larger than 1 need to be scaled appropriately using the rx mode 1 0 control To achieve a coefficient value of 1 0 for any given coefficient rx mode 1 0 sh
269. e i2c hps power down in clk out Clock manager clk in gated out gated Figure 74 HPS Block Diagram The HPS block provides two separate low pass filters which can be selected using hps filt bypass The HPS filter can be powered down using hps power down hps power down IO Map Address 0x1A85 7 Powers down the horizontal pre scaler block HPS Powered down by default to save power Function hps power down Description 0 HPS is active 1 default HPS Block is powered down hps filt bypass IO Map Address 0x1A85 4 This bit bypasses filtering done before downsampling Aliasing may occur if this filtering is not done Function hps filt bypass Description 0 default Do not bypass 1 Bypass hps bypass downsample IO Map Address 0x1A85 3 This bit bypasses data downsampling Use this control to just filter but not downsample video data Rev 0 Page 161 of 326 06 707 Function hps bypass downsample Description 0 default Do not bypass 1 Bypass hps phase sel downsample IO Map Address 0x1A85 2 This bit selects whether the downsampling should start by keeping or dropping the first pixel when in a 2 1 downsampling Function hps phase sel downsample Description 0 Start by keeping the first Pixel 1 default Start by dropping the first Pixel hps mode 1 0 IO Map Address 0x1A85 1 0 The filter has 2 operatin
270. e HBR Audio 100 Reserved 125 format 1 0 TX2 Main Map Address 0xF40C 1 0 This signal is used to set the format of the 125 audio stream input to the part Function i2s format 1 0 Description 00 default 125 01 Right justified 10 Left justified 11 AES3 direct mode audio mode 1 0 2 Main Map Address 0xF40A 3 2 This signal is used to specify the exact audio mode when the input format of the audio is specified Case 1 DSD audio input select 0b010 0x DSD raw mode 1x SDIF 3 mode Case 2 audio input select 0b011 00 4 stream with Bi Phase Mark BPM encoding 01 4 stream without BPM encoding 10 1 stream with BPM encoding 11 1 stream without BPM encoding Case 3 DST audio input select 0b100 x0 normal mode 01 DST 2x clock 10 DST 1x clock DDR Rev 0 Page 219 of 326 06 707 Function audio mode 1 0 Description Case 1 Ox 1x Case 2 00 default 01 10 11 DSD AUDIO INPUT SELECT 06010 DSD raw mode SDIF 3 mode HBR AUDIO INPUT SELECT 0b011 4 stream with Bi Phase Mark BPM encoding 4 stream without BPM encoding 1 stream with BPM encoding 1 stream without BPM encoding mclk ratio 1 0 2 Main Map Address OxF40A 1 0 This signal is used to specify the ratio between the audio sampling frequency and the clock described using the N and CTS values Function mclk ratio 1 0 Description 00 128 fs 01
271. e The necessary interactions with the ADV8005 registers and EDID memory as well as when these interactions should take place are illustrated in the diagram Note that there is no need to interact with the DDC bus directly because all of the DDC functionality is controlled by the Tx HDCP EDID controller and follows the HDCP specification 1 4 Rev 0 Page 244 of 326 Set HDCP Request Bit HDCP DESIRED to1 Wait For BKSV ready interrupt Read BKSVs From Registers Tx EDID map Clear BKSV Ready Flag Set BKSV FLAG INT to 1 Send Audio and Video Across HDMI Link If HDMI Tx is Compare BKSVs jWeltfarc nrollen of a repeater i i BCAPS 5 with Revocation HDCP CONTROLU 871 DEPTH ds ist V ER STATE 7 DEVICE COUNT 54 to receiver _ 2 YES fa For BKSV ready interrupt Clear BKSV Ready Controller State 4 Flag Set HDCP CONTROLU BKSV FLAG INT to STATE 1 2 If HDMI Tx is part Compare BKSVs YES m gt with Revocation Read BKSVs from EDID memeroy A of a repeater store BSTATUS info from EDID memory 1 time this state is reached YES Controller State 4 NO Check Number of BKSVs available BKSV_COUNT List Figure 108 HDCP S
272. e 256 individual responses the corresponding gain values ranging from 8 to 7 for each filter must be programmed into the ED HD sharpness filter gain register These are programmed using kb 3 0 and ka 3 0 kb 3 0 Encoder Map Address 0xE440 7 4 This signal is used to configure the ED HD sharpness filter gain value B Rev 0 Page 273 of 326 06 707 Function kb 3 0 Description 0000 default Gain B O 0001 Gain B 1 0111 Gain B 7 1000 Gain B 8 1110 Gain B 2 1111 Gain B 1 ka 3 0 Encoder Map Address 0xE440 3 0 This signal is used to configure the ED HD sharpness filter gain value A Function ka 3 0 Description 0000 default Gain AO 0001 Gain A 1 0111 Gain A 7 1000 Gain A 8 1110 Gain A 2 1111 Gain A 1 7 4 18 2 ED HD Adaptive Filters The ED HD adaptive filter Threshold A Threshold B and Threshold C registers the ED HD adaptive filter Gain 1 Gain 2 and Gain 3 registers and the ED HD sharpness filter gain register are used in adaptive filter mode To activate the adaptive filter control the ED HD sharpness filter and the ED HD adaptive filter must be enabled Refer to the register tables above for enabling and disabling the sharpness and adaptive filter The derivative of the incoming signal is compared to the three programmable threshold values that is the ED HD adaptive filter Threshold A Threshold B and Threshold C registers These registers thold a 7 0 thold b 7 0 a
273. e BKSV Flag interrupt Function bksv flag int Description 0 default Interrupt not active 1 Interrupt active The KSVs from the downstream sink have been read and available in the Memory Map hdcp desired TX2 Main Map Address 0xF4AF 7 This bit is used to request HDCP encryption Function hdcp desired Description 0 default Input audio and video content not to be encrypted 1 The input audio and video content should be encrypted frame encryption en TX2 Main Address OxFAAF 4 This bit is used to request HDCP frame encryption Function frame encryption en Description 0 Current video frame should not be encrypted 1 Current video frame should be encrypted bksv 39 32 TX2 Main Map Address 0xF4C3 7 0 Read Only This register is used to readback the BKSV Byte 4 read from the downstream receiver by the HDCP controller enc on TX2 Main Map Address OxFAB8 6 Read Only This bit is used to readback the HDCP encryption status Rev 0 Page 242 of 326 06 707 Function enc on Description 0 default The audio and video content is not being encrypted 1 The audio and video content is being encrypted 6 13 2 Multiple Sinks and No Upstream Devices When connecting the ADV8005 as a source to an HDMI input of a repeater it is necessary to read all BKSVs from downstream devices These BKSVs must be checked against a revocation list which will be provided on the source conte
274. e CVBS or luma chroma signal 7 4 7 2 ED HD Filters The ADV8005 encoder core also includes a sinc compensation filter designed to counter the effect of sinc roll off in DAC 1 DAC 2 and DAC 3 while operating in ED HD mode The benefit of the filter is illustrated in Figure 116 and Figure 117 which show the effect of the filter when enabled and disabled This filter is enabled by default but can be disabled using sinc filt df en Rev 0 Page 260 of 326 06 707 0 5 0 4 0 3 0 2 0 1 AIN dB o O 0 1 0 2 0 3 0 5 0 5 10 15 20 25 30 FREQUENCY MHz Figure 116 ED HD Sinc Compensation Filter Enabled 06398 067 0 5 0 4 0 3 0 2 0 1 GAIN dB o 5 10 15 20 25 30 FREQUENCY MHz Figure 117 ED HD Sinc Compensation Filter Disabled 06398 068 sinc filt df en Encoder Map Address 0xE433 3 This bit is used to disable the sinc compensation filter on DAC1 DAC2 and DAC3 Function sinc filt df en Description 0 Disabled 1 Enabled 7 4 8 ED HD Test Pattern Generator ADV8005 is able to internally generate ED HD black bar uniform background color or hatch test patterns It is not possible to output a color bar test pattern while EH HD video is being routed through the encoder This test pattern can be enabled using hdtv tp en and the test pattern used can be determined using hdtv flat tp y colour 7 0 cr
275. e DDR2 Memory Features FRC Motion Random Noise OSD Dual Output ADV8005 8A 8N 8C Adaptive De Reduction only Rev 0 Page 69 of 326 06 707 interlacing SD input Supported Supported Supported Total area of all OSD Supported HD input Supported N A Not supported regions on screen at Supported 720p same time must be HD input Supported Intra field Not supported 2 720 480 pixels Supported 10801 interpolation not supported Entire OSD can be up HD input Notsupported N A Not supported scaled to desired Support only for 1080p VSP 3D works output resolution 1 gt 1080 2 in bypass 480p 720p 1080p as VSP 3D mode works in bypass mode Table 7 Indication of ADV8005 Capabilities with Two DDR2 Memories Features FRC Motion Random Noise OSD Dual Output ADV8005 Adaptive De Reduction 8A 8N 8C only interlacing SD input Supported Supported Supported Total area of all OSD Supported HD input Supported N A Supported regions on screen at same Supported 720p time must be 3 720 HD input Supported Supported Supported 480 pixels Supported 10801 HD input Supported N A Only supported for Entire OSD can be up Supported 1080p 8 bit processing scaled to desired output Cannot be resolution supported when OSD enabled Rev 0 Page 70 of 326 2 2 5 3 Table 8 Indication of ADV
276. e DID and SDID from the sending device must match the value programmed in 1A 1A4A 7 0 and 1A 1A4B 7 0 The format of the ancillary data packet is shown in Table 9 Rev 0 Page 74 of 326 2 2 8 3 06 707 Table 9 Output Mode Outline Byte B9 B8 B7 B6 B5 B4 B2 B1 BO Description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 qas ee 0 0 Ancillary Data Preamble 2 1 1 1 1 1 1 1 1 1 1 3 EP EP 12C_DID6 4 0 0 0 DID Data Identification Word 4 EP EP I2C SDID7 25 0 0 0 SDID Secondary Data Identification Word 5 EP EP 0 DC 4 0 0 0 ID1 User Data Word 1 6 EP EP Padding 1 0 VBI DATA STDI 3 0 0 0 ID2 User Data Word 2 7 EP EP LCOUNTT 1 6 0 0 ID3 User Data Word 3 8 EP EP LCOUNTI5 0 0 0 ID4 User Data Word 4 9 EP EP 0 0 0 EF VDP_TTXT 0 0 ID5 User Data Word 5 TYPE 1 0 10 EP EP 0 0 WORD 1 7 4 0 0 ID6 User Data Word 6 11 EP EP 0 0 WORD 1 3 0 0 0 ID7 User Data Word 7 12 EP EP 0 0 WORD 2 7 4 0 0 ID8 User Data Word 8 13 EP EP 0 0 VBI WORD 2 3 0 0 0 ID9 User Data Word 9 1 0 0 0 0 0 0 0 0 0 Pad May or may not be present N 1 B8 Checksum 0 0 SPI Data Extraction If there is not an input video data bus which can provide the ancillary data it may be serialized and sent to the part via a SPI master The ADV8005 contains a dedicated SPI slave for receiving VBI data The SPI interface receives serialized anci
277. e EIA CEA 861 specifications e MPEG InfoFrame registers are considered valid if the following two conditions met ms infoframe det is 1 e ms inf cksum err is 0 This condition applies only if always store infis set to 1 5 9 6 Vendor Specific InfoFrame Registers Table 38 provides a list of readback registers available for the Vendor Specific InfoFrame Table 38 VS InfoFrame Registers InfoFrame Register Name Byte Name Map Address OxE3EC IR vs packet id 7 0 Packet Type Value OxE3ED InfoFrame version number OxE3EE InfoFrame length OxE354 Checksum OxE355 noo pas pas pa pas pa pa OxE35B Data Byte 7 Data Byte 8 vs inf pb O 12 Data Byte 11 OxE35C OxE35D OxE35E OxE35F 0 59 vs inf pb 0 6 Data Byte 5 OxE35A vs inf pb 0 7 Data Byte 6 Rev 0 Page 197 of 326 06 707 InfoFrame R W Register Name Byte Name Map Address OxE36D pb 0 26 Data Byte 25 OxE36E pb 0 27 Data Byte 26 OxE36F R vs inf pb 0 28 Data Byte 27 The Vendor Specific InfoFrame registers are considered valid if the following two conditions are met e vs infoframe det is 1 e inf cksum err is 0 This condition applies only if always store infis set to 1 5 10 PACKET REGISTERS 5 10 1 ISRC Packet Registers Table 39 and Table 40 provide lists of the readback registers available for the ISRC packets Refer to the HDMI 1 4 specifications for a detaile
278. e FFS also decides which frame buffer should be read back by the VOM The SVSP utilizes a frame repeat drop mechanism to implement FRC which is also managed by the FFS svsp enable ffs Secondary VSP Map Address 0xE610 7 This bit is used to control the Field Frame Scheduler FFS If this bit is set to 1 the FFS is enabled and the VIM and VOM are scheduled by the FFS which means the Secondary VSP is in work mode If this bit is set to 0 the Secondary VSP is in idle mode Function svsp enable ffs Description 0 default Disable FFS FRC 1 Enable FFS FRC 3 3 1 1 Autoconfiguration Each block inside the VIM and the VOM be automatically configured to decrease the configuration complexity The svsp autocfg input vid 7 0 and svsp autocfg output vid 7 0 registers should be set to make the autoconfiguration work The 59 94 23 97 Hz timings have the same VID as the corresponding 60 24 Hz timing in Table 28 svsp autocfg input vid 7 0 Secondary VSP Map Address OxE660 7 0 This register is used to set the input timing VIC If this register is 0 SVSP will use values in registers of svsp h vin v and svsp vin fr to set input video Function svsp autocfg input vid 7 0 Description 0x00 default Custom input video OxXX Input timing VIC Table 28 SVSP Supported Input Video Timing and VID Video Timing VID 640x480p60 1 720x480p60 20r3or 140r 15 or 35 or 3
279. e Pa and Pb syncword which marks the beginning of a stream repetition with the subpacket 0 For data bursts with a repetition period which is a multiple of four frames the synchronization will persist If the data burst does not have a repetition period of four frames setting papb sync is not needed but will not have any negative effects The transition of the bit from 0 to 1 causes the one time synchronization so setting the bit from 1 to 0 will have no effect Rev 0 Page 228 of 326 06 707 The mapping between the 125 input signals to the Tx core and the HBR subpackets can be via the following controls e subpktO 1 src subpktO r src e subpktl 1 src subpktl src e subpkt2 1 src subpkt2 src e subpkt3 1 src subpkt3 src Note When the HBR input stream is coming from an ADI HDMI Rx device or from the Rx section of the ADV8005 the fields listed above are set to the respective default values Since there is no standard for chip to chip HBR transfer different settings may be required to map the HBR stream input to the Tx core and a non ADI HDMI Rx device Refer to Table 58 for additional details on the HBR modes supported by the ADV8005 papb sync TX2 Main Address 0xF447 6 This bit is used to synchronize the Pa and Pb syncwords with subpacket 0 for HBR audio Function papb sync Description 0 default No function 1 Synchronize Pa and Pb syncwords with subpacket 0 6 11 4 Nand CTS Paramete
280. e ULAI in demo window pvsp demo window cue enable Primary VSP Map Address OxE87F 5 This bit is used to enable CUE correction in the demo window Function pvsp demo window cue ena ble Description 0 default 1 Disable CUE in demo window Enable CUE in demo window pvsp demo window intra field enable Primary VSP Map Address 0xE87F 4 This bit is used to enable the intra field interpolation in the demo window Function pvsp demo window intra fi eld enable 0 default 1 Description Disable intra field interpolation in demo window Enable intra field interpolation in demo window The contour based interpolation scaler 274 generation with 4k x 2k support demo can be enabled by setting pvsp srscal demo mode ento compare the contour based interpolation scaler and the frequency adaptive scaler 1 generation performance side by side pvsp srscal demo mode en Primary VSP Map Address OxE890 4 This bit is used to enable scaler demo mode Function pvsp srscal demo mode en 0 default 1 Description Scaler not in demo mode Scaler in demo mode 3 2 3 15 Progressive to Interlaced Converter The main progressive to interlaced PtoI converter can be connected to many blocks for example Video TTL input channel EXOSD TTL input channel PVSP and so on The block can be used for video conversion for example conversion of 1080p to 10801 It drops the progressive vide
281. e and manual values selected Function hs end pos 9 0 Description OxXX release hs when hcount reaches OxXX vs beg o pos 10 0 IO Map Address 0x1B91 2 0 Address 0x1B92 7 0 This signal is used to specify the horizontal beginning position of VS for odd fields counting from the EAV if CEA 861 timing generation is enable and manual values selected Function vs h beg o pos 10 0 Description OxXX assert vs when hcount reaches OxXX on odd fields vs h beg e pos 10 0 IO Map Address 0x1B93 7 0 Address 0x1B94 7 5 This signal is used to specify the horizontal beginning position of VS for even fields counting from the EAV if CEA 861 timing generation is enable and manual values selected Rev 0 Page 80 of 326 06 707 Function vs h beg e pos 10 0 Description OxXX assert vs when hcount reaches OxXX on even fields vs v beg pos 5 0 IO Map Address 0x1B94 3 0 Address 0x1B95 7 6 This signal is used to specify the vertical beginning position of VS if CEA 861 timing generation is enable and manual values selected Function vs v beg pos 5 0 Description OxXX assert vs when Icount reaches vs v end pos 5 0 IO Map Address 0x1B95 5 0 This signal is used to specify the vertical ending position of VS if CEA 861 timing generation is enable and manual values selected Function vs v end pos 5 0 Description OxXX release vs when Icount reaches OxXX For the secondar
282. e plldll pre div 1 0 PC controls plidil pre div 1 0 Xtal Clock divider phase detector charge pump gt loop filter VCO ddr2 Figure 38 DDR2 PLL Architecture Figure 38 shows the block diagram of the PLL with the relevant controls The formula used to determine the frequency of the DDR2 memory interface clock is given in Equation 3 plldll sel div plldll _ pre_div 1 Equation 3 DDR2 Memory Interface Clock Frequency The DDR2 clock frequency must not be changed during operation and should only be set prior to initialization of the memory interface plldll_sel_div 5 0 IO Map Address 0x1AA2 5 0 This signal is used to control the DDR2 PLL loop divider The DDR2 clock frequency is given by fxtal i2c plldll sel div i2c plldll pre div plidll_pre_div 1 0 IO Map Address 0x1AA3 3 2 This signal is used to control the DDR2 PLL pre divider 2 2 5 2 DDR2 Bandwidth and Memory Selection The DDR2 interface on ADV8005 can be configured to work with one or two default DDR2 memories Using a single DDR2 memory limits the amount of functionality Different capabilities are possible with different memory sizes An outline of expected limitations are outlined in Table 7 Table 6 and Table 8 Table 6 Indication of ADV8005 Capabilities with On
283. e subpktl src e subpktl src e subpkt2 1 src e subpkt2 src e subpkt3 1 src subpkt3 src The audioif ca 7 0 must be set to a speaker mapping that corresponds to the 125 input stream to subpacket routing Using SPDIF has a default setting of two channels The audio packets use the channel status format conforming to the IEC 60958 specification When the part is configured to receive an 125 stream the information sent in the channel status fields is provided by the following fields e cr bit e info e e category code e source number e word length e channel status e i2s sf Table 63 provides a mapping between the channel status bit encapsulated in the Audio Sample packets sent across the HDMI link to the downstream sink and corresponding ADV8005 fields located in the Tx Main register map Note that the mapping shown in Table 63 is the only application for 125 modes 0 1 2 and 3 set via the i2s format 1 0 field When the part is configured to receive an SPDIF stream the channel status information is taken from the input SPDIF stream audioif ca 7 0 TX2 Map Address 0xF476 7 0 This register is used to set the Speaker Mapping or placement Audio InfoFrame Function audioif ca 7 0 Description 00000000 default Default value XXXXXXXX Speaker mapping cr_bit TX2 Main Map Address 0xF412 5 This bit is used to set the Channel Status Copyright Information Refer to the IEC 60958 3
284. e to the encoder Function func mode 2 0 Description 000 default SD Input Only 001 ED HD SDR input only 010 Reserved 011 Simultaneous SD and ED HD SDR 100 Reserved 101 Reserved 110 Reserved 111 Reserved Once the input configuration to the encoder section is configured the input standard to the SD and or HD encoder must be selected Table 69 lists the possible input standards supported by the ADV8005 encoder core Note that if using the ADV8005 de interlacer and or scaler the input standard of the encoder must be set to that of the output of the VSP section If bypassing the VSP section the user should set this to the standard of the external input video If configuring the HD encoder the input standard must be set using enc mode 4 0 hd enc mode 4 0 Encoder Map Address 0xE430 7 3 This signal is used to select the ED HD output standard Rev 0 Page 251 of 326 06 707 Function hd enc ip mode 4 0 Description 00000 default SMPTE293M 1996 483P 60 1 001 OR ITU R BT 1358 483P 60 1 001 00010 BTA T 1004 EDTV2 483P 60 1 001 OR ITU R BT 1362 483P 60 1 001 00011 ITU R BT 1358 576P 50 00100 ITU R BT 1362 576P 50 00101 SMPTE296M 2001 1 720P 60 OR SMPTE296M 2001 2 720P 60 1 001 00110 SMPTE296M 2001 3 720P 50 00111 SMPTE296M 2001 4 720P 30 OR SMPTE296M 2001 5 720P 30 1 001 01000 5 296 2001 6 720 25 OR 01001 SMPTE296M 2001 7 720P 24 OR SMPTE296M 2001 8 720P 24 1 001
285. easons Rev 0 Page 176 of 326 06 707 timerl flag SPI Device Address 0x0B TIMER Address 0x09 0 Read Only Timer 1 flag Function timer1 flag Description 0 Timer 1 is running 1 Timer 1 is done Note that the rest of the bits within this register perform the same operation as for but for the other seven timers that is bit 1 controls timer2 bit 2 controls timer3 and so they are not included here for readability reasons timerl interval 31 0 SPI Device Address 0x0B TIMER Address 0x0A 7 0 Address 0x0B 7 0 Address 0 0 7 0 Address 0x0D 7 0 Timer 1 interval unit is ms timer2 interval 31 0 SPI Device Address 0x0B TIMER Address 0x0E 7 0 Address 0 0 7 0 Address 0x10 7 0 Address 0x11 7 0 Timer 2 interval unit is ms timer3 interval 31 0 SPI Device Address 0x0B TIMER Address 0x12 7 0 Address 0x13 7 0 Address 0x14 7 0 Address 0x15 7 0 Timer 3 interval unit is ms timer4 interval 31 0 SPI Device Address 0x0B TIMER Address 0x16 7 0 Address 0x17 7 0 Address 0x18 7 0 Address 0x19 7 0 Timer 4 interval unit is ms timer5 interval 31 0 SPI Device Address 0x0B TIMER Address 0x1A 7 0 Address 0x1B 7 0 Address 0x1C 7 0 Address 0x1D 7 0 Timer 5 interval unit is ms timer6 interval 31 0 SPI Device Address 0x0B TIMER Address Ox1E 7 0 Address 0x1F 7 0 Address 0x20 7 0 Address 0x21 7 0 Timer 6 interval unit is ms timer7 interval 31
286. eater than 162MHz and or horizontal resolutions larger than 1920 pixels line Rev 0 Page 163 of 326 06 707 Int Pr og to Hz ids a IEEE 80p 66 00 20 0 8 50 05 spes sss usspe 80p 40 20 0 8 8 50 05 sevi wwe rw Er SIS SIS STER T Op 0 28 4 232 80 2 8 0 50 05 meses saeua spec c Op 0 4 32 80 2 8 0 50 05 6p 56 80 6 6 2 50 01 The 3D gt 2D conversions for Frame Packing Side by Side Full and Side by Side Half packing modes which need to make use of the HPS are shown on the following tables Rev 0 Page 164 of 326 6p 80i 801 D p 720 1440 Pro enne pp 119 88 296 7 134 120 04 119 88 296 7 179 20 04 se C NEZ I 0 720 1440 Int 200 21 x576i 4 240 KARAER g 240 Int Pr og 80p 120 0 0 0 80p 0 0 0 3 5 4 3D Side by Side Full The following 3D standards need to go through the HPS before being converted to a 2D mode VI Int Pr Pixel V H 09 Freq Fre tota MHz q Hz dot s s Op 0 33 4 0 0 Op 5 0 0 0 69 4 4 0 0 69 4 4 0 mii eme 5 2 0 2 Rev 0 Page 165 of 326 Vsy nc lin es gt gt 06 707 wo pis D an o o Ds m o oan ee Oi dd 119 88 Oi dr 119
287. ed on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for the ITU R BT 1358 625p standard VBI data can be present on Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL If CGMS is enabled and VBI is disabled the CGMS data is nevertheless available at the output 7 4 5 SD Subcarrier Frequency Control The ADV8005 encoder core is able to generate the color subcarrier used in CVBS and S Video Y C outputs from the input pixel clock Four 8 bit registers are used to set up the subcarrier frequency The value of these registers is calculated using Equation 27 and Equation 28 Subcarrier Frequency Register Number of subcarrier periods in one video line ju Number of 27 MHz clk cycles in one video line Equation 27 SD Subcarrier Frequency Calculation where the sum is rounded to the nearest integer For example in NTSC mode Subcarrier Register Value 225 222 569408543 Equation 28 SD Subcarrier Frequency Calculation where Subcarrier Register Value 5694085434 0x21F07C1F SD Fsc Register 0 Ox1F SD Fsc Register 1 0x7C SD Fsc Register 2 0 SD Fsc Register 3 0x21 Rev 0 Page 256 of 326 06 707 7 4 5 1 Programming the FSC The subcarrier frequency register value is divided into four FSC registers as shown in Equation 28 The subcarrier frequency registers fsc 31 0 must be updated sequentially starting with Subcarrier Frequency Register 0 and ending with Subcarrier Freque
288. edge sensitive int mb2 Description 0 Disable edge sensitive int detection interrupt for 2 1 Enable edge sensitive int detection interrupt for INT2 In this section all raw bits are classified as being triggered by either level sensitive or edge sensitive events with the following understanding of the terminology Level sensitive events are events that are generally either high or low and which are not expected to change rapidly The raw bit for level sensitive events is not latched and therefore always represents the true real time status of the event in question Edge sensitive events are events that only exist for an instant The raw bits for edge sensitive events are latched and therefore represent the occurrence of an edge sensitive event that happened in the past Raw bits for edge sensitive events must be cleared by the corresponding clear bit 8 2 2 Interrupt Architecture Overview The following is a complete list of Serial Video Rx interrupts their mode of operation edge or level sensitive and a description of each interrupt Table 83 Serial Video Rx Level Sensitive Interrupts Mode of Operation Description Level sensitive Interrupt rx cable det raw st mb1 clr Used to detect if the Serial Video inputs are connected to an upstream IC rx tmdspll Ick raw st mbx clr Level sensitive Used to indicate if the TMDS PLL has locked to the incoming TMDS clock rx tmds clk det raw st mbx clr Level s
289. en Encoder Map Address OxE483 4 This bit is used to enable data on the Vertical Blanking Interval VBI to be accepted as valid data This is valid for SD video data only Function vbi data en Description 1 Enabled 0 default Disabled 7 6 DACCONFIGURATIONS The ADV8005 encoder features six DACs which all operate low drive mode Low drive mode is defined as 4 33 mA full scale current into a 300 load The ADV8005 encoder has two Rser pins which are used to control the full scale DAC output current and therefore the DAC output voltage levels this is achieved through a resistor connected between the pin and GND For low drive operation both Rser and Rser must have value of 4 12 and must have a value of 300 The resistors connected to the Rseri and Rserz pins should have a 1 tolerance The ADV8005 encoder uses two pins for compensating the DAC reference buffer COMP1 and COMP2 A 2 2 nF capacitor should be connected from each of these pins to AVDD2 7 6 1 Voltage Reference The ADV8005 contains an on chip voltage reference that can be used as a board level voltage reference via the Vrer pin Alternatively the ADV8005 can be used with an external voltage reference by connecting the reference source to the Vrer pin For optimal performance an external voltage reference such as the AD1580 is used with the ADV8005 encoder reference voltage If an external voltage reference is not used a 0
290. enable int ie 2 0 IO Map Address 0x1BD2 5 3 This bit is used to control the input path enable for the INT pins Function int pin ie 2 0 Description 0 default input path disable 1 input path enable sclk ie IO Map Address 0x1BD2 2 This bit is used to control the input path enable for the audio SCLK pin Function sclk ie Description 0 default input path disable 1 input path enable mclk ie IO Map Address Ox1BD2 1 This bit is used to control the input path enable for the audio MCLK pin Function mclk ie Description 0 default input path disable 1 input path enable dsd clk ie IO Map Address Ox1BD2 0 This bit is used to control the input path enable for the audio DSD CLK pin Function dsd clk ie Description 0 default input path disable 1 input path enable spil cs ie IO Map Address Ox1BD3 7 This bit is used to control the input path enable for the spil CS pin Function Spi1 cs ie Description 0 default input path disable 1 input path enable spil miso ie IO Map Address Ox1BD3 6 This bit is used to control the input path enable for the spil MISO pin Function miso ie Description 0 default input path disable 1 input path enable spil mosi ie IO Map Address Ox1BD3 5 This bit is used to control the input path enable for the spil MOSI pin Rev 0 Page 49 of 326 06 707 Functio
291. encoder variants of the ADV8005 ADV8005KBCZ 8A 8N The variants of ADV8005 with no encoder are ADV8005KBCZ 8B 8C 7 2 INPUT CONFIGURATION The ADV8005 encoder core is capable of supporting independent SD and ED HD video outputs and also both SD and ED HD video in simultaneous mode The data coming either from the VSP section or directly from the ADV8005 front end input is input to the SD encoder through two 8 10 12 bit SDR buses the ED HD encoder is accessed through three 8 10 12 bit SDR buses Rev 0 250 of 326 VIDEO FROM INTERNAL ADV8002 DATAPATH VIDEO FROM INTERNAL ADV8002 DATAPATH U6 707 ADV8005 ENCODER PROCESSOR MUX S DAGI DAC1 lt 16 20 24 BIT YCbCr 4 4 4 4 4 4 to 4 2 2 SDENCODER gt oes Conversion DAC2 Y 14 BIT pac3 DAC3 14 N A paca DAC 4 gt MBIT pacs 7 24 30 36 YCbCr 4 4 4 TBIT 7 2 c pace dace Figure 111 Simplified View of ADV8005 Encoder Block The video being routed to the SD and ED HD encoders can be selected through the 0x0004 7 4 register ED HD encoder and 0x0004 3 0 SD encoder Refer Section 2 2 1 for more information Once the desired video has been routed to the encoder the mode of the incoming video data needs to be set using func mode 2 0 func mode 2 0 Encoder Map Address 0xE401 6 4 This signal is used to select the input mod
292. ensitive Used to indicate activity on the TMDS clock line rx video 3d raw st mbx clr rx av mute raw st mbx clr Level sensitive Level sensitive Used to indicate if the incoming video is 3D format Used to indicate the AVMUTE value from the general control packet rx hdmi mode raw st mbx clr Level sensitive Used to indicate if the incoming video is HDMI mode or DVI mode rx gen ctl pckt raw st mbx clr Level sensitive Used to indicate if a general control packet has been detected rx gamut raw st mbx clr rx isrc2 pckt raw st mbx clr Level sensitive Level sensitive Used to indicate if a gamut metadata packet has been detected Used to indicate if an ISRC2 packet has been detected rx isrc1 pckt raw st mbx clr Level sensitive Used to indicate if an ISRC1 packet has been detected rx vs info frm raw st mbx clr Level sensitive Used to indicate if a vendor specific InfoFrame has been detected rx ms info frm raw st mbx clr Level sensitive Used to indicate if an MPEG source InfoFrame has been detected rx spd info frm raw st mbx clr rx avi info frm raw st mbx clr Level sensitive Level sensitive Used to indicate if an SPD InfoFrame has been detected Used to indicate if an AVI InfoFrame has been detected Rev 0 Page 292 of 326 06 707 Table 84 Serial Video Rx Edge Sensitive Interrupts Interrupt Mode of Operation Description
293. ensitive int raw Description 0 Event condition not currently occurring 1 Event condition currently occurring edge sensitive int raw IO Address Read Only This readback indicates the status of the edge sensitive interrupt When set to 1 it indicates that an event has occurred Once set this bit remains high until the interrupt is cleared via edge sensitive int clr Function edge sensitive int raw Description 0 No event condition occurred 1 Event condition occurred Level sensitive bit level sensitive int raw always represents the current status of whether or not a particular event or condition is occurring e g if the part is receiving AVI InfoFrames It is not a latched bit and never requires to be cleared Edge sensitive bit edge sensitive int raw indicates that a transient event or condition has occurred it is latched and it needs to be cleared This approach is adopted for important events which have a transient nature e g if the part has received a new AVI InfoFrame If edge sensitive int raw did not latch and returned to 0 sometime after the event occurred the user could miss the fact that the event or Rev 0 Page 289 of 326 06 707 condition occurred Therefore edge sensitive raw bits do not truly represent the current status instead they represent the status of an edge event that happened in the past To clear a latched bit the user must set the corresponding clear bit to 1 Figure 140
294. er the TTL inputs allows the video TTL input pins and the EXOSD TTL input pins to be connected to either the primary or the secondary input channel The primary input channel features an input formatter manually programmable CSC updither function ACE contrast brightness and saturation controls The secondary input channel features an input formatter manually programmable CSC and updither function The Serial Video Rx is connected directly to the Rx input channel and features an input formatter manually programmable CSC and updither function Rev 0 Page 15 of 326 ADV8005 Secondary Input Channel EXOSD High Speed 148 5MHz to 300MHz 24 bit 60 bit Input TTL Input Video Input 36 bit Channel EDS Input ws High Speed Serial Video RX Input Channel Figure 2 ADV8005 Digital Video Interface 1 1 2 Flexible Digital Core The ADV8005 has a flexible digital core allowing multiple options for the routing of video data This allows the user to place the OSD in front of the video processing so the OSD will be overlaid on one or more outputs Alternatively video processing can be placed before the OSD ensuring all outputs are processed to the highest quality The digital core can also be configured so that the ADV8005 can output one or all of the inputs in various arrangements for example picture in picture with one input
295. eral control packet can be read back from deep color mode 1 0 It is possible to override the deep color mode that the ADV8005 unpacks from the video data encapsulated in the processed HDMI stream This is achieved by configuring the override deep color mode and deep color mode user 1 0 controls deep color mode 1 0 HDMI RX Map Address OxE20B 7 6 Read Only This control is a readback indicating the deep color mode information extracted from the general control packet Function deep color mode 1 0 Description 00 default 8 bits per channel 01 10 bits per channel 10 12 bits per channel 11 16 bits per channel not supported override deep color mode HDMI RX Map Address OxE240 6 This bit is used to override the Deep Color mode Function override deep color mode Description 0 default 1 The HDMI section unpacks the video data according to the deep color information extracted from the General Control packets Normal operation Override the deep color mode extracted from the General Control Packet The HDMI section unpacks the video data according to the Deep Color mode set in DEEP COLOR MODE USER 1 0 deep color mode user 1 0 HDMI RX Map Address 0xE240 5 4 This control is used to manually set the Deep Color mode The value set in this register is effective when override deep color mode is set to 1 Function deep color mode user 1 0 Description 00 default 8 bits per channe
296. erlaced inputs can be input to the device in this mode However the SVSP can only accept progressive input formats Therefore the SVSP would be excluded from the processing in this case as would the OSD blend Rev 0 Page 32 of 326 06 707 2 1 8 Mode7 Mode 7 should be used if e HDMI input video is copy protected e Additional processing is required on the new output formats e OSD is required on multiple outputs e OSD and video scaling are to be kept separate Mode 7 OSD rendered at a single set resolution 720p DDR2 Memory Interface Build Scale 050 720p 55 1080 Video Primary Output Txi Muxing VSP Muxing 1080p OSD Input Secondary 2701 Data Hey Formatting nw p 74 2 EOM Lu amp CSC un 1080p OSD Sg 1 Secondary Video 20 36 bit he Pa HD Input toit 3 S Encoder Port Formatting N A 480p OSD only CSC amp ACE Y 4 720p Video 877 from 6 720 Encoder Transceiver Formatting amp CSC b SS d Figure 17 ADV8005 Mode 7 Configuration Mode 7 is different to other modes in that OSD is not overlaid on video data on certain outputs but rather just output on its own In certain cases where HDMI video from an upstream IC is copy protected video data can be output on HDMI outputs but not analog outputs However OSD data can
297. erlaced mode For 240p 59 94 Hz input the ADV8005 encoder core should be configured for NTSC operation For 288p 50 Hz input the ADV8005 encoder core should be configured for PAL operation 7 4 7 Filters The ADV8005 encoder core offers numerous filtering options for both SD and ED HD as well as for both luma and chroma data 7 4 7 1 SD Filters Table 72 provides details on the numerous available SD filters Table 72 Internal Filter Specifications Filter Pass Band Ripple dB 3 dB Bandwidth MHz Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0 65 MHz Monotonic 0 65 Rev 0 Page 257 of 326 06 707 Filter Pass Band Ripple 3 dB Bandwidth MHz Chroma 1 0 MHz 1 Chroma 1 3MHz 009 13095 Chroma 2 0 MHz 22 Chroma 3 0 MHz 32 Chroma CIF 0 65 Chroma QCIF Monotonic 0 5 Pass band ripple is the maximum fluctuation from the 0 dB response in the pass band measured in decibels The pass band is defined to have 0 Hz to fc Hz frequency limits for a low pass filter and 0 Hz to f1 Hz and f2 Hz to infinity for a notch filter where fc f1 and f2 are the 3 dB points 23 dB bandwidth refers to the 3 dB cutoff frequency The luma filter supports several different frequency responses including two low pass responses two notch responses an extended SSAF response with or without gain boost attenuation a CIF response and QCIF respo
298. es VSync pulse width in field 0 Unit is in half lines VSync back porch width in field 0 Unit is in half lines Figure 94 Vertical Parameters for Field 0 Note Field 1 measurements should not be used for progressive video modes 5 9 INFOFRAME REGISTERS In HDMI the auxiliary data is carried across the digital link using a series of packets The ADV8005 Serial Video Rx can automatically detect and store the following HDMI packets e InfoFrames e Audio content protection e International Standard Recording Code ISRC e metadata Section 5 9 1 explains the method through which the ADV8005 can extract and store these InfoFrames 5 9 1 InfoFrame Collection Mode The ADV8005 has two modes for storing the InfoFrame packets sent from the source into the internal memory By default the ADV8005 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame The ADV8005 also provides a mode to store every InfoFrame sent from the source regardless of an InfoFrame packet checksum error This can be configured by setting always store infto 1 always store inf HDMI RX Map Address 0 247 0 This bit is used to force InfoFrames with checksum errors to be stored Function always store inf Description 0 default Stores data from received InfoFrames only if their checksum is correct 1 Always store the data from received InfoFrame regardless of their checksum 5 9 2 InfoF
299. et to 1 the ADV8005 encoder core can automatically identify an NTSC or a PAL B D G H I input stream The ADV8005 encoder core is also configured to correctly encode the identified standard The SD standard bits sd enc ip mode 1 0 and the subcarrier frequency registers are not updated to reflect the identified standard all registers retain their default or user defined values These registers should therefore not be used as a way of determining the decoded standard Table 69 Standards Directly Supported by ADV8005 Encoder Processor Active Frame Standard Resolution Rate Hz 720 x 240 720 x 288 720 x 480 ITU R BT 601 656 720 x 576 ITU R BT 601 656 Rev 0 Page 252 of 326 Active Frame Standard Resolution Rate Hz 720 483 5994 SMPTE293M 720 483 5994 1004 720x483 5994 ITU RBT 1358 720 576 50 ITU R BT 1358 720x483 ITU R BT 1362 720x576 ITU R BT 1362 1920x1035 SMPTE 240M 1920x1035 SMPTE 240M 1280 x 720 5 296 1280 720 E SMPTE 296M 1920x1080 30 25 5 274 1920x1080 29 97 SMPTE 274M 1920x1080 25 SMPTE295 1920x1080 50 ITU RBT7095 1920x1080 30 25 24 SMPTE 274 1920 1080 23 98 5 274 29 97 1920x1080 24 ITU RBT7095 1920x1080 50 5 295 1920x1080 50 59 94 SMPTE 274M 60 06 707 I interlaced P progressive 7 3 OUTPUT CO
300. etected 5 0 TX2 Main Map Address 0xF43E 7 2 Read Only This signal is used to readback the input video code VIC detected refer to the CEA 861 specification aux vic detected 2 0 TX2 Main Map Address 0xF43F 7 5 Read Only This register returns the format of video inputs that have a resolution not defined in the CEA 861 specification Function aux vic detected 2 0 Description 000 default Set by Register 3E 001 240p Not Active 010 576i not active 011 288p not active 100 480i active 101 240p active 110 576i active 111 288p active aspect ratio TX2 Map Address OxF417 1 This bit is used to set the aspect ratio of input video This bit is used to distinguish between CEA 861D video timing codes where aspect ratio is the only difference Function aspect ratio Description 0 default 4 3 1 16 9 progressive mode info 1 0 2 Map Address 0xF43F 4 3 Read Only This bit is used to specify additional information for 240p or 288p input formats Function progressive mode info 1 0 Description 00 default Reserved 01 262 total lines per frame for 240p and 312 total lines per frame for 288p 10 263 total lines per frame for 240p and 313 total lines per frame for 288p 11 Reserved for 240p and 314 total lines per frame for 288p 6 10 3 Pixel Repetition Pixel repetition is used in HDMI to increase the amount of blanking period available to send packets or to increase the pixel clock t
301. f there is a valid clock on the TMDS clock input and if the Serial Video Rx has locked to this If both of these are true rx hdmi mode can be used to indicate the video data that is available on the Serial Video Rx either DVI data or HDMI data rx hdmi mode HDMI RX Map Address 0xE205 7 Read Only This bit is a readback to indicate whether the stream processed by the HDMI core is a DVI or an HDMI stream Function rx hdmi mode Description 0 default DVI Mode Detected 1 HDMI Mode Detected rb rx tmds clk det IO Map Address OXLADF 3 Read Only This bit is used to indicate if there is a clock on the Serial Video RX input lines Function rb rx tmds clk det Description 0 default No TMDS clock detected on the Serial Video RX input lines 1 TMDS clock detected on Serial Video RX input lines tmds pll locked HDMI RX Map Address OxE204 1 Read Only This bit is a readback to indicate if the TMDS PLL is locked to the TMDS clock input of the selected HDMI port Function tmds pll locked Description 0 default The TMDS PLL is not locked 1 The TMDS PLL is locked to the TMDS clock input of the selected HDMI port Note The tmds pll locked flag should be considered valid if a TMDS clock is input on the Serial Video Rx freqtolerance 3 0 HDMI RX Map Address OxE20D 3 0 Sets the tolerance in MHz for new TMDS frequency detection This tolerance is used for the audio mute mask mt msk vclk chng and
302. foFrames which include the AVI InfoFrame MPEG InfoFrame and Gamut Metadata packet GMP are described in Section 6 10 5 Section 6 10 6 and Section 6 10 7 6 10 5 AVI InfoFrame The AVI InfoFrame is defined in the latest CEA 861 specification The user can enable the transmission of AVI InfoFrames to the downstream sink by setting the aviif pkt en bit When the transmission of AVI InfoFrames is enabled the Tx transmits an AVI InfoFrame once every two video fields Table 53 provides the list of registers that can be used to configure AVI InfoFrames aviif pkt en TX2 Main Map Address OxF444 4 This bit is used to enable the AVI InfoFrame Packet Rev 0 Page 214 of 326 06 707 Function aviif pkt en Description 0 Disable AVI InfoFrame 1 default Enable AVI InfoFrame Table 53 AVI InfoFrame Configuration Registers 1 As defined in the latest CEA 861 specification 2 Only used when auto checksum 0 6 10 6 MPEG InfoFrame HDMI Tx Main Bit Location Access DefaultValue Field or Byte Map Address OxEC52 2 0 R W 060100 InfoFrame version number OxEC53 4 0 R W 0b01101 InfoFrame length 0 54 17 0 R W 0600000000 Checksum OxEC55 7 0 R W 0600000000 Data Byte 1 OxEC56 7 0 R W 0600000000 Data Byte 2 OxEC57 7 0 R W 0600000000 Data Byte 3 0 58 7 R W 0 0 Bit 7 of Data Byte 4 OxEC59
303. g modes Mode 0 has higher bandpass but less aliasing rejection Function hps filt mode 1 0 Description 0 Filter mode 0 1 default Filer mode 1 2 Unused 3 Unused 3 5 1 HPS Downscaling The video downsampling block provides a 2 1 reduction on the horizontal resolution of the video stream required to route high resolution high speed data to the PVSP SVSP If only the filter of the HPS is to be used this downsampling block can be disabled with hps bypass downsample It is possible to select whether to keep drop the first pixel of the line when downsampling This is done through hps phase sel downsample Below image illustrates how this control affects a one pixel wide black white column video pattern sent through the HPS Note that the filtering has been disabled in order to preserve the one pixel wide pure black white pattern Changing the phase of the downsampling results in a completely white or black pattern at the output of the HPS block Figure 75 HPS effect of hps phase sel downsample Rev 0 Page 162 of 326 06 707 In order to perform downscaling of video standards with pixel clocks greater than 162MHz it will be necessary to go through the HPS before routing the video to either the PVSP or SVSP For video standards in which after the HPS block the horizontal resolution is bigger than 1920 pixels line it is mandatory to go through the SVSP HPS 2kx2k 24 1080p 60 4kx2k 24 DIN 47 0 2 1 Downsample
304. g the bitmap OSD The external MCU uses the ADV8005 SPI slave serial port 1 interface to configure the registers in the bitmap OSD module The ADV8005 uses its SPI master serial port 2 interface to obtain the OSD data fonts icons and images from an external flash memory and store it into the DDR2 memory The OSD can then be blended onto either of the video paths through the OSD core Rev 0 Page 170 of 326 06 707 SPI Flash SPI SPI Slave Master Blend Blend Blended Output 1 Video Input 1 Output 1 ADV8003 Video Input 2 _ Blend OSD Blend Blended Output 2 Input 2 Output 2 Figure 81 Typical Application Diagram 4 1 3 Typical OSD Component Sizes An indication of typical OSD component sizes in provided in Table 33 This can be used to gain an approximation of the size of an OSD Table 33 Output Port Configuration Settings for Example Output Formats Component Color Mode DDR2 Size 4 2 ARCHITECTURE OVERVIEW 4 2 1 Introduction As outlined in Section 4 1 2 the OSD core in the ADV8005 is controlled mainly via a SPI slave interface and loads images and OSD data into the part via a SPI master interface Consequently a number of the configuration registers for the OSD core are SPI registers and the code required to control these registers is automatically generated by the Blimp OSD software tool abstracting the user away from having to understand them For this reason ma
305. gressive format Therefore this mode can only be used when the input is progressive This mode allows the user to overlay the OSD on the higher resolution output s It can be seen in Figure 13 that the same output formats can be generated in this mode However the OSD is now only generated on the higher resolution outputs This mode allows the user to generate two different outputs resolutions and only display OSD on one output Note De interlaced inputs can be input to the device in this mode however the SVSP can only accept progressive input formats Therefore the SVSP would be excluded from the processing in this case Rev 0 Page 29 of 326 06 707 2 1 5 Mode 4 Mode 4 should be used if e Three possible separate output formats are required e Additional processing is required on the new output formats e OSD is required on multiple output formats s OSD rendered at a single set resolution 720p DDR2Memoy Interface i i Build Scale i OSD 7209 0 i HDMI Tx1 Video i Primary 1080p OSD Muxing VIP 1080p Blend EE gt ur Input HDMI Muxing Secondary T Data 720p Input 4 Formatting A 2 amp CSC MS v E 741 Secondary VSP 720p HD 36 bit Primary AN ood Encoder Us MEL Data SEN 1080p OSD Port Formatting Be
306. h can add effects such as scrolling animation and 3D depth to OSD displays This allows customers to create advanced OSD designs to differentiate their products Once created OSD designs are stored in an external SPI flash memory connected to the ADV8005 The control of the OSD must be performed from the system microcontroller via SPI OSD designs can be created using ADTs software development tool Blimp OSD The ADV8005 offers flexible configuration of its internal circuitry allowing the output of one two or three input channels simultaneously The output of multiple ADV8005s can be synchronized using the master clock horizontal sync and vertical sync inputs This facilitates with the incorporation of a simple FPGA seamless per pixel switching of multiple synchronized ADV8005 inputs The ADV8005 can also measure the picture position and sample quality of the video being processed this assists in identifying the exact video format and the optimum sampling phase of the video front end s ADC Video can be output from the ADV8005 via one or both of the HDMI transmitters the 6 DAC SD HD video encoder or using the TTL interface Both HDMI transmitters support the HDMI v1 4b specifications of increased resolutions 3D video and audio return channel ARC The ADV8005 supports both S PDIF and 8 channel 25 audio The audio can be sourced from either the external audio interface or using the audio pass through feature of the Serial Video Rx The ADV8005
307. h_start 10 0 lt HORIZONTAL RESOLUTION OUTPUT BY VIM 1 e 0 lt svsp_vom_crop_v_start 10 0 lt RESOLUTION OUTPUT BY VIM 1 e svsp vom crop h start 10 0 svsp_vom_crop_width 10 0 lt HORIZONTAL RESOLUTION OUTPUT BY VIM e svsp vom crop v start 10 0 svsp vom crop height 10 0 lt VERTICAL RESOLUTION OUTPUT BY VIM 3 3 3 3 Output Port This section describes the configuration registers for the final block of the VOM of the SVSP The main purpose of the output port is to generate the output video timing and output the video data For more details regarding the various register settings for the output port for various common video formats refer to Table 31 The output setting can be automatically configured using autocfg output vid 7 0 If the output configuration is to be set manually svsp man timing enable should be set to 1 Refer to Figure 68 for more information svsp man dp timing enable Secondary VSP Map Address OxE663 7 This bit is used to enable manually setting output timing Function svsp man dp timing enable Description 0 default Disable 1 Enable svsp dp decount 10 0 Secondary VSP Map Address 0xE632 7 0 Address 0xE633 7 5 This signal is used to set the DE duration of output timing This register s value will be used while svsp autocfg output vid is 0 Function svsp dp decount 10 0 Description 0x000 default Default 0 Data enable count of output timing
308. hat offer four possible output formats this means without reconfiguring the digital core Only three possible output formats are supported at a single time the input format and the two converted formats The number of different output formats will be limited when using the ADV8005KBCZ 8B 8C Rev 0 Page 25 of 326 06 707 Note Table 3 does not list the definitive operation of the device in each mode For example in mode 3 it is listed as possible to have two different output resolutions and just have OSD on a single output However using the output muxing it would also be possible to have a single output format 1080p in this case with OSD going to several outputs Table 3 provides only a guideline for the ADV8005 and should be used as such Depending on user requirements many of these modes could be tailored to a specific solution Section 2 1 2 to Section 2 1 9 describe the usable modes of operation as recommended by ADI These modes should be studied and the appropriate one selected for a given application 2 1 1 Selecting a Mode General guidelines for selecting a mode of operation involve selecting the location of certain blocks in the VSP section For example mode 5 and mode 6 both use the PVSP and SVSP in parallel However as the SVSP can only accept progressive formats input video to the ADV8005 must be progressive If interlaced only the PVSP can be used Therefore a note should be kept of the input formats if selecting these i
309. he SVSP The second is a standalone block The function of this block is exactly as named and can be used for example if the user was to convert an ED format such as 480p to a HD format such as 1080i The PtoI block would be required as part of this conversion Refer to Section 3 2 3 and Section 3 3 3 for more details on the hardware blocks Rev 0 Page 24 of 326 06 707 2 1 ADV8005 MODES OF OPERATION This section outlines the most practical modes in which the ADV8005 can be configured as recommended by ADI These modes describe the various ways to configure the VSP block depending on the input formats as well as the outputs required Table 3 outlines the various options afforded to the user in each mode Depending on the desired output options the appropriate mode should be chosen Table 3 ADV8005 Modes of Operation No of Different Interlaced Input No of Output Input Video Output Formats Format Allowed Formats with Copy Protected OSD2 Mode 1 3 Yes 1 No Mode 2 3 Yes 3 No Mode 3 2 No if using SVSP 1 No Mode 4 2 Yes 2 No Mode 5 3 No if using SVSP 3 No Mode 6 2 No if using SVSP 1 No Mode 7 1 2 Yes 1 2 Yes Mode 8 1 2 Yes 1 2 Yes Mode 9 Bypass 1 Yes 0 Yes Mode 10 PiP 2 No if using SVSP 2 No Mode 11 PiP 1 No if using SVSP 2 No Mode 12 Dual OSD 1 Yes 2 Yes Mode 13 RX OSD 2 Yes 2 Yes Mode 14 3 Inputs 3 Yes 2 Yes modes t
310. he autoposition and autophase blocks is in RGB format If the input is in YCrCb format the auto must be cleared enabling the ADV8005 to perform the color space conversion to RGB If the input is RGB then the CSC should be bypassed Before running the auto position software routine ensure a bright test pattern is used For example a white RGB flat field which will have valid video on the first and last pixel in each line The bright color makes it easier for the algorithm to detect the blank area Rev 0 Page 100 of 326 06 707 ADV7850 ADV7850 VFE map 0 16 0 17 map 0x8C 0x8D 28 Set front end pll ratio Increase fend horizontal Set fend datapath and video standar first blanking area AVI to RGB then enable manual pll Ignore blanking area Select TTL RX input Set ADV8005 datapath IO Ox1B49 5 0x1B89 7 to RGB no CSC 10 map OX1BEO 5 10 Ox1BEO 7 6 Initialize noise threshold 0x80 10 Ox1BE7 1 0 0 18 7 0 Increase noise threshold Enable auto position IO Map 1BE7 7 Reset auto position 10 map Ox1BFE 0 IO map OX1BEA to Ox1BF1 Adjust front end sampling clock Based on video 1 standard detected i Front End write frequenc ADV7850 VFE 0x16 0x17 Figure 52 ADV8005 Auto Position Software Flow Chart auto phpo inp sel 1 0 IO Map Address 0
311. he first byte as the address and the second byte and third bytes as the appropriate subaddress The fourth byte is then considered the data for this subaddress register This means that writes to the part will be in the form lt I C Address Address MSBs Address LSBs gt Data For example to write OxFF to the encoder register map register 0x59AF the writes needed are 0x1A 0x59 OxFF The addresses are outlined in Table 2 Figure 7 shows the register map architecture for the ADV8005 Table 2 ADV8005 Address and Register Address Range for Different HW Blocks Register Map Name Address Register Address IO Map 0x1A00 to Ox1BFF Primary VSP Map OxE800 to OxEBFF Primary VSP Map 2 OxE900to OxESFF Secondary VSP Map OxE600 to OxEGFF Rx Main Map fT OXE2 00 to 2 Rx InfoFrame Map 0 00 to 1 22 OxECOO to Tx1 EDID Map OxEEO0 to OXEEFF Tx1 UDP Map OXF200 to OxF2FF 1 Test OxF300to 2 Main Map OxF400to OxFAFF 2 EDID Map O0xF600 to OxF6FF Tx2 UDP Map Do OXFA00 to 2 Test OxFBOO to OxFBFF Encoder Map fT 0 400 to OxEAFF DPLL Map OxEO00 to OxEOFF PRIMARY VSP PRIMARY VSP SECONDARY DPLL Rx MAIN Rx INFOFRAME ENCODER Tx1 TEST MAP MAP 2 VSP MAP MAP MAP MAP MAP MAP ADDRESS 0x1A00 TO 0 800 TO OxE900 TO OxE600 TO 0 000 TO OxE200 TO 0
312. he input path enable for the master HS pin Function mas hs ie Description 0 default input path disable 1 input path enable mas vs ie IO Map Address Ox1BD4 0 This bit is used to control the input path enable for the master VS pin Rev 0 Page 50 of 326 06 707 Function mas vs ie Description 0 default input path disable 1 input path enable 2 2 2 5 Serial Video Rx The Serial Video Rx can only be connected to the RX input channel see Section 2 2 2 8 2 2 2 6 Primary Input Channel The ADV8005 primary input channel incorporates an input formatter CSC updither block and ACE control The input formatter provides a number of controls to configure what data the video TTL input channel is configured for The video TTL input channel must be connected to either the video TTL input pins the EXOSD TTL input pins or the high speed TTL input pins using p inp chan sel 1 0 If the primary input channel is connected to the video TTL input pins the format and bit width of the data for example 2 x 8 bit buses of 4 2 2 data must be specified using vid format sel 4 0 vid swap bus ctrl 2 0 can be used to indicate which input pins are used to carry the upper middle and lower ranges of bits for example upper D 35 25 middle D 24 12 lower D 11 0 or upper D 11 0 middle D 35 25 lower D 24 12 p inp chan sel 1 0 IO Map Address 0x1A07 1 0 This signal is used to select the input for
313. hich is used to control the Serial Video Rx These registers are used to configure the ADV8005 to accept input video from a device such as an HDMI transceiver for example ADV7623 or a front end device with HDMI output for example 7850 5 1 5V DETECT The Serial Video Rx on the ADV8005 can monitor the level on the 5 V power signal pin This 5 V signal can be used to reset the Rx section if requested If 5 V detection is not being used this pin should be connected to a 5 V supply The controls for 5 V detection can be found in the following I C registers These registers are valid even when the part is not processing TMDS information filt 5v det dis HDMI RX Map Address OxE256 7 This bit is used to disable the digital glitch filter on the HDMI 5V detect signals The filtered signals are used as interrupt flags and also used to reset the HDMI section The filter works from an internal ring oscillator clock and is therefore available in power down mode The clock frequency of the ring oscillator is 42MHz 10 Note If the 5 V pins are not used and left unconnected the 5 V detect circuitry should be disconnected from the HDMI reset signal by setting dis cable det rst to 1 This avoids holding the HDMI section in reset Function filt 5v det dis Description 0 default Enabled 1 Disabled Note If the 5 V pins are not used and left unconnected the 5 V detect circuitry should be disconnected from the Rx reset
314. his pin must be connected digital B13 PVDDI PLL Analog Supply Voltage 1 8 V Float this pin B14 B19 RX_1P Float this pin B20 RX_2P Float this pin 821 Connect this to ground through 4 7 resistor B22 B23 C1 C2 CL This pin must be connected Serial port Connect this pin to ground through a control 4 7 resistor Miscellaneous Connectthis pin to ground through a digital 4 7 resistor Miscellaneous This pin must be connected digital C8 C10 C11 C12 C14 C15 Mnemonic MISO1 G COMP1 DAC4 OSD IN 19 EXT DIN 3 OSD_IN 20 EXT_DIN 4 SCK1 INTO Type Float this pin Miscellaneous analog1 Analog video output OSD video input miscellaneous digital OSD video input miscellaneous digital Audio input GND Hoat this pin Float tis pin C16 RX_HPD Float this pin C17 AVDD1 Power C19 PDN GND GND NC NC GND GND GND Description if Unused B17 RX CP Float this pin B18 _ Float this pin Float this pin Float this pin as it is disabled by default Float this pin as it is disabled by default V Ground Serial Video Rx Inputs Analog Supply 3 3 Pin Type Digital output Digital output Digital Input Digital Input N A N A Digital output Digital output N A Digital input Digital input Digital input Digital input N A Analog input Analog output Bi directional
315. his readback indicates the raw status of the ISRC1 packet received signal Once set this bit remains high until cleared via the corresponding clear bit Function rx_isrc1_pckt_edge_raw Description 0 default No new ISRC1 packet received 1 ISRC1 packet with new content received Table 40 ISRC2 Packet Registers InfoFrame R W Register Name Packet Byte Map Address OxE3F5 R W isrc2_packet_id 7 0 Packet Type Value Ox E3F6 R isrc2_header1 HB1 Ox E3F7 R isrc2 header2 HB2 Ox E3A8 R isrc2 pb 0 1 PBO Ox E3A9 R isrc2 pb 0 2 1 Ox isrc2 pb 0 3 PB2 Ox E3AB R isrc2 pb 0 4 PB3 Ox E3AC R isrc2 pb 0 5 PB4 Ox E3AD R isrc2 pb 0 6 PB5 Ox E3AE R isrc2 pb 0 7 PB6 Ox E3AF R isrc2 pb 0 8 PB7 Ox E3BO R isrc2 pb 0 9 PB8 Ox 1 R isrc2 pb 0 10 PB9 Ox E3B2 R isrc2 pb 0 11 PB10 Ox E3B3 R isrc2 pb 0 12 PB11 Ox 4 R isrc2 pb 0 13 PB12 Ox E3B5 R isrc2 pb 0 14 PB13 Ox E3B6 R isrc2 pb 0 15 14 Ox E3B7 R isrc2 pb 0 16 PB15 Ox E3B8 R isrc2 pb 0 17 PB16 Ox E3B9 R isrc2 pb 0 18 PB17 Ox E3BA R isrc2 pb 0 19 PB18 Ox E3BB R isrc2 pb 0 20 PB19 Ox R isrc2 pb 0 21 PB20 Ox E3BD R isrc2 pb 0 22 PB21 Rev 0 Page 199 of 326 06 707 InfoFrame R W Register Name Packet Byte No Map Address Ox E3BE R isrc2 pb 0 23 PB22 Ox E3BF R isrc2 pb 0 24 PB23 Ox E3CO R isrc2 pb 0 25 PB24 Ox R isrc2 pb 0 26 PB25 O
316. hould be left powered down vid ie IO Map Address Ox1BC8 5 This bit is used to control the input path enable for the VID CLK pin Function vid clk ie Description 0 default input path disable 1 input path enable osd ie IO Map Address Ox1BC8 4 This bit is used to control the input path enable for the osd clk pin Function clk osd ie Description 0 default input path disable 1 input path enable pix pins ie 31 0 IO Map Address 0x1BC9 7 0 Address Ox1BCA 7 0 Address 0x1BCB 7 0 Address 0x1BCC 7 0 This bit is used to control the input path enable for the pixel pins Function pix pins ie 31 0 Description 0 default input path disable 1 input path enable osd pins ie 23 0 IO Map Address 0x1BCD 7 0 Address Ox1BCE 7 0 Address Ox1BCF 7 0 This bit is used to control the input path enable for the osd pins Rev 0 Page 47 of 326 06 707 Function osd pins ie 23 0 Description 0 default input path disable 1 input path enable hs ie IO Map Address Ox1BDO 7 This bit is used to control the input path enable for the HS pin Function hs ie Description 0 default input path disable 1 input path enable vs ie IO Map Address Ox1BDO 6 This bit is used to control the input path enable for the VS pin Function vs ie Description 0 default input path disable 1 input path enable de ie IO Map Address Ox1
317. hreshold 5 0 When dnr enable sharpness is enabled it is possible to add a fraction of the signal that lies above the set threshold to the original signal because this data is assumed to be valid data and not noise The overall effect is that the signal is boosted similar to using the extended SSAF filter dnr enable sharpness Encoder Map Address 0xE4A5 3 This bit is used to select the Digital Noise Reduction DNR mode Function dnr enable sharpness Description 0 default DNR mode 1 DNR sharpness mode 7 4 19 8 DNR Block Offset Control offset 3 0 allows a shift of the data block of 15 pixels maximum The coring gain positions are fixed The block offset shifts the data in steps of one pixel so that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data offset 3 0 Encoder Map Address 0xE4A5 7 4 This signal is used to configure the Digital Noise Reduction DNR block offset Rev 0 Page 282 of 326 06 707 Function offset 3 0 Description 0000 default 0 pixel offset 0001 One pixel offset 1110 14 pixel offset 1111 15 pixel offset 7 4 19 9 SD Active Video Edge Control The ADV8005 encoder core is able to control fast rising and falling signals at the start and end of active video in order to minimize ringing artifacts When the active video edge control feature is enabled the first three pixels and the last three pixel
318. icates if the algorithm has locked to the left edge of the input video If this bit is high it has locked to the left edge a low indicates it has not locked to it Rev 0 Page 102 of 326 06 707 rb auto po r edg lock flag IO Map Address Ox1BE9 0 Read Only This bit indicates if the algorithm has locked to the right edge ofthe input video If this bit is high it has locked to the right edge a low indicates it has not locked to it rb auto po t offset 15 0 IO Map Address Ox1BEA 7 0 Address Ox1BEB 7 0 Read Only This readback signal returns the top offset the number of blank lines before the start of active video This offset excludes the vertical blanking area rb auto po b offset 15 0 IO Map Address 0x1BEC 7 0 Address 0x1BED 7 0 Read Only This readback signal returns the bottom offset the number of blank lines after active video This offset excludes the vertical blanking area rb auto po 1 offset 15 0 IO Map Address Ox1BEE 7 0 Address Ox1BEF 7 0 Read Only This readback signal returns the left offset the number of blank Pixels before the start of active video This offset excludes the horizontal blanking area rb auto po offset 15 0 IO Map Address 0 1 0 7 0 Address Ox1BF1 7 0 Read Only This readback signal returns the right offset the number of blank Pixels after active video This offset excludes the horizontal blanking area 2 2 14 ADV8005 Silicon Revision The ADV8005 silicon revision
319. ideo Timing and VID Video Timing VID 640x480p60 1 720x480p60 20r3or 140r 15 35 or 36 720 1440 x240p60 8or9 720 2880 x240p60 12 or 13 1280x720p60 4 1920 1080160 5 720 480160 7 100r 11 1920 1080 16 720x576p50 17 or 18 or 29 or 30 37 or 38 1280x720p50 19 1920x1080i50 20 720x576i50 21 or 22 or 25 or 26 720x288p50 23 or 24 or 27 or 28 1920x1080p50 31 1920x1080p24 32 Rev 0 Page 139 of 326 06 707 Video Timing VID 1920x1080p25 33 1920x1080p30 34 720p100 41 576p100 42 or 43 720p120 47 480p120 48 or 49 576p200 52 or 53 480p240 56 or 57 VGA 200 SVGA 201 XGA 202 WXGA 203 VESAtiming SXGA 204 WXGA 2 205 UXGA 206 WXGA 3 207 WUXGA 208 Note The SVSP does not support the following formats 10 1280x720p 23 97 24 Hz CEA VIC 60 11 1280x720p 25 Hz CEA VIC 61 12 1280x720p 29 97 30 Hz CEA VIC 62 If overscan crop or album mode is employed the required blocks should be configured manually by enabling the corresponding enable bits such as svsp_vim_crop_enable to enable the VIM crop block 3 3 1 2 Customized Input Output Video Format Configuration If the input timing is not in the SVSP input format table the input format needs to be set manually If the input resolution has a variation in regard to standard timing for example if autocfg input vid 7 0 is set
320. important to note that if the output timing is being locked to the external MAS VS reference it cannot be locked to the input timing at the same time This means that if there are frequency differences between the external timing and input timing provided to the ADV8005 input frames of video will be either dropped or repeated to account for these differences and keep the output timing locked to the external master Rev 0 Page 167 of 326 06 707 reference MAS VS It is also possible to add a track offset via track offset 20 0 to the phase error that is eliminated This allows the ADV8005 to either advance or delay the output timing versus the reference timing which is externally provided on the MAS VS ball in this case If there is not the possibility of providing an advanced external sync versus the desired output timing then an advance can be programmed to individual ADV8005 parts in order to achieve the same effect pvsp track offset 20 0 IO Map Address 0x1A94 4 0 Address 0x1A95 7 0 Address 0x1A96 7 0 This signal is used to program the delay on the output timing of VSyncs from the Primary VSP Function lt track offset 20 0 Description 0 input and output VSync coincident 1 1 Xtal clk between input and output VSync MAS sync mode using frame track can be enabled using frtrk mas mode en pvsp frtrk mas mode en IO Map Address 0x1B97 0 This bit enables the use of external master hs
321. impossible to run out of regions while designing even the most complex OSD Node5 6 Node3 Node4 7 Node8 Figure 85 OSD Menu Bar Component Rev 0 Page 174 of 326 06 707 4 2 5 2 OSD Color Space Bitmap images as well as external OSDs are passed to the OSD core in 8 bit RGB format However all video processing in the ADV8005 takes place in YCbCr The OSD core features a CSC to enable conversion of the OSD data from RGB to YCbCr The OSD core CSC can convert into either full of limited range YCbCr 4 2 6 OSD Timers ADV8005 OSD supports up to eight hardware timers One of these timers user selectable the OSD firmware is used by the OSDTimer component of Blimp OSD which can be inserted within any OSD design consult the Blimp OSD manual for a detailed description of how to do this Blimp OSD will automatically handle a number of OSD timers and will map all of them to one hardware timer If the OSD design flow with the Blimp OSD tool is followed the user does not need to know any low level details about the timers However since they can also be used as general purpose system timers its low level functionality will be described in this section Note that the HW timer being used by Blimp OSD user selectable as mentioned will not be available to be used as general purpose timer Any of these eight timers can trigger an interrupt on the INTO pin This interrupt can then be handled by the M
322. in 0001 11 16 1 8 0010 42 16 2 8 0011 3 16 3 8 0100 4 16 4 8 0101 15 16 5 8 0110 16 16 6 8 0111 47 16 7 8 1000 8 16 1 7 4 19 3 DNR Threshold dnr threshold 5 0 is used to define the threshold value in the range of 0 to 63 The range is an absolute value Rev 0 Page 280 of 326 06 707 dnr threshold 5 0 Encoder Map Address 0xE4A4 5 0 This signal is used to configure the Digital Noise Reduction DNR threshold Function dnr threshold 5 0 Description 000000 default 0 000001 1 111110 62 111111 63 7 4 19 4 Border Area When blk border 2 is set to 1 the block transition area can be defined to consist of four pixels If this bit is set to logic 0 the border transition area consists of two pixels where one pixel refers to two clock cycles at 27 MHz 720 x 485 PIXELS NTSC TWO PIXEL BORDER DATA yY t PA 8 x 8 PIXEL BLOCK 8 x 8 PIXEL BLOCK 06398 080 Figure 129 SD DNR Border Area blk_border_2 Encoder Map Address 0xE4A4 6 This bit is used to select the Digital Noise Reduction DNR border area Function border 2 Description 0 default 2 pixels 1 4 pixels 7 4 19 5 Block Size Control dnr mpeg 1 is used to select the size of the data blocks to be processed Setting the block size control function to 1 defines a 16 pixel x 16 pi
323. ing ability Function di bnr global strength gain Description 3 0 1000 default Recommended setting for low mid level BNR 1100 Recommended setting for high level BNR di bnr detect scale line 3 0 Primary VSP 2 Map Address 0xE987 7 4 This signal is used to configure the BNR processing ability Function di bnr detect scale line 3 0 Description 0111 default Recommended setting for low mid level BNR 1001 Recommended setting for high level BNR 3 2 3 10 Sharpness Enhancement The sharpness enhancement block extracts high frequency data from the de interlaced and de noised video frame to help simultaneously sharpen the appearance of edges and other video details recover high frequency components and provide pictures with a natural look without adding a halo or ringing artifact Since the sharpness works on a two dimensional pixel array before the scaler noise will not be scaled during the scaling operation Detail and edge sharpness enhancement supports both interlaced and progressive inputs It can be enabled or disabled using di sharpness enable The sharpness level can be adjusted using the signed twos complement value in pvsp srscal scale gain 11 0 To increase the sharpness setting the value in srscal scale gain 11 0 should be increased To decrease the sharpness setting the value pvsp srscal scale gain 11 0 should be decreased di sharpness enable Primary VSP Map Address 0xE84C 7
324. ing is performed using the frequency adaptive scaler which implements the same algorithm as the VIM down scaler A manual selection between the contour based interpolation scaler and the frequency adaptive scaler is provided by pvsp srscal interp mode 1 0 Also because ADV8005 provides 4kx2k timing 8 bit precision srscal 8bit is provided to make the entire scaler operate in 8 bit mode This lowers the power consumed by the scaler pvsp srscal interp mode 1 0 Primary VSP Map Address OxE894 7 6 This signal is used to select the scaler algorithm employed Function pvsp srscal interp mode 1 0 Description 00 default Automatic scaler algorithm selection 01 Contour based interpolation scaler 2nd gen scaling algorithm with 4k x 2k support 10 Frequency adaptive scaler 1st gen scaling algorithm 11 Bilinear scaler pvsp srscal 8bit en Primary VSP Map Address 0 890 3 This bit is used to set the scaler into 8 bit mode This bit should be set when output 4K x 2K timing Function pvsp srscal 8bit en Description 0 default Scaler not in 8 bit mode 1 Scaler in 8 bit mode The size of the active image sent to the scaler is set by pvsp di crop height 10 0 and di crop width 10 0 The scaler output can then be set using pvsp out height 12 0 and out width 12 0 by setting pvsp man out enable to 1 or it can set automatically using pvsp autocfg input vid 7 0
325. internal bitmap based OSD Customers can generate elaborate OSD designs that can include bitmap images 3D overlay and animation Up to 256 regions in total can be created and displayed These 256 regions are bitmap images defined during the design stage and can be characters pictures buttons and so on Individual regions can be alpha blended and prioritized versus other regions SPI 1 DDR2 Internal OSD Generator OSD Build OSD Scaler External OSD Video 1 OSD Blend Video 2 Figure 4 ADV8005 Bitmap OSD The OSD is controlled by the host microcontroller via the ADV8005 SPI slave serial port 1 In response to commands the ADV8005 loads the data from the external SPI flash memory via the SPI master serial port 2 The ADV8005 uses DDR2 memory when rendering and blending the OSD In order to lower the load of the DDR2 memory there is a block in the ADV8005 OSD hardware called the OSD co processor The OSD co processor is responsible for handling upper level commands from the microcontroller and translating them into lower level operations for the OSD and DMA which retrieves data from the external DDR2 memories The OSD blend can be switched between either of the two video streams routed through the OSD blend block without disturbing the output video This enables seamless OSD blending in dual zone systems Bitmap 5 can be created and compiled using ADTs software development tool Blimp OSD This allows users to create their
326. interrupt ERROR INT is 1 Rev 0 Page 211 of 326 06 707 Function hdcp controller error 3 0 Description 0000 default No error 0001 Bad receiver BKSV 0010 Ri Mismatch 0011 Pj Mismatch 0100 I2C error usually no acknowledge 0101 Timed out waiting for downstream repeater 0110 Maximum cascade of repeaters exceeded 0111 SHA 1 Hash check of KSV list fail 6 10 VIDEO SETUP 6 10 1 Input Format The HDMI Tx core of the ADV8005 receives video data from the ADV8005 digital core via a 36 bit wide bus and four synchronization signals the pixel clock the data enable and the horizontal and vertical synchronization signals The HDMI Tx core always receives the video data in a 4 4 4 and SDR format from the VSP core It is possible to send YCrCb 4 2 2 data from the TMDS directly to the HDMI Tx In which case register 0 15 must be set appropriately in the Tx main map vfe input id 3 0 TX1 Main Map Address 0xEC15 3 0 This signal is used to specify the video input format Function vfe input id 3 0 Description 0000 RGB 444 or YCbCr 444 0001 YCbCr 422 0101 Pseudo 422 YCbCr Pee Pee Component Channel Y Bit 12 0 GY x GY X GY X GY x GY D X X Miis X ids X PM Cr Bit 12 0 RG X RQ X RG X RG 1 RG 1 e Figure 96 Format of Video Data Input HDMI Tx Core 6 10 2 Video Mode Dete
327. io sampling freq sel TX2 Map Address 0xF40C 7 This bit is used to select whether the audio sampling frequency is set automatically or manually via I2C Function audio sampling freq sel 0 1 default bit le Description Use sampling frequency from 125 stream for SPDIF stream Use sampling frequency from I2C registers 0 34 78 Sub frame gt 27 28 29 30 31 Aux Data LSB Audio Data v u c P Figure 98 IEC60958 Sub Stream Rev 0 Page 225 of 326 Validity c User Data Channel Status Data Parity Bit 27 31 Data LRCLK SCLK 31 Validity Flag 21 User Data Channel Status Block Start Flag Figure 99 AES3 Stream Format Input to ADV8005 LEFT RIGHT MSB DATA MSB LSB LSB LRCLK SCLK DATA LRCLK SCLK DATA 32 Clock Slots 32 Clock Slots Figure 100 Timing of Standard I2S Stream Input to ADV8005 Rev 0 Page 226 of 326 LEFT RIGHT lt MSB xX MSB X MSB XMSB 1 LSB
328. ion pvsp vim d scal out width Description 10 0 0x000 default Default 0 Output width of VIM scalar 3 2 2 3 Scaler Interpolation Mode This section describes the method for scaling the input video data The purpose of the scaler is to allow different input formats to be displayed on a screen with a fixed resolution The VIM scaler is usually used for downscaling for example 1080p to be downscaled to a lower definition format such as 480p Different scaling interpolation modes will affect scaler performance The options for video scaling modes are described below and are chosen using pvsp vim scal type 1 0 Proprietary ADI Algorithm This is a custom algorithm developed by ADI which allows improved performance in the scaling of the input video This can reduce many common artifacts when scaling video data such as e tooth otherwise known as jaggies this is an artifact that occurs when an image is zoomed in and is one of the most important criteria when evaluating scaling performance e Edge blurring when zooming in most high frequency information is lost resulting in edges becoming blurred The proprietary ADI algorithm keeps the edge region sharp by retaining the high frequency information e Ringing also known as the Gibbs phenomenon can be found on video due to a reduction in high frequency information The proprietary ADI algorithm helps with the reduction of such artifacts Sharp Smooth Both the sharp smooth o
329. ion is enable and manual values selected Rev 0 Page 81 of 326 06 707 Function hs end pos 9 0 Description OxXX release hs when hcount reaches OxXX vs beg o pos 10 0 IO Map Address 0x1B91 2 0 Address 0x1B92 7 0 This signal is used to specify the horizontal beginning position of VS for odd fields counting from the EAV if CEA 861 timing generation is enable and manual values selected Function vs h beg o pos 10 0 Description OxXX assert vs when hcount reaches on odd fields vs h beg e pos 10 0 IO Map Address 0x1B93 7 0 Address 0x1B94 7 5 This signal is used to specify the horizontal beginning position of VS for even fields counting from the EAV if CEA 861 timing generation is enable and manual values selected Function vs h beg e pos 10 0 Description OxXX assert vs when hcount reaches on even fields vs beg pos 5 0 IO Map Address 0x1B94 3 0 Address 0x1B95 7 6 This signal is used to specify the vertical beginning position of VS if CEA 861 timing generation is enable and manual values selected Function vs v beg pos 5 0 Description OxXX assert vs when Icount reaches OxXX vs v end 5 0 IO Map Address 0x1B95 5 0 This signal is used to specify the vertical ending position of VS if CEA 861 timing generation is enable and manual values selected Function vs v end pos 5 0 Description OxXX release vs when Icount reaches OxXX worked exa
330. is section documents the register bits used for resetting various sections of the ADV8005 These resets can be used by the system controller to reset individual sections of the device without having to reset the whole part If the whole device needs to be reset this can be implemented by setting the global reset main reset these register bits are self clearing which means that when set to 1 they are set back to 0 after the appropriate section has been reset Refer to Section 6 2 for more information on the reset strategy for the HDMI Tx svsp reset IO Map Address 0x1AFD 7 Self Clearing This bit is used to reset the Secondary VSP Function svsp reset Description 0 default Default 1 Reset Rev 0 Page 76 of 326 pvsp reset IO Map Address 0x1AFD 6 Self Clearing This bit is used to reset the Primary VSP U6 707 Function pvsp reset Description 0 default Default 1 Reset p2i reset IO Map Address 0x1AFD 5 Self Clearing This bit is used to reset the Progressive to Interlaced core Function p2i reset Description 0 default Default 1 Reset ddr2 intf reset IO Map Address 0x1AFD 4 Self Clearing This bit is used to reset the external DDR memory interface core Function ddr2 intf reset Description 0 default Default 1 Reset spi reset IO Map Address Ox 1AFD 3 Self Clearing This bit is used to reset the SPI hardware both master and slave Fu
331. itter variants of ADV8005 are the following lt lt ADV8005KBCZ 8A lt lt ADV8005KBCZ 8N e ADV8005KBCZ 8C The single transmitter variant of the ADV8005 is the ADV8005KBCZ 8B Keys Tx Video Path Video data Video data 23 3 Cho 9 0 5 3 po Data 35 0 xi 23 0 n Black Pry TX Ts Chi 9 Serializer and HS Simplified gt COLOR HDCP HDMI Encode Drivers o TX1 gt 444 2 422 eal gt Packet Builder Encryption vs enable Che 9 0 TX2 oO DE Audio data Aldi gt LTO 2 2 e 8 AVI vid Tx x HS z Audio Receiver TMDS PLL Format 6999 Audio data 8 0 vs Detect gt repitition gt p 12C AUD IN 5 0 SCLK MCLKIN Figure 95 Functional Block Diagram of HDMI Tx Core As the two ADV8005 HDMI transmitters can be configured independently there are separate register maps for both the HDMI Tx1 and HDMI Tx2 The addresses for these register maps are listed in Table 42 Table 42 HDMI Transmitter Memory Addresses Register Map Register Map Address HDMI Tx1 Main Map OxECOO OxECFF HDMI Tx1 EDID Map 0 00 OxEEFF HDMI Tx1 UDP Map OxF200 OxF2FF HDMI Tx1 Test Map OxF300 OxF3FF HDMI Tx2 Main
332. ization TAA Nertical Blanking Interval 7 455 SD Subcarrier Frequency Control 7 4 5 Programming the FSC c scd NIU 7 4 6 SD Non Interlaced Mode 240 p 288p ias TAT ve mau tM vr aM 745707 o ED HD 7 4 8 ED HD Test Pattern Generatoriai TAS Color Space Conversion 7 4 10 ED HD Manual CSC Matrix Adjust Feature 7 4 10 1 Programming the MatriX 7 4 11 5 Luma and Color Scale Control esent A R R A 7422 3SE Hue Adjust CODtIol ott te etm ema umm tm 7 4 13 SDBrighthess D tectz ooi ee e R HERE e DRE EUR e e REED RS ERG He DEG 7 4 14 SD Brightness Control 7 4 15 Double oe e eat ttti 7 4 15 1 ED HD Doubling Buffering s i 7 4 15 2 SD Doubling B ffering 7 4 16 Programmable DAC Gain Control 7 4 17 Gamma Correc toi 7 4 17 1 ED EHD Gamma COFteCtion 7 4 17 2 5 EM CC DD 7 4 18 ED HD Sharpness Filter and Adaptive Filter Controls 7 4 18 1 ED E
333. l 01 10 bits per channel 10 12 bits per channel 11 16 bits per channel not supported Notes Rev 0 Page 189 of 326 06 707 e Deep color mode be monitored via the deepcolor mode chng edge sensitive interrupt in the IO Map which indicates if the color depth of the processed stream has changed e ADV8005 can be configured to trigger an interrupt when the deepcolor mode chng edge sensitive interrupt in the IO Map changes from 0 to 1 5 6 VIDEOFIFO The ADV8005 contains a FIFO located after the TMDS decoding block refer to Figure 92 Data arriving into the Serial Video Rx will be at 1X rate for non deep color modes 8 bits per channel and 1 25X 1 5X or 2X for deep color modes 30 36 and 48 bits respectively Data unpacking and data rate reduction must be performed on the incoming data to provide the ADV8005 digital core with the correct data rate and data bit width The video FIFO is used to pass data safely across the clock domains TMDS Clock PLL T R TMDS 0 TMDS TMDS gt gt and Channel 1 Data TMDS Channel2 Figure 92 HDMI Video FIFO The video FIFO is designed to operate completely autonomously It automatically resynchronizes the read and write pointers if they are about to point to the same location However it is also possible for the user to observe and control the FIFO operation with a number of FIFO control and status registers describe
334. l SDRAM is 2Gbit word size 3 0 IO Map Address 0x1A5C 7 4 This signal is used to specify the word size on the user interface The data width to the SDRAM is half of this value All other values are reserved Function word size 3 0 Description 0010 32 bits 0011 default 64 bits burst length 2 0 IO Map Address 0x1A5D 1 0 Address Ox1ASE 7 This signal is used to indicate the burst length of the read write transaction Function burst length 2 0 Description 010 default Burst of 4 011 Burst of 8 rw ctr oe sets the direction for several of the pins on the DDR2 memory interface By default these pins are set to input However when set to 1 this bit enables these pins to be outputs Likewise when ddr2 ck oe is set to 1 the DDR2 clock pin becomes an output rw ctr oe Map Address 0 1 8 7 This bit is used to control the output enable for external memory read write signals ras cas clock address Rev 0 Page 68 of 326 06 707 Function rw ctrl oe Description 0 default Input 1 Output ddr2 ck oe IO Map Address 0 1 8 6 This bit is used to control the output enable for external memory clock signal Function ddr2 ck oe Description 0 default Input 1 Output PLL clock generator for the DDR2 memory interface be set to a user defined frequency over the range of 200 to 250MHz by setting the plldll sel div 5 0 and th
335. l be an integer frame latency from input to output If frequency locked is selected there could be a non integer frame latency number from input to the output Selecting phase error latency is the recommended setting Frame tracking results in an integer ratio relationship between the input and output frame rates of 1 1 2 1 1 2 5 2 or 2 5 For example if scaling from 1080p30 to 720p59 94 with frame tracking enabled the resulting output may be 720p60 due to the 1 2 relationship Frame rate tracking is primarily intended for cases where the input frame rate and output frame rate have a 1 1 relationship or are close to this target that is 59 94 Hz to 60 Hz However it can also be used for some standard frame rate conversion modes such as 24 Hz to 60 Hz 25 Hz to 50 Hz and 30 Hz to 60 Hz The list of scaling conversions where frame tracking can be enabled is covered in Table 5 Table 5 Frame Tracking Output Frame Rate 23 97 Hz 24Hz 25Hz 29 97 Hz 30Hz 50Hz 59 94 Hz 60 Hz 4 23 97 2 5 5 5 Yes 5 24 Hz Yes Yes No No No No Yes Yes 9 25 Hz No No Yes No No Yes No No 5 29 97 Hz No No No Yes Yes No Yes Yes t 30 Hz No No No Yes Yes No Yes Yes 50 2 5 5 59 94 Hz Yes Yes No Yes Yes No Yes Yes 60 Hz Yes Yes No Yes Yes No Yes Yes pvsp track en is set to enable frame tracking for the PVSP svsp track en is set to enable frame
336. laced Buffers MOTION _ BUF _ SIZE byte pvsp_motionbuf0_addr 31 0 Primary VSP Map Address 0xE818 7 0 Address OxE819 7 0 Address OxE81A 7 0 Address OxE81B 7 0 This signal is used to set the start address of motion information buffer 0 Motion buffers are needed only when motion adaptive deinterlacing is enabled for interlaced input Function pvsp motionbufO addr 31 0 Description 0x00000000 default Default OxXXXXXXXX Start address of motion buffer 0 pvsp motionbufl addr 31 0 Primary VSP Map Address 0xE81C 7 0 Address OxE81D 7 0 Address OxE81E 7 0 Address OxE81F 7 0 This signal is used to set the start address of motion information buffer 1 Motion buffers are needed only when motion adaptive deinterlacing is enabled for interlaced input Function pvsp motionbuf1 addr 31 0 Description 0x0007E900 default Default OxXXXXXXXX Start address of motion buffer 1 3 2 3 4 Low Angle De interlacing The ultra low angle de interlacing interpolation algorithm ULAI developed by ADI performs intra field interpolation for the de interlacing function It is capable of determining the correct direction by examining several different directions and interpolating missing pixels based on this information This results in higher quality low angle interpolation and reduces the effect of jaggies The ultra low angle interpolation function is only used for converting from interlaced to progressive forma
337. ld be downscaling to video modes with pixel clocks of less than 162MHz e g 4K 30 to 1080p 60 2 Up conversion of video standards with pixel clocks greater than 162MHz and or more than 1920 pixels line but less than 3840 to video modes with pixel clocks greater than 162MHz e g VESA 2048x1152 162MHz to 4K VESA 1920x1440 234MHz to 4K 3 Conversion of video standards with pixel clocks greater than 162MHz and more than 3840 pixels lines Typical use would be converting between different 4K timings e g 4 924 to 4 24 SMPTE 4 3Dto2D conversion of some video modes 5 Bypassing the downsampling block within the HPS be used just as an additional high frequency filter to the one provided by the P SVSP Video may be routed in to the HPS from any of the ADV8005 inputs using hps inp sel The output from the HPS can be routed to either the PVSP or to the SVSP using inp sel 3 0 and svsp inp sel 3 0 hps inp sel 3 0 IO Map Address 0x1A09 7 4 This signal is used to select the video source for the Horizontal pre scaler HPS block Rev 0 Page 160 of 326 06 707 Function hps inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Secondary Input Channel 0x02 From RX Input 0x03 From Internal OSD Blend 1 data in 35 0 de in in vs in i2c hps bypass 2 1 Video Downsample Antialiasing data out 35 0 YCbCr de Filter agi vs out i2c bypass downsampl
338. ll reset IO Map Address OxLAFE 2 Self Clearing This bit is used to reset the DPLL clock generator Function reset Description 0 default Default 1 Reset xtal reset IO Map Address 0 1 0 Self Clearing This bit is used to reset all the clocks in the device and peripheral logic in the core including the interrupt generator and the automatic clock selection Function xtal reset Description 0 default Default 1 Reset main reset IO Map Address 0x1BFF 7 Self Clearing This bit is used to initiate a global reset for the device Function main reset Description 0 default Default 1 Reset 2 2 10 Image Processing Colorimetry Breakdown The ADV8005 performs its image processing in the YUV format except for the internal OSD which is generated in RGB The internally generated OSD is muxed with the external OSD which can be in either YUV or RGB before being input into a CSC The CSC converts all input signals into YUV format for input into the OSD video blend block Rev 0 Page 78 of 326 External OSD In YUV RGB De interlacer and Cadence Detection YUV Motion Detection Low Angle Processing Cadence Detection Cue Correction M OSD Video Blend YUV Video Enhancement YUV Reduction Mosquito Noise Reduction Block Noise Reduction Detail Enhancement Kee Fore te es F
339. llary data bytes All of the ancillary data packets must be encoded including the preamble A high to low transition on the VBI CS line indicates the start of a new byte As the bytes are directly encoded ancillary data the same decoder described in Section 2 2 8 2 for ancillary data can be used to extract the VBI data Only modes 0 and 3 are supported by the SPI slave and therefore the SPI master must use one of these modes 2 2 8 4 VBI Data Delay Once the VBI data has been decoded for each of the supported standards it is latched and delayed by the desired amount The delay on the VBI data is measured in frames and is controllable in the range 0 lt delay lt 3 frames The data can be delayed on either the rising or falling edge of the input VSync The output VBI data is muxed directly with the VBI data from the encoder register map before being output by the encoder vbi src IO Map Address 0x1A4C 7 This bit is used to choose the source of the VBI data Function vbi src Description 0 default VBI data from ancillary input 1 VBI data from SPI input odd en IO Map Address 0x1A4C 3 This bit is used to enable disable closed caption data extraction on the odd field Rev 0 Page 75 of 326 06 707 Function ccap odd en Description 0 default Disable closed caption data extraction on odd field 1 Enable closed caption data extraction on odd field ccap even en IO Map Address 0x1A4C
340. llowing sections are a guide for designing a board using the ADV8005 Analogue Digital Video Interface Outputs The HDMI TMDS trace pairs must have a 1000 differential impedance and should be routed in the shortest trace length possible to minimize the possibility of cross talk with other signals The HDMI TMDS trace pairs must be routed on the same side of the PCB as the ADV8005 and should not be routed through vias to any other layers A solid plane must be maintained underneath the HDMI TMDS trace pairs for their full trace length Any external ESD suppressors should be placed as close as possible to the HDMI connector to reduce the impact on impedance TDR measurements If the ADV8005 is to support 3 GHz signals from the HDMI Txs it is recommended the TMDS trace widths are set to 0 2 mm The spacing of the traces the height of the copper and the trace s height above the ground plan should all be controlled to maintain the trace impedance with this trace width The encoder analog outputs must have a 750 characteristic impedance and should be routed in the shortest trace length possible to minimize the possibility of cross talk with other signals To assist in reducing cross talk ground traces can be added between adjacent encoder analog outputs The encoder analog outputs must be routed on the same side of the PCB as the ADV8005 and should not be routed through vias to any other layers A solid plane must be maintained underneath the encoder analog
341. lowing actions are taken e In read mode the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse e In write mode the data the invalid byte is not loaded into any subaddress register no acknowledge is issued by the ADV8005 and the part returns to the idle condition SDA SCL Device Address fi Regie Address MSBs _ Register Address LSBs 1 1 1 1 1 1 1 1 1 f 9 1 8 fs 9 225 RW ACK ACK ACK Figure 8 Bus Data Transfer Device Register Register Data Data Address AG Address MSBs A Address LSBs AG AG AMS Device Register Register Device Data _ s Address A S Address MSBs A S Address LSBs AMS 5 Address AM S Start Bit A S Acknowledge by Slave A S Acknowledge by Slave P Stop Bit A M Acknowledge by Master A M Acknowledge by Master 1 4 CONFIGURING THE ADV8005 The ADV8005 requires a number of configuration settings for each mode of operation To ensure the part is correctly configured refer to either the recommended settings configuration script supplied with the ADV8005 evaluation software or the reference software
342. lse Code Modulation Mbps Megabit per Second MNR Mosquito Noise Reduction Rev 0 Page 10 of 326 Acronym Abbreviation Description MPEG Moving Picture Expert Group ms Millisecond MSB Most Significant Bit NC No Connect NSV Noise Shaped Video OSD On Screen Display OTP One Time Programmable Ptol Progressive to Interlaced Pj HDCP Enhanced Link Verification Response Refer to HDCP documentation PVSP Primary VSP Ri HDCP Link verification response Refer to HDCP documentation RNR Random Noise Reduction Rx Receiver SA Slave Address SAV Start of Active Video SD Standard Definition SDP Standard Definition Processor SDR Single Data Rate SMPTE Society of Motion Picture and Television Engineers SNR Signal to Noise Ratio SOG Sync on Green SOY Sync on Y SPA Source Physical Address SPD Source Production Product Descriptor SPDIF Sony Philips Digital Interface SPI Serial Peripheral Interface SRM System Renewability Message SSPD Synchronization Source Polarity Detector STDI Standard Identification SVSP Secondary VSP TBC Timebase Correction TMDS Transition Minimized Differential Signaling Tx Transmitter ULAI Ultra Low Angle Interpolation US Up Sampling VBI Video Blanking Interval VDP VBI Data Processor VIC Video Identification Code VIM Video Input Module VOM Video Output
343. lt VERTICAL RESOLUTION OUTPUT BY VIM 3 2 3 3 Motion Detection The ADV8005 de interlacer is used to convert interlaced video to progressive video The PVSP has an extremely high quality de interlacer algorithm which achieves excellent quality interlaced to progressive conversion The algorithm uses motion adaptive de interlacing technology which includes motion detection cadence detection low angle detection and interpolation Motion detection extracts the motion information of each pixel Based on this information the ADV8005 chooses the most suitable form of Rev 0 Page 122 of 326 06 707 de interlacing For static pixels that is pixels where no motion is deemed to have occurred inter field interpolation is performed For pixels where motion is detected intra field interpolation is performed Motion detection technology is the essence of de interlacing so if a static pixel is detected as motion by mistake vertical detail is lost In contrast if motion is detected as static by mistake combing artifact occurs In order to support motion detection for interlaced inputs two buffers in external memory are needed to store motion information Their addresses are defined in the pvsp_motionbuf0_addr 31 0 and pvsp motionbufl addr 31 0 registers The size of each buffer should be equal to the MOTION BUF SIZE which can be calculated from Equation 20 active input video widthxactive input video _ height 4 Equation 20 Calculating Inter
344. mended to the user as best practice for updating VSP registers The appropriate protocol should be used depending on the current status of the device The seamless transfer of the VSP between standards can be achieved by using the bootup protocol reboot protocol gentle reboot protocol and VOM set protocols If not changing VSP registers in real time the free access protocol can be used 3 4 1 Bootup Protocol The bootup protocol is used to configure the PVSP or SVSP from a reset state All registers can be accessed using this protocol Rev 0 Page 155 of 326 06 707 pvsp enable ffs 0 pvsp enable vim 0 pvsp enable vom 0 pvsp lock vom 0 pvsp update vom 1 Configure all registers mm arabia far pvsp enable vim 0 pvsp enable vom 0 pvsp lock vom 0 pvsp update vom 1 Enable FFS by assert pvsp enable ffs pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 0 pvsp lock vom 0 V te vom 1 Enable VIM by assert En DE pvsp enable vim pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 pvsp lock vom 0 pvsp update vom 1 Enable VOM by assert pvsp enable vom Figure 69 Bootup Protocol Flowchart Figure 69 shows the process for the bootup protocol for the PVSP This is exactly the same for the SVSP with the appropriate registers replaced 3 4 2 Reboot Protocol The reboot protocol is used to reset the PVSP and configure it again using different settings especially different input timing or o
345. mma A and gamma B curves and the ED HD CGMS registers 7 4 15 2 SD Doubling Buffering db en Encoder Map Address 0xE488 2 This bit is used to enable double buffering on the appropriate SD registers Function db en Description 1 Enabled 0 default Disabled Double buffering can be activated on the following SD functions the SD gamma A and gamma B curves SD Y scale SD Cr scale SD Cb scale SD brightness SD closed captioning and SD Macrovision bits Reg OxEAEO Bits 5 0 Rev 0 Page 267 of 326 06 707 7 4 16 Programmable DAC Control It is possible to adjust the DAC output signal gain up or down from its absolute level This is illustrated in Figure 119 CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS SUBADDRESS 0x0A 0x0B 700mV D CASEB NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS SUBADDRESS 0x0A 0x0B 700mV 300mV D D Figure 119 Programmable DAC Gain Positive and Negative Gain 06398 070 In Case A of Figure 119 the video output signal is gained The absolute level of the sync tip and the blanking level increase with respect to the reference video output signal The overall gain of the signal is increased from the reference signal In Case B of Figure 119 the video output signal is reduced The absolute level of the sync tip and the blanking level decrease with respect to the reference video output signal The overall gain of the signal i
346. mple showing how 720 1440 x 240p can be supported using manual AV code configuration is shown Figure 42 The horizontal measurements must be the following de h beg pos 9 0 276 2 138 0010001010 de beg pos 6 0 22 0010110 de beg e pos 6 0 22 0010110 hs beg pos 9 0 38 2 19 0000010011 hs end pos 9 0 162 2 81 0001010001 vs v beg pos 5 0 4 000100 vs h beg o pos 10 0 38 2 19 00000010011 vs h beg e pos 10 0 38 2 19 00000010011 vs v end pos 5 0 7 000111 Rev 0 Page 82 of 326 06 707 1716 Total Horizontal Clocks per 216 1440 Clocks for Active Video 124 38 gy 114 clocks hs beg pos 38 vs h beg o pos 38 vs h beg e 38 mode 1 22 Vertical Blanking Lines 1 Data Enable 1 i 1716 clocks 38H 240 Active Vertical Lines per field Frame mode 2 23 Vertical Blanking Lines 240 Active Vertical Lines per field 1 Data Enable 1 dev bes 53 a8 1716 clocks 7 21 22 201 202 1 Figure 42 720 1440 x 240p 59 94 60Hz CEA Formats 8 and 9 2 2 12 Color Space Conversion Although all processing in the ADV8005 is performed in the YCbCr color space the part is capable of receiving video in the RGB and YCbCr color spaces ADV8005 provides any to any CSC on each of the inputs and on both of the outputs five color space converters in all All C
347. n Function brightness 7 0 Description Ox7F 127 8 0x00 default No adjustment 8 OxFF 1 8 brightness 8 Figure 32 Brightness Processing saturation 7 0 IO Map Address 0x1A29 7 0 This register is used to adjust the saturation value for U V channels The register uses 1 7 notation Function saturation 7 0 Description 0x00 Gain of 0 0x80 default Unity Gain OxFF Gain of 2 blank level u 11 0 IO Map Address 0x1A26 7 0 Address 0x1A27 7 4 This signal is used to adjust the blank level of u input to the vid adjust block Rev 0 Page 55 of 326 06 707 Function blank level u 11 0 Description 0x000 blank level sits at code 0 0x800 default u blank level sits at code 2048 decimal blank level v 11 0 IO Map Address 0x1A27 3 0 Address 0x1A28 7 0 This signal is used to adjust the blank level of v input to the vid adjust block Function blank level v 11 0 Description 0x000 v blank level sits at code O 0x800 default v blank level sits at code 2048 decimal u v in Out blank level u v saturation blank level u v Figure 33 Saturation Processing Refer to Section 2 2 12 1 for more information on the CSC controls for the primary input channel Refer to Section 3 2 3 16 for more information on the ACE controls for the primary input channel 2 2 2 7 Secondary Input Channel The ADV8005 secondary input channel incor
348. n 0 default Disable bypass 1 Enable bypass The primary input path features contrast brightness and saturation controls All contrast brightness and saturation controls contrast 9 0 brightness 7 0 saturation 7 0 blank level y 11 0 blank level u 11 0 and blank level v 11 0 are doubled buffered on VSync The contrast 9 0 value has a range of 0 to 1 992 Refer to Figure 31 for more information on how the contrast controls influence the video signal The brightness 7 0 value has a range of 1024 to 1016 Refer to Figure 32 for more information on how the brightness controls influence the video signal Rev 0 Page 54 of 326 06 707 The saturation 7 0 value has range 0 to 1 992 Refer to Figure 33 more information on how the saturation controls influence the video signal contrast 9 0 Encoder Map Address OxE49D 7 0 Address OxE49C 1 0 This signal is used to set the SD Y scale value blank level y 11 0 IO Map Address 0x1A24 3 0 Address 0x1A25 7 0 This signal is used to adjust the blank level of y input to the vid adjust block Function blank level y 11 0 Description 0x000 y blank level sits at code 0 0x100 default y blank level sits at code 256 decimal y in y out blank level y contrast blank level y Figure 31 Contrast Processing brightness 7 0 IO Map Address 0x1A2A 7 0 This register is used to adjust the brightness value for Y channel The register uses s1 6 notatio
349. n svsp track offset 20 0 Description 0 default input and output vsync coincident 1 1 clk between input nad output vsync 3 7 PROGRESSIVE TO INTERLACED CONVERSION ADV8005 has two progressive to interlaced converters 21 The primary P2I converter is an independent block to which the PVSP OSD and inputs can be connected The primary P2I converter convert from any progressive format to its interlaced equivalent The input to the primary P2I converter is selected by p2i inp sel 3 0 The secondary P2I converter is connected directly to the SVSP The secondary P2I converter cannot convert from 1080p to 1080i but can handle all other progressive to interlaced conversions p2i inp sel 3 0 IO Map Address 0x1A06 7 4 This signal is used to select the video source for the Progressive to Interlaced converter Function p2i inp sel 3 0 Description 0x00 From Primary VSP 0x01 From Internal OSD Blend 1 0x02 From EXOSD TTL Input 0x03 From RX Input 0x04 From Video TTL Input Rev 0 Page 169 of 326 06 707 4 SCREEN DISPLAY 4 1 INTRODUCTION The On Screen Display OSD core in the ADV8005 allows the user to overlay a bitmap based OSD onto one of the input video streams The OSD blend is capable of being performed at data rates up to 3 GHz The OSD can be designed using the ADI Blimp software tool This code generating tool may be used to design simulate and compile the OSD which will
350. n spi1 mosi ie Description 0 default input path disable 1 input path enable spil sclk ie IO Map Address 0x1BD3 4 This bit is used to control the input path enable for the spil SCLK pin Function 6 1 sclk ie Description 0 default input path disable 1 input path enable spi2 cs ie IO Map Address 0x1BD3 3 This bit is used to control the input path enable for the spil CS pin Function Spi2 cs ie Description 0 default input path disable 1 input path enable spi2 miso ie IO Map Address 0x1BD3 2 This bit is used to control the input path enable for the spi2 OSP pin Function 2 miso ie 0 default 1 Description input path disable input path enable spi2 mosi ie IO Map Address Ox1BD3 1 This bit is used to control the input path enable for the spi2 MOSI pin Function Spi2 mosi ie Description 0 default input path disable 1 input path enable spi2 sclk ie IO Map Address Ox1BD3 0 This bit is used to control the input path enable for the spi2 SCLK pin Function Spi2 sclk ie Description 0 default input path disable 1 input path enable mas clk ie IO Map Address 0 1 4 2 This bit is used to control the input path enable for the master CLK pin Function mas clk ie Description 0 default input path disable 1 input path enable mas hs ie IO Map Address Ox1BD4 1 This bit is used to control t
351. n edge regions of interlaced video e Cadence detection any cadence detection possible e Progressive cadence supported e Super resolution video scaler e Aspect ratio conversion panorama scaling e Arbitrary upscaling and downscaling for both horizontal and vertical direction e Sharpness detail and edge enhancement e Noise reduction for random mosquito and block noise e Frame Rate Conversion e Color Upsampling Error CUE correction e Progressive to interlaced PtoI converter Game mode supported e Album mode supported e Demo window 1 2 1 2 Horizontal Pre Scaler e 8 bit internal processing e Downscales video standards of greater than 162MHz and or more than 2048 pixels line 1 2 1 3 Secondary VSP e 8 bit internal processing e Input and output timing up to 1080p e Input and output format YCbCr at 4 4 4 e Up scaling and down scaling for both horizontal and vertical direction e Aspect ratio conversion and panorama scaling e Frame Rate Conversion e Progressive to interlaced PtoI converter 1 2 2 OSD e Internally generated bitmap based OSD allowing overlay of bitmap images on one or more video outputs e Dual video paths through the OSD blend block to support dual zone OSD Dedicated OSD scaler allows OSDs to be rendered at a single resolution reducing external memory bandwidth e Blending onto 3 GHz video formats e Pixel by pixel alpha blending of OSD data on video data e Option of externally gener
352. n parallel mode The location of the OSD blend core must then be selected This can be placed before the PVSP and both the input video and OSD can be scaled at the same time However depending on the application the optimal solution may be to have both the input video and OSD scaled separately and then blended If blending the OSD after the PVSP the OSD may need to be scaled to different resolutions This can be done in two ways 1 OSD bitmap images are created at higher resolutions 2 OSD can be rendered at single resolution and scaled internally in the ADV8005 using the OSD scaler There are limitations to both of these methods Rendering OSDs at larger resolutions increases the system resources required to store these bitmaps Alternatively scaling the OSD internally in the part increases power consumption on the ADV8005 The optimum solution to this depends on customer requirements and system capabilities It should be chosen taking these considerations into account Note For the following modes of operation red indicates an active video path and black indicates a path is not used If for example there are two red dashed lines video may be available on one or the other but not on both 2 1 2 Mode 1 Mode 1 should be used if e Three separate output formats are required e Additional processing BNR RNR and so on is required on the new output formats e OSD is required on a single output format most likely the
353. n the ADV8005 is designed to tune the ADC sampling phase in a device with an analog front end such as the ADV7850 ADV7844 or ADV7842 Figure 48 shows a system view of how the ADV8005 implements autoposition and phase Figure 49 shows a block diagram of how the ADV8005 interfaces with the system software to tune the analog front end device the ADV7850 For the autophase the software driver cycles through each of the ADV7850 ADC sampling phases The ADV8005 analyzes the input video timing and then rb auto ph right phase 5 0 indicates the best sampling phase to use The software routine required to implement this routing is decribed in Figure 50 Rev 0 Page 98 of 326 06 707 Select TTL RX input CSC input used for Set the number Enable auto auto phase of phases phase 10 OX1BEO 7 6 10 map OX1BEO 5 10 0 1 1 6 0 10 map OX1BE1 7 map 0 1 0 Reset auto phase Scan current phase yes Write current Phase to ADV7850 CP DLL PHASE AFE map OxC8 Read Statistical Write current Phase to 10 map scan result for phase AUTO SCAN OX1BE2 5 0 IO map no Ox1BEA Ox1BE5 0 1 6 10 map OX1BE3 7 Read Best Phase IO map Ox1BE3 5 0 Write Best Phase to CP Write Best Phase to uus SUC DLL_PHASE AUTO_PH_SCAN RE ADV7830 10 map OX1BE2 ADV8005 write 4 OxC8 Fis a ge A ae 3
354. n the control of the VIM scaling function and should be tailored according to user requirements Anti alias filters are provided to improve the performance of the SVSP downscaling and can be enabled using vim anti alias en and svsp vim scal anti alias v en svsp vim scal anti alias en Secondary VSP Map Address OxE650 5 This bit is used to enable the anti aliasing filter for horizontal direction Function svsp vim scal anti alias h e Description n 0 Disable 1 default Enable svsp vim anti alias v en Secondary VSP Map Address OxE650 6 This bit is used to enable anti aliasing filter for vertical direction Function svsp vim scal anti alias v e Description n 0 Disable 1 default Enable svsp vim type 1 0 svsp vim scal anti alias h en and vim scal anti alias v en be manually set These settings take effect only when svsp man scaler para enable is set to 1 otherwise they can be automatically configured by the SVSP using svsp autocfg input vid 7 0 and svsp autocfg output vid 7 0 svsp scaler para enable Secondary VSP Map Address 0 662 4 This bit is used to enable manually setting scaler parameters Function svsp man scaler para enabl Description e 0 default Disable 1 Enable When a picture is zoomed in it is possible to maintain the original high frequency content However maintaining thi
355. n this section is just provided so the user can find a suitable SPI flash memory which can be interfaced to the ADV8005 SPI master interface The SPI master is designed to be compatible with the M25P16 and supports the FAST READ command The SPI master clock can be configured to support up to 80 MHz The SPI master similar to the slave can support the following modes CPOL 0 CPHA 0 CPOL 0 CPHA 1 e CPOL 1 CPHA 0 e CPOL 1 CPHA 1 Figure 90 shows the effect that these settings may have on the data CPOL CPHA 0 5 2 H n 0 1 2 1 0 5 2 1 1 2 im bii D B Instruction 0x0B ple 24 bit Address gt lt ummy Byte gt MOSI2 23 221211 13 21 111 0 7 6 51 41 31 2111 0 le Data out 1 gt lt Data out 2 MISO2 7 6 5 4 31 2 1 01 7 6 514131 2 1 0 Figure 90 SPI Master Interface Timing and Data Format The CPOL CPHA can be configured through the following registers spi master cpol IO Map Address 0x1A14 1 This bit is used to select the SPI master clock polarity Rev 0
356. nction spi reset Description 0 default Default 1 Reset sys reset IO Map Address 0x1AFD 2 Self Clearing This register bit resets the clock for the digital core Function sys clk reset Description 0 Default 1 Reset osd reset IO Map Address 0x1AFD 1 Self Clearing This bit is used to reset the OSD core and the secondary input channel Function osd reset Description 0 default Default 1 Reset inp reset IO Map Address 0x1AFD 0 Self Clearing This bit is used to reset the input capture and formatting logic for the primary input channel Function inp sdr reset Description 0 default Default 1 Reset rx reset IO Map Address Ox1AFE 7 Self Clearing This bit is used to reset the Serial Video RX core and the RX input channel Rev 0 Page 77 of 326 06 707 Function rx reset Description 0 default Default 1 Reset enc reset IO Map Address Ox1AFE 6 Self Clearing This bit is used to reset the HD and SD encoders Function enc reset Description 0 default Default 1 Reset tx2 reset IO Map Address Ox1AFE 5 Self Clearing This bit is used to reset the HDMI TX2 Function tx2 reset Description 0 default Default 1 Reset tx1 reset IO Map Address Ox1AFE 4 Self Clearing This bit is used to reset the HDMI Function tx1 reset 0 default 1 Description Default Reset dp
357. ncy Register 3 The reason for this is because the subcarrier frequency only updates when Subcarrier Frequency Register 3 has been updated The SD input standard autodetection feature sd autodetect en must be disabled The registers to be programmed are described below fsc 31 0 Encoder Map Address OxE48F 7 0 Address OxE48E 7 0 Address OxE48D 7 0 Address OXE48C 7 0 This register is used to set the subcarrier frequency value Table 71 outlines the values that should be written to the subcarrier frequency registers for NTSC and PAL B D G H I Table 71 Typical Fsc Values Register Description NTSC PAL B D G H I 0 48 OxCB OxE48D 0 8 OxE48E 0x09 OxE48F Fsc3 0x21 Ox2A 7 4 6 SD Non Interlaced Mode 240p 288p The ADV8005 encoder core supports an SD non interlaced mode Using this mode progressive inputs at twice the frame rate of NTSC and PAL 240p 59 94 Hz and 288p 50 Hz respectively can be input into the ADV8005 encoder If the user selects the input to be 240p or 288p sd non interlaced must be set correspondingly Refer to Section 7 2 for more details on setting the input format sd non interlaced Encoder Map Address OxE488 1 This bit is used to enable the support of SD non interlaced modes Function sd non interlaced Description 1 Enabled 0 default Disabled Note All input configurations output configurations and features available in NTSC and PAL modes are available in SD non int
358. nd thold c 7 0 are described below The recommended threshold range is 16 to 235 although any value in the range of 0 to 255 can be used thold 7 0 Encoder Map Address 0xE45B 7 0 This register is used to set the ED HD adaptive filter threshold A thold b 7 0 Encoder Map Address 0xE45C 7 0 This register is used to set the ED HD adaptive filter threshold B thold c 7 0 Encoder Map Address OxE45D 7 0 This register is used to set the ED HD adaptive filter threshold C The edges can then be attenuated with the settings in the ED HD adaptive filter Gain 1 Gain 2 and Gain 3 registers Refer to the registers fil resp aa 3 0 fil resp ab 3 0 fil resp bb 3 0 fil resp ca 3 0 and fil resp cb 3 0 for details on setting the adaptive filter gains fil resp ab 3 0 Encoder Map Address 0xE458 7 4 This signal is used to set the adaptive filter gain 1 for the ED HD standard This is value B Rev 0 Page 274 of 326 06 707 Function fil resp ab 3 0 Description 0000 default Gain B O 0001 Gain B 1 0111 Gain B 7 1000 Gain B 8 1110 Gain B 2 1111 Gain B 1 fil resp aa 3 0 Encoder Map Address 0xE458 3 0 This signal is used to set the adaptive filter gain 1 for the ED HD standard This is value A Function fil resp aa 3 0 Description 0000 default Gain AO 0001 Gain A 1 0111 Gain 7 1000 Gain 8 1110 Gain 2 1111 Gain 1 fil resp bb 3 0 Encoder Map Address 0xE459 7
359. nel subpkt3 1 src 2 0 TX2 Main Map Address 0xF411 5 3 This signal is used to specify the source of sub packet 3 left channel Rev 0 Page 224 of 326 Function U6 707 subpkt3 src 2 0 Description 000 001 010 011 100 101 110 default 111 125101 left channel 125101 right channel 125111 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 125 3 left channel I2S 3 right channel subpkt3 src 2 0 TX2 Map Address 0xF411 2 0 This signal is used to specify the source of sub packet 3 right channel Function subpkt3 r src 2 0 000 001 010 011 100 101 110 111 default Description 125101 left channel 125101 right channel I2S 1 left channel I2S 1 right channel 125121 left channel I2S 2 right channel 125 3 left channel I2S 3 right channel 125 32bit mode TX2 Main Map Address 0xF442 3 Read Only This bit is used to readback the 125 mode detection It shows the number of SCLK periods per LRCLK period Function i2s 32bit mode Description 0 default 125 32 bit mode detected 1 125 64 bit mode detected cs bit override TX2 Main Map Address 0xF40C 6 This bit is used to select the source of channel status bits when using 125 Mode 4 Function cs bit override Description 0 default Use channel status bits from 125 stream 1 Use channel status bits programmed in I2C registers aud
360. ng VSP 1080p Input Exosd 2 Muxing Secondary 24 bit Data HDMI Input X Formatting A Tx2 1 8 5 N AA 720p 47 227 2 7 bi rimary 480p Video WE HN Daa from Pot Formatting ncoder Decoder CSC amp ACE WC lt 720p Video 720p gt Data Encoder Transceiver R Formatting amp CSC Figure 22 8005 Mode 12 Configuration Mode 12 is used to support dual zone OSD output without disturbing either video stream Using this mode two inputs for example 480p from the video TTL input port and 720p from the Serial Video Rx can be applied to the part processed and connected to the OSD core The OSD can be blended onto one or other of the two video streams and switched between the two video streams without causing any disturbance to either Rev 0 Page 38 of 326 06 707 2 1 14 Mode 13 OSD from HDMI RX Mode 13 should be used if the ADV8005 is being used in conjunction with a legacy standalone OSD generator with an HDMI interface Mode 13 DDR2 Memory HDMI Output Txi Muxing Muxing 1080p OSD 3 Input es Muxing Secondary Data Input e 4 Formatting 7 S d amp CSC JA 1080p OSD X Secondary Video 7 5 1080 36 bit Primary em Video from Input 9 Data F tti Enc
361. nly This bit is used to readback the state of the Rx sense Function rx sense state Description 0 default HDMI clock termination not detected 1 HDMI clock termination detected rx sense pd TX2 Main Map Address OxFAE6 5 This bit is used to enable the termination sense power down Function rx sense pd Description 0 default Termination Sense Monitoring Enabled 1 Termination Sense Monitoring Disabled Note rx sense pd should not be applied during the configuration of the HDMI Tx as it disables an oscillator required to complete the Rev 0 Page 204 of 326 06 707 configuration of the TMDS output clock channel It is recommended to use rx sense pd when the HDMI Tx has been completely configured 6 2 RESET STRATEGY The HDMI Tx and subsections of it can be reset in a number of ways Table 43 Error Reference source not found and Table 44 describe how each of the HDMI Tx maps are reset in response to a number of different events Table 43 HDMI Tx Main Map Reset Strategy IO Map IO Map IO Map Tx Main Map Tx Main Map Event Event txl reset Ox1AFC 7 main reset system pd OxEC98 4 Tx Hot Plug Reset Pin OxF498 4 0x00 0x91 Reset Reset Reset Reset Reset 0x92 0x97 Reset Reset Reset 0x98 OxAE Reset Reset Reset OxAF Reset Reset Reset Reset OxBE OxCF Reset Reset Reset Reset OxDO OxFE Reset Reset Reset Table 44 HDMI Tx Packet Map
362. nly Timer 7 value unit is ms timer8 cnt 31 0 SPI Device Address 0 0 TIMER Address 0x46 7 0 Address 0x47 7 0 Address 0x48 7 0 Address 0x49 7 0 Read Only Timer 8 value unit is ms timerl irq cnt 31 0 SPI Device Address 0x0B TIMER Address 4 7 0 Address 0x4B 7 0 Address 0x4C 7 0 Address 0x4D 7 0 Read Only The number of times the timer 1 interrupt was generated timer2 irq cnt 31 0 SPI Device Address 0x0B TIMER Address 0x4E 7 0 Address 0x4F 7 0 Address 0x50 7 0 Address 0x51 7 0 Read Only The number of times the timer 2 interrupt was generated timer3 irq cnt 31 0 SPI Device Address 0x0B TIMER Address 0x52 7 0 Address 0x53 7 0 Address 0x54 7 0 Address 0x55 7 0 Read Only The number of times the timer 3 interrupt was generated timer4 irq cnt 31 0 SPI Device Address 0x0B TIMER Address 0x56 7 0 Address 0x57 7 0 Address 0x58 7 0 Address 0x59 7 0 Read Only The number of times the timer 4 interrupt was generated timer5 irq cnt 31 0 SPI Device Address 0x0B TIMER Address 0x5A 7 0 Address 0x5B 7 0 Address 0x5C 7 0 Address 0x5D 7 0 Read Only The number of times the timer 5 interrupt was generated timer6 irq cnt 31 0 SPI Device Address 0x0B TIMER Address 0x5E 7 0 Address Ox5F 7 0 Address 0x60 7 0 Address 0x61 7 0 Read Only The number of times the timer 6 interrupt was generated timer7 irq cnt 31 0 SPI Device Address 0 0 TIMER Address
363. nnected to OSD input 1 is output to the OSD blend 1 output and the video stream connected to OSD input 2 is output to the OSD blend 2 output It is only possible to blend video on OSD blend 1 output or on OSD blend 2 output It is not possible to OSD blend on both at the same time The OSD can be blended onto either one of the two video streams connected to the OSD core that is there is only one source of OSD data and it must be configured to match one video stream s format and timing at a time The OSD can be switched between the two video streams without causing any disturbance on either output video stream The OSD core outputs can be connected to one or more of the output blocks for example HDMI TX1 HDMI TX2 SD encoder and HD encoder The OSD is blended with the selected video stream using alpha blending This means that each pixel of OSD has its own blending parameter which is used to blend this pixel with its corresponding background video If the OSD data is transparent the background video will be passed through and unadjusted As shown in Figure 82 the OSD data needs to be scaled to the target resolution before getting into the blending block refer to Section 4 2 7 The clock and DE of the selected video stream are used to read the scaler output data Delay is added to DATA DE HS and VS for matching the delay of the OSD processing so the OSD scaler can ensure the correct synchronization of OSD data and input video data Rev 0 Page
364. nput video image to a given image size The scaler can be used to scale a video resolution to any target resolution The pixel packer is used to pack pixels data into memory words and write them into external memory The starting address in external memory is provided by FFS and is configured by the user using the frame buffer registers As indicated at the start of Section 3 3 in order for the VIM module to operate it must first be enabled This can be done using the svsp_enable_vim bit If the VIM is disabled by setting this register to 0 the output video will be frozen 3 3 2 1 VIM Cropper The VIM cropper block is used to define a sub window within the given input resolution This cropped image will then become the video which will be processed by the SVSP The following registers are used to define this sub window e svsp vim crop enable e svsp vim crop h start 12 0 e svsp vim crop v start 12 0 e svsp vim crop width 12 0 e svsp vim crop height 12 0 To enable cropper block in VIM svsp vim crop enable must be set to 1 svsp vim crop enable Secondary VSP Map Address OxE662 6 This bit is used to enables the VIM crop Rev 0 Page 144 of 326 06 707 Function svsp vim crop enable Description 0 default Disable 1 Enable Figure 64 shows the correlation between the cropped image and the input video resolution Input Video SVSP VIM CROP V START Cropped Image SVSP VIM CROP H START SVSP VIM CR
365. nse These can be configured using luma filter sel 2 0 luma filter sel 2 0 Encoder Map Address 0xE480 4 2 This signal is used to configure the luma filters for SD data Function luma filter sel 2 0 Description 000 LPF NTSC 001 LPF PAL 010 Notch NTSC 011 Notch PAL 100 default SSAF Luma 101 Luma CIF 110 Luma QCIF 111 Reserved If SD SSAF gain is enabled there are 13 response options in the 4 dB to 4 dB range The desired response can be programmed using register 0 2 The variation in frequency responses is shown in Figure 112 Figure 113 and Figure 114 The registers required for enabling and controlling the SSAF filter gain are described below MAGNITUDE dB 0 1 2 3 4 5 6 7 FREQUENCY MHz 06398 036 Figure 112 SD Luma SSAF Filter Programmable Responses Rev 0 Page 258 of 326 06 707 MAGNITUDE dB 06398 037 FREQUENCY MHz Figure 113 SD Luma SSAF Filter Programmable Gains MAGNITUDE dB 06398 038 FREQUENCY MHz Figure 114 SD Luma SSAF Filter Programmable Attenuation peak en Encoder Map Address OxE487 4 This bit is used to enable the SD SSAF filter gain Function peak en Description 1 Enabled 0 default Disabled peak 3 0 Encoder Map Address 0xE4A2 3 0 This signal is used to configure the SD luma SSAF gain attenuation only applicable if subad
366. nt bksv count 6 0 will read 0 when the first BKSV interrupt occurs with bksv flag int set to 1 After the first BKSV interrupt is cleared if the sink connected to the ADV8005 is a repeater a second BKSV interrupt will occur The ADV8005 will automatically read up to 13 5 byte BKSVs at a time and store these in the EDID memory These BKSVs can be accessed from the EDID Map as shown in Table 68 The number of additional BKSVs available stored in the EDID Map can be obtained from bksv_count 6 0 If there are more than 13 additional BKSVs to be processed the ADV8005 will collect the next up to 13 BKSVs from the sink then generate another BKSV interrupt with bksv flag int set to 1 when the next set is ready Table 68 KSV Fields Accessed From EDID Map KSV Number Field Name Register Addresses 0 bksvO byte 0 7 0 OxEEO0 7 0 byte 0 bksvO byte 1 7 0 OxEEO1 7 0 byte 1 bksvO byte 2 7 0 OxEEO2 7 0 byte 2 bksvO byte 3 7 0 OxEE03 7 0 byte 3 bksvO byte 4 7 0 OxEE04 7 0 byte 4 1 bksv1 byte 0 7 0 OxEE05 7 0 byte 0 bksv1_byte_1 7 0 OxEEO6 7 0 byte 1 bksv1 byte 2 7 0 OxEEO7 7 0 byte 2 bksv1 byte 3 7 0 OxEE08 7 0 byte 3 bksv1 byte 4 7 0 OxEEO9 7 0 byte 4 2 bksv2 byte 0 7 0 OxEEOA 7 0 byte 0 bksv2 byte 1 7 0 OxEEOB 7 0 byte 1 bksv2 byte 2 7 0 OxEEOC 7 0 byte 2 bksv2 byte 3 7 0 OxEEOD 7 0 byte 3 bksv2 byte 4 7 0 OxEEOE 7 0 byte 4 3 bksv3 byte O 7 0 OxEEOF 7 0 byte 0 bksv3 byte 1 7 0 OxEE1
367. nt video streams are input on the video TTL and EXOSD TTL inputs and the Serial Video Rx These video streams can then be routed through internal processing blocks for example PVSP or progressive to interlaced converter or connected directly to the backend transmission blocks for example HDMI transmitters and encoder 2 2 ADV8005 TOP LEVEL OVERVIEW This section documents the ADV8005 top level register descriptions explaining some of the registers required to configure the part which are not section or hardware block specific For more details on block specific settings refer to their appropriate sections Note This section details the ADV8005KBCZ 8A 8N Other versions of the ADV8005 do not offer the same functionality for example single Tx or no encoder 2 2 1 Video Muxing There are several blocks which make up the ADV8005 VSP as described in Section 2 The digital core of the ADV8005 offers flexible routing of video data as shown in Figure 25 Rev 0 Page 40 of 326 06 707 ADV8005 VI s inp chan sel 1 Digital Video Input Video Signal Processing Video Output p Primary Input Channel OSD Primary Input Channel Video TTL Input 9 Primary Primary VSP Blend 1 Primary VSP Td EXOSD TTL Input Input Secondary VSP gt Ptol n Channel Secondary Input Channel 201 OSD Blend 1 48 bit TTL Input RX Input Channel P Secondary VSP
368. ntrol possible ringing artifacts on the output of the encoder sd under limiter 1 0 Encoder Map Address OxE489 1 0 This signal is used to configure the SD undershoot limiter Function sd under limiter 1 0 Description 00 default Disabled 01 10 6IRE 11 1 5IRE sd y min value Encoder Map Address OxE48A 6 This bit is used to configure the SD minimum luma value Function sd y min value Description 0 default 401 1 7 5IRE 7 5 VERTICAL BLANKING INTERVAL The ADV8005 is capable of accepting input VBI data for example CGMS WSS and CCAP in SD ED and HD modes If VBI is disabled for SD mode see vbi open for HD mode see vbi data en VBI data is not present at the encoder output and the entire VBI is blanked These control bits are valid in all modes For SMPTE 293M 525p VBI data can be inserted on Lines 13 to 42 of each frame For ITU R BT 1358 625p VBI data can be inserted on Lines 6 to 43 For NTSC VBI data can be inserted on Lines 10 to 20 For PAL VBI data can be inserted on Lines 7 to 22 If CGMS is enabled and VBI is disabled the CGMS data is available at the output vbi open Encoder Map Address OxE483 4 This bit is used to enable data on the Vertical Blanking Interval VBI to be accepted as valid data This is valid for SD video data only Rev 0 Page 284 of 326 06 707 Function vbi open Description 1 Enabled 0 Disabled vbi data
369. ny of the SPI registers are not described in this section For more information refer to the Blimp OSD software tool user manual 4 2 2 Top Level Diagram Figure 82 provides a diagram of the ADV8005 OSD top level Rev 0 Page 171 of 326 06 707 OSD TTL Input External OSD SPI Master Slave Internally Generated OSD Microcontroller Flash Video Input 1 Blended Output 1 Blend Blended Output 2 Figure 82 Bitmap OSD Top Level Diagram Video Input 2 OSD Blend Used to overlay the OSD data with the input video OSD Scaler Used to scale the OSD to the target resolution CSC Used to convert the OSD core data color to the same color space as that of the input video OSD Core Used to generate internal OSD data Reads data from DDR2 memory and outputs data to FIFO SPI Master and SPI Slave SPI master used to copy flash data into DDR2 memory SPI slave used as the only means to control OSD configuration registers and memories 4 2 3 OSD Blending The OSD core in the ADV8005 has two video inputs and two video outputs and is capable of blending at data rates of up to 3 GHz The two video inputs allow two different video streams to be connected to the OSD core for example video TTL input channel and SVSP output The inputs connected to the OSD core can be selected using osd blend inp sel 3 0 and osd_blend_inp_2_sel 3 0 Refer to Figure 25 for further details The video stream co
370. o meet the minimum TMDS clock rate of 25 MHz The ADV8005 offers three choices for the user to implement pixel repetition in the Tx core These choices or modes are described below and can be set via mode 1 0 Automatic mode In automatic mode the ADV8005 uses the audio sampling rate and the detected VIC information as parameters to decide if pixel repetition is needed to obtain sufficient blanking periods to send the audio For 125 input stream the sampling rate is always set by the user via the i2s sf 3 0 field In the case of an SPDIF stream the source of the audio sampling rate information is set via the audio sampling freq sel bit If the pixel repetition factor is adjusted to meet bandwidth requirements the detected input VIC may be different from the VIC sent to the downstream sink The VIC of the actual video sent across the HDMI link to the downstream sink and which is included in the AVI InfoFrame be read from the vic to rx 5 0 field Manual mode In the manual pixel repetition mode the VIC sent in the AVI InfoFrame needs to be set The factor between the pixel clock Rev 0 Page 213 of 326 06 707 input to the Tx core and the output TMDS clock frequency must programmed in the pll manual 1 0 field The pixel repetition value sent to the HDMI sink must be programmed in pr value manual 1 0 Refer to the latest HDMI specification for more details on valid pixel repetition formats Max mode The max mode wo
371. o odd or even lines based on the field signal of the output interlaced video It can only support 480p 576p and 1080p input The associated interlaced timing signals can be generated in the independent PtoI hardware block By enabling m p2i drop line as pvsp flag the Ptol module can drop interpolated lines to get optimal output performance Rev 0 Page 135 of 326 06 707 The hardware can be enabled using m p2i enable m p2i enable Secondary VSP Map Address OxE649 4 This bit is used to enable the Ptol In VSP top Function m p2i enable Description 0 default Disable 1 Enable m p2i drop line as pvsp flag Secondary VSP Map Address 0xE65B 7 In Game Mode this bit is used to select an interlaced mode If the PVSP works in game mode and the PVSP s input is interlaced this bit should be set to 1 for the P2I block to drop interpolated lines Otherwise this bit should be set to 0 In external sync mode this bit enables field tracking When this bit is set low it uses the internally generated field instead of the master one provided The input video to the Ptol block is defined using m p2i vid 7 0 Refer to Table 27 for more details on the value of this register m p2i vid 7 0 Secondary VSP Map Address 0xE64B 7 0 This register is used to set the VIC of Ptol in VSP top Function m 21 vid 7 0 Description 0x00 default Default Table 27 VID Set to PtoI Input Timing Format
372. o the downstream sink by setting the pkt en bit When the transmission of ACP packets is enabled the ADV8005 transmits an APC packets once every two video fields acp pkt en TX2 Main Map Address OxF440 4 This bit is used to enable the ACP Packet Function acp pkt en Description 0 default Disabled 1 Enabled Table 65 ACP Packet Configuration Registers Packet Map Access Type Field Name Default Value Byte Address 0x40 R W acp hbO 7 0 0600000000 Header Byte 0 0 41 R W acp hb1 7 0 0500000000 Header Byte 1 0x42 R W acp_hb2 7 0 0b00000000 Header Byte 2 0x43 R W acp pbO 7 0 0600000000 Data Byte 0 0x44 R W acp pb1 7 0 0600000000 Data Byte 1 0x45 R W acp_pb2 7 0 0b00000000 Data Byte 2 Rev 0 Page 237 of 326 06 707 Packet Access Field Name Default Value Byte Name Address 0x46 R W acp pb3 7 0 0600000000 Data Byte 3 0x47 R W acp pb4 7 0 0600000000 Data Byte 4 0x48 R W acp pb5 7 0 0600000000 Data Byte 5 0x49 R W acp pb6 7 0 0600000000 Data Byte 6 Ox4A R W acp pb7 7 0 0600000000 Data Byte 7 Ox4B R W acp pb8 7 0 0600000000 Data Byte 8 0 4 R W acp pb9 7 0 0600000000 Data Byte 9 0 40 R W acp pb10 7 0 0600000000 Data Byte 10 Ox4E R W acp_pb11 7 0 0b00000000 Data Byte 11 Ox4F R W acp_pb12 7 0 0b00000000 Data Byte 12 0x50 R W pb13 7 0 0600000000 Data
373. oder Decoder Port GSC AGE 480p OSD only 720p RX 720p 65 1 OSD from 4 Serial gt Data Encoder generator Formatting amp CSC 2 Figure 23 8005 Mode 13 Configuration Mode 13 is used to support OSD input from an OSD generator with an HDMI interface Using this mode the Serial Video Rx video is loaded into memory before being called out by the OSD core This video can then be scaled and blended with the video on the primary video channel It is possible to output the unblended video the blended video or the raw OSD Rev 0 Page 39 of 326 06 707 2 1 15 Mode 14 Handling Triple Inputs Mode 14 should be used if three independent video streams are required on the output of the ADV8005 Mode 14 DDR2 Memory Interface Video Primary 1 i VSP uxing 080p Input Exosd 480i Muxing Video from 24 bit Data HDMI Decoder nput B A Formatting Tx2 amp CSC 10801 4 Mies YET video tom HD ideo trom Input ata Decoder gt Formatting Encoder CSC amp ACE 720p 1080p 60 Video from Serial Data Progressive to Encoder Transceiver Formatting Interlaced amp CSC 4 RNC Figure 24 ADV8005 Mode 14 Configuration Mode 14 is used to support three independent video streams The independe
374. oftware Implementation Rev 0 Page 245 of 326 N_ON Clear HDCP Request return to START UG 707 06 707 6 13 4 AV Mute AV mute can be enabled once HDCP authentication is completed between the ADV8005 and the downstream sink This can be used to maintain HDCP synchronization while changing video resolutions While the KSVs for the downstream devices are being collected an active HDCP link capable of sending encrypted video is established but video should not be sent across the link until the KSVs have been compared with the revocation list Itis not recommended to rely on AV mute to avoid sending audio and video during HDCP authentication This is because AV mute does not actually mute audio or video in the Tx It requests the function from the sink device The best way to avoid sending unauthorized audio and video is to not send data to the Tx core of the ADV8005 until authentication between the ADV8005 and the downstream sink is complete Another option is to black out the video data input to the Tx core and disable the audio inputs to mute the audio Refer to Section 6 4 for an explanation of how to enable AV mute Refer to Section 6 11 for an explanation of how to disable the various audio inputs 6 14 AUDIO RETURN CHANNEL The ADV8005 features an Audio Return Channel ARC Rx in each HDMI Tx that supports the extraction of an SPDIF stream from the ARC component of an HDMI Ethernet and Audio Channel HEAC sign
375. oif cc 2 0 to 0x7 If one stereo channel only is needed the 125 audio stream data must be input to AUD IN 0 i2s en 3 0 and audioif cc 2 0 control fields must be set to 1 When audio sampling freq sel is set to 1 the audio sampling frequency programmed via 125 SF is used for the determination of the pixel repetition factor refer to Section 5 7 for more details audioif sf 2 0 TX2 Main Map Address 0xF474 4 2 This signal is used to specify the Audio Sampling Frequency in the Audio InfoFrame Function audioif sf 2 0 Description 000 default Case 1 Not DSD audio or Case 2 DSD audio AUDIO INPUT SEL 06010 001 64 x 32 kHz 010 64 x 44 1 kHz 011 64 x 48 kHz 100 64 x 88 2 kHz 101 64 x 96 kHz 110 64 x 176 4 kHz 111 64 x 192 kHz audioif cc 2 0 TX2 Main Map Address 0xF473 2 0 This signal is used to set the Audio Channel Count Audio InfoFrame Function audioif cc 2 0 Description 000 default Refer to Stream Header 001 2 channels 010 3 channels 011 4 channels 100 5 channels 101 6 channels 110 7 channels 111 8 channels Ds en 3 0 2 Main Map Address 0xF40C 5 2 This signal is used to enable the I2S pins Rev 0 Page 222 of 326 06 707 Function i2s en 3 0 Description 0000 All 12S disabled 1111 default All 125 enabled i2s_sf 3 0 2 Main Map Address 0 415 7 4 This signal is used to set the Sampling frequency for 12S audio This information
376. on Function di cadence enable Description 0 Disable cadence detection 1 default Enable cadence detection The PVSP supports the following cadence types 22 e 2 2 2 4 3 2 e 2 3 3 2 2 2 3 32 3 2 3 2 2 3 3 44 5 5 64 87 Each of these cadence types can be disabled by setting the corresponding bit in di fd disabled cadence 10 0 to 1 For conversion of 60 Hz interlaced and progressive input timing to 24 Hz progressive timing pvsp frc change phase en should be asserted For all other cases pvsp frc change phase en should be disabled when using 1 external DDR2 memory pvsp frc change phase en Primary VSP Map Address 0 84 4 This bit is used to lock the phase change for cadence detection Function pvsp frc change phase en Description 0 Disable 1 default Enable di fd disabled cadence 10 0 Primary VSP Map Address 0xE8FA 7 0 Address OXESFB 7 5 This signal is used to disable corresponding cadence detection Function di fd disabled cadence 10 0 Description 0x000 default Default Table 24 Corresponding Bit for Each Cadence Type Bit Disabled Cadence OxE8FB 5 2 2 OxE8FB 6 2 2 2 4 OxE8FB 7 3 2 OxE8FA O 2 3 3 2 2 OxE8FA 1 2 3 3 2 OxE8FA 2 3 2 3 2 2 OxE8FA 3 3 3 OxE8FA 4 4 4 OxE8FA 5 5 5 OxE8FA 6 6 4 OxE8FA 7 8 7 Rev 0 Page 124 of 326 06 707 3
377. on gamut packet id 7 0 Description Packet type value of packet stored InfoFrame Map Address 4 to OxDF Packet type value of InfoFrame stored in InfoFrame Map Address 0 4 to OxDF Note The packet type values and corresponding packets should not be programmed in the packet type values registers The general control packet 0x03 is always processed internally and cannot be stored in the packet InfoFrame registers in the InfoFrame Map 5 12 HDMI SECTION RESET STRATEGY The following reset strategy is implemented for the HDMI section e Global chip reset This means the ADV8005 Serial Video Rx core can be reset using the rx reset or main reset A global chip reset is triggered by asserting the RESET pin to a low level The HDMI section is reset when a global reset is triggered e Loss of TMDS clock or 5 V signal reset A loss of TMDS clock or 5 V signal to the Serial Video Rx resets the entire Serial Video Rx section The loss of a 5 V signal condition is discarded if dis cable det rst is set high e DVI mode reset The packet processing block including InfoFrame memory is held in reset when the Serial Video Rx processes DVI stream Rev 0 Page 202 of 326 06 707 6 HDMI TRANSMITTER The HDMI transmitters on the ADV8005 are capable of outputting video data at up to 3 GHz and support 3D video output ARC common mode only and audio output The dual transm
378. on 13 TTL Output CSC Channel A Output Ou A In A 42 0 saec 2 01 212 01 312 0 4096 4096 4096 Equation 14 TTL Output CSC Channel B Output Out B 2 4 12 2 CSC Rev 0 Page 93 of 326 06 707 Color Space Conversion HDTV YCbCr limited to RGB limited HDTV YCbCr limited to RGB full HDTV YCbCr limited to SDTV YCbCr limited HDTV YCbCr limited to SDTV YCbCr full HDTV YCbCr full to SDTV YCbCr limited SDTV YCbCr limited to RGB limited SDTV YCbCr limited to RGB full SDTV YCbCr limited to HDTV YCbCr limited SDTV YCbCr limited to SDTV YCbCr full SDTV YCbCr full to HDTV YCbCr limited RGB limited to HDTV YCbCr limited RGB limited to SDTV YCbCr limited RGB limited to RGB full C12 0 px 242 0 4096 4096 Equation 15 TTL Output CSC Channel C Output RED oc 2201 In ou C Im A 12 a DM E Table 16 TTL Output Channel CSC Common Configuration Coefficients 1 0 csc mode x0C53 0 0800 0 0000 0 1906 0 1 56 0 0800 x2 0 0734 oxo4AD 0 0000 0 1 1 Ox1DDC 0x04AD 0 Mil 0 0000 loxiFeC 0 0058 0 0188 0 0800 0 0 0 0 0 0 0 0 08 0 0000 0 1 58 0 1 0 01 9 0 0950 uni 0 0000 0 0000 0 0100 0 0000 lOxODBC x1 x1 x1 x1 x1 x1 0 xOAF8 0 0800 0 0000 0 1 84 lOx1A6A 0 0800 0
379. onal digital IO Digital input Digital input Digital input Digital output Digital output Digital output Digital output N A N A N A Digital output Digital output N A Digital input Digital input Digital input Digital input N A A22 RSET1 Miscellaneous Float this pin Analog input analog A23 VREF Miscellaneous Float this pin Analog input analog B1 OSD IN 21 EXT DIN 5 B2 OSD IN 22 EXT DIN 6 B3 OSD VS OSD video Float this pin as it is disabled by default sync Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default B4 AUD 1 01 B5 AUD IN 3 B6 SFL B7 1 OUT OSD video input miscellaneous digital OSD video input miscellaneous digital Audio output Float this pin as it is disabled by default Float this pin as it is disabled by default Connect this pin to ground through a Bi directional digital IO Bi directional digital IO Bi directional digital IO Digital input Digital input Digital input Digital output Rev 0 Page 301 of 326 06 707 Location Serial port Float this pin as it is disabled by default control B9 MOSI2 Serial port Float this pin as it is disabled by default control B8 B10 MISO2 Serial port Float this pin as it is disabled by default control B11 ALSB control Connect this pin to ground through a 4 7 resistor B12 XTALP Miscellaneous T
380. ould be set high and the coefficient should be programmed to value of 0 5 Otherwise the largest value would be 4095 4096 0 9997 While this value could be interpreted as 1 it is recommended to use the value of 0 5 and set the rx csc mode 1 0 bits for maximum accuracy The CSC configurations for common modes are provided in Table 15 Table 15 RX Input Channel CSC Common Configuration Coefficients Rev 0 Page 90 of 326 Color Space Conversion HDTV YCbCr limited to RGB limited HDTV YCbCr limited to RGB full HDTV YCbCr limited to SDTV YCbCr limited HDTV YCbCr limited to SDTV YCbCr full HDTV YCbCr full to SDTV YCbCr limited SDTV YCbCr limited to RGB limited SDTV YCbCr limited to RGB full SDTV YCbCr limited to HDTV YCbCr limited SDTV YCbCr limited to SDTV YCbCr full SDTV YCbCr full to HDTV YCbCr limited RGB limited to HDTV YCbCr limited RGB limited to SDTV YCbCr limited RGB limited to RGB full RGB full to HDTV YCbCr limited RGB full to SDTV YCbCr limited RGB full to RGB limited output input 1 0 csc mode x0C53 0 0800 0 0000 0 1906 0 1 56 0 0800 0x04AD 0 0000 loxiciB loxiDDC 0 04 0 0 0000 0 1 0 0058 0 0188 0 0800 0 0000 0 1 58 1 0 01 9 0 0950 0x0 0 0 00 0 0000 0 0000 0 0100 0 0000 lOxODBC d 0 0800 0 0000 0 1 84 Ox1A6A 0
381. output port description 3 3 1 3 Frame Buffer Number Depending on the type of conversion that is to take place a certain number of buffers must be allocated for the input output video data Depending on the conversion required this should be set in the svsp_fieldbuf_num 2 0 register svsp_fieldbuf_num 2 0 can be automatically set per svsp autocfg input vid 7 0 and svsp autocfg output vid 7 0 The svsp fieldbuf num 2 0 register will not change when crop album mode is enabled svsp fieldbuf num 2 0 Secondary VSP Map Address 0xE610 2 0 This signal is used to set the number of field frame buffers This signal needs to be configured while svsp osd mode en is 1 Function svsp fieldbuf num 2 0 Description 000 default Default XXX Number of field frame buffers 3 3 1 4 Frame Buffer Address and Size In order to store video data in external memory in the correct size frames the buffer size of the external DDR2 memory must be programmed by the user These programmed field buffers or frame buffers are allocated by setting the svsp_fieldbuffer0_addr 31 0 svsp fieldbufferl addr 31 0 svsp fieldbuffer2 addr 31 0 and svsp fieldbuffer3 addr 31 0 registers The value programmed into each of these registers is determined in Equation 22 frame size active video _ width x active video height bytes per pixel Equation 22 Calculating External Memory Field Buffers For example for an output video resolution of 720p
382. outputs for their full trace length The termination resistors on the encoder analog outputs should be kept as close as possible to the ADV8005 Any external filtering on the encoder outputs should be placed as close as possible to the analog connectors External DDR2 Memory Requirements The ADV8005 must be placed as close to and on the same side of the PCB as the external DDR2 memories Balanced T routing should be used for all shared connections between the ADV8005 and the external DDR2 memories traces should be 750 and impedance controlled to ensure robust timing Traces should be routed on the same side of the PCB as the devices where possible If this is not possible all traces should be kept on the outer layers differential signals for example DDR CK and DDR CKB should be treated as described above These signals should be routed in parallel and on the same side of the PCB Match the DDR CK trace length to DDR trace length to 20 mils 0 5 mm Any stubs on the clock lines should be kept as short as possible to avoid signal reflections The following 4 byte wide data lanes should be matched to within 50 mils on the PCB layout The precise matching of these signals is critical e DDR3 DM3 DDR DQS3 DDR DQSB3 DDR DDR DQ24 e DDR2 2 DDR DQS2 DDR DQSB2 DDR DQ23 DDR 16 e DDR DQSI DDR DQSBI DDR DQI15 DDR e DDR0 DDR DQS0 DDR DDR DQ7 DDR Differen
383. ows the relationship of the VOM scaler image and the output video In this case the blank area around the output image is filled with color defined by pvsp dp margin color 23 0 in the YCbCr color space Output video from Primary VSP PVSP DP VIDEO V START Output video from PVSP DP VIDEO H START VOM Output PVSP SCAL OUT HEIGHT PVSP DP ACTIVELINE PVSP SCAL OUT WIDTH PVSP DP DECOUNT Figure 61 VOM Output Dimensions pvsp dp video h start 12 0 Primary VSP Map Address 0xE848 4 0 Address OxE849 7 0 This signal is used to set the horizontal start position where the output video of the scaler is placed Function pvsp dp video h start 12 0 Description 0x000 default Default OxXXX Horizontal start position of VOM output pvsp dp video v start 12 0 Primary VSP Map Address OxE84A 4 0 Address OxE84B 7 0 This signal is used to set the vertical start position where the output video of scaler is placed Function pvsp dp video v start 12 0 Description 0x000 default Default OxXXX Vertical start position of VOM output pvsp_dp_margin_color 23 0 Primary VSP Map Address OxE866 7 0 Address 0xE867 7 0 Address OxE868 7 0 This signal is used to set the default color in output video in YUV colorspace Rev 0 Page 133 of 326 06 707 Function pvsp dp margin color 23 0 Description 0x000000 Default OxXXXXXX Default color in YUV colorspace
384. p dp vfrontporch 9 0 Secondary VSP Map Address 0xE63C 7 0 Address 0xE63D 7 6 This signal is used to set the vertical front porch duration of output timing This register s value will be used while svsp_autocfg_output_vid is 0 Function svsp dp vfrontporch 9 0 Description 0x000 default Default OxXXX Vertical front porch of output timing svsp dp vsynctime 9 0 Secondary VSP Map Address 0xE63E 7 0 Address 0xE63F 7 6 This signal is used to set the vertical synchronous time of output timing This register s value will be used while svsp autocfg output vid is 0 Function svsp dp vsynctime 9 0 Description 0x000 default Default OxXXX Vsync width of output timing svsp dp vbackporch 9 0 Secondary VSP Map Address 0xE640 7 0 Address 0xE641 7 6 This signal is used to set the vertical back porch duration of output timing This register s value will be used while svsp_autocfg_output_vid is 0 Function svsp_dp_vbackporch 9 0 Description 0x000 default Default OxXXX Vertical back porch of output timing svsp_dp_vpolarity Secondary VSP Map Address 0xE642 7 This signal is used to set the polarity of output Vsync This register s value will be used while svsp_autocfg_output_vid is 0 Function svsp dp vpolarity Description 0 default Low 1 High svsp dp hpolarity Secondary VSP Map Address OxE642 6 This signal is used to set the polarity of output Hsync This register s value
385. p period of the DPLL section This should be programmed based on the value calculated from the given equations svsp vid clk update IO Map Address 0x1A3F 4 This bit is used to trigger the open loop period to be captured in the DPLL A low to high transition triggers the action Function svsp vid clk update Description 0 default Do not update open loop period 1 Update open loop period in DPLL For example the following procedure for updating the SVSP DPLL clock period is very similar to that of the PVSP 1A 1 9 0A Put the DPLL into ADV8005 mode 1A 1A40 XX Configure DPLL clock period setting 1A 1A41 XX Configure DPLL clock period setting 1A 1A42 XX Configure DPLL clock period setting 1A 1 43 XX Configure DPLL clock period setting 1A 1A3F 80 Recommended setting 1A 1 90 Recommended setting Once configured the clock in Figure 37 is programmed for operation 2 2 4 3 Frame Tracking The ADV8005 employs frame tracking on its scaler outputs There will always be some error in the input frame rate versus the ideal frame Rev 0 Page 66 of 326 06 707 rate This could cause frame drops repeats at the output Frame tracking allows the output timing to track the input timing in such that eliminates frame drops and repeats while also remaining immune to discontinuities in the input The system can be fully frequency and phase locked using If phase locked is selected there wil
386. ple word width is set via the word length 3 0 field The ADV8005 can also receive an 125 stream in both 64 bit and 32 bit modes so either 32 or 16 bit clock that is the signal input through SCLK pin edges or cycles per channel are valid The ADV8005 will adapt to 32 or 64 bit modes automatically and the current mode can be read in the i2s 32bit mode field Refer to Figure 100 to Figure 104 for timing diagrams on I2S streams input to the ADV8005 When the ADV8005 is configured to receive a direct AES3 stream the stream it receives should have IEC60958 like subframes refer to Figure 98 with the stream formatted as follows e Data should be aligned as shown in Figure 98 e Preamble left out as shown in Figure 99 e Parity bit is replaced by the block start flag The ADV8005 automatically computes the parity bit The channel status data collected from the audio stream input to the AUD IN 0 pin is used in the Audio Sample packets sent by the ADV8005 to the downstream sink The channel status data can alternately be programmed by setting the cs bit override bit When cs bit override is set to 1 setting audio sampling freq sel allows the programming of the audio sampling frequency used for the channel status bits while all other channel status data is extracted from the audio stream input to 1250 The sampling frequency is set via the 125_ 3 0 field Note four stereo channels AUD IN 3 0 are enabled by setting 125 en 3 0 to OxF and audi
387. porates an input formatter CSC and updither block The input formatter provides a number of controls to configure what data the secondary input channel is configured for The secondary input channel must be connected to either the video TTL input pins or the EXOSD TTL input pins usings inp chan sel 1 0 If the secondary input channel is connected to the video TTL input pins the format and bit width of the data for example 2 x 8 bit buses of 4 2 2 data must be specified using exosd format sel 4 0 exosd swap bus ctrl 2 0 can be used to indicate which input pins are used to carry the upper middle and lower ranges of bits for example upper D 35 25 middle D 24 12 lower D 11 0 or upper D 11 0 middle D 35 25 lower D 24 12 s_inp_chan_sel 1 0 IO Map Address 0x1A07 3 2 This signal is used to select the input for the Secondary Input Channel Function 5 inp chan sel 1 0 Description 00 Video TTL input P 35 0 01 default EXOSD TTL Input OSD 23 01 10 RX video 11 N A exosd format sel 4 0 IO Map Address 0x1B68 4 0 This signal is used to select the input format for the video data Rev 0 Page 56 of 326 06 707 Function exosd format sel 4 0 Description 0x00 1x8 bit bus 4 2 2 0x01 1x 10 bit bus 4 2 2 0x02 1x 12 bit bus 4 2 2 0x03 2x8 bit buses 4 2 2 0x04 2x 10 bit buses 4 2 2 0x05 2x 12 bit buses 4 2 2 0x06 3 x 8 bit buses SDR 4 4 4 0x07 3x 10 bit buses SDR 4 4
388. pper Function pvsp vim crop v start 10 0 Description 0x000 default Default OxXXX Vertical start position of VIM cropper input pvsp vim crop width 10 0 Primary VSP Map Address 0 836 2 0 Address 0xE837 7 0 This signal is used to set the input width of the VIM cropper Function pvsp vim crop width 10 0 Description 0x000 default Default OxXXX Width of VIM cropper input pvsp vim crop height 10 0 Primary VSP Map Address 0xE838 2 0 Address 0xE839 7 0 This signal is used to set the input height of the VIM cropper Function pvsp vim crop height 10 0 Description 0x000 default Default OxXXX Height of VIM cropper input Note The following limitations apply to the values that can be programmed in these registers e 0 lt pvsp_vim_crop_h_start 10 0 lt INPUT VIDEO HORIZONTAL RESOLUTION 1 e 0 lt pvsp_vim_crop_v_start 10 0 lt INPUT VIDEO VERTICAL RESOLUTION 1 e pvsp vim crop h start 10 0 pvsp vim crop width 10 0 lt INPUT VIDEO HORIZONTAL ACTIVE PIXELS e pvsp vim crop v start 10 0 vim crop height 10 0 lt INPUT VIDEO VERTICAL ACTIVE PIXELS Rev 0 Page 117 of 326 06 707 3 2 2 2 Horizontal Down Scaler Although the VOM has both horizontal and vertical scalers there is also a horizontal down scaler in the VIM The purpose ofthe VIM down scaler is to save external memory bandwidth by doing horizontal downscaling before writing video
389. ptions for scaler interpolation are versions of the proprietary ADI algorithm The sharp and smooth versions allow for limited customization of the scaler function This function can be set depending on the user preference Bilinear The bilinear option uses an averaging method within a 2x2 pixel array to increase the size of the input frame This is a cruder method of Rev 0 Page 118 of 326 06 707 scaling than the default proprietary ADI Algorithm In most cases the scaler should be left at the default setting pvsp vim scal type 1 0 Primary VSP Map Address OxESE5 7 6 This signal is used to set the VIM scaling algorithm For up scaling the proprietary ADI algorithm is recommended whereas for down scaling the sharp setting is recommended Function pvsp vim scal type 1 0 Description 00 Proprietary ADI Algorithm 01 Sharp 10 Smooth 11 default Bilinear 3 2 2 4 Scaler Controls The following register is used in the control of the VIM scaling function and should be tailored according to user requirements pvsp vim scal overshoot ctrl 11 0 Primary VSP Map Address 0 8 9 7 0 Address OxE8EA 7 4 This bit is used to control the overshoot in the scaling of input video If set to a value larger than the default setting more overshoot is allowed Function pvsp vim scal overshoot ctr Description 11 01 0x080 default Default 3 2 2 5 Pixel Packer At the back end of the VIM the pixel packer conver
390. put Data Formatter Video TTL Input EXOSD TTL Input External OSD Alpha Output Figure 27 EXOSD TTL Input Channel RX Input Channel gt 1080 12 bit data RX Input Channel Serial Output Video Ru Up dither csc RX otate Receiver Mc UN External OSD Ld Alpha Output Figure 28 RX Input Channel 2 2 2 1 Video TTL Input Rev 0 Page 44 of 326 06 707 The video TTL input pins are defined as follows e P 47 0 e HS VS DE e PCIK The video TTL input pins can be connected to either the primary input channel refer to Section 2 2 2 6 or the secondary input channel refer to Section 2 2 2 7 2 2 2 2 EXOSD TTL Input The EXOSD input pins are defined as follows e 050 IN 23 16 e 050 IN I5 VBI SCK e 050 IN 14 VBI MOSI e 050 IN 13 VBI SCK e 050 IN 12 0 e 05 HS e OSD VS e 05 DE e 05 The EXOSD input pins can be connected to either the primary input channel refer to Section 2 2 2 6 the secondary input channel refer to Section 2 2 2 7 2 2 2 3 TTL Output The ADV8005 includes TTL output port The external OSD TTL input pins OSD IN 23 0 and 12 of the TTL input pins P35 24 can function as TTL output pins refer to Table 90 and Table 91 If all 36 TTL pins are used as outputs this leaves only 24 pins for TTL inputs Appendix C describes the different pinout options available for the TT
391. put OSD video input OSD video input OSD video input OSD video input miscellaneous digital Miscellaneous analog Do Not Connect OSD video input OSD video input OSD video input OSD video input Digital Power Supply 1 8 V Miscellaneous analog Miscellaneous analog OSD video Description if Unused Float this pin as it is disabled by default Float this pin Ground Float this pin Float this pin Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin Encoder PLL Supply 1 8 V Ground Float this pin Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default Float this pin as it is disabled by default Ground Ground Ground Ground Ground Digital Power Supply 1 8 V Ground Ground Ground Ground This pin must be connected This pin must be connected Ground Float this pin as it is disabled by default Pin Type Bi directional digital IO N A Digital output N A Analog input Analog output Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Analog input N A N A Digital output Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi
392. put Digital output Digital output Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO Bi directional digital IO 06 707 Location AB23 ACT AC2 AC3 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mnemonic DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DO 16 DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 20 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 22 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DQ 25 DDR interface Connect this pin to ground through a 4 7 resistor DDR DO 28 DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 27 DDRinterface Connect this pin to ground through a 4 7 resistor DDR DOD4 DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 10 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DOS 1 DDR interface Connect this pin to ground through a 4 7 resistor DDR DQ 15 DDR interface Connect this pin to ground through a 4 7 resistor DDR DOI7 DDRinterface Connectthis pin to ground through a 4 7 resistor DDR DO 2 DDRinterfa
393. quency Lock SFL mode rtcen 11 When SFL mode is enabled the SFL pin receive a serial digital stream from an ADI decoder for example ADV784x which is used to lock the subcarrier frequency This enables the ADV8005 encoder to stay locked to a video pixel clock which drifts over the time this happens with poor video sources like VCRs Since the color subcarrier in SD modes is generated from the input pixel clock to the ADV8005 these variations on its frequency may alter the final color on the CBVS or Y C output Hence the SFL mode allows the ADV8005 encoder core to automatically alter the subcarrier frequency to compensate for these line length variations When the part is connected to a device such as an ADV784x video decoder that outputs a digital data stream in the SFL format the part automatically changes to the compensated subcarrier frequency on a line by line basis This digital data stream is 67 bits wide and the subcarrier is contained in Bit 0 to Bit 21 Each bit is two clock cycles long rtcen 1 0 Encoder Map Address 0 484 2 1 This signal is used to select the Sub carrier Frequency Lock mode The value of these register bits along with the status of the SFL pin determine the operation Function rtcen 1 0 Description 00 default Disabled 11 SFL mode enabled Rev 0 Page 255 of 326 06 707 7 4 3 SD VCR FF RW Synchronization In DVD record applications where the encoder is used with a decoder the V
394. r full csc_mode 1 0 HDTV YCbCr 0 0 OxOEOD 0 0000 0x0000 0 0100 0 0000 OxODBC OxOEOD 10 0100 full to SDTV YCbCr limited SDTV YCbCr OxOAF8 0 0800 0 0000 0 1 84 0 1 0 0800 OxODDE 10 1913 limited to RGB limited SDTVYCbCr 0 2 0 0669 0 04 0 0000 Ox1C81 Ox1CBC 0 04 0x081A Ox1BA9 limited to RGB full SDTV YCbCr 0x0833 0 0000 0 0099 Ox1F99 0 1 56 0 0800 0x0826 0x1F78 limited to HDTV YCbCr limited SDIVYCbCr 0 1 OxO91B 0 0000 0 0000 Ox1F6E 0 0000 0 0950 0x091B 10 1 limited to SDTV YCbCr full SDTV YCbCr 0 2 0x039D 0 0000 0 0043 OxOF26 0 1 44 0 036 0x0397 0x004D full to HDTV Rev 0 Page 85 of 326 06 707 Color Space Conversion 1 0 csc mode YCbCr limited RGB limited 0 0 0 082 0 1893 Ox1F3F 0 0800 uM 0x0B71 0x19B2 to HDTV YCbCr limited RGB limited 0 0 0 082 0 1926 Ox1EAC 0 0800 0 04 9 0 0965 to SDTV YCbCr limited RGB limited 0 0 OxODBC 0 0000 0 0000 0 0100 to RGB full RGB full to OxO OxO6FF 10 19 0 1 58 0 0800 E OxO9CB HDTV YCbCr limited RGB Full to 0 0 OxO6FF 0 1 24 Ox1EDD 0 0800 0 0418 0 080 OxO6FF 0 0800 SDTV YCbCr limited RGB Full to 0 1 0x0950 0 0000 0 0000 0 1 6 0 0950 0x0950 0 1 6 RGB limited Identity matrix Ox1 0 0800 0 0000 0 0
395. r Cr Scale Value 1 3 x 512 665 6 Y Cb or Cr Scale Value 666 rounded to the nearest integer Y Cb or Cr Scale Value 1010 0110 10b Reg 0 49 SD scale LSB register 0x2A Reg 0xE49D SD Y scale register 0xA6 Reg 0xE49E SD Cb scale register 0 Reg OxEA9F SD Cr scale register 0 Note It is recommended that the SD luma scale saturation feature saturate luma be enabled when scaling the Y output level to avoid excessive Y output levels saturate luma Encoder Map Address 0xE487 1 This bit is used to enable the SD luma scale saturation Function saturate luma Description 1 Enabled 0 default Disabled 7 4 12 SD Hue Adjust Control When enabled the SD hue adjust control register is used to adjust the hue on the SD composite and chroma outputs To enable this feature hue en must be programmed to 1 hue en Encoder Map Address 0xE487 2 This bit is used to enable the hue adjust function Function hue en Description 1 Enabled 0 default Disabled Register 4 0 contains the bits required to vary the hue of the video data that is the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst The ADV8005 encoder provides a range of 22 5 in increments of 0 17578125 For normal operation zero adjustment this register is set to 0x80 Value OxFF and value 0x00 represent the upper and lower limits re
396. rame Checksum Error Flags Rev 0 Page 193 of 326 06 707 To determine if a checksum error has occurred with the InfoFrame packets the user can poll the various status bits in the IO Map There are several interrupt flags in the IO Map which indicate the status of the various InfoFrames Refer to Section 8 2 2 for more details on the Serial Video Rx interrupts Rev 0 Page 194 of 326 06 707 5 9 3 AVI InfoFrame Registers Table 35 provides a list of readback registers for the AVI InfoFrame data Refer to the EIA CEA 861 specifications for a detailed explanation of the AVI InfoFrame fields Table 35 AVI InfoFrame Registers InfoFrame Access Type Register Name Byte Map Address OxE3EO Packet Type Value OxE3E1 ee InfoFrame version number OxE3E2 R avi_inflen InfoFrame length R Checksum R iitpbos DataByted Ox R DataByte12 DE R aiintpb020 DataByte 19 OxE31B R inf pb 0 28 Data Byte 27 As defined by the EIA CEA 861 specifications The AVI InfoFrame registers are considered valid if the following two conditions are met e avi infoframe detis 1 e avi inf cksum err is 0 This condition applies only if always store infis set to 1 Rev 0 Page 195 of 326 06 707 5 9 4 SPD InfoFrame Registers Table 36 provides a list of readback registers available for the SPD InfoFrame Refer to the EIA CEA 861 specifications for a detailed
397. rame was detected Used to indicate if an MPEG source InfoFrame was detected rx spd info frm Edge sensitive Used to indicate if a source product descriptor InfoFrame was detected edge raw st mb2 clr rx avi info frm e dge raw st mb2 clr Edge sensitive Used to indicate if an AVI InfoFrame was detected 8 2 2 1 Multiple Interrupt Events If an interrupt event occurs and then a second interrupt event occurs before the system controller has cleared or masked the first interrupt event the ADV8005 does not generate a second interrupt signal The system controller should check all unmasked interrupt status bits as more than one may be active 8 2 3 Serial Video Interrupts Validity Checking Process All Serial Video interrupts have a set of conditions that must be taken into account for validation in the system firmware When the ADV8005 alerts the system controller with a Serial Video interrupt the host must check that the following validity conditions for that interrupt are met before processing that interrupt This is valid for all the interrupts described above e ADV8005 is configured in HMDI mode rx tmds clk det raw is set to 1 if the Serial Video Rx input is being used e rx tmdspll lck raw bit is set to 1 8 3 VSP AND OSD SECTION This section describes the interrupts provided by the ADV8005 OSD and VSP section These interrupts are not accessed through the I2C interface as the interrupts for the Seri
398. re output clock period is the period of the desired output sampling frequency For example for HD video the output clock sampling frequency would be 148 5 MHz This equation returns a decimal value Once calculated this should be converted to hex and written to pvsp vid clk period 33 0 and svsp vid period 33 0 Table 4 outlines some common resolutions and their associated dpll clock period values Table 4 Example Values for dpll clock period Active Resolution Frame Rate Hz Sampling clock period Frequency MHz Hex 720 x 480i 29 97 13 5 0x180000000 720 x 480p 59 94 27 0x0C0000000 720 x 576i 25 13 5 0x180000000 720x 576p 50 27 0x0C0000000 960 x 480i 29 97 18 0x120000000 960 x 576i 25 18 0x120000000 1280 x 720p 59 94 74 175 0x045E386DC 1280 x 720p 60 74 25 0x045D1745D 1920 x 1080i 29 97 74 175 0x045E386DC 1920 x 10801 30 74 25 0 045017450 1920 1080 59 94 148 35 0x022F1C36E 1920 x 1080p 60 148 5 0x022b8BA2F 1920 x 1080i 25 74 25 0x045D1745D 1920 x 1080p 50 148 5 0x022E8BA2F Depending on the sampling frequency required the following registers need to be programmed with this DPLL clock period Note To enable the DPLL to configure the correct clocks for the ADV8005 register 0x0039 must be set to 0x0A This register must always be configured before the following registers are set This configures the ADV8005 clock generators to generate the clocks for the ADV800
399. re provided in Table 79 Table 79 SD Gamma Curve A Curve Type Point Register Address SD Gamma Curve A Point 24 0 6 SD Gamma Curve A1 Point 32 OxA7 SD Gamma Curve A A2 Point 48 0 8 SD Gamma Curve A3 Point 64 0 9 SD Gamma Curve A4 Point 80 OxAA SD Gamma Curve A A5 Point 96 OxAB SD Gamma Curve A A6 Point 128 OxAC SD Gamma Curve A A7 Point 160 OxAD SD Gamma Curve A Point 192 OxAE SD Gamma Curve A A9 Point 224 OxAF SD Gamma Curve B BO Point 24 OxBO SD Gamma Curve B B1 Point 32 OxB1 SD Gamma Curve B B2 Point 48 OxB2 SD Gamma Curve B B3 Point 64 OxB3 SD Gamma Curve B B4 Point 80 0 4 0 B5 Point 96 OxB5 SD Gamma Curve B B6 Point 128 OxB6 SD Gamma Curve B B7 Point 160 OxB7 SD Gamma Curve B B8 Point 192 OxB8 SD Gamma Curve B B9 Point 224 OxB9 To select between both the A and B curves gamma curve b must be programmed gamma curve b Encoder Map Address OxE488 7 This bit is used to select the gamma correction curves for SD video data Rev 0 Page 272 of 326 06 707 Function gamma curve b Description 0 default Gamma Correction Curve A 1 Gamma Correction Curve B 7 4 18 ED HD Sharpness Filter and Adaptive Filter Controls There are three filter modes available on the ADV8005 encoder block a sharpness filter mo
400. red to be an EDID extension map This map should be parsed according to the VESA EDID specification to determine where additional EDID blocks are stored in the sink EDID storage device such as EEPROM RAM and so on The ADV8005 is capable of accessing up to 256 segments from EDID of the sink as allowed by the EDID specification By writing the desired segment number to the edid_segment 7 0 field the ADV8005 will automatically access the correct portion of the sink EDID over the Tx DDC lines and load the 256 bytes into the EDID HDCP memory When the action is complete the ADV8005 triggers the edid ready int interrupt refer to Section 6 8 The EDID data read from the sink can then be accessed from the Tx EDID Map If the host controller needs access to previously requested EDID information then it can be stored in its own memory Rev 0 Page 240 of 326 06 707 Figure 107 shows how to implement software to read EDID from the downstream sink using the ADV8005 V START a x HDP_INT Power up Tx via SYSTEM_PD a EDID Set Ready Interrupt EDID_SEGMENT DID READY INT desired Segment YES Disable EDID Read EDID data Need Parse EDID Interrupt Setup Audio and from M EDD Data NO gt READY INT 777797 Video until next HPD Figure 107 Reading Sink EDID Through ADV8005 6 12 4 edid tries Control edid tries 3 0 can be u
401. resolution of input video pvsp vin v 10 0 Primary VSP Map Address 0xE830 2 0 Address 0xE831 7 0 This signal is used to set the vertical resolution of the input video This register s value will be used while man input res is 1 or pvsp autocfg input vid is 0 Function pvsp vin v 10 0 Description 0x000 default Default 0 Vertical resolution of input video Similarly if the output timing is not in the PVSP output format table customized output format needs to be set manually The detailed configuration instructions are given in the PVSP VOM output port description 3 2 1 3 Field Frame Buffer Number Depending on the type of conversion that is to take place a number of buffers must be allocated for the input output video data Depending on the conversion required this should be set in the pvsp fieldbuf num register pvsp fieldbuf num can be automatically set by pvsp autocfg input vid 7 0 and pvsp autocfg output vid 7 0 The pvsp fieldbuf num register does not change when crop or album mode is enabled pvsp fieldbuf num 2 0 Primary VSP Map Address 0xE829 2 0 Sets the number of field frame buffers Function lt fieldbuf num 2 0 Description 000 Default XXX Number of field frame buffers 3 2 1 4 Field Frame Buffer Address and Size In order to store video data in external memory in the correct size fields the buffer size of the external DDR2 memory must be programmed by
402. rial Video Rx Float this pin input AVDD2 Encoder Analog Power Supply 3 3 V AVDD2 Encoder Analog Power Supply 3 3 V Analog video Float this pin output DAC2 Analog video Float this pin output SDA CST GND OSD IN 13 VBI SCK OSD video input miscellaneous Float this pin as it is disabled by default OSD IN 14 VBI MOSI digital OSD video input miscellaneous digital Float this pin as it is disabled by default Pin Type N A N A Analog output Analog output Bi directional digital IO Bi directional digital IO Bi directional digital IO N A N A Digital input N A Digital input N A Digital output Digital output N A Digital output Digital output Digital output Digital input Digital input Digital input Analog input N A N A Analog output Analog output Bi directional digital IO Bi directional digital IO Rev 0 Page 303 of 326 06 707 Location E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G20 G21 G22 G23 H1 Mnemonic OSD IN 15 VBI CS Type OSD video input miscellaneous DVDD IO Digital Interface Supply 3 3 V COMP2 OSD IN 10 OSD IN 11 OSD IN 12 RSET2 PVDD3 OSD IN 5 OSD OSD INI 7 OSD INI 8 OSD IN 1 digital Miscellaneous analog Miscellaneous analog Analog video out
403. rks in the same way as the automatic mode except that it always selects the highest pixel repetition factor the Tx core is capable of This makes the video timing independent of the audio sampling rate This mode is not typically used pr mode 1 0 2 Main Map Address 0xF43B 6 5 This signal is used to specify the pixel repetition mode selection This should be set to 00 unless a non CEA 861 standard video resolution must be supported Function pr mode 1 0 Description 00 default auto mode 01 max mode 10 manual mode 11 manual mode pr manual 1 0 TX2 Main Map Address 0xF43B 4 3 This signal is used to specify the ratio between the input pixel clock and the TMDS output clock when manual pixel repetition is enabled Function pr pll manual 1 0 Description 00 default x1 01 x2 10 x4 11 x4 pr value manual 1 0 TX2 Main Address OxF43B 2 1 This signal is used to specify the user programmed pixel repetition sent to the downstream sink This field is used in manual pixel repetition Function pr value manual 1 0 Description 00 default x1 01 x2 10 x4 11 x4 vic to rx 5 0 TX2 Map Address 0xF43D 5 0 Read Only This signal is used to set the AVI InfoFrame video code VIC to send to the downstream sink Function vic to rx 5 0 Description XXXXXX VIC sent to the downstream sink 6 10 4 Video Related Packets and InfoFrames Video related packets and In
404. rogrammed via CTS MANUAL 19 0 Rev 0 Page 230 of 326 Table 60 Recommended and Expected CTS Values for 32 kHz Audio cts manual 19 0 TX2 Main Map Address 0xF407 3 0 Address OxF408 7 0 Address 0xF409 7 0 This signal is used to manually set the Cycle Time Stamp CTS This parameter is used with the N parameter to regenerate the audio clock in the receiver n 19 0 TX2 Main Map Address 0xF401 3 0 Address OxF402 7 0 Address 0xF403 7 0 This signal is used to specifies the audio clock regeneration parameter N This parameter is used with CTS to regenerate the audio clock in the receiver 32 kHz Pixel Clock MHz N CTS 25 2 1 001 4576 28125 25 2 4096 25200 27 4096 27000 27 1 001 4096 27027 54 4096 54000 54 1 001 4096 54054 74 25 1 001 11648 210937 210938 74 25 4096 74250 148 5 1 001 11648 421875 148 5 4096 148500 Other 4096 Measured cts internal 19 0 TX2 Main Map Address OxF404 3 0 Address 0 405 7 0 Address OxF406 7 0 Read Only This signal is used to readback the automatically generated Cycle Time Stamp CTS parameter This parameter is used with the N parameter to regenerate the audio clock in the receiver Table 61 Recommended N and Expected CTS Values for 44 1 kHz and Multiples U6 707 44 1kHz 88 2 kHz 176 4 kHz Pixel Clock MHz N CTS N CTS N CTS 25 2 1 001 7007 31250 14014 31250 2
405. rom Internal OSD Blend 1 0x02 From Secondary Input Channel 0x03 From RX Input 0x04 From Secondary VSP 0x05 From Horizontal Pre scaler p2i inp sel 3 0 IO Map Address 0x1A06 7 4 This signal is used to select the video source for the Progressive to Interlaced converter Function p2i inp sel 3 0 Description 0x00 default From Primary VSP 0x01 From Internal OSD Blend 1 0x02 From Secondary Input Channel 0x03 From RX Input 0x04 From Primary Input Channel osd blend inp sel 3 0 IO Map Address 0x1A06 3 0 This signal is used to select the video source to the OSD Blend block Function osd blend inp sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Secondary VSP Ptol Converter 0x02 From Primary VSP 0x03 From Secondary Input Channel 0x04 From RX Input osd blend inp 2 sel 3 0 IO Map Address 0x1A08 3 0 This signal is used to select the video to be blended on OSD channel 2 Function osd blend inp 2 sel 3 0 Description 0x00 default From Primary Input Channel 0x01 From Secondary VSP Ptol Converter 0x02 From Primary VSP 0x03 From Secondary Input Channel 0x04 From RX Input For example when using the ADV8005 in mode 3 described in Section 2 1 4 the following register settings are needed to configure the video data path 1A 1A03 34 Output of OSD blend to HDMI Tx1 Output of Secondary VSP to HDMI Tx2 1A 1A04 30 Output of OSD blend to HD encoder S
406. rs The audio data carried across the HDMI link to the downstream sink which is driven by a TMDS clock only does not retain the original audio sample clock The task of recreating this clock at the sink is called Audio Clock Regeneration ACR There are varieties of ACR methods that can be implemented in an HDMI sink each with a different set of performance characteristics The HDMI specification does not attempt to define exactly how these mechanisms operate It does however present a possible configuration and defines the data items that the HDMI source shall supply to the HDMI sink in order to allow the HDMI sink to adequately regenerate the audio clock The HDMI specification also defines how that data shall be generated In many video source devices the audio and video clocks are generated from a common clock coherent clocks In that situation there exists a rational integer divided by integer relationship between these two clocks The ACR architecture can take advantage of this rational relationship and can also work in an environment where there is no such relationship between these two clocks that is where the two clocks are truly asynchronous or where their relationship is unknown SOURCE DEVICE SINK DEVICE DIVIDE CYCLE 128 x fs BY TIME N COUNTER VIDEO CLOCK 1 REGISTER N N 1N AND CTS VALUES ARE TRANSMITTED USING THE AUDIO CLOCK REGENERATION PACKET VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL 06076 008
407. rs in the ADV8005 in 4 4 4 mode Therefore if video input to the device is not in this format it must be first converted to 4 4 4 Setting this bit to 1 converts video data to 4 4 4 exosd ps444 r444 conv IO Map Address 0x1B69 6 This bit is used to convert 4 2 2 data to pseudo 444 or to real 444 Function exosd ps444 r444 conv Description 0 default 1 Nothing done Pseudo444 to Real 444 conversion exosd rev bus is used to reverse the order of the video TTL input By default this is set to non reversed exosd rev bus IO Map Address 0 1 6 4 This bit is used to reverse the input video bus i e D 23 0 gt D 0 23 Function exosd rev bus Description 0 default Reverse the pin mapping on the OSD bus 1 Use the OSD bus as it comes from the pins exosd hs pol exosd vs poland exosd de pol configure the polarity of the input video timing signals These must be set depending on the polarity of the upstream IC If active low these register can be left at their default If these signals from the upstream IC are active high their polarity can be inverted exosd hs pol IO Map Address 0x1B69 0 This bit is used to set the polarity of the input External OSD HS timing signal Function exosd hs pol Description 0 default Input HS polarity doesn t change 1 Input HS polarity gets inverted exosd vs pol IO Map Address 0 1 69 1 This bit is used to set the polarity of the input E
408. s cleared by setting it to 1 vsync int 5 When set to 1 it indicates that leading edge detected on VSync input to Tx core Once set it remains high until it is cleared by setting itto 1 rx sense int 6 When set to 1 it indicates that TMDS clock lines voltage has crossed 1 8 V from high to low or Rev 0 Page 210 of 326 06 707 Bit Bit Position Description low to high Once set it remains high until it is cleared by setting it to 1 hpd int 7 When set to 1 it indicates that transition for high to low or low to high was detected on input HPD signal Once set it remains high until it is cleared by setting it to 1 Table 51 HDMI Tx Interrupt Bits in Main Map Register OXEC97 Bit Name Bit Position Description flag int 6 When set to 1 it indicates that the KSVs from the downstream sink have been read and available in the Memory Map Once set it remains high until it is cleared by setting itto 1 hdcp error int 7 When set to 1 it indicates that the HDCP EDID controller has reported an error This error is available in HDCP CONTROLLER ERROR Once set it remains high until it is cleared by setting it to 1 Table 52 Status Bits in Map Register 0xEC42 Bit Name Bit Position Description hpd state 6 See description for state on page 204 sense state 5 See description for rx sense state on page 204 6 8 EDID HDCP CONTROLLER STATUS The Tx
409. s content can sometimes introduce ringing artifacts This overshoot can be controlled by adjusting vim overshoot ctrl 11 0 according to user preference svsp vim scal overshoot ctrl 11 0 Secondary VSP Map Address 0xE647 7 0 Address OxE648 7 4 This signal is used to control the overshoot in the scaling of input video If set to a value larger than the default setting more overshoot is allowed Function svsp vim scal overshoot Description 11 0 0x080 default Default 3 3 2 5 Panorama Mode This feature is the same as for the PVSP If the scaled video has a different aspect ratio to the original and the horizontal scaling factor is larger than the vertical one the panorama function can be enabled using svsp vim pano en In effect this stretches the left and right most Rev 0 Page 147 of 326 06 707 sides of the input video to fill the output resolution This method keeps the original ratio in the centre of the screen Figure 60 explains the panorama mode scaling feature svsp vim scal pano en Secondary VSP Map Address OxE650 7 This bit is used to enable panorama scaling for the Secondary VSP Function svsp vim scal pano en Description 0 default Disable panorama 1 Enable panorama The position from which the output video becomes stretched is controlled using svsp vim scal pano pos 10 0 This allows the user to control the width of the sides of the output image Refer
410. s linked to the Serial Video RX interrupts Function int pin od en 2 0 Description 000 default All interrupts TTL 001 INTO open drain 010 INT1 open drain 100 INT2 open drain 111 All interrupts open drain int oe 2 0 IO Map Address 0x1ACC 6 4 This signal is used to enable the INTO and INT2 interrupt pins INTO is linked to the OSD interrupts is linked to the HDMI TX interrupts and INT2 is linked to the Serial Video RX interrupts Function int pin oe 2 0 Description 000 default All interrupts tristated 001 INTO interrupt enabled 010 interrupt enabled 100 INT2 interrupt enabled 111 All interrupts enabled 8 1 1 Interrupt Duration The interrupt duration can be programmed independently for interrupt pin INT2 When an interrupt event occurs the interrupt pin INT2 becomes active with a programmable duration as described in this section intrq dur sel 1 0 IO Map Address 0x1A69 3 2 This signal is used to set the interrupt signal duration for the Serial Video RX interrupts output on pin INT2 Function intrq dur sel 1 0 Description 00 default 4 Xtal periods 01 16 Xtal periods 10 64 Xtal periods 11 Active until cleared Rev 0 Page 288 of 326 06 707 Note When the active until cleared interrupt duration is selected and the event that caused an interrupt ends the interrupt persists until it is cleared or masked 8 1 2 Storing Masked
411. s no need to change the setting of the field frame buffer It is recommended to leave the setting of the buffer number and the buffer size unchanged pvsp_fieldbuffer0_addr 31 0 Primary VSP Map Address 0xE800 7 0 Address 0 801 7 0 Address 0xE802 7 0 Address OxE803 7 0 This signal is used to set the start address of field frame buffer 0 Software should arrange memory space properly avoiding conflict between different buffers Function pvsp fieldbuffero addr 31 0 Description 0x004F 1A00 Default OxXXXXXXXX Start address of field frame buffer 0 pvsp fieldbufferl addr 31 0 Primary VSP Map Address 0xE804 7 0 Address 0xE805 7 0 Address 0xE806 7 0 Address OxE807 7 0 This signal is used to set the start address of field frame buffer 1 Software should arrange memory space properly avoiding conflict between different buffers Function pvsp fieldbuffer1 addr 31 0 Description Ox00CDAAOO Default OxXXXXXXXX Start address of field frame buffer 1 pvsp fieldbuffer2 addr 31 0 Primary VSP Map Address 0xE808 7 0 Address 0xE809 7 0 Address 0 80 7 0 Address OxESOB 7 0 This signal is used to set the start address of field frame buffer 2 Software should arrange memory space properly avoiding conflict between different buffers Function pvsp fieldbuffer2 addr 31 0 Description 0x014C3A00 Default OxXXXXXXXX Start address of field frame buffer 2 pvsp fieldbuffer3
412. s of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible This feature is highlighted in Figure 131 At the start of active video the first three pixels are multiplied by 1 8 1 2 and 7 8 respectively Approaching the end of active video the last three pixels are multiplied by 7 8 1 2 and 1 8 respectively All other active video pixels pass through unprocessed Figure 132 and Figure 133 show the difference between having this feature enabled and disabled This feature can be enabled using slope en LUMA CHANNEL WITH LUMA CHANNEL WITH ACTIVE VIDEO EDGE ACTIVE VIDEO EDGE DISABLED ENABLED 100 IRE 100 IRE 87 5 IRE 50 IRE 12 5 IRE 0 IRE 0 IRE Figure 131 Example of Active Video Edge Functionality 06398 082 06398 083 Figure 132 Example of Video Output with SD Active Video Edge Control Disabled Rev 0 Page 283 of 326 06 707 1 IRE FLT 100 50 06398 084 2 0 2 4 6 8 10 12 Figure 133 Example of Video Output with SD Active Video Edge Control Enabled slope en Encoder Map Address OxE482 7 This bit is used to enable the SD active video edge control Function slope en Description 1 Enabled 0 default Disabled pattern with sharp transitions is being output through the encoder and the user does not want slope en to have an effect because it softens the edges it is possible to use sd under limiter 1 0 and sd y min value to co
413. s reduced from the reference signal The range of this feature is specified for 7 5 of the nominal output from the DACs For example if the output current of the DAC is 4 33 mA the DAC gain control feature can change this output current from 4 008 mA 7 5 to 4 658 mA 47 596 To enable the gain for the relevant set of DACs dac4to6 tuning 7 0 and dac1to3 tuning 7 0 must be configured dac4to6 tuning 7 0 Encoder Map Address OxE40A 7 0 This register is used to set the gain for 4 6 output voltage Function dac4to6 tuning 7 0 Description 11000000 7 596 11000001 7 382 11000010 7 364 11111111 0 018 00000000 default 096 00000001 0 01896 00000010 0 03696 00111111 47 382906 01000000 47 596 daclto3 tuning 7 0 Encoder Map Address OxE40B 7 0 This register is used to set the gain for DACs 1 3 output voltage Rev 0 Page 268 of 326 06 707 Function dac1to3_tuning 7 0 Description 11000000 7 5 11000001 7 382 11000010 7 364 11111111 0 018 00000000 default 096 00000001 0 01896 00000010 0 03696 00111111 47 382906 01000000 47 596 The reset value of the control registers is 0x00 that is nominal DAC current is output Table 76 shows how the output current of the DACs varies for a nominal 4 33 mA output current Table 76 DAC Gain Control DAC Gain Register Value DAC Current mA Gain Note 0100 0000 0x40 7 500096 0011 1111 0x3F 7 382096 0011 1110
414. s set to 1 the sampling frequency used to determine the pixel repetition factor refer to Section 6 11 1 is not extracted from the input SPDIF stream and must be programmed in the 128 sf 3 0 field Note that the sampling frequency that is used in the Audio Sample packets sent to the downstream sink be read from the spdif sf 3 0 field The ADV8005 is capable of accepting SPDIF with or without an audio master clock input to through the input pin MCLK When the ADV8005 does not receive an audio master clock the ADV8005 uses the bit clock input via the SCLK pin to internally generate an audio master clock and determine the CTS value spdif sf 3 0 TX2 Main Map Address 0xF404 7 4 Read Only This signal is used to readback the audio sampling frequency from the SPDIF channel Rev 0 Page 227 of 326 06 707 Function spdif sf 3 0 Description 0000 default 44 1kHz 0001 NA 0010 48 kHz 0011 32kHz 0100 NA 0101 NA 0110 NA 0111 NA 1000 88 2kHz 1001 NA 1010 96kHz 1011 NA 1100 176 4kHz 1101 NA 1110 192kHz 1111 NA 6 11 3 3 DSD Audio The ADV8005 uses 1 bit Audio Sample packets to transmit DSD audio data across the HDMI link to the downstream sink The ADV8005 supports up to six channels of DSD data which be input onto six data lines clocked by the signal input to DSD_CLK The ADV8005 can be configured to receive a DSD stream by setting audio input sel 2 0 to 0b010 The mode of the DSD stream input to
415. s used in conjunction with an MPEG decoder MPEG decoders use embedded timing codes rather than using external HS and VS signals Similarly other ADI decoders HDMI Rxs can output video using embedded timing codes This register should be programmed depending on the timing method of the upstream IC Refer to Section 2 2 11 for more information on AV codes vid hs vs mode IO Map Address 0x1B4B 7 This bit is used to select the method of input timing Function vid hs vs mode Description 0 Use embedded SAV EAV codes 1 default Use external HS VS synchronization signals vid av pos sel IO Map Address 0x1B4B 3 This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes Rev 0 Page 53 of 326 06 707 Function vid av pos sel Description 0 default Generate HS coincident with EAV code 1 Generate HS VS based on 861 timing vid av split code IO Map Address 0x1B4B 2 This bit is used to control how AV codes are decoded replicated on or split across all channels Function vid av split code Description 0 default Decodes AV codes which are replicated on all channels 1 Decodes AV codes which are split across all channels vid av codes rep man en IO Map Address Ox1BAB 1 This bit is used to control the enable for AV source codes AV codes rep man is used instead of the auto based on the input video format Function
416. sc en control The HDMI Tx CSC mode can be configured using csc scaling factor 1 0 The CSC mode is used to define the fixed point position of the CSC coefficients which are located after csc scaling factor 1 0 in the TX Main Map Reference configuration scripts to configure the HDMI Tx CSCs are provided with the evaluation software csc en TX2 Main Map Address OxF418 7 This bit is used to enable the colour space converter Function csc en Description 0 default CSC Disabled 1 CSC Enabled scaling factor 1 0 TX2 Map Address 0 418 6 5 This signal is used to specify the CSC scaling factor The CSC scaling factor sets the fixed point position of the CSC coefficients including a4 b4 c4 and offsets Function csc scaling factor 1 0 Description 00 1 0 4096 to 4095 01 2 0 8192 to 8190 10 default 4 0 16384 to 16380 11 4 0 16384 to 16380 The characteristic equations for the HDMI Tx CSCs are captured in Equation 16 Equation 17 and Equation 18 112 0 ET 2 12 0 In Cs A3 12 0 292 4096 4096 4096 Equation 16 HDMI Tx CSC Channel Output Ou A In A 1 12 0 Ede Be B2 12 0 Cs B3 12 0 4 12 0 266 4096 4096 E 4096 Equation 17 HDMI Tx CSC Channel B Output Rev 0 Page 95 of 326 Out B 06 707 2 01 12 0 _ _ eno a 409 C4 12 a g 6
417. se the following formula C1 C2 2 Croaa Cstray Cog where Cis usually 2 to 3 pF depending on board traces and pin to ground capacitance is 4 pF for the ADV8005 Example 30 pF 50 pE C2 50 pF in this case 47 pF is the nearest real life cap value to 50 pF Encoder Component Placement External component placement must be carefully considered they should be kept as far away from noisy circuits as possible as close to the ADV8005 as possible and preferably on the same layer as the ADV8005 The external loop filter connected to PVDD3 COMP termination resistors Vrer and Rser circuits must all be laid out carefully otherwise noise may couple onto the SD or HD encoder outputs Any external filter and buffer components connected to the encoder analog outputs should be placed close to the ADV8005 to minimize the possibility of noise cross talk between neighboring circuitry The encoder analog output traces should be kept as short as possible to reduce the possibility of any signal integrity issues and to minimize the effect of trace capacitance on output bandwidth HDMI Transmitter Component Placement External component placement must be carefully considered they should be kept as far away as possible from noisy circuits as close to the ADV8005 as possible and preferably on the same layer as the ADV8005 TX1 and TX2 resistors and PVDD5 and PVDD6 power supplies must all be carefully laid out other
418. sed to configure audio InfoFrames audioif pkt en TX2 Map Address OxF444 3 This bit is used to enable the Audio InfoFrame Function audioif pkt en Description 0 Disable audio InfoFrame 1 default Enable audio InfoFrame Table 64 Audio InfoFrame Configuration Registers HDMI Tx Main Bit Location Access Type Default Value Field or Byte Map Address OxEC70 2 0 R W 0b001 InfoFrame version number OxEC71 4 0 R W 0b01010 InfoFrame length OxEC72 7 0 R W 0600000000 Checksum OxEC73 7 0 R W 0600000000 Data Byte 1 0 74 7 0 R W 0600000000 Data Byte 2 OxEC75 7 0 R W 0500000000 Data Byte 3 OxEC76 7 0 R W 0500000000 Data Byte 4 OxEC77 7 0 R W 0500000000 Data Byte 5 OxEC78 7 0 R W 0600000000 Data Byte 6 OxEC79 7 0 R W 0600000000 Data Byte 7 OxEC7A 7 0 R W 00000000 Data Byte 8 OxEC7B 7 0 R W 00000000 Data Byte 9 OxEC7C 7 0 R W 00000000 Data Byte 10 As defined in the latest CEA 861 specification 2 Only used when auto checksum 0 6 11 7 ACP Packet The Audio Content Protection ACP packet is used for transmitting content related information about the active audio stream Using the ACP packet will be defined in the license agreement of the protected audio stream The contents of the ACP packet can be set via the set of Packet Map registers listed in Table 65 The user can enable the transmission of an ACP packet t
419. sed to set the number of times the Tx EDID HDCP controller will try to read the sink EDID after a failure Each time an EDID read fails with an PC Not Acknowledged this value of edid tries 3 0 is decremented Once the edid tries 3 0 reaches the value 0 the Tx EDID HDCP controller will not attempt to read the EDID until edid tries 3 0 is set to a value other than 0 This could be used if a sink asserts high its HPD signal before the DDC bus is ready resulting in several NACKs as the ADV8005 attempts to read the EDID edid tries 3 0 TX2 Main Map Address OxF4C9 3 0 This signal is used to control the number of times that the EDID read will be attempted if unsuccessful Function edid tries 3 0 Description XXXX Number of time the EDID HDCP controller attempts to read the EDID 6 12 5 EDID Reread Control If the EDID data from the sink is read in and the host determines that the data needs to be reread edid reread be set from 0 to 1 and the current segment set via edid segment 7 0 will be reread Rereading the sink EDID may be useful for example if the host finds that one EDID checksum read from the sink is invalid Note It is also possible to reread the EDID from the sink by toggling the Tx core power down system pd from 0 to 1 Rev 0 Page 241 of 326 06 707 edid reread TX2 Map Address 0xF4C9 4 This bit is used to request a the EDID controller to reread the current segment if toggled from
420. sense int is triggered and rx sense state is set to 1 The detection of TMDS clock terminations from downstream sink devices is useful to delay powering up the transmitter sections until the downstream sink devices are actually ready to receive signals A typical implementation for a sink is to tie the transmitter 5 V power signal to HPD through a series resistor In this case the ADV8005 will detect a high level on TX1 HPD TX2 for HDMI Tx 2 regardless of whether or not the downstream sink is powered on and ready to receive a TMDS stream For this reason it is best to wait for both the rx sense state and state to be high before powering up the Tx core when trying to achieve minimum power consumption system pd TX2 Main Map Address OxF441 6 This bit is used to power down the TX Function system pd Description 0 Normal operation 1 default Power down TX hpd state TX2 Main Map Address OxF442 6 Read Only This bit is used to readback the state of the hot plug detect Function hpd state Description 0 default Hot Plug Detect inactive low 1 Hot Plug active high hpd override 1 0 TX2 Main Map Address 0xF49F 5 4 This signal is used to select the source of the internal HPD signal Function hpd override 1 0 Description 00 default HPD from HPD pin and CDC HPD 01 HPD from CDC HPD 10 HPD from HPD pin 11 HPD set to 1 rx sense state TX2 Main Map Address OxF442 5 Read O
421. spectively of the attainable adjustment in NTSC mode Value OxFF and value 0x01 represent the upper and lower limits respectively of the attainable adjustment in PAL mode The hue adjust value is calculated using the following equation Hue Adjust 0 17578125 HCRa 128 where is the hue adjust control register decimal For example to adjust the hue by 4 write 0x97 to hue 7 0 128 1514 0x97 0 17578125 Rev 0 Page 265 of 326 06 707 where the sum is rounded to the nearest integer To adjust the hue by 4 write 0x69 to hue 7 0 128 1054 0 69 0 17578125 where the sum is rounded to the nearest integer hue 7 0 Encoder Map Address 0xE4A0 7 0 This register is used to set the SD hue adjust value Function hue 7 0 Description 0x00 default SD Hue Value 7 4 13 SD Brightness Detect The ADV8005 encoder core allows the user to monitor the brightness level of the incoming video data This feature is used to monitor the average brightness of the incoming Y signal on a field by field basis The information is read from the and based on this information the color saturation contrast and brightness controls can be adjusted for example to compensate for very dark pictures The luma data is monitored in the active video area only The average brightness register is updated on the falling edge of every VSYNC signal This can be monitored using brigh
422. t sync PCLK Digital Video Float this pin as it is disabled by default Sync DVDD IO Digital Interface Supply 3 3 V Rev 0 Page 305 of 326 Pin Type Bi directional digital IO Bi directional digital IO Bi directional digital IO N A N A N A N A N A N A N A N A N A N A N A N A N A Digital output Digital output Digital input Digital input Bi directional digital IO Bi directional digital IO N A N A N A N A N A N A N A N A N A N A N A Digital output N A Digital output Digital output Digital input Digital input N A 06 707 Location K4 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K20 K21 K22 K23 L1 L2 L3 L4 L7 L8 L9 L10 L11 L12 L13 L1 L15 L16 L17 L2 L2 L2 L2 M gt gt 2 w M4 M7 M8 M9 M10 Mnemonic Type Description if Unused wp Gp fen Ground y E amp 8 V G G G GND G G G DDC1_SCL GND N N N qp O Px TX1_0 HDMI Tx1 Float this pin 1 0 HDMI Tx1 Float this pin P 32 Digital video Float this pin as it is disabled by default input P 34 Digital video Float this pin as it is disabled by default input P 35 Digital video Float this pin as it is disabled by default input 1 8V Digi Power Supply D D D
423. t Y on rising edge of clock 1 C on rising edge of clock vid ddr edge sel IO Map Address 0x1B4A 3 This bit is used to select which edge the first sample of DDR data is latched on Function vid ddr edge sel Description 0 default Posedge data first 1 Negedge data first Using the pixel clock as a reference ADV8005 expects the Y sample on a rising edge and then a chroma sample on the falling edge When vid_ddr_yc_swap is set ADV8005 expects a chroma sample on the rising edge and the Y sample on the falling edge vid_swap_cb_cr_422 can be used to swap the order of the chroma data By default ADV8005 expects a sequence of Cb Cr Cb Cr When vid swap cb cr 422 is set ADV8005 expects a sequence of Cr Cb Cr Cb vid swap cb cr 422 IO Map Address 0x1B49 7 This bit is used to swap the order of the C data when decoding 4 2 2 data Function vid swap cb cr 422 Description 0 default Cb Cr decoding 1 Cr Cb decoding vid ps444 r444 conv is used to convert from pseudo 444 video data to real 444 processing occurs in the ADV8005 in 4 4 4 mode Therefore if video input to the device is not in this format this must be first converted to 4 4 4 Setting this bit to 1 converts video data to 4 4 4 Rev 0 Page 52 of 326 06 707 vid ps444 r444 conv IO Map Address 0x1B49 6 This bit is used to convert 4 2 2 data to pseudo 444 or to real 444 Function vid ps444 r444 conv Description 0
424. t byte lanes are to be matched to 200 mils 5 08 mm of each other 470 series termination resistors should be placed as close to the source 8005 as possible on the following signals e Address signals DDR A12 DDR A0 and DDR BA0 DDR BA2 e Clock differential signals DDR CK and DDR use discrete resistors for these two signals e Control signal DDR and command signals DDR CSB DDR RASB DDR CASB and DDR WEB e Data mask signals DDR DM3 DDR Rev 0 Page 296 of 326 06 707 470 series termination resistors should be placed in the middle of the trace on the following signals e Data bus signals DDR DQ31 DDR e Data strobe signals DDR DQS3 DDR DQS3B DDR DQSO DDR DQSOB The DDR2 reference voltage DDR VREF should be routed as far away as possible from other signals to avoid any variations on the voltage This trace should be wide There should be a 100 nF decoupling cap close to the DDR2 reference voltage pins as well as the ADV8005 reference pin Power Supply Bypassing It is recommended to bypass each power supply pin with a 0 1 uF and a 10 nF capacitor where possible The fundamental idea is to have a bypass capacitor within 0 5 cm of each power pin Current should flow from the power plane to the capacitor to the power pin The power connection should not be made between the capacitor and the power pin Generally the best approach is to place a via underneath the 10 nF capacitor pads down
425. t color space selected using yuv out If the user needs to automatically update the CSC coefficients the following procedure is followed If the user selects the RGB output color space the ED HD CSC matrix scaler uses the following equations 0 5 B GY x Y BU x Pb Note Subtractions in these equations are implemented in the hardware The following registers need to be programmed with these values gy 9 0 Reg 0xE405 7 0 Reg OxE403 1 0 e gu 9 0 Reg 0xE406 7 0 Reg 0 404 7 6 gv 9 0 Reg 0xE407 7 0 Reg 0 404 5 4 e 9 0 Reg 0xE408 7 0 Reg 0 404 3 2 e rv 9 0 Reg 0xE409 7 0 Reg 0 404 1 0 On powerup the CSC matrix is programmed with the default values shown in Table 74 Table 74 ED HD Manual CSC Matrix Default Values Register Default 0x03 0x03 0x04 OxFO 0x05 Ox4E 0x06 OxOE 0x07 0x24 0x08 0x92 0x09 0 7 When the ED HD manual matrix adjust feature is enabled the default coefficient values in Reg 0 403 to Reg 0 409 are correct for the HD color space only The color components are converted according to the following 1080i and 720p standards SMPTE 274M SMPTE 296M Y 1 575 G 0 468 0 187Pb B Y 1 855Pb The conversion coefficients should be multiplied by 315 before being written to the ED HD CSC matrix registers This is reflected in the default values for gy 0x13B gu
426. t detect val 7 0 bright detect val 7 0 Encoder Map Address 0xE4BA 7 0 Read Only This register is used to adjust the SD brightness value Function bright detect val 7 0 Description OxXX Larger settings results in a brighter output 7 4 14 SD Brightness Control When this feature is enabled the SD brightness WSS control register setup 6 0 is used to control brightness by adding a programmable setup level onto the scaled Y data To enable this feature setup en must be configured setup en Encoder Map Address 0xE487 3 This bit is used to enable the SD brightness control feature Function setup en Description 1 Enabled 0 default Disabled For NTSC with pedestal the setup can vary from 0 IRE to 22 5 IRE For NTSC without pedestal and for PAL the setup can vary from 7 5 IRE to 15 IRE Refer to Figure 118 for more details The SD brightness control register is an 8 bit register The seven LSBs of this 8 bit register are used to control the brightness level which can be a positive or negative value For example to add a 20 IRE brightness level to an NTSC signal with pedestal the procedure is as follows 0 x SD Brightness Value 0 x IRE Value 2 015631 0 x 20 x 2 015631 0 x 40 31262 0x28 To add a 7 IRE brightness level to a PAL signal write 0x72 to setup 6 0 0 x SD Brightness Value Rev 0 Page 266 of 326 06 707 0 x IRE Value x 2 075631 0 x 7 x 2 015631
427. t driver capacitance loading should be limited to less than 15 pF This can be accomplished easily by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV8005 creating more digital noise its power supplies Particular attention must be paid to the routing of clock and sync signals for example PCLK OSD_CLK HS OSD HS VS OSD VS DE 5 DE XTALN and XTALP Any noise that gets onto these signals can add jitter to the system Therefore the trace length should be minimized and digital or other high frequency traces should not be run near it XTAL and Load Cap Value Selection The ADV8005 requires a 27 MHz crystal Figure 144 shows an example of a reference clock circuit for the ADV8005 Special care must be taken when using a crystal circuit to generate the reference clock for the ADV8005 Small variations in reference clock frequency can impair the performance of the ADV8005 Rev 0 Page 297 of 326 06 707 ATpF 47 V 7 Figure 144 Crystal Circuit These guidelines are followed to ensure correct operation e Usethe correct frequency crystal 27 MHz recommended Tolerance should be 50 ppm or better e Know the Coa for the crystal part number selected The value of capacitors and C2 must be matched to the Cia for the specific crystal part number in the user s system To find C1 and C2 u
428. t elements of the OSD for example the text images icons and so on In other words the regions define how the OSD pixels to be displayed are stored in DDR2 memory The equivalence between OSD components and regions can be found in Table 34 A maximum of 256 regions can be displayed simultaneously on the screen Note Only the regions being displayed at a given time count and not the total on the whole OSD so this number should be more than enough for even the most complex OSD For example if the designed OSD uses the OSD Menu bar component shown in Figure 85 and the user is moving through the icon menu there will be three regions in use at the time when the selected icon is Nodel that is the elements from the same level Nodel Node5 and Node6 When the selected icon is Node3 there will be three regions in use that is Node2 Node3 and Node4 When the selected icon is OSD region OSD plane Background Video Figure 84 Definition of OSD Region Table 34 Regions Used for OSD Components Component Number of Regions Needed in Hardware OSDLabel 1 OSDImage 1 OSDHistogram 1 OSDKeyboard 2 OSDProgressbar 2 OSDTextbox 1 OSDMenubar One region per item on each level OSDListbox One region per item OSDTimer 0 OSDIptextbox 1 Node7 there will be two regions in use that Node7 and Node8 Note how the efficient translation of components to regions means that it is almost
429. ters can be used to enable each corresponding demo function pvsp demo window rnr enable Primary VSP Map Address OxE87E 4 This bit is used to enable the RNR in the demo window Function pvsp demo window rnr ena Description ble 0 default Disable RNR in demo window 1 Enable RNR in demo window pvsp demo window enable Primary VSP Map Address 0xE87E 3 This bit is used to enable the MNR in the demo window Function pvsp demo window mnr en Description able 0 default Disable MNR in demo window 1 Enable MNR in demo window pvsp demo window bnr enable Primary VSP Map Address OxE87E 2 This bit is used to enable the BNR in the demo window Rev 0 Page 134 of 326 Function U6 707 pvsp demo window bnr ena ble Description 0 default 1 Disable BNR in demo window Enable BNR in demo window pvsp demo window cadence enable Primary VSP Map Address OxES7E 1 This bit is used to enable the cadence detection in the demo window Function pvsp demo window cadence enable Description 0 default 1 Disable Cadence detection in demo window Enable Cadence detection in demo window pvsp demo window enable Primary VSP Map Address OxE87E 0 This bit is used to enable the ULAI in the demo window Function pvsp demo window ulai en able Description 0 default 1 Disable ULAI in demo window Enabl
430. the HDMI status bit new tmds frq raw Function freqtolerance 3 0 Description 0100 Default tolerance in MHz for new TMDS frequency detection XXXX Tolerance in MHz for new TMDS frequency detection 5 3 CLOCK AND DATA TERMINATION CONTROL The ADV8005 provides the clock terma disable control for TMDS clock and data termination all Serial Video Rx input pins Rev 0 Page 188 of 326 06 707 clock terma disable HDMI RX Map Address 0xE283 0 This control is used to disable clock termination on port A It can be used when term auto is set to 0 Function clock terma disable Description 0 Enable Termination port A 1 default Disable Termination port A 5 4 MUTE STATUS av mute is used to indicate the status of the avmute bit in the general control packet As with the TMDS clock detection bits this register bit can be polled by the system software and the appropriate configuration done av mute HDMI RX Map Address OxE204 6 Read Only This bit is a readback of AVMUTE status received in the last General Control packet received Function av mute Description 0 default AVMUTE not set 1 AVMUTE set 5 5 DEEP COLOR MODE SUPPORT The ADV8005 supports HDMI streams with 24 bits per sample and deep color modes The addition of a video FIFO refer to Section 5 6 for more details allows for the robust support of these modes The deep color mode information that the ADV8005 extracts from the gen
431. the realtime frame latency Function svsp rb frame latency 2 0 Description 0 Frame latency svsp rb hsync latency 11 0 Secondary VSP Map Address 0xE6F3 7 0 Address 4 7 4 Read Only This signal is used to readback the realtime Hsync latency Function svsp rb hsync latency 11 0 Description OxXXX HSync latency svsp rb max latency 14 0 Secondary VSP Map Address 0xE6F5 7 0 Address OXEGF6 7 1 Read Only This signal is used to readback the maximum frame Hsync latency Upper 3 bit is VS latency Lower 12 bit HS latency Rev 0 Page 143 of 326 06 707 Function svsp rb max latency 14 0 Description OxXXX Maximum of frame latency svsp rb min latency 14 0 Secondary VSP Map Address 0xE6F7 7 0 Address OxE6F8 7 1 Read Only This signal is used to readback the minimum frame Hsync latency Upper 3 bit is VS latency Lower 12 bit HS latency Function svsp rb min latency 14 0 Description OxXXX Minimum of frame latency 3 3 1 6 Freezing Output Video Output video can be frozen by disabling the VIM by setting svsp_enable_vim to 0 3 3 2 SVSP Video Input Module VIM Video Input Module VIM Input Video VIM Horizontal Vertical Cropper Scaler Write to DDR2 Figure 63 SVSP Video Input Module Figure 63 shows the structure of the SVSP VIM This can be broken up into three hardware blocks The VIM cropper can be used to crop an i
432. the start address of field frame buffer 6 Software should arrange memory space properly avoiding conflict between different buffers Function pvsp_fieldbuffer6_addr 31 0 Description 0x03073200 Default OxXXXXXXXX Start address of field frame buffer 6 3 2 1 5 Frame Latency Different resolutions have different frame latencies depending on the timing combination to and from the PVSP This is due to the increased processing required in converting and scaling video data Table 21 lists the frame latencies in normal mode for various resolutions Table 21 Frame Latency in Normal Mode Output Frame Rate 50 Hz 59 94 60 Hz 23 97 24 Hz 25 30 Hz Input Frame rate Timing 576p 720p 1080 480p 720p 1080p 720p 1080p 720p 1080p 4kx2k 50 Hz 576i 1 1 2 4 1080i 576p 0 1 1 4 720p 1080p 59 94 60 Hz 480i 0 1 1 4 10801 480 0 1 1 4 720p 1080p 23 97 24 25 30 720 1080 0 1 0 8 0 1 1 3 Hz means x x times the input video field frame A B means frame latency is not a fixed value it varies between A and B If cadence detection is disabled this value should be 0 3 1 4 with setting pvsp_frc_change_phase_en to 0 otherwise is 0 3 3 4 If progressive cadence detection is disabled this value should be 0 3 1 4 with setting pvsp_frc_change_phase_en to 0 otherwise it is 0 3 3 4 When crop or album mode is enabled frame latency will be different from what is listed in Table 21 In
433. the stronger the MNR noise reduction Function di mnr th min 3 0 Description 0010 default Normal strength MNR 0110 High strength MNR 3 2 3 9 Block Noise Reduction Rev 0 Page 126 of 326 06 707 The block noise reduction BNR algorithm removes blocky artifacts introduced into highly compressed video such as MPEG2 encoded video For the best results this function should be enabled when the input video is not scaled The BNR has excellent performance for high level block artifact patterns and it has smart block position detection BNR supports both interlaced and progressive input It can be enabled or disabled using di bnr enable The BNR level can be controlled by setting di detect scale line 3 0 di bnr disable local detect di bnr edge offset 7 0 di global strength gain 3 0 di bnr scale global hori 2 0 and di bnr scale global vert 2 0 The corresponding value for different reduction level is given in Table 25 Table 25 Corresponding Value for Block Noise Reduction Level Register Name High Middle Low di detect scale line 3 0 9 7 7 di bnr disable local detect 0 1 1 di edge offset 7 0 96 64 32 di bnr global strength gain 3 0 12 di bnr scale global hori 2 0 6 di bnr scale global vert 2 0 6 di bnr enable Primary VSP Map Address 0 84 6 This bit is used to enable block noise reduction BNR
434. tings for ED HD Sharpness Filter Gain Values Adaptive Filter Control Application The register settings in Table 81 are used to obtain the results shown in Figure 125 that is to remove the ringing on the input Y signal as shown in Figure 124 Input data is generated by an external signal source Table 81 Register Settings for Figure 125 Register Register Setting OxE400 OxFC OxE401 0x38 OxE402 0x20 OxE430 0x00 OxE431 0x81 OxE435 0x80 OxE440 0x00 0 458 OxAC OxE459 Ox9A OxE45A 0x88 0 458 0 28 0 45 Ox3F OxE45D 0x64 06398 075 Figure 124 Input Signal to ED HD Adaptive Filter The effects of selecting between the two adaptive filter modes using adapt bc can be seen in Figure 125 and Figure 126 Rev 0 Page 277 of 326 06 707 06398 076 Figure 125 Output Signal from ED HD Adaptive Filter Mode A 06398 077 Figure 126 Output Signal from ED HD Adaptive Filter Mode B 7 4 19 SD Digital Noise Reduction The ADV8005 encoder block offers a feature for digital noise reduction DNR DNR is applied to the Y data only A filter block selects the high frequency low amplitude components of the incoming signal DNR input select The absolute value of the filter output is compared to a programmable threshold value DNR threshold control Two DNR modes are available DNR mode and
435. tion pvsp bypass ddr mode Description 0 default Normal mode 1 Game mode External memory is not used in game mode Intra field interpolation is used for interlaced input Mosquito block noise reduction and sharpness are supported in game mode both for interlaced input and progressive input In game mode the following functions are not supported e Frame rate change e Motion adaptive de interlacing autodisabled e Cadence detection autodisabled e Random noise reduction autodisabled e correction autodisabled e Crop e Album mode The functions listed as autodisabled do not need to be manually disabled in game mode ADV8005 will automatically disable them when game mode is enabled Functions which are not listed as autodisabled must be manually disabled before game mode is enabled 3 2 1 7 Low Latency Mode Game mode has a very small frame latency but some processing functions cannot be supported in this mode ADV8005 provides another mode low latency mode which can support frame rate change scaling crop and album mode To enable low latency mode pvsp_frc_low_latency_mode should be set to 1 Frame latency in low latency mode is listed in Table 22 which shows the maximum frame latency is 1 4 x frame Table 22 Frame Latency in Low Latency Mode Output Frame Rate 50 Hz 59 94 60 Hz 23 97 24 Hz 25 30 Hz Input Frame rate Timing 576p 720p 1080 480 720 1080 720p 1080p 720p 1080p p 4kx
436. tion 2 2 3 The updither settings are shared for all channels primary secondary and RX Rev 0 Page 59 of 326 06 707 exosd ud bypass man en IO Map Address 0x1B6A 2 This bit is used to enable the manual bypass for the up dither Setting this bit enables the bypass to be used Function exosd ud bypass man en Description 0 default 1 Manual bypass disable Manual bypass enable exosd ud bypass man IO Map Address 0x1B6A 1 This bit is used to bypass the up dither block Function exosd ud bypass man 0 default 1 Description Disable bypass Enable bypass Refer to Section 2 2 12 2 for more information on the CSC controls for the secondary input channel 2 2 2 8 RX Input Channel The ADV8005 RX input channel incorporates an input formatter CSC and updither block The updither feature in the ADV8005 can be used to randomize quantization error preventing large scale patterns such as color banding in images Refer to Section 2 2 3 for more information on the updither block The updither block on the RX input channel can be controlled via the rx ud bypass man en and rx ud bypass man bits By default the manual bypass is disabled which means that the updither block cannot be bypassed The updither block configuration is outlined in Section 2 2 3 The updither settings are shared for all channels primary secondary and RX rx ud bypass man en IO Map Address 0x1B8A 2 This bit is used to ena
437. to 576p 1080p50 480p 1080p60 21 svsp m p2i vid 17 31 2 16 The PVSP PtoI does not have direct access to the data from the input pins but it can be utilized to convert a progressive input format to interlaced using the PVSP core bypass path by setting the bypass bit 3 2 3 16 Automatic Contrast Enhancement The Automatic Contrast Enhancement ACE block is used to intelligently enhance the contrast of the whole picture by making dark regions darker and bright regions brighter It is stable under scene changes as well as being robust in the presence of noise ACE supports both interlaced and progressive inputs and be enabled disabled using enable ace enable IO Map Address 0x1A30 7 This bit is used to enable the automatic contrast enhancement ACE block Function ace enable Description 0 default Bypass A C E 1 Enable A C E 3 3 SECONDARY VSP 3 3 1 Introduction to SVSP Rev 0 Page 136 of 326 06 707 Secondary VSP FFS Output Progressive Video to Interlaced Read from DDR2 Write to DDR2 Figure 62 ADV8005 SVSP Figure 62 shows the structure of the SVSP The SVSP comprises of four sections the VIM the VOM a controller which is the FFS and a PtoI converter The SVSP can be used to offer the option of a second output resolution to the user The structure of the SVSP is similar to the PVSP but it is much simpler in design
438. to Figure 60 for more details svsp vim scal pano pos 10 0 Secondary VSP Map Address 0xE651 7 0 Address 0xE652 7 5 This signal is used to define the width of the output video frame which is not stretched when panorama mode is enabled but rather scaled properly The maximum value of this register is set by svsp vim crop width svsp vim scal out height svsp vim crop height svsp vim scal out width 2 This register sets half the width of the output frame which is to be scaled normally By default this register is set to 0 which means that all the input frame will be stretched It is therefore recommended that this register is set by the user before enabling the panorama function Function svsp vim scal pano pos 10 0 Description 0x000 default Default OxXXX Width of not stretched image 3 3 2 6 Pixel Packer At the back end of the VIM the pixel packer converts input video to word packets suitable for writing to external memory The operation of this hardware block is similar to the pixel packer in the PVSP The SVSP manages pixels in 8 bit precision Pixels in external memory have two different data formats which can be selected using svsp ex mem data format 1 0 e 24 bit YCbCr e 16 bit YCbCr 4 2 2 svsp ex mem data format 1 0 Secondary VSP Map Address OxE611 7 6 This signal is used to set the data format in external memory Function svsp ex mem data format 1 Description 0 01 YCbCr 8b 8b 8b 1
439. to the power plane refer to Figure 143 via to GND layer and GND pin 10nF 0 1uF via to VDD pin VDD supply Figure 143 Recommended Power Supply Decoupling It is recommended to individually filter all supplies to prevent switching noise on some supplies coupling onto other more sensitive supplies For example DVDD consumes a significant amount of current and will also suffer significant switching noise DVDD must be isolated from more sensitive supplies such as PVDD3 PVDD5 and PVDD6 The DVDD and DVDD DDR supplies should be connected to the same supply PVDD DDR should be filtered from DVDD to provide noise free power supply It is recommended to use a single ground plane for the ADV8005 Careful attention must be paid to the layout of any internal power supply planes when traces run on adjacent layers traces on a layer directly above or below a power supply layer must not cross between two power supply planes as this will impact the return current paths General Digital Inputs and Outputs The trace length that the digital inputs outputs have to sink source should be minimized Longer traces have higher capacitance which requires more current that can cause more internal digital noise Shorter traces reduce the possibility of reflections It is recommended to route traces in the shortest trace length possible and keep the number layer transitions to a minimum If possible the digital outpu
440. ts It can be enabled or disabled by asserting or de asserting register di_ulai_enable di ulai enable Primary VSP Map Address OxE84C 3 This bit is used to enable the ultra low angle de interlacing algorithm ULAT Function di ulai enable Description 0 Disable ULAI 1 default Enable ULAI 3 2 3 5 Cadence Detection The ADV8005 cadence detection can handle multiple different types of cadences typically introduced when content originated as film format but was converted into interlaced format for broadcast Examples of such conversion can be seen in Figure 54 The PVSP is able to detect arbitrary cadences and even unknown cadence modes with per pixel correction for combing artifacts There are several features of cadence detection including the reliable detection of 2 2 cadences for PAL video and the detection of poor editing techniques often found in films converted to video standards this may introduce artifacts These artifacts are caused by multiple cadences in the same source as well as fast switching from film to video or between different cadences For an interlaced video input cadence detection can be enabled or disabled by asserting or de asserting di cadence enable For progressive Rev 0 Page 123 of 326 06 707 video input cadence detection can be enabled or disabled by asserting or de asserting pcadence enable di cadence enable Primary VSP Map Address OxE84C 2 This bit is used to enable cadence detecti
441. ts input video to word packets suitable for writing to external memory Refer to Figure 55 for more details on where the pixel packer is located in the hardware Depending on the format of the input video there are four different packing formats e 12 bit 4 4 4 YCbCr e 10 bit 4 4 4 YCbCr e 12 bit 4 2 2 YCbCr 8 bit 4 2 2 YCbCr There is a trade off in the number of bits that can be stored A higher number of bits means the video stored will be stored at a higher quality however this will reduce the available DDR2 memory bandwidth for other functions such as OSD read write The data format can be set the pvsp ex mem data format 1 0 register This register can be set at any time but it may take some time not more than 300 ms to become valid This delay is related to the ADV8005 taking control of the memory format change to avoid the display of garbage information This information is important when calculating the field frame buffer sizes as explained in Section 3 2 1 pvsp ex mem data format 1 0 Primary VSP Map Address 0xE829 4 3 This signal is used to set the data format in external memory Function pvsp ex mem data format 1 Description 0 00 default YCbCr 12b 10b 10b 01 YCbCr 8b 8b 8b 10 YCbCr 4 2 4 12b 11 YCbCr 4 2 2 8b Table 23 indicates the number of bytes required when storing a particular type of video data Table 23 Bytes per Pixel pvsp ex mem data format Format in Memory Bytes per Pixel
442. udio samples s The layout bit in the Audio Sample packet header and the sample present spX bit are determined based on the values programmed in the audioif cc 2 0 field For example if audioif cc 2 0 is set to 0b001 which indicates stereo audio the layout bit will be zero and all Audio Sample subpackets will contain information for channels 1 and 2 If audioif cc 2 0 is set to 05011 indicating four channels the layout bit will be 1 sample 0 will be 1 sample present spl will be 1 sample present sp2 will be 0 and sample present sp2 will be 0 Rev 0 Page 235 of 326 06 707 Audio Sample Packet Header Layout bit Audio Sample Packet Header sample presentspX bit Audio Sample Packet Header sample presentspX bit Audio Sample Subpacket X Audio Sample Subpacket X CI 23 20 2 X 1 CI 23 20 1 Cr 23 20 2 X 2 Cr 23 20 2 Audio Sample Subpacket X Not Present Figure 106 Definition of Channel Status Bits 20 to 23 6 11 6 Audio InfoFrame The audio InfoFrame allows the sink to identify the characteristics of an audio stream before the channel status information is available The ADV8005 can be configured to transmit audio InfoFrame by setting audioif_pkt_en to 1 When the transmission of audio InfoFrame is Rev 0 Page 236 of 326 06 707 enabled the ADV8005 transmits an audio InfoFrame once every two video fields Table 64 provides the list of registers that can be u
443. ust be converted to 10 bit or 12 bit for output The operation of the updither block can be seen in Figure 35 When converting to a higher bit width the ADV8005 updither block first converts to a bit width of 14 and then down converts to 12 and 10 bit width 8 bit video source 8 to 14 bit up dithering 14 to 12 bit down dithering 12 to 10 bit 10 bit video output down dithering Figure 35 Updither Operation 12 bit video output updither level 1 0 is used to configure the updither algorithm level This should be configured depending on the input and output from the block For example if the input video is 8 bit data and the output is 12 bit data this should be set to the highest level updither level 1 0 IO Map Address 0x1A0D 5 4 This signal is used to set the sharpness of the updither block s HPF processing of the video data When this signal is set to low the characteristic of the dither block s HPF gives smoother output video When this signal is set to high the characteristic of the dither block s gives sharper output video Function updither level 1 0 Description 00 Low updither 11 High updither 2 2 4 Clock Configuration This section describes the method of configuring the various clocks of the ADV8005 using the automatic controls video in id 7 0 exosd id 7 0 and rx in id 7 0 These controls can be employed to automatically configure the internal clocks for the following e Pi
444. utlined in this section de v beg e pos 6 0 IO Map Address 0x1B8C 7 1 This signal is used to specify the DE vertical beginning position for even fields if CEA 861 timing generation is enable and manual values selected Function de v beg e 6 0 Description OxXX assert de when Icount reaches OxXX on even fields de v beg o pos 6 0 IO Map Address 0x1B8C 0 Address 0x1B8D 7 2 This signal is used to specify the DE vertical beginning position for odd fields if CEA 861 timing generation is enable and manual values selected Function de v beg o pos 6 0 Description OxXX assert de when Icount reaches OxXX on even fields de h beg pos 9 0 IO Map Address Ox1B8D 1 0 Address 0x1B8E 7 0 This signal is used to specify the DE horizontal beginning position counting from the EAV if CEA 861 timing generation is enable and manual values selected Function de h beg 9 0 Description OxXX assert de when hcount reaches OxXX hs beg pos 9 0 IO Map Address Ox1B8F 7 0 Address 0x1B90 7 6 This signal is used to specify the HS beginning position counting from the EAV if CEA 861 timing generation is enable and manual values selected Function hs beg pos 9 0 Description OxXX assert hs when hcount reaches OxXX hs end pos 9 0 IO Map Address 0x1B90 5 0 Address 0x1B91 7 4 This signal is used to specify the HS ending position counting from the EAV if CEA 861 timing generation is enabl
445. utput horizontal resolution of scaler in the VIM Function svsp vim scal out width 10 Description 0 0x000 default Default 0 Output width of VIM scaler Image before Scaler in Scaled Image Scaler m VIM SVSP CROP HEIGHT SVSP VIM SCAL OUT HEIGHT lt SVSP_VIM_CROP_WIDTH SVSP VIM SCAL OUT WIDTH Figure 65 VIM Scaler Dimensions 3 3 2 3 Scaler Interpolation Mode This section describes the method for scaling the input video data The purpose of the scaler is to allow different input formats to be displayed on a screen with a fixed resolution This can allow lower resolution video for example 480p to be upscaled to a high definition format such as 1080p This can improve the overall quality of a video signal when displayed on a high definition television The four options of video scaling are listed below and are chosen using svsp vim scal type 1 0 Refer to Section 3 for more information on the types of scaler algorithm svsp vim scal type 1 0 Secondary VSP Map Address OxE646 7 6 This signal is used to set the VIM scaling algorithm In most cases the scaler type should be left at the default setting Rev 0 Page 146 of 326 06 707 Function svsp vim scal type 1 0 Description 00 default Proprietary ADI Algorithm 01 Sharp 10 Smooth 11 Bilinear 3 3 2 4 VIM Miscellaneous Control The following registers are used i
446. utput timing registers can be accessed using this protocol It should be noted that the output video will be interrupted using this protocol Rev 0 Page 156 of 326 06 707 pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 Start pvsp lock vom 0 pvsp update vom 1 pvsp enable ffs 0 pvsp enable vim 0 Disable VIM FFS pvsp enable 1 pvsp lock vom 0 pvsp update vom 1 pvsp enable ffs 0 pvsp enable vim 0 pvsp enable vom 0 pvsp lock vom 0 pvsp update vom 1 Disable VOM pvsp enable ffs 0 pvsp enable vim 0 Configure all registers pvsp enable vom 0 pvsp lock vom 0 pvsp update vom 1 pvsp enable ffs 1 pvsp enable vim 0 Enable FFS by assert enable vom 0 pvsp enable ffs pvsp lock vom 0 pvsp update vom 1 pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vim pvsp lock vom 0 pvsp update vom 0 pvsp enable ffs 1 pvsp enable vim 1 pvsp enable vom 1 Enable VOM by assert pvsp enable vom pvsp lock vom 0 pvsp update vom 1 Figure 70 Reboot Protocol Flowchart Figure 70 shows the process for the reboot protocol for the PVSP This is exactly the same for the SVSP with the appropriate registers replaced Rev 0 Page 157 of 326 06 707 3 4 3 Gentle Reboot Protocol The gentle reboot is used to reboot the PVSP with different configuration settings but does not interrupt the output timing The output video is frozen during
447. vbackporch 8 0 8 0 8 0 8 0 8 OxE8 0 8 OxE8 OxE8 0 8 0 8 0 8 0 8 0 0 8 0 0 56 57 58 59 5 5 5 50 5 5F 60 61 62 63 64 65 69 1 69 0 576p 0x02 OxDO 10 00 0 0 0x00 10 40 0 00 10 44 0 02 0 40 10 00 0x05 10 00 10 05 10 00 10 27 0 720 50 0 05 0x00 0x01 OxB8 10 00 0x28 0x00 10 02 0 0 0x00 0 05 10 00 0x05 10 00 10 14 1 1080p50 0x07 x80 0x02 0x10 10 00 0 2 0x00 10 94 0 04 0x38 10 00 0 04 10 00 0 05 10 00 0x24 1 0 02 x80 0 00 0x10 10 00 0x60 0x00 0x30 10 01 0 0x00 0 0 10 00 0x02 10 00 0x21 0 480 0 02 OxDO 0 00 0x10 10x00 0 0x00 0 3 10 01 jJOxEO 10 00 0x09 10 00 0x06 10 00 0 1 p 0 720p60 0x05 0x00 0 00 Ox6E 0x00 10 28 10 00 0x02 0 0 0x00 0 05 10 00 0x05 10 00 10 14 1 1080p60 0x07 x80 0x00 0x58 0x00 0 2 0x00 0x94 0 04 0x38 10 00 0 04 10 00 05 10 00 10 24 1 1080p24 0x07 x80 0x02 Ox7E 0x00 0 2 0x00 10 94 0 04 0x38 10 00 0 04 10 00 05 10 00 0x24 1 The size of output images of the VOM scaler can be smaller than that defined by the parameters of the output port that is album mode The starting position for the PVSP output video can be set using pvsp dp video h start 12 0 and dp video start 12 0 Figure 61 sh
448. vert progressive video to interlaced video It drops odd or even lines of the progressive video based on the output interlaced video field signal Support is limited to 480p and 576p The associated interlaced timing signals can be generated in the PtoI hardware block The Ptol converter in the SVSP cannot operate in standalone mode it must be connected to the SVSP The PtoI hardware can be enabled using svsp p2i enable svsp p2i enable Secondary VSP Map Address OxE649 5 This bit is used to enable the Ptol in Secondary VSP Function svsp p2i enable Description 0 default Disable 1 Enable The input video to the PtoI block is defined using svsp p2i vid 7 0 For more details on the values which must be programmed into this register refer to Table 32 Rev 0 Page 154 of 326 06 707 svsp p2i vid 7 0 Secondary VSP Map Address OxE64A 7 0 This register is used to set the VIC of the PtoI in Secondary VSP Function svsp p2i vid 7 0 Description 0x00 default Default Table 32 VID for Ptol Input Timing Formatto 576p 480p 21 svsp s p2i vid 17 2 3 4 VSP REGISTER ACCESS PROTOCOLS This section is used to describe the methods available to the user to update the VSP registers The following types of register access protocols are available e Bootup protocol e Reboot protocol e Gentle reboot protocol e VOM set protocol e Free access protocol These protocols are recom
449. vid av codes rep man en Description 0 default AV codes replicated based on internal flag 1 Use i2c bit vid av codes rep man IO Map Address 0 1 4 0 This bit is used to specify if the codes are replicated or not Codes replicated 4 4 4 FF FF FF 00 00 00 00 00 00 AV AV AV Codes not replicated FF 00 00 AV Function vid av codes rep man Description 1 0 default AV codes are replicated AV codes are not replicated The updither feature in the ADV8005 can be used to randomize quantization errors preventing large scale patterns such as color banding in images Refer to Section 2 2 3 for more information on the updither block The updither block on the video TTL input channel can be controlled via the vid ud bypass man en and vid ud bypass man bits By default the manual bypass is disabled which means that the updither block cannot be bypassed The updither block configuration is outlined in Section 2 2 3 The updither settings are shared for all channels primary secondary and RX vid ud bypass man en IO Map Address 0x1B4A 2 This bit is used to enable the manual bypass for the up dither Setting this bit enables the bypass to be used Function vid ud bypass man en Description 0 default Manual bypass disable 1 Manual bypass enable vid ud bypass man IO Map Address 0x1B4A 1 This bit is used to bypass the up dither block Function vid ud bypass man Descriptio
450. will be used while svsp autocfg output vid is 0 Function svsp dp hpolarity Description 0 default Low 1 High Table 31 Output Port Configuration Settings for Example Output Formats Output Timing decount hfrontporch HSync hbackporch activeline Vfrontporch VSync Mbackporch vpol OxE 0 6 OxE6 632 633 634 635 636 637 638 639 63A 638 63 630 6 63F 640 641 42 7 42 6 Rev 0 Page 152 of 326 06 707 Output Timing decount hfrontporch HSync hbackporch activeline Vfrontporch VSync Mbackporch vpol OxE OxE 0 0 6 0 6 632 633 634 635 636 637 638 639 63A 638 63 630 63E 63F 640 641 42 7 42 6 576i 0 5 0 00 0x00 0 0 0x00 0x48 0 01 0 01 0 40 09 0 0 576 0 5 0x00 0x03 x00 x10 x00 Oxll 0x00 0x48 0x00 0 01 10 40 0 01 0x40 0x09 0 0 0 720 50 OxAO 0x00 6 x00 0 x00 0x37 0x00 0 5 0x00 0 01 10 40 0 01 0x40 0x05 x00 1 1 1080i50 OxFO x00 10 84 0x00 OxOB x00 0x25 0x00 0x87 0x00 0 01 10 00 0x01 0x40 0x09 10 00 1 1 1080p50 OxFO 0x00 10 84 0x00 0 x00 0x25 0x00 0x87 0x00 0 01 10 00 0x01 0x40 0
451. wise the HDMI transmitter performance for example HDMI compliance testing may be reduced Power Supply Design and Sequencing The ADV8005 requires only two regulators one 3 3 V and one 1 8 V The recommended power supply design is illustrated in Figure 145 If using more than 1 8 V regulator to supply ADV8005 it must be ensured that DDR PVDD DDR and DVDD are supplied by the same regulator The power up sequence of the ADV8005 is as follows Rev 0 Page 298 of 326 06 707 Hold RESET and pins low Bring up the 3 3 V supplies DVDD IO AVDDI and AVDD2 A delay of a minimum of 20 ms is required from the point in which the 3 3 V reaches its minimum recommended value that is 3 14 V before powering up the 1 8 V supplies Bring up the 1 8 V supplies DVDD CVDDI PVDDI PVDD2 PVDD3 AVDD3 DVDD DDR and PVDD DDR These should be powered up together that is there should be a difference ofless than 0 3 V between them RESET may be pulled high after supplies have been powered up A complete RESET is recommended after power up This can be performed by the system microcontroller gt Filter AVDD1 P Filter AVDD2 gt Filter DVDDIO R C Delay Y Enable 18V AD V8005 Regulator gt Filter AVDD3 P Filter bm CVDD1 F ilter gt DVDD m Fiter gt
452. wo independent signal paths for SD and ED HD so different video processing filtering color conversion and so on can be individually and simultaneously applied to each of the streams The input to the SD encoder block is always 16 20 24 bit 4 2 2 YCbCr stream and a 24 30 36 bit 4 4 4 YCbCr stream for ED HD modes Although the encoder cannot take an RGB input stream in it features a CSC matrix which enables the generation of RGB video signals at the component output The oversampling at 216 MHz SD and ED and 297 MHz HD ensures that external output filtering is not required The block diagram for the ADV8005 encoder core is shown in Figure 110 ENCODER PROCESSOR i H i 1 14 4 1 LUMINANCE 14 BIT 24 BIT DAC2 4 22 Veber FILTER DAC2 E 1 lt SD VIDEO E 5 lt sme parrean J PROGRAMMABLE gt 2463 1 BURST CHT ORENG 5 a a o H 2 H 5 14 BIT 0 Tee lt 2 lt H 1 5 2 36 BIT Q PROGRAMMABLE 4 4 4 Yeber HDTV FILTERS amp VIDEO PATTERN SHARPNESS AND DAC6 ej GENERATOR ADAPTIVE FILTER f CONTROL 1 1 i VIDEO TIMING GENERATOR Tex AX OVERSAMPEING DAC PL i i e ee 02 22 21022101 Figure 110 ADV8005 Encoder Block Diagram Note The video
453. x E3C2 R isrc2 pb 0 27 PB26 Ox E3C3 R isrc2 pb 0 28 PB27 As defined by the HDMI 1 4 specifications The ISRC2 packet registers are considered valid if and only if rx isrc2 pckt edge raw is set to 1 rx isrc2 pckt edge raw IO Map Address 0x1AFB 5 Read Only This readback indicates the raw status of the ISRC2 packet received signal Once set this bit remains high until cleared via the corresponding dear bit Function rx isrc2 pckt edge raw Description 0 default No new ISRC2 packet received 1 ISRC2 packet with new content received 5 10 2 Gamut Metadata Packets Refer to the HDMI 1 3 1 4 specifications for a detailed explanation of the Gamut Metadata packet fields Table 41 Gamut Metadata Packet Registers HDMI R W Register Name Packet Byte No Map Address OxE3F8 R W gamut packet id 7 0 Packet Type Value R mda pb o9 Pes mdata pb 0 11 10 OxE3CF mdata pb 0 12 11 OxE3DO R mdata pb 0 13 PB12 OxE3D1 gamut mdata pb 0 14 PB13 OxE3D2 mdata pb 0 15 14 OxE3D3 gamut mdata pb 0 16 PB15 OxE3D4 gamut mdata pb 0 17 PB16 OxE3D5 gamut mdata pb 0 18 PB17 OxE3D6 gamut mdata pb 0 19 PB18 OxE3D7 gamut mdata pb 0 20 19 OxE3D8 gamut mdata pb 0 21 PB20 OxE3D9 gamut mdata pb 0 22 PB21 OxE3DA gamut mdata pb 0 23 PB22 OxE3DB R gamut mdata pb 0 24 PB23 Rev 0 Page 200 of 326
454. x09 x00 1 1 vga 0x50 x00 10 04 x00 0x18 x00 0 0 0x00 0 3 0x00 0x02 0x80 0x00 0x80 0x08 0x40 0 4801 0 5 10 00 0x04 0 00 OxOF x80 xOF 0x00 Ox3C 10 00 0x02 20x40 0 01 0x80 0x07 0x80 0 0 480p Ox5A 0x00 0x04 0x00 OxOF x80 0 0x00 Ox3C 10 00 0x02 0x40 0 01 0x80 0x07 0x80 0 0 720p60 OxAO 0x00 OxlIB x80 x00 0x37 0x00 0 5 0x00 0 01 10 40 0 01 0x40 0x05 x00 1 1 1080i60 OxFO x00 10 16 0x00 OxOB x00 0x25 0x00 0x87 0x00 0x01 10 00 0x01 0x40 0x09 x00 1 1 1080p60 OxFO 0x00 10 16 0x00 0 x00 0x25 0x00 0x87 10 00 0 01 10 00 10 01 0x40 0x09 x00 1 1 1080 24 OxFO 0x00 Ox9F 0x80 0 x00 0x25 0x00 0x87 0x00 0 01 10 00 0x01 0x40 0x09 x00 1 1 The size of the output images of the VOM scaler can be smaller than that defined by the parameters of the output port The starting position for the SVSP output video can be set using svsp dp video h 10 0 and svsp dp video start 10 0 Figure 68 shows the relationship of the VOM scaler image and output video In this case the blank area around the output image is filled with color defined by the dp margin color 23 0 register the YUV color space This feature can be enabled using svsp dp output blank SVSP DP VIDEO H START Output video from Primary VSP SVSP DP VIDEO V START Output video from VOM Output SVSP DI CROP HEIGHT SVSP DP ACTIVELINE
455. x1080p 50Hz 0x20 1920x1080p 24Hz 0x21 1920x1080p 25Hz 0x22 1920x1080p 30Hz 0x24 2880x480p 60Hz 0x26 2880x576p 50Hz 0x80 640x350 85hz 0x81 640x400 85hz 0x82 720x400 85hz 0x83 640x480 60hz 0x84 640x480 72hz 0x85 640x480 75hz 0x86 640x480 85hz 0x87 800x600 56hz 0x88 800x600 60hz 0x89 800x600 72hz Ox8A 800x600 75hz Ox8B 800x600 85hz 0 8 1024x768 60hz Ox8E 1024x768 70hz Ox8F 1024x768 75hz 0x90 1024x768 85hz OxFC 720x288p 50Hz OxFD 720x240p 60Hz OxFE default 720x480i 60Hz OxFF 720 576 amp 50 2 Rev 0 Page 63 of 326 06 707 exosd in id 7 0 IO Map Address 0x1B6C 7 0 This register is used to specify the video id relative to CEA 861 Function exosd in id 7 0 Description 0x01 CEA 861 VIC 1 480p 60 640 0x02 CEA 861 VIC 2 480p 60 0x03 CEA 861 VIC 3 480p 60 0x04 CEA 861 VIC 4 720p 60 0x05 CEA 861 VIC 5 10801 60 0x06 CEA 861 VIC 6 480i 60 0x07 CEA 861 VIC 7 4801 60 0x08 CEA 861 VIC 8 240p 60 0x09 CEA 861 VIC 9 240p 60 0x10 CEA 861 VIC 16 1080p 60 0 11 CEA 861 VIC 17 576 _50 0x12 CEA 861 VIC 18 576p 50 0x13 CEA 861 VIC 19 720p 50 0x14 CEA 861 VIC 20 1080i_50 0x15 CEA 861 VIC 21 576 50 0x16 CEA 861 VIC 22 576i 50 0x17 CEA 861 VIC 23 288p_50 0x18 CEA 861 VIC 24 288p_50 Ox1F CEA 861 VIC 31 1080p_50 OxFC CEA 861 VIC 252 288p_50 OxFD CEA 861 VIC 253 240p 60 OxFE default CEA 861 VIC 254 480i 60 OxFF CEA 861 VIC 255 5761 50 rx in id 7 0
456. x1BE0 7 6 This control signal is used to select which input is routed to the auto position and auto phase blocks Function auto phpo inp sel 1 0 Description 00 default VID TTL 01 OSD TTL 10 RX 11 N A auto phpo IO Map Address Ox1BEO0 5 This bit is used to bypass the CSC or not before routing to the auto Phase and auto Position detection blocks Function auto phpo byp csc Description 0 CSC output used for auto PHPO 1 default CSC input used for auto PHPO auto ph en IO Map Address Ox1BE1 7 This bit is used to enable auto phase detection block Rev 0 Page 101 of 326 06 707 Function auto ph en Description 0 default Disabled 1 Enabled auto ph num 6 0 IO Map Address 0x1BE1 6 0 This control signal sets the total number of phases available on the front end part e g 8 16 32 etc auto ph scan 5 0 IO Map Address Ox1BE2 5 0 This control signal sets the scan phase number being tested When the scan value changes a new scan is triggered to start rb auto ph read ready IO Map Address 0x1BE3 7 Read Only This bit is used to indicate rb auto ph diff sum lock is valid a HIGH means it is valid to read the value in auto ph diff sum lock rb auto ph right phase 5 0 IO Map Address 0x1BE3 5 0 Read Only This signal is used to indicate the correct phase after i2c auto ph scan has been indexed through all of the phases rb auto ph diff sum lock 23 0 IO Map A
457. xF2EB R W spare2 pb8 7 0 0600000000 Data Byte 8 OxF2EC R W spare2 pb9 7 0 0600000000 Data Byte 9 OxF2ED R W spare2 pb10 7 0 0600000000 Data Byte 10 Rev 0 Page 208 of 326 Packet Map Access Type Register Name Default Value Byte Name Address OxF2EE R W spare2 pb11 7 0 0600000000 Data Byte 11 OxF2FF R W spare2 pb12 7 0 0600000000 Data Byte 12 2 R W spare2_pb13 7 0 0b00000000 Data Byte 13 OxF2F1 R W spare2 pb14 7 0 0600000000 Data Byte 14 OxF2F2 R W spare2 pb15 7 0 0600000000 Data Byte 15 OxF2F3 R W spare2 pb16 7 0 0600000000 Data Byte 16 OxF2F4 R W spare2 pb17 7 0 0600000000 Data Byte 17 OxF2F5 R W spare2_pb18 7 0 0b00000000 Data Byte 18 OxF2F6 R W spare2 pb19 7 0 0600000000 Data Byte 19 OxF2F7 R W spare2 pb20 7 0 0600000000 Data Byte 20 OxF2F8 R W spare2 pb21 7 0 0600000000 Data Byte 21 OxF2F9 R W spare2 pb22 7 0 0600000000 Data Byte 22 OxF2FA R W spare2 pb23 7 0 0600000000 Data Byte 23 OxF2FB R W spare2 pb24 7 0 0600000000 Data Byte 24 OxF2FC R W spare2 pb25 7 0 0600000000 Data Byte 25 OxF2FD R W spare2 pb26 7 0 0600000000 Data Byte 26 OxF2FE R W spare2 pb27 7 0 0600000000 Data Byte 27 Table 48 Spare Packet 3 Configuration Register Test Map Address Access Type Register Name Default Value Byte Name OxF3CO R W spare3 headerO 7 0 0600000000 Header Byte
458. xel data block and 0 defines an 8 pixel x 8 pixel data block where one pixel refers to two clock cycles at 27 MHz dnr mpeg 1 Encoder Map Address OxE4A4 7 This bit is used to select the Digital Noise Reduction DNR block size Function dnr mpeg 1 Description 1 16 pixels 0 default 8 pixels 7 4 19 6 DNR Input Select Control dnr fmode control 2 0 is used to select the filter which is applied to the incoming Y data The signal that lies in the pass band of the selected filter is the signal that is DNR processed Figure 130 shows the filter responses selectable with this control Rev 0 Page 281 of 326 06 707 1 0 FILTER D 0 8 7 FILTER C 8 06 2 5 0 4 FILTER 0 2 FILTER 0 0 1 2 3 4 5 6 FREQUENCY MHz Figure 130 SD DNR Input Filter Select 06398 081 dnr fmode control 2 0 Encoder Map Address 0xE4A5 2 0 This signal is used to configure the Digital Noise Reduction DNR input filter Function dnr fmode control 2 0 Description 001 Filter A 010 Filter B 011 Filter C 100 Filter D 7 4 19 7 DNR Mode Control DNR works on the principle of defining low amplitude high frequency signals as probable noise and subtracting this noise from the original signal In DNR mode it is possible to subtract a fraction of the signal that lies below the set threshold assumed to be noise from the original signal The threshold is set using 4 t
459. xel de repetition front end formatter clock configuration main and secondary TTL channels and Serial Video Rx channel e Timing generation for inputs with AV codes main and secondary TTL channels only e configuration main TTL channel only e ancillary data main TTL channel only In any of these modes the video id 7 0 exosd in id 7 0 and rx id 7 0 controls must be configured Rev 0 Page 61 of 326 06 707 Secondary p 080 1 35 Y TTL NE OSD IN 0 03 VS Set exosd id Main TTL Inputs Set by vid in id 2 Y Rx2 Cb Serial 1 Cr Rx1 Video Rx0 RX Rx0 HS RxC dk RxC d Set by rx in id Figure 36 Configuring Input Port Clock Rev 0 Page 62 of 326 video id 7 0 IO Map Address 0x1A00 7 0 This register is used to set the output clock frequencies from the input video formatting block used by both the Serial Video RX and Video U6 707 TTL input ports Function video in id 7 0 Description 0x01 640x480p 60Hz 0x03 720x480p 60Hz 0x04 1280x720p 60Hz 0x05 1920x1080i 60Hz 0x07 720 1440 x480i 60Hz 0x09 720 1440 x240p 60Hz OxOB 2880 x480i 60Hz 0 2880 x240p 60Hz OxOF 1440x480p 60Hz 0x10 1920x1080p 60Hz 0x12 720x576p 50Hz 0x13 1280x720p 50Hz 0x14 1920x1080i 50Hz 0x16 720 1440 x576i 50Hz 0x18 720 1440 x288p 50Hz Ox1A 2880 x576i 50Hz Ox1C 2880 x288p 50Hz 0 1 1440x576p 50Hz Ox1F 1920
460. xternal OSD VS timing signal Function exosd vs pol Description 0 default Input VS polarity doesn t change 1 Input VS polarity gets inverted exosd de pol IO Map Address 0x1B69 2 This bit is used to set the polarity of the input External OSD DE timing signal Rev 0 Page 58 of 326 06 707 Function exosd de pol Description 0 default Input DE polarity doesn t change 1 Input DE polarity gets inverted exosd hs vs mode is used to select the method by which the input video will be synchronized This may be required when the ADV8005 is used in conjunction with an MPEG decoder MPEG decoders use embedded timing codes rather than using external HS and VS signals Similarly other ADI decoders HDMI Rxs can output video using embedded timing codes This register should be programmed depending on the timing method of the upstream IC Refer to Section 2 2 11 for more information on AV codes exosd hs vs mode IO Map Address 0x1B6B 7 This bit is used to select the method of input timing Function exosd hs vs mode Description 0 Embedded timing codes 1 default VS DE mode exosd av pos sel IO Map Address Ox1B6B 3 This bit is used to select if the HS generated is consistent with EIA 861 timing or dependant on the embedded timing codes Function exosd av pos sel Description 0 default 1 Generate hs coincident with eav code Generate hs vs based on 861 timing exos
461. y Output Txt VSP Muxing 1080p OSD 1080 Video i SER cu N HDMI Exosd Input Us 720p OSD 54 bit Muxing Secondary p Data Input I Formatting 480p SC REED REMO 8 amp CSC TEE X HD ERAS Video 7 480p OSD 480p Video 5 Primary Hee TOM Input ata Decoder Formatting CSC amp ES lt i Encoder Serial Data i m Formatting i d amp CSC Figure 15 ADV8005 Mode 5 Configuration Mode 5 places the OSD blend block before both the PVSP block and the SVSP block Both the PVSP block and the SVSP work in parallel in this mode As the OSD is before both scalers the OSD will be available on all the outputs As mentioned in Section 2 1 4 the input to the SVSP must be progressive therefore this mode can only be used when the input is progressive As can be seen in the example in Figure 15 the output formats required are 1080p and 720p The 1080p format is converted through the PVSP block with the SVSP upscaling to 720p It should be noted from Figure 15 that when large video scalings are required these should be processed by the PVSP block for optimal performance Note De interlaced inputs can be input to the device in this mode however the SVSP can only accept progressive input formats Therefore the SVSP would be excluded from the processing in this case Rev 0 Page 31 of 326 06 707 2 1 7 Mo
462. y input channel the controls are as follows de v beg e pos 6 0 IO Map Address 0 188 17 1 This signal is used to specify the DE vertical beginning position for even fields if CEA 861 timing generation is enable and manual values selected Function de v beg e pos 6 0 Description OxXX assert de when Icount reaches OxXX on even fields de v beg o pos 6 0 IO Map Address Ox1B8C 0 Address 0x1B8D 7 2 This signal is used to specify the DE vertical beginning position for odd fields if CEA 861 timing generation is enable and manual values selected Function de v beg o pos 6 0 Description OxXX assert de when Icount reaches OxXX on even fields de h beg pos 9 0 IO Map Address 0x1B8D 1 0 Address 0x1B8E 7 0 This signal is used to specify the DE horizontal beginning position counting from the EAV if CEA 861 timing generation is enable and manual values selected Function de h beg pos 9 0 Description OxXX assert de when hcount reaches hs beg pos 9 0 IO Map Address 0x1B8F 7 0 Address 0x1B90 7 6 This signal is used to specify the HS beginning position counting from the EAV if CEA 861 timing generation is enable and manual values selected Function hs beg pos 9 0 Description OxXX assert hs when hcount reaches OxXX hs end pos 9 0 IO Map Address 0x1B90 5 0 Address 0x1B91 7 4 This signal is used to specify the HS ending position counting from the EAV if CEA 861 timing generat
463. y the mp2i block or not The control signal svsp frtrk mas mode en must also be enabled for this bit to take effect Function sp2i frtrk mas fld Description 0 default Disable tracking of input master field 1 Enable tracking of input master field s p2i invert vsp2d flag Secondary VSP Map Address OxE65E 7 This bit is used to invert the field information being sent to the secondary P2I block Rev 0 Page 168 of 326 06 707 The following I2C controls are used external sync mode 3 only pvsp mas resync en Primary VSP Map Address 0xE8A1 7 This bit enables direct timing generation reset via external sync for the PVSP This is for modes 2 and 3 only pvsp freq sel IO Map Address 0x1A44 7 This bit is used to manually configure the vertical frequency for the Primary VSP Function pvsp freq sel Description 0 default 59 94Hz or 23 9Hz 1 60Hz or 24Hz pvsp track offset 20 0 IO Map Address 0x1A94 4 0 Address 0x1A95 7 0 Address 0x1A96 7 0 This signal is used to program the delay on the output timing of vsyncs from the Primary VSP Function pvsp track offset 20 0 Description 0 default input and output vsyncs are coincident 1 1 clk between input and output vsync svsp track offset 20 0 IO Map Address 0x1A97 4 0 Address 0x1A98 7 0 Address 0x1A99 7 0 This signal is used to program the delay on the output timing of vsyncs from the Secondary VSP Functio

ADV8005 Hardware Reference Manual (Rev. 0)

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