Introduction to Simulation of VHDL Designs Using ModelSim
Contents
1. INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus I 14 1 File Edit View Add Tools Bookmarks Hanim Help s3 4 x Poeun inne if Msgs Edit majority3 x 1 No Data Edit majority3 x No Data Edit majority3 x3 No Data sim majority3 f o Data Now d Cuori Figure 25 Setting the simulation interval File Edit View Add Format Tools Bookmarks Window Help oe A if Msgs Edit majority3 x 1 No Data Edit majority3 x2 No Data Edit majority 3 3 No Data sim majority3 f No Data ne Now Ta Cursor 1 Ops to 800 ns Edit ile Ee Figure 26 Running the simulation 18 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 File Edit View Add Tools Bookmarks ae Help gal Wave Default Msgs Edit majority3 x 1 Edit majority3 x Edit majority3 x3 sim majority3 f Now 900 ns 155 385 ns Dj Figure 27 Result of the simulation 6 Making Changes and Resimulating Changes in the input waveforms can be made using the approaches explained above Then it is necessary to resim ulate the circuit using the altered waveforms For example change the waveform for x to have the logic value 1 in the interval from 0 to 200 ns as indicated in Figure 28 Now click on the Restart icon shown in the fi2. Loaded gt lt No Context gt Figure 6 ModelSim window after compilation 4 Creating Waveforms for Simulation To perform simulation of the designed circuit it is necessary to enter the simulation mode by selecting Simulate gt Start Simulation This leads to the window in Figure 7 6 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 14 1 D modelsim_intro majority vhd SMODEL_TECH altera vhdl 220model SMODEL_TECH altera verilog 220m MODEL_TECH altera vhdl altera SMODEL_TECH altera vhdl altera_l SMODEL_TECH altera verilog altera SMODEL_TECH altera vhdl altera_mf SMODEL_TECH altera verilog altera saan D tg tion Optimization Enable optimization Figure 7 Start Simulation window Expand the work directory and select the design called majority as shown in the figure Then click OK Now an Objects window appears in the main ModelSim window It shows the input and output signals of the designed circuit as depicted in Figure 8 majority majority logicfu x2 H standard standard E LU Signal fj textio textio a f J Signal W std_logic_1164 std logic_1164 FlName Typefitered State Order_ ParentPath Tine gt VHDL Process Active 1 majority Figure 8 Signals in the Objects window To simulate the circuit we must first specify the values of input sign
3. MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus I 14 1 To illustrate how a clock signal can be defined we will specify x3 in this manner Right click on the x3 input in the Objects window and select Modify gt Apply Wave In the Create Pattern Wizard window select Clock as the required pattern and specify 0 and 800 ns as the start and end times respectively as indicated in Figure 20 Click Next which leads to the window in Figure 21 Here specify 0 as the initial value 200 ns as the clock period and 50 as the duty cycle Click Finish Now the waveform for x3 is included in the Wave window Generate a waveform for ai Select Pattern any signal for the chosen Fatterns pattern f Clock Sim majority x3 The allowed patterns F aos f Constant Start Time End Time Time Unit Constant f Random lo leod ns kd Clock Repeater Random e E Repeater L Counter Signal Name lt Previous Next gt Cancel Figure 20 Selecting a signal of clock type gt Clock Attributes Initial Value me Clock Period Time Unit Specify the Clock Pattern Attributes zod ns kd Duty Cyde 50 lt Previous Finish Cancel Figure 21 Defining the characteristics of a clock signal Lastly it is necessary to include the output signal f Right click on f in the Objects window In the drop down menu that appears select Add to gt Wave gt Selected Signals as shown in Figure 22 The result is the image in Figur
4. EFORM EDITOR For Quartus U 14 1 File Edit View Add Format Tools Bookmarks Window Help gej Wave SSS SSS 8 SSS Saunas i x ya 2 fewer ae lad Hp T t i funn if eeu a a a ae TUM er Msgs Now 0 00 ns Cursor 1 201 538 ns 401 538 ns oa Be i 0 ps to 800 ns cS Figure 16 Editing the waveform Edit majority x2 Start Time End Time Time Unit eco o ss w eee Figure 17 Specifying the exact time interval Altera Corporation University Program 13 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus I 14 1 File Edit View Add Format Tools Bookmarks Window Help 4 o BBE 0 HE TTET E ETE T T toexr ete s 4 4 98 2 QQQQaliy wm 2 Msgs A Edit majority3 x1 sto Edit majority3 x2 Sti Now 0 00 ns are 201 538 ns E DE BE Ops to 800 ns Edit majority3 x1 Figure 18 The modified waveform 4 Edit majority3 x1 No Data 4 Edit majority3 x2 No Data Ee Now 0 00 ns ae 840 ns WOAH B vii 0 ps to 800 ns a Figure 19 Completed waveforms for x and x2 We will use a third approach to draw the waveform for x3 This signal should alternate between 0 and 1 logic values at each 100 ns interval Such a regular pattern is indicative of a clock signal that is used in many logic circuits 14 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING
5. Introduction to Simulation of Fi VHDL Designs Using ModelSim Graphical Waveform Editor For Quartus II 14 1 1 Introduction This tutorial provides an introduction to simulation of logic circuits using the Graphical Waveform Editor in the ModelSim Simulator It shows how the simulator can be used to perform functional simulation of a circuit specified in VHDL hardware description language It is intended for a student in an introductory course on logic circuits who has just started learning this material and needs to acquire quickly a rudimentary understanding of simulation Contents e Design Project e Creating Waveforms for Simulation e Simulation e Making Changes and Resimulating e Concluding Remarks Altera Corporation University Program 1 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 2 Background ModelSim is a powerful simulator that can be used to simulate the behavior and performance of logic circuits This tutorial gives a rudimentary introduction to functional simulation of circuits using the graphical waveform editing capability of ModelSim It discusses only a small subset of ModelSim features The simulator allows the user to apply inputs to the designed circuit usually referred to as test vectors and to observe the outputs generated in response The user can use the Waveform Editor to represent the input signals as waveforms In this t
6. LSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 At this point the main Modelsim window will include the file as indicated in Figure 5 Observe that there is a question mark in the Status column Now select Compile gt Compile All which leads to the window in Figure 6 indicating in the Transcript window at the bottom that the circuit in the majority vhd file was successfully compiled Note that this is also indicated by a check mark in the Status column The circuit is now ready for simulation pA ModelSim ALTERA 10 le Custom Altera Version File Edit View Simulate Add Project Tools Layout Bookmarks Window a T Layout ne ign kd L ColumnLayout at icolume kd a EEE majority vhd VHDL 0 08 14 14 06 28 26 PM Transcript MMMM l4 Reading 5 tools acdskit 14 0 1 204 windows 4 modelsim Lae tel vsin pref tcl l4 Loading project majority ModelSim gt Project majority lt No Design Loaded gt lt No Context gt Figure 5 Updated ModelSim window Altera Corporation University Program 3 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 14 1 mM ModelSim ALTERA 10 1e Custom Altera Version File Edit View Compile Simulate Add ssn Tools Layout Bookmarks Window en S _ majority vhd y VHDL O 08 14 1406 28 26 PM Loading project majority Compile of majority vhd was successful ModelSim gt Project majority lt No Design
7. USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus Il 14 1 ml Wave Sa Edit View Add Format Tools aoe Window Help Standard FSFE Bookmarks a sapped Compile Edit majority3 x2 w Mode 7 Simulate w Step Wave Wave Compare w Wave Cursor i Wave Edit w Wave Expand Tm Zoom Reset i Figure 15 Selecting the Wave Edit mode The waveform for x2 should change from 0 to 1 at 200 ns then back to 0 at 400 ns and again to 1 at 600 ns Select x2 for editing by clicking on it Then click just to the right of the 200 ns point hold the mouse button down and sweep to the right until you reach the 400 ns point The chosen interval will be highlighted in white as shown in Figure 16 Observe that the yellow cursor line appears and moves as you sweep along the time interval To change the value of the waveform in the selected interval click on the Invert icon as illustrated in the figure A pop up box in Figure 17 will appear showing the start and end times of the selected interval If the displayed times are not exactly 200 and 400 ns then correct them accordingly and click OK The modified waveform is displayed in Figure 18 Use the same approach to change the value of x2 to in the interval from 600 to 800 ns which should yield the result in Figure 19 12 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAV
8. als which can be done by drawing the input waveforms using the Graphical Waveform Editor Select View gt Wave which will open the Wave window depicted in Figure 9 The Wave window may appear as a part of the main ModelSim window in this case undock it by clicking on the Dock Undock icon in the top right corner of the window and resize it to a suitable size If the Altera Corporation University Program 7 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus I 14 1 Wave window does not appear after undocking then select View gt Wave in the main ModelSim window We will run the simulation for 800 ns so select View gt Zoom gt Zoom Range and in the pop up window that will appear specify the range from 0 to 800 ns This should produce the image in Figure 9 pe Wave File Edit View Add Format Tools Bookmarks Window Help We gt Bae Msgs Figure 9 The Wave window For our simple circuit we can do a complete simulation by applying all eight possible valuations of the input signals x X2 and x3 The output f should then display the logic values defined by the truth table for the majority function We will first draw the waveform for the x input In the Objects window right click on x1 Then choose Modify gt Apply Wave in the drop down box that appears as shown in Figure 10 This leads to the window in Figure 11 which makes it possible to specify the value of t
9. ation or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties repre sentations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 22 Altera Corporation University Program December 2014
10. e 23 Altera Corporation University Program 15 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 14 1 View Memory Contents Add Wave Add Wave New Add Wave To Add Dataflow Figure 22 Adding a signal to the Wave window 16 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus I 14 1 File Edit View Add Format Tools Bookmarks Window Help Msgs Edit majority3 1 No Data Edit majority3 x No Data Edit majority3 x3 No Data a sim majority3 f o Data Now 0 00 ns Py ees 840 ns Tt LULU il i eas a Figure 23 The completed Wave window Save the created waveforms as majority do file as indicated in Figure 24 MA Save Format D modelsim intro ma ority do Save contents W Waveform formats W Waveform edits Cancel Figure 24 Saving the waveform file 5 Simulation To perform the simulation open the Wave window and specify that the simulation should run for 800 ns as indicated in Figure 25 Then click on the Run All icon as shown in Figure 26 The result of the simulation will be displayed as presented in Figure 27 Observe that the output f is equal to 1 whenever two or three inputs have the value 1 which verifies the correctness of our design Altera Corporation University Program 17 December 2014
11. gn files that specify the circuit to be simulated We will first create a directory folder to hold the project used in the tutorial Create a new directory and call it modelsim_intro Copy the file majority vhd into this directory Open the ModelSim simulator In the displayed window select File gt New gt Project as shown in Figure 1 pA ModelSim ALTERA 10 1e Custom Altera Version Edit View Compile Simulate Add Library Tools Layout Bookmarks Window Help Folder a4 E Pa m Source Library lS Debug Archive tutorial SMODEL_TECH altera vhdl 220model Change Directory SMODEL_TECH altera verilog 220model Use Source SMODEL_TECH altera vhdl altera Source Directory SMODEL_TECH faltera vhdl altera_Insim a SMODEL_TECH altera verilog altera_Insim Datasets SMODEL_TECH altera vhdl altera_mf SMODEL_TECH altera verilog altera_mf SMODEL_TECH altera verilog altera Page Setup SMODEL_TECH altera vhdl altgxb Print SMODEL_TECH altera vhdl altgxb Print Postscript SMODEL_TECH altera verilog altgxb ii e SMODEL_TECH altera vhdl arriagx seems Daer ienn S MODEL_TECH altera vhdl arriagx_hssi Recent Projects SMODEL_TECH altera verilog arriagx_hssi Close Window Quit Reading 5 tools acdskit 14 0 1 204 windows64 modelsim ae tcl vsim pref tcl Environment Project serial lt No Design Loaded gt altera_Insim z Figure 1 The ModelSim window A Create Project pop up box
12. gure A pop up box in Figure 29 will appear Leave the default entries and click OK Upon returning to the Wave window simulate the design again by clicking on the Run All icon The result is given in Figure 30 Altera Corporation University Program 19 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 H x sase e iarites ST E s Mags Edit majority3 x 1 Edit majority3 x2 Edit majority3 x3 sim majority3 f pe Now Ta Cursor Keep W List Format lf Wave Format lf Breakpoints lv Logged Signals v Virtual Definitions if Assertions if Cover Directives lw ATV Format Figure 29 The Restart box 20 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 File Edit View Add Format Tools Bookmarks Window Help Msgs Edit majority3 x 1 Edit majority3 x Edit majority3 x3 a sim majority3 f Figure 30 Result of the new simulation Simulation is a continuous process It can be stopped by selecting Simulate gt End Simulation in the main Model Sim window 7 Concluding Remarks The purpose of this tutorial is to provide a quick introduction to ModelSim explaining only the rudimentary aspects of functional simulation that can be performed using the ModelSim Graphical User Interface More details ab
13. he selected signal in a time period that has to be defined Choose Constant as the desired pattern zero as the start time and 400 ns as the end time Click Next In the window in Figure 12 enter 0 as the desired logic value Click Finish Now the specified signal appears in the Wave window as indicated in Figure 13 8 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR View Memory Contents Add Wave Add Wave New Add Wave To Add Dataflow Add to Generate a wavetorm for i Signal Name any signal for the chosen i pattern E im majority x1 The allowed patterns Start Time End Time Time Unit b ho fs Figure 11 Specifying the type and duration of a signal Altera Corporation University Program December 2014 For Quartus II 14 1 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus Il 14 1 opecify the Constant Pattern Attributes Constant Attributes Value id lt Previous Finish Cancel Figure 12 Specifying the value of a signal File Edit View Add Format Tools Bookmarks Window Edit majority3 x1 sto Figure 13 The updated Wave window To draw the rest of the x signal right click on its name in the Wave window In the drop down window that appears select Edit gt Create Modify Waveform This leads again to the window in Figure 11 N
14. out the ModelSim GUI and its use in simulation can be found in the Generating Stimulus with Waveform Editor chapter of ModelSim SE User s Manual which is available as part of an installed ModelSim SE simulator A more extensive discussion of simulation using the ModelSim simulator is provided in the tutorial Using ModelSim to Simulate Logic Circuits for Altera Devices which is available on Altera s University Program Web site Altera Corporation University Program 21 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 Copyright 1991 2014 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the applic
15. ow specify 400 ns as the start time and 800 ns as the end time Click Next In the window in Figure 12 specify 1 as the required logic value Click Finish This completes the waveform for x as displayed in Figure 14 10 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 File Edit View Add Format Tools Bookmarks Window Help Edit majority3 x 1 sto i Cursor 1 0 00 ns aa e E Ops to 800 ns a Figure 14 The completed waveform for x input ModelSim provides different possibilities for creating and editing waveforms To illustrate another approach we will specify the waveform for x2 by first creating it to have a O value throughout the simulation period and then editing it to produce the required waveform Repeat the above procedure by right clicking on x2 in the Objects window to create a waveform for x that has the value O in the interval O to 800 ns So far we used the Wave window in the Select Mode which is indicated by the highlighted icon Now click on the Edit Mode icon ft and then right click to reach the drop down menu shown in Figure 15 and select Wave Edit if it has not been checked Note that this causes the toolbar menu to include new icons for use in the editing process Altera Corporation University Program 1 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS
16. utorial the reader will learn about e Test vectors needed to test the designed circuit e Using the ModelSim Graphical Waveform Editor to draw test vectors e Functional simulation which is used to verify the functional correctness of a synthesized circuit This tutorial is aimed at the reader who wishes to simulate circuits defined by using the VHDL hardware description language An equivalent tutorial 1s available for the user who prefers the Verilog language PREREQUISITE The reader is expected to have access to a computer that has ModelSim SE software installed 3 Design Project To illustrate the simulation process we will use a very simple logic circuit that implements the majority function of three inputs x1 x2 and x3 The circuit is defined by the expression ff X1 X2 X3 X1 X2 X1 XZ X2X3 In VHDL this circuit can be specified as follows LIBRARY ieee USE ieee std_logic_1164 all ENTITY majority IS PORT x1 x2 x3 INSTD_LOGIC f OUT STD_LOGIC END majority ARCHITECTURE LogicFunction OF majority IS BEGIN f lt xl AND x2 OR x1 AND x3 OR x2 AND x3 END LogicFunction 2 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus U 14 1 Enter this code into a file called majority vhd ModelSim performs simulation in the context of projects one project at a time A project includes the desi
17. will appear as illustrated in Figure 2 Specify the name of the project we chose the name majority Use the Browse button in the Project Location box to specify the location of the directory that you created for the project ModelSim uses a working library to contain the information on the design in progress in the Default Library Name field we used the name work Click OK Altera Corporation University Program 3 December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODELSIM GRAPHICAL WAVEFORM EDITOR For Quartus II 14 1 maj ority roject Location D fmodelsim intro Browse fault Library Name work Copy Settings From ds modelsim ae modelsim ini Browse Copy Library Mappings Reference Library Mappings Figure 2 Created Project window In the pop up window in Figure 3 click on Add Existing File and add the file majority vhd to the project as shown in Figure 4 Click OK then close the windows M4 Add items to the Project Click on the icon to add items of that type u Create New File Add Existing File M a Create Simulation Create New Folder Figure 3 Add Items window D modelsim intro majority vhd Browse Add file as type default kd f Reference from current location Copy to project directory OK Cancel i Figure 4 Add Items window 4 Altera Corporation University Program December 2014 INTRODUCTION TO SIMULATION OF VHDL DESIGNS USING MODE
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