NCL30051LEDGEVB - ON Semiconductor
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1. Se 42 mn CH 46 50 OUTPUT FORWARD VOLTAGE Vdc Figure 10 Efficiency versus line and load Power Factor and Input Harmonic Content The power factor will remain above 0 90 for the rated load output 1 A and to minimum Vslevels for 120 Vac input and down to Ve 35 Vdc for 230 Vac As the actual current load is decreased from the rated maximum the power factor will also degrade with lower Vz These effects are shown in Figure 10 In addition to power factor a more critical parameter in some regions is harmonic content Lighting Power supplies fall under the IEC61000 3 2 Class C standard and there are vary strict limits on harmonic content for power supplies gt 25 W http onsemi com 16 POWER FACTOR PF 1 00 0 95 0 90 0 85 0 80 0 75 0 70 0 65 POWER FACTOR PF 0 90 0 85 0 80 0 75 0 70 NCL30051LEDGEVB 25 30 35 40 45 OUTPUT FORWARD VOLTAGE Vdc Figure 11 Power Factor versus Forward Voltage lout 1 A 15 140 165 190 215 240 265 INPUT LINE VOLTAGE Vac Figure 12 Power Factor versus Output Current 90 1 http onsemi com 17 NCL30051LEDGEVB 25 20 Harmonic Current Percentage of Fundametal a Limit 96 10 4 Measured 96 5 Harmonic Figure 13 Harmonic Levels 230 Vac input Full Load Dimming E2. Volt 1 Co Probe 10 Voltage Invert AC Line 0 004 60 0055Hz CH1 200mvBy M 5 00ms 17 May 10 16 50 Figure 18 Input Line Current under Different Operating Conditions http onsemi com 21 NCL30051LEDGEVB CONCLUSIONS current needs and illustrates different methods to implement The application note describes the operation of the dimming NCL30051LED Evaluation board and describes the primary design stages including transformer design as well as References operational behaviors This architecture can achieve very 1 NCL30051 Data Sheet high efficiency for LED lighting applications while meeting 2 NCS1002 CVCC controller data sheet power factor and harmonic content requirements The 3 ON Semiconductor Application Note AND8470 D evaluation board is flexible to support a range of LED drive 4 ON Semiconductor Application Note AND8427 D 5 ON Semiconductor Design Note DN06068 D Golden DRAGON LED is a registered trademark of OSRAM Opto Semiconductor Inc XLamp is a trademark of Cree Inc ON Semiconductor and are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically discla
3. bulk voltage across the transformer primary due to the capacitive divider network formed by resonant capacitors C6 and C7 By choosing the maximum bulk voltage at about 500 Vdc and assuming a maximum output voltage of 50 V the turns ratio on the transformer will be Vbulk 2 divided by 50 Vout 250 50 5 So a turns ratio of 5 1 is required between the primary and one of the half s of the secondary note push pull output rectification All that is required now is to determine the minimum number of primary turns necessary to avoid core saturation and then ratio the secondary turns from this point The selected core is a PQ 2020 with a cross sectional core area Ae of 0 6 cm Using the transformer design relationship Np VxDx108 _ 20V x 1 x 108 4xFxBMxAe 4 x 35kHz3200G x 0 6 cm 96 7 turns Where Np is the minimum primary turns needed V is the max voltage across the primary with a little margin F is the switching frequency Bm is the maximum flux density in the ferrite core Ae is the cross sectional area of the core The average primary current will be a little more than 60 W 250 Vdc x 0 95 228 mA assuming close to 95 converter efficiency The rms value will actually be a little higher but AWG 28 magnet wire will easily handle this and 96 turns can comfortably be wound over 3 layers with 32 turns per layer The number of secondary turns will be 96 5 19 2 turns so 19 turns will be close enough It turns
4. Leakage Inductance 90 100 uH nominal resonant half bridge leakage inductance is Lr Bobbin Type PQ20 20 14 pin PC mount bobbin Windings in order Winding type Turns Material Gauge Insulation Data Primary winding 2 5 96 turns of 28 HN magnet wire over 3 layers 32 turns per layer approx Self leads to pins Insulate with Mylar tape sufficient for 3 kV Hipot to next winding Secondary winding 7 11 10 14 19 turns of 2 X 26 magnet wire bifilar wound over two layers Self leads to pins per schematic below Final insulate with Mylar tape Note The critical parameter is to achieve a leakage inductance of 90 100 uH with a min primary inductance of 6 mH The overall turns can be increased or decreased to achieve this as long as the turns ratio remains 5 1 Vacuum varnish assembly Hipot 3000 volts from Primary to Secondary 1 minute Schematic Lead Breakout Pinout Bottom View e 14 06 gt e 1 2 7 e lei e pu M ttle Jelg Primary Secondary z 14 10e A lel4 el J 5 10 eN Ass 7 e le e 6 Figure 4 Resonant Half Bridge Transformer Design T1 hitp onsemi com 8 NCL30051LEDGEVB PFC Choke Design L2 Using the PFC design approach illustrated in ON Semiconductor Application Note AND8123 we can analyze the PFC choke design Inductor rms current at 50 W output and 85 Vac input 0 72A Inductor peak current at 50 W
5. SE ox External Dim TP3 100K Pot Adj TP4 R11 gt R10 VAY 11K 10K Vcc LM324DG Figure 7 DIM Card Schematic http onsemi com 12 NCL30051LEDGEVB Topology Limitations Despite the high efficiency and relatively low complexity of the resonant half bridge and magnetics design in this topology it does have some limitations with respect to the ac line and output load forward voltage extremes These limitations are primarily due to the fact that since the feedback loop controls the output voltage of the power factor corrector the bulk voltage is directly proportional to Vout or the Vg of the diode string when operating in the normal constant current mode Since the output Vbulk of a boost converter must always be higher then the peak ac input voltage for the boost converter to function the relationship that Vbuk gt Vac peak must always be maintained for continuous circuit operation and constant output In the design example for this demo board the PFC output bulk voltage is 10 times the output voltage or Vy due to the transformer turns ratio 5 1 and the fact that the resonant half bridge switches 1 2 of the bulk across the transformer primary We can deduce some of the limitations from this fact The best way is to see the impact the nominal ac line voltage has on the output Vr The NCL30051 has a 600 V max rating on the high side gate driver section pins 15 and 16 As a consequence assuming an 85 derating the
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7. out and 85 Vac input 1 75 A Maximum inductance for reasonable switching frequency 1200 uH max Turns ratio to aux winding to produce a 15 to 18 Vdc Vcc 9 1 or 10 1 To maintain component consistency a PQ 2020 ferrite core was also selected for the PFC choke Based on an rms choke current of 0 72 A and an average switching frequency of around 100 kHz three strands of AWG 30 magnet wire was chosen for the main winding to minimize ac losses Calculations based on the approximate wire diameter 2 x 0 012 or 0 61 mm and a core bobbin inside winding width of about 0 47 12 mm it appears that 75 turns of this wire can comfortably be wound on 4 or 5 layers with about 18 turns per layer Using the above parameters from the design spreadsheet and the following inductor relationships we can determine the optimum design using this PQ 2020 core N X Bmax X Ae 0 47 x N x Ipk and Lg Ipk x 108 Bmax Where N is the number of turns Bmax is the max flux density Ipk is the peak inductor current Ae is the core cross sectional area cm Lg is the total core gap cm Substituting the known values into first equation for N 75 turns Bmax 3000 gauss Ae 0 6 and Ipk 1 75 A we get L 770 uH which is less than the max of 1200 uH This will result in a switching frequency of 70 kHz min and 200 kHz max for typical operation so this is probably a reasonable inductance to start with We could increase the inductance and lower
8. out that due to the center tapped secondary two strands of 26 magnet wire wound bifilar on top of the primary will make the secondary easily handle up to 1 5 A output current The primary leakage inductance is the only unknown factor that was not actually purposely designed in however with the three layer primary and adequate insulating tape between the primary and secondary there should be adequate leakage inductance that will facilitate a resonant capacitor with a common value that will obtain a reasonable resonant frequency that can be accommodated by the internal half bridge clock in the NCL30051 controller By shorting the transformer secondary pins out with very short wires the primary leakage can be measured with an inductance meter In this design the leakage inductance worked out to be between 90 and 100 uH sufficient to produce a resonant frequency of 36 kHz with a pair of 0 1 uF capacitors in parallel effectively for C6 and C7 It turned out that a clock timing capacitor of 1 nF for C10 sets the switching frequency to about 36 kHz which provided the optimum tuning as displayed in primary current waveform of Figure 2 The design summary of the transformer T1 is shown in Figure 4 Since the output current and or voltage is regulated by controlling the PFC bulk voltage the value of the bulk voltage will be directly proportional to Vout via the turns ratio of the transformer For example if we have an LED string with a nominal fo
9. the PFC switching frequency by adding more turns but this would probably require a larger core In order to prevent saturation the core must be gapped per the second equation Substituting in the known parameters we get Lg 0 055 cm or 0 022 inches Since this is the total gap we would use half of this length if we were gapping all three pole legs of the core This gap should also give us the required inductance of about 700 uH The final choke design is shown in Figure 5 http onsemi com 9 NCL30051LEDGEVB Part Description PFC Choke 60 W 100 kHz CRM Rev 4 6 8 10 Schematic ID L2 Core Type PQ20 20 Ferroxcube 3C95 or equivalent material Core Gap Gap for 675 uH 25 uH across pins 1 to 3 Inductance 650 700 uH nominal Bobbin Type PQ20 20 14 pin PC mount bobbin Windings in order Winding type Turns Material Gauge Insulation Data Main winding 1 3 75 turns of 3 strands of 30 trifilar wound Wire can be twisted if desired Self leads to pins Insulate with 2 or 3 layers of Mylar tape to next winding Other option 2 strands 28 bifilar Vcc winding 4 6 8 turns of 30 magnet wire spiral wound over one layer Self leads to pins Final insulate with Mylar tape Vacuum varnish assembly Hipot 1000 volts from main winding to Vcc winding Schematic Lead Breakout Pinout Bottom View e 1 14fe felt e 7 N Main 75T RE A Ne of 3 x
10. 30 pue s Li DE 3 10 e X el A e e S j 4 el m e b Vcc 8T 7 e J e 6 of 30 e Figure 5 PFC Choke Design Details L2 http onsemi com 10 NCL30051LEDGEVB Dimming Capabilities not installed More details of the DIM card operation can be To demonstrate the LED dimming capabilities of this found in AND8470 A table for configuring the three circuit the same DIM control card used in the NCL30001 different operating modes is shown below and the schematic LED driver circuit described in AND8470 has been used for the DIM card circuit is shown in Figure 7 here Dimming can be accomplished using three methods pulse width modulation PWM of the output current Modifications Jumper analog current dimming where the current reference voltage Dimming Configuration Configurations for U4B is modified via a 1 to 10 V control signal to linearly External PWM dimming Omit DIM card short pins 2 and control the output current to the LEDs and bi level input 3 of P1 dimming in which a logic level signal will lower the LED Inject PWM signal into J3 intensity level by reducing the LED output current Without Internal PWM dimming Add DIM card with JMP1 added this DIM card a PWM input terminal J3 is still provided to P1 on DIM card Add JMP3 to for an external 160 to 300 Hz PWM input signal to control USE ve Adjust pat Bra the output current This is done by switching transistor Q6 on and off which in turn switches the sample and hol
11. 33 181 520Hz T Jun 10 11 32 173 443Hz Figure 6 PWM Dimming Mode Output Current Profile Depending on the selected PWM dimming frequency C1 modulation at some pulse widths It is best to select the of Figure 7 it is possible to get a slight beat between this PWM dimming frequency to be in between the line frequency and a harmonic of the line frequency Depending frequency harmonics Thus 160 or 220 Hz would be on the magnitude of the overall output ripple and the recommended optimum PWM frequencies for a line selection of C4 C5 there is the potential for LED current frequency of 60 Hz See section on Output Ripple below http onsemi com 11 NCL30051LEDGEVB Con1 to P1 PWM Out source Vcc In bii Vcc IE O UF 25V i R16 2N7002KT1G lt 10K gt MMBT2222A x pe WH R2 A 150K aad d 10K R3 20K Vref In a 9 2 5V c5 1nF Dim Select P2 Bi level JMP3 or PWM d VS ey Go Temp Analog JMP2 dd Compensation U2B R14 SCH R12 gt 30K Analog Dim Out 2 15 V 10 Boe C9 R13 C8 0 1 10K 10nF Cr 0 1 1 Common Dimming Option Control Card Schematic Rev 3 Notes 1 Pots R1 and R9 are Vishay Spectrol 43P type 20 turn cermet trimmers Mouser part 4 594 43P203 and 594 43P104 2 All caps are SMD ceramic 25V min 3 TH1 is PTC thermistor LS 5mm 4 All semiconductors are ON Semi parts D3 MMSD4148 TP1 Bi Level Switch 10V a TP2 Analog Dimming R9 400K
12. 5 http onsemi com 2 NCL30051LEDGEVB o A ech A Q d D1 D4 MUBA160 je EE MRA4007 NDDO4N60ZT D7 ce 400v Pod RIAL L1 x4 Q2A gt C1 e C2 vw T1 Se E x X Loz 0 22 c3 AN m RIBS X 0 22uF i gt 400V 11 fe AN Q2B 14 etl v 1 g SC M C7 m ER 0 1uF po 400V q MURA160 no 1 Q2A Q2B are D Pak devices 2 L1 is Coilcraft E3492 AL 2 9 mH 3 Heavy schematic lines are recommended ground plane areas blue is power ground black is signal logic ground green is drive ground 4 NCL30051 signal grounds and associated components should be single point connected to the power and drive ground planes as shown in schematic 5 L2 and T1 are PQ2020 cores with 14 pin bobbins 6 Q1 requires small heatsink 7 C10 C17 and Q7 R40 should be as close to associated U1 pins as possible rm MURA160 10K R42 R11 54K 680K 0 5W R15 2 7K U3 2 PS2561A R12 680K 0 5W 4 U2 fi Aro d El pum Din 3 2 LA PS2561A Pirmary H Ground C27 Plane A C A CVCC Feedback C Figure 1 Primary Side Schematic onsemi com http NCL30051LEDGEVB Power Factor Correction Section The boost power factor corrector circuit is composed of MOSFET Q1 boost diode D6 boost inductor L2 and the components associated with the PFC control section and pins of the NCL30051 control IC U1 D5 provides a bypass diode to prevent resonant L C charging of series
13. NCL30051LEDGEVB 35 50 Volt Up to 1 5 Amp Offline Power Factor Corrected LED Driver with Flexible Dimming Options Evaluation Board User s Manual Introduction This application note describes a 60 W off line power factor corrected line isolated LED driver using ON Semiconductor s new NCL30051 two stage controller This controller contains the control circuitry for both a critical conduction mode CRM boost power factor corrector PFC and a fixed frequency series resonant half bridge converter and is housed in a 16 pin SOIC package The high level of integration and low pin count is based on a novel control topology where the PFC output bulk voltage is adjusted via closed loop to change the amount of power transferred by the fixed duty cycle half bridge The resonant half bridge essentially functions as a dc to dc step down transformer This approach is simpler to implement and stabilize compared to the more complex LCC topology where the frequency of the resonant controler is varied to change the amount of power transferred to the load The fixed frequency and symmetrical duty cycle of the resonant half bridge clocking allows for very simple transformer design This topology is capable of powering series LED loads with efficiencies reaching 90 This is mainly due to the CRM power factor corrector and the very high efficiency of the resonant half bridge which results in zero current and voltage switching in the power MOSFE
14. Ts Such efficiencies would be quite difficult using a conventional flyback converter in the second stage Constant voltage constant current control CVCC is handled on the secondary side of the power circuit using ON Semiconductor s NCS1002 CVCC controller with integrated reference Although this particular design represents a 60 W nominal application the controller topology is ideal for power levels to 200 W and higher This specific design is available as evaluation board NCL30051LEDGEVB There are a wide variety of medium power lighting applications that would benefit from replacing the traditional light source with an LED source including street lights refrigerator cases parking garages wall washers wall packs and architectural lighting All of these applications have high operating hours challenging environmental conditions and can benefit from advanced dimming control to further save energy Moreover many of Semiconductor Components Industries LLC 2011 November 2011 Rev 1 ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL these applications have accessibility issues that would significantly reduce maintenance costs given the LEDs long operating lifetime This specific driver design is tailored to support LEDs such as the Cree XLAMP XP G and XM L and OSRAM Golden DRAGON Plus that have maximum drive currents of at least 1000 mA These LEDs exhibit good efficacies at higher drive currents allo
15. boost output capacitors C4 and C5 during initial startup when the line voltage is first applied Two 400 Vdc capacitors are used in series for the bulk capacitors to accommodate the 550 maximum bulk voltage 300 Vdc rated capacitors could have also been used in this application C3 is a polypropylene film capacitor used to stiffen the input source impedance to the boost converter and provide EMI filtering Operating bias Vcc for the control IC U1 is derived from the low voltage auxiliary winding on boost choke L2 This is essentially a charge pump circuit comprised of R7 C8 Z1 D10 and Vcc filter capacitors C15 and C16 The power factor correction circuit operates in critical or boundary conduction mode CRM and hence has a variable switching frequency depending on line and load conditions Since the L2 inductor current always drops to zero before O1 is turned back on again boost diode D6 will have essentially no reverse recovery losses when O1 is switched on each cycle In addition the turn on gate drive requirement for O1 is minimized since the MOSFET current always starts at zero however complementary driver Q3 Q8 is implemented in the gate drive line for efficient switching of O1 In some cases it is possible to vary the resistance of R11 R12 slightly to improve the power factor at high line This circuit provides feed forward signal information to the PFC on time setting capacitor C17 It should also be noted that res
16. bulk bus can be set at 510 Vdc max Under these conditions Vout max under no load conditions could be 50 Vdc with the 5 1 turns ratio on T1 Assuming this 50 Vdc output max as our nominal open circuit Vout let s see what the minimum output Vr can be that will still maintain boost converter operation for normal ac line voltages 120 Vac In this case the peak line voltage will be 1 4 x 120 Vac 168 Vpk Dividing this peak by 10 T1 turns ratio x half bridge factor of 2 yields 16 8 V which is less than 1 3 of the Vf max of 55 V This would theoretically allow a 3 1 Vt compliance ratio however due to the fact that the primary Vcc is derived from the PFC inductor aux winding experimentation has shown that 20 Vdc is actually the lowest safe minimum Ne for 120 Vac input for reliable Vcc maintenance for this design 230 Vac The peak line voltage will be 230 x 1 4 322 Vpk Again dividing this by 10 yields 32 2 V or 35 V for the minimum output Ne with a tolerance margin 277 Vac Vpk 277 x 1 4 388 Vdc so output Vr minimum becomes about 40 Vdc 305 Vac Vpk 305 x 1 4 427 Vdc so output Vr minimum becomes about 45 Vdc This limitation should considered up front when designing the LED driver and the consequential effects of the min and max of the diode string V as a result of binning forward current and thermal variations For applications with high nominal line levels the transformer turns ratio becomes more critical when optim
17. ctance Without any complex winding structure the leakage inductance of T1 came out to about 100 uH with the transformer design shown in Figure 4 The waveform of the sinusoidal primary current 45 W output is shown in Figure 2 The use of fixed frequency resonant switching in the half bridge creates a condition of zero current switching in the MOSFETS which results in very high conversion efficiency Diodes D7 and D8 provide voltage clamping to the bulk rail in the event of parasitically generated voltages or transients during start up and or dynamic operation M Pos 1 200 us CH1 Coupling TH Primary Current 45 Wout 0 2 My n CIO 560 pF CH1 200mvBy M 10 0 us 1 Jun 10 15 35 BY Limit On 20MHz Volts Div arse Probe 10 Voltage Invert Off CH1 Z 120mV 33 7721kHz Figure 2 Resonant Half Bridge Current Waveform http onsemi com NCL30051LEDGEVB Secondary Side Circuitry The secondary winding of the half bridge transformer the full wave center tap rectifier and the associated secondary side circuitry are shown in the schematic of Figure 3 The secondary rectifier D16 is a dual Schottky device and because of the symmetrical duty ratio only a modest amount of capacitive filtering is necessary to attenuate the high frequency output ripple In this design a paralleled pair of 4 7 uF 100 Vdc film capacitors were used The current and voltage sensing circuitry is based around the NCS1002 CVCC co
18. d Bi LevelDimming Add DIM card with JMP 1 P1 removed Add JMP3 to P2 on transistor gate drive and toggles optocoupler U2 which card Connect switch from TP1 switches U1 s Ct pin 2 via buffer transistor Q7 This pin and TP2 Closed switch gives when grounded will terminate drive to the half bridge low dim level MOSFETs Q2A Q2B thus rapidly stopping output current Analog Dimming Internal Add DIM card with JMP1 P1 flow Due to the low value of output capacitors C18 and C19 Adjust P DE eis P2 a rectangular wave signal in the frequency range of 160 to E 300 Hz will adequately PWM the output current with good a ida edema RA INEP rise and fall times see Figure 6 C1 on the DIM card sets Adjust Seer UE d JMP2 to Lr this frequency Higher dimming frequencies can but used Remove pot R9 and wire in imi external 100k potentiometer to but the dynamic range of the dimming can be limited due to TPs 2 3 and 4 TP3 is the pot waveform fall times It should be noted that jumper J2 across wiper Adjust external pot for pins 2 and 3 of connector P1 is necessary if the DIM card is LED brightness Tek J Trig d M Pos 40 00 us CH Tek Si Trig d M Pos 40 00 us CH1 Coupling Coupling PIN Dimming S056 Jout S00 mA ew PAM Dimming D 10 ot 100 mA CH 20MHz 20MHz Volts Div Volts Div Probe Probe 10 10 4 Voltage Voltage 1 un Invert Off CH1 S mVBy M 2 50ms CH1 440mV CH1 500mvBy M 2 50ms CH1 440mV T Jun 10 11
19. e extra current through the opto transistor without loading pin 8 of U1 Since the PFC also senses the bulk output voltage via resistor network R14 R18 and R19 this divider is set via R19 such that this inner voltage loop is closed when the bulk voltage reaches 550 Vdc so as to not prematurely interfere with the secondary voltage loop of U4A Note that if the secondary voltage feedback loop were to fail the inner PFC voltage feedback loop would clamp the bulk voltage to approximately 550 Vdc http onsemi com 5 NCL30051LEDGEVB D16 T1 Ed MBRF10H150 imi 100 Vx2 C18 19 20 R20 Vcc 14V 22K R23 A CVCC Feedback C D15 MMSD4148 To Primary Side Ground Plane C27 2 2nF R39 Ae PWM Dim 2 7K C Notes 1 D16 requires small heatsink 2 Heavy schematic lines are recommended ground plane areas C21 O 1uF 100V Current Sense Sample amp Hold MMBTAOG6LT1G Jumper if DIM Card not used OQ Vref In m Oo Analog i Dim out NCL30051 LED Driver CVCC Secondary Sensing LED Anode J2 LED Cathode O J3 O PWM In GndO 100 200Hz Dimming Control Options Card Figure 3 Secondary Side Schematic onsemi com http NCL30051LEDGEVB Resonant Half Bridge Transformer Design T1 Since the half bridge transformer operates in a fixed frequency symmetrical duty ratio the design becomes very straightforward A half bridge converter switches 1 2 of
20. ffects on Power Factor and V Limits The power factor is also affected by both analog and PWM dimming and is reduced at lower dimming levels This is shown in Figure 14 http onsemi com 18 NCL30051LEDGEVB 1 00 0 95 0 90 NH s M 0 85 POWER FACTOR PF 0 80 0 75 0 70 Vac P 0 10 20 30 40 50 60 70 80 90 10 ao eee TTL o LITAT JA 0 PERCENT OF FULL LOAD Figure 14 Power Factor versus Dimming Dimming Limitations PWM dimming is effective down to less than 5 duty ratio for 120 and 230 Vac within the V ranges shown in the graphs of Figure 8 above It is not recommended to take PWM dimming to zero as this will ultimately result in the power supply going into a start stop hiccup mode due to controller Vcc depletion Analog dimming is limited to 10 of rated max current due to depletion of primary circuitry Vcc Output Ripple The output current ripple is primarily a function of the amount of bulk capacitance C4 and C5 and the ripple on the bulk will be reflected to the output by the product of the transformer turns ratio and the half bridge switch voltage reduction ratio or as mentioned previously 5 x 2 10 Since the power factor control loop must have a low bandwidth to produce high power factor the 120 Hz bulk ripple will naturally be transferred to the output proportionally In this example the use of two bulk capacitors of 82 uF in series giving a to
21. ience This is especially useful in outdoor and underground lighting were bi level control can reduce the light level based on time of day or activity detection to save power without compromising safety In fact the California Lighting Technology recently published a study where bi level LED lighting saved 87 over conventional 70 W HID outdoor pathway bollards Publication Order Number EVBUM2039 D NCL30051LEDGEVB Beyond the power stage design circuitry is provided for demonstrating three types of dimming control Analog dimming with a O to 10 V programming signal Bi level dimming with a simple logic level input signal PWM dimming using an onboard oscillator with variable pulse width These three dimming functions are incorporated on an optional plug in DIM card Without the card the demo board can be dimmed with a user provided PWM input signal operating from 150 to 300 Hz The maximum output voltage can be adjusted via selection of a single resistor however it is compliant enough to handle almost a 2 1 output voltage compliance range depending on the string forward voltage and worst case high line voltage The default output current is set at 1 A but a maximum DC output current of 1 5 A is available by modifying a single resistor value Higher currents can be supported with different transformer designs The power level of this design is targeted at applications operation below 60 Vdc maximum and below 100 VA to be unde
22. ims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not
23. istor R9 is used to provide the zero current detect signal or de magnetizing signal to the chip from L2 s aux winding so that the circuit can operate in true CRM Tek BI DS Resonant Half Bridge Section The resonant half bridge is comprised of MOSFET switches Q2A and Q2B resonant capacitors C6 C7 transformer T1 and the associated components and half bridge driver section of U1 Since Q2A the upper MOSFET is floating at a switched node a bootstrap driver bias supply composed of D11 C9 and the internal circuitry of U1 is implemented for gate drive of this MOSFET The half bridge is operated with a fixed frequency symmetric duty ratio with dead time between each half cycle signal and is powered from the PFC bulk voltage The NCL30051 controller is rated for up to 600 Vdc operation in the half bridge section so factoring in system derating a maximum operating PFC bulk voltage in the 480 510 V range is recommended Resonant circuit operation is achieved by resonating the leakage inductance of T1 s primary with capacitors C6 C7 which appear in parallel By adjusting the L C ratio of these parameters to match the switching frequency of the gate drive output of U1 resonant operation is possible with very low switching losses in MOSFETs Q2A and Q2B The frequency of the half bridge drive is set by the C capacitor C10 This value can be changed to accommodate the resonant frequency determined by C6 C7 and T1 s leakage indu
24. izing max and min load Vs tolerances As seen from the 120 Vac input example there is much Vj latitude The usable dimming range can also be affected by the combination of line voltage and Vy This is particularly acute when using the analog dimming mode because this mode also reduces the primary side control circuit Vcc as the output current is reduced PWM dimming mode has less effect on the Vcc due to the fact that the Voc capacitor is peak charged and the reflected peak Vcc aux voltage does not appreciably decrease with PWM dimming Figure 8 shows the limitations of increasing AC input line on the minimum usable V out The diagonal section of the graph indicates converter shutdown and re start action http onsemi com 13 LED FORWARD VOLTAGE Vdc NCL30051LEDGEVB EE L LL EL tT It EL Id BERR o gt e 0 100 200 300 400 500 600 700 800 900 1000 OUTPUT CURRENT mA Figure 8 Output Current Voltage Transfer Function versus Line http onsemi com 14 NCL30051LEDGEVB o LED FORWARD VOLTAGE Vdc INPUT LINE VOLTAGE Vac Figure 9 Minimum Forward Voltage versus Line and Output Current Efficiency the efficiency is greater than 90 from 35 45 W for both With this topology it is possible to achieve better than 9096 120 and 230 Vac for this 50 W nominal design efficiency even at modest loads As illustrated in Figure 10 http onsemi com 15 NCL30051LEDGEVB EFFICIENCY 34 38
25. long with the associated bias drive and primary feedback circuitry As shown in the primary side schematic the circuit grounds should are segregated into three areas logic drive and power and interconnected at strategic star or tree points as shown to minimize ground loops and cross talk interaction For optimum circuit performance and stability it is critical that star grounding be used for the PCB layout Logic level timing and filter components such as C10 C12 C14 C15 C17 and C16 should be located as close to main controller U1 as possible Jumper JMP1 and test point terminals are provided to facilitate testing the PFC and resonant half bridge separately Jumper JMP3 can be used as a wire loop for a clip on current probe to check the current waveform profile and tuning of the resonant half bridge Referring to Figure 1 a combination common and differential mode conducted EMI filter is incorporated at the mains input The leakage inductance of L1 in conjunction with X capacitors C1 and C2 form a differential mode filter Common mode filtering is achieved via the coupled inductance of L1 and Y2 capacitor C27 which ac couples the primary and secondary grounds In this particular design the simple common mode filter indictor of L1 was sufficient to pass EN55022 Level A for commercial applications A plot of the conducted EMI is shown in Figure 14 and the harmonic line current profile is shown in Figure 1
26. ntroller The specific sensing circuitry is essentially identical to that used in ON Semiconductor application note AND8470 for the NCL30001 LED controller and will only be briefly described here Current regulation is accomplished by section B of U4 The output current is sensed by resistor R22 and the dc output current level can be adjusted by changing R26 If PWM dimming is used the circuit of Q5 C22 R31 and R32 form a sample and hold circuit that prevents the current pulse interruptions through current sense resistor R22 from corrupting the dc current sense information presented to pin 6 of U4B This keeps the peak current output level constant during PWM dimming Output voltage sensing is achieved via the sense divider of R28 and R29 and U4A The maximum output voltage can be adjusted by the value of R28 and is set to approximately 50 V in this application Both amplifiers drive optocoupler U3 which controls the pulse width of the PFC MOSFET by pulling compensation pin 8 low on the main controller U1 In this way the bulk output voltage of the PFC is regulated so as to provide a correct high voltage dc input to the resonant half bridge converter The amplifier whose output is lowest will be dominant thus providing constant current constant voltage control with a smooth transition at the CVCC knee To minimize the Miller capacitance effects of optocoupler U3 s photo transistor to the feedback loop R15 and D13 have been added to forc
27. r the maximum power requirements of IEC EN 60950 1 UL1310 Class 2 supplies The specification table below lists the key design objectives Specifications Universal Input 90 265 Vac up to 305 Vac with component changes Frequency 47 63 Hz Power Factor gt 0 9 50 100 of Load with dimming Harmonic Content EN61000 3 2 Class C Compliance Efficiency gt 88 at 50 100 of 50 W Tout 1A Ve 50V Target UL1310 Class 2 Dry Damp isolated lt 100 VA and lt 60 V peak Vmax Range 35 to 50 Vdc selectable by resistor divider Constant Current Tout Range 0 7 1 5 A 1 A nominal selectable by resistor gt 50 to 100 of Vout 2 or better Vout Compliance Current Tolerance Cold Startup lt 1 sec typical to 50 of load Pout Maximum 60 W Dimming Two Step Bi level Analog Dimming PWM dimming with optional DIM board PWM dimming frequency 160 Hz 300 Hz with external signal input referenced to a secondary side signal ground Dimming range gt 10 1 0 10 V 100K analog voltage input dimming 1 minimum 10 V is 100 on range dependent on nominal AC input Short Circuit Protection Open Circuit Protection lt 60 V peak Over Temperature optional Over Current Protection Auto recovery Over voltage protection input and optional output Protection Primary Side Circuitry The primary side circuit schematic is shown in Figure 1 It contains the PFC and resonant half bridge a
28. rward voltage of 40 V the bulk voltage will be regulated at Vout x Np Ns x 22 40x 5 x2 400 Vdc where two represents the fact that the half bridge primary switches only 1 2 of the bulk voltage Herein highlights a limitation of this topology in cases where the string voltage may be very low For a Vr of 32 V the bulk voltage will be 320 Vdc and this puts a limit on the maximum line voltage in which the PFC boost converter can function The bulk voltage must always be higher than the peak of the line voltage for the boost converter to work so at 230 Vac input the line peak is 1 4 x 230 322 V so now we have reached the lower limit of the LED forward voltage range Obviously at 120 Vac Vpeak 170 Vdc we could feasibly allow the output Vf to go even as low as 25 Vdc without any problems 25 Vdc x 5 x 2 250 Vdc bulk which is still higher than Vac peak Careful analysis of the throughput voltage conversion and proper selection of the transformer turns ratio will allow optimization for a given LED application A maximum operating PFC bulk voltage of 510 Vdc is recommended for adequate safety margins Examples and further discussions of the circuit limitations are addressed below under Topology Limitations http onsemi com 7 NCL30051LEDGEVB Part Description Resonant Half bridge Transformer 60 W 35 kHz Rev 3 Schematic ID T1 Core Type PQ20 20 Ferroxcube 3C95 or equivalent material Primary Inductance 6 mH minimum
29. supplies were tested for FCC Level A These results are shown in the figures below Green is peak conducted emissions Waveforms of the input line current at and red is average http onsemi com 20 NCL30051LEDGEVB dBuV 100 90 80 NCL30051 120 Vac 45 W output EN 55022 Class A Conducted Quasi Peak Peak Neutral 70 NA imi EN 55022 Class A Conducted Average 60 RE MI 50 40 30 20 10 5 18 2010 2 51 02 PM Tek alg Trig d M Pos 1 200 us CH1 Coupling 120Vac 45Vout BW Limit On 20MHz 1 Probe 10 Voltage Invert AC Line 0 004 60 0224Hz Volts Div Loarse CH1 200mvBy M 5 00ms 17 May 10 16 47 Tek ae M Pos 1 200 us CH1 Tria d Coupling Line Current 230Vac 45Vde out 1A B W Limit Un 20MHz s Div arse Volt 1 Co Probe 10 Voltage Invert AC Line 0 004 60 0018Hz CH1 200mVBy M 5 00ms 17 May 10 16 43 Bees WIESE Ale Nose e AR M 1 10 Start 0 15 Stop 30 00 MHz Figure 17 Conducted EMI Spectrum at 1 A with V 45 V Red average Tek EE M Pos 1 200 us CH1 Trig d Coupling Line Current 120Vac 30Vdc out BW Limit Un 20MHz Volts Div Coarse 1 Probe 10 Voltage Invert AC Line 0 004 60 01 46Hz CH1 200mvBy M 5 00ms 17 May 10 16 48 M Pos 1 200 us CH1 Tek J n Couplina Line Current 230Vac SOVde out 14 BW Limit On 20MHz s Div arse
30. tal capacitance of 41 uF was adequate to keep the output current ripple below 10 Figure 15 shows the output current ripple with an LED string of Vy 40 V The magnitude of the ripple is only slightly affected by Vr and line voltage http onsemi com 19 NCL30051LEDGEVB Tek Anl E Auto M Pos 1 200 us CH1 E Coupling Output Current Ripple 14 40V LED Load BW Limit On a tien ollie gg ne Volts Div Coarse Probe 10 Scale 200 m division Voltage Invert 1 CH1 200mVBy M 5 00ms CH1 2 38V 3 Jun 10 14 26 lt 10Hz Figure 15 Output Current Ripple at 1 A Load and V 40 Vdc Output Current Profile at Turn on overshoot The nature of the start up profile can be tailored Despite the low control loop bandwidth approximately by the proper selection of feedback compensation 25 Hz the output current profile during start up when the components R23 and C25 around current amplifier U4B ac line is applied is very well controlled from excessive The start up profile is shown in Figure 16 Tek ES O Acq Complete M Pos 100 0ms CH1 Coupling BW Limit On 20MHz J volts Div Output Current at Turn On Coarse 230 Vac Input Probe 200 m per Division vertical 10 Voltage 1 Invert CH1 200nVBy M 100ms CH1 680mV 3 Jun 10 12 56 lt 10Hz Figure 16 Output Current Profile at Supply Turn on 230 Vac Line Current and Conducted EMI different line voltages and V points were also captured The prototype
31. wing fewer LEDs to be used to achieve the same light output For example the Cree XLAMP XM L is rated for up to 3 A drive current and has a very low typical forward voltage of 31V 1500 mA drive current At 1500 mA and 85 C junction temperature in cool white each LED generates from 440 475 lumens typical with an efficacy of greater than 100 Im W So with just 12 LEDs the source lumen output would be in the range of 5200 5700 lumens at 85 C junction temperature and the typical load power would be 53 W which is over 100 Im W This application note also focuses on various options for dimming including PWM analog and bi level dimming Intelligent dimming takes full advantage of the instant turn on characteristics of LEDs and combines it with lighting controls to save significant energy without compromising lighting quality or user safety and comfort Some traditional large area light sources are difficult to easily dim and have long turn on times to full brightness This is not the case with LEDs as they can quickly be turned on and off and their lifetime improves when dimmed because the average operating junction temperature is reduced PWM and analog dimming are traditional techniques for dimming Bi level or multi level dimming uses these techniques and adds sensors or controls motion networked or timer based to incorporate two or more discrete lighting levels This allows additional energy savings without compromising safety and conven
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