8 Hints for Solving Common Debugging Problems with Your Logic
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1. 8 Hints for Solving Common Debugging Problems with Your Logic Analyzer Application Note 1326 oft Agilent Technologies Table of Contents Hint 1 Acquiring data from a multiplexed address data bus Hint 2 What to do when your target system is functioning normally but the data you capture does not appear to be valid Hint 3 Using a golden trace to troubleshoot unexpected system changes Hint 4 Using PC hosted mode to remotely control your logic analyzer Hint 5 How to capture data before a system crash Hint 6 Analyzing serial data with a logic analyzer Hint 7 Generating files for an Agilent pattern generator using third party EDA tools Hint 8 Selecting the right probe for your logic analyzer Logic analyzer families to help you get your job done Cost effective solutions that match your specific application needs Sales and Service Reducing the complexity in your job Logic analyzers are complex instruments They have to be in order to handle the capabilities of today s advanced electronic devices Unfortunately the complexity of logic analyzers can cause you headaches when you need critical information about your digital designs Yet using a logic analyzer is frequently the best way and sometimes the only way to understand how your device is working or why it s not So if you need to look at your logic in state mode for example or examine timing relationships on a large nu2. no initial sequences To export a timing diagram to a pattern generator simply go the Export menu in WaveFormer Pro i WayeFormer Pro and select Export Signals As as shown in Figure 17 This will bring up a dialog box that will allow you to save your file as pattern generator binary format pgb The pgb format is a binary format that is useful for large data files and is supported by the 16720A pattern generator It s also possible to generate input files for the pattern generator without using an EDA tool You can either program the pattern generator using the system interface or you can type the pattern generator commands in an ASCII file and import them into the pattern generator File Export Edit Bus Libraries Report Wiew Options Window Help Get Ba S RRR simdom Pll gt a Diagram C WaveForm WriteCycle tim Delay Setup Sample Hold fe 5 120ns 9 22ns n ponsi Data 7 0 Save As ClockSetup LstOnDelay Walid Data Save in My Recent Documents Desktop O waveform v My Documents 43 My Computer File name My Network Places reg Request reg 7 0 Addr wire Enable INS Row 4 Line 19 verilog log waveperllog Differences f Grep WriteC Figure 17 Exporting a file from Waveform Pro _ UN Eoee O ee aN lt gt 100ns Interactive HDL Simulation with editable HDL
3. systems Purchase the capability you need now then expand as your needs evolve Maximize mainframe usage by operating them separately then connecting them together for complex high channel count multiple bus Figure 23 Agilent 16900 Series logic analysis system applications Whether you are doing simple hardware debug real time analysis of instruction execution hardware software integration signal quality analysis or complex system validation you have a system that meets each of your long term digital measurement needs For more information on Agilent logic analysis systems visit www agilent com find logic Logic analyzer families to help you get your job done continued Cost effective solutions that match your specific application needs The Agilent 16800 Series portable logic analyzers offer the performance applications and usability your digital development team needs to quickly debug validate and optimize your digital system The 16800 Series have a large 15 inch 38 1 cm color display with available touch screen Each logic analyzer delivers 4 GHz 250 ps timing zoom up to 1 GHz timing analysis up to 450 MHz state analysis and memory depths up to 32 M Models with an integrated pattern generator let you control and monitor real time Figure 24 Agilent 16800 Series portable logic analyzers Related literature Publication title Agilent 16900 Series Logic Analysis System
4. 0 Series logic analyzers you can send the trigger to the oscilloscope which is also Advanced Trigger for My 16950A 1 Trigger Functions Trigger Sequence Step 1 Pattern present for gt t time Find Bus signst HEARTBT High Then x Trigger and fill memory v probing the device under test to get a better understanding of the cause of the crash Figure 10 shows what the oscilloscope caught prior to the trigger that it received from the logic analyzer In this case the oscilloscope can help get to the cause of the system crash Without an actual trigger event there would be no trigger signal to send to the oscilloscope Using timers in a logic analyzer s trigger system can allow you to trigger on nothing since you can describe the condition as too much time between successive heartbeats Figure 9 Configuring a heartbeat trigger J Lof 2 Figure 10 Oscilloscope display of results Hint 6 Analyzing serial data with a logic analyzer While logic analyzers are commonly used to analyze parallel data for example microprocessor address and data some modern logic analyzers also allow you to analyze serial data This feature comes in handy when you are trying to debug simple serial protocols such as RS 2382C CAN LAN USB or your proprietary bus Here s an example of how to use an Agilent 16900 Series logic analyzer to analyze and troubleshoot data from
5. Code ala xX Gy EJ Toos Save as type Microsoft Office Excel Workbook xIs Scie 150ns 20 GateDelay aa v Save v Cancel 11 Hint 7 Generating files for an Agilent pattern generator using third party EDA tools continued An example of a file you can load into the pattern generator ACSII 000000 ASCDOWN FORM MODE FULL LABEL LAB1 8 LABEL DATA 8 LABEL TEST 9 LABEL CLK 3 VECT 800000092 12 34 56 7 02270 A0 33 00 1 M 92 6F 00 1 CA CA 001 0010110 In the 16800 Series logic analyzer select Overview gt File gt Import Select Pattern Generator Binary file as the file type and click the pgb file as shown in Figure 18 Then select the Pattern Generator Sequence tab and click Run That is all you have to do The data in the input file has been imported into your pattern generator Figure 19 shows the pin assignments in the pattern generator and Figure 20 shows the pattern generator sequence that will result from your actions The combination of WaveFormer Pro and an Agilent logic analyzer makes a powerful design and debugging tool We ve demonstrated how to get data from WaveFormer Pro into Agilent s pattern generators In addition data captured by your logic analyzer can be imported into WaveFormer Pro The circuit operations captured by the logic analyzers can be translated by WaveFormer Pro into stimulus files for driving the s
6. End of Frame Start of Frame Data Block End of Frame Signal Name StartOfFrame E Output bus Parallel Word width 8 End frame alter data block of 8 Pattern Width Remove stuffed End frame on pattem Jptions Start Pattem x Pass entire data block Pass selected bits in data block Options Cancel Help Cancel Help Figure 13 Start of Frame dialog box Figure 14 Data Block dialog box Figure 15 End of Frame dialog box Serial To Parallel 1 Sample Number Parallel Parallel Time Signed Decimal Hex Ascii Absolute ms ms ms ms 6 600000 ms 7 740000 ms ms ms O O JAN b amp b WN mO ip wm w ms H tj ms ms ms j b b S in 11 12 2i i 14 s e O ms ms a in iO ms 9 210000 ms PAA 0 360000 ms l J O H a5 y NN NY NIQ N m A a El ms 0D Nw ms J j Ta in N ms ms nm J 26 080000 ms 27 220000 ms 28 370000 ms J inNnbe bb W ol Figure 16 Data listing 10 Hint 7 Generating files for an Agilent pattern generator using third party EDA tools Electronic Design Automation EDA tools have become an integral part of most engineers tool sets You can use EDA tools for drawing analyzing simulating and documenting the circuits that you are working on Wouldn t it be nice if you could leverage the work that you did in your EDA environment while debugging your protot
7. Mainframes Agilent 16800 Series Portable Logic Analyzers Publication type Data sheet Data sheet Publication number 5989 0421EN 9989 6063EN system operation Select from eight models that range from 34 to 204 channels to meet your demanding troubleshooting challenges For more information on Agilent portable logic analyzers visit www agilent com find 16800 15 as Agilent Email Updates www agilent com find emailupdates Get the latest information on the products and applications you select Agilent Direct www agilent com find agilentdirect Quickly choose and use your test equipment solutions with confidence Agilent f Open aa www agilent com find open Agilent Open simplifies the process of connecting and programming test systems to help engineers design validate and manufacture electronic products Agilent offers open connectivity for a broad range of system ready instruments open industry software PC standard 1 0 and global support which are combined to more easily integrate test system development LX www xistandard org LXI is the LAN based successor to GPIB providing faster more efficient connectivity Agilent is a founding member of the LXI consortium Phone Americas Canada Latin America United States Asia Pacific Australia China Hong Kong India Japan Korea Malaysia Singapore Taiwan Thailand Europe Austria Belgium Denmark Finland France G
8. Unnamed Configuration Overview S file Edit View Setup Tools Markers Run Stop Overview Window Help D o gt ed Mill to M2 Ht is Windows Modules E ity 16910 11 1 HERI a Listing 1 e V B wavetorm 1 Ss Lae GE Compare 1 q amn Your stored golden trace file K Figure 6 Using compare on signals and buses s Compare 1 gt gt Copy Range amp Offset Compare Until 76 0100 1011 Pf O100 1100 78 0100 1101 79 0100 1110 60 0100 i111 81 0101 Mooo 82 0101 0001 83 0101 0010 84 0101 001i 85 0101 0100 86 0101 0101 SS Overview Sample Number My Bus 1 mnnn a Listing 1 SA When differences occur data is shown in a different color Waveform 1 Se Compare 1 Figure 7 Using the compare window to identify changes Hint 4 Using PC hosted mode to remotely control your logic analyzer PC hosted mode allows you to remotely control your logic analyzer through the network It uses the power and speed of your remote PC If you are connecting through a PC with higher speed and better memory specifications than your logic analyzer your logic analyzer operation will be more efficient Simply install the Be Salzer Syston 19 Us logic analyzer application on your PC and provide the IP address or the hostname of the logic analyzer you want to connect to This feature also allows users from multiple sites or regions to access
9. also allows you to specify the logic for the master and slave clocks Then go to the Bus Signal Setup tab shown in Figure 3 and assign the pins for your logic analyzer probe Note that your logic analyzer s setup and hold requirements in demultiplex clocking mode may be different from those in normal clocking mode Check your logic analyzer s specifications for details Poststore 1M v Thresholds and Sample Positions Select Master Slave Demux mode Read address here Read data here Ce Display Q QJ Slot 8 Pod 1 Tiweshotd TTL Thweshold TTL tos B cin a sd SF 6 F SIS TS 10S URNI Figure 3 Formatting clock mode wove rest sit dues Assign pins here EERE import Netist System Summary Hint 2 What to do when your target system is functioning normally but the data you capture does not appear to be valid This situation occurs in several circumstances 1 When your logic analyzer sampling thresholds do not match your target system s switching characteristics 2 When you re in state sampling mode and your target system does not meet the setup and hold times required by your logic analyzer 3 When the target system generates excessive noise ground bounce simultaneous switching noise or crosstalk causing the analyzer to sample incorrectly Adjusting various logic analyzer settings often resolves the first two conditions The third condition noise is most ofte
10. an RS 232C output port Once you have connected the serial port on your target system to the logic analyzer through one of its data pods you will need to put the logic analyzer into timing or asynchronous mode because the sampling clock is being supplied by the logic analyzer Even though you are in timing analysis mode you will be able to view the data as parallel information in a listing form via the B4601C serial to parallel analysis tool Next you will need to assign a label serial to the input data bit The RS 232C protocol has a data format with 1 start bit 8 data bits and 1 5 stop bits as shown in Figure 11 To capture the data you can set the trigger on any data value Here we have set the trigger on the start bit Once you have done this you will need to configure the serial analysis tool as shown in Figure 12 Select the Serial input label and create an output parallel label with a word width of 8 bits with the LSB as the first bit This dialog box will also allow Start bit you to choose the right bit order to invert the input data so that it is easier to analyze Now comes the really neat part You will have to specify to the logic analyzer how you would like the input frame to be processed Under Advanced Processing select the Enable frame processing check box and click Define 1 5 stop bits i 104 17 us 8 data bits Figure 11 Timing for RS 232C before it is inverted Serial To Paral
11. e the sample clocks are coming from the device under test set the analyzer to State or Synchronous mode Address clock specification CLK rising AND ADS low true Data clock specification CLK rising AND DS low true ADS DS l l ADDR DATA l BUS Figure 1 An example of a multiplexed bus The key to making this measurement is to determine the clock or clock combination for the address phase and for the data phase If these are not different the bus is not really multiplexed As an example in the Agilent Technologies 16800 and 16900 Series logic analyzers you can go to the logic analysis Overview window and on the logic analysis module click the Sampling Setup icon On this screen you can set your logic analyzer to Analyzer Setup for My 16910 11 1 orn Buses Signals Sampling Acqueshor Timing 4synchronous Sampling State Sychionous Sampling 500 Mb s maximum clock rate Timing Options 7 Force Prestore Acquisition Depth State Options Speedy when the logc analyzer should acquire samptes Sampling Options 250 MHz v Clock Mode Matter Slave Demx v Advanced Clocking 1 Pod Bi Clock Description Chk2 aki 0 s X s spot Figure 2 Sampling clocking mode Analyzer Setup for My 16910 11 1 __ Buses Signas Sampling Enter buses and signals and the channels they comespond to Master Slave Demux clocking mode as shown in Figure 2 This screen
12. ermany lreland Italy Netherlands Spain Sweden Switzerland Switzerland United Kingdom www agilent com For more information on Agilent Technologies products applications or services please contact your local Agilent office The complete list is available at www agilent com find contactus 877 894 4414 305 269 7500 800 829 4444 1 800 629 485 800 810 0189 800 938 693 1 800 112 929 81 426 56 7832 080 769 0800 1 800 888 848 1 800 375 8100 0800 047 866 1 800 226 008 0820 87 44 11 32 0 2 404 93 40 45 70131515 358 0 10 855 2100 0825 010 700 01805 24 6333 0 14 minute 1890 924 204 39 02 92 60 8484 31 0 20 547 2111 34 91 631 3300 0200 88 22 55 French 44 21 8113811 Opt 2 German 0800 80 53 53 Opt 1 44 0 7004 666666 Other European countries www agilent com find contactus Revised March 23 2007 Product specifications and descriptions in this document subject to change without notice Agilent Technologies Inc 2007 Printed in USA April 19 2007 0968 5 700E ae Agilent Technologies
13. imulations to test your circuit design For more information see your logic analyzer user manual or go to www syncad com 12 Look in e waveform B patten_generator pgb File name pattern_generator pab Destination My 167204 1 v Figure 18 Selecting the file to load into the pattern generator Pattern Generator Setup Buses Signals Clocking Sequence Macros Enter buses and signals and the channels they correspond to Bus Signal Hame Sanaa Width x LAB Pod F6 7 0 8 X DATA Pod F5 7 0 8 Xx K TEST Pod F4 7 0 9 W CLK Pod F3 6 4 3 Pod F3 3 0 12 Figure 19 Pattern generator pin assignments m Files of type Pattern Generator Binary Files pgb v YASASININ 0 7 61514 312 110 7 861514 3 21110 71615141312 1110 Pattern Generator Setup Buses Signals Clocking Sequence Macros Figure 20 Pattern generator sequence Hint 8 Selecting the right probe for your logic analyzer When you use a logic analyzer working with low speed signals in memory debug you would one of the most important and have very few debug pins want to have easy access to considerations is the type of High speed board design and command data and address probe Probing connections are complicated circuitry calls buses It is also important to divided into two categories for higher bandwidth and place the connector or footprint designed in and after thought low loading probes Designed i
14. lel 1 Input Bus Signal Serial Output Bus Parallel Name Parallel E width 8 bits Bit Order LSB First v Start Sample 2 J Advanced Processing Enable frame processing Enable clock recovery OK Cancel Help Make sure this box is selected Then click Define to bring up the Frame Parameters dialog boxes Figure 12 Serial analysis window Hint 6 Analyzing serial data with a logic analyzer continued In the dialog box for specifying stuffing Since you do not to look at the serial data the frame parameters you can need to perform any pattern Figure 16 shows a listing of the specify the start of the frame to manipulation pass the entire data looking at just the parallel have the label Start as shown data block through In a similar labels It shows the serial data in Figure 13 It is binary and has fashion under the End of Frame coming down the output port As a width of 1 bit Under the Data tab you will need to specify that you can see the serial analysis Block tab clear the box for the frame ends after 8 bits as tool in the logic analyzer gives stuffed Os because the RS 232C shown in Figure 15 Having done you the versatility to analyze and protocol does not do any bit all this work you are now ready debug serial protocols Frame Processing Frame Processing Frame Processing LD p He O A E Start of Frame Data Block End of Frame Start of Frame Data Block
15. mber of channels you might reluctantly pull out your logic analyzer Sound familiar We d like to help you overcome your reluctance by helping you build the measurement expertise you need to do your job That s why we ve gathered and published these hints They are not intended to be comprehensive tutorials They are suggestions intended to help you understand how you can use logic analyzers most effectively and how they can help you save time in getting your job done Hint 1 Acquiring data from a multiplexed address data bus Many engineers who design with modern microprocessors and micro controllers use multiplexed buses in order to conserve pins and reduce cost Engineers used this technique in early processors such as the Intel 8088 and they re using it in current processors such as custom cored ASICs In order to effectively capture the information you need in this complex design arena you need a logic analyzer with specialized features Today s logic analyzers offer specific clocking capabilities to handle the acquisition of address and data from multiplexed buses You can capture information on two different clock events one when the address is valid and another when the data is valid Because the bus is multiplexed you only need one set of logic analyzer probes You can connect the logic analyzer probes to the multiplexed address data bus either with individual probes or through a probing adapter Sinc
16. n only resolved by design changes to your board Let s look at the first two situations Different logic families have different switching thresholds Some examples TTL gt 1 5V 5V CMOS gt 2 5V 3 3V CMOS gt 1 6V If you suspect that sampling thresholds may be the cause of your problem then the solution is straightforward First identify the logic families and therefore the switching voltage of the signals you are probing Next change the threshold settings on the logic analyzer Some analyzers allow you to set different thresholds for different groups of signals The Agilent 16800 and 16900 Series logic analyzers allow independent settings on 16 channel one pod boundaries In addition to the standard switching thresholds these logic analyzers allow you to specify any arbitrary threshold From the logic analysis Overview window and on the logic analysis module click the Bus Signal Setup icon This screen allows you to change both the sampling threshold and the setup and hold times Figure 4 shows the threshold setup dialog box Click here Analyzer Setup for My 16910 11 1 Buses Signals S amping Enter buses and signals and the channels they correspond to Slot B Pod 2 Threshold TTL Channels Bus Signal lame Asclaned i ee Pod B1 7 0 8 lt Figure 4 Changing your analyzer s thresholds en Threshold Settings Slot B Pod 2 v Apply settings t
17. n as close to the signal source as A designed in probe has proper probes such as Samtec and possible to avoid signal integrity connectors incorporated into connectorless probes meet these issues You may then use the design during board layout criteria When you work with after thought probing for after thought probes are FPGAs or components designs it unforeseen problem signals connections made with an is important to first identify the Adopting the right probing method individual probe tip as shown in signals of interest for testing or will greatly increase efficiency in Figure 21 After thought probing debugging purposes For example your debugging work is the best solution when you are Figure 21 After thought probe Flying leads Figure 22 Designed in soft touch connectorless probe 13 Logic analyzer families to help you get your job done The Agilent 16900 Series modular logic analysis mainframes deliver the performance you need to conquer your toughest digital debug problems You get accurate and reliable measurements for today s complex circuits with expandability and performance headroom to cover future technology trends In addition the intuitive user interface gives you the ultimate in productivity without sacrificing performance or capability You get performance and intuitive usability at a price you can afford Expandability is the key to the long term value of the Agilent 16900 Series logic analysis
18. o all pods Threshold Settings Probe General purpose probing Standard TTL 1 50 v Cm C e fam X Slot B Pod 1 Tiweshold TTL 654 2 i0 uese tT VJJ gt Change threshold here Hint 2 What to do when your target system is functioning normally but the data you capture does not appear to be valid continued The second situation involves setup and hold times and only occurs when you sample based on the clock supplied by the target system The solution here is also relatively straightforward First determine the setup and hold requirements of the logic you are probing Hopefully you considered this in your design because the interconnected ICs must satisfy each others setup and hold requirements Next determine the setup and hold time requirements for your logic analyzer Does your target meet the logic analyzer s required time If the window setupthold supplied is smaller than that required by the logic analyzer you may need to upgrade your logic analyzer If the window is larger but either the setup or hold time is violated you may be in luck Some logic analyzers allow you to adjust the window as needed The example shown in Figure 5 shows that you can adjust the state sampling position and the threshold voltage setting It also allows you to set different channel groups differently Adjusting your thresholds and setup hold windows can be valuable ways to sq
19. t crashes Here s one way around the problem use a timer in the logic analyzer to get a trigger soon after the system crashes To use a timer in the trigger first figure out what event should happen regularly in order for you to consider your system under test alive and working fine Let s call this event the system s heartbeat This could be an address strobe a periodic interrupt or anything that occurs consistently at some minimum frequency Then set a timer equal to the longest period between successive heartbeats that you would expect to see before you would consider the system nonfunctional In the trigger sequence if you start the timer when a heartbeat occurs and restart the timer whenever another heartbeat occurs you can then test if the timer reaches the maximum value that you set If the timer reaches the maximum value then the logic analyzer should trigger since the heartbeat isn t occurring as often as it should You can also experiment with the timer value to determine just how long a period between heartbeats is normal Here s an example of this trigger timer idea using an Agilent 16800 Series portable logic analyzer and an external oscilloscope Set up the logic analyzer trigger as shown in Figure 9 The heartbeat in this example is a signal that consistently occurs at 8 us intervals This trigger setup will force a trigger 10 us after the last heartbeat With the Agilent 16800 and 1690
20. the same logic analyzer to acquire and analyze data Access to the logic analyzer is locked if someone else is using it If you wish to use the logic analyzer you can use the chat function to send a request to the current user to free up the instrument To allow others to access the instrument the current user can save his or her acquired data as ala files and use the offline analysis tool to view them on the PC TET System Current Status Analyzer Description Available 169024 Logic Analysis System lt not in use gt Host offline lt none gt lt not in use gt lt none gt lt not in use gt m tess cc _ Set Local Password Set As Auto Connect Figure 8 Connecting remotely to a logic analyzer session Hint 5 How to capture data before a system crash Capturing the cause of a system crash can be tricky with a logic analyzer This is true because you have to get the instrument to trigger when nothing happens How do you describe nothing to a logic analyzer s trigger menu One tried and true technique is to set up the logic analyzer to store only the data of interest and never trigger Then you can stop the instrument manually when the system under test crashes When this technique works the logic analyzer has a history stored in its pretrigger trace buffer But this technique only works if you can set up your logic analyzer to capture meaningful information then stop when the system under tes
21. time trace so you can find the differences You can set up the compare window to perform the comparison on specific signals or buses or on all signals or buses that are present in both data sources You can also set it up in a repetitive run mode in which each new run is compared to a data file You can set up the analyzer to stop capturing and comparing data when it finds a specified number of differences In the example shown in Figure 6 the compare window has an analyzer as one data source and a data file as the other The data file represents your stored golden trace You can display the results of the comparison using a compare window The data that is different in each source is highlighted This technique shows you what changed between your golden trace and the current trace and helps you quickly identify what caused the problem Often simulators are used to test software when hardware is not yet available When the first versions of the hardware become available the software that was tested and working on the simulation system may not work on the actual system hardware You can use the compare tool to compare simulation data that has been run through a conversion program so that it can be read by the analyzer with real acquired data This helps you with hardware software integration by letting you quickly find signals that are not behaving as they did in the simulations Offline Agilent Logic Analyzer
22. ueeze more mileage out of your analyzer especially if your target system is heavily taxing the capabilities of your current analyzer Thresholds and Sample Positions Legend I Current Sample Postion tSample Current Threshold vThresh 4 Suggested Threshold Signal Buses Signals to Run viJ My Bus 1 0 viIJ My Bus 1 1 vij My Bus 1 2 Auto Threshold and Sample Position Setup Figure 5 Adjusting sampling positions If your logic analyzer meets the specifications required by your target system and neither of these techniques solves your problems you most likely have a noise problem That means it s time to get your oscilloscope back out and put on your analog designer hat A Suggested Sample Postion Signal Activity Envelope Advanced Activity 8 Channels Selected for Run Adjust state sampling position and threshold voltage settings Hint 3 Using a golden trace to troubleshoot unexpected system changes When you are developing your target system and it is working properly life is good This is the time you should connect your target to a logic analyzer and capture a golden trace of the signals Performing this small task might save the day if your target system starts behaving unexpectedly If you have saved a golden trace you can use your logic analyzer s compare window to zero in on the problem The compare window takes data from a stored golden trace file and compares it to a real
23. ype The pattern generators that are integrated into Agilent logic analyzers allow you to do this without much trouble With shrinking times to market you typically cannot wait for your prototype to be complete before you start testing Suppose your circuit board is ready but your third party partner has not yet delivered your ASIC The pattern generators available in Agilent logic analyzers allow you to debug your circuit by replacing the missing components All you need to do is program the pattern generator and hook it to the circuit where the ASIC belongs The integrated pattern generator will stimulate your circuit while you analyze it using the logic analyzer SynaptiCAD the creators of WaveFormer Pro an EDA tool used for drawing analyzing simulating and documenting timing diagrams has worked closely with Agilent to make it easy for you to export your timing diagrams to Agilent s pattern generators Once you have created your timing diagram using WaveFormer Pro make sure that it includes a sampling clock and user created signals because the signals are sampled using the first clock in the timing diagram In addition the diagram should include at least one documentation marker The first documentation marker found in the timing diagram denotes the beginning of the main sequence separating the initialization from the main section If no documentation marker is present only main sequences will appear i e
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