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GENISvs· MICROLOK PLUS TM - Ansaldo STS

1. ic14 ean bane fk pie Sep eto EMULATION OR e DOES NOT USE APPLICA kab Wow Sa S acs UP TO 5 APPLICATION LOGIC TION LOGIC EPROMS OR J EPROMS IC 24 25 26 27 28 BEER PEN aera NON USES GENISYS DEVELOPMENT VITAL SECTION oe il FOR APPLICATION LOGIC NOTE AA oo eee ae NON VITAL APPLICATION LOGIC MICROLOK PLUS COVERED IN THIS MANUAL REFER TO SM 6400A FOR VITAL APPLICA TION LOGIC PROGRAMMING Figure 3 2 MICROLOK PLUS Application and Executive Software 6300A p 3 4 3 2 COMPONENTS 3 2 1 Cardfile see page v and Figure 3 3 The MICROLOK PLUS package is housed in a printed circuit board cardfile designed for mounting in a standard 19 inch equipment rack Vital section boards are placed in the ten left most slots while non vital boards are placed in the three right most slots The non vital section is controlled by a single Controller PCB Two slots are provided to the right of the Controller PCB for local interfacing When the application requires only one relay output r optical input board this board is always installed in slot P When the application requires one relay output and optical input board the relay output board is always installed in slot P and the optical input board is always installed in slot Q 3 2 2 PCBS 3 2 2 1 Controller N451441 5602 The Controller PCB performs all logical decisions and calculations for the MICROLOK PLUS non vital section and serves as the remote communica
2. 200 Number of relays with parailel values integer 20 Total number of spares defined integer 26 How many timers defined integer 69 Will the SLAVE port be used yan y How many MASTER addresses integer 3 How many local VO boards integer 10 Average number of CONTACTS per assignment statement integer 6 Average number of OPERATIONS per assignment integer 5 Total Memory usage 24632 bytes ar 24 6K NOTE For a MICROLOK PLUS program the local I O boards total is Limited to l or 2 Each SPROM can store 8K bytes of application programming Therefore the above application would require approximately three ZPROMs 24 6 8 will be required 4 8 G D S EPROM PROGRAMMER NOTE This section includes references to the Data I O Corp Model 21A and 201 EDROM programmer which were origin ally supplied with the GENISYS Development Svstem These references have been retained for current Model 212 users The Model 21A was replaced in 1987 with the Data I O Corp Model 201 EPROM programmer The Model 201 was replaced with the Data I O Corporation Model 212 in 1991 GENISYS Development Svstem Versions 1 02 and higher accomodate Models 21A and 201 Version 3 90 is required for the Model 212 4 8 1 General The GENISYS EPROM Programmer GENPROM is used to make final checks of the compiler EPROM table and transfer that table to the Controller board EPROM ICs This program raquires the Data
3. Because of the skew factor US amp S recommends that all time delays be defined at greater than 100 milliseconds This will insure that the desired delay is preserved The rastriction does not have to be observed if the time delav is used to alter the order in which logic equations are queued for queuing order smaller time delays can be used The two queue ootion will still cause breaks equations to be executed before makes equations even if the makes ar2 queued first Therefore a longer time delay may be necessary ta force a make equation to occur before a break equation 6300A Dd 5 2 5 3 VALIDATION OPTION 5 3 1 Introduction The Validation Option Validate Value compiler switch oravents the GENTSYS or MICROLOK PLUS non vital system from delivering data until all inputs requirad to determine the outout state have been received This option is orimarily intended for reset conditions If an unexpected reset occurs outputs should be left in the state they held before the reset until a new valid state is determined by receiving inputs and processing logic If the Validation Ontian is turned off an output could be derformed before all inputs have been received This may cause a momentary change in outputs until all inputs have been received For example 0 represents an unoccupied track circuit TIt is being read as a local input and is assigned as a serial output for transmission back to an office During the time the tr
4. 4 3 GENISYS DEVELOPMENT SYSTEM G D S GENERAL The GENISYS Development Svstem G D S enables the user to compose debug and load an application program into the GENISYS or MICROLOK PLUS non vital section system hardware Refer to Appendix A for development system components Note A text editor is not available with develooment system Figure 4 5 shows the general steps in the use of the G D S The source program is written and entered into the compiler using a text editor The compiler checks the program for proper terminology and format and lists any errors in a listing file Using the information in this file the user returns to the text editor and corrects these errors The compiler cannot detect mistakes in the user s application of logic statements These are located using the Simulator Again the user returns to the text editor to correct errors When the simulator indicates satisfactory operation of the program it may be loaded into the Controller PCB EPROM The compiler is used to convert the source program into PROM tables The EPROM programmer unit performs final checks of these tables and the EPROM itself before actual loading of the data into the chip PROGRAM GA CA gt gt COMPILER gt SIMULATOR EPROM IC PROM 4 me EDO GRAMMER Figure 4 5 Development System Block Diagram 4 4 G D S AVAILABLE FILES The GENISYS Development System software uses seven file extensions These extensions enable the
5. mo W TJ Mach i bI b MAK YON POWER FOR ni CUT OFF RELAY AND f a L i ti CONTACTS RELAY il LAMP DRIVE mennenenn OPTIONS k kata ae a ieee 4 t 12 VDC BATTERY 24 VDC SUPPLY a e VITAL MAST PORT 12 VOC BATTERY VITAL SECTION eee NON VITAL SECTION POWER SUPPLY CONVERTER d NON VITAL BUS ms PORTS PRO vo cope pem 1 Bi DC STD SID con retay opto cesson Bus f system prera OR POLAR LAMP INPUI INPUT TROLLER OUIPUI INPUT pca nierk mimere pce voit REtAY priver ece PCB Pce ecs FCB TOTAL WO pca PCB LIMITED DRIVER PCB Bi SLOTS 10 RELAY Pce POLAR L ee DRIVER CONFIG pco VITAL CPU 41 x4N4 44 VITAL WO 3 1 3 Application and Executive Software See Figure 3 2 Bach section vital and non vital of the MICROLOK PLUS unit incorporates its own independent Application and Zxecutive software These ara contained in EPROM chips on the logic boards of the respective sections The Application softwara or logic in each section is developed for the specific installation either by US amp S or the customer The source program is written and compiled on a computer using a language that enables the system logic to be expressed in terms familiar to the railroad engineer The finished program is converted into a form that can be entered or burned inta the EPROM chips The MICROLOK PLUS non vital anplicat
6. 4 1 In this example the 1 GENISYS or MICROLOK PLUS unit receives two bits RCV A 2 and RCV B 2 from the 2 unit and two more bits RCV A 3 and RCV B 3 from unit 3 Two bits SND A 2 and SND B 2 are also sent from unit 1 to unit 2 and two bits SND A 3 and SND B 3 are sent from unit 1 ta unit 3 UNIT 1 MASTER MP MASTER PORT SP SLAVE PORT MP sP sp UNIT 2 SLAVE UNIT 3 SLAVE Figure 4 1 Master Slave Communications Programming Reference Diagram The program code for unit 1 in Figure 4 1 MASTER I O subsection is as follows MASTER ADDRESS 2 OUTPUT SND A 2 SND 8 2 INPUT RCV A 2 RCV B 2 ADDRESS 3 OUTPUT SND A 3 SND B 3 INPUT RCV A 3 RCV B 3 6300A p 4 15 In the Slave units the SLAVE subsections must nave ADDRESS OUTPUT INPUT listinags that correspond to the equivalent listing in the Master unit program Both programs in this example ar similar accepting two input bits and sending two output bits The input and output bits in the Slave unit programs need not use the same names as the corresponding bits defined in the Master unit program However the input output order must be correct The first bit on the Master unit s MASTER output list is the first bit on the Slave unit s SLAVE input list etc The program for the Slave section of unit 2 is as follows SLAVE ADDRESS 2 OUTPUT OUT 2 A OUT 2 B INPOT IN 2 A IN 2 3 The prog
7. 4 24 If the timer value is not specified the contact will operate at a speed which cannot be detected bv the run time system This would create an indeterminate function at this point inhibiting execution of the program The double coil relay examples in Figure 4 4 are conceptual models which pertain to signal control slotting Models can not apply to circuits with control contacts to both coils of a double coil relay The pertinent program statement for the model containing the CANCEL contact is ASSIGN NOT CANCEL AND IN 1 TO IN 1 The capability to assign to serial inputs may be applied to the design of auto clearing controls In the case of auto clearing of requests if the input is a request for a clear signal and CANCEL is a track relay the signal request will be cleared when the track is occupied The following statement shows how requests from the office can be cleared if the communications link is lost ASSIGN MASTER ON AND IN 1 TO IN 1 These techniques are presented as conveniences for designing auto clearing logic They may not be suitable in all applications Consult US amp S Engineering for further guidance in the development of this type of logic Cascading timer relays are used to build up a comparatively long delay on the output delay relay Only one timing specification SET and CLEAR needs ta be written for all timer relays equal addends for the desired delay Tl T2 SET 5 SEC CLEAR 5 SEC 6300A D 4 25
8. 4 6 a Table 4 4 Software Switch Sectinas for Slave Port Baud Rate EE e Switch Baud Switc Baud Value s Rate Value s Rate 1 50 9 1800 2 75 A 2400 3 110 B 3600 4 134 ai 4800 5 150 D 7200 6 300 E 9600 7 600 8 1200 Table 4 5 Software Switch Settings for Master Port Baud Rate Switch Baud Switch Baud Switch Baud Value SM Rate Value m Rate Value M Rate 0 Hardware 5 150 A 2400 1 50 6 300 B 3600 2 75 7 600 C 4800 3 110 8 1200 D 7200 4 134 9 1800 E 9600 Defaults to baud rate set on Controller PCB rotary switch SWI Only applicable to Executive software revisions 11 0 and hiaher Table 4 6 Software Switch Settings for Control Delivery Time 2 Software Switch Software Switch SO Setting Control Del Time So Setting Control Del Time 1 10 msec 9 4 sec 2 30 msec A 8 sec 3 70 msec B 16 sec 4 130 msec c 30 sec 5 250 msec D 1 min 6 S00 msec E 2 min 7 l sec F 4 min 8 2 sec 6300A p 4 7 4 2 3 Program Examples 4 2 3 I Local Input Output The following Sample program shows the basic local input output and logic features of the non vital program language PROGRAM NBR1 INTERFACE LOCAL OUTPUT WORD OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 INPUT WORD IN A IN B IN C BEGIN ASSIGN IN A AND IN B TO OUT 1 ASSIGN IN A XOR IN B TO OUT 2 ASSIGN IN A OR IN B TO OUT 3 ASSIGN NOT IN A TO OUT 4 ASSIGN IN C TO OUT 5 END e VR The major se
9. 5 will be used by the run time system to determine what address the SLAVE port will respond All output bits must be specified before input bits The user has defined OUTPUT information after specifying the INPUT specifications for a given section In every I O section the OUTPUT s must be specified first Use of SPARE in ASSIGNMENT statement The special identifier SPARE has been used in an ASSIGN statement Only user defined relay names may be used ID relay name is undefined The user has specified an undefined relay name in a TIMER statement or an ASSIGN statement Every relay used in these statements must be defined in some I O section or the VAR section Invalid Switch setting Switch s The setting specified for this switch is invalid Check individual switch documentation 6300A p 8 3 22 ID relay name multiple assigned The relay name shown appears in two ASSIGN statements Bach relay may only be ASSIGNED in one 1 statement 23 ID relay name already specified in this ID list The relay name shown appears twice in an ID list 25 Assignment of SPARE as timer bit SPARE may not appear in a TIMER statement 26 Assignment of SPARE as internal bit SPARE may not appear in a VAR statement 27 ID relay name Set and clear delay for this timer bit are both 0 A timer bit was defined to have both a set delay and clear delay of zero The system will work properly but additional processing
10. CR When an invalid timer bit is cleared the clear time of that relay is recorded in the Status column and the relay is placed on the timer queue However the relay itself is neither set nor clear Note that the Timer List entry in the status line changes from 0 to 1 This shows that one timer relay has been placed on the timer queve Note also that the change to this relay is noted in the scroll area 6300A p 4 41 TI is next given a Set command SE 19 CR or SE TI CR The effec of chis command at this time is to ramove Tl from the timer queune and set it TI is then given another Clear command With this action the ralav is placed on the timer queue When the simulation is conducted and 1000 nillisaconds elanse the bit will be removed from the timer queue and the relay will finally be cleared Bit Number Name Value Status Bit Number Name Value Initial clear of HF aaa relay T1 e AR 19 T1 1000 cir Trigger List 10 System Time 00 00 00 000 Timer tist Command a T1 Program NBR3 Screen Relays put relay 19 on timer queve Bit Number Name Value Status Bit Number Name Value Set relay T1 A 19 Ti set Trigger List 10 System Time 00 00 00 000 Timer List 0 Command SE T1 Program NBR3 Screen Relays remove relay 19 T1 from timer queue Bit Number Name value Status Bit Number Name Value Relay T1 set IN ae SS and queued for clearing ef 19 T9 set 1000 cir Tr
11. Cause Remedv Error found by progran mec during download such as illegal address in code or unknown ra cord type Compiler output corrupted by bad disk or attempted alter ation in compiler code Refer to programmer manual for error code meanings Communication error be Check settings of rotary tween programmer and Switches on programmer computer involving par under keypad and ity framing overrun check installation of oc baud rate BIA cable During verification step programmer did not re ceive same data again This may be caused by Communication error Repeat procedure Check EIA cable and pra grammer Hardware error Bad data media compu Use new disk ter did not read same data Programmer detected an error during final pro gramming phase usually indicates bad EPROM Refer zo programmer manual for error code meanings Check settings of rotary switches on programmer under keypad Programmer terminated operations after a set number of attempts to create a communications link Usually caused b bad initialization of programmer 6300A on 4 61 4 8 5 Communications Interrupt Tf the EPROM oprogrammer is interruoted while interactive with the compute i e turned off reset or TIA cable disconnected the GENISYS EPROM srogrammer will cease operation This is indicated by lock up of the computer no cesponse to any commands To remedy this problem correct the problem and reset t
12. Closed Parity Disabled default Open Parity Enabled 6 Closed Odd Parity Open Even Parity To simulate earlier revisions pre Revision 6 rockers 7 and 8 should be placed in the closed position Rocker 6 is ignored by the system when rocker 7 is closed Rockers 7 and 8 are mutually exclusive Either 2 stop bits may be used or parity may be enabled If parity is enabled rocker 7 open then only e stop bit will be used rocker 8 will be ignored by the system 6300A p 8 10 A member of the ANSALDO Group SERVICE MANUAL 6300A 5800 Corporate Orive Pittsburgn PA 15237 APPENDIX A PARTS LIST DEVELOPMENT SYSTEM GENISYS NON VITAL LOGIC EMULATOR MICROLOK PLUS VITAL NON VITAL CONTROL PACKAGE NON VITAL SECTION Up to and including Executive Software Revision 11 Application Logic Software Version 3 0 October 1991 A 10 91 2645 1 IDO312F 0313F ANSALDO COPYRIGHT 1991 UNION SWITCH amp SIGNAL INC Trasporti PRINTED IN USA DEVELOPMENT SYSTEM G D S EQUIPMENT Item Description US amp S Part No EPROM Programmer l Data I O Corp Model 212 J703105 0003 Cable EPROM Programmer to PC 25 Pin N451458 7201 EPROM Eraser Spectronics PE 14T J703105 0005 Diskette w Software G D S Hard and Floppy Disk N451232 0101 Versions 5 1 4 Diskette w Software G D S Hard and Floppy Disk N451232 0112 Versions 3 1 2 Blank Diskette 5 1 4 J703105 0004 Blank Diskette 3 1 2 J703105 0
13. Common Command bit in the mode byte When accessed via the FC command a response is given as is normally the case with controls Description Comments FI Common Control command 00 FF station number 0 all stations 00 01 control byte nbr 0 1 00 FF common control byte Repeat control byte number control byte 00 FP low byte of CRC 16 00 FF high byte of CRC 16 F 6 terminator 7 2 3 Slave to Master Data Transmission NOTE If the Slave unit does not properly decode the Master unit message the Slave will not respond 7 2 3 1 Acknowledge Master Response The Acknowledge Master Response is sent as response to messages when no other messages are pending Byte 1 l 1 Description Comments P1 Acknowledge master response 01 FF station number 0 not used P6 terminator 7 2 3 2 Indication Data Response The Indication Data Response is used to send indication data to the Master unit Byte H pw pa jn yo Description Comments F2 Indication data response 01 FF station number 0 not used 00 FF indication byte number 00 FF indication byte Repeat byte number and data as required 00 FF low byte of CRC 16 00 FF high byte of CRC 16 F6 terminator 6300A p 7 9 7 2 3 3 Control Checkback Command The Control Checkback Command is used to verify controls from the Master unit if the Checkback Control mode is set The Master responds with
14. D 17 INPUT LOCAL VARS STICK 18 INTERNAL Ti 19 INTERNAL 1 0 SEC 1 0 SEC SWITCH SETTINGS Slave Baud Rate Hardware switch Master Baud Rate 1200 BPS Polfing Time Out 1000 MSEC Control Delivery Time Hardware switch Security Automatic Debug ON Symbol Table Listing ON Validity Check ON Two Queue Option ON 6300A p 4 33 MICROLOK PLUS SYMBOL TABLE Bit Symbol Table for NBR3 5 JUNE 1991 PAGE SYM 1 IDENTIFIER BIT NUMBER amp TYPE TIMER SET CLEAR LOCAL WO BOARDS r OUTPUT SLOT 3 OUT 1 1 OUTPUT OUT 2 2 OUTPUT OUT 3 3 OUTPUT SPARE 4 SPARE 5 SPARE 6 2 SPARE 7 TOTAL SPARE 8 YO OUT 4 9 OUTPUT BOARDS OUT 5 10 UNASSIGNED OUT 6 11 OUTPUT OUT 7 12 OUTPUT 1 0 SEC 1 0 SEC OUT 8 13 OUTPUT 0 0 MSEC 500 0 MSEC INPUT SLOT 5 IN A 14 INPUT IN B 15 INPUT IN C 16 INPUT IN D 17 INPUT LOCAL VARS STICK 18 INTERNAL TI 19 INTERNAL 1 0 SEC 1 0 SEC SWITCH SETTINGS Slave Baud Rate Hardware switch Master Baud Rate 1200 BPS Polling Time Out 1000 MSEC Control Delivery Time Hardware switch Security Automatic Debug ON Symbol Table Listing ON Validity Check ON Two Queue Option ON NOTE OUTPUT SLOT 3 is slot P in the MICROLOK PLUS cardfile INPUT SLOT 4 is slot Q in the MICROLOK PLUS cardfile 6300A p 4 34 1 5 4 3 Helio S reen This Note HELP CR produces the standard Simulator Help screen shown below screen shows all display and operat
15. I O Corporation Model 212 ERPCM Programmer The programmer contains a zero insertion force ZIF IC socket for the PROM US amp S recommends EPROM J715029 0409 for the compiler program 6300A p 4 55 4 3 2 Initial Configuration file G D S Versions 1 04 and Ziaher ENPROM program uses a configuration file to store information regarding tie EPROM programmer and EPROMs This program makes use of an Environment Table to determine the location of the configuration file rafer to the appropriate DOS manual for details on the Environment Table To make this determination the environment table is searched to find the entry GDSEPROM If found the value of this entry determines the name and Location of the configuration file for example The G 3 Use the SET Command to specify the location of the configuration file SET GDSEPROM C N GENISYS GDSEPROM CFG This instructs the GENPROM program that the Configuration Pile is named GDSEPROM CFG and that it resides in the directory C NGENISYS TI the entry is not found the default is GDSEPROM CFG in the current directory The first time the GENPROM program is run the configuration file is set up to specify the type of Programmer Unit Model 21A 201 or 212 and type of EPROM Once this file is complete it does not nave to reentered NOTE Refer to section 4 8 6 if running the following pro cedure with GENISYS Development System Versions 1 01 through 1 03 1 The fi
16. MISCELLANEOUS PROGRAM DESIGN NOTES GENISYS AND MICROLCK PLUS 5 1 LOGIC AND TIMING OVERFLOWS Tf the application program causes the system to attemot to place too many elements on loaic or timer queues a system overflow will occur This will NOT be recognized by the executive software as a fault The excess elements will not be placed in a queue and the expected event will not hapoen There will be no indication that the logic equation or timing delav was not processed When there is no logic timing or I O to process the executive software will systematically execute all the Loaic equations through an idle loop Tf the idle loop executes an equation and discovers that a bit value is in error the correct value will be assigned to the bit In this way loaic equations and timing delays that were not performed as a rasult of logic or timer queue overflows may be executed at a later time Depending on the size of an application and system loading this time will vary 5 2 TIMING ELEMENTS 5 2 1 Introduction Any output or internal bit in an application program can have a timing delav The delay emulates slow pick up and slow drop away relays Individual timing delays range from 10 milliseconds to 25 minutes Sach bit can have a set delay slow pick a clear delay slow drop or both This time is the delay between when the logic equation is executed and when the value of the bit is changed 5 2 2 General Processing After a logic equation
17. Screen Relays clr relay 1 OUT 1 4 6 4 13 Trace Command The Trace command performs the same function as the Execute command however the actual boolean logic statements are displayed in the scroll area as they ar2 executed The following example repeats the operation of the Execute command in the previous section however three logic equations ara executed rather than one With the Trace command this is done by entering TR 3 CR 6300A p e 4 47 Trace three logic executions 8it Number Name Value Status Bit Number Name Value Status 1 Our cle Trigger List 8 System Time 00 00 00 000 Timer List 3 Command gt tr 3 Program N8R3 Screen Relays clear relay 1 OUT 1 LINE 23 ASSIGN IN B IN A TO OUT 2 CR to execute equation Note that a three logic equations were executed with this command Trigger list down to 8 b this particular equation which ran through the scroll uses the standard GENISYS shorthand notation for XOR a and c the prompt that notes this logic equation can be executed by entering a carriage returne By using the No Display NO CR command the Display Relays list will disappear from the screen allowing a larger number of traced logic equations to be viewed at the same time 4 6 4 14 Run Command The Run Command RU _ CR executes logic equations and increments system time Like the Increment command this command is entered with a time r2presenting how long t
18. XOR IN 3 TO OUT 2 24 ASSIGN IN A OR IN B TO OUT J 25 ASSIGN NOT IN A TO OUT 4 26 ASSIGN IN C OR STICK AND NOT IN D TO STICK 27 ASSIGN STICX TO OUT 6 28 ASSIGN NOT TI TO TI 29 ASSIGN Ti TO OUT 7 gt 30 ASSIGN NOT Tl TO OUT 8 In the Print command output these statements would appear as follows Logic equations for Program NBR3 Line 22 ASSIGN IN B IN A TO OUT 1 Line 23 ASSIGN IN B IN A TO OUT 2 Line 24 ASSIGN IN B IN A TO OUT 3 Line 25 ASSIGN A IN A TO OUT 4 Line 26 ASSIGN IN D STICK IN C Line 27 ASSIGN STICK TO OUT 6 Line 28 ASSIGN T1 TO TI Line 29 ASSIGN TI TO OUT 7 Line 30 ASSIGN ATI TO OUT 8 6300A p TO STICK 4 52 of displayed assign statements will differ slightly zar tr 4 5 4 18 Reset and Quit Commands The Reset RES CR command may te used to raset the simulator With this command a All bits are reset clear or invalid b Trigger and timer lists are reset c System time returned to 00 00 00 000 d All equations are queued on the trigger list This is the same procedure used when the simulator is initialized with the program name The Quit QU CR command terminates the simulation and exits the simulator 4 6 4 19 Color CRT Command NOTE The color CRT commands are available with Simulator Version 3 0 and higher In previous versions the Simulator was designed to be run on a monochrome video display I
19. a N S Trigger List 0 System Time 00 00 00 100 Timer List 3 Command gt RU 100 Program N8R3 Screen Relays set relay 11 set relay 19 increment time Run System No Increment Specified Bit Number Name Value Status Bit Number Name Value 1 OUTA cir 2 OUT2 che 3 OUT3 cir 9 OUT 4 set 10 OUT S 11 OUT 6 set 12 OUT 7 cle 5Q0 set 13 OUT 38 set 14 INA cir 15 IN B che 16 IN C cir 17 IN D cir 18 STICK set 19 T1 set 500 cir Trigger List 0 System Time 00 00 00 500 Timer List 2 Command RU Program NBR3 Screen Relays increment time 400 msec 6300A p 4 49 4 6 4 15 Value Command The Value command VA _ CR may be used to display the value af any desired relays For example if a Run command has been carried out with the Display IO screen the Value command can be used to check back on a relay that already changed state In the example below VA 18 19 CR or VA STICK TI CR would show the states of the internal relays that are not displayed on the screen Value of relays 18 and 19 1 1 2 2 3 3 a a 3 s 6 6 7 7 8 8 Listing for GENISYS Program Equivalent Listing for MICROLOK PLUS Program ee ee ee ee ed Trigger List 0 System Time 00 00 01 350 Timer List 2 Command gt VA 18 19 Program NBR3 Screen VO Boards relay 18 STICK relay 19 TI 4 65 4 16 Read Command The Read REA CR command may be used to read commands from a file rather than the k
20. also serviced This queue handles those time delays specified in seconds within the range of 1 to 25 seconds The last timer queue is based upon a 6 second time frame This queue is scheduled once every 60 times that a 100 millisecond queue is serviced The queue handles all time delays in excess of 25 seconds up to the maximum delay of 25 minutes Each timer queue has an internal timing accuracy that is one half the base time These are as follows Timer Queue Rance Accuracy 10 millisecond 5 milliseconds 100 millisecond 50 milliseconds 6 second 3 seconds 5 2 4 Skew Time The internal timing accuracy of each timer queue is the same with all GENISYS and MICROLOK PLUS non vital systems However the executive software is also subject to a 45 millisecond skew time The skew time is related to system loading and varies within a given unit over time dependina on the present loading conditions In smaller systems there is little or no skew time In a larger and more complex system there may be a skew durina high load times High load times occur primarily when serial data is processed A hiqh baud rate or a large number of serial data bits contributes most heavily to a system skew factor The system skew time added to internal timer queue accuracies dives these worst case system timing accuracies Timer Queue Range Accuracy 10 millisecond S0 milliseconds 100 millisecond 95 milliseconds 6 second queue 3 45 seconds
21. be used as part of an expression in an ASSIGN statement to condition logic or may be listed in an output statement Since they have a predetermined value they may not appear in an input statement or be the object of an ASSIGN statement Initially these relays are clear dropped When the first valid message is received from a Slave unit the associated relay in the Master is SET picked The relay will remain SET until the Master detects two consecutive errors in transmission At this time the relay is cleared dropped and will remain in this state until communications are resumed with that Slave 6300A on 4 22 At each Slave unit one internal communication relay is automatically defined as MASTER ON This relay is automatically SET and CLEARED by the Run Time system to indicate the status of communications from the Master unit It may be used as part of an expression in an ASSIGN statement to condition logic or may be listed in an output statement Since it has a pre defined value it may not appear in an input statement or be the object of an ASSIGN statement The MASTER ON internal relay is SET and CLEARED differently from the SLAVE ON n relays MASTER ON is initially CLEAR dropped When the Slave unit receives the first valid message addressed to its station number the bit is set The Slave unit then continues to look for the text header followed by a trailer followed by text header etc If more than five seconds elapse
22. dDrogram is converted into a form that can be entered or burned into the EPROM chips 6300A n 2 1 C voot9s cez sanbia LE WE4S4S SASINZI oOtseg MASTER PORT a TO NON VITAL aor vo P SERIAL 1 0 DIRECT INTERFACE SLAVE UNITS POWER RS A23 SUPPLY RS 423 50 FT MAX RS 232 SV TIL 5 FT MAX SLAVE PORT TO OR MASTER SLAVE NON VITAL MASTER sym CONTROL INDICA rake OFFICE COMP 4 RELAY RELAY LOCAL PANEL ETC COILS CONTACTS RELAY orta M MASTER PORT RELAY Orio OUT IN PWR CONT SWA CONT SLAVE PORT oul ity OPTICAL POWER SOURCE 9 5 TO 35 VDC OR 120 VAC ewr tiem SUPRLY f CHTAL conv ecu SERIAL I O MODEM INTERFACE Pca SLAVE GENISYS MASTER 9 Mm FOR CABLE LENGTH BIR Pce OVER 50 FT POWER EIA RS 423 AS 232C CARDENE BUS mun ATIONS RELAY oPtO COMPATIBLE ktiAY OFTQ PWR CONI out IN e SV TIL USRS PWR con oul i DCS 600 MODEM LOCAL TOTAL LOCAL VO PER UNIT M MASTER PORT vo ey ee S S SLAVE PORT e 256 RELAY OUTPUT AND OR OPTICAL INPUT RELAY OUTPUT PCBS 256 RELAY OUTPUT ONLY OPTICAL INPUT PCBS e 256 OPTICAL INPUT ONLY SERIAL 1 0 SYSTEM CONFIGURATIONS DESIGN MAX a 255 SLAWES PRACTICAL LIMIT 45 TU 50 SLAVES e 16PERPCB 16 PER PCO e NAS1441 3601 NG51441 5002 MASTER EXTERNAL STROBE 5 TO 32 voc OUTPUT INPUTS N4S4441 4701 e N451441 7202 INTERNAL STROBE 5 T
23. for simulator PROM file name GCD ouput for PROM programmer Program PROMs GENPROM Pragram PROMS using the file name GCD GENISYS Simulator GENSIM Simulate the execution of a GENISYS program GENISYS PROM Size Estimate GENSIZE For Documentation GENSIZE help Estimate the size of a GENISYS program NOTE HELP FILE ALSO APPLIES TO MICROLOK PLUS NON VITAL SECTION 4 6 G D S SIMULATOR 4 6 1 General The GENISYS Simulator allows testing of a completed GENISYS or MICROLOK PLUS non vital program prior to actual loading into the system hardware Commands are provided in the simulator to mimic operating aspects of the designed system This includes setting and clearing internal and external relays executing logic equations and advancing system time Logic statements and the system clock can be stepped individually or simultaneously at any desired increment Commands are also available to display a inputs and outputs according to their actual arrangement in the system cardfile b names bit numbers and status of individual relays c logic statements as they are executed With the simulator the source program is compiled in the same manner as the program that will be loaded into the system hardware with the exception of the debug switch refer to section 4 6 2 The EPROM code file with extension GCD is the standard input to the simulator The identifier symbol file with extension GID supplies relay names without thi
24. in this area as the program is executed This section shows a maximum of four lines at one time To scroll information from the top of the screen enter NO CR This is the command for No Display The status lines will remain on the screen 6300A p 4 30 4 6 4 Simulator Operation 4 6 4 1 When the performs a b c d 4 6 4 2 General simulator is executed and the EPROM tables are entered the simulator the necessary housekeeping functions Initialize all bits either CLEAR OR INVALID Reset system time Initialize all queues and lists Queue all equations on the Trigger List Sample Program Simulator commands are described in subsequent sections using a sample program shown on page 4 32 Each of the available commands see Help screen section 4 6 4 3 is exercised with this program in a typical order of execution and not in order shown on the Help screen This is not a required order with practice the user will find it desirable to call up a variety of commands at any point in the simulation NOTES Note the MICROLOK PLUS LOCAL I O assignments at the bottom of the sample program This shows the 2 board limit placed on the MICROLOK PLUS non vital section Compare this with the GENISYS sample program which covers four total I O boards Otherwise the com plete MICROLOK PLUS sample program is identical to the GENISYS program except for the left hand line numbering Certain aspects of the
25. is executed each bit assianed the result of the equation is evaluated to see if its value will change because of the result of the logic equation If a bit gets a new value the system checks whether there is a timer delay on that bit before executing the change of state TF there is a delay information is placed on a timer queue along with the length of the delay When the delay expires a new value is assigned to the bik The change of state does not take effect until the time delav has expirad If a change in system status occurs that causes the bit to retain its original value before the delay expires the time delay is cancelled and the bit never changes state 5 2 3 Parameters Time delavs are specified in milliseconds seconds or minutes Timing accuracy depends on the units selected The Executive softwar2 has three internal timing queues for different time ranges The timing of a GENISYS or MICROLOK PLUS system is based on a 10 millisecond processor interrupt Every 10 milliseconds the timer chip on the vrocessor board demerates an interrupt The interrupt routine then schedules the timer queue handler 6300A p 5 1 Shorter time delays are handled at this level every 10 milliseconds These time delays ara defined in milliseconds and ara within the ranae of IQ to 2500 milliseconds The next level of timer accuracy is the 100 millisecond timer queue very lOth time the 10 millisecond queue is scheduled a 100 millisecond queue is
26. missing 6300A p 8 1 8 2 SEMANTIC ERROR MESSAGES Following is a list of semantic error messages that may appear while developing the GENISYS or MICROLOK PLUS non vital program on the compiler l More than n ID s in ID list ID lists have various limits corresponding to the limits imposed by the hardware For example an INPUT WORD or OUTPUT WORD statement in the LOCAL I O section may only contain 16 relay names for GENISYS and two relay names for MICROLOK PLUS due to the physical limit on each of the input or output boards Above n specifies the limit that was exceeded 2 Set or clear delay more than 25 minutes The pick up or drop delay was specified as greater than 25 minutes If longer times are desired assign one time delayed relay to another to obtain the desired net effect 3 Multiple defined relay relay name A user defined relay name was specified in more than one I O statement or VAR statement for internal pits Any bit that appears in two or more definitions is illegal 4 ID relay name Multiple defined set clear delay The same relay was specified in two TIMER statements Each relay may have only one 1 timing specification 5 ID relay name Input Bit assigned as Timer Bit Input bits get their values externally and hence cannot have user specified pick up or drop delays 6 Invalid switch s The user has specified a switch incorrectly 7 LOCAL I O section already defined The user
27. not been defined a semantic error will be detected Refer to sections 8 1 and 8 2 for a complete Listing af compiler error messages As the source program is processed it is converted to a special purpose code that in turn is processed by the Assembler section of the compiler The assembler converts the output of the code generator to a format that can he processed by the EPROM Programmer The compiler is accessed by using the batch file GENISYS name Typing in this term invokes the batch file This file can perform several functions depending on how it is invoked GENISYS name If name GEN appears as a file in the current directory it is compiled Otherwise a file does not exist message is displayed GENISYS HELP This displays the G D S help file This file is shown at the top of the next pace The batch file performs several operations l1 Determines if the requested file exists displays error message and stops if this file does not exist 2 Deletes the previous EPROM code GCD file 3 Calls the code generator 4 Calls the assembler if no errors were detected The batch file is recommended for compiling a GENISYS or MICROLOK PLUS non vital program 6300A p 4 27 GENISYS Heip File Version 3 00 GENISYS Compiler GENISYS name For Help GENISYS heip Run the GENISYS compiler using the files Source file name GEN input Listing file name GLS output source listing Symbol file name GiD output
28. progranm 2 Open the small access panel on the front of the Model 21A and set the three left hand rotary switches to 5 0 and C respectively Do nat readjust the three right hand switches Note These will be the permanent positions of these switches for all future operations of the orogrammer They do not have to be raset each time power is turned on 3 Turn on the Model 2IA and check that the word PASS appears on tne ADDRESS portion of the digital display This indicates the programmer has passed its own start up diagnostics 6300A D 4 62 10 11 Type GENPROM or genprom and a carriage return CR to enter the ZPROM programmer routine This will generate a cover screen that remains hroughout the program This screen shows the version of the EPROM programmer The file name of the source program should be entered after the prompt Enter the name of the PROM file followed by a CR When the file name is entered the program will indicate how many blank EPROMS are needed to carry the entire program Type in any key except X as indicated by the prompt at the bottom of the screen To place a blank EPROM in the programmer make certain the pin latching lever is in the up position and insert the EPROM with the notch away from the lever Next execute the instruction Enter SELECT C SET on the EPROM Programmer which appears at the bottom of the screen The screen will then indicate which EPROM if mor
29. range FO to FE hex 2 Character FF is illegal since this is commonly created on noisy lines 3 Data in the range 00 to EF hex is sent as is Data in the range FO to FP hex is sent as the escape character FO hex followed by the low nibble of the data For example a data byte F3 would be sent as FO followed by 03 The receiver of a message will always OR the byte following an FO with it and treat the result as one data byte This refers to all non control character information station address byte number byte data and CRC 16 4 Data security will be in the form of CRC 16 The generator polynomial will be the standard CRC 16 polynomial X 16 X 15 X 2 l 5 Communication status bits MASTER ON and SLAVE ON xx will be provided which are accessible through the high level lanquage These bits will be set upon receipt of a valid message addressed to that unit If no message is received within the selectable time out period the bits will be modified 6 Control and indication byte addresses 223 255 EO SFF are reserved for status type information currently defined in these bytes These include the following Control byte address EO sent in FC or F9 message bit 0 Data base complete 4 Future 0 data base not complete 5 Future l Use check back controls 6 Future 2 Use secure poll only 7 Future Allow common command 3 Indication byte address E0 sent in F2 message bit 0 Data b
30. responds to this acknowledgement with an F1 or F2 message d If the Slave unit sends another F2 message the Master unit sends another acknowledgement until the Slave unit responds with an r1 message Master Unit Message Slave Unit Response FC or FB F2 All data being sent or SFC or FD F2 Changed data being sent The Master unit then sends an FA message in response to the Slave unit s F2 message Master Unit Message Slave Unit Response FA F2 Changed data being sent or F1 No data changes to report As long as the Slave unit sends new information in F2 messages to the Master unit the Master unit will continue to acknowledge the received data When the Slave unit terminates the communication with an Fl message the Master can continue the polling cycle with the next Slave unit 7 1 3 Good and Bad Messages A good message conforms to the format described in the previous section and passes the CRC check when applicable A bad message may include an invalid header control character an incorrect station address a bad CRC checksum where applicable or an invalid or missing termination character A Slave unit only responds to a good message that includes its correct station address a A message start is regarded as a valid control character If a valid control character is noted but only a partial message is received the message receiving process is aborted b Any current or pending transmit messag
31. s list print all logic equations read commands from file end simulation reset system aff bits invalid this screen Trigger List 0 0 Command Help System Time 00 00 00 000 Timer List 0 0 Program NBR3 Screen Help The first four display commands require a combination of DI a space and the minimum letters of the command For example DI TR CR would display all equations currently on the trigger list The notations after the Help screen commands are defined as follows J Optional argument Tf this is not specified the simulator will resort to the associated default For example if the Disolay Relays command is entered without a list of requested relays all relays on the relay display list will be shown list List of bit names numbers The list is used to svecify a bit or series of bits refer also to section 2 6 3 Required argument If not specifie it will be prompted file File name Default extensions will be added 4 6 4 4 Display IO Command The Display I O DI IO CR command shows the physical arrangement of the source program inputs and outputs on the cardfile I O boards In the example at the top of the following page Out 1 etc represents the relav output PCB s and their word numbers in the cardfile Like the actual cardfile installation relay outputs are located to the left of the optical inouts Note the difference between the GENISYS and MICROLOK PLUS displays The 1 16 column on
32. section 2 8 8 6300A p 4 63 When EPROM programming has Seen successfully completed the message PROM 3 has been programmed will appear and the check sum for that ZPROM will be displayed The check sum may be used to distinguish the ZPROMs 13 If more than one EPROM is needed to hold the tables the anv key message will appear When such a key is pressed the system will go back to sken 8 Otherwise the terminal will display several messages indicating that the programmer should be reset and turned off 14 When the programmer has been turned off pressing any key will exit GENPROM 4 3 8 Error Messages G D S Version 1 00 Computer error messages available with GENISYS Development System Version 1 00 include all of those under later Versions plus the following message Message Cause Remedy The Program was compiled As indicated Recompile the program with the DEBUG switch ON without the debug switch it will not execute on the switch off default or GENISYS hardware The pro reset the switch ta D gram must be recompiled without the DEBUG option 4 8 9 EPROM Programmer Driver Color Disolay The Version 3 00 GENISYS EPROM Programmer Driver program supports color video displays In previous versions the program would only produce displays witn black and white characters The new version makes use of colors and alsa supports the Data I O Corp Model 212 EPROM programmer 6300A p 4 64 SECTION 7
33. the left represents the output and input bit numbers respectively on the relay and opto boards Make certain not to confuse these with the 0 15 output and input bit numbering on the PCBs themselves Bit l on this screen is equivalent to bit 0 on the PCB The line dividing bits 1 38 and 9 16 represents the two 8 bit bytes transferred consecutively off the PCB At the start of a simulation question marks will appear at the specific bits of each board if the validate value compiler switch is 34v If the switch is set to v all bits equal 0 At this time all active inputs are invalid neither 0 or 1 and are represented by this symbol Any SPARE relays are indicated as clear clr but will have no effect on the program As the simulation is run the invalid relays will change to cir clear or set set 4 6 4 5 Display Triggers Command The Display Triggers DI TR CR command gives a listing of all equations on the trigger list by specifying the line number generated by the compiler The screen from the sample NBR3 program is show at the middle of the following page The tabulation at the bottom of the next page may be used to determine which list an equation will be added to when a bit changes It is also possible for an equation to be queued on both lists In the NBR3 example line 26 appears on both lists 26 ASSIGN IN C OR STICK AND NOT IN D TO STICK In this equation both IN C and IN D start out with a valu
34. time will be required for the bit shown 28 Program name name contains illegal characters Refer to sections 4 2 1 3 and 4 2 4 1 for allowed characters 8 3 CODE SYSTEM PRE PROGRAMMED EPROMS US amp S provides a series of EPROMs which contain a program for configuring the GENISYS or MICROLOK PLUS non vital section as a CTC system field code unit These programs are used to interface the local I O with the SLAVE port In these programs the serial input is mapped to the local outputs and the local inputs are mapped to the serial outputs The following list shows the default values used for compilation Function Default Value Slave Baud Rate Hardware Switch Master Baud Rate 1200 BPS Control Delivery Time Hardware Switch Security Automatic Validity Check On Two Queue Option Off Setting on the Controller PCB switch Default for this switch in G D S Version 1 00 is called off The Code System EPROMs are tabulated in Table 8 1 The Controls and Indications listings represent the maximum number of output and input PCBs respectively that may be installed in the GENISYS or MICROLOK PLUS cardfile for these functions EPROMs may be selected for applications which do not use the precise control indication configurations listed in the table provided 6300A p 8 4 the precise number of output boards does not exceed the listed maximum in the table For example a GENISYS system requiring five relay outout and five opt
35. user to employ the various parts of the G D S Extension File Contents GEN Source program for the application logic GLS Listing file with errors pro uced by the compiler GID Identifiers file produced by compiler and used by simulator GCD EPROM code file produced by the compiler assembler and used by the simulator and EPROM programmer SEQ Equations generated by the simulator GSI Simulator initialization file GIM Temporary file used during compilation 6300A p 4 26 4 5 G D S COMPILER NOTE Different revisions of the GENISYS Development System compiler may yield different check sums and code sizes dowever the program should behave in the same manner The compiler checks and converts the application program into a code that can be processed by the Executive software contained in a separate Controller PCB EPROM The compiler performs two functions including code generation and assembling The code generation section checks the source program for any errors using a two phase process Syntax Analysis and Semantic Analysis Syntax analysis looks for improper grammar in the program During this analysis two types of errors may be detected including token errors more than 12 characters illegal character etc and statement syntax errors no BEGIN Reserved Word missing semicolon etc Semantic analysis checks for meaningful statements For example ASSIGN A AND B TO C If C is defined as an input bit or B has
36. 0 OUTY CYCLE CLOSED PARITY DISABLED TRANSMITTED ON ieee PARITY ENABLED C iiD SAD SERIAL LINE C uos sou x x o jo wswa out ALL ee 1 STOP MIT SPACES TRANSMITTED OPEN 2 STOP BITS 4109 WAICHOOG KI x o s wswe OUT ALL MARKS TRANSMITTED C store onma jumping 16 280 X x o O WISWA N ALL MARKS TRANSMITTED on No x x 0j1 WISWA IN ALL SPACES TRANSMITTED on abe ant sbt ant anvi r man sw ooo ouo GOO Uoo LOO ZB SET aut SET ALL KEY ON DELAY KEY OFF DELA a JUMPERS a J JUMPERS a a TO A B POS 10 BC pos ROCKERS ROCKERS Z fon ns a23 eee en s 4 jan PUSH DOWN ROCKER TO OPEN SIDE FOR 3 PUSH DOWN ROCKER TO NUMBERED SIDE FOR 0 1 2 3 4 DELAV 15 6 7 8 DELAY e a ee aac 466 aet agit ase ram ofaja o ZERO 010 010 sen ooo BOU GOU Oou oou olilojol al o i e a ey Ve en 1 o o nj ipi o o i a gt renee ofojijo 16 fojojijo tja 1707170 20 1707040 6 a COMMUNICATIONS MODE elililol asf i 1i o HES 01001 n ofojoji sw NOTE ilo o 1 j i ofo t kai ofijoji aol joprpoji re J DIP SWITCHES vivijoji 44 sisjoji 3 e ojojili asi ojojijs a WA GhTE De sw tjoji 1 sz vlojijn 6 jaa olifij i se lolififs 3 lan REVERSE OF SWITCHES sifai l fatadals siz swa4 SWS SW6 AND SW7 ON w MICROLOK CODE SYSTEM PCB 1 gun TIME ci gt CARMA FEST ANG AVIISE O 10 mSEC S16 A130 SWA 1 30 mSEC 3 2 70 mSEC w p Canna MOUN Biase aye yun S 1 SEC RATE gt
37. 0 00 00 000 Timer List 2 Command gt SE 12 Program NBR3 Screen Relays put relay 12 on timer queue A Clear command removes OUT 7 from its timer queue and also eliminates the invalid state Relay OUT 7 eared Value Bit Number Name Status Bit Number Name Value 12 OUT 7 Trigger List 10 System Time 00 00 00 000 Timer List 1 Command gt CL 12 Program N8R3 Screen Relays put relay 12 on timer queue A relay with a set time of 0 such as OUT 8 would be set and clearad from the invalid state in a corresponding manner 5300A p 4 44 4 6 4 10 Increment Command The Increment command INC CR allows the system time 9 be advanced without executing any logic equations The value entered after this command must be a factor of 10 milliseconds If a time is specified that is not a factor of 10 milliseconds it will be converted to the next smaller valid interval To demonstrate this command all timer relays in NBR3 have been queued to their respective set and clear times Note the following is the RELAY display Bit Number Name Value Status Bit Number Name Value Status 12 OUT 7 cir 1000 set 13 OUT 8 set 500 cir 19 T1 set 1000 cir HS V Time is then incremented 10 milliseconds INC 10 CR Note below that the queued times in the Status column have all decreased by 10 millisecands and tnat the System Time has advanced by that amount System t
38. 008 Model 201 replaced Model 21A in 1987 Model 212 replaced Model 201 in 1991 6300A D A 1
39. 0A p 4 46 4 6 4 12 Execute Command The Zxecute command EX CR executes logic equations without advancing the system time A number may be entered with this command scecifyving the number of trigger list equations to be executed If a number is not specified then all equations on the trigger list will be executed In the example below program NBR3 is returned to the point with all timer queues on and at their full values EX l CR is entered This command tells the simulator to exercise only the first equation on the Triager List Note that relay OUT 7 has been changed from invalid to clear and the Trigger List total is reduced by 1 This indicates that nine Triager List equations remain to be executed When the trigger List total reaches 0 no more logic equations ara queved for execution Some GENISYS and MICROLOK PLUS non vital programs may be written such that certain individual logic executions do not result in a change of output Thus some Execute commands may appear to have no effect when in fact they are changing internal bits displayed in the scroll area Execute one logic equation Value Status Bit Number Name Value Status Bit Number Name 1 OUT cir 2 OUT2 3 OUTJ 9 OUTA 10 OUT 11 OUT 6 12 OUT 7 1000 set 13 OUT 8 cir 500 cir 14 IN A set 15 IN B cir 16 IN C cir 17 IN D cir 18 STICK set Trigger List 9 System Time 00 00 00 000 Timer List 0 Command gt EX 1 Program NBR3
40. 3 M OUT 4 M OUT S BEGIN ASSIGN IN A AND iN B TO M OUT 1 ASSIGN IN A XOR IN B TO M OUT 2 ASSIGN IN A OR IN B TO M OUT 3 ASSIGN NOT IN A TO M OUT 4 ASSIGN IN C TO M OUT S5 END 6300A p 4 11 This sample shows Master Slave serial communications for the Slave unit PROGRAM NBRAS INTERFACE LOCAL OUTPUT WORD OUT 1 OUT 2 OUT 3 SLAVE ADDRESS 2 INPUT M IN 1 M IN 2 M IN 3 M IN 4 M IN S BEGIN ASSIGN M IN 1 OR M IN S TO OUT 1 ASSIGN M IN 4 XOR NOT M IN 2 TO OUT 2 ASSIGN M IN 3 AND M IN 4 TO OUT 3 END SO The above programs allow communication between a Master and one Slave unit The Slave unit responds to address 2 The Master unit inputs three bits of information performs logic functions and sends five new output bits M OUT I through M OUT 5 to the Slave unit The Slave receives these bits M IN 1 through M IN 5 performs additional logic and outputs the new computed values to the relay output PCB in the cardfile For a complete explanation of Master Slave communications refer to section 4 2 4 2 part c 4 2 4 Detailed Statement Descriptions 4 2 4 1 PROGRAM Statement The first statement in the program must be a PROGRAM statement This statement gives a name to the program for documentation purposes FORMAT PROGRAM id The identifier entered here will be printed in the listing at the top of the Symbol table It is written with user defined symbol refer to section 4 2 1 3 Comments
41. A member of ine ANSALDO Group SERVICE MANUAL 6300A 9800 Corporate Drive Pittsburgh PA 15237 Non Vital Application Logic Programming GENISYS NON VITAL LOGIC EMULATOR MICROLOK PLUS VITAL NON VITAL CONTROL PACKAGE NON VITAL SECTION Up to and including Executive Software Revision 11 Application Logic Software Version 3 0 October 1991 1D0312F 0313F ANSALDO T 2 COPYRIGHT 1991 UNION SWITCH amp SIGNAL INC respon SENTED IN USA Revised and new nages of this manual ara listed by page number and date Page No Date Daae No Date II ITI IV CONTENTS Section I INTRODUCTION TO MANUAL 1 1 PURPOSE AND ARRANGEMENT 1 2 FAMILY OF MANUALS GENERAL INFORMATION GENISYS INTRODUCTION Overall System Application and Executive Software COMPONENTS Cardfile Printed Circuit Boards 1 Controller 2 Relay Output PCBs 3 Optical Input PCBs 4 Power Supply Converter PCBs NON VITAL SECTION SPECIFICATIONS Programming Related s Ne NNN NNN NNN PIN UNN MN NNN pk mm ry NN NN Nn kr e e e GENERAL INFORMATION MICROLOK PLUS INTRODUCTION Overall System Non Vital Section Application and Executive Software COMPONENTS Cardfile PCBs 1 Controller N451441 5602 2 Relay Output PCBs 3 Optical Input PCBs SPECIFICATIONS Programming Related Wwww Www Ww wow e n a e WONONNNDHN NY He m on WAN m e e o a e gt NN NM HN eH PROGRAMMING PROCEDURE
42. Development System compiler permits up to 16 I O PCBs to be defined However the MICROLOK PLUS non vital section only allows two I O PCBs When writing the application program for the MICROLOK PLUS non vital section make certain not to specify more than two I O boards No error message will be generated if more than two boards are specified The actual system logic is defined with ASSIGN statements These statements define the interconnecting logic of the inputs and outputs The order of the ASSIGN statements will usually have no effect on the logic refer also ta section 4 2 5 2 In this example OUT 1 is the logical AND of the twa inputs IN A and IN B Similarly OUT 2 is the EXCLUSIVE CR and OUT 3 is the OR of the two inputs OUT 4 is the logical NOT of IN A and QUT 5 directly follows IN C 4 2 3 2 Internal Relays and Stick Logic The following program shows the handling of internal relays and stick logic PROGRAM NBR2 INTERFACE LOCAL OUTPUT WORD OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 INPUT WORD IN A IN B IN C IN D VAR i STICK BEGIN ASSIGN IN A AND IN B TO OUT 1 ASSIGN IN A XOR IN B TO OUT 2 ASSIGN IN A OR IN B TO QUT 3 ASSIGN NOT IN A TO QUT 4 ASSIGN IN C TO OUT 5 ASSIGN IN C OR STICK AND NOT IN D TO STICK ASSIGN STICK TO OUT 6 END a Pe This program is similar to the program NBRl in section 4 2 3 1 however OUT 6 is added as the 6th output on the relay output board Als
43. ECIAL CHARACTERS SPECIAL CHARACTERS Upper Letters A 2 Colon Backslash Lower Letters a z Semicolon Percent Sign Numerals 0 9 Comma j At Sign a Period Equal Sign Plus Sign Dollar Sign Open Parens Asterisk Unde rscore Close Parens Tilda A 6300A p 4 1 4 2 1 2 Reserved Words A Reserved Word has a predefined meaning to the compiler The 25 Reserved Words are listed in Table 4 2 Table 4 2 GENISYS Reserved Words PROGRAM OUTPUT SET AND MSEC INTERFACE INPUT CLEAR OR SEC LOCAL WORD BEGIN NOT MIN MASTER VAR END XOR ADDRESS SLAVE TIMER ASSIGN TO SPARE 4 2 1 3 User Defined Symbols User defined symbols are used to create relay names in the source program These symbols must contain characters from the first part of Table 4 1 and cannot consist of all numbers A maximum of 12 characters may be used ta create symbol names Examples of legal symbols in G D S Versions 1 01 and higher include relay 123 DOG INPUT RELAY 1TK INSTRKSIN Illegal examples of the above symbols in G D S Versions 1 01 and hiaher include INPUT RELAY 1 Exceeds 12 character maximum RELAY 1 Contains an illegal character 123 all numbers Examples of legal symbols in G D S Version 1 00 include relay 123 INSTRKSIN 1 TK DOG TNPUT RELAY Illegal examples of the above symbols in G D S Version 1 00 include 1TX Begins with number INPUT RELAY 1 Exceeds 12 character maximum RELAY 1 Con
44. FE message If the following message to this station is not a valid FE message for this Comments Control Checkback command station number 0 not used control byte number control byte Repeat control byte number and data as required low byte of CRC 16 high byte of CRC 16 terminator Format Affected by Modes Slave to Master Non Secure no Secure no Secure yes 1 End of Text Master to Slave station the control is lost Byte Description 1 F3 1 01 FF 1 00 FF 1 00 FF 1 00 FF 1 00 FF 1 P6 7 2 4 Control Code Summary Code Message P1 Acknowledge Master F2 Indication Data F3 Control Checkback F6 End of Text character F7 future F8 future FI Common Controls FA Ack Indication amp Poll PB Poll FC Controls FD Recall FE Execute Secure yes 2 Secure no Either yes 3 Secure no Secure no Secure yes 4 1 If Checkback Controls are not enabled in the E0 byte Control Checkback is not a valid protocol character 2 If Common Controls are not enabled in the E0 byte Common Control is not av alid protocol character 3 Default is secure poll non secure poll can be selected in the E0 byte 4 If Checkback Controls are not enabled in the E0 byte execute is not a val id protocol character 6300A np 7 10 SECTION VIII SUPPLEMENTAL DATA 8 1 TOKEN AND PARSING ERROR WARNING MESSAGES The following tabluation lists al
45. GRAMMING PROCEDURES GENISYS AND MICROLOK PLUS 4 1 GENERAL In the non vital application program various bits input output internal etc and logic procedures are defined in a text data file on a computer Input and output statements are described by location They can be local I Q connected directly to that unit or remote I O on either of two serial lines Master Slave Timing values indicate the set pick up and or clear drop away delays of the bits Boolean statements are used to describe the system logic The completed written program is referred to as the source program It is processed by the compiler and converted into data tables In turn these tables ara burned into one or several ZPROMs the EPROM s are then installed into the Controller PCB Sections 4 3 to 4 8 describe haw these basic programming operations are handled with the US amp S GENISYS Development System G D S 4 2 PROGRAMMING LANGUAGE 4 2 1 Terms 4 2 1 1 Character Set The Character Set consists of the full ASCII character set as defined for the user s computer These are listed in Table 4 1 Only certain characters may be used to make up user defined symbols refer to section 4 2 1 3 Although all letters are acceptable all lower case letters a z are converted ta upper case A Z by the system For example Stick is read the same as STICK Lower case is only used for readability Table 4 1 Character Set FOR USER DEFINED SYMBOLS SP
46. IGN STICK TO OUT 6 34 ASSIGN NOT T1 TO T1 35 ASSIGN T1 TO OUT 7 36 ASSIGN NOT T1 TO OUT 8 37 END Errors Detected 0 LOCAL I O SECTION OF MICROLOK PLUS NON VITAL PROGRAM 12 LOCAL MAN 13 OUTPUT WORD OUT 1 OUT 2 OUT 3 TOTAL 14 SF ARE SPARE SPARE SPARE SPARE WO 15 OUT 4 OUT S OUT 6 OUT 7 OUT 8 BOARDS 16 INPUT WORD INA IN B IN C IN D 6300A p 4 32 NOTES The sample bit symbol table below applies to GENISYS Development System Versions 1 01 and higher In Version 1 00 the BIT TYPE column is placed in a separate column at the right and the TIMER column is called GENISYS TIME DELAY SYMBOL TABLE The Version 1 00 table as a whole covers 132 spaces in Versions t 01 and higher the table covers 80 spaces In the SWITCH SETTINGS listing at the bottom Version 1 00 does not include Polling Time Out and the Security switch is ON or OFF rather than ON or AUTOMATIC 4 TOTAL YO BOARDS Bit Symbol Table for NBR3 S JUNE 1991 PAGE SYM 1 IDENTIFIER BIT NUMBER amp TYPE TIMER SET CLEAR LOCAL YO BOARDS OUTPUT SLOT 3 OUT 1 1 OUTPUT OUT 2 2 OUTPUT OUT 3 3 OUTPUT SPARE 4 SPARE 5 SPARE 6 SPARE 7 SPARE 8 OUT 4 9 OUTPUT OUT 5 10 UNASSIGNED OUT 6 11 OUTPUT OUTPUT SLOT 4 OUT 7 12 OUTPUT 1 0 SEC 1 0 SEC OUT 8 13 OUTPUT 0 0 MSEC 500 0 MSEC INPUT SLOT 5 IN A 14 INPUT IN B 15 INPUT INPUT SLOT 6 IN C 16 INPUT IN
47. ITY TERMINATION STATION CHARACTER ADDRESS DATA BYTE S CHECKSUM CHARACTER HEADER CRC TRAILER l Control Character a Each message must start with a control or header character which denotes the type of message b Different control characters are defined for the Master and Slave ports 2 Station Address a If the transmitting system is a Master unit this address refers to the location of the receiving Slave unit b When the Slave unit receives the transmission the station address is decoded If the message applies to that station the message is processed and acted upon Messages addressed to other Slave units are ignored Ce If the transmitting system is Slave unit this address refers to the address of that Slave unit d The Master unit expects a message from the Slave unit it initially addressed including the address of that Slave unit 3 Data Byte a Data is always sent as two 8 bit bytes including a byte number followed by a data byte b Each byte is identified with a byte number which starts at zero For example a message with 24 data bits would be packaged as follows 6300A 0 7 1 Byte No Data Bits 0 1 8 l 9 16 2 17 24 Cc With this format it is not necessary to send the entire data base to transmit selected bits 4 Security Checksum a This is the automatic 2 byte cyclical redundancy check CRC checksum b When this checksum is included all other message bytes exc
48. J10 select TTL or EIA RS 423 RS 232C compatible communications for the Master and Slave ports of the GENISYS or MICROLOK PLUS non vital unit If the unit is a stand alone type the jumper locations are ignored by the software Each jumper position is set up A B C with the plug installed either A B or B C Table 8 6 lists jumper positions for the different communications modes on the Master and Slave ports NOTE For applications where high noise immunity is re quired RS 423 is recommended Table 8 6 Master and Slave Communications Mode Select TTL or RS 423 Port Communications Mode Jumper No Jumper Position Master RS 423 J6 J10 A B Slave RS 423 JI J5 A B Master TTL J6 J10 B C Slave TTL JI J5 B C 6300A p 8 9 8 4 7 Serial Port Test SW7 Rockers 1 through 4 of DIP switch SW7 are used to test controller PCB serial ports and local modem To set up the controller For normal operation set rockers l and 2 to 0 8 4 8 Serial Port Data Byte Pormat SW7 On GENISYS and MICROLOK PLUS systems with Revision 7 and higher of the Executive EPROM IC29 SW7 rockers 6 7 and 8 select the data byte format for the serial ports On previous revisions these were set at l start bit 8 data bits 1 stop bit and no parity Table 8 7 lists switch settings for the available format options Table 8 7 Serial Data Byte Format SW7 SW7 Rocker Position Format Selected 8 Closed 1 Stop Bit default Open 2 Stop Bits 7
49. MENTN When the compiler encounters the percent sign characters are ignored until it reaches a backslash Switches are the exception refer to section 4 2 2 3 Note that comments may begin anywhere including the middle of a statement and span any number of lines in a source program However they cannot begin in the middle of a word ASSI GN is illegal Hence another example of a correct comment is a follows THIS IS AN EXAMPLE OF A LEGAL GENISYS OR MICROLOK PLUS COMMENT N The closing backslash N must be inserted otherwise the compiler ignoras all other characters until a backslash is found 6300A p 4 3 Compiler Version 3 0 and Sigher Note the in the oroaram example on page 4 3C that an 2xclamation point appears before each comment This character only appears if the comment is the first non blank item on the line or soans multiple lines and is automatically inserted after the line number ta help distinguish the comment from other parts of the program Thus if the closing backslash is accidentally omitted from the comment the exclamation point will appear after every line number to indicate that the compiler regards all subsequent lines as comments rather than other tvpes of program statements 4 2 2 3 Compiler Switches Compiler switches are used in the source program to select various options such as baud rates Refer to Section 8 4 for hardware switch ootions Compiler switches begin with a percent s
50. MER T1 SET 1 5EC CLEAR 1 5EC BEGIN ASSIGN IN A AND IN B TO OUTA ASSIGN IN A XOR IN B TO OUT 2 ASSIGN IN A OR IN B TO OUT 3 ASSIGN NOT IN A TO OUT 4 ASSIGN IN C TO OUT S ASSIGN IN C OR STICK AND NOT IN D TO STICK ASSIGN STICK TO OUT 6 ASSIGN NOT T1 TO T1 ASSIGN T1 TO OUT 7 ASSIGN NOT T1 TO QUT 8 END 6300A p 4 10 gt Note the ASSIGN statement ASSIGN NOT Tl TO Tl The statement will take the current value of bit TI initially 0 perform the logical NOT operation and attempt to assign a value of 1 to TI However because Tl is defined to have a SET or pick up delay of 1 second the actual value will remain at 0 for one second When time has elapsed and the bit becomes a l the assignment statement will execute again causing the value of O to be assigned to T1 with a one second delay as specified by the CLEAR parameter of the timer statement Thus the internal bit T1 will toggle at a one second rate Note the final two assignment statements added to this program ASSIGN TI TO OUT 7 ASSIGN NOT Tl TO OUT 8 Outputs OUT 7 and OUT 8 will alternately flash at a one second rate OUT 7 on when TI is 1 and OUT 8 on when TI is 0O 4 2 3 4 Master Slave Communications The following program shows the handling of Master Slave serial communications for the Master unit PROGRAM NB8R4M INTERFACE LOCAL INPUT WORD IN A IN B IN C MASTER ADORESS 2 OUTPUT M OUT 1 M OUT 2 M OUT
51. NISYS may be interfaced directly with a controlling computer and with digital carrier system modems A Master Slave protocol is used for communications between a computer and GENISYS unit s or between two or more units Configurations may include 1 stand alone units with no serial communications links and 2 Master Slave systems with serial communications Links Master Slave systems may in turn incorporate one or more Master GENISYS units These configurations are shown in Figure 2 1 Communications options include EIA RS 423 RS 232C compatible or TTL compatible Modems are required when more than one Slave unit is connected to a Master unit or when direct interface communications limits ara exceeded Each GENISYS unit may control a total of 256 inputs and outputs in any configuration including those where inputs or outputs are absent Up ta 255 Slave units may be controlled by a Master unit however the typical Practical limit is in range of 40 to 50 units 2 1 2 Application and Executive Software The GENISYS system incorporates independent Application and Executive software These are contained in separate EPROM chips on the Controller board The Application software or logic is developed for the specific installation either by US amp S or the customer The source program is written and compiled on a computer using a language that enables the system logic to be expressed in terms familiar to the railroad engineer The finished
52. NON VITAL SECTION PCBS YO I SLOT PART NO DESCRIPTION N45 1441 3601 CONTROL OEVIIVERYT N45 1443 7101 CONSTANT DELIVERY N45 1441 4701 CONTROL amp DELIVERY 1895 3441 7202 OPTO ANPUT HIGH THRESHOLD N45 1441 5802 OFTO INPUT WIDE RANGEL INSTALLATION ONE RELAY OUTPUT SLOT P ONE OPTO INPUT SLOT P ONE RELAY OUTPUT AND ONE OPTO INPUI RELAY IN SLOT P OPTO IN SLOT Q oo 44 WAY PCB VITAL CoDt VITAL EDGE CONNECTORS MASTER SYSTEM SLAVE vitat YO AND PORT Pout PURI ALL NON ViITAL PCBS JI PIN D 25 Pite D Irin D TAT MOTHERBOARD COVER OFF p gt VCOR OUTPUT T RIINALG 3 3 NON VITAL SECTION SPECIFICATIONS Programming Related Total Bits Local I O Boards Local I O Bits Master to Slave Communications Slave to Master Communications Serial Addresses Serial Baud Rates Active Timing Elements Logic Equations Triggered 1450 bits maximum can te divided between local 1 0 serial I O and internal 2 maximum per cardfile 16 maximum per local I O board 255 Slave units maximum communication from Master unit l Master unit maximum communication from Slave unit 1 to 255 inclusive 50 75 100 134 150 300 600 1200 1800 2400 3600 4800 7200 9600 100 maximum active at any one time in application logic more timers may be defined 1000 maximum one queue option 500 maximum each queue two queue option refer to page 4 21 6300A p 3 7 8 SECTION IV PRO
53. NVALID 7 and higher VALID VALUE CF 0 1 AND INVALID 7 and nigher INVALID When the Validation Option is used on in executive software Revisions 7 and higher there are two identities that allow partial processing of equations with invalid parameters k l1 OR X l Q AND X 0 These identities ara not evaluated in Revisions 0 through 6 Any invalid Parameter in Revisions 0 through 6 causes an invalid result With Revision 7 and higher the value of X in the above identities is irrelevant even if it is invalid In Revisions 7 and higher the identities may be applied to process logic with invalid parameters This is particularly useful where there is both a remote control and a local control for the same function ASSIGN RC AND RI OR LC AND LI TO OUTPUT With Executive software Revisions 0 through 6 this function will not work in Local Control LC unless the Remots Control RC function is valid This could cause problems in cases of code line failure The function will work with Revisions 7 and higher 6300A p 5 4 5 4 LOGIC QUEUING AND ZXECUTION 5 4 1 Comparison of Hardware and Software Relay Logic There ar2 limits to which the GENISYS or MICROLOK PLUS non vital systems can emulate actions and reactions of a non vital relay svstem Relay svstems which are based on electrical hardware connections orocesses multiple logic functions in parallel GENISYS and MICROLOK PLUS which are based on software and a microprocessor
54. O 32 VDC CENTRALIZED ourPur INPUT ASSURED CONTROL e N4S1441 7101 VDC THRESHOLD CONSTANT STATE AT POWER OFF DISTRIBUTED CONTROL G S may be programmed by using the GENISYS Development System G D S y system enables the user to design and test his own proaram and then lead into the system hardwar2 The G D S consists of a personal computer an ROM Programmer and the GENISYS software which is contained on a single iskette The G D S can only be employed with the programming equipment supplied by USSS ENTS This it EP d The Executive software is common to all GENISYS systems This software performs input internal and output logic operations defined in the application logic This manual edition covers all software versions up to and including Executive Software Version ll and Application Compiler Software Version 3 0 2 2 COMPONENTS 2 2 1 Cardfile see page v and Figure 2 2 The GENISYS Non Vital Logic Emulator is housed in a standard 19 inch rack mount cardfile The cardfile always contains a power supply converter PCB in the far lefthand slot a controller PCB in the second slot and between zero and 16 relay output and or optical input PCBs in the remaining slots When relay output PCBs are present they are always placed as a group to the left of any optical input PCBs Empty slots are allowed between relay output and or optical input boards provided these slots are defined as spares in the application progr
55. PERIPHERAL SLOT A Ati VITAL APPLICATIONS SLOT B ALL VITAL APPLICATIONS SLOI C WHEN REQ D BY APPLICATION SLOT D ALL VITAL APPLICATIONS TS OE NT te VITAL SECTION PCBS WO ISLOT PART NO DESCRIPTION N45 1441 6601 STANDAKD RELAY DRIVER N451441 8501 VOLT LIMI RELAY DRIVER N45 1441 870 BI POLAK KELAY DRIVER N451441 6702 OC LAMP DRIVER 18 W LAMP N45 1441 6703 DC LAMP DRIVER 25 W LAMP N45 1441 7301 DC LAMP DRIVER 36 W LAMP N45 1441 8802 STANOARD INPUT 12 v NOM N45 1441 8603 STANOAKO INPUT 24 V NOM t N INSTALLATION SEE EXAMPLES BELOW aa CPU vav nv QUIPUT OUTPUT LED LED ABCDEFGH IJ FRONT NON VITAL SECTION sJ TA n gt VITAL TETN e esv SV zav OUTPUT OUTPUT INPUT Leo LED LED POWER SUPPLY DRAWER VITAL VO INSTALLATION EXAMPLES EXAMPLE 4 OUTPUT PCBS EXAMPLE 6 OUTPUT PCBS ONLY oe ee i n MN Shes sls K kow kou i AS AE RN an Se n ee OuTPUT PCB IN SLOT So NO EMPTY SLOTS RETIAIEEN AF AF NO EMPTY SLOTS AP TISIF Ey nerap EXAMPLE 5 INPUT PCBS ONLY J VITAL YO kk ees INPUT PCB IN SLOT E 3 INPUT PCBS 1ST INPUT Oe cee IN SLOT VITAL vo 1ST OUTPUT PCB IN SLOT E Ra NO FMPTY SI ANTE K d MN OPQ 24 V INPUT TERMINALS NON VITAL SECTION PCB LOGIC SLOT PART NO DESCRIPTION l wasteanson CONTROLLER INSTALLATION SLOT Q ALL NON VITAL APPLICATIONS
56. PU iWWWNNNNNNN iii Paqe 4 62 4 62 4 64 4 64 LI L S ee QUV Uuw WI mori men nannan a Ub uur oF ouuu j a 1 pou i NM ewe eRe TOETATI I Li moOUVU UOOJGOGOOQX 14 OABAN pi pop Q yuuyuyyuy Wal wa Wa ypy yyy IN Li H Q Section CONTENTS Cont d VII SUPPLEMENTAL DATA GENISYS AND MICROLOK PLUS 8 1 e e gt e gt om Ae oosoocoov ovs on PrP hb bh Ph hh PhP amp WY O xANRUVRUwWN m APPENDIX A Figura TOKEN AND PARSING ERROR WARNING MESSAGES SEMANTIC ERROR MESSAGES CODE SYSTEM PRE PROGRAMMED EPROMS CONTROLLER PCB HARDWARE PROGRAMMING Slave Port Baud Rate SW1 Control Delivery Time SW2 Carrier Mode SW3 Slave Station Address SW5 Key On and Key Off Delays SW6 Communications Mode Select Jumpers Serial Port Test SW7 Serial Port Data Byte Format SW7 PARTS LIST DEVELOPMENT SYSTEM EQUIPMENT ILLUSTRATIONS y w Q D bass DA en ke Pen HOw emorynuuh ror L Q i 5 a te GENISYS Cardfile Cover removed SECTION I INTRODUCTION TO MANUAL 1 1 PURPOSE This manual provides instructions for programming the non vital application software of both the GENISYS Non Vital Logic Emulator NVLE and the non vital section of the MICROLOK PLUS Vital Non Vital Control Package These systems share identical non vital logic and interface circuit boards as well as executive and application software PCB hardware and sof
57. R statement will in effect set or clear instantaneously Timer delays can be individually specified in the program The available units include I MIN minutes 2 SEC seconds 3 MSEC milliseconds Generally speaking the smaller units have greater timing accuracy Unit Accuracy MIN 3 sec SEC 50 msec MSEC 5 msec gt The shortest non zero delay allowed is 10 milliseconds and the longest is 25 minutes The actual ranges that the compiler uses are as follows Unit Range MIN 0 1 min to 25 min SEC 0 1 sec to 25 sec MSEC 10 msec to 2500 msec NOTE Although the lowest timing ranges for minutes and seconds are given as 0 1 min and O I sec res pectively the actual set and clear times specified must be an integer value For example 0 1 sec would be specified as 100 msec and 0 1 min as 6 sec Values greater than the above may be used The compiler will automatically convert out of range values to the smallest acceptable range For example if 3000 MSEC is entered the compiler will convert this to 3 SEC with an accuracy of 50 milliseconds However small values with larger units will not be converted to the smallest units even if this is possible For example if 2 SEC is entered the compiler will read this as 2 seconds and not convert this to 2000 MSEC The standard format for entering timer values is as follows TIMER id list SET integer unit CLEAR integer unit i
58. ROM has been programmed and the check sum for that EPROM If the installed EPROM is not the last in the set tne computer will repeat the Press any key message and the program will go back to step 7 6300A p 4 58 2 TF the installed SPROM is the last in the set the computer will disslayv several messages indicating that the orcoarammer should be reset and turned off pu ka 13 When the programmer is turned off pressing any key on the computer will exit the GENPROM program 4 8 4 Error Messaces G D S Versions 1 01 and Higher NOTE Refer to section 4 8 8 for computer error massages in G D S Version 1 00 The tabulation on the following pages lists computer error messages that may appear in the course of the GENPROM procedure In most cases the user should repeat the original procedure as the first means of removing the error 6300A p 4 59 to The PROM file is incor rect Invalid format Recompile the GENISYS program and try again The PROM file is incor cect unexpected end of file Unable to set PROM type The PROM is not properly inserted in the PROM Message PROM proarammer failed accept a command socket The PROM is not blank Possibly a damaged PROM Srror code from PROM Pro grammer rho Error code from tne PROM Programmer a Unable to set base Unable to read the PROM ia of the PROM Cause EPROM programmer not
59. S GENISYS AND MICROLOK PLUS 4 1 GENERAL 4 2 PROGRAMMING LANGUAGE 4 2 1 Terms 4 2 1 1 Character Set 4 2 1 2 Reserved Words 4 2 1 3 User Defined Symbols 4 2 1 4 Delimiters 4 2 2 Formats 4 2 2 1 General Arrangement of Statements 4 2 2 2 Non Program Comments 4 2 2 3 Compiler Switches 4 2 3 Program Examples 4 2 3 1 Local Input Output 4 2 3 2 Internal Relays and Stick Logic 4 2 3 3 Timing Relays 4 2 3 4 Master Slave Communications 4 2 4 Detailed Statement Descriptions 4 2 4 1 PROGRAM Statement 4 2 4 2 INTERFACE Section g W a a Hop oad i ror pu rea tt LA AJK W RON VU VU Wwe r n ti EIRIN AP D NNNN ly wu LJ laj Gad to ab lay G ta Ww lap l m fe RPh f fal mim m m i N a Q 7 ee a ae ee ee ee ee HH ODOM WH WON UH Pee on i ra pb LA H po NN 4 13 Section eo ea Aunnnnnbkr A amp h o o Cry e a gt 8 2 o a e gt a e a gt o e e o ahh n PRP k PH hPL RL HE hphiiwNtDNN kr Nr n a E e a a S a E a r a r r r a a a a a a a L Ah O nh k k A Ah Ah oOoGOoOoxxN RSJ NSANRANAKANKANRMNKAN KANKRARKANKAMANMNAKANANMANGMNMAABUPSTUWONENENNM KN fNTH RHNIiI e Ne a e w Aum d 6 oe gt a Wh kr Ne Ee p pw A jwet pt je ood n oa gt DOU MON A WON ou WOON KHUN A UNEO CONTENTS Cont d VAR Section TIMER Section Main Proaram Body ASSIGN Statement Run Time System Des
60. SESI MOU RESET 6 a 2 SEC 06150 46 2 400 Yo 4 SEC 1 300 5 4 000 22600 6 9 600 J 1 200 Table 8 2 Hardware Defined Slave Port Baud Rates SW1 SW1 Setting Baud Rate SW1 Setting Baud Rate Q 150 4 2400 l 300 5 4800 2 600 6 9600 3 1200 8 4 2 Control Delivery Time SW2 Rotary switch SW2 sets the Control Delivery Time for the local relay output PCBs This rate may also be selected in the application program refer to section 4 2 2 3 If no Control Delivery Time is specified in the program the delay will be determined by the setting of SW2 If the Control Delivery Time is selected in the program compiler switch 01 to 0F this rate will override the SWl setting Table 8 3 lists the available Slave Port Control Delivery Times on SW2 NOTE US amp S recommends against using the 10 msec setting Some relays may fail to react to this short of a control pulse Table 8 3 Hardware Defined Control Delivery Times SW2 Control Del Control Del SW2 Setting Delay SW2 Setting Delay 4 250 msec 5 1 sec 6 2 sec 7 4 sec 8 4 3 Carrier Mode SW3 Toggle switch SW3 is set according to the application When placed in the CARRIER position the constant carrier mode is invoked and the RTS line on the serial port remains high throughout the data transmission Constant carrier can only be used on the Master port the Slave port always uses the key delays When this switch is placed in the OPERATE position the Key On a
61. Simulator s operation such as scrolling lines cannot be depicted in this text To best understand the operation of the Simulator the user should enter the sample program in his system and run the various commands as they ar presented The card slot locations of the inputs and outputs are shown in the symbol tables on page 4 33 GENISYS and 4 34 MICROLOK PLUS NOTE As indicated in the MICROLOK PLUS diagram board slot numbers are based on the GENISYS cardfile slot numbering Make certain to note the difference in the MICROLOK PLUS non vital section slot numbering 6300A p 4 31 GENISYS PROGRAM GENISYS Source Listing Version 3 00 S JUN 1991 Page 1 Copyright 1984 Revised 1991 Union Switch 3 Signal Inc 1 2 THIS IS AN EXAMPLE 3 OF A BASIC NON VITAL 4 PROGRAM 5 6 7 YSD DEBUG ON 8 SQ TWO QUEUE OPTION 9 10 PROGRAM NBR3 11 INTERFACE 12 LOCAL a 13 OUTPUT WORD OUT 1 OUT 2 OUT 3 4 14 SPARE SPARE SPARE SPARE SPARE TOTAL 15 OUT 4 OUT S OUT 6 VO 16 OUTPUT WORD OUT 7 OUT 8 BOARDS 17 INPUT WORD IN A IN B 18 INPUT WORD IN C IN D 19 20 VAR STICK T1 21 22 TIMER 23 T1 SET 1 SEC CLEAR 1 SEC 24 OUT 7 SET 1 SEC CLEAR 1 SEC 25 OUT 8 SET 0 SEC CLEAR 500 MSEC 26 27 BEGIN 28 ASSIGN IN A AND IN B TO OUT 1 29 ASSIGN IN A XOR IN 8 TO OUT 2 30 ASSIGN IN A OR IN B TO OUT 3 31 ASSIGN NOT IN A TO OUT 4 32 ASSIGN IN C OR STICK AND NOT IN D TO STICK 33 ASS
62. Systems Installation of MICROLOK Development System M D S Hard and Dual Floppy Disks 6300A D 1 2 SECTION II GENERAL INFORMATICN GENISYS 2 1 INTRODUCTION 2 1 1 Overall System See Figure 2 1 The GENISYS Non Vital Logic Emulator NVLE is a general purpose micro computer and I O interfacing unit that can perform the Functions of various non vital relay logic and digital logic systems according to a custom designed software program This program uses a Boolean high level lanquage taking inputs performing logic and timing functions on those inputs and produces outputs The program is conceptually similar to a system of interconnected relays Typical applications include processing of central office controls and local indications at a CTC system field station and Processing of local indications for a local wayside control panel The basic hardware elements of GENISYS include a single microprocessor based controller printed circuit board PCB a power supply converter PCB and a configuration of input and output PCBs determined by application Three optional output PCBs are equipped with 16 single pole relay outputs for various relay and or control panel lamp driving applications Two optional input PCBs are equipped vith 16 optical isolator ICs for interfacing of contact generated input signals Power supply converter options are tailored for dc voltages in the range of 9 5 to 35 Vdc and standard 120 Vac commercial power GE
63. ack is occupied the system resets If the Validation Option is turned on the local input showing occupancy is read before the serial output can be sent to the office The indication always shows the correct status If the Validation Option is turned off the serial output may occur before the local input As a result the information sent ta the office may temporarily show a clear track 5 3 2 Parameters When validation is enabled all local input bits ara considered invalid until the input board has been successfully accessed and the data read AIl serial input bits are considered invalid until they are received over the serial port All other bits are initialized with a validation value of 0 If a logic equation can be resolved to a valid value bits assigned to the statement are also marked as valid and assigned the result of the equation Tf a final result is not valid the bits assigned to the statement retain their current value and validation status When output processors local or serial format output states for delivery na invalid outputs may be delivered Since the outputs are not delivered on a bit by bit basis one invalid output may prevent other outouts from beina delivered whether or not they are valid On the local output boards all l bits are delivered simultaneously If any one of these bits is invalid the entire board is prevented from delivering outputs On the serial oorts anv one invalid bit will prohibit an enti
64. am For example in Pigure 2 2 empty slots 7 and 8 spare allow future expansion of outputs without having to reconfigure the inputs 6300A D 2 3 EXAMPLE 5 RELAY OUTPUT PCBS ONLY EXAMPLE 7 OPTICAL INPUT PCBS ONLY SLOT NO Se 1 2 18 SLOT NO te 1 2 1ST RELAY OUTPUT PCB 1ST OPTICAL INPUT PCB EXAMPLE 4 RELAY OUTPUT AND GENISYS PLUG IN CIRCUIT BOARDS 4 OPTICAL INPUT PCBS SLOT NO DESCRIPTION PART NO 1 POWER SUPPLY 9 5 35 VDC Na 1441 7601 POWER SUPPLY 120 VAC N451441 4601 2 CONTROLLER N45 1441 5602 3 18 RELAY OUTPUT OPTIONS CONTROL DELIVERY Na51441 3601 CONSTANT DELIVERY N451441 7101 SLOT NO a 1 2 3 9 i CONTROL AND DELIVERY N451441 4701 z 1ST RELAY E B OPTICAL INPUT OPTIONS OUTPUT PCS 1ST OPTICAL INPUT PCB OPTO INPUT HIGH THRES N451441 7202 OPTO INPUT WIDE RANGE Na51441 5802 THESE PCBS ALWAYS IN THESE SLOTS SLOTS 7 AND 8 EMPTY MUST BE DEFINED AS SPARES IN APPLICATION PROGRAM Figure 2 2 GENISYS Cardfile PCB Arrangements 6300A p 2 4 ZeSdEZ PCB3S 2 2 2 1 Controller N451441 5602 The Controller PCB performs all logical decisions and calculations for the GENISYS system and serves as the remote communications interface for any external devices Primary functions include management of local I O via card file interface boards and remote I O via serial data line according to the custom design program and execution of internal
65. ase complete 4 Future 0 need controls 5 Puture 1 Use check back controls 6 Future 2 Use secure poll only 7 Puture 3 Allow common controal command The Message formats supported include the folowing l Header byte station address terminator three byte format used for messages which do not require security 2 Header byte station address message CRC 16 terminator variable length format for messages with checksum NOTE On the following pages the character preceding a number denotes a hexidecimal base 16 number 7 2 2 Master to Slave Data Transmission 7 2 2 1 Poll Command A Poll Command is sent to allow a Slave unit to respond The Slave responds with Fl F2 Non secure format Bytes Description 1 FB l 01 FF 1 r6 Secure Format Byte Description FB 01 FF 00 FF 00 FF F6 f n j pan pen 7 2 2 2 Acknowledge Data Command Comments Poll command station number 0 not used terminator Comments Poll command station number 0 not used low byte of CRC 16 high byte of CRC 16 terminator The Acknowledge Data Command is sent to acknowledge data from a Slave unit The Slave responds with Fl F2 Byte Description FA 01 FF 00 SFF 00 FF F6 f go g gn pu 6300A p 7 7 Comments Acknowledge Data command station number 0 not used low byte of CRC 16 high byte of CRC 16 terminator 7 2 2 3 Control Com
66. au rates are listed in Table 4 5 on page 4 7 6300A p 4 4 NOTE The following compiler switch ASPXxxXx applies to GENISYS Development System Versions 1 02 and higher and Executive PROM IC29 Revision 7 and higher This switch is not available with earlier versions e Pxxxx Specify the Master No Response Time Out where x 100 throuah 9999 This value is set only in the source program It specifies the number of milliseconds the Master will wait for the Slave to begin responding If the Slave has not responded within this time the message is considered bad and the Master will continue with the polling cycle The value entered is rounded upward to the next multiple of 100 For example P735 polling time out 735 milliseconds would instruct the executive software to wait 800 milliseconds for the Slave to respond If this switch is not specified the default is 1 second e On Set the Control Delivery time where n l through Hexadecimal F This value is the duration of the Controller PCB delivery pulse to the relay output PCB s It is defined on the hardware switch or in the source program and is a single character If no 0 switch is present in the source program the Control Delivery time set on switch SW2 will be used Software values are listed in Table 4 6 on page 4 7 NOTE The following compiler switch a cv N applies to GENISYS Development System Versions 1 01 and higher In version 1 00 this switch is liste
67. ay names these commands would be entered as SE OUT 1 OUT 2 and CL OUT 3 OUT 4 QUT 6 CR Note that the changes to the relays are shown in the scroll area The example shows the last two lines in this particular scroll All relays that ara changed are scrolled on the screen 6300A p 4 40 Ser and Clear of non timer relays Bit Number Name Status Bit Number Name Vaiue Status 1 OuUT 1 set 2 OuT 2 set 3 OUTJ dir 9 OUT 4 cir 10 OUT S cr 11 OUT 6 cir clear relay 10 clear relay 11 B Timer Relays a General Comments If a bit is being set and it has a set delay greater than 0 the bit will remain in its current state and be placed on the timer list to be set this will happen only after the specified time has elapsed When a bit is placed on the timer list its set delay will be displayed under the Status column If a bit is invalid and is on the timer queue to be set and a clear command is issued the bit will be removed from the timer queue and immediately cleared If an output bit is not used in any logical equations then an explicit set or clear command for that bit will cause an error statement indicating that changing the bit will nave no effect on the system NOTE Clearing of a bit also follows from this description b Examples The example on the next page uses timer relay Tl which has set and clear times both greater than 0 First Tl initially invalid is cleared CL 19 CR or CL TI
68. ay need to be executed If so the new equations are placed breaks before makes at the end of the queue after any equations that are already queued The executive continues to execute equations one at a time until the queue is empty At this time any changed outputs will be delivered to the outout processors f The two queue option has two separate queues one for the breaks and one for the makes The executive queues equations to be executed in the same manner as the one queue option except that the breaks ao in one queue and makes in another queue Equations on the break queue are executed before equations on the make queue Any equation queued by a break is executed before equations queued by makes even if the make was queued The difference between the two options is shown in the example in Figure 5 2 R3 RA 8 N R4 R8 8 1 N n RC on 1 N a ASSIGN R1 R2 R3 TO RA RS ASSIGN Ra RB TO RB B ASSIGN R2 RB RC RS TO RC Yo L Y Figure 5 2 Queuing Option Example 6300A p 5 6 In Figure 5 2 the following occurs RI is dropped 22 R3 R4 and RS ara picked RA and RA ara picked while RC is dropved If 22 drops RC may or may not vick depending on the queuing option chosen One queue option When R2 drops both the RA and RC equations are placed on the queue to be executed RA which involves the break is queued and executed first When the RA equation is executed RA
69. between two active bits the symbol SPARE must be used to indentify the unused bit All output boards must be fully defined ahead of input boards Outputs or inputs that are unused at the end of a control or indication word need not be defined NOTE Input boards are scanned at a 50 millisecond rate Control Delivery times are selectable compiler switch So refer to section 4 2 2 3 5300A p 4 13 PROGRAM id INTERFACE LOCAL OUTPUT WORD id list GENISYS Up to 16 total VO boards id list may have up to 16 relay names MICROLOK PLUS Non Vital One or two YO INPUT WORD id list boards id list may have up to 16 names MASTER ADORESS n OUTPUT id list Avan INPUT id list ve en PALES pS gan ADDRESS n correspond to associat lave uni OUTPUT id list INPUT id list SLAVE ADORESS n OUTPUT id list Each id list should correspond to its INPUT id list associated Master unit Oniy 1 Slave C Serial Communications Interfaces 1 Master Port The Master serial port see Figure 4 1 enables a given GENISYS or MICROLOK PLUS unit to communicate with another such Slave unit or units The MASTER subsection defines the I O operations for the Master unit of such a system Por each Slave unit in this system one ADDRESS OUTPUT INPUT group must be defined under the MASTER interface section of the proaram The Master unit communicates among the Slave uni
70. ble in the previous section If relay OUT 4 had been accidentally removed from this listing it could be restored with the command DI RE OUT 4 ca However OUT 4 would reappear at the end of the listing rather than in its numerical position If the simulator is exited or reset the SPARE relays will appear again on this Listing and must be removed again Spare Relays Removed Bit Number Name Value Status Bit Number Name Value Status 1 OUTA 2 OUT 2 3 OUTJ 9 OUT 4 10 OUTS 11 OUT 6 12 QUT 7 13 QUT 8 14 INA 15 INB 16 IN C 17 IN D 18 STICK 19 Ti A Trigger List 10 7 System Time 00 00 00 000 Timer List 0 ka DY WE ES EY L OO W W A A A W aa Command REM 4 8 Program NBR3 Screen Relays 4 6 4 8 Input Command The Input INP CR command is used to set or clear the input bits in the source program Sither a single number or range of numbers may be entered with this command representing the number s of the input boards In the example at the top of the following page the Display IO screen is called up and INP 1 CR is entered Then a 0 CR is entered In the scroll area the names and numbers of all relays on the first optical input board to the right of the relay boards ara listed along with the instruction for entering a logic 0 or 1 The entered 0 changes the state of the first input bit on the 1 opto board from invalid to clear clr A logic l sets that relay When all input bits
71. cription Input Output Description Logic Processing Serial Communications Pre Defined Relays Valid Bit Option Introduction Relay Models and Programming Techniques GENISYS DEVELOPMENT SYSTEM G D S GENERAL G D S AVAILABLE FILES G D S COMPILER G D S SIMULATOR General Access to Simulator General Procedure Standard Formats Simulator Operation General Sample Program Help Screen Display IO Command Display Triggers Command Display Relays Command Remove Command Input Command Relay Set and Clear Commands Increment Command Display Timers Command Execute Command Trace Command Run Command Value Command Read Command Print Command Reset and Quit Commands Color CRT Commands G D S EPROM SIZE ESTIMATES PROGRAM General Sample Execution G D S EPROM PROGRAMMER Gene ral Initial Configuration File G D S Versions 1 04 and Higher Programmer Operation G D S Versions 1 01 and Higher Error Messages G D S Versions 1 01 and Higher Communications Interrupt ii Pace 4 16 4 16 4 18 4 18 4 20 4 20 4 20 4 22 4 23 4 24 4 26 4 26 4 27 4 28 4 28 4 29 4 29 4 29 4 30 4 31 4 31 4 31 4 35 4 36 4 36 4 38 4 39 4 39 4 40 4 45 4 46 4 47 4 47 4 48 4 50 4 50 4 51 4 53 4 53 4 54 4 54 4 55 4 55 4 55 4 56 4 57 4 59 4 62 CONTENTS Cont d Section VI VII pou oo a Initial Configuration File G D S Versions 1 00 throug
72. ctions of the program PROGRAM INTERFACE LOCAL OUTPUT WORD etc are always placed in the order shown These are discussed further in section 4 2 4 The INTERFACE section defines the local inputs and outputs corresponding to the relay output and optical input boards and individual bits on those boards in the cardfile This sample program requires one LOCAL relay output board and one LOCAL optical input board The output board and input board must be installed as follows GENISYS Output board in slot 1 J3 of the cardfile and input board in Slot 2 J4 of the cardfile MICROLOK PLUS Output board in non vital slot 1 P of the cardfile and input board in non vital slot 2 Q of the cardfile Five output bits OUT 1 OUT 2 OUT 3 OOT 4 OUT 5 are defined on the output board OUT 1 is delivered on the first output bit 0 OUT 2 through OUT S are delivered through bits l through 4 respectively Three inputs are similarly defined for inputs 0 through 2 The number and order of the I O boards in the program text must match the actual hardware configuration Output board definitions must be specified before input board definitions in the program This is in accordance with the left to right order of I 0 boards in the cardfile see Figures 2 2 and 3 3 Less than 16 bits may be defined on an input or output board Unused input bits are ignored Unused output bits are always output as zero 6300A p 4 8 NOTE The GENISYS
73. d as Security On Off There is no operational difference between the two Versions e cv Security On Automatic where v or Slave unit polling from a Master port in a GENISYS or MICROLOK PLUS system can occur with or without CRC security refer to protocols in Section VII The CRC security is either send poll with CRC security or automatic on off CRC security for poll When the value is selected the Master unit will always send the secure form of the polling command If the option is selected the security is automatically included when the Master determines that the line is sufficiently noisy to warrant it The default for this option is c automatic CRC inclusion s vv Validate Value where v or This switch is used to inform the Executive software whether or not to wait for validation before an output is performed Refer to sections 4 2 5 4 and 5 3 for detailed descriptions of this switch The value v of this switch is either plus or minus Plus corresponds to option on and minus to option off The default for this switch is v validation on 6300A pD 4 5 s Dv Debug whersa v or G D S Versions 1 01 and Ziaher This switch informs the compiler that the simulator will be used to debug the program When this switch is turned on D the compiler retains in separate file relay names assigned in the application program so that these names may be used when simulat
74. d list SET integer unit CLEAR integer unit 6300A p 4 17 we vo Where id list is a list of previously defined internal or output relay bit names separated by commas integer is an integer constant in the range of 0 9999 unit is specified as one of the Reserved Words Tu MSEC for milliseconds 2 SEC for seconds 3 MIN for minutes For example TIMER T1 T2 SET S500 MSEC CLEAR 500 MSEC 1XXRR SET 250 SEC CLEAR 0 MSEC 4 2 4 5 Main Program Body The actual system logic is written in the main program body Every internal or output relay bit name defined in the INTERFACE and VAR sections should be given a value in the main program body except Spare keyword bits This is done by making the bit the object of an ASSIGN statement refer to section 4 2 4 6 If an output bit is not the object of an ASSIGN statement the program may operate properly but that bit will be ignored Serial input bits from Master or Slave may be the object of an ASSIGN statement For a complete explanation of how the actual input logic output cycle occurs in relation to input assignments refer to section 4 2 5 Run Time System Description 4 2 4 6 ASSIGN Statement The ASSIGN statement enables the various Boolean operators OR NOT etc and bit names to be combined in logic equations For example ASSIGN IN A XOR IN C AND NOT IN A OR IN B TO OUT 5 Four logical operators are available to crea
75. drops This causes the RB equation to be queued Since there is only one queue the RB equation is placed in the queue after the RC equation The RC equation is then removed and executed RB is still picked and R2 is dropped causing RC to pick Since RC has now changed state and is used in the RC equation this equation goes back on the queue after the RB equation The RB equation is removed from the queue and executed This causes RB to drop The RC equation is removed and re executed RB is now down However since RC has already picked and has a valid path through a stick circuit RC remains picked Two queue option When R2 drops both the RA and RC equations are queued ta be executed The RA equation which involves a break is placed on the break queue The RC equation which involves a make is placed on a make queue Any equation queued because of a break is done before those caused by a make Therefore the RA equation is removed and executed First When the RA equation is executed RA drops This causes the RB equation to be queued Since the RB equation is being queued because of a break in the RA relay the RB equation is placed on the break queue Since this equation is in the break queue it is removed and executed before the RC equation which is in the make queue This occurs even though the RC equation was queued prior to the RB equation When the RB equation is executed RB drops The RC equation is now removed and executed At this t
76. e of zero NOT IN D is queued on the make list and IN C is queued on the break list This equation will be executed twice once from the Break list and then from the Make list If switch 85Q N only one trigger list exists 6300A p 4 36 n Li 1 t n i 1 4 pi 1 3 l n 2 a Initial NBR3 gt i oa A dann Display 1 0 i i K i Screen for x jou GENSYS x as i Me 5 6 dr Equivalent i Program eti i k g 7 dr listing for ye bi i 8 dr MICROLOK i ia A 9 k PLUS M i w 10 tou 11 i 13 i eet n nn man menn m a aaa an Trigger List 10 System Time 00 00 00 000 Timer List 0 Command Dt TR Program N8R3 Screen VO Boards Initial NBR3 Trigger List Screen Trigger List 10 System Time 00 00 00 000 Timer List 0 Command gt Dt TR Program NBR3 Screen Triggers Trigger List Development Table Equation Bits Changing h Value To Uses Queued On Bit O 1 bit Make List Bit 0 1 bit Break List Bit 1 0 bit Break List Bit 1 0 bit Make List 6300A p 4 37 4 5 4 6 Display Relays Command The Display Relays DI RE CR command has two forms selectsd relavs and all relays for example DIS RE 1 3 9 14 17 CR adds relays 1 through 3 9 and relays 14 through 17 to the list DI RE CR shows all relays currently on the list The present state of the relay set clr 3 is show in the value column If the relay has a pick set or drop clear de
77. e than one are required to insert in the programmer the hexadecimal base address of that EPROM the program file name and several instructions The base addresses are 4000 6000 8000 A000 and c000 When any key is pressed the screen should show the following series of messages in succession 3lank check of PROM Downloading program to the PROM programmer Verifying contents of the PROM programmer Programming PROM Please Wait The program is not loaded directly into the EPROM IC when any key is pressed First the EPROM is checked to make certain it is blank and properly inserted in the programmer socket Blank check of PROM Next the program is transferred to temporary memory in the programmer Downloading program Then the programmer repeats this procedura to make certain the two match Verifying contents This is designed to detect any errors that might have been generated in the tables during the first downloading process Finally the program is loaded inta the BPROM itself a procedura that typically takes about two minutes Note during the initial EPROM downloading download check and final loading that the ADDRESS characters on the Model 21A ara cycling These present the addresses in the EPROM program as they are delivered Any physical problems in the hardware or errors in the transferred messages will be indicated by any of a variety of fault messages at this time These ar2 described in
78. ept the termination character are included in the checksum S Termination Character The message is always terminated by the termination or trailer character F6 7 1 2 Message Sequence The following discussion is based on the use of a GENISYS or MICROLOK PLUS unit as the non vital serial link Master If some other type of computer or the US amp S Programmable RCCI is being used as a Master unit it may not be possible to implement this sequence Also the discussion does not refer to systems with a check back function The check back function can onlv be used in certain types of system configurations and affects system timina Contact US amp S for information on the use of the check back function in a GENISYS or MICROLOK PLUS non vital system In a normal communication sequence the Master unit sends a message to a particular Slave unit The Slave unit decodes this message then formats and transmits a response Once the Master unit receives and decodes the message from the Slave unit the Master unit determines if another message is to be sent to that same Slave unit or continue to the next station in the polling cycle In either case the Master always formats and transmits a new message The appropriate Slave unit responds and the cycle continues The tabulation at the top of the next page shows a background polling cycle from a GENISYS or MICROLOK PLUS Master for a system with seven field stations The first two lines indicate
79. es at that Slave unit are also aborted However data changes and latched bits are not lost Only the transmission is aborted 6300A p 7 4 The receive port on the Slave unit is always enabled The Slave unit cannot olock a transmission from the Master unit except when the receive sort circuit is disabled because of an absent DCD sianal The Master unit is programmed to expect a response to all messages transmitted to the Slave unit s a Messages should not be received from the Slave units when no tranmiSsion has been made from the Master unit When the Master unit is transmitting a message its receive port circuit is disabled When the full message is transmitted the No Response Time Out timer is started This timer represents that maximum amount of time allowed between send and receive transmissions refer also to section 4 2 2 3 The No Response Time Out is stopped when the starting control character is received from the Slave unit A second time out is then started This time out is the maximum time that can exist between two received characters It is set at 300 milliseconds Each time a character is received this time out is reset until the F6 character is seen When the termination trailer character is received the message is then processed by the Master unit logic If the message is from a Slave station other than the one originally addressed wrong station address has an invalid format or does not pass t
80. eyboard It is designed to simplify the re entering of commands with long Lists of items at the beginning of a simulation or to execute a series of commands in sequence Nhen the cead command is invoked the initializing File name is requested The default extension for this file is GSI If a file extension is entered it will override this default If the command READ NBR3 cr is entered the file used is NBR3 GSI If the command is simply READ CR the file name is prompted by INIT FILE The default extension of GSI is always used by the simulator 6300A p 4 50 In the example below the editor is used to crsata file NBR3 GSI The disnlay relays and input commands are entered so that a only active relavs are displayed and 5 the four inputs on the input soard nave alternating values when the text editor is exited these commands will be available in the simulator While running the simulator enter READ NBR3 CR the commands will be read from that file and executed Set up Display Relay and Input commands in file ewww em we meme www eee ee SIART OF TEXT ann oananeceseanezannnann di re 1 3 9 17 i H inp 1 i 1 This term would not 4 a appear on display gP for MICROLOK PLUS i Only 1 input board Two special commands are valid when reading an Init file Pause and Continue To temporarily suspend the reading of commands from an Init file a Pause command may be entered into the fi
81. f PROM Downloading program to the PROM programmer Verifying contents of the PROM programmer Programming PROM Please Wait The program is not loaded directly into the EPROM IC when any key is Pressed Instead The EPROM is first checked to make certain it is blank and properly inserted in the programmer socket Slank check of PROM Next the program is transferred to temporary memory in the programmer Downloading program Then the programmer repeats this procedura to make certain the two match Verifying contents This is designed to detect any errors that might have been generated in the tables during the first downloading process Finally the program is loaded into the PROM itself a procedure that typically takes about two minutes Model 201 or 212 programmer The message COMPUTER CONTROL remains on during program downloading checking and transfer to the EPROM Also a period cycles from left to right on the LCD disolay Model 21A Programmer Address characters cycle These represent the addresses in the EPROM program as they are deliverad Any hardware problems or errors in the transferred messages will be indicated by any of a variety of fault messages at this time Messages on the computer are described in section 4 8 4 Refar to the Programmer manuals for their particular error mesaages IF the orogram requires two or more EPROMS the computer will display P
82. gnal request application illustrates a serial input bit being given a value from an ASSIGN statement The controlling Master unit which may be a full office mini computer may send a green request using a serial input bit This request may be combined with other information to produce the actual green output The green signal request is usually to be cancelled when the appropriate track circuit becomes occupied Note that logic may be written to clear the signal request input from the serial line 4 2 5 2 Logic Processing Note Refer to section 5 4 for a detailed descriotion of logic processing and queuing An ASSIGN statement is equivalent to tracing the path or paths of current flow from a battery to the assigned relay coils Therefore the logic for all of the wiring associated with that relay coil must be contained in one ASSIGN statement The order of the ASSIGN statements in the source program will usually have no effect on the output An ASSIGN statement is re computed each time one of the relay coils included in the statement changes state This involves the following chain of events The system first determines if the coil has a timing delay If so the specified time is run until the relay is to be set or cleared Assignments for non timer coils ar2 carried out immediately and all ASSIGN statements in 6300A p 4 20 which this coil is referenced are re computed This process continues until the system reaches a stable state Duri
83. h 1 03 Programmer Operation G D S Version 1 00 Error Messages G D S Version 1 00 EPROM Programmer Driver Color Display gt ha ha oo o eo won ISCELLANEOUS PROGRAM DESIGN NOTES GENISYS AND MICROLOK PLUS LOGIC AND TIMING OVERFLOWS TIMING ELEMENTS e 2 1 Introduction 2 2 General Processing 2 3 Parameters 22 4 Skew Time VALIDATION OPTION 3 1 Introduction 3 2 Parameters 3 3 Recommendations LOGIC QUEUING AND EXECUTION Comparison of Hardware and Software Relay Logic Breaks Before Makes Rule Queuing Options ANNANN ANNANN nw Li D a a U A W WU NNNN NH wn m MISCELLANEOUS APPLICATION INFORMATION GENISYS AND MICROLOK PLUS 6 1 LOCAL I O Using Slave Units as I O Processors Determining the Control Delivery Time 1 Introduction 2 Selection Considerations SERIAL COMMUNICATIONS TIMING ERIAL COMMUNICATIONS PROTOCOL GENISYS AND MICROLOK PLOS INTRODUCTION 1 Message Format 2 Message Sequence 3 Good and Bad Messages DETAILED DESCRIPTION General Specifications Master to Slave Data Transmission 1 Poll Command 2 Acknowledge Data Command 3 Control Command 4 5 6 R ol 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Recall Indications Command Execute Controls Command Common Control Mode Slave to Master Data Transmission 1 Acknowledge Master Response 2 Indication Data Response 3 Control Checkback Command Control Code Summary SS a SS St SS NS eS SSN L
84. has attempted to define two LOCAL I O sections 8 MASTER I O section already defined The user has attempted to define two MASTER sections 9 ID relay name INVALID ASSIGNMENT TO A PHYSICAL INPUT BIT The relay name specified in the ASSIGN statement is an input bit on the bit on the LOCAL I O It is illegal to assign these bits values with ASSIGN statements 6300A p 8 2 yon va ll 12 13 l4 16 18 19 20 21 SLAVE I O section already defined The user has attempted to define a second SLAVE section More than one address in SLAVE I O definition The user has attempted to define multiple address specifications in the Slave section The GENISYS unit can be programmed to respond to only one Slave address ID relay name should be Relay name The user has used the identifier defined as the program name where a relay name should have been used Master Station address already defined The user has already used this station address in a previous definition Illeqal Master Station Address The user has defined a slave unit with an illegal address to be in communication with this unit s MASTER port Each SLAVE must have an address specified in the range 1 255 Tllegal SLAVE station address The user has defined an invalid address for the Slave port of this unit The address of the SLAVE port must have an address specified in the range 0 255 If zero is specified the value of the hardware switch
85. have been defined for opta board 1 the command stops This command also accepts a range INP l 2 would cause the simulator to input values for board 1 followed by board 42 6300A p 4 39 Once the input bits have seen defined they cannot be returned to the invalid state without exiting or resetting the proaram Input l Board 1 cleared t t 1 l 1 i L LI 3 t 8 1 de LI dr 2 2 2 Input 1 cleared 3 13 2 i in GENISYS a dr 14 de program 3 dr Equivalent listing RART AS dr 5 S for MICROLOK ou a i cir LI der 8 dr PLNS i8 dr i 19 2 i 110 i a Trigger List 10 System Time 00 00 00 000 Timer List 0 Command gt iNP 1 Program N8R3 Screen YO Boards relay 14 IN A input value 0 1 or CR to exit 0 relay 15 IN A input value 0 1 or CR to exit 4 6 4 9 Relay Set and Clear Commands A Non Timer Relays The Set SE CR and Clear CL CR commands are used to set or clear all internal and external celays in the source program Relays can be set or clearsd by bit number or name These commands operate differently devending on the characteristics of the specific bit If a bit without a set clear delay is set cleared the command will produce an immediate change In the example at the top of the next page non timer relays l and 2 ars set using SE 1 2 CR while non timer relays 3 and 9 through ll are cleared with CL 3 9 11 CR Using the rel
86. he CRC check it is considered an invalid message by the Master unit logic If an invalid message is received or either of the receive data time outs elapses the Master unit logic ignores any partially received data and goes to a special bad receive handler The first time Slave unit fails to respond properly to a Master unit transmission a The Master unit will retransmit the same message once This is done to allow for intermittent line noise that may have interfered with the first transmission If this second attempt also fails the intended Slave unit is designated as off line in the Master unit logic The SLAVE ON xx bit is cleared in the application logic and the Master continues the polling cycle with the next Slave unit When a Slave unit is designated as off line future polling cycles will only consist of one tranmission from the Master unit no retranmission occurs until that Slave unit responds to the initial transmission Note This function is only available with Executive software IC29 Revisions 3 and higher 6300A p 7 5 7 2 DETAILED DESCRIPTION 7 2 1 General Specifications The default GENISYS and MICROLOK PLUS non vital data transmissions consist of 10 bits 1 start bit 8 data bits and l stop bit no parity This can be changed on Controller PCB switch SW7 refer to section 8 4 8 The general format is as follows l The transmission is a modified binary with unique control characters in the
87. he entire system 4 8 6 Initial Configuration File G D S Versions 1 00 through 1 03 l The first screen in the routine asks for selection of either the Model 21A 201 or 212 programmer Press the l key on the terminal for the model 21A the 2 key for the 201 or the 3 key for the 212 2 The next screen asks for selection of the EPROM code If the Model 2IA was selected in step 1 the routine will ask for selection of either the US amp S recommended EPROM Code 63 or the code for the alternate EPROM Refer to the Data I O Model 21A manual for information on the available EPROM types If the Model 201 or 212 was selected in step 1 the routine will ask for selection of two possible US amp S recommended EPROMS 7933 or 4533 or the code for the alternate EPROM Press the appropriate key for the type of EPROM 3 If an alternate EPROM is to be used the screen next asks for the appropriate code of that EPROM Refer to the S2ROM Programmer manual for this code 4 When the RETURN key is hit to enter the EPROM code the system is now ready for programming procedures 4 8 7 Programmer Operation G D S Versions 1 00 l Before entering the GENPROM program make certain the compiler debug switch for the simulator is turned off This may be done dy changing the switch to S D N or erasing the switch switch off default in effect If this is not done a series of error messages will appear at tne start of the GENPROM
88. he system is to be run If no time is specified RU CR the system will execute all equations on the Trigger List If the timer relay list has any entries the first relay will be ramoved from the list and tne system time will be incremented If the program contains no timer relays the default will execute all equations on the trigger list In the example at the top of the next page NBR3 is once again set with all Trigger List equations waiting to be executed and all timers at their full increments RU 100 CR is entered Equations will be executed and the system time incremented until 100 milliseconds has elapsed Next the system is run without a specified time interval Since the lowest queued timer relay delay is 400 milliseconds relay O0T 8 the system increments at this value Note that relay OUT 8 has now cleared and that 500 milliseconds remain on relays OUT 7 and TI The No Display command can also be used in conjunction with the Run command tc permit a larger scroll area Also the Run Command can be overated while observing the Display IO screen to observe the actual card inputs and outputs 6300A p 4 48 Run System for 100 Milliseconds Bit Number Name Vaiue Status Bit Number Name Value Status 1 OUT 1 cir 2 OuT2 cir 3 OUT 3 dr 9 OUT 4 set 10 OUT S 11 OUT 6 set 12 OUT 7 cir 300 set 13 OUT 8 set 400 cir 14 INA cir 15 N B cir 16 N C cir 17 N D cir 18 STICK set 19 T1 set 900 cir a N
89. ical input boards could use EPRCM N451575 0910 The empty indication board slots in this case are ignored by the program The N45 575 0910 code system EPROM is the GENISYS standard NOTES Any of the following EPROMS may be used in the non vital section of MICROLOK PLUS since this unit is limited to two non vital I O slots The Code System EPROMs contain complete programs that cannot be modified to include custom user logic If the GENISYS or MICROLOK PLUS unit is to include features in addition to a simple code system it must be custom programmed Table 8 1 Code System Application EPROMsS I Q PCB Configurations I O PCB Configurations Part Number Controls Indications Part Number Controls Indications N451575 0904 0 16 N451575 0913 9 7 0905 1 15 0914 10 6 0906 2 14 0915 11 5 0907 3 13 0916 12 4 0908 4 12 0917 13 3 0909 5 11 0918 l4 2 0910 6 10 0919 15 1 0911 7 9 0920 16 0 0912 8 8 8 4 CONTROLLER PCB HARDWARE PROGRAMMING See Figure 8 1 8 4 1 Slave Port Baud Rate SW1 Rotary switch SWI sets the baud rate of the Slave Port on the Controller PCB This rate may also be selected in the application program refer to section 4 2 2 3 The Master port baud rate is only selected on the application program If no Slave port baud rate is specified in the program the system will operate at the rate selected on SWI If the Slave port baud rate is selected in the p
90. igger List 10 System Time 00 00 00 000 Timer List 1 Command CL T1 Program N8R3 Sereen Relays put relay 19 T1 on timer queue 6300A p 4 42 Some relays Tay have a clear or set time egual to 0 msec In the example below OUT 7 clear time of 0 nsec is given a Clear command CL 12 CR or CL OUT 7 CR Since this relay has no clear delay the command nas the immediate effect of changing OUT 7 from invalid to clr Initial clear of relay OUT 7 Bit Number Name Value Bit Number Name Value Status 12 QUT 7 Trigger List 10 System Time 00 00 00 000 Timer List 1 Cammand CL 12 Program NBR3 Screen Relays clear relay 12 To put this relay on a timer queue for its 1000 msec set interval a Set command SE 12 CR or SE OUT 7 CR would be entered Relay OUT 7 set Bit Number Name Value Bit Number Name Value Status 12 OUT 7 1000 set Trigger List 10 System Time 00 00 00 000 Timer List 2 Command gt SE 12 Program NBR3 Screen Relays put relay 12 on timer queue 6300A p 4 43 An initial Set command for OUT 7 SZ 12 CR or SE OUT 7 CR outs the ralay on its set queue However since the relay started invalii and nas noz vet changed state the Value of OUT 7 remains invalid Initial set of relay OUT T7 Value Bit Number Name Bit Number Name 12 OUT 7 1000 set Trigger List 10 System Time 0
91. ign like non program comment To distinquish it from a comment a dollar sian must be placed immediately after the percent sign After the dollar sign is a single letter representing the switch name Next is a character s representing the value of the switch All characters after the value character s are ignored by the compiler until the next backslash symbol Example Comment S3 Sets switch S to value 3 D THIS IS A COMMENT FOLLOWING THE SWITCEN Sets switch D to off Remainder is a comment Compiler switches are as follows a Sn Set the Baud Rate on the Slave Port where n 1 through Hexadecimal E This value is defined on the hardware switch or in the source program and is a single character If no Slave baud rate switch is present in the source program the rate set on switch SWI will be used Software values for this function are listed in Table 4 4 on page 4 7 NOTE In Executive software revisions 0 through 10 of the following switch Mn a setting of n 0 would generate an error The revision 11 function is as follows Mn Set the Baud Rate on Master Port where n 0 through Hexadecimal This value is set only in the source program and is a single character If no Master baud rate switch is present in the source proaram the default rate is 1200 BPS If 0 is specified the compiler defaults to the setting on rotary switch SWI on the Controller PCB Softwara values and associated b
92. ime RB has already dropped therefore RC will not pick Differences in queuing options can be masked by using timers If RA or RB had a clear delay emulating a slow drop relay RC will always pick If RC is not to pick it could be given a set delay emulating a slow pick relay Either configuration may achieve the desired result 6300A p 5 7 8 SECTION VI MISCELLANEOUS APPLICATION INFORMATION GENISYS AND MICROLOK PLUS 6 1 LOCAL I O 6 1 1 Using Slave Units as I O Processors A GENISYS unit is capable of handling a maximum of 256 local input and output bits A MICROLOK PLUS unit non vital section is capable of handling a maximum of 32 local input and output bits Certain applications such as those with local control panel or event recorder may have local I O requirements for a single location that exceed the above bit limit Extreme care should be used when attempting to handle the additional I O with Slave GENISYS units Where possible the logic and local I O should be divided between units to share the system load as much as possible If only one GENISYS unit is designated to handle all logic and timing functions as well as local and serial I 0Q the chances of a system overload are increased 6 1 2 Determining the Control Delivery Time 6 1 2 1 Introduction The Control Delivery Time is the time that the system holds a deliver pulse on each relay output board This time is selected with a compiler switch in the application pr
93. ime incremented by 10 milliseconds Bit Number Name Value Bit Number Name Value e Pe 12 OUT 7 ele 990 set 13 OUT 8 set 490 cir 19 T1 set 990 cr Trigger List 10 System Time 00 00 00 010 Timer Ust 3 Command gt INC 10 Program N8R3 Screen Relays increment time 10 msec 6300A D 4 45 Next the system time is incremented by 490 milliseconds INC 490 CR the remaining time needed to clear ralav OUT 3 Note a the additional time on the system clock b the reduction of time on relavs OUT 7 and Tl c the State change for OUT 8 and d the reduction in the Timer List total System time incremented by 490 milliseconds Value Status 8it Number Name Value Bit Number Name 12 OUT 7 cir 500 set 13 OUT 8 cir 19 71 set 500 cir Trigger List 10 System Time 00 00 00 500 Timer List 2 Command gt INC 490 Program NBR3 Screen Relays increment time 490 msec 4 6 4 11 Display Timers Command The Display Timers DI TI CR command gives a listing of all relays currently on the timer queue with an active set or clear delay This command uses the same basic table as the Display Relays command In the NBR3 sample program the DI TI CR would produce Display timer relays Bit Number Name Value Status Bit Number Name Value 12 QUT 7 500 set 19 Ti 500 cir Trigger List 10 System Time 00 00 00 500 Timer List 2 Command DI Ti Program NBR3 Screen Relays 630
94. ined TSP Total number of Spare bits defined TINPT Total number of inputs defined Master Slave local TRP Total relays in parallel i e equations with two or more relays receiving the same value AC Average number of contacts in an assignment statement AO Average number logical operations per assignment statement NT Number of timer ralays defined NM Number of GENISYS units that will be addressed from Master part SL Zero 0 if Slave port is not used one l if Slave port is used NIOB Number of I O boards MA Memory used for assignment statements TMU Total memory used The memory requirement estimation for ASSIGN statement MA is given by MA TNR TSP TINPT TRP 4 2 4 AC AQ 2 TRP TS2 or more simply MA TNR TSP TINPT TRP 6 4 AC Ao 2 TRP TSP The total memory soit ene estimation of a system TMU is given bw TMU 16 MA 6 TNR 4 NT NIOB 4 9 SL 11 NM Z or more simply TMU 22 MA 6 TNR 4 NT NIOB 9 SL 11 NM NOTE The above formulas should be used only to obtain an estimate of memory usage Exact memory usage can only be determined by actually creating the program compil ing it and examining the EPROM 6300A p 4 54 1 7 2 Sample Execution A sample axecution of the GENSIZE program is shown below How many total relays defined integer How many total inputs master slave local integer
95. ing a change on each board If the external devices require each of the GENISYS outputs to be energized for 1 second the 10 second output lag cannot be avoided However if devices can tolerate a shorter Control Delivery Time this time should be utilized US amp S suggests a 70 millisecond Control Delivery Time for the Constant Delivery PCB N451441 7101 This time is sufficient to energize the particular type of relays used on this board For the Control Delivery N451441 3601 and Control and Delivery N451441 4701 PCBs the Control Delivery Time must be long enough for the Slowest acting device to recognize and accept the output state 6 2 SERIAL COMMUNICATIONS TIMING There is no standard formula for determining the proper timing elements of a GENISYS or MICROLOK PLUS serial data link When requested by the customer US amp S performs these calculations on a project by project basis using the unique specifications of each customer s system Contact the US amp S Headquarters office for assistance on the serial timing calculations 6300A p 6 2 SECTION VII SERIAL COMMUNICATIONS PROTOCOL GENISYS AND MICROLOK PLUS 7 1 INTRODUCTION NOTE On the following pages the character ge preceding a number denotes a hexidecimal base 16 number The sign is not a transmitted character 7 1 1 Message Format The GENISYS or MICROLOK PLUS non vital serial communications protocol consists of the following sequence of messages CONTROL SECUR
96. ing commands and their purposes that the command names include capital and lower case letters The capital letters are the minimum characters required for a valid command Usina the QUIT command as an example Q CR would cause an error message but QU cr would be a valid command QUI and QUIT are also valid Capital letters are only used on the help screen to show the shortest substring that can be specified for that command In practice these may also be entered in lower case letters for example qu qui quit NOTE The No Display command is discussed where it might be used with some of the other commands HELP SCREEN Display DIS play 10 TRiggers display ail values of VO boards display aif equations on trigger list RElays list display ail relays on display list Simulation 8it Operations Control VAlue list REMove list NOdisplay COtor MOno RUn x EXecute xj iINCrement x TRace x SEt list CLear list INPut list PRint file REAd file Quit RESet HEip Timers display all relays on timer queue display value of relay s remove relays s from list full screen display use color characteristics for display use monochrome characteristics for display tun system for x milliseconds execute x number of logic equations increment system clock x milliseconds display and execute x logic equations set relay s list clear relay s list input values for board
97. ing the application logic Programs to be run on the simulator must have the D switch The program does not have to be recompiled with D to permit programming of PROMS The default for this switch is s D N G D S Version 1 00 Same function After debugging the program must be recompiled with D to permit programming of EPROMs The default for this switch is D Qv Queuing where v or This switch sets the number of logic queues to be used One queue or two queues may be selected Refer to section 4 2 5 2 for a detailed description of this switch 3 Bv Symbol Table Listing where v or This switch inhibits the symbol table from being placed in the list file When set to B N this switch turns off the symbol table at the bottom of the compiler listing If the validation switch refer to previous page is enabled the program should be compiled with the symbol table enabled before the PROM is programmed This will insure that no unassigned outputs exist If any exist they should be assigned values and the program recompiled to avoid validation errors The default for this switch is 3 B NOTE The following compiler switch SSEN applies to GENISYS Development System Versions 3 0 and higher This switch is not available with earlier versions SSEN Page Generator When the compiler encounters the E switch the next source line is placed at the top of a new page in the compiler listing 6300A
98. ion logic can be develoved using the optional GENISYS Development System G D S This system enables the user to design and test his own program and then load it into the system hardware The G D S consists of a personal computer an EPROM Programmer and the GENISYS software which is contained on a single diskette The G D S can only be employed with the programming equipment supplied by USSS The Executive software of the vital and non vital sections of MICROLOK PLUS are common to all units The non vital section Executive software performs input internal and output logic operations defined in the non vital application logic This manual edition covers all software versions up to and including Executive Software Version ll and Application Compiler Software Version 3 0 6300A p 3 3 MICROLOK AND GENISYS DEVELOPMENT SYSTEMS PC e COMPILE AND SIMULATE APPLICATION LOGIC PROGRAMMER APPLICATION e CHECK EPROM LOGIC EPROM LOAD APPLICATION LOGIC 8K X 8 PERIPHERAL PCB Na51441 5502 DEVELOPMENT SYSTEM SOFTWARE FOR PC e THREE EXECUTIVE EPROMS IC20 21 22 Q COMPILER PROGRAMS e e UP TO THREE APPLICATION LOGIC EPROMS oe eee IC 15 16 19 e EPROM PROGRAMMER DRIVER e USES MICROLOK DEVELOPMENT SYSTEM FOR APPLICATION LOGIC EPROMS nne CONTROLLER PCB N451441 5602 CODE SYSTEM INTERFACE BCB NaS 1441 5302 e ONE EXECUTIVE EPROM IC29 ONE EXECUTIVE EPROM e APPLICATION OPTION CODE SYS
99. l parsing error and warning messages that may appear while developing the GENISYS or MICROLOK PLUS non vital program on the compiler With parsing errors the compiler will point with carets to the area where it first detected a problem and stop The carets may actually be pointing to an item past the location where the actual error occurred The programmer should look for the error at or before the carets Parsing Error Token Error Ref No Type of Error Ref No Type of Error l PROGRAM statement missing 1 Input line truncated 3 INTERFACE statement missing 2 Too many Identifiers 4 Remote I O specification expected declared 5 Address specification expected 3 Numeric constants qreat 6 INPUT or OUTPUT word specifica er than four digits tion expected 5 ID identifier 7 Relay name expected contains an illegal 8 Unexpected ID found after character 10 Incorrect interface format 6 Word more than 12 char ll COMMA or COLON expected acters 12 Semicolon or comma expected 7 Unknown compiler switch 13 Invalid SET OPTION 8 Missing or zero value fo 14 Invalid timer units specified compiler switch 15 16 Invalid timer SET CLEAR statement 17 Missing clear parameter on timer declaration 18 19 Invalid timer declaration 20 Invalid declaration format 21 BEGIN missing 22 Missing ASSIGN statement 23 ASSIGN statement or end of program expected 24 Invalid expression syntax warning 55 Semicolon
100. lay its state will be displayed in the status column All times ara specified in milliseconds As with the Display IO command all active relays begin with an invalid value and all SPARES are shown as clear clr Up to 34 relays may be displayed at any given time The relay display list can hold up to 34 relays If more relay additions are attempted to a full display list an error message will be generated When spare relays are present on an initial listing they can be removed to allow display of more active relays on a given screen This is done with the Remove command refer to section 2 6 4 7 In the following example DI RE 1 19 CR was entered Display All Relays Bit Number Name Value Status 8it Number Name Value OUT 1 18 STICK OUT 2 19 T1 OUT 3 SPARE SPARE SPARE SPARE SPARE OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 IN A IN B IN C IN D O NDUNA UN l ESS S DO W E E a Trigger List 10 System Time 00 00 00 0090 Timer List 0 Command gt DI RE 1 19 Program NBR3 Screen Relays Relays may also be displayed by name For example DI RE IN A CR would display the same relay as DI RE 14 CR bit 14 and IN A refer to the same relay 6300A p 4 38 4 6 4 7 Remove Command The Remove REM CR command allows removal of relays from the relay display list Relays can be ramoved by bit number or name In the example below REM 4 8 CR was entered to remove spare relays from the Display Relays ta
101. le When this command is read from the file the simulator pauses and accepts keyboard commands At this point the user may enter other commands When the continue command is entered the Read command continues to process commands from the Init file The Pause command will remain in effect until the Continue command is entered 4 6 4 17 Print Command The Print PR CR command is used to convert a compiler EPROM table i e a GCD file back into readable statements Only the assign statements in the source program are returned This command can be used to generata the Lagic equations if a compiler listing is not available To execute the Print command with the NBR3 sample program the user would enter PR NBR3 CR The default file extension for this command is GEQ L another extension is desired it must be entered in the command When conversion of the EPROM tables is complete the following message will appear Fil2 NBR3 GEQ contains the logic equations To obtain the logic equations themselves use the Quit command QU CR Ta leave the simulator type NBR3 GEQ CR In this instance the GEQ extension must be used 6300A p 4 51 The the identical format and syntax Statements in the This is a source listina normal feature of the simulator system nowever they are functionally For axamole the NBR3 program the assign statements are written as follows 22 ASSIGN IN A AND IN 3 TO OUT L gt 23 ASSIGN IN A
102. mand The Control Command is used to send controls to a station with checkback controls the slave responds with F3 message the Slave responds with Fl F2 Byte Description 1 FC 1 1 1 Repeat control byte 1 00 FF l 1 F6 7 2 2 4 Recall Indications Command The Recall Indications Command is used to recall responds with an F2 message Byte Description 1 PD 1 1 1 1 F6 7 2 2 5 Execute Controls Command 01 FF 00 FF 00 FF 00 FF 01 FF 00 FF 00 FF With non checkback controls Comments Control Command station number 0 not used control byte number control byte number and data as required low byte of CRC 16 high byte of CRC 16 terminator all indications The Slave Comments Recall Indications command station number 0 not used low byte of CRC 16 nigh byte of CRC 16 terminator The Executive Controls Command is the response to a valid control checkback The Slave responds with Fl F2 Byte Description 1 FE 1 1 1 1l 76 7 2 2 6 Common Control Mode 01 FF 00 FF 00 FF comments Execute Controls station number 0 not used low byte of CRC 16 high byte of CRC 16 terminator The Common Control Mode is used to deliver control byte 0 or 1 to one or all Slave units Slave does not respond Control bytes 0 and l are always accessible by the control FC command regardless of the state of the Allow
103. maximum of 500 equations may be present on each queue break and make Any attempt to queue more equations using either option will be ignored by the Run Time executive The Q option is slightly faster and should be used when possible However it may cause problems with same stick circuits consult US amp S Engineering 4 2 5 3 Serial Communications Pre Defined Relays When the serial I O lines Master or Slave are used in GENISYS or MICROLOK PLUS it may be necessary to condition logic processing for successful or unsuccessful completion of communications i e code line up or down Par example 1 A Master unit may be programmed to turn on an output i e an indicator lamp when it loses communications with a Slave unit 2 A Slave unit may be programmed to perform field auto clear functions if communications are lost with its Master unit Both of these situations can be accommodated with the GENISYS or MICROLOK PLUS non vital system The compiler contains pre defined relay names that are SET and CLEARed automatically by the Run Time system On the Master Port one internal relay is created for each Slave unit address specified in the MASTER part of the INTERFACE section Each name is automatically defined as follows SLAVE ON n The letter n corresponds to the address of the particular Slave unit served by the relay The value of n may range from 1 to 255 the same range as Slave unit addresses These relays may
104. may be placed before a proaram statement 6300A p 4 12 4 2 4 2 INTERFACE Section a General The INTERFACE section defines the various output and input specifications af the system There are three sub sections in the INTERFACE section LOCAL I O MASTER I O port and SLAVE I O port These correspond to the three input output interfaces on the controller board At least one of the three I O interfaces must be defined Bach begins with a name LOCAL MASTER or SLAVE that designates the type of interface The LOCAL I O if any is defined first followed by MASTER if any and then SLAVE if any Within each of these outputs if any are defined first followed by inputs if any Either outputs or inputs may be blank but not both at the same time The standard format is shown at the top of the next page b LOCAL I O The LOCAL I O subsection defines the names of the bits that are input and output on the cardfile I O boards If there is no local I O this subsection may be omitted GENISYS Up to 16 words may be defined with 1 to 16 bit names on each word MICROLOK PLUS One or two words may be defined with 1 to 16 bit names on each word Each input or output WORD corresponds to a single I O board The first symbol defined on each word corresponds to the First input or output on the corresponding board The second symbol corresponds to the second input or output and so on On interfaces where there is an unused bit
105. mple ASSIGN A AND B OR NOT C TO D E F 6300A p 4 19 4 2 5 Run Time System Description 4 2 5 1 Input Output Description The GENISYS and MICROLOK PLUS non vital section svstems use an internal RAM table containing the current state of every relay defined in the svstem This table includes the LOCAL input and output bits as well as the internal bits defined in the VAR section The values of LOCAL input bits in the table are automatically updated in a 50 millisecond scan Therefore LOCAL inputs may not receive a value based on an ASSIGN statement otherwise a logical conflict could exist For example there could be an input with an actual state of 1 and a logic ASSIGN statement which computes its value as 0 The LOCAL output bits are delivered in groups of 16 whenever any one of the bits in that group change state If Constant Delivery relay output boards N451441 7101 are used the outputs directly follow the states of the internal table Input bits on either the Master or Slave serial line have their internal table value updated differently When a GENISYS or MICROLOK PLUS unit receives a bit on a serial line its received value is put in a table It will keep that value until the bit is received again Because the input value of serial bits is only updated when received each may also be given a value with an ASSIGN statement However no more than one ASSIGN statement may be specified for each relay The slot off of a si
106. n which equations ara executed affects the internal and autput states of the system To emulate relay circuits operation as closely as possible the executive employs the traditional break before make rule of relay systems It determines which equations involve the front contact and which equations involve the back contacts of a relay in a typical application Depending on whether the relay 6300A p 5 5 picks or drops one set of contacts is defined as the breaks and one set is defined as the makes Those equations that ara the breaks ara executed befor2 those that ar the makes When a change of state is observed by an input internal or output bit all logic equations that involve a contact of that bit are queued for execution breaks before makes 5 4 3 Queuing Options The Executive software has two available queuing options These are selected with compiler switch Q Queuing The Q setting which is the default setting selects the one queue option The Q setting selects the two queue option There are certain cases where the queuing option affects the internal and output states of the system The one queue option has one queue in which all equations to be executed are placed breaks before makes The executive takes equations out of the queue one at a time starting with the first equation and continuing until the queue is empty If any executed equation causes a change in value of anv bit more equations m
107. nd Key Off Delays are activated The RTS line on the serial port is toggled high for the specified number of bit times before the a byte is sent and toggled low for the specified number of bit times after the byte has been sent across the serial line This feature is applied when using modems which require toggling of the RTS line a certain number of times before the data byte is sent 6300A p 8 7 NOTES With Executive ZPROM IC29 Revision 3 and higher the incoming carrier DCD on the Master and Slave ports must be turned off and kept off before a outgoing transmission can be made Other wise transmissions from these ports will be aborted This applies to half duplex communications only When the outgoing carrier from the Master port is on RTS on changes in the incoming carrier will not affect the data trans mission When the outgoing carrier from the Slave port is on changes in the incoming carrier will cause the transmission to be aborted These conditions apply to half duplex communica tions only and are in effect with all revisions of the Executive EPROM 8 4 4 Slave Station Address SW5 DIP switch SWS selects the station address of a GENISYS or MICROLOK PLUS non vital Slave station This switch may be ignored when the unit is a first Master or stand alone unit If no station address is selected in the application program address O defined the station address will be defined by the value on switch SW5 The stati
108. nd higher also allow the user to retry the connection to the Orogrammer without terminating the program 4 When the file name is entered the program will indicate how many blank EPROMS are needed to carry the entire Drogram Type in anv key except x as indicated by the prompt at the bottom of the screen 5 Model 201 or 212 Programmer As requested on the screen use the twa scroll keys on the Model 201 or 212 so that RS232 PORT appears on the LCD display When this message appears press the ENTER kev on the Model 201 or 212 Next use the two scroll keys so that COMPUTER CONTROL appears on the LCD display When this message appears press the ENTER key on the Model 201 of 212 6300A p 4 57 Wn it Model 21A Progarammer Execute the instruction Enter SELECT gt C lt SET gt on the programmer As instructed on the screen place a blank EPROM in the programmer Make certain the pin latching lever is in the up position and insert the EPROM with the notch away from the lever then close the lever Press any key on the computer when the EPROM is inserted The screen wili then indicate which ZPROM if more than one ara required will be programmed the hexadecimal base address of that EPROM the program file name and several instructions The base addresses are 4000 6000 80at A000 and c000 When any key is pressed on the computer the screen should show the following series of messages Blank check o
109. ng the time ASSIGN statements are being computed no output operations local or serial ar2 performed inputs are still scanned at 50 millisecond rate Any output started before the logic sequence will continue to be processed However outputs cannot be updated In accordance with actual relay logic practices logic processing always uses a break before make format When a relay changes values the break is done before the make However there are circumstances where a make may occur before a break in a relay chain depending upon the setting of the queueing compiler switch SQvN v or The relay execution order in Figure 4 3 shows the operation of this switch option Q ORDER Q ORDER BREAK 1 EQ 1 EQ 2 EQ2 L R3 2 03 3 EQ3 3 EQ6 4 EQ 5 EQ6 MAKE 6 EQS 4 EQ2 n Pe 6 EQS Figura 4 3 Queuing Option Reference Diagram When the switch is set to Q default equations are processed relay by relay with breaks executed before makes in the order in which they occur In Figure 4 3 if relay Rl changes state EQl is executed break followed by Q2 make Next the change in EQl relay R2 causes EQ3 to be executed break thus the make of EQ2 occurs before the break of EQ3 If the queuing switch is set to Q there are two queues for logic equations including one for the breaks and one for the makes Breaks are always done First regardless of when they happen In Figure 4 3 note that the three break e
110. o input IN D is added as the 4th input bit A new section VAR is added to define an internal bit An internal bit is neither input nor output it is only processed internally All internal VAR bits are initially deenergized An example is a stick relay Note the additional ASSIGN statement ASSIGN IN C OR STICK AND NOT IN D TO STICK 6300A p 4 9 When input IN C is eneraized STICK becomes energized With the following direct assianment of STICX to OUT 6 both OUT 6 and STICK will remain energized even if IN C is deeneraized The internal STICK and OUT 6 will cemain energized until IN D is energized This results in the clearing af the stick circuit Note however that if IN C is still energized STICK and OUT 6 will remain energized 4 2 3 3 Timing Relays The sample program below shows the handling of timing relays This program makes use of one timer relay Continuing from the example in section 4 2 3 2 two more defined output bits OUT 7 and OUT 8 are added In the VAR section another internal relay T1 is defined Relays with timing characteristics ara defined in the TIMER section always after the VAR section Every bit name specified in a TIMER statement must be previously defined as an output or internal bit Input bits may not have timina characteristics PROGRAM NBR3 INTERFACE LOCAL OUTPUT WORD OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 INPUT WORD IN A IN B IN C IN D VAR STICK T1 TI
111. ogram or on the Controller PCB For the Control Delivery PCB N451441 3601 and the Control and Delivery PCB N451441 4701 the Control Delivery Time represents the time the outputs remain energized With the Constant Delivery PCB N451441 7101 which has a final stick output outputs remain energized after the Control Delivery Time expires Refer to section 4 2 2 3 for the Control Delivery Time compiler switch options in the application program Refer to section 8 4 2 for the Control Delivery Time switch settings on the Controller PCB 6 1 2 2 Selection Considerations The optimum Control Delivery time is determined by the application The selected time must be long enough to activate the devices connected to the GENISYS or MICROLOK PLUS non vital outputs but not longer than required The Executive software delivers controls to one relay output board at a time When changes are to be delivered to several boards at once the changes area sent to these boards one at a time The deliver pulse must be held on each output board for the length of the Control Deliver Time I the control Deliver Time is set too long it can delay an output sequence for a GENISYS system For example a GENISYS system has 10 relay output boards and each of the 10 boards needs controls delivered to it If the Control Deliver Time is set to 1 second there will be a 10 second lag between delivery of controls to the first board and delivery of controls to the last board assum
112. on address can be any value in the range of 0 to 255 Table 8 4 lists rocker positions and corresponding address values A 0 indicates the rocker is closed and l indicates the rocker is open Selected bits are added toqether to from the desired address For example Slave station address 3 is created by placing rockers 1 and 2 to the 1 position and all remaining rockers to the 0 position Table 8 4 Slave Unit Station Address SWS Rocker Bit Value SW5 Rocker Bit Value 5 16 6 32 7 64 8 128 8 4 5 Key On and Key Off Delays SW6 DIP switch SW6 selects the carrier Key On and Key Off delays Rockers Il through 4 define the Key On delays while rockers 5 through 8 define the Key Off delays Table 8 5 lists rocker positions and corresponding delay values A 0 indicates the rocker is closed and l indicates the rocker is open 6300A p 8 3 Table 8 5 Key On and Key Off Delays SW6 Switch 6 Rockers Switch 6 Rockers 4 Key on Delay yon jw Ju a jan la a Key 0ff Delay 0 0 0 0 zero delay 0 0 0 0 zero delay 1 0 0 0 4 l 0 0 0 4 0 l 0 0 8 0 1 0 0 8 1 1 0 0 12 l 1 0 0 12 0 0 1 0 16 0 0 1 0 16 1 0 1 0 20 l 0 1 0 20 0 1 1 0 24 0 l 1 0 24 1 1 1 0 28 1 1 1 0 28 0 0 0 1 32 0 0 0 1 32 1 0 0 l 36 1 0 0 l 36 0 1 0 1 40 0 1 0 1 40 1 1 Q 1 44 1 1 0 1 44 0 0 1 1 48 0 0 1 1 48 1 0 1 l 52 1 0 1 1 52 0 1 1 1 56 0 1 1 1 56 1 1 1 1 60 1 1 l 1 60 8 4 6 Communications Mode Select Jumpers Jumpers Jl through
113. on the Trigger List The System Time records the total time elapsed during the execution of simulation Left to right increments are in hours minutes seconds milliseconds All timed operations are advanced in increments of tens of milliseconds The Timer List provides the total number of timer relays in the source program that are on a timer queue Command names and lists of items such as relays are entered after the Command prompt and executed with a carriage return CR When entering a series of non consecutive items after the command leave a space between each item number i e 1 3 7 12 19 When entering a series of consecutive items a dash may be used for the intermediate items i e 1 5 7 9 11 30 Use the same procedure when listing items by name i 2 OUT 1 OUT 3 OUT 5 If more items are requested than are available in the listing an invalid range error listing will appear Do not attempt to enter more items than space allows between Command and Program Instead enter a CR after the first group and repeat the command to enter a following group Program indicates the name of the source program undergoing the simulation Screen indicates the type of information presently on the screen For example the initial GENSIM cover screen is Init Scrolled information is run in the space immediately below the status lines For example selected commands show source program logic equations and output results
114. process multiple logic functions sequentially For example where a single contact in a relay system is used in processing two different logic functions both logic functions start processing simultaneously when the relay changes state In GENISYS and MICROLOK PLUS however one equation is processed before the other Also when a relay changes state in an actual relay system there is a very brief time when neither the front or back contact has energy applied When a relay changes state in the GENISYS or MICROLOK PLUS non vital lagic program there is no true transfer time In GENISYS and MICROLOK PLUS those equations that use the energized state of a bit can be equated to the front contacts of a relay Those equations that use a de energized state can be equated to the back contacts of a relay An example is provided in figure 5 1 R1 RA ASSIGN R1 TO RA j ASSIGN NOTRI TO R8 igure 5 1 Example of Front and 3ack Contact Assignments j In this example the RA equation is the front contact and the RB equation is the back contact All equations that use the NOT overand are a back contact In a relay system there will be a measurable time when R1 starts to dron when neither the Front nor back contacts has energy applied In GENISYS and MICROLOK PLUS this transfer is instantaneous Either the front ar back contact has energy applied at all time 5 4 2 Breaks Before Makes Rule The Executive softwar2 recognizes that the order i
115. quations EQl EQ3 EQ6 are executed before any of the makes Even if the makes were queued first and then break occurred the break is done first NOTE The following paragraph applies to GENISYS Development System versions 3 0 and higher In versions of the compiler before 3 9 the Break Before Make rule was not always followed when processing some types of logic equations Under certain limited conditions logic equations could be executed in an order that would not strictly follow the Break Before Make ordering Version 3 00 is desianed to assure that all equations will be properly processed and executed in the Break 3efore Make order If an older application logic proaram is recompiled with version 3 00 the EPROMS generated may not be identical to the older EPROMs These differences would only involve the order in which the logic equations are processed No changes ar2 required on any installation that is currently in service and has undergone complete testing during a cut over 6300A p 4 21 NOTE The following paragraph applies to GENISYS Develop ment System Versions 1 03 and higher and Executive PROM IC29 Revisions 3 and higher In earlier Versions and Revisions a maximum of 500 equations may be queued at any one time If the 2 queue option Q is used a maximum of 250 equations may be present on each queue break and make A maximum of 1000 equations may be queued at any one time If the 2 queue option Q is used a
116. r 3 SPECIFICATIONS Proaramming Related Total Bits Local I O Boards Local I O Bits Master to Slave Communications Slave to Master Communications Serial Addresses Serial Baud Rates Active Timing Elements Logic Equations Triggered 1450 bits maximum can be divided between local I 0 serial I O and internal 16 maximum per cardfile any combination 16 maximum per local I O board 255 Slave units maximum communication from Master unit l Master unit maximum communication from Slave unit 1 to 255 inclusive 50 75 100 134 150 300 600 1200 1800 2400 3600 4800 7200 9600 100 maximum active at any one time in application logic more timers may be defined 1000 maximum one queue option 500 maximum each queue two queue option refer to page 4 21 6300A Da 2 6 SECTION III GENERAL INFORMATION MICROLOK PLUS 3 1 INTRODUCTION 3 1 1 Overall System See Figure 3 1 The MICROLOK PLUS Vital and Non Vital Control Package is a multi purpose microprocessor based device designed for use in both vital and or non vital railroad control systems t is typically used for smaller applications such as a single end of siding that do not require the large input output capabilities of seperate vital and non vital controllers The device can be configured with a vital control section only or with vital and non vital control sections A non vital only configuration is also possible bu
117. ram for the Slave section of unit 3 is as Follows SLAVE ADDRESS 3 OUTPUT OUT 3 A OUT 3 B INPOT IN 3 A IN 3 8 In this example the Master unit refer to program segment on previous page outputs SND A 2 and SND B 2 to Slave unit 2 where they are input into the relays IN 2 A and IN 2 B respectively Unit 2 outputs OUT 2 A and OUT 2 B which are received by the Master unit as RCV A 2 and RCV B 2 The I O for unit 3 is similar NOTES A single GENISYS OR MICROLOK PLUS unit may be program mmed to use both its Master and Slave ports simultaneously Two or more units programmed to be Slaves of some Master cannot conduct direct serial communication with each other Any communication between Slave units must pass through their common Master unit 4 2 4 3 VAR Section The VAR section of the GENISYS program is used to specify the names of internal relays those that are neither input or output Relays not defined in the VAR section must be defined as an input or output on a MASTER SLAVE LOCAL interface The format of the VAR section is as follows VAR id list Each identifier in the id list is separated by a comma 6300A p 4 16 4 2 4 4 TIMER Section NOTE Refer to section 5 2 for a detailed description of system internal timing The TIMER section of a program is used to give distinct set pick or clear drop delays to an internal relay or output bit A bit not specified ina TIME
118. re 8 bit byte from being deliverad 5 3 3 Recommendations If the Validation Option is turned on check the list file generated by the development system compiler to verify there are no unassianed outputs on the serial links or the local boards When upgrading a GENISYS or MICROLOK PLUS non vital system to a hiaher revision of the executive PROM IC29 and usinga the Validation Oovtion on make sure the new configuration does not cause operational problems 6300A p 5 3 With revision 7 and higher of the executive software the Validation Option resolves mora logic equations than earlier ravisions Asa result local or erial outputs may be delivered that would not have been delivered with the arlier software revisions L u The following tabulation lists the applications of the Validation Option with the different executive software revisions Statement Revision No Result VALID OR VALID 9 and higher VALID VALID XOR VALID 0 and hiaher VALID VALID AND VALID 0 and higher VALID NOT VALID 0 and higher VALID INVALID OR INVALID 0 and higher INVALID INVALID XOR INVALID 0 and higher INVALID INVALID AND INVALID 0 and higher INVALID NOT INVALID 0 and higher INVALID VALID OR INVALID 0 6 INVALID VALID OR INVALID 7 and higher See below VALID XOR INVALID 0 and higher INVALID VALID AND INVALID 0 6 INVALID VALID AND INVALID 7 and higher 3 See below 0 OR INVALID 7 and higher INVALID 1 OR INVALID 7 and higher VALID VALUE OF I 0 AND I
119. rogram compiler switch Sl through 8 SF this rate will override the SWI setting Table 8 2 on page 8 7 lists the available Slave Port baud rates on SWl NOTE In Executive software revisions ll and higher a setting of 0 on the Master port baud rate in the application logic program causes the system to default to the hardware baud rate for the Slave port 6300A p 8 5 d vOot9 9 8 It g In rd SUOTIUO pazdatas AITENUPW gd 21a IO1Juon GENISYS NON VITAL LOGIC EMULATOR MICROLOK PLUS VITAL NON VITAL CONTROL PACKAGE CONTROLLER PC8 BOARD N451441 56 REV NO EXEC SOFTWARE 1C29 REV NO IC29 PART NO N451575 0901 SERIAL NO LOCATION OPTIONS SELECTED SLAVE ADDRESS TYPE Hi gan VALUE KEY ON KEY OFF CONTROL DELIVERY TIME TYPE H gan VALUE SLAVE BAUD RATE TYPE H _ S VALUE COMMUNICATION EIA OR TTL JUMPERS 1 10 SET A B FOR EIA B C FOR TTL HARDWARE SELECTED SOFTWARE SELECTED CARRIER TEST AND ADJUST ROCKERS X EITHER POS OK ERIAL POR E h E la l TEST FUNCTION pani KE Aa Han A mrw oe n paa AS AND 6 0 X X NORMAL OPERATION REVISION TAND C uoa sais NOTE vjojx x PI PORT TEST kk PROM 1C29 ONLY C uos maro a mou NEFER YO TENT ONE ka li PAY bate e TEST use CLOSED ODO PARITY CJ tou FOR SET UP OF kl Taastea AND SLAVE OPEN EVEN PARITY C uos siro THESE SWITCHES PORT TESTS C ims san p X 1 fx f
120. rst screen asks for selection of Commmunication Port I or Communication Port 2 This allows use of either Port 1 or Port 2 on the back of the computer Press the 1 key on the terminal for Port l ar the 2 key for Port 2 2 The second screen in the routine asks for selection of either the Model 21A 201 or 212 programmer Press the 1 key on the terminal for the model 214 the 2 key for the 201 or the 3 key for the 212 3 The next screen asks for selection of the EPROM family pinout code If the Model 21A was selected in step l the routine will ask for selection of either the US amp S recommended EPROM Code 63 or the code for the alternate EPROM Refer to the Data I O Model 21A manual for information on the available EPROM types If the Model 201 or 212 was selected in sten l the routine will ask for selection of two possible US amp S recommended EPROMs 7933 or 4533 or the code for the alternate EPROM Refer to the Data I O Model 201 ar 212 manual for information on the available EPROM types Press the appropriate key for tne type of EPROM 4 If an alternate EPROM is to be used the screen next asks for the appropriate code of that EPROM Refer to the EPROM Programmer manual for this code 6300A gt 4 56 5 When the RETURN key is hit to enter the EPROM code raady for programming procedures The screen shows e options i a Fart l or Port 2 selected to this point IF the onzions ara corract caress Y to con
121. s after receiving 1 a header with no trailer or 2 a trailer without a new message that starts with a header the bit is cleared 4 2 5 4 Valid Bit Option Introduction NOTE Refer to section 5 3 for a detailed description of the Valid Bit Option At power on reset the GENISYS or MICROLOK PLUS non vital unit sets all internal and output relays to zero clear No actual output can occur at this time After the initial reset optical input boards if any are scanned to determine the value of bits defined as LOCAL INPUT bits in the program If any input bits are defined in the program but refer to boards not actually in the cardfile those bits will be given Invalid or unknown values Similarly any bit defined as an input on either of the two serial lines becomes invalid until the bit is received from the unit at the other end of the line During processing of an ASSIGN statement any invalid input bit referenced during the computation will stop the processing procedure The relay defined as the object of this ASSIGN statement cannot be changed Only invalid input bits will stop the processing of a logic statement Output and internal bits may also be invalid but will not interrupt the completion of an ASSIGN statement At reset these types of bits are initialized as zeros They are treated as valid zeros during processing of ASSIGN statements Once all output bits in a LOCAL output word or serial protocol b
122. s file the simulator cannot be run In the simulator logic execution follows the same alogrithm as the Run Time system refer to section 4 2 5 4 6300A Dd 4 28 The simulator supports the following two switches Switch Name Comments Q Queuing Option If Q use two queues break before make otherwise use only one queue Default is Q one queue v Validation Check If v INVALID becomes a valid state and is checked during execution of logic equations If an equation contains an invalid bit it will be executed per the rules in section 4 2 5 4 If v all bits are cleared Default is V validation on 4 6 2 Access to Simulator 4 6 2 1 General NOTE The following paragraph applies to GENISYS Develop ment System Versions 1 01 and higher Refer to section 4 2 2 3 page 4 6 for the debug switch used in Version 1 00 The simulator uses the EPROM file produced by the compiler If a program is to be debugged using the simulator it must be compiled with the debug switch on S D N The program does not have to be recompiled with 34D to permit programming of PROMS The default is D Command terms in the following text are shown in all capital letters to help distinguish them from other words in the text In the acutual use of the simulator these words may be typed in lower case letters as well as upper case CR indicates the carriage return key or ENTER 4 6 2 2 Procedure NOTE In GENISYS Develpment Sys
123. set up properly Hardware malfunction Ouptut of compiler is not in a valid format because Bad disk EPROM code file modified after creation by compiler Same as above The EPROM programmer did not recognize the EPROM type because of a set up problem As indicated Defective EPROM During verification stap in download EPROM oro grammer returned an error code Refer to programmer manual for error code meanings EPROM could not be read by the programmer error message returned Refer to programmer manual for error code meanings Program too large for the GENISYS or MICRO LOK PLUS hardware 6300A p 4 60 Remedy Check Data I 9 manual Repair or replace EPROM programmer cable and or computer Recompile on new disk Recomoile Same as above Verify that the EPROM programmer has been set up correctly Check that the EPROM ts fully inserted in the holder and that the lever is down Replace EPROM Check for possible jerrors and recompile the oe program connect es sage PROM WA Ze en cejected the data rror code from PROM ESE ere ai Transmission error during data transfer Data verification error data conflict between computer and PROM Pro agrammer The PROM did not program it may be damaged Error code Erom PROM programmer Unable to successfully with PROM program mer Pa n n n ce
124. t not typical In a typical single end of siding application both sections are utilized The vital section controls the interlocking logic manages switch machines signals and track circuits in the control area while the non vital section provides an interface point for a local control panel processes CTC office commands and transmits indications from the vital section Another typical end of siding configuration could consist of the vital section only with code system inputs and outputs processed within the vital section no local control panel The MICROLOK PLUS system is derived from the US amp S MICROLOK Vital Interlocking Control System and the GENISYS Non Vital Logic Emulator It uses the same plug in printed circuit boards the same Executive software and the same application logic compilers as the MICROLOK and GENISYS systems 3 1 2 Non Vital Section The non vital section of MICROLOK PLUS incorporates a Master port that enables the device to serve as the managing unit of a non vital Master Slave system Up to 255 Slave units can be controlled from this port although the practical upper limit is about 40 to 50 units The Slave units for such a system might include additional MICROLOK PLUS or GENISYS units or a combination of both The non vital Slave port enables the unit to function as a Slave to another Master unit The Master unit can include another MICROLOK PLUS unit non vital section a GENISYS system or an office compu
125. t was written using the monochrome character istics of high and low intensities and underlining If earlier Simulator versions are used on a PC with a color display the output screens are displayed with mono chrome characteristics which would be displayed using different colors Since the earlier version uses under lining to divide the screen into regions colors do not adequately suffice The Version 3 00 Simulator makes use of both monochrome and color characteristics to produce more easily viewed displays The default mode af the Simulator is monochrome When using a color display with Version 3 00 the command COLOR must be entered to select color graphics instead of monochrome graphics Also a MONOCHROME command is available to revert back to the default mode In either mode the same volume of information is displayed 6300A p 4 53 4 7 G 5 S EPROM SIZE ESTIMATES PROGRAM 4 7 1 General The EPROM Size estimate program can be used to determine the total number of bytes in the completed source program This program is useful in estimating the approximate number of EPROMS that will be needed to carry the application Program The GENSIZE help screen provides the memory usage algorithm for this astimate The details of this algorithm are not required for determining the number of application EPROMs they are provided for general reference The terms used in the algorithm are listed below TNR Total number of relays def
126. tains an illegal character 6300A D 4 2 4 2 1 4 Delimiters Delimiters separate individual words Delimiters in the non vital proaram language are listed in Table 4 3 Table 4 3 Delimiters space semicolon 3 open parenthesis to tab equal sign close parenthesis colon comma carriage return CR backslash N percent 3 tilda A at Plus sign Asterisk Every distinct word or token in the source program must be separated by one of the above delimiters Extra space and tab delimiters may be inserted anywhere in the program they have no effect on the meaning of the program 4 2 2 Formats 4 2 2 1 General Arrangement of Statements Source program statements may begin anywhere on a line with tans Non significant spaces are ignored by the compiler If a statement is toa long to Fit on one line it may be continued to any number of following lines as required The maximum allowable line length is 100 characters If this is exceeded an error message will be generated Although the non vital compiler uses a free format statements should be arranged for easy reading 4 2 2 2 Non Program Comments Miscellaneous comments may be inserted in the source program to aid the user in charting and reviewing the program To distinquish a non program comment From program statements begin the statement with a and end with a backslash For example 3 THIS IS AN EXAMPLE OF A LEGAL GENISYS OR MICROLOK PLUS COM
127. te expressions in a program These are listed in Table 4 7 Table 4 7 Logical Operator Symbols eserved Shorthand Reserved Shorthand Word Operator Word Operator 6300A p 4 18 Sither form Reserved Word or shorthand operator character may b used in assignment expressions For example the ASSIGN statement shown on the previous page may be written using shorthand symbols ASSIGN IN A IN C La sa IN A IN B TO OUT 5 The operators AND OR NOT and XOR along with their shorthand symbols are evaluated according to the truth tables in Table 4 8 Table 4 8 ASSIGN Operators Truth Tables The order of evaluation is determined by the following precedence rules HIGHEST NOT AND LOWEST OR XOR Operations with the highest precedence are performed first Operations at the same precedence level are evaluated left to right Parentheses may be added to alter this default order Parentheses take precedence over the defined operational order The order of evaluation of the above assiaqnment statement is shown in Pigure 4 2 ASSIGN INA AND T INA OR N B TOOUT S A OR AND L A so man A OR AND C Figure 4 2 ASSIGN Operators Order of Precedence Samples If more than one relay is to be assigned the same value the logic expression need not be repeated in a second ASSIGN statement Additional relay names may be assigned using the same statement by listing them after the TO Reserved Word separated by commas For exa
128. tem Versions 1 02 and higher the user can enter the simulator as GENSIM or GENSIM file The latter option allows the file name to be obtained from the command line without being prompted l The simulator is run by entering GENSIM and a carriage return CR as shown in the Help Pile The simulator cover screen will then be displayed showing the version of the simulator 2 The prompt on the cover screen asks for the name of the source program When the name is entered a tabulation will appear immediately below This table lists the basic totals of bits and boards in the source program 6300A p 4 29 3 Entry of the program name will also produce several permanent status lines near the bottom of the screen These lines are explained in section 4 5 3 To obtain a summary of all simulator commands enter HELP CR at the command prompt in the second status line The Help Screen is explained in section 4 6 4 3 l NOTE The examples shown use programs compiled with the Validation Option on V This initially flags all bits as invalid 4 6 3 Standard Formats A typical set of status lines for the begining of a simulator exercise is shown below Trigger List 10 System Time 00 00 00 000 Timer List 0 Command Program NBR3 Screen Init The Trigger List refers to the total number of logic equations that are queued to be executed Whenever a bit changes all logic equations that usa that bit will be placed
129. ter When the application requires a serial link between the non vital and vital sections of the MICROLOK PLUS unit the non vital Master port is used for this purpose while the Slave is used for external communications Non vital serial link communications are formatted to ETA RS 423 standards and derated to operate under the RS 232C standards This enables the MICROLOK PLUS non vital serial ports to be interfaced to an ETA compatible modem for remote communications 6300A De 3 1 NON VITAL CONTROL SYSTEM e MICROLOK PLUS M MASTER CONTROL SYSTEM NON VITAL SECTION MICROLOK PLUS M eGENISYS VITAL SECTION SEE SM 6300B FOR COMPLETE SERIAL COMMUNICATION LINK OPTIONS VITAL CONTROL SYSTEM SLAVE e MICROLOK PLUS VITAL SEC CODE e MICROLOK CODE NON VITAL CONTROL eMICROLOK PLUS eGENISYS SYSTEM SLAVE WA NON VITAL SECTION NON VITAL CONTROL SYSTEM MASTER MICROLOK PLUS NON VITAL SECTION eGENISYS OFFICE COMPUTER MICROLOK NON VITAL SERIAL LINK eM an am Wi m WE a om e em am m n ma mn mn ye Gn m e on em on a nn NON VITAL SERIAL LINKS VITAL SERIAL LINK NON VITAL LOCAL CIRCUITS NON VITAL SERIAL LINK CONTROU Z E d vooct9g I sanbl WSISAS SNI XOTOUJIHK Diseg 1 1 i 1 I f l i RELAY sonar amp A ae LAMPS i i cS Ee f
130. the sequence for system initialization The remaining lines shows a normal background polling scheme used by a Master unit This table only shows the First control character to be sent by the Master and does not show any field responses or additional messages sent by a Master to the same field 6300A on 7 2 si s2 FD FD FC rc FD FB FC FB FB FB FB FB FB FB FB FB FB FB FB FD FD FC FC FB FB FB 3 Station No s4 s5 s6 Messages FD FD FD SFC Fc SFC FB FB FB FB FB PB FB FB FB FB FB FD FB FD FC FD FC FB Pc FB FB FB FB FB FB FB FB FB FB FB FB FB FB S7 The Master unit will start a communication with a Slave unit usina any one of the following messages and the Slave unit will respond as indicated Master Unit Message FD rc Slave Unit Response F2 All data being sent F2 Changed data being or F1 No data changes to F2 Changed data being or 71 No data changes to sent report sent report When the Master unit decodes the Slave unit s response the Master unit will format its next message a If the Slave unit responds with an Fl message the Master unit may transmit a message to the next Slave unit in the polling cycle b If the Slave unit responds with an F2 message the Master unit will send an acknowledgement message FA before continuing with the next Slave unit C In turn the Slave unit
131. tinue If not sress N to re enter this information he system is now h n b pe 4 8 3 Programmer Operation G D S Versions 01 and fiaher NOTE Refer to section 4 8 7 if running the Following pro cedure using GENISYS Development System Version 1 00 l Model 201 or 212 Programmer Turn on the programmer and check that SELF TEST OK DATA I O 201 N appears on the LCD display This indicates that the programmer has passed its ow start up diagnostics no not make any other adjustments on the programmer Model 21A Programmer Open the small access panel on the front of the Model 21A and set the three left nand rotary switches to 5 9 and C respectively Do not ceadjust the three right hand switches Note These will be the permanent positions of these switches for all future operations of the programmer They do not have to be reset each time power is turned on Then turn on the Model 21A and check that the word PASS appears on the ADDRESS portion of the digital display This indicates the programmer nas passed its own start up diagnostics 2 Type GENPROM or genprom and a carriage return CR to enter the EPROM progarammer routine 3 The file name of the source program should be entered after the srampt Enter the name of the PROM file followed by a CR NOTES In Versions 1 04 and hniaher the program will con tinue even if an incorrect File name is entered The user may retry the file name Versions 1 04 a
132. tions interface for any external devices Primary functions include management of local I O via card file interface boards and remote I 0 via serial data line according to the custom design program and execution of internal watchdog and testing routines 3 2 2 2 Relay Output PCBs US amp S provides three different relay output PC3s for the MICROLOK PLUS non vital section outputs Applicable PCBs are as follows PCB Name Part Number Operating Type Control Delivery N451441 3601 Pulsed Delivery Constant Delivery N451441 7101 Stick Relays Control and Delivery N451441 4701 Internal Strobe The 3601 PCB is the standard MICROLOK PLUS non vital output board The remaining boards are used for special applications 3 2 2 3 Optical Input PCBs US amp S provides two different optical input PCBs for the MICROLOK PLUS non vital section inputs Each is designed to handle different input voltage ranges and types Applicable PCBs are as follows Name Part Number Indication Opto N451441 5802 Indication Opto N451441 7202 The 7202 PCB is the standard MICROLOK PLUS non vital input board 6300A p 3 5 d voocr9o C sanbra JuoWabue1aV god SITJEZBI SAJA MOTOUDJIK VITAL SECTION PCBS CPU PART NO DESCRIPTION Na51441 570 PROCESSOR SLOT 845 1443 6001 VO BUS INTERFACE N45 1441 5302 CODE SYSTEM INTERFACE 145 1441 5502 PERIPHERAL vAF w INSTALLA HON PROCESSOR 10 BUS INTERFACE CODE SYSTEM INTERFACE
133. ts defined in a round robin polling scan The order of the address statements in the program not the address numbers represents the order in which Slave units will be polled The scan time of the Slave units varies based on the total system configuration This includes baud rate and number of defined Slave units The Master unit delivers an output bit to each Slave when the output bit changes value Note that the connection from a Master port is always made to a correspondingly programmed set of Slave ports All addresses defined under the MASTER interface section must be in the range of 1 255 0 is not valid Each address must also be unique 6300A p 4 14 2 Slave Port The Slave interface on the GENISYS or MICROLOK PLUS unit is desianed to communicate with only one such protocol Master unit In the SLAVE section of the program only one ADDRESS OUTPUT INPUT group may be specified Each unit can only be a Slave to one Master unit but can be a Master to more than one Slave units Each Slave port only responds to its one proper address Therefore only one ADDRESS group is permitted When defining the Slave port address in the software use a number other than zero Otherwise set this value to zero and select the address with switch 5 of the Controller board refer also to section 8 4 As with the other INTERFACE sections all output bits must be specified before any input bits 3 Master Slave Programming Example See Figure
134. tware design revisions affect both systems 1 2 FAMILY OF MANUALS This manual is one of eight manuals that cover the GENISYS Non Vital Logic Emulator the MICROLOK Vital Interlocking Control System and or the MICROLOK PLUS Vital Non Vital Control Package The following table summarizes these manuals SM No System s Covered Purpose 6300A GENISYS MICROLOK PLUS Both Systems Programming of Non Vital Application Logic 63008 GENISYS MICROLOK PLUS GENISYS Hardware Installation Local and Serial Data Interfacing Field Troubleshoot ing MICROLOK PLUS Local Serial Data Interfacing and Field Troubleshooting of Non Vital Section refer to SM 64008B for MICROLOK PLUS hardware installation 6300c GENISYS MICROLOK PLUS Both Systems Shop Troubleshooting af Non Vital Printed Circuit Boards 6301 GENISYS MICROLOK PLUS Both Systems Installation of GENISYS Development System G D S Hard and Dual Floppy Disks 6400A MICROLOK MICROLOK PLUS Both Systems Programming of Vital Application Logic 6400B MICROLOK MICROLOK PLUS MICROLOK Hardware Installation Power and Data Interfacing MICROLOK PLUS Hardware Installation Power Interfacing Data Interfacing af Vital Section refer to SM 63008 for non vital data interfacing 6300A 1 1 SM No Svstem s Covered Purpose 6400C MICROLOK MICROLOK PLUS MICROLOK Field Troubleshooting MICROLOK PLUS Field Troubleshooting of Vital Section 6401 MICROLOK MICROLOK PLUS Both
135. watchdog and testing routines 2 2 2 2 Relay Output PCBs USSS provides three different relay output PCBs for the output group of the GENISYS cardfile see Figure 2 2 The cardfile need not contain any relay output PCBs or may contain these PCBs in all cardfile slots maximum af 16 Applicable PCBs are as follows PCB Name Part Number Operating Type Control Delivery N451441 3601 Pulsed Delivery Constant Delivery N451441 7101 Stick Relays Control and Delivery N451441 4701 Internal Strobe The 3601 PCB is the standard GENISYS output board The remaining boards are used for special applications 2 2 2 3 Optical Input PCBs US amp S provides two different optical input PCBs for the input group of the GENISYS cardfile see Figure 2 2 Each is designed to handle different input voltage ranges and types The cardfile need not contain any optical input PCBs or may contain these PCBs in all cardfile slots maximum of 15 Applicable PCBs are as follows Name Part Number Indicat ion Opto N451441 5802 Indication Dpto N451441 7202 The 7202 PCB is the standard GENISYS input board 2 2 2 4 Power Supply Converter PC3s US amp S provides two power supoly converter PCBs for GENISYS which output operating power for other cardfile PCBs and power for the carrier modem interface 12 Vdc when required by application These are as follows Part Number Input Voltage N451441 7601 9 5 to 35 Vde N451441 4601 120 Vac nom 6300A D 2 5 t
136. yte become valid the LOCAL word is delivered to the actual outputs or it becomes available to the serial line However the bits cannot be delivered until they have received a valid value as the result of successfully resolving an ASSIGN statement 6300A p 4 23 NOTE The following statement applies to GENISYS Development System Versions 1 02 and higher In Versions 1 00 and 1 01 the indicated Boolean identities would not be evaluated The following Boolean identities will be evaluated even if x has an invalid value 1 oR x 1 0 AND x 0 In these identities the value of x is irrelevant 1 ORed with anything is a l and 0 ANDed with anything is a 0 4 2 6 Relay Models and Programming Techniques Figure 4 4 provides sample relay circuits for GENISYS and MICROLOK PLUS non vital programming models The flasher relay set up could not exist in actual relay logic but is possible in GENISYS or MICROLOK PLUS by establishing a distinct pick up drop away interval for the relay The pertinent parts of the program include TI SET 1 SEC CLEAR 1 SEC ASSIGN NOT TI TO TI ASSIGN NOT Ti TO Ti SB SOFTWARE BATTERY SN SOFTWARE NEGATIVE ASSIGN IN 1 AND NOT CANCEL TO IN 1 SERIAL INPUT CONTROL CASCADING TIMERS X SECOND DELAY se pr ji su X SECOND DELAY m T2 SN Ouri sw NET DELAY X X AT OUT oO Figure 4 4 Conceptual Relay Models for GENISYS and MICROLOK PLUS Programming 6300A p

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