EETS4K Block User Guide V02.07
Contents
1. rt leg Use Access _00 EEPROM Clock Divider Register ECLKDIV R W _01 RESERVED1 R _02 RESERVED2 R _03 EEPROM Configuration Register ECNFG R W S 04 EEPROM Protection Register EPROT R W S 05 EEPROM Status Register ESTAT R W _06 EEPROM Command Register ECMD R W _07 RESERVED3 R S 08 EEPROM High Address Register EADDRHI R W _09 EEPROM Low Address Register EADDRLO R W _0A EEPROM High Data Register EDATAHI R W _0B EEPROM Low Data Register EDATALO R W NOTES 1 Intended for factory test purposes only NOTE Register Address Register Base Address 110 Address Offset where the Register Base Address is defined by the HCS12 Core INITRG register and the Address Offset is defined by the EEPROM module O MOTOROLA For More Information On This Product Go to www freescale com 15 EETS4K Block User Guide vid 42 e scale Semiconductor Inc 3 3 Register Descriptions 3 3 1 ECLKDIV EEPROM Clock Divider Register The ECLKDIV register is used to control timed events in program and erase algorithms Register address BASE 110 7 6 5 4 3 2 1 0 EDIVLD prpive EDIV5 EDIv4 EDIV3 EDIV2 EDIV1 EDIVO RESET 0 0 0 0 0 0 E 9 Unimplemented or Reserved Figure 3 2 EEPROM Clock Divider Register ECLKDIV All bits in the ECLKDIV register are readable bits 6 0 are write once and bit 7 is not writable EDIVLD Clock Divider Loaded 1 Register has been written to si2. Program and erase functions are controlled by a command driven interface Both sector erase and mass erase of the entire EEPROM memory are supported An erased bit reads 1 and a programmed bit reads O The high voltage required to program and erase is generated internally by on chip charge pumps It is not possible to read from the EEPROM memory while it is being erased or programmed The EEPROM memory is ideal for data storage for single supply applications allowing for field reprogramming without requiring external programming voltage sources WARNING A word must be erased before being programmed Cumulative programming of bits within a word is not allowed 1 1 1 Glossary Command Sequence A three step MCU instruction sequence to program erase or erase verify the EEPROM 1 2 Features e 4K bytes of EEPROM memory e Minimum erase sector of 4 bytes e Automated program and erase algorithms e Interrupts on EEPROM command completion and command buffer empty e Fast sector erase and word program operation e 2 stage command pipeline e Flexible protection scheme for protection against accidental program or erase e Single power supply program and erase M MOTOROLA 9 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid f e scale Semiconductor Inc 1 3 Modes of Operation e Program and erase operation please refer to 4 1 for details 1 4 Block Diagram Figur
3. A protection violation has occurred 0 No failure ACCERR EEPROM Access Error The ACCERR flag indicates an illegal access to the selected EEPROM array see 4 1 4 Illegal EEPROM Operations This can be either a violation of the command sequence issuing an illegal command illegal combination of the CMDBx bits in the ECMD register or the execution of a CPU STOP instruction while a command is executing CCIF 0 The ACCERR flag is cleared by writing a 1 to ACCERR Writing a O to the ACCERR flag has no effect on ACCERR While ACCERR is set it is not possible to launch another command in the EEPROM 1 Access error has occurred 0 No failure BLANK Array has been verified as erased The BLANK flag indicates that an erase verify command has checked the EEPROM array and found it to be erased The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command sequence Writing to the BLANK flag has no effect on BLANK 1 EEPROM array verifies as erased 0 If an erase verify command has been requested and the CCIF flag is set then a zero in BLANK indicates array is not erased 20 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor WGs s12eersakv2 D vo2 07 3 3 7 ECMD EEPROM Command Register The ECMD register defines the EEPROM commands Register address BASE 116 7 6 5 4 3 2 1 0 CMDB6 CMDB5 9 5 CMD
4. 5 1 General A O coat Section 6 Interrupts OA General sats er een ON 6 2 Description of Interrupt Operation cee eee eee For More Information On This Product Go to www freescale com O MOTOROLA Freescale Semiconductor ING si2cetsakv2 vo2 07 List of Figures Figure 1 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 4 1 Figure 4 2 O MOTOROLA Module Block Diagram cherie nears Se eae aha hE ere oe kas Naa 10 EEPROM Memory Mapeo rss notado de rider 14 EEPROM Clock Divider Register ECLKDIV eee 16 RESERVED a eae MA wee weed AA EA Re ae eas 16 RESERVED 2st ices Apes ke ea we o w Role CBAC tea Ohi 17 EEPROM Configuration Register ECNFG o 17 EEPROM Protection Register EPROT oooocccocccccccc eee 18 EEPROM Status Register ESTAN ic apk RA lr pia tasca 19 EEPROM Command Register ECD eee eee 21 RESERVEDS 40 kA NANG Gd dl Ge Geiss NUN on mee ee 21 EEPROM Address High Register EADDRHI 0 ee 22 EEPROM Address Low Register EADDRLO 0002000 eee 22 EEPROM Data High Register EDATAHI 2000 ee eee eee 22 EEPROM Data Low Register EDATALO 000 0c eee eee 23 PRDIV8 and EDIV bits Determination Procedure aana aa eanan 27 Example Program Algorithm but as is sana 29 5 For More Information On This Product Go to www fr
5. algorithms are controlled by a state machine whose timebase EECLK is derived from the oscillator clock via a programmable divider The command register as well as the associated address and data registers operate as a buffer and a register 2 stage FIFO so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress The pipelined operation allows a simplification of command launching Buffer empty as well as command completion are signalled by flags in the EEPROM status register Interrupts for the EEPROM will be generated if enabled The next four subsections describe e How to write the ECLKDIV register e The write sequences used to program and erase the EEPROM but also to perform more sophisticated commands like sector modify and erase verify e Valid EEPROM commands Errors resulting from illegal EEPROM operations 4 1 1 Writing the ECLKDIV Register Prior to issuing any program or erase command it is first necessary to write the ECLKDIV register to divide the oscillator down to within 150kHz to 200kHz range The program and erase timings are also a function of the bus clock such that the ECLKDIV determination must take this information into account If we define e FECLK as the clock of the EEPROM timing control block e Tbus as the period of the bus clock e INT x as taking the integer part of x e g INT 4 323 4 then ECLKDIV register bits PRDIV8 and
6. v02 07 START PROGRAM ERASE IMPOSSIBLE PRDIV8 0 reset oscillator clock no gt 12 8MHz PRDIV8 1 PRDCLK oscillator clock 8 PRDCLK oscillator clock PRDCLK MHz 5 Tbus us no an integer A EDIV S 0 INT PRDCLK MAHz 5 Tbus us EDIV 5 0 PRDCLK MHz 5 Tbus us 1 TRY TO DECREASE Tbus EECLK PRDCLK 1 EDIV 5 0 1 EECLK MHz Tbus us gt 5 AND EECLK 2 0 15MHz EDIV 5 0 gt 4 PROGRAM ERASE IMPOSSIBLE Figure 4 1 PRDIV8 and EDIV bits Determination Procedure O MOTOROLA 27 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid f e scale Semiconductor Inc 4 1 2 Program and Erase A Command State Machine is used to supervise the write sequencing for program and erase More specialized commands like sector modify or erase verify follow the same flow Before starting a command sequence it is necessary to check that there is no pending access error or protection violation the ACCERR and PVIOL flags should be cleared in the ESTAT register After this initial step the CBEIF flag should be tested to ensure that the address data and command buffers are empty If so the command sequence can be started The following 3 step command write sequence must be strictly adhered to and no intermediate access to the EEPROM array is permitted between the 3 steps It is possible to read any EEPROM regist
7. 9 0 Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 5 EEPROM Configuration Register ECNFG CBEIE and CCIE are readable and writable Bits 5 0 read zero and are not writable CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the EEPROM 1 An interrupt will be requested whenever the CBEIF flag Figure 3 7 is set 0 Command Buffer Empty interrupts disabled CCIE Command Complete Interrupt Enable The CCIE bit enables the interrupts in case of all commands being completed in the EEPROM 1 An interrupt will be requested whenever the CCIF Figure 3 7 flag is set 0 Command Complete interrupts disabled M MOTOROLA 17 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid 42 e scale Semiconductor Inc 3 3 5 EPROT EEPROM Protection Register The EPROT register defines which EEPROM sectors are protected against program or erase Register address BASE 114 7 6 5 4 3 2 1 0 R eporen MY ne NG EPDIS EP2 EP1 EPO Reset F F F F F F F F Unimplemented or Reserved Figure 3 6 EEPROM Protection Register EPROT The EPROT register is loaded from EEPROM array address _FFD during reset as indicated by the F in Figure 3 6 All bits in the EPROT register are readable Bits NV 6 4 are not writable The EPOPEN and EPDIS bits in the EPROT register can only be written to the pr
8. B2 o CMDBO Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 8 EEPROM Command Register ECMD Bits 7 4 3 and 1 read zero and are not writable Bits CMDB6 CMDB5 CMDB2 and CMDBO are readable and writable during a command sequence CMDB Valid normal mode commands are shown in Table 3 4 Any other command than those mentioned in Table 3 4 sets the ACCERR bit in the ESTAT register 3 3 6 Table 3 4 EEPROM Normal Mode Commands Command Meaning 05 Erase Verify 20 Word Program 40 Sector Erase 41 Mass Erase 60 Sector Modify 3 3 8 RESERVED3 This register is reserved for factory testing and is not accessible to the user Register address BASE 117 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 9 RESERVED3 All bits read zero and are not writable M MOTOROLA 21 For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 3 3 9 EADDR EEPROM Address Register EADDRHI and EADDRLO are the EEPROM address registers Register address Base 118 7 6 5 4 3 2 1 0 R 0 0 0 0 0 w EABHI Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 10 EEPROM Address High Register EADDRHI Register address Base 119 7 6 5 4 3 2 1 0 R w EABLO Reset 0 0 0 0 0 0 0 0 Figure 3 11 EEPROM Address Low Register EA
9. BEIE Bit empty All Commands are CCIF completed on EEPROM ESTAT register NOTE Vector addresses and their relative interrupt priority are determined at the MCU level 6 2 Description of Interrupt Operation For a detailed description of the register bits refer to the EEPROM Configuration register and EEPROM Status register sections respectively 3 3 4 and 3 3 6 35 O MOTOROLA For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 36 O MOTOROLA For More Information On This Product Go to www freescale com O MOTOROLA Freescale Semiconductor ING s12 ETS4kv2 D vo2 07 Block Guide End Sheet 37 For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc FINAL PAGE OF 38 PAGES 38 O MOTOROLA For More Information On This Product Go to www freescale com
10. DDRLO In normal modes all EADDRHI and EADDRLO bits read zero and are not writable In special modes all EADDRHI and EADDRLO bits are readable and writable except EADDRHI 7 3 which are not writable and always read zero For sector erase the MCU address bits AB 1 0 are ignored For mass erase any address within the block is valid to start the command 3 3 10 EDATA EEPROM Data Register EDATAHI and EDATALO are the EEPROM data registers Register address BASE 11A 7 6 5 4 3 2 1 0 R W EDHI Reset 0 0 0 0 0 0 0 0 Figure 3 12 EEPROM Data High Register EDATAHI 22 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING si2cetsakv2 vo2 07 Register address BASE 11B 7 6 5 4 3 2 1 0 R W EDLO Reset 0 0 0 0 0 0 0 0 Figure 3 13 EEPROM Data Low Register EDATALO In normal modes all EDATAHI and EDATALO bits read zero and are not writable In special modes all EDATAHI and EDATALO bits are readable and writable O MOTOROLA 23 For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 24 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12FETS4KV2D vo2 07 Section 4 Functional Description 4 1 Program and Erase Operation Write and read operations are both used for the program and erase algorithms described in this section These
11. EDIV 5 0 are to be set as described in Figure 4 1 For example if the oscillator clock is 950kH7 and the bus clock is 10MHz ECLKDIV bits EDIV 5 0 should be set to 4 binary 000100 and bit PRDIV8 set to 0 The resulting EECLK is then 190kHz As a result the EEPROM algorithm timings are increased over optimum target by 200 190 200 x 100 5 NOTE Command execution time will increase proportionally with the period of EECLK O MOTOROLA 25 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid f e scale Semiconductor Inc WARNING Because of the impact of clock synchronization on the accuracy of the functional timings programming or erasing the EEPROM cannot be performed if the bus clock runs at less than 1 MHz Programming the EEPROM with an oscillator clock lt 150kHz should be avoided Setting ECLKDIV to a value such that EECLK lt 150kHz can reduce the lifetime of the EEPROM due to overstress Setting ECLKDIV to a value such that 1 EECLK Tbus lt 5s can result in incomplete programming or erasure of the memory array cells If the ECLKDIV register is written the bit EDIVLD is set automatically If this bit is zero the register has not been written since the last reset Program and erase commands will not be executed if this register has not been written to 26 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETS4KV2D
12. Field _FFO FFC 1 Reserved 3 FFD 1 EEPROM Protection byte _FFE _FFF 2 Reserved The EEPROM module has hardware interlocks which protect data from accidental corruption A protected sector is located at the higher address end of the EEPROM array just below address _FFF The protected sector in the EEPROM array can be sized from 64 bytes to 512 bytes In addition the EPOPEN bit in the EPROT register see section 3 3 5 can globally protect the entire EEPROM array NOTE Chip security is defined at the MCU level O MOTOROLA 13 For More Information On This Product Go to www freescale com EETS4K Block User Guide vos 42 escale Semiconductor Inc 12 bytes REGISTER BASE 110 7 EEPROM Registers REGISTER BASE _11B EEPROM BASE _000 3 5K bytes EEPROM Array _E00 _E40 _E80 _ECO FOO EEPROM Protected High Sectors al 64 128 192 256 320 384 448 512 bytes _F40 5 F80 _FCO EEPROM BASE FFF 107777 _FFO _ FFF EEPROM Protection Reserved Field Figure 3 1 EEPROM Memory Map 14 M MOTOROLA For More Information On This Product Go to www freescale com 110 to BASE 11B Freescale Semiconductor ING s12EETS4KV2D vo2 07 The EEPROM module also contains a set of 12 control and status registers located in address space BASE Table 3 2 gives an overview on all EETS4K registers Table 3 2 EEPROM Register Memory Map
13. Freescale Semiconductor Inc DOCUMENT NUMBER S12EETS4KV2 D EETS4K Block User Guide V02 07 Original Release Date 22 FEB 2001 Revised 8 APR 2003 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA For More Information On This Product Go to www freescale com EETS4K Block Use
14. IW A Oa a oes he A RET eco a aed pen LA Bes 11 Section 3 Memory Map and Registers Sl COVE os pedido DUDA Bie a di Ole eo amie oa e Bee 13 3 2 Module Memory Map sao ARA lo e EAN EA 13 3 3 Register Descriptions O 16 3 3 1 ECLKDIV EEPROM Clock Divider Register annua n anaana 16 3 3 2 RESERMEDT 19 7 A A aid gue SE ETA cas andre er eaten Ss 16 3 3 3 RESERVED un ar ocaso 17 3 3 4 ECNFG EEPROM Configuration Register ooo 17 3 3 5 EPROT EEPROM Protection Register a L 18 3 3 6 ESTAT EEPROM Status Register annaa aaa 19 3 3 7 ECMD EEPROM Command Register eee eee eee 21 3 3 8 PEGE SS upoan NG Ban AL BNG ngk tere o 21 3 3 9 EADDR EEPROM Address Register 0c eee eee eee 22 3 3 10 EDATA EEPROM Data Register a eee ie Ved LAR Ve 22 Section 4 Functional Description 4 1 Program and Erase Operation za baka sobrada Oh NATAL cee 25 4 1 1 Writing the ECEKDIV Register ii EA mire dae eee ge 25 4 1 2 Program and n x asocia oad Ge emer ee tee ees 28 4 1 3 Valid EEPROM Commande ote co ie bra ae td to eR ata RAS a 30 4 1 4 M dalEEPROM Operations ecc ot RRS Rae il 30 4 2 Y Wat Mode 2 ice O fete Barats Beis Dog nA Owe ara ee Reread gre eRe Se 31 K BO MOUS aaron Ea dra 31 3 O MOTOROLA For More Information On This Product Go to www freescale com EETS4K Block User Guide vid f escale Semiconductor Inc 4 4 Background Debug Mode eee eee eee Section 5 Resets
15. TOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETS4KV2D vo2 07 Table 3 3 EEPROM Address Range Protection Protected EP 2 0 Address Protected Size Range 000 FCO FFF 64 bytes 001 F80 FFF 128 bytes 010 F40 FFF 192 bytes 011 FOO FFF 256 bytes 100 ECO FFF 320 bytes E80 FFF 384 bytes 110 E40 FFF 448 bytes 111 E00 5 FFF 512 bytes NV 6 4 Non Volatile Flag Bits These three bits are available to the user as non volatile flags 3 3 6 ESTAT EEPROM Status Register The ESTAT register defines the EEPROM state machine command status and EEPROM array access protection and erase verify status Register address BASE 115 7 6 5 4 3 2 0 P CBEIF E PVIOL ACCERR S sia na MER y Reset 1 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 7 EEPROM Status Register ESTAT Register bits CBEIF PVIOL and ACCERR are readable and writable bits CCIF and BLANK are readable and not writable bits 3 1 and O read zero and are not writable CBEIF Command Buffer Empty Interrupt Flag The CBEIF flag indicates that the address data and command buffers are empty so that a new command sequence can be started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a O to CBEIF after writing an aligned word to the EEPROM addres
16. e 1 1 shows a block diagram of the EETS4K module Command EEPROM Array Interface 2048 16 Bits Command Pipeline raan Command comm2 comm1 omar Complete addr2 addr Interrupt data2 data1 Command Buffer Empty Interrupt Figure 1 1 Module Block Diagram 10 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Mgs si2cets4Kv2 D vo2 07 Section 2 External Signal Description 2 1 Overview The EETS4K module contains no signals that connect off chip O MOTOROLA 11 For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 12 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETS4KV2D vo2 07 Section 3 Memory Map and Registers 3 1 Overview This section describes the EETS4K memory map and registers 3 2 Module Memory Map Figure 3 1 shows the EETS4K memory map Location of the EEPROM array in the MCU memory map is defined in the specific MCU Device User Guide and is reflected in the INITEE register contents defined in the HCS12 Core User Guide Shown within the EEPROM array are a protection reserved field and user defined EEPROM protected sectors The 16 byte protection reserved field is located in the EEPROM array from address _FFO to _FFF A description of this protection reserved field is given in Table 3 1 Table 3 1 EEPROM Protection Reserved
17. eescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 6 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING si2cetsakv2 vo2 07 List of Tables Table 3 1 EEPROM Protection Reserved Field oo 13 Table 3 2 EEPROM Register Memory Map 0 000 e eee ee 15 Table 3 3 EEPROM Address Range Protection cee eee eee 19 Table 3 4 EEPROM Normal Mode Commande cece eee eee 21 Table 4 1 Valid EEPROM Commande 00 eee eee 30 Table 6 1 EEPROM Interrupt Sources 0 0000 cee ee 35 O MOTOROLA For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 8 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETS4KV2D vo2 07 Section 1 Introduction 1 1 Overview This document describes the EETS4K module which is a 4K byte EEPROM Non Volatile memory The EETS4K block uses a small sector Flash memory to emulate EEPROM functionality It is an array of electrically erasable and programmable non volatile memory The EEPROM memory is organized as 2048 rows of 2 bytes 1 word The EEPROM memory s erase sector size 1s 2 rows or 2 words 4 bytes The EEPROM memory may be read as either bytes aligned words or misaligned words Read access time is one bus cycle for byte and aligned word and two bus cycles for misaligned words
18. er during a command sequence The command sequence is as follows 1 Write the aligned data word to be programmed to the valid EEPROM address space The address and data will be stored in internal buffers For program all address bits are valid For erase the value of the data bytes is don t care For mass erase the address can be anywhere in the available address space of the array For sector erase the address bits 1 0 are ignored 2 Write the program or erase command to the command buffer These commands are listed in Table 4 1 3 Clear the CBEIF flag by writing a 1 to it to launch the command When the CBEIF flag is cleared the CCIF flag is cleared by hardware indicating that the command was successfully launched The CBEIF flag will be set again indicating the address data and command buffers are ready for a new command sequence to begin The completion of the command is indicated by the CCIF flag setting The CCIF flag only sets when all active and pending commands have been completed NOTE The Command State Machine will flag errors in program or erase write sequences by means of the ACCERR access error and PVIOL protection violation flags in the ESTAT register An erroneous command write sequence will abort and set the appropriate flag If set the user must clear the ACCERR or PVIOL flags before commencing another command write sequence By writing a 0 to the CBEIF flag the command sequence can be aborted after the word
19. f e scale Semiconductor Inc WARNING As active commands are immediately aborted when the MCU enters STOP mode it is strongly recommended that the user does not use the STOP command during program and erase execution 4 4 Background Debug Mode In Background Debug Mode BDM the EPROT register is writable If the chip is unsecured then all EEPROM commands listed in Table 4 1 can be executed In special single chip mode if the chip is secured then the only possible command to execute is mass erase 32 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING si2cetsakv2 vo2 07 Section 5 Resets 5 1 General If a reset occurs while any command is in progress that command will be immediately aborted The state of the word being programmed or the sector block being erased is not guaranteed 33 O MOTOROLA For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc 34 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETS4KV2D v02 07 Section 6 Interrupts 6 1 General The EETS4K block can generate an interrupt when all commands are completed or the address data and command buffers are empty Table 6 1 EEPROM Interrupt Sources Interrupt Source Interrupt Flag Local Enable rai EEPROM Address Data CBEIF and Command Buffers ESTAT register C
20. nce the last reset 0 Register has not been written PRDIV8 Enable Prescaler by 8 1 Enables a prescaler by 8 to divide the EEPROM module input oscillator clock before feeding into the CLKDIV divider 0 The input oscillator clock is directly fed into the ECLKDIV divider EDIV 5 0 Clock Divider Bits The combination of PRDIV8 and EDIV 5 0 effectively divides the EEPROM module input oscillator clock down to a frequency of 150kHz 200kHz The maximum divide ratio is 512 Please refer to section 4 1 1 for more information 3 3 2 RESERVED1 This register is reserved for factory testing and is not accessible to the user Register address BASE 111 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 3 RESERVED1 All bits read zero and are not writable 16 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductors Gs si2cetsakv2D vo2 07 3 3 3 RESERVED2 This register is reserved for factory testing and is not accessible to the user Register address BASE 112 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 4 RESERVED2 All bits read zero and are not writable 3 3 4 ECNFG EEPROM Configuration Register The ECNFG register enables the EEPROM interrupts Register address BASE 113 7 6 5 4 3 2 1 0 CBEIE CCIE 0 9 2
21. nd write sequence to immediately abort 1 Writing to the EEPROM address space before initializing ECLKDIV 2 Writing a misaligned word or a byte to the valid EEPROM address space 3 Writing to the EEPROM address space while CBEIF is not set 4 Writing a second word to the EEPROM address space before executing a program or erase command on the previously written word 5 Writing to any EEPROM register other than ECMD after writing a word to the EEPROM address space 6 Writing a second command to the ECMD register before executing the previously written 30 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING si2cetsakv2 vo2 07 command 7 Writing an invalid command to the ECMD register in normal mode 8 Writing to any EEPROM register other than ESTAT to clear CBEIF after writing to the command register ECMD 9 The part enters STOP mode and a program or erase command is in progress The command is aborted and any pending command is killed 10 A 0 is written to the CBEIF bit in the ESTAT register The ACCERR flag will not be set if any EEPROM register is read during the command sequence If the EEPROM array is read during execution of an algorithm i e CCIF bit in the ESTAT register is low the read will return non valid data and the ACCERR flag will not be set When an ACCERR flag is set in the ESTAT register the Command State Machine is locked It is n
22. ot possible to launch another command until the ACCERR flag is cleared The PVIOL flag will be set during the command write sequence after the word write to the EEPROM address space and the command sequence will be aborted if any of the following illegal operations are performed 1 Writing a EEPROM address to program in a protected area of the EEPROM 2 Writing a EEPROM address to erase in a protected area of the EEPROM 3 Writing the mass erase command to ECMD while any protection is enabled When the PVIOL flag is set in the ESTAT register the Command State Machine is locked It is not possible to launch another command until the PVIOL flag is cleared 4 2 Wait Mode When the MCU enters WAIT mode and if any command is active CCIF 0 that command and any pending command will be completed The EETS4K module can recover the MCU from WAIT if the interrupts are enabled see Section 6 4 3 Stop Mode If a command is active CCIF 0 when the MCU enters the STOP mode the command will be aborted and the data being programmed or erased is lost The high voltage circuitry to the EEPROM array will be switched off when entering STOP mode CCIF and ACCERR flags will be set Upon exit from STOP the CBEIF flag is set and any pending command will not be executed The ACCERR flag must be cleared before returning to normal operation M MOTOROLA 31 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid
23. otected state i e 0 The EP 2 0 bits can be written anytime until bit EPDIS is cleared If the EPOPEN bit is cleared then the state of the EPDIS and EP 2 0 bits is irrelevant To change the EEPROM protection that will be loaded on reset the upper sector of EEPROM must first be unprotected then the EEPROM Protect byte located at address _FFD must be written to A protected EEPROM sector is disabled by the EPDIS bit while the size of the protected sector is defined by the EP bits in the EPROT register Trying to alter any of the protected areas will result in a protect violation error and PVIOL flag will be set in the ESTAT register A mass erase of a whole EEPROM block is only possible when protection is fully disabled by setting the EPOPEN and EPDIS bits An attempt to mass erase an EEPROM block while protection is enabled will set the PVIOL flag in the ESTAT register EPOPEN Opens the EEPROM for program or erase 1 The EEPROM sectors not protected are enabled for program or erase 0 The whole EEPROM array is protected In this case the EPDIS and EP bits within the protection register are ignored EPDIS EEPROM Protection address range Disable The EPDIS bit determines whether there is a protected area in the space of the EEPROM address map 1 Protection disabled 0 Protection enabled EP 2 0 EEPROM Protection Address Size The EP 2 0 bits determine the size of the protected sector Refer to Table 3 3 18 O MO
24. r Guide vos escale Semiconductor Inc Revision History Version Revision Effective Description of Changes Number Date Date V01 00 22FEB01 15NOVOO Initial Version Do not set PVIOL for erase verify command if address written to is V02 00 22MAY01 27MARO1 in a protected area Allow data writes of 00 and 40 to ECLKDIV Make formats SRS V2 compliant V02 01 25MAYO01 Reorder and restructure document Add overview block diagram Add document names NA NAN Hide names and variable definitions V02 03 290CT01 O cc Cl Minor cleanup vo2 04 14MARO2 Modify document number Fix cross references Modify document number HI Rearrange Section 3 2 Module Memory Map V02 06 23JAN03 Add description of EADDR and EDATA registers Modify description of 3 3 5 EPROT EEPROM Protection Register to clarify mass erase restrictions Modify description of CBEIF and CCIF flags in 3 3 6 ESTAT EEPROM Status Register V02 07 08APR03 O MOTOROLA For More Information On This Product Go to www freescale com EETS4K Block User Guide vod GP e scale Semiconductor Inc Table of Contents Section 1 Introduction tI a oo Bite nae a a ose ae a een een en sean 9 1 1 1 RIO S A PA O O 9 la AFC 2 di taa 9 1 37 Modes of Operation tt ii II A AI ate ode ee NGA 10 Id Block Diagram e agape piaetaeredemed Cais NAA HATE soem Se NINA 10 Section 2 External Signal Description 2 1 CU GPV
25. s space but before CBEIF is cleared will abort a command sequence and cause M MOTOROLA 19 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid f e scale Semiconductor Inc the ACCERR flag in the ESTAT register to be set Writing a O to CBEIF outside of a command sequence will not set the ACCERR flag The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request 1 Buffers are ready to accept a new command U Buffers are full CCIF Command Complete Interrupt Flag The CCIF flag indicates that there are no more commands pending The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands The CCIF flag does not set when an active command completes and a pending command is fetched from the command buffer Writing to the CCIF flag has no effect The CCIF flag is used together with the CCIE bit in the ECNFG register to generate an interrupt request 1 All commands are completed 0 Command in progress PVIOL Protection Violation The PVIOL flag indicates an attempt was made to program or erase an address in a protected EEPROM memory area see 4 1 4 Illegal EEPROM Operations The PVIOL flag is cleared by writing a 1 to PVIOL Writing a 0 to the PVIOL flag has no effect on PVIOL While PVIOL is set it is not possible to launch another command in the EEPROM 1
26. valid EEPROM commands Also shown are the effects of the commands on the EEPROM array Table 4 1 Valid EEPROM Commands ECMD Meaning Function on EEPROM Array 05 Erase Verify all memory bytes of the EEPROM array are erased Verify If the array is erased the BLANK bit will set in the ESTAT register upon command completion 20 Program Program a word two bytes 40 maa Erase two words four bytes of EEPROM array 41 Mass Erase all of the EEPROM array Erase A mass erase of the full array is only possible when EPDIS and EPOPEN are set Sector Erase two words of EEPROM 60 Modify re program one word WARNING It is not permitted to program an EEPROM word without first erasing the sector in which that word resides The sector modify command executes a two step algorithm which first erases a sector 2 words of EEPROM array and then re programs one of the words in that sector The EEPROM sector which is erased by the sector modify command is the sector containing the address of the aligned array write which starts the valid command sequence That same address is re programmed with the data that was written By launching a sector modify command and then pipelining a program command it is possible to completely replace the contents of an EEPROM sector 4 1 4 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal operations are performed causing the comma
27. write to the EEPROM address space or after writing a command to the ECMD register and before the command is launched Writing a O to the CBEIF flag in this way will set the ACCERR flag A summary of the program algorithm is shown in Figure 4 2 For the erase algorithm the user writes either a mass erase or sector erase command to the ECMD register 28 O MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor ING s12EETS4KV2D vo2 07 Read Register ECLKDIV Clock Register Written Bit EDIVLD set Check Write Register ECLKDIV 4 Write Array Address and Program Data ta b NOTE command sequence Write Register ECMD e e Program Command 20 E AE 00 to ae a NOTE command sequence 3 Write Register ESTAT aborted by writing 00 to Clear bit CBEIF 80 ESTAT register Read Register ESTAT Protection yes Write Register ESTAT Violation Check Clear bit PVIOL 20 Access Error Check yes Write Register ESTAT Clear bit ACCERR 10 Address Data Command Buffer Empty Check Bit Polling for Command Completion Check Read Register ESTAT Figure 4 2 Example Program Algorithm M MOTOROLA 29 For More Information On This Product Go to www freescale com EETS4K Block User Guide vid f e scale Semiconductor Inc 4 1 3 Valid EEPROM Commands Table 4 1 summarizes the
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