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Chapter 2 Altera DE2

1. Figure 6 3 Block diagram of the TV PIP demonstration Demonstration Setup File Locations and Instructions Project directory DE2 70 TV PIP Bit stream used DE2 70 TV PIP sof or DE2 70 TV PIP pof Connect composite video output yellow plug of DVD player 1 and DVD player2 to the Video in 1 and Video in 2 RCA jack J8 and J9 of the DE2 70 board respectively Both DVD players must be configured to provide ME 4 7 886 3 5753170 o 60 Hz refresh rate Wk dr JJ Hk f Eg 86 21 54151736 HES JJ Ha eH 86 755 83298787 Http o 4 3 aspect ratio www 100y com tw o Non progressive video Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Connect the one audio output of the DVD player to the line in port of the DE2 70 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of 70 DE2 70 User Manual RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 70 board this 1s the same type of plug supported on most computers e Load the bit stream into FPGA e The detailed configuration for switching video source of main and sub window are listed in Table 6 1 Figure 6 4 illustrates the setup for this demonstration Mp 7 886 3 5753170 WE 7 H i 86 21 54151736 HER 7 i i 86755 88298787 Http www 100y com tw VGA Out Figure 6 4 The setup
2. 64 Bytes Data 4 Bytes Checksum Nios ll Interrupt Davicom CPU 4 DM9000A Read Data Ethernet 64 Bytes Data 4 Bytes Checksum 4 SN Figure 6 11 Packet sending and receiving using the Nios II processor Demonstration Setup File Locations and Instructions e Project directory DE2 70 NET e Bit stream used DE2 70 NET sof e Nios II Workspace DE2 70 NETNSoftware e Plug aCAT5 loop back cable into the Ethernet connector of DE2 70 e Load the bit stream into the FPGA Run the Nios ll IDE under the workspace DE2 70 NET e Click on the Compile and Run button e You should now be able to observe the contents of the packets received 64 byte packets sent 68 byte packets received because of the extra checksum bytes Figure 6 12 illustrates the setup for this demonstration Wed 7 886 3 5753170 Wy RF E 86 21 54151736 Wd JJ Hi UI 86 755 83298787 Http www 100y com tw 9 DE2 70 User Manual 10 100Mbps CAT 5 Cable R Loopback Device Ethernet Driver he 44 7 S 4 886 3 5753170 WE 5 JJ ETER 86 21 54151736 WEAR HL JI 86 755 83298787 Http www 100y com tw Figure 6 12 The setup for the Ethernet demonstration 6 5 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices so that good aud
3. 66 6 1 DE2 My Factory Codi burafiQIk M eeeeeeeeee lees ee e MM None eee eere 66 6 2 TV BoxB rmonsttratih A NA ee SAY LL rem ee M 67 6 3 TV Box Picture in Picture PIP Demonstration 69 6 4 NUSB Paintbgdeh Iesse INN QN Mere CNN 72 6 5 USB Device lt N N12 RENN LLL I 74 66 gt A Karaoke MachiyhN 2 CA 1 L N 76 6 7 Ethernet Packet Sendim g ReceivmAAN S u L NN T Qe Nose c e 78 6 8 SD Card Music Player yr GRIN peenes ne ccceeseng 80 6 9 Music Synthesizer Demonstration u s A 2 KL M p 83 Audio Recording and 4 1160 87 Chapter 7A Bperidix eee eee ee e eq le MMS IN Pete o o rro eee eonun oo roro oe eee 90 7 1 Reon History 1 0 2 A QUY gprs e NL NN esee ea 7 2 Copyright Statement 4 7 S L 886 3 5753170 EHETE 86 21 54151736 HES JJ Hi d GUI 86 755 83298787 Http www 100y com tw NBIS8 SYN DE2 70 User Manual Chapter 1 DE2 70 Package The DE2 70 package contains all components needed to use the DE2 70 board in conjunction wi
4. aaa hitp www altera com ter asic Target Memory WwW DET BAIC EO About SDRAM LI2 Download Code Disconnect Exit Connected Figure 3 6 Monitoring switches and buttons The ability to check the status of button and switch 15 not needed in typical design activities However it provides users a simple mechanism for verifying if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 34 SDRAM SSRAM Flash Controller and Programmer The Control Panel can be used to write read data to from the SDRAM SSRAM and FLASH chips on the DE2 70 board We will describe how the SDRAM U1 may be accessed the same approach is used to access the SDRAM U2 SRAM and FLASH Click on the Memory tab and select SDRAM UI to reach the window in Figure 3 7 Please note the target memory chosen for storing elf file 1s read only Also please erase the flash before writing data to it d H 886 3 5753170 86 21 54151736 WE 45 IT HLF 86 755 83298787 Http www 100y com tw 16 DE2 70 User Manual Control Panel VT LED 7 SEG LCD Button Memory USB P82 SD CARD Audio SDRAM U1 1000000h WORDS M Randam Access Address wDATA Deca DATA nooo Write Read sequential yrite Address pnnnon Length 1000000 File Length 7 aee i Write a File ta Memory
5. HS and VGA_VS to enable the display on a VGA 67 J 4 J HH 886 3 5753170 WERE 86 21 54151736 WE doe JJ EGE 86 755 83298787 Http www 100y com tw DE2 70 User Manual monitor spram TD_DATA iles Frame ecoder Data Valid Buffer Request Initiation LEE Delay DEN gt Timer DLY2 VGA VGA n p Controller HS DAC Decoder VGA Y VGA VS 7123 7180 TDHS s Locked To Control the ca e eye O TD_VS Initiation ce Detector Sequence S I2C SCLK YUV 4 2 2 YCbCr lt DC AV To Eze de Config YUV 4 4 4 RGB Figure 6 1 Block diagram of the TV box demonstration Demonstration Setup File Locations and Instructions Figure 6 2 illustrates the setup for this demonstration Project directory DE2_70_TV Bit stream used DE2_70_TV sof or DE2_70_TV pof Connect a DVD player s composite video output yellow plug to the Video IN 1 RCA jack J8 of the DE2 70 board The DVD player has to be configured to provide o NTSC output o 60 Hz refresh rate o 4 3 aspect ratio o Non progressive video Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Connect the audio output of the DVD player to the line in port of the DE2 70 board and conne
6. ALTERA pabi MEE TERASIC http www altera com ter Target Memory www Derasic com About SDRAM U2 Downoad Code Disconnect Exit Connected am b m Set LCD Success J Figure 3 5 Controlling LEDs and the LCD display The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 3 3 Switches and Buttons Choosing the Button tab leads to the window in Figure 3 6 The function is designed to monitor the status of switches and buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the switches and buttons Press the Start button to start button switch status monitoring process and button caption is changed from Start to Stop In the monitoring process the status of buttons and switches on the board is shown in the GUI window and updated in real time Press Stop to end the monitoring process We 44 7 HM 886 3 5753170 Wd JJ ETLER 86 21 54151736 15 WER 7 V EGEY 86 755 83298787 Http www 100y com tw DE2 70 User Manual Control Panel VT LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Buttan Switch Buttarnr m r ewitch NC Product Mame zm
7. N 2 ANN N AA 2 KAL 32 5 3 Usine they Seoment IO18plays N3 A M 37 u X K Lese go 36 5 4 QO CK CircuN8 2 a CSNN NN MQ Mele 1D Neuere A ecesees 38 5 5 Usine the LCI Module K INN e QUI n eee esee qu INN eee rene SN 40 5 06 Usinenthe Expansion Header x x NN A eor K A GS tes 4 5 7 LOIS TUA n S enr Et hM On t LO 45 5 8 Using the 2a Dit Audio UIDEC t Iesse C eese eene 48 5 9 RS 232 Serial POUt J NM 2 NI eee C CW5Y u 40 5 10 PS 2 Serial Port AUY Nee N Meer p CYNA 49 5 11 Fast Ethetmet Netwawb Controllec 73M N2 er ANMN a 5 50 Altera DE2 Board 5 127 TV NC QOL UTE S s CSS ANM ASI Tm 22 5 13 Nimplementine4 TV EncOk r N 1 MY N M 2 54 5 14 Wings USB Host and Devite N3 e AQUA E c I Leetsieeeeeeeeeeeeee creer 29 5 15 Ug IrDA a Meu ue CNN AM Teese QUM N 56 5 16 UsIm SDRAM SERANFlashasS 28 NS a QU AZ CNN 57 Chapter 6 Examples of Advanced Demonstrations
8. to the line out port For this demonstration the sample rate is set to 48 kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via the I2C bus cycling through one of the ten predefined gains volume levels provided by the device 34 7 S 4 886 3 5753170 WE 5 JJ Wa Ei 86 21 54151736 o WEE JJ Hi 86 755 83298787 Http www 100y com tw moo DE2 70 User Manual JN 5 RYA Audio line out Configuration Audio IS Push Button CODEC Ine m Auer Mic in ADC to DAC Figure 6 9 Block diagram of the Karaoke Machine demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 70 i2sound e Bit stream used DE2 70_i2sound sof or DE2 70 i2sound pof e Connect a microphone to the microphone in port pink color on the DE2 70 board e Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the DE2 70 board e Connect a headset speaker to the line out port green color on the DE2 70 board e Load the bit stream into the FPGA e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels 0 to 9 Figure 6 10 illustrates the setup for this demonstration We d 7 5 886 3 5753170 RF CES 86 21 54151736 HEJ E 86 755 83298787 Http www 100y com tw 77 DE2 70 User Manua
9. Each LED is driven directly by a pin on the Cyclone II FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches 15 given in Figure 5 4 A schematic diagram that shows the LED circuitry appears in Figure 5 5 A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches is given in Table 5 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 5 2 and 5 3 respectively RN33 100K OVCC33 KEYINO KEYN g ET AVY w Wlie KEYNS C13 C14 C15 C16 KEYO KEY1 KEY2 KEYS BUTTONO O 9 TACT SW BUTTON1 o Q O TACT SW BUTTON2 JOR O O TACT SW VCC33O 74HC245 swo SW1 SW2 SW3 sw4 W7 GND GND GND GND GND GND GND GND VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 Swi SW2 SW3 SW4 SW5 SW6 SW7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SW8 SW9 SW10 SW11 SW12 SW13 GND GND ND ND ND GND VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 swe SW9 SW10 Swit SW12 R50 120 SW13 GND GND GND GND GND GND GND GND GND GND GND GND SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SW14 SW15 SW16 SW17 4 GND GND GND GND VCC33 VCC33 VCC33 VCC33 N35 120 sxExI0 3l 8 LAWN SW17 GND GND GND GND infit SW16 SWIO 1
10. 15 D3 ELLOW D2 D1 GREEN RJ45INTLED 4 E ETA CHSGND N VCC33O D4 N VCC33O 0 1u 0 1 NGND NGND 120 SPEED R78 120 ACT Figure 5 17 DATA O ENET DATA 1 ENET_DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 ENET_DATAI7 DATA 8 ENET DATA 9 ENET DATA 10 ENET_DATA 11 ENET DATA 12 ENET DATA 13 ENET DATA 14 ENET DATA 15 PIN B23 PIN D27 PIN B27 ENET CLK ENET CMD WWW N VCC250 u 100y com tw NGND BC36 BC37 lOW Pas L2 BEAD IOR amp INT 34 RX En AQ bM EI Xa TX DM9000A 8 16bt H DM9000AE wo Qa D 0 LL x lt t a D e aa So Fast Ethernet schematic DM9000A DATA 15 DM9000A Clock 25 MHz DM9000A Command Data Select 0 Command 1 Data S 1 N_VCC33 O R72 ENET CS n N DE2 70 User Manual ENET RESET e ENET IOR n INT ENET CND lt ENET D8 ENET D9 ENET D10 ENET D11 ENET D12 ENET D13 ENET Di4 D15 ENET DO ENET 1 ENET D2 D3 ENET D4 ENET_D5 ENET D6 ENET D7 oN_VCC33 ON_VCC33 NDE o DE2 70 User Manual UI TA ENET CS N PIN C28 DM9000A Chip Select ENET INT PIN C27 DM9000A Interrupt ENET_IOR_N PIN_A28 DM9000A Read ENET_IOW_N PIN_B28 DM9000A Write ENET RESET N PIN B29 DM9000A Reset Table 5 15 Fast Ethernet pin assignments
11. 86 755 83298787 Http www 100y com tw e Bit stream used DE2 70 Synthesizer sof or DE2 70_Synthesizer pof e Connect a PS 2 Keyboard to the DE2 70 board e Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work e Connect the Lineout of the DE2 70 board to a speaker e Load the bit stream into FPGA e Make sure all the switches SW 9 0 are set to 0 Down Position e Press KEYI on the DE2 70 board to start the music demo e Press KEYO on the DE2 70 board to reset the circuit Table 6 2 and 6 3 illustrate the usage of the switches pushbuttons KEYs PS 2 Keyboard e Switches and Pushbuttons Reset Circuit KEY 1 Repeat the Demo Music SWI9 OFF DEMO ON PS2 KEYBOARD Channel 1 ON OFF SWI2 Channel 2 ON OFF Table 6 2 Usage of the switches pushbuttons KEYs SW O OFF BRASS ON STRING PS 2 Keyboard DE2 70 User Manual Table 6 3 Usage of the PS 2 Keyboard s keys F ZH 9 886 3 5753170 VERE ETLER 86 21 54151736 WER E Y JI 86 755 83298787 Http www 100y com tw Line Out Keyboard Input 4 7 7777772 o AS TE es aS z ae a ae a e SU Figure 6 16 The Setup of the Music Synthesizer Demonstration 86 4 J HM 886 3 5753170 WE JJ RF Ei 86 21 54151736 DE2 70 User Manual WEAF 7 HLF GR 86 755 83298787 Http www 100y com tw 6 10 Audio Rec
12. Each input output device is controlled by the NIOS II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The NIOS II interprets the commands sent from the PC and performs the corresponding actions BE jk 7 HM d 886 3 5753170 WE T JJ ETLE 86 21 54151736 MEJ E FRESI 86 755 83298787 Http www 100y com tw 23 DE2 70 User Manual SEG7 Controller T SEG Display SDRAM Controller SDRAM U1 Nios II USB Controller o gt USB Mouse PS2 Controller os PS2 Keyboard PIO Controller ira cx LED Button FPGA SOPC JTAG Blaster Hardware IULI Switch Seg7 SD Card Avalon MM Flash C A Tristate Bridge K gt Controller K Flash Nios II Avalon MM SSRAM Tri state Bridge K Controller ar usd NPROET AME 91118 1 1290919111 154 Figure 3 13 The block diagram of the DE2 70 control panel We oH J ML 3 886 3 5753170 WE 5 JJ ETLER 86 21 54151736 WEE JJ HA Q3 86 755 83298787 Http www 100y com tw 24 V Bo DE2 70 User Manual S RYA Chapter 4 DE2 70 Video Utility The DE2 70 board comes with a video utility that allows users to access video components on the board from a host computer The host computer communicates with the board through the USB Blaster link The facility can be used to verify the functionality of video components on the board capture the video sent from the vide
13. O Figure 5 23 lt FLASH D 0 14 Essay FLASH A 0 21 SSRAM schematic F VCC33 FLASH AO FLASH A1 z aw IM FLASH A2 FLASH A3 4 FLASH DO FLASH A4 FLASH D1 FLASH A5 FLASH D2 FLASH A6 11 FLASH D3 FLASH A7 44 FLASH D4 FLASH A8 0 Ac ZFLASEIRD5 FLASH A9 s A amp WFIYASH D6 FLASH A10 o o FLASH D7 FLASH gt FLASH D8 FLASH A12 a FLASH D9 FLASH A13 40 FLASH D10 FLASH A14 2 DQ10 745 FLASH D11 FLASH A15 DQ11 FLASH D12 FLASH A16 DQ12 7 FLASH D13 FLASH A17 DQ13 FLASH D14 FLASH A18 DQ14 FLASH D15 A i FLASH A19 DQ15 A 1 FLASH A20 FLASH A21 FLASH 8Mx8 FLASH WE n 27 Nea 30 2 VSS 52 F VCC33 R32 4 7K FLASH RY R33 4 7K FLASH CE Figure 5 24 Flash schematic 59 lt gt DE2 70 User Manual INDIE SYAN DE2 70 User Manual 0 Me 4 7 d 886 3 5753170 WEE JJ HE 86 21 54151736 WEE JJ Hi d GUI 86 755 83298787 Http www 100y com tw DE2 70 User Manual DRAMO CKE PIN AA8 SDRAM 1 Clock Enable 1 M F 72 48886 3 5753170 WF JJ LEM 86 21 54151736 BEEF JJ Hk GUI 86 755 83298787 Http www 100y com tw INDIE YAN DE2 70 User Manual DRAM1 RAS N PIN N9 SDRAM 2 Row Address Strobe DRAM1 CAS N PIN N8 SDRAM 2 Column Address Strobe DRAM1 CKE PIN L10 SDRAM 2 Clock Enable DRAM1 CLK PIN G5 SDRAM 2 Clock DRAM1 WE N PIN M9 SDRAM 2 Write Enable DRAM1 CS N PIN P9 SDRAM 2 Chip Select Tab
14. PS2 amp RS 232 Ports DPDT Switches 18 Push Button Switches 4 20 0 SDRAM 64 Mbyte SRAM 2 Mbyte 7 SEG Display 8 Expansion Headers 2 EPCS16 USB Config Blaster Dev Figure 2 2 Block diagram of the DE2 70 board Following is more detailed Information about the blocks in Figure 2 2 Cyclone II 2C70 FPGA 68 416 LEs e 250 M4K RAM blocks Wide JJ HA GE HI 86 755 83298787 1 152 000 total RAM bits Http www 100y com tw e 150 embedded multipliers e 4PLLs e 622 user I O pins e FineLine BGA 896 pin package he 44 o4 4 4 886 3 5753170 WE JJ HL 86 21 54151736 Serial Configuration device and USB Blaster circuit Altera s EPCS16 Serial Configuration device e On board USB Blaster for programming and user API control JTAG and AS programming modes are supported V Bodh DE2 70 User Manual JAN O fs RYA SSRAM 2 Mbyte standard synchronous SRAM e Organized as 512K x 36 bits e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel SDRAM e Two 32 Mbyte Single Data Rate Synchronous Dynamic RAM memory chips e Organized as 4M x 16 bits x 4 banks e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel Flash memory 8 Mbyte NOR Flash memory e Support both byte and word mode access e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel SD card socket e Provides SPI and 1 bit SD mode for SD Card access e Accessible as m
15. Position Controller and VGA_Multiplexer The Composite 10 VGA block consists all of the function blocks in the TV box demonstration project 69 DE2 70 User Manual described in the section 6 2 The Composite to VGA block takes the video signals from the TV decoders as input and generate VGA interfaced signals as output The circuit in the FPGA is equipped with two Composite 10 VGA blocks converting the video signals from the TV decoder 1 and TV decoder 2 respectively To display two video signals in PIP mode on the LCD CRT monitor the output VGA data rate of the Composite 10 VGA block for the sub window must be two times as fast as the rate of the Composite to VGA block for the main window In addition the output timing of the VGA interface signal from the Composite 10 VGA block is controlled by the pip position controller block that determines the stating poison of the sub window Finally both of the two VGA interfaced signals will be multiplexed and sent to the LCD CRT monitor via the VGA multiplexer block Video in 1 7 IN TD data VGA data Composite to TV decoder M rov PiP position Sub window TD clock Sub controller Control signal 54Mhz Em VGA data Sub VGA DAC Video in 2 TD clock id in1 27Mhz VGA l TV deas Ger 4 Composite_to_ data Main VGA multiplexer Main window TD data VGA Main window
16. 4 SDRAM SSRAM Flash Controller and Programmer 16 2 9 WS B Monitoring N M e 16 0 0 PSA DeYVice 5 e Pel esee eee p C NA 2 RN denne A CON 19 3 7 SD GAWIU D L A O A K Y L K AM SC 20 3 8 Audio Playing and Recording 4 QQV X2 A N N 1 L ASA m 21 5 9 Overall Structure of the DE2 70 Control Panel 23 Chapte amp yb DE2 70 Video Utility N3 4 amp A 2 1 eoa erue ee rosae 25 4 Wideo Utility S tup 7 T AT ON MS ccsssccasccessceessssesecceesge NIS eese 25 4 2 AQ Display LM N e 1 AMM A K 5 M ees 26 4 3 Vade Capture XX NM 28 8 1 40 QAR 32 u C A E ED Z 4 4 Overall Structure of the DE2 70 Video Utility 28 Chapter 5 Using the DE2470 Board NA e AM 7 tdeo eere eere ee rere 9 9 9 e oro eg fioe MM 30 5 1 Configiring theesjclore II e NN 30 5 2NN Using4leYPEDs ands Witches
17. 5 12 TV Decoder The DE2 70 board is equipped with two Analog Devices ADV7180 TV decoder chips The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal NTSC PAL and SECAM into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in both of the TV decoders can be programmed by a serial I2C bus which is connected to the Cyclone II FPGA as indicated in Figure 5 18 Note that the I2C address of the TV decoder 1 U11 and TV decoder 2 U12 are 0x40 and 0x42 respectively The pin assignments are listed in Table 5 16 Detailed information on the ADV7180 is available on the manufacturer s web site or in the Datasheet TV Decoder folder on the DE2 70 System CD ROM Wed 7 S 886 3 5753170 WERE HE 86 21 54151736 Wd E 86 755 83298787 Http www 100y com tw B2 DE2 70 User Manual V VCC33 E TD1 DIO 7 V VCC18 AV1_VCC18 PV1 VCC18 O 31 0 1u C30 R91 10n 1 74K 9 id RN44 47 0 AIN3 P0 AAA 16 TDL BO Y TD1 Di TD1 RESET n T d 4 TD1 D2 V pees P2 o WAAL TDT D3 VGND C27 0 1u Bs E FEE SA TD D4 C28 VW d TD1 D5 P5 78 z WAN a0 T1_D6 29 0 tu odu RUE 6 75 WAY Lg TDLD7 ADV7180 v 2
18. 70 User Manual Table 5 11 ADV7123 pin assignments 47 We od d 886 3 5753170 MERE ES 86 21 54151736 Wi 453 EERE 86 755 83298787 Http www 100y com tw NDE o DE2 70 User Manual Jionv4 5 8 Using the 24 bit Audio CODEC The DE2 70 board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC enCOder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry is shown in Figure 5 14 and the FPGA pin assignments are listed in Table 5 12 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s web site or in the Datasheet Audio CODEC folder on the DE2 70 System CD ROM J11 LINE IN VCC33 VCC33 R108 R109 N 2K 2K 1200 SDAT 126 SCLK SCLK R103 330 a a l S lt S r I2C ADDRESS READ IS 0x34 N d ic x C40 lt l2C ADDRESS WRITE IS 0x35 U13 I PHONE JACK P u R104 680 0 C41 10u V 1 o dd C42 R105 DAGND AGND OA_VCC33 n adii 6 J12 LINE OUT gt AGND AGND AGND EXPOSED DACDAT DACLRCK ADCDAT ADCLRCK HPVDD LHPOUT RHPOUT C43 AUD ADCLRCK lt gt O A VCC33 WAIN AGND AGND Figure 5 14 Audio CODEC schematic Table 5 12 Audio CODEC pin as
19. Board Ignore any warning messages produced during installation e The host computer should report that a Philips PDIUSBDI2 SMART Evaluation Board is now installed e Execute the software DE2 70 NIOS DEVICE LED SW ISP1362DcUsb exe on the host computer Then experiment with the software by clicking on the ADD and Clear buttons Figure 6 5 illustrates the setup for this demonstration We 7 3 4 886 3 5753170 75 PER J EPLER 86 21 54151736 Wd Jj EERE 86 755 83298787 Http www 100y com tw DE2 70 User Manual ISP1362 DeviceText Terasie DE2 z AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD ooooo0o0o0000000000000090 gt gt m gt gt gt gt x gt gt gt gt 2322222222222222222222 bhhhRhbhhhhbhhht hihi 555656 USB Driver Figure 6 8 The setup for the USB device demonstration 6 6 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DE2 70 board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode where the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 6 9 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in port 15 then mixed with the microphone in port and the result is sent
20. D17 DRAMO A2 DRAM D2 DRAMI A2 DRAM D18 DRAMO A3 x DRAM D3 DRAMI A3 DRAM D19 DRAMO A4 z 2 DRAM D4 DRAMI A4 z x DRAM D20 A5 DRAM D5 DRAMI A5 0 DRAM D21 DRAMO A6 DRAM D6 DRAMI A6 DRAM D22 DRAMO A7 DRAM D7 DRAMI A7 DRAM D23 DRAMO A8 DRAM D8 DRAM1_A8 DRAM D24 DRAMO A9 y DRAM D9 DRAMI A9 y DRAM D25 DRAMO A10 DRAM D10 DRAMI A10 DRAM D26 DRAMO DRAM D11 DRAMI A11 2 DRAM D27 DRAMO A12 3 au SDRAM 16Mx1 A AR DRAM D12 DRAMI A12 n SDRAM 16Mx1817 AB DRAM D28 DRAMO CLK a DRAM D13 DRAMI CLK a DRAM D2 3 CLK D13 gt ze 5 D13 X Ls DRAMO CKE DRAM D14 DRAMI CKE DRAM D30 CKE D14 D14 DRAMO LDQMO DRAM D15 DRAMI LDQMO DRAM D31 K v DRAMO UDQMT a2 LDQM D15 RAMI DOMT a D15 i gt UDQM gt DRAMO WE gt 0 n 6 nWE DRAM1 WE n G DRAMO CAS n DRAMI CAS n ATS L nCAS DRAMO RAS n 18 DRAMI RAS n 18 D nRAS 2 DRAMO CS n 49 DRAMI CS n 4o ncS gt DRAMO BAO 0 DRAMI BAO 27 DRAMO BA BAO 2 DRAMI BAT We BA1 I gt SDRAMO on veces SDRAM1 Ri 4 7K DRAMO WE n R7 47K DRAM1 WE n R2 ey DRAMO CAS R8 47K DRAM1 CAS n R3 4 7K DRAMO RAS n R9 47K DRAM1 RAS n R4 4 7K DRAMO CS n R1 4 7K DRAM1 CS n R5 4 7K DRAMO_CKE R1 4 7K CKE Figure 5 22 SDRAM schematic d 7 S 4 886 3 5753170 MER H ETUER 86 21 54151736 Wd 3 EERE 86 755 83298787 Http 58 www l00y com tw 34 7 4 4 886 3 5753170 EE k CE 86 21 54151736 Wi 453 EERE 86 75
21. KBDAT n PS2 MSCLK D9 BAT54S 40 VCC33 R49 120 iW Dra n W 1 T BUR A APORNINY PS2 KBCLK PS2 MSDAT aT WAY AWe DE2 70 User Manual VCC5 VCC5 VCC5 O Q Q R46 R47 R172 R173 2K 2K R48 120 D10 D95 D96 BAT54S BAT54S BAT54S b VCC33 VCC33 VCC33 Figure 5 16 PS 2 schematic PIN F24 PS 2 Clock PIN E24 PS 2 Data PIN D26 PS 2 Clock reserved for second PS 2 device PIN D25 PS 2 Data reserved for second PS 2 device Table 5 14 PS 2 pin assignments 5 11 Fast Ethernet Network Controller The DE2 70 board provides Ethernet support via the Davicom DM90004A Fast Ethernet controller chip The DM90004A includes a general processor interface 16 Kbytes SRAM a media access control MAC unit and a 10 100M PHY transceiver Figure 5 17 shows the schematic for the Fast Ethernet interface and the associated pin assignments are listed in Table 5 15 For detailed information on how to use the DM9000A refer to its datasheet and application note which are available on the manufacturer s web site or in the Datasheet Ethernet folder on the DE2 70 System CD ROM Wed 7 886 3 5753170 WE JJ RF E 86 21 54151736 WERE JJ Hi d GU 86 755 83298787 Http www 100y com tw 50 1 7 H EAE EF LE 5753170 54151736 886 3 iff 86 21 WEED ETRE 86 755 83298787 Http S ENET Df0
22. for the TV box PIP demonstration SW 17 OFF Signal display mode 71 NBre o DE2 70 User Manual Jionv SW 16 OFF SW 17 OFF Signal display mode Video in 1 SW 16 ON SW 17 ON Main window Video in 2 PIP display mode SW 16 OFF Sub window Video in 1 SW 17 ON Main window Video in 1 PIP display mode SW 16 ON Sub window Video in 2 Table 6 1 The setup for the TV box PIP demonstration 6 4 USB Paintbrush USB is a popular communication method used in many multimedia products The DE2 70 board provides a complete USB solution for both host and device applications In this demonstration we implement a Paintbrush application by using a USB mouse as the input device This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector We also implemented a video frame buffer with a VGA controller to perform the real time image storage and display Figure 6 5 shows the block diagram of the circuit which allows the user to draw lines on the VGA display screen using the USB mouse The VGA Controller block is integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor Once the program running on the Nios II processor is started it will detect the existence of the USB mouse connected to DE2 70 board Once the mouse is moved the Nios II processor is able to keep track of the movement and record it
23. i r OTG_D15 18 56 C48 C49 OTG D14 a VDD USCS 3 I USB A TYPE H oc2 4 p MP ot D12 H PSW2 35 dh A Du D11 H_DM2 COPY ehh ANNAN E VE O O D10 H DP2 AA D3 42 D8 H OCi 8 1 D7 H PSW1 5 m R114 R115 D6 OTG_DM1 a DS Orao 50 Fly 15K 15K D4 ISP1362 4g 4 7K ake DS A Df mie ak RR OO D2 OTGMODE D1 VBUS R111 Bep es 0 U_VCC330 Pa CP_CAP1 GOOD CS ar 39 R120 4 A 330 QU voces O WR GL VA 7 4 INT2 TEST2 so Ee NATU LEDB J INT1 TESTI R123 V v100K D87 D88 RESET TESTO U VCC33 BAT54S BAT54S DREQ2 CLKOUT 38 2 J ji OTG FSPEED R124 1 5K 3 OTG LSPEED R128 1 5K D D 3 111 BEAD O_VCC5 A 5 C52 C53 O 47p 47p OTG _DREQ1 OTG DACKi n 29 OTG DREQO 24 OTG DACKO n 28 USB B TYPE Bced O iu Figure 5 20 USB 19813262 host and device schematic OTG D 2 PIN G11 ISP1362 Data 2 OTG D 3 PIN F11 ISP1362 Data 3 he 4 7 3 4 886 3 5753170 WF JJ HR T Eg 86 21 54151736 WERE Hi d GU 86 755 83298787 Http www 100y com tw DE2 70 User Manual AVU S n VA OTG PIN J12 ISP1362 Data 4 Table 5 17 USB ISP1362 pin assignments 5 15 Using IrDA The DE2 70 board provides a simple wireless communication media using the Agilent HSDL 3201 low power infrared transceiver The datasheet for this
24. illustrates the AS configuration set up To download a configuration bit stream into the EPCS16 serial EEPROM device perform the following steps e Ensure that power is applied to the DE2 70 board e Connect the supplied USB cable to the USB Blaster port on the DE2 70 board see Figure 2 1 e Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the PROG position e The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG switch back to the RUN gl DE2 70 User Manual position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS16 device to be loaded into the FPGA chip USB Blaster Circuit PROG RUN Quartus Il AS Mode Programmer Config AS Mode PROG Auto J TAG Config Port Power on Config EPCS16 Serial Configuration Device Figure 5 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster port on the DE2 70 board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 5 2 Using the LEDs and Switches The DE2 70 board provides four pushbutton switches Each o
25. in a frame buffer memory The VGA Controller will overlap the data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display BE 4 7 886 3 5753170 WEE JJ ETLN 86 21 54151786 Wee 7 H GUI 86 755 83298787 Http www 100y com tw 72 moo DE2 70 User Manual JN OS RYA Philips ISP1362 USB Host Mouse Port Altera Niosll gt System CPU Interconnect Fabric VGA Controller lt ADV7123 Frame Buffer Figure 6 5 Block diagram of the USB paintbrush demonstration Demonstration Setup File Locations and Instructions Project directory DE2_70_NIOS_HOST_MOUSE_VGA Bit stream used DE2_70_NIOS_HOST_MOUSE_VGA sof Nios II Workspace DE2_70_NIOS_HOST_MOUSE_VGA Software e Connect a USB Mouse to the USB Host Connector type A of the DE2 70 board e Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA e Run the Nios II and choose DE2 70 NIOS HOST MOUSE VGA as the workspace Click on the Compile and Run button e You should now be able to observe a blue background with an Altera logo on the VGA display e Move the USB mouse and observe the corresponding movements of the cursor on the screen e Left click mouse to draw white dots lines and right click the mouse to draw blue d
26. 0 tutorials folder on the DE2 70 System CD ROM The user is encouraged to read the tutorial first and to treat the information below as a short reference The DE2 70 board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power 15 applied to the board Using the Quartus II software it 15 possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream 15 downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power 15 applied to the board the configuration 1s lost when the power 15 turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCSIO serial EEPROM chip It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DE2 70 board 15 turned off When the board s power 15 turned on the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both met
27. 3 5753170 MEJ k E 86 21 54151736 WERE HAGE 86 755 83298787 Http www 100y com tw We 3 7 oH 5 886 3 5753170 WE JJ RF Ei 86 21 54151736 89 70 User Mannal HAGE 86 755 83298787 Http www 100y com tw Chapter 2 Altera DE2 70 Board This chapter presents the features and design characteristics of the DE2 70 board 2 1 Layout and Components A photograph of the DE2 70 board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components Ethernet 10 100M Port USB Derita Pont Mic in Lineln Line Out VGA Out RS 232 Port USB Blaster Port USB Host Port Video In 1 In 2 1 TV Decoder NTSC PAL X2 12V DC Power Supply lt gt PS2 Port Connector T VGA 10 bit DAC Power ON OFF Switch LJEN Ethernet 10 100M Controller USB Host Slave ce z Controller if Audio CODEC tal f TLELE CELE LE LECCE Le Le ce oe lt i it a e i Tz s e ENS fh TESI 50Mhz Oscillator s 2 Altera USB Blaster Controller chipset Mau LITE TM i mm Expansion Header 2 IG L 31 a Altera EPCS16 Configuration Device Expansion Header 1 i E RUN PROG Switch for JTAG AS Modes ter CELLS SD Card Slot gt wew terosic con SD Card Not Included i an o e Pe Altera Cyclone 16x2 LCD Module F uus LJ eJ Red bid B mmm FPGA
28. 5 83298787 CS SBAM DQo st Http ps SRAM DPAJO 3 Y SRAM 0 18 SRAM BE n 0 3 SRAM addro SRAM data0 SRAM addri n A0 SRAM data SRAM addr2 a SRAM data SRAM _ addr3 4 SRAM data3 SRAM addr4 ko a SRAM data4 SRAM addr5 4 SRAM data5 SRAM addr6 A4 9 3 SRAM data6 SRAM addr7 An A6 z SRAM data7 SRAM addr8 A SRAM datapar SRAM addr9 a SRAM 4g 9 SRAM data8 SRAM addrii A10 SRAM data9 SRAM addr12 o A11 SRAM data10 SRAM _addri3 a4 SRAM datat1 SRAM addr14 Q A13 A SRAM data12 SRAM addri5 oo Al4 SRAM data13 SRAM addri6 100 a SRAM data14 SRAM addri7 43 416 O SRAM data15 SRAM addri8 2 30 SRAM datapari NC A19 9 SRAM data16 NC A20 SSRAM 512Kx36 SRAM data17 SRAM MODE 3 SRAM data18 SRAM ZZ a4 MOD IS61LPS51236A 200TQLI SRAM data19 SRAM outen n ae ZZ a SRAM data20 SRAM clock ag QE n SRAM data21 SRAM globalw n gg CLK SRAM data22 SRAM writeen n g7 SRAM data23 SRAM advance n aa PWE n SRAM datapar2 SRAM adsconttroler m Aes SRAM adsprocessor p4 SC_n a SRAM data24 SRAM chipeni n og ADSP_n SRAM data25 SRAM chipe o7 CEl_n SRAM data26 SRAM chipen3 n e CE2 SRAM data27 SRAM byteen 93 CES SRAM data28 SRAM byteen ni o4 A d SRAM data29 SRAM byteen n2 BWB_n SRAM data30 SRAM byteen n3 oe BWC_n SRAM data31 BWD n SRAM datapar3 www 100y com tw SR VCC33 SR VCC33 O O v Tb GG a CO O O
29. 5753170 ETLE 86 21 54151736 WERE HL JI 86 755 83298787 Http www 100y com tw 90
30. 7 GND GND GND GND si eA SW15 C SLIDE SW SLIDE SW SLIDE SW SLIDE SW XN We d 7 od 886 3 5753170 WE JJ ETIEN 86 21 54151736 WEE H gl 86 755 83298787 Http www 100y com tw We d M 8 886 3 5753170 Wk dr JJ ETLE 86 21 54151736 DE2 70 User Manual Wi 45 JJ Hi d GUI 86 755 83298787 Http www 100y com tw LEDR10 7A LEDR 330 8 LEDR11 LZ LEDR 5 LEDR12 IZ LEDR LEDR13 ZA LEDR t We d J oH d 886 3 5753170 end SA icon ETTEN 86 21 54151736 WEAF J HAE ee 86 755 83298787 Http www 100y com tw LEDR17 ZA LEDR Figure 5 5 Schematic diagram of the LEDs 34 N DTE SYN DE2 70 User Manual SW 16 PIN L7 Toggle Switch 16 SW 17 PIN L8 Toggle Switch 17 Table 5 1 Pin assignments for the toggle switches Table 5 2 Pin assignments for the pushbutton switches We d d 886 3 5753170 WEE JJ HA 86 21 54151736 Wi 453 EERE 86 755 83298787 Http www 100y com tw NBre o DE2 70 User Manual JionVv4 LEDG 7 PIN AA24 LED Green 7 LEDGI8 PIN AC14 LED Green 8 Table 5 3 Pin assignments for the LEDs 5 3 Using the 7 segment Displays The DE2 70 Board has eight 7 segment displays These displays are arranged into two pairs and a group of four with the intent of displaying numbers of various sizes As indicated in the schematic in Figure 5 6 the seven segments are connected to pins on the Cyclone II FPGA Applying a l
31. 8MHZ u XTAL VS FIELD 4 555 0 m VD XTAL1 HS US I2C ADDRESS IS 0x40 i Poteet V VGND V VCC33 v TD2 D 0 O O V VCC18 AV2 VCC18 PV2 VCC18 C D84 37 0 1u BAT54S SI C36 R96 10n 1 74K 0 1u O RN45 47 RCA JACK 0 LD 16 TD2 DO PO 8 WA 45 TD2 DI TD2 RESET n 10 3 le fA 4 TD2 D2 a P2 Pa a 1 ID2 D3 VGND C33 0 1u pas 2 TD2 D4 C34 TD2_D5 PSs WAN 40 12 DS C35 Lo 1ul_o 1u 6 5 8 WA TD D7 ADV7180 28MHZ VS FIELD 224 y S IDE VS S RAL 26 ADDRESS IS 0x42 y vcc33o l2C SCLK l2C SDAT Figure 5 18 TV Decoder schematic We oH 7 oH 4 886 3 5753170 WE JJ E 86 21 54151736 Wd JJ i 86 755 83298787 Http www 100y com tw e DE2 70 User Manual Jianv4 TD1 CLK27 PIN G15 TV Decoder 1 Clock Input Table 5 16 TV Decoder pin assignments 5 13 Implementing a TV Encoder Although the DE2 70 board does not include a TV encoder chip the ADV7123 10 bit high speed triple ADCs can be used to implement a professional quality TV encoder with the digital processing part implemented in the Cyclone II FPGA Figure 5 19 shows a block diagram of a TV encoder implemented in this manner TV Encoder Block Cyclone 2C70 O Composite Y U cos V sin Clock Calculate or Y S Video Timing Composite or RCA Y El U cos V sin SIN OrRCA Pb COS Tables Figure 5 19 ATV Encoder that uses th
32. Ei 86 21 54151736 EAE HERRI 86 755 83298787 Http www 100y com tw Figure 6 15 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAFF and TONE GENERATOR The DEMO SOUND block stores a demo sound for user to play PS2 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s are pressed The TONE GENERATOR 1s the core of music synthesizer SOC User can switch the music source either from PS2_KEYBOAD or the DEMO SOUND block using SW9 To repeat the demo sound users can press KEY 1 The TONE GENERATOR has two tones 1 String 2 Brass which can be controlled by SWO The audio codec used on the DE2 70 board has two channels which can be turned ON OFF using SW1 and SW2 Figure 6 17 illustrates the setup for this demonstration CYCLONE Il 2070 SN Wa SN HS DEMO1 CODE rau UND 2 CODE Lm o DAC VGGSS o VGAB SOUND1 CODE STAFF SOUND2 CODE L SOUND CODE SOUND2 PS2KB TONE AUDIO KEYBOARD KEY2_CODE sounD1_oFF GENERATOR CODEC SOUND2 OFF SW 9 SW 0 SW 2 1 Figure 6 17 Block diagram of the Music Synthesizer design Demonstration Setup File Locations and Instructions e Project directory DE2 70 Synthesizer 84 Wed J oH 4 886 3 5753170 NSS WERT ETLE 86 21 54151736 DE2 70 User Manual Wi 453 ETRE
33. G LCD Button Memory USB PS2 SD CARD Audio ab CARD SD CARD Identification Manufacturer OEM Applicatian ID 2D48h Praduct Name Product Revisian Dh Serlal No 00800595h Date Cade 075h SO CARD Specification CSD Version Mo 1 0 Fead Access Time 20 ms Product Name Fead Access Time NSACYT x100 cycle DE 70 Max Data Transfer Rate 25 Mbits s Max Read Data Block Length 512 Byte AN DTE RYA Memory Capacity 122 MB ti http www altera com Read ter asic Target Memory WWW LEFBSIE EGIT SDRAM U2 Download Code Disconnect Exit Connected SD CARD read success Figure 3 10 Reading the SD card Identification and Specification 3 8 Audio Playing and Recording This interesting audio tool is designed to control the audio chip on the DE2 70 board for audio playing and recording It can play audio stored in a given WAVE file record audio and save the audio signal as a wave file The WAVE file must be uncompressed stereo 2 channels per sample and 16 bits per channel Its sample rate must be either 96K 48K 44 1K 32K or 8K Follow the steps below to exercise this tool Choosing the Audio tab leads to the window in Figure 3 11 To play audio plug a headset or speaker to the LINE OUT port on the board Select the Play Audio item in the com box as shown in Figure 3 11 Click Open Wave to select a WAVE file The waveform of the specified wave
34. LED drive current e Integrated EMI shield EC825 1 Class 1 eye safe e Edge detection input Two 40 pin expansion headers 72 Cyclone II I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors e 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives e Diode and resistor protection is provided 2 3 Power up the DE2 70 Board The DE2 70 board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board 15 working properly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2 70 board For communication between the host and the DE2 70 board it is necessary to install the Altera USB Blaster driver software If this driver 1s not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DE2 70 Board This tutorial is available in the directory DE2 70 tutorials on the DE2 70 System CD ROM Connect the 12V adapter to the DE2 70 board Connect a VGA monitor to the VGA port on the DE2 70 board Connect your headset to the Line out audio port on the DE2 70 board Turn the RUN PROG switch on the left edge of the DE2 70 board to RUN position the PROG position is used only for the AS Mode programming 6 Turn the power on by pr
35. MEJ EFTER 86 21 54151736 DE2 70 User Manual Wd 7 HA 3 86 755 83298787 Http www 100y com tw 5 5 Using the LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller which 15 called HD44780 Detailed information for using the display is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet LCD folder on the DE2 70 System CD ROM A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure 5 9 The associated pin assignments appear in Table 5 6 Q1 8050 Q2 8550 E VCC430 680 LCD ON R35 680 Q3 ze SEN VCC43 Q4 8550 VCC430 R38 1K LCD DIJO 7 R36 680 E ool R39 ASAR LCD BLON R37 680 Q5 Q aiaaaaaaaa 47 EN gt 8050 IAN 1 e a O al DIS1 2 X 16 DIGIT LCD LCD 2x16 Figure 5 9 Schematic diagram of the LCD module LCD DATA O PIN LCD Data 0 LCD DATA 1 PIN E3 LCD Data 1 LCD DATA PIN D2 LCD Data 2 LCD DATA 3 PIN D3 LCD Data 3 LCD PIN C1 LCD Data 4 40 INDIE YAN DE2 70 User Manual LCD PIN C2 LCD Data 5 LCD RW LCD Read Write Select 0 Write 1 Read LCD EN LCD Enable LCD RS PIN F2 LCD Command Data Select 0 Command 1 Data LCD ON PIN F1 LCD Power ON OFF LCD BLON PIN G3 LCD Back Light ON OFF Table 5 6 Pin assignments for the LCD module Note t
36. Product Name DE2 70 sequential Read t Address jonnann Length 1000000 Entire Memory Load Memory Content to a File hitp www altera com ter asic Target Mernory WwW DET BAIC EO About SDRAM LI2 Download Code Disconnect Exit Connected SDRAM U1 Random Write Success he 44 7 B 886 3 5753170 HER 7 ETLER 86 21 54151736 ETRE 86 755 83298787 Figure 3 7 Accessing the SDRAM UI Http www 100y com tw A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 7 depicts the result of writing the hexadecimal value 6 into location 200 followed by reading the same location The Sequential Write function of the Control Panel 15 used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file 1s to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing of data click on the Write a File to Memory button When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files wi
37. R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCrCb to RGB and VGA Controller The figure also shows the TV Decoder ADV7180 and the VGA DAC ADV7123 chips used As soon as the bit stream 15 downloaded into the FPGA the register values of the TV Decoder chip are used to configure the TV decoder via the 26 AV Config block which uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector 1s responsible for detecting this instability The ITU R 656 Decoder block extracts YCrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder 15 interlaced we need to perform de interlacing on the data source We used the SDRAM Frame Buffer and a field selection multiplexer MU X which is controled by the VGA controller to perform the de interlacing operation Internally the VGA Controller generates data request and odd even selected signals to the SDRAM Frame Buffer and filed selection multiplexerr MU X The YUV422 to YUV444 block converts the selected YCrCb 4 2 2 YUV 4 2 2 video data to the YCrCb 4 4 4 YUV 4 4 4 video data format Finally the YCrCb to RGB block converts the YCrCb data into RGB output The VGA Controller block generates standard VGA sync signals
38. RAM UI will be uploaded to the host computer and displayed on the waveform window Click Save Wave to save the waveform into a WAV file he 44 7 S 886 3 5753170 WE t 86 21 54151736 Wd 3 He Hil 86 755 83298787 Http www 100y com tw 22 VETEREM DE2 70 User Manual ANU S RYA Control Panel 1 0 0 Talula lala tala AAA EE Product Mame DE 70 http www altera com Sample Rate 441K v SaveWave Star Record Gias c Target Memory _ WWW LEFBSIE EGIT About SDRAM U2 Download Code Disconnect Exit Connected Auiod record successfully Figure 3 12 Audio Recording and Saving as a WAV file To record audio sound from LINE IN port please connect an audio source to the LINE IN port on the board The operation is as same as recording audio from MIC 3 9 Overall Structure of the DE2 70 Control Panel The DE2 70 Control Panel is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM U2 or SSRAM The software part is implemented in C code the hardware part is implemented in Verilog code with SOPC builder which makes it possible for a knowledgeable user to change the functionality of the Control Panel The code is located inside the DE2 70 demonstrations directory on the DE2 System CD ROM To run the Control Panel users must first configure it as explained in Section 3 1 Figure 3 13 depicts the structure of the Control Panel
39. SD CARD socket SD 1 Bit Mode is used to access the SD card and is implemented by software All of the other SOPC components in the block diagram are SOPC Builder built in components 100 MHZ Phase 65 deg SSRAM Chip SDRAM Chip Audio Socket 50 MHZ 5 Audio Audio MIC In 3 Controller Chip Nt Line In L Line Out d o LCD dul TI t Seg 7 oe Device PLL ontrolle K a3sDCard Socket Figure 6 13 Block diagram of the SD music player demonstration Figure 6 14 shows the software stack of this demonstration SD 1 Bit Mod block implements the SD 1 bit mode protocol for reading raw data from the SD card The FAT16 block implements FATI6 file system for reading wave files that stored in the SD card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for receiving audio signal from wave files The I2C block implements I2C protocol for configuring audio chip The SEG7 block implements displaying function for display elapsed playing time The Audio block implements audio FIFO checking function and audio signal sending receiving function 81 4 7 886 3 5753170 7 ETLER 86 21 54151736 EREI 86 755 83298787 Http www 100y com tw NBTE DE2 70 User Manual FAT 16 SD 1 Bit Mode NIOS HAL Figure 6 14 Software Stack of the SD music player demonstration The audio chip should be configured be
40. The 87 moo DE2 70 User Manual JNO RYA hardware part 15 built by SOPC Builder under Quartus II The hardware part includes all the other blocks The AUDIO Controller is a user defined SOPC component It is designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip is programmed through I2C protocol which is implemented in C code The I2C pin from audio chip 1s connected to SOPC System Interconnect Fabric through PIO controllers In this example the audio chip is configured in Master Mode The audio interface is configured as I2S and 16 bit mode A 18 432MHz clock generated by the PLL is connected to the XTI MCLK pin of the audio chip through the AUDIO Controller 50M Hz Store CAM Audio RESE N SDRAM Data SRAM SRAM Nios II JT AG Contr oller Pro gram UART PIO lt LED KEY SW I2C LCD Controller LCD me to SDRAM SRAM Un un e 3 e e e 5 5 5 e SEG7 SEG7 Controller AUDIO K AUDIO Controller Figure 6 19 Block diagram of the audio recorder and player Demonstration Setup File Locations and Instructions e Hardware Project directory DE2 70 AUDIO e Bit stream used DE2P_TOP sof e Software Project directory DE2 70 AUDIONsoftwareNproject audio e Software Execution File DE2 70 AUDIONsoftwareNproject auidovaudioMlebug audio elf e Connect an Audio Source to the LINE IN port of the DE2 70 b
41. X2 2M 8M ITV SRAM LASH Decoder 68 416 LEs PGA User Development and Education Board Manual UNIVERSAL SERIAL BUS Version 1 01 Copyright 2007 Terasic Technologies We d 7 d 886 3 5753170 Altera DE2 Board Ha f Eg 86 21 54151736 EFJ FRESI 86 755 83298787 Http www 100y com tw Chapter 1 DE2 7 Packagecysa A GNS Sa 1 1 1 Packa Contents amp 5 AAN n eena a SNL l 1 2 The REANO Board ASSEMBLY er he NN net Gabel 1 2 1 3 Getung Help AN ANNE Lin t S MEAT Lo 3 Chapter 2 Altera DE2 70 Board A rere eee eere e epp Ne Meo eoe eoo o paie o ao Do o o ooo apr o onore nune eeu 4 2 Layout and o6mponeRfsC A lt lt N NNNM Ne eeaeee CSN 4 2 2 lt Block Diagnatinot the DEZ X0 Board xr SN e Seele e lt N 5 2 3 Power up the DER 70 QM NN enn CN esee ee Meses 9 Chapter 3 DE2 70 ControlNPanel S2 NN e 1 3 1 s amp ntrol Panek amp etllp mip AA INN anaana NN ee MN 11 A2 Controlling the LEDs 7 Segment Displays and LCD Display 13 3 3 Switches and Button Nx 2 00 I NN S o 15 3
42. age level setting of the expansion headers using JP1 Rt We d 4 4 886 3 5753170 Wd JJ ETUER 86 21 54151736 BEEF JJ HB EH 86 755 83298787 Http www 100y com tw DE2 70 User Manual 1 8V 2 5V 3 3V 2 4 6 We d J M 886 3 5753170 WE T JJ ETUER 86 21 54151736 WE JJ ri 86 755 83298787 989 Http www 100y com tw JP1 e e 1 3 5 Figure 5 10 pin settings VCCIO5 VCCIOS GPIO 0 J4 IO CLKINnO M 0 CLKINpO dede IO M BHL BAT54S BAT54S lO 6 ape 10 lO A7 ASW IO A9 GPIO DO R51 47 A0 SESS Lo 16 o GPIO Di K R52 V V VAT IO L E SENE fo o 18 D A13 ELA tO CLKOUTnO d 20 A14 CLKOUTp024 22 A15 lO A16 Lo o 1 24 IO A17 OA eote on protection registors and diodes IO A22 L o lO A23 not shown for other ports D A24 o o 34 OA O O O lO A28 38 lO A29 lO A30 5 c 40 IO A31 BOX Header 2X20M VCCIO5 VCCIO5 GPIO 1 J5 CLKINn1 lO BO IO CLKINp1 IO B1 BATS4S IO IO 6 86 m 6 87 9 GPIO D32 R60 47 BO O 9 B9 GPIO D33 R61 A47 IO B1 lO B10 M i 16 lO B11 O CONA Ha 5 CS at o o J 21 36 Bre O O 4 protection registors and diodes AE Co o 10 B19 O O VCC33 9 90 not shown for o
43. al clock source to the board In addition all these clock inputs are connected to the phase lock loops PLL clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit The clock distribution on the DE2 70 board is shown in Figure 5 8 The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 5 5 fie Fe 7 H 886 3 5753170 Re ES JJ CES 86 21 54151736 WE 53 Ha GUI 86 755 83298787 Http www 100y com tw Hs AR 7 886 3 5753170 DE2 70 User Manual We JJ Hi Egg 86 21 54151736 WEE 7 E FREI 86 755 83298787 Http www 100y com tw GPIO 0 GPIO 1 2 SD Card 2 2 SMA oy Connector AUDIO 74 gt CODEC 50 MHz 4 x Oscillator lt AA PS 2 Cyclone II 2 FPGA 28 MHz Oscillator TV decoder 1 Ethernet TV decoder 2 VGA DAC SSRAM FLASH Figure 5 8 Block diagram of the clock distribution CLK 28 PIN E16 28 MHz clock input CLK 50 PIN AD15 50 MHz clock input CLK 50 2 PIN D16 50 MHz clock input CLK 50 3 PIN R28 50 MHz clock input CLK 50 4 PIN R3 50 MHz clock input EXT CLOCK PIN R29 External SMA clock input Table 5 5 Pin assignments for the clock inputs 39 4 7 S 4 886 3 5753170 ova
44. ar 5 Select the target memory SDRAM U2 or SSRAM on the control panel Note The e f file will be downloaded to the target memory and the memory will be read only in later memory access operation 6 Click Download Code button Note the Control Panel will occupy the USB port until you di1 NH S SYN DE2 70 User Manual close that port you cannot use Quartus II to download a configuration file Into the FPGA until you close the USB port 7 The Control Panel is now ready for use experiment by setting the value of some LEDs display and observing the result on the DE2 70 board Control Panel JLEDG JLEDRB ILILEDG1 ILEDR JLEDG2 _ILEDR8 ILEDGS ILEDR8B ILILEDG4 ILEDR1D ILEDGS5 JLEDR11 L ILEDR12 ILILEDG JLEDR13 ILILEDGS _ILEDR14 ae x LILEDRO LILEDR15 Product Name ILEDR1 JLEDR16 2 LEDR17 IL iL EDRS3 LILEDR4 _ILEDRS http www altera com Light All Unlight All ter T M ENTE WWW DEPasic com About SDRAM AI2 Download Code Disconnect Exit Connected Download Cade success Figure 3 1 The DE2 70 Control Panel The concept of the DE2 70 Control Panel is illustrated in Figure 3 2 The Control Codes that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to issue
45. ard input receiving process Button caption is changed from Start to Stop 4 In the receiving process users can start to press the attached keyboard The input data will be displayed in the control window in real time Press Stop to terminate the monitoring process he d 7 M 4 886 3 5753170 ERE VR Egg 86 21 54151736 WEA 7 B FREI 86 755 83298787 Http www 100y com tw 19 NBIS8 SYN DE2 70 User Manual Control Panel V1 0 0 PS2 Keyboard Product Mame DE 70 http www altera com Tasic x WWW LET BAIG COM About SDRAM LI2 gt Iscannaect Exit Connected Figure 3 9 Reading the PS2 Keyboard 3 7 SDCARD The function is designed to read the identification and specification of the SD card The 1 bit SD MODE is used to access the SD card This function can be used to verify the functionality of SD CARD Interface Follow the steps below to exercise the SD card 1 Choosing the SD CARD tab leads to the window in Figure 3 10 First 2 Insert a SD card to the DE2 70 board then press the Read button to read the SD card The SD card s identification and specification will be displayed in the control window We d J oH 886 3 5753170 HER J ETLER 86 21 54151736 WEE II Hu PRRI 86 755 83298787 Http www 100y com tw 20 We 44 7 oH 4 886 3 5753170 WE ETLE 86 21 54151736 Y 83 86755 83298787 Http www 100y com tw LED 7 SE
46. commands to the control codes It handles all requests and performs data transfers between the computer and the DE2 70 board d J oH 4 886 3 5753170 86 21 54151736 WEE II i 86 755 83298787 Http www 100y com tw 12 DE2 70 User Manual Med 7 HH 886 3 5753170 7 SEG Display WEAR JJ VR F CES 86 21 54151736 TETTE HES JJ EERE 86 755 83298787 LL LCD MEM Http www 100y com tw USB Blaster Control Codes ix USB Device SD Card Soket LEDs Figure 3 2 The DE2 70 Control Panel concept The DE2 70 Control Panel can be used to light up LEDs change the values displayed on 7 segment and LCD displays monitor buttons switches status read write the SDRAM SSRAM and Flash Memory monitor the status of an USB mouse read data from a PS 2 keyboard and read SD CARD specification information The feature of reading writing a word or an entire file from to the Flash Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Memory Programmer 3 2 Controlling the LEDs 7 Segment Displays and LCD Display A simple function of the Control Panel 15 to allow setting the values displayed on LEDs 7 segment displays and the LCD character display Choosing the LED tab leads to the window in Figure 3 3 Here you can directly turn the individual LEDs on or off by selecting them or click Ligh
47. ct a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 70 board this is the same type of plug supported on most computers Load the bit stream into FPGA Press KEYO on the DE2 70 board to reset the circuit Wed 7 4d 886 3 5753170 Wd JETUE 86 21 54151736 68 WES JJ H q GUI 86 755 83298787 Http www 100y com tw 1 3F J M 886 3 5753170 IER J ETLER 86 21 54151736 S RA EERE 86 755 83298787 Http www 100y com tw Anl Line Out Line In CVBS S Video YPbPr Output VGA Out Audio Output Figure 6 2 The setup for the TV box demonstration 6 3 TV Box Picture in Picture PIP Demonstration The DE2 70 board has two TV decoders and RCA jacks that allow users to process two video sources simultaneously using the 2C70 FPGA This demonstration will multiplex two different video source signals from the TV decoders and display both video signals on the LCD CRT monitor using picture in picture mode PIP mode One picture 15 displayed on the full screen and the other picture 15 displayed in a small sub window Also users can select which video 15 displayed in main sub window via a toggle switch Figure 6 3 shows the basic block diagram of this demonstration There are three major blocks in the circuit called Composite to VGA PIP
48. device is provided in the DatasheetNMrDA folder on the DE2 70 System CD ROM Note that the highest transmission rate supported 15 115 2 Kbit s and both the TX and RX sides have to use the same transmission rate Figure 5 21 shows the schematic of the IrDA communication link Please refer to the following website for detailed information on how to send and receive data using the IrDA link http techtrain microchip com webseminars documents IrDA B W pdf We dE 7 8886 3 5753170 26 Hk f E 86 21 54151736 HEJ Hi 86 755 83298787 Http www 100y com tw DE2 70 User Manual AVU n VA Figure 5 21 IrDA schematic IRDA TXD PIN W 21 IRDA Transmitter IRDA RXD PIN W22 IRDA Receiver Table 5 18 IrDA pin assignments 5 16 Using SDRAM SRAM Flash The DE2 70 board provides a 2 Mbyte SSRAM 8 Mbyte Flash memory and two 32 Mbyte SDRAM chips Figures 5 22 5 23 and 5 24 show the schematics of the memory chips The pin assignments for each device are listed in Tables 5 19 5 20 and 5 21 The datasheets for the memory chips are provided in the Datasheet Memory folder on the DE2 70 System CD ROM Wed 7 4 L 886 3 5753170 WE JJ RF ES 86 21 54151736 Wd 86 755 83298787 Http www 100y com tw 57 DE2 70 User Manual x DRAM_DJ0 34 DRAMO A 0 12 DR VCC33 DR VCC33 DRAMI_AL 0 12 DRAMO A0 DRAM DO DRAM1_ AO DRAM D16 DRAMO A1 2 DRAM D1 DRAMI 7 DRAM
49. e Cyclone II FPGA and the ADV7123 his d J H886 3 5753170 54 WE JJ EPLE 86 21 54151736 WER HAGE 86 755 83298787 Http www 100y com tw V EBey DE2 70 User Manual S RYA 5 14 Using USB Host and Device The DE2 70 board provides both USB host and device interfaces using the Philips ISP1362 single chip USB controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at full speed 12 Mbit s and low speed 1 5 Mbit s Figure 5 20 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed 1n Table 5 17 Detailed information for using the ISP1362 device is available in its datasheet and programming guide both documents can be found on the manufacturer s web site or in the Datasheet USB folder on the DE2 70 System CD ROM The most challenging part of a USB application is in the design of the software driver needed Two complete examples of USB drivers for both host and device applications can be found in Sections 6 4 and 6 5 These demonstrations provide examples of software drivers for the Nios II processor U VCC33 iu OTG D 0 15 3 Ep U14 U VCC5 BAT54S BAT54S O FR SIG AT 62 1 SUSPEND H SUSWKUP 33 M L n A0 H SUSPEND D SUSWKUP 34 9
50. e Supports Composite Video CVBS RCA jack input e Supports digital output formats 8 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD e Applications DVD recorders LCD TV Set top boxes Digital TV Portable video devices and TV PIP picture in picture display 10 100 Ethernet controller e Integrated MAC and PHY with a general processor interface e Supports 100Base T and IOBase T applications e Supports full duplex operation at 10 Mb s and 100 Mb s with auto MDIX e Fully compliant with the IEEE 802 3u Specification e Supports IP TCP UDP checksum generation and checking e Supports back pressure mode for half duplex mode flow control USB Host Slave controller e Complies fully with Universal Serial Bus Specification Rev 2 0 e Supports data transfer at full speed and low speed e Supports both USB host and device e Two USB ports one type A for a host and one type B for a device e Provides a high speed parallel interface to most available processors supports Nios II with a Terasic driver e Supports Programmed I O PIO and Direct Memory Access DMA 8 A id 7 H mous T DE2 70 User Manual eiu Wd JJ ETLE 86 21 54151736 Wd JJ Hi d GUI 86 755 83298787 Http www 100y com tw Serial ports e One RS 222 port e One PS 2 port DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the DE2 70 board IrDA transceiver e Contains a 115 2 kb s infrared transceiver e 32mA
51. e period called the front porch d where the RGB signals must again be off before the next sync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 5 13 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 5 9 and 5 10 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be 45 Be AF J 886 5 5755170 ER 7 86 21 54151736 FNI i4 DE2 70 User Manual WERE JJ Hi 86 755 83298787 Http www 100y com tw found on the manufacturer s web site or in the Datasheet VGA DAC folder on the DE2 70 System CD ROM The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 5 11 An example of code that drives a VGA display is described in Sections 6 2 6 3 and 6 4 Back porch b Front porch d Display interval HSYNC Sync a Figure 5 13 WGA horizontal timing specification DATA Come D EXER T Cu wwr er m wn EHE m 108 2806 GODE XGA 70Hz 1024x768 XGA 85Hz 1024x768 1280x1024 60Hz 1280x1024 Table 5 9 VGA horizontal timing specification Table 5 10 WGA vertical timing specification 46 SYAN DE2
52. emory for the Nios II processor with the DE2 70 SD Card Driver Pushbutton switches e 4 pushbutton switches Debounced by a Schmitt trigger circuit e Normally high generates one active low pulse when the switch is pressed Toggle switches 18 toggle switches for user inputs e A switch causes logic 0 when in the DOWN closest to the edge of the DE2 70 board position and logic 1 when in the UP position Clock inputs 50 MH ill NN SA A J 4 7 M 1 886 3 5758170 us WEAR tB FUEN 86 21 54151736 e SMA external clock Input WEE JJ Hk ve 86 755 83298787 Http www 100y com tw JA Mr 7 M Ft 886 3 5753170 DE2 70 User Manual n Wd JJ H Ei 86 21 54151736 Wd JJ Hi 86 755 83298787 Http www 100y com tw Audio CODEC e Wolfson WM8731 24 bit sigma delta audio CODEC e Line level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 240 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector e Supports up to 1600 x 1200 at 100 Hz refresh rate e Can be used with the Cyclone II FPGA to implement a high performance TV Encoder NTSC PAL SECAM TV decoder circuit Uses two ADV7180 Multi format SDTV Video Decoders e Supports worldwide NTSC PAL SECAM color demodulation e One 10 bit ADC 4X over sampling for CVBS
53. erify the functionality of the USB Host Follow the steps below to exercise the USB Mouse Monitoring tool 1 Choosing the USB tab leads to the window in Figure 3 8 2 Plug an USB mouse to the USB HOST port on the DE2 70 board 3 Press the Start button to start the USB mouse monitoring process and button caption 15 changed from Start to Stop In the monitoring process the status of the USB mouse 15 updated and shown in the Control Panel s GUI window in real time Press Stop to terminate the monitoring process A d J 8865 6755170 ERR ETER 86 91 54151786 Wt JJ ETTE 86 755 83298787 Http www 100y com tw 18 DE2 70 User Manual Product Mame DE 70 hittp www altera com A299 Y 215 L 1 MID ter WW reraasic com Connected T lusb mause status checking Figure 3 8 USB Mouse Monitoring Tool 3 6 PS2 Device The Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time The received scan codes are translated to ASCII code and displayed in the control window Only visible ASCII codes are displayed For control key only Carriage Return ENTER key is implemented This function can be used to verify the functionality of the PS2 Interface Please follow the steps below to exercise the PS2 device Choosing the PS2 tab leads to the window in Figure 3 9 Plug a PS2 Keyboard to the FPGA board Then Press the Start button to start PS2Keybo
54. essing the ON OFF switch on the DE2 70 board b oue ue dd DE2 70 User Manual S RYA At this point you should observe the following All user LEDs are flashing All 7 segment displays are cycling through the numbers 0 to F The LCD display shows Welcome to the Altera DE2 70 The VGA monitor displays the image shown in Figure 2 3 Set the toggle switch SW17 to the DOWN position you should hear a 1 kHz sound Set the toggle switch SW17 to the UP position and connect the output of an audio player to the Line in connector on the DE2 70 board on your headset you should hear the music played from the audio player MP3 PC iPod or the like You can also connect a microphone to the Microphone in connector on the DE2 70 board your voice will be mixed with the music played from the audio player Figure 2 3 The default VGA output pattern Wed 7 4 4 886 3 5753170 WER J ETLER 86 21 54151736 WEE 7 EFRR 86 755 83298787 Http www 100y com tw 10 He 4 2 M od 886 3 5753170 lE JJ ETLE 86 21 54151736 VA H DE2 70 User Manual eu ti 86 755 83298787 Http www 100y com tw Chapter 3 DE2 70 Control Panel The DE2 70 board comes with a Control Panel facility that allows users to access various components on the board from a host computer The host computer communicates with the board through an USB connection The facility can be used to verify the functionality of componen
55. f these switches 1s debounced using a Schmitt Trigger circuit as indicated in Figure 5 3 The four outputs called KEYO KEY KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it 15 not pressed and provides a low logic level 0 volts when depressed Since the pushbutton switches are debounced they are appropriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced Figure 5 3 Switch debouncing 32 We 1 7 886 3 5753170 WERE IT Hig 86 21 54151786 HES JJ Ha 86 755 83298787 Http www 100y com tw DE2 70 User Manual There are also 18 toggle switches sliders on the DE2 70 board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch 1s connected directly to a pin on the Cyclone II FPGA When a switch 15 in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch is in the UP position it provides a high logic level 3 3 volts There are 27 user controllable LEDs on the DE2 70 board Eighteen red LEDs are situated above the 18 toggle switches and eight green LEDs are found above the pushbutton switches the 9 green LED 15 in the middle of the 7 segment displays
56. file will be e MAS displayed in the waveform window The sampling rate of the wave file also 1s displayed in the Sample Rate Combo Box You can drag the scrollbar to browse the waveform In the waveform window the blue line represents left channel signal and green line represents right channel signal 5 Click Start Play to start audio play The program will download the waveform to SDRAM UI configure the audio chip for audio playing and then start the audio playing process You will hear the audio sound from the headset or speaker To stop the audio playing simply click Stop Play 21 DE2 70 User Manual Lus Control Panel 1 0 0 Product Name DE 70 http www altera com Sample Rate s1 OpenWeve StamPlay ter asic Target Memory www LeFBSIC COMI About SDRAM U2 Download Code Disconnect Exit Connected SD CARD read success Figure 3 11 Playing audio from a selected wave file To record sound using a microphone please follow the steps below Plug a microphone to the MIC port on the board 2 Select the Record MIC item in the com box and select desired sampling rate as shown in Figure 3 12 3 Click Start Record to start the record process The program will configure the audio chip for MIC recording retrieve audio signal from the MIC port and then save the audio signal into SDRAM UI 4 To stop recording click Stop Record Finally audio signal saved in SD
57. fore sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio interface as I2S with 16 bits per channel and sampling rate according to the wave file content In audio playing loop the main program reads 512 byte audio data from the SD card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program have to make sure the FIFO 15 not full The design also mixes the audio signal from the microphone in and line in for the Karaoke style effects by enabling the BYPASS and SITETONE functions in the audio chip Finally users can obtain the status of the SD music player from the 2x16 LCD module the 7 segment display and the LEDs The top and bottom row of the LCD module will display the file name of the music that 1s playing on the DE2 70 board and the value of music volume respectively The 7 segments display will show how long the music file has been played The LED will indicate the audio signal strength We od dM 8 886 3 5753170 VERE RF CES 86 21 54151736 Demonstration Setup File Locations and Instructions Wd Jy ti TREHI 86 755 83298787 e Project directory DE2_70_SD_Card_Audio_Player Http www 1003 com tw e Bit stream used DE2 70 SD Card Audio Player sof e Nios Il Workspace DE2 70 SD Card Audio PlayerNSoftware e Format your SD card into FAT 6 format Put the played wave files t
58. hat the current LCD modules used on DE2 DE2 70 boards do not have backlight Therefore the LCD BLON signal should not be used in users design projects 5 6 Using the Expansion Header The DE2 70 Board provides two 40 pin expansion headers Each header connects directly to 36 pins of the Cyclone II FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Among these 36 I O pins 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA The voltage level of the I O pins on the expansion headers can be adjusted to 3 3V 2 5V or 1 8V using JP1 Because the expansion I Os are connected to the BANK 5 of the FPGA and the VCCIO voltage VCCIOS of this bank is controlled by the header JP1 users can use a jumper to select the input voltage of VCCIOS to 3 3V 2 5V and 1 8V to control the voltage level of the I O pins Table 5 7 lists the jumper settings of the The pin outs of the appear in the Figure 5 10 Finally Figure 5 11 shows the related schematics Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only two of the pins on each header but this circuitry 1s included for all 72 data pins Table 5 8 gives the pin assignments Short Pins 1 and 2 Short Pins 5 and 6 Short Pins 3 and 4 Table 5 7 Volt
59. hods the DE2 70 board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DE2 70 Board This tutorial is available on the DE2 70 System CD ROM 30 VETERES DE2 70 User Manual NOTE RYA Configuring the FPGA in JTAG Mode Figure 5 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps e Ensure that power is applied to the DE2 70 board e Connect the supplied USB cable to the USB Blaster port on the DE2 70 board see Figure 2 1 e Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the RUN position e The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension USB Blaster Circuit PROG RUN Quartus Il J TAG Confi Programs RUN H pone J TAG Config Port Power on Config ME 7 hL 886 3 5753170 WERE JJ ETUER 86 21 54151786 EPCS16 Serial Configuration Device Wd JJ EERE 86 755 83298787 Http www 100y com tw Figure 5 1 The JTAG configuration scheme Configuring the EPCS16 in AS Mode Figure 5 2
60. io quality can be produced The DE2 70 board provides the hardware and software needed for SD card access and professional audio performance so that it 1s possible to design advanced multimedia products using the DE2 70 board In this demonstration we show how to implement an SD Card Music Player on the DE2 70 board in which the music files are stored in an SD card and the board can play the music files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music 80 e DE2 70 User Manual Jianv4 Figure 6 13 shows the hardware block diagram of this demonstration The system requires a 50 MHZ clock provided from the board The PLL generates a 100 MHZ clock for NIOS II processor and the other controllers except for the audio controller The audio chip is controlled by the Audio Controller which is a user defined SOPC component This audio controller needs an input clock running at 18 432 MHZ In this design the clock is provided by the PLL block The audio controller requires the audio chip working in master mode so the serial bit BCK and the left right channel clock LRCK are provided by the audio chip The 7 segment display is controlled by the Seg 7 Controller which also is a user defined SOPC component Two PIO pins are connected to the I2C bus The I2C protocol is implemented by software Four PIO pins are connected to the
61. keyboard connector e IrDA transceiver e SMA connector e Two 40 pin Expansion Headers with diode protection In addition to these hardware features the DE2 70 board has software support for standard I O interfaces and a control panel facility for accessing various components Also software 1s provided for a number of demonstrations that illustrate the advanced capabilities of the DE2 70 board In order to use the DE2 70 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 70 Board and Quartus II Introduction which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DE2 70 tutorials on the DE2 70 System CD ROM that accompanies the DE2 70 board and can also be found on Altera s DE2 70 web pages 2 2 Block Diagram of the DE2 70 Board Figure 2 2 gives the block diagram of the DE2 70 board To provide maximum flexibility for the user all connections are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design DE2 70 User Manual 50Mhz 28Mhz Ext In USB 2 0 Host Device 24 bit Audio CODEC 10 100 Ethernet PHY MAC XSGA 10 bit Video DAC SD Card TV Decoder 2 Cyclone FPGA IrDA Transceiver User Green LEDs 9 Flash 8 Mbyte User Red LEDs 18 16x2 LCD Module
62. l Ww 12 D HENCE s rn p su 1 tan a T wit 5 n We od 1 886 3 5753170 WE JJ Rf Eit 86 21 54151736 ERED E PREI 86 755 83298787 Http www 100y com tw Figure 6 10 The setup for the Karaoke Machine 6 7 Ethernet Packet Sending Receiving In this demonstration we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 70 board As illustrated in Figure 6 11 we use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY MAC Controller The demonstration can be set up to use either a loop back connection from one board to itself or two DE2 70 boards connected together On the transmitting side the Nios II processor sends 64 byte packets every 0 5 seconds to the DMO9000A After receiving the packet the DM9000A appends a four byte checksum to the packet and sends it to the Ethernet port On the receiving side the DM9000A checks every packet received to see if the destination MAC 78 mu DE2 70 User Manual ules A address in the packet is identical to the MAC address of the DE2 70 board If the packet received does have the same MAC address or is a broadcast packet the DM9000A will accept the packet and send an interrupt to the Nios II processor The processor will then display the packet contents in the Nios II IDE console window 64 Bytes Data Ww os 64 Bytes Data 4 Bytes Checksum
63. le 5 19 SDRAM pin assignments We od 2 d 886 3 5753170 7 ETLE 86 21 54151736 JJ EGE 86 755 83298787 Http www 100y com tw DE2 70 User Manual SRAM 8 PIN AK17 SRAM Data 8 2 BE jk 7 M dH 886 3 5753170 Ws ETUE 86 21 54151736 WERE JJ Hi 86 755 83298787 Http www 100y com tw DE2 70 User Manual SRAM DPA2 PIN AK20 SRAM Parity Data 2 SRAM_DPA3 PIN AJ9 SRAM Parity Data 3 SRAM GW N PIN AG18 SRAM Global Write Enable SRAM OE N PIN AD18 SRAM Output Enable SRAM WE N PIN AF18 SRAM Write Enable Table 5 20 SSRAM pin assignments We d M 1 886 3 5753170 Wd JJ H f Eg 86 21 54151736 EE Ht 3 3I 86 755 83298787 Http www 100y com tw DE2 70 User Manual FLASH DQ 5 PIN AB29 FLASH Data 5 FLASH WP N FLASH Write Protect Programming Acceleration Table 5 21 Flash pin assignments We 3 J oH 4 886 3 5753170 WERE ETUER 86 21 54151736 WERE Hi 86 755 83298787 Http www 100y com tw 65 We d J oH d 886 3 5753170 DNA MER JJ Ha f Ei 86 21 54151736 DE2 70 User Manual HES JJ EERE 86 755 83298787 Http www 100y com tw Chapter 6 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2 70 board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities and USB and Ethernet con
64. nectivity For each demonstration the Cyclone II FPGA or EPCS16 serial EEPROM configuration file 15 provided as well as the full source code in Verilog HDL code All of the associated files can be found in the DE2 70 demonstrations folder from the DE2 70 System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the DE2 70 demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory DE2 70 demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 6 1 DE2 70 Factory Configuration The DE2 70 board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions e Project directory DE2 70 Default e Bit stream used DE2 70 Default sof or DE2 70 Default pof e Power on the DE2 70 board with the USB cable connected to the USB Blaster port If necessary that is if the default factory configuration of the DE2 70 board is not currently stored in EPCS16 device download the bit stream to the board by using either JTAG or AS programmi
65. ng e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red and green LEDs are flashing Also Welcome to the Altera DE2 70 is shown on the LCD display 66 V Bo DE2 70 User Manual S RYA Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors e Optionally connect a powered speaker to the stereo audio out jack e Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio out port Alternatively if switch SW17 1s DOWN the microphone in port can be connected to a microphone to hear voice sounds or the line in port can be used to play audio from an appropriate sound source The Verilog source code for this demonstration 1s provided in the DE2_70_Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called DE2_70_Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 6 2 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output audio CODEC and one TV decoder U11 on the DE2 70 board Figure 6 1 shows the block diagram of the design There are two major blocks in the circuit called 26 AV Config and TV to VGA The TV to VGA block consists of the ITU
66. o in ports or display desired pattern on the VGA port This chapter first presents some basic functions of the Video Utility control panel then describes its structure in block diagram form and finally describes its capabilities 4 1 Video Utility Setup The Video Utility is located in the DE2_70_video utility SW folder in the DE2 70 System CD ROM To install it just copy the whole folder to your host computer Launch the Video Utility by executing the DE2 70 UTILITY exe Specific configuration files should be downloaded to your FPGA board before the Control Panel can request it to perform required tasks The configuration files include one sof file and one e f file To download the codes simply click the Download Code button on the program The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB Blaseter US B 0 connection The sof file is downloaded to FPGA The e f file is downloaded to SDRAM UI To activate the Video Utility perform the following steps 1 Make sure Quartus II and Nios II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON Set the RUN PROG switch to the RUN position Start the executable DE2 70 AV Utility exe on the host computer The Video Utility user interface shown in Figure 4 1 will appear 5 Click the Download Code button The Cont
67. o the root directory of the SD card The provided wave files must have a sample rate of either 96K 48K 44 1 K 32K or 8K Besides the wave files must be stereo and 16 bits per channel Also the file name must be short filename e Load the bitstream into the FPGA on the DE2 70 board Run the Nios II IDE under the workspace DE2_70_SD_Card_Audio_Playe Software e Connect a headset or speaker to the DE2 70 board and you should be able to hear the music played from the SD Card 82 NBIS8 SYN DE2 70 User Manual e Press KEY3 on the DE2 70 board can play the next music file stored in the SD card e Press KEY2 and KEYI will increase and decrease the output music volume respectively Figure 6 16 illustrates the setup for this demonstration with music fils wav We 4 7 4 4 886 3 5753170 WE JJ ETEN 86 21 54151736 WE 4 JJ i PEI 86 755 83298787 Http www 100y com tw Figure 6 16 The setup for the SD music player demonstration 6 9 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using DE2 70 board with a PS 2 Keyboard and a speaker PS 2 Keyboard is used as the piano keyboard for input The Cyclone II FPGA on the DE2 70 board serves as the Music Synthesizer SOC to generate music and tones The VGA connected to the DE2 70 board is used to show which key is pressed during the playing of the music 83 MR 4p 2 OM 886 3 5753170 DE2 70 User Manual WE JJ
68. oard e Connect a Microphone to MIC IN port on the DE2 70 board e Connect a speaker or headset to LINE OUT port on the DE2 70 board e Load the bit stream into FPGA note 1 he 44 7 4 886 3 5753170 88 HE E JJ t f Egg 86 21 54151736 Wee J 86 755 83298787 Http www 100y com tw N DTE SYN DE2 70 User Manual e Load the Software Execution File into FPGA note 1 e Configure audio with the toggle switches Press KEY3 on the DE2 70 board to start stop audio recoding note 2 e Press KEY2 on the DE2 70 board to start stop audio playing note 3 Note 1 Execute DE2 70 AUDIONdemo batchNaudio bat will download sof and elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely Audio is from MIC Audio is from LINE IN Disable MIC Boost Enable MIC Boost Disable Zero cross Detection Enable Zero cross Detection Unlisted combination Table 6 4 Toggle switch setting for audio recorder and player Wed 7 3 886 3 5753170 WERE JJ ETLER 86 21 54151736 WE RED Hi d GUI 86 755 83298787 Http www 100y com tw 89 N DTE SYN DE2 70 User Manual Chapter 7 Appendix 7 1 Revision History Version Change Log Initial Version Preliminary V1 01 1 Add appendix chapter 2 Modify Chapter 2 3 4 5 6 7 2 Copyright Statement Copyright 2007 Terasic Technologies All rights reserved We d 7 886 3
69. omputer downloads the raw image data to SDRAM U2 2 Host issues a display command to Nios II processor 3 Nios II processor interprets the command received and moves the raw image data from the SDRAM to SSRAM through the Multi Port SSRAM controller 4 VGA Controller continuously reads the raw image data from the SSRAM and sends them to the VGA port The control flow for video capturing is described below 1 Host computer issues a capture command to Nios II processor 2 Nios II processor interprets the command and controls Video In controller to capture the raw image data into the SSRAM After capturing is done Nios II processor copies the raw image data from the SSRAM to SDRAM U2 3 Host computer reads the raw image data from the SDRAM U2 Host computer converts the raw image data to RGB color space and displays it he 44 7 4 4 886 3 5753170 WE Jj RF Ei 86 21 54151736 WEAF JJ H i 86 755 83298787 Http www 100y com tw 29 TA Me J 886 3 5753170 DE2 70 User Manual SN ERR A ETE 86 21 54151736 HES Jj EERE 86 755 83298787 Http www 100y com tw Chapter 5 Using the DE2 70 Board This chapter gives instructions for using the DE2 70 board and describes each of its I O devices 5 1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DE2 70 board 15 described in the tutorial Quartus II Introduction This tutorial is found in the DE2 7
70. onnect Exit Connected Video Capture success Dim 720x576 7 7 sec Figure 4 3 Video Capturing Tool 4 4 Overall Structure of the DE2 70 Video Utility The DE2 70 Video Utility 15 based on a NIOS II system running in the Cyclone II FPGA with the SDRAM U2 or SSRAM The software part is implemented in C code the hardware part is implemented in Verilog code with SOPC builder which makes it possible for a knowledgeable user to change the functionality of the Video Utility The code is located inside the DE2 70 demonstrations directory on the DE2 70 System CD ROM Figure 4 4 depicts the block diagram of the Video Utility Each input output device is controlled by the NIOS II Processor instantiated The communication between the DE2 70 board and the host PC is via the USB Blaster link The NIOS II processor interprets the commands sent from the PC and performs the appropriate actions B oH 7 3d 886 3 5753170 MEJ EQ 86 21 54151736 HER Hi 86 755 83298787 Http www 100y com tw 28 DE2 70 User Manual NIOS II Program SDRAM NIOS II Controller vy SDRAM UI 5 SDRAM C SDRAM U2 Controller VGA JTAG Controller Blaster Hardware Multi Port SSRAM SSRAM lt Controller Avalon MM Slave VIDEO In K N VIDEO IN Controller 91151 J9 uuood Jul 5 Figure 4 4 Video Capture Block Diagram The control flow for video displaying 1s described below 1 Host c
71. ording and Playing This demonstration shows how to implement an audio recorder and player using the DE2 70 board with the built in Audio CODEC chip This demonstration is developed based on SOPC Builder and NIOS II IDE Figure 6 18 shows the man machine interface of this demonstration Two push buttons and six toggle switches are used for users to configure this audio system SWO is used to specify recording source to be Line in or MIC In SWI is to enable disable MIC Boost when the recoding source is MIC In SW2 15 used to enable disable Zero Cross Detection for audio playing SW3 SWA and SW5 are used to specify recording sample rate as 96K 48K 44 1 K 32K or 8K The 16x2 LCD 1s used to indicate the Recording Playing status The seg7 is used to display Recording Playing duration with time unit in 1 100 second The LED 15 used to indicate the audio signal strength Table 6 4 summarizes the usage of toggle switches for configuring the audio recorder and player Record Play Status Record Play Duration Signal Strength Play Sample rate Record Audio Source MIC Boost Zero Cross Detect Figure 6 18 Man Machine Interface of Audio Recorder and Player Figure 6 19 shows the block diagram of the design of the Audio Recorder and Player There are hardware part and software part in the block diagram The software part means the Nios II program that stored in SSRAM The software part is built by Nios II IDE in C programming language
72. ots lines on the screen tke 44 J 4 4 886 3 5753170 Wk dg JJ ETUER 86 21 54151736 Hi d GUI 86 755 83298787 Http www 100y com tw Figure 6 6 illustrates the setup for this demonstration 73 DE2 70 User Manual AE DE2 Board USB Driver 7 Wed 7 3b o4 886 3 5753170 WE JJ ETLE 86 21 54151736 WEE JJ Hu 86 755 83298787 Http www 100y com tw Figure 6 6 The setup for the USB paintbrush demonstration 6 5 USB Device Most USB applications and products operate as USB devices rather than USB hosts In this demonstration we show how the DE2 70 board can operate as a USB device that can be connected to a host computer As indicated in the block diagram in Figure 6 7 the Nios II processor is used to communicate with the host computer via the host port on the DE2 70 board s Philips ISP1362 device After connecting the DE2 70 board to a USB port on the host computer a software program has to be executed on the Nios II processor to initialize the Philips ISP1362 chip Once the software program 15 successfully executed the host computer will identify the new device in its USB device list and ask for the associated driver the device will be identified as a Philips PDIUSBDI2 SMART Evaluation Board After completion of the driver installation on the host computer the next step is to run a software program on the host computer called JSP 362DcUsb exe this program communicates wi
73. ow logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display 15 identified by an index from 0 to 6 with the positions given in Figure 5 7 In addition the decimal point is identified as DP Table 5 4 shows the assignments of FPGA pins to the 7 segment displays HEXO DI0 6 DO HEXO Di HEXO D2 HEX0 D3 HEXO D4 HEXO D5 HEXO D6 HEXO DP he d 7 4 4 886 3 5753170 71 Hk f Ei 86 21 54151736 HEt H EERE 86 755 83298787 Http www 100y com tw Figure 5 7 Position and index of each segment in a 7 segment display HEXO D 0 PIN AE8 Seven Segment Digit O O HEXO D 1 PIN AF9 Seven Segment Digit O 1 HEXO D 2 PIN AH9 Seven Segment Digit O 2 36 f PER JH Ha eH 86 755 83298787 We d J oH d 886 3 5753170 EHETE 86 21 54151736 DE2 70 User Manual Http www 100y com tw HEXO D S PIN AD10 Seven Segment Digit O 3 37 e DE2 70 User Manual Jianv4 HEX5 D 0 PIN M3 Seven Segment Digit 5 0 Table 5 4 Pin assignments for the 7 segment displays 5 4 Clock Circuitry The DE2 70 board includes two oscillators that produce 28 86 MHz and 50 MHz clock signals Both two clock signals are connected to the FPGA that are used for clocking the user logic Also the 28 86 MHz oscillator 1s used to drive the two TV decoders The board also includes an SMA connector which can be used to connect an extern
74. rol Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 6 The Video Utility is now ready for use We 4 J M 886 3 5753170 WE T JJ V Ei 86 21 54151736 ERE I E ERRI 86 755 83298787 25 Http www 100y com tw DE2 70 User Manual Video Utility V1 0 0 Display Capture Image Position CENTER Dimension 540 x 480 Pixels Load Display Download Code Disconnect Exit Connected Download code success Figure 4 1 The DE2 70 Video Utility window 4 7 4 1 886 3 5753170 BEEF JJ t 86 21 54151736 HES JH EERE 86 755 83298787 4 0 VGA Display Http www 100y com tw Choosing the Display tab in the DE2 70 Video Utility leads to the window shown in Figure 4 2 The function 15 designed to download an image from the host computer to the FPGA board and output the image through the VGA interface with resolution 640x480 Please follow the steps below to exercise the Video Utility 1 Connect a VGA monitor to the VGA port of the board 2 Click Load button and specify an image file for displaying It can be a bitmap or jpeg file The selected image file will be displayed on the display window of the Video Utility 3 Select the desired Image Positioning method to fit the image to the VGA 640x480 display dimension Click Display button to start downloading the image to
75. signments 48 jk Jo 886 3 5753170 WE d ETUER 86 21 54151736 WEE Hi GU 86 755 83298787 Http www 100y com tw J F 7 1 886 3 5758170 DE2 70 User Manual n JEE JJ ETUE 86 21 54151736 ERED Hid GUI 86 755 83298787 Http www 100y com tw 5 9 RS 232 Serial Port The DE2 70 board uses the ADM3202 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which 1s available on the manufacturer s web site or in the Datasheet RS232 folder on the DE2 70 System CD ROM Figure 5 15 shows the related schematics and Table 5 13 lists the Cyclone II FPGA pin assignments RXD LEDR R44 330 AX UART RXD VCC33 TXD LEDG R45 330 AX UART TXD AY DART RD R1OUT UART RTS Q E J UART TXD LX NP UART CTS N lt gt C9 1u C NN E ADM3202 Table 5 13 RS 232 pin assignments 5 10 PS 2 Serial Port The DE2 70 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse In addition users can use the PS 2 keyboard and mouse on the DE2 70 board simultaneously by an plug an extension PS 2 Y Cable Figure 5 16 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The pin assignments for the associated interface are shown in Table 5 14 49 u PS2
76. sssis s sis ROO nA TK gt gt gt gt gt gt gt gt gt gt R81 560 RSET BC47 BC48 VGA R 0 9 d 0 1u 0 1u VGA 0 9 U10 TAIS 7 VGA B 0 9 VGA GO VGA G1 VGA G2 VGA R van Ge HL OWN VOACB VGA G4 IOR 725 VGA B VGA G5 6 1 a VGA G6 ADV7123 IOG Fan 2 VGA_G7 x VAA bo R82 R83 R84 VGA G8 9 283 VGA G9 i IOB 757975 VGA BLANK n G9 PUE ETa lt YGA SYNC n 12 Los 7 VGA HS R85 4 Z wWvGA VS R86 4 VGA B3 VGA B8 Q O Pi lt 5 gt VGA_BO VGA B1 VGA B2 VGA B4 VGA B5 VGA B6 VGA B7 VGA B9 O VGA_VCC33 Figure 5 12 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 5 13 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there 15 a tim
77. t All or Unlight All 13 Product Mame DE 2 70 wiLEDIG3 vILEDG4 wiLEDIGS viLEDGB wILEDG WILEDGE mi LEDRO wiLEDR1 vILEDR2 wILEDR i LEDRB wiLEDRS LEDR10 v LEDR11 wILEDR12 LEDR13 iLEDR14 MILEDR15 wILEDR18 vILEDR17 DE2 70 User Manual vLEDR3 v LEDR4 MILEDRS http www altera com Light All Unlight All D ter asic EET Memory WWW DePasic com About SDRAM LJ2 1 5 Download Code Disconnect a Exit SH Connected Em X Set Led Success Figure 3 3 Controlling LEDs Choosing the 7 SEG tab leads to the window in Figure 3 4 In the tab sheet directly use the Up Down control and Dot Check box to specified desired patterns the 7 SEG patterns on the board will be updated immediately Control Panel 2 0 0 123 4 5678 dot dot dot dot B dot dot dot dot Product WT Y 5 IM ES EE IE s Eu Ein DE 2 7U http www altera com ter asic Target Memory Www DErasic com About j SDRAM LJ2 gt Download Code ao Disconnect TR Exit Connected S Set Led Success Figure 3 4 Controlling 7 SEG display d J oH 886 3 5753170 14 ERJ B 86 21 54151736 WEAR E PREI 86 755 83298787 Http www 100y com tw DE2 70 User Manual Choosing the LCD tab leads to the window in Figure 3 5 Text can be written to the LCD display by typing it in the LCD box and pressing the Set button LCD
78. th a computer that runs the Microsoft Windows software 1 1 Package Contents Figure 1 1 shows a photograph of the DE2 70 package 1 4 7 886 3 5753170 ERE ETIEN 86 21 54151736 Wd JJ Ha 30 86 755 83298787 Http www 100y com tw Figure 1 1 The DE2 70 package contents 1 NH S SYN DE2 70 User Manual The DE2 70 package Includes 1 2 The DE2 70 board USB Cable for FPGA programming and control DE2 70 System CD containing the DE2 70 documentation and supporting materials Including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises CD ROMs containing Altera s Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software Bag of six rubber silicon covers for the DE2 70 board stands The bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers Clear plastic cover for the board 12V DC wall mount power supply The DE2 70 Board Assembly To assemble the included stands for the DE2 70 board Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE2 70 board The clear plastic cover provides extra protection and is mounted over the top of the board by using additional stands and screws BY Figure 1 2 The feet for the DE2 70 board 1 44 7 S 4 886
79. th a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789ABCDEF defines four 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively 17 NOE DE2 70 User Manual into the memory The Sequential Read function is used to read the contents of the SDRAM UI and place them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM UI are to be copied which involves all 32 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the SSRAM and Flash Please note that users need to erase the flash before writing data to it 3 5 USB Monitoring The Control Panel provides users a USB monitoring tool which monitors the real time status of a USB mouse connected to the DE2 70 board The movement of the mouse and the status of the three buttons will be shown in the graphical and text interface The mouse movement is translated as a position x y with range from 0 0 1023 767 This function can be used to v
80. th the DE2 70 board In the JSP1362DcUsb program clicking on the Add button in the window panel of the software causes the host computer to send a particular USB packet to the DE2 70 board the packet will be received by the Nios II processor and will increment the value of a hardware counter The value of the counter is displayed on one of the board s 7 segment displays and also on the green LEDs If 74 NDE DA DE2 70 User Manual JiaonvA the user clicks on the Clear button in the window panel of the software driver the host computer sends a different USB packet to the board which causes the Nios II processor to clear the hardware counter to zero Link to Host PC SN Setup Package eee Philips Enumeration ISP1362 Information Communication Figure 6 7 Block diagram of the USB device demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 70 NIOS DEVICE LEDNIW e Bit stream used DE2 70 NIOS DEVICE LED sof e Nios II Workspace DE2 70 NIOS DEVICE LEDNHWASoftware e Borland BC Software Driver DE2 70 NIOS DEVICE LEDNSW e Connect the USB Device connector of the DE2 70 board to the host computer using a USB cable type A B e Load the bit stream into FPGA e Run Nios IL IDE with HW as the workspace Click on Compile and Run e A new USB hardware device will be detected Specify the location of the driver as DE2_70_NIOS_DEVICE_LED D12test inf Philips PDIUSBDI2 SMART Evaluation
81. the DE2 70 board 5 After finish downloading you will see the desired image shown on the screen of the VGA monitor 26 5 A DE2 70 User Manual Image Position STRETCH Dimension 640 x 480 Pixels Load Display Download Code Disconnect Exit Y M Connected m display success 6 4 sec Figure 4 2 Displaying selected image file on VGA Monitor 4 3 Video Capture Choosing the Capture tab leads to the window in Figure 4 3 The function is designed to capture an image from the video sources and sent the image from the FPGA board to the host computer The input video source can be PAL or NTSC signals Please follow the steps below to capture an image from a video source 1 Connect a video source such as a VCD DVD player or NTSC PAL camera to VIDEO IN 1 or VIDEO IN 2 port on the board Specify Video Source as VIDEO IN 1 or VIDEO IN 2 3 Click Capture button to start capturing process Then you will see the captured image shown in the display window of the Video Utility The image dimension of the captured image is also displayed 4 Users can click Save button to save the captured image as a bitmap or jpeg file j 3 7 886 3 5753170 WE JJ RF E 86 21 54151736 27 WE RE JJ Ha 86 755 83298787 Http www 100y com tw DE2 70 User Manual Video Utility 1 0 0 Display Capture Video Source VIDEO IN 1 Dimension 720x575 Save Capture Download Code Disc
82. ther ports 0 99 2 053 lO B24 LE B25 lO B26 5 o lO B27 lO B28 o 38 B29 IO B30 3 40 IO B31 BOX Header 2X20M Figure 5 11 Schematic diagram of the expansion headers IO A 0 PIN C30 GPIO Connection 0 IO 0 IO A 1 PIN C29 GPIO Connection 0 1 IO A 2 PIN E28 GPIO Connection 0 2 DE2 70 User Manual IO A 3 PIN D29 GPIO Connection 0 IO 3 43 We o 886 3 5753170 WE JJ H T Eg 86 21 54151736 Wi 45 JJ Hi d GUI 86 755 83298787 Http www 100y com tw DE2 70 User Manual IO B 4 PIN H28 GPIO Connection 1 IO 4 Table 5 8 Pin assignments for the expansion headers MR at 7 hL 886 3 5753170 Wd JJ RF CER 86 21 54151736 WEE JJ EREI 86 755 83298787 Http www 100y com tw We 4 d 886 3 5753170 ANU ava WEAR ti FLEN 86 21 54151736 WEED Hi 86 755 83298787 Http www 100y com tw 5 7 Using VGA The DE2 70 board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone II FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC 15 used to produce the analog data signals red green and blue The associated schematic 1s given in Figure 5 12 and can support resolutions of up to 1600 x 1200 pixels at 100 MHz VGA VCC33 minds ur ww O ssi
83. ts on the board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel Software Utility is located in the DE2 70 control pane SW folder in the DE2 70 System CD ROM To install it just copy the whole folder to your host computer Launch the control panel by executing the DE2 70 Control Panel exe Specific control codes should be downloaded to your FPGA board before the control panel can request it to perform required tasks The control codes include one sof file and one e f file To download the codes just click the Download Code button on the program The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB Blaster USB 0 connection The sof file is downloaded to FPGA The e f file is downloaded to either SDRAM U2 or SSRAM according to the user option To activate the Control Panel perform the following steps 1 Make sure Quartus II and NIOS II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON Set the RUN PROG switch to the RUN position Start the executable DE2 70 control panel exe on the host computer The Control Panel user interface shown in Figure 3 1 will appe
84. with 70K LEs sE IrDA Transceiver 7 Segment Displays 8Mbyte Flash Memory 8 Green LEDs or SMA Extemal Clock 18 Red LEDs 18 Toggle Switches 32Mbyte SDRAMx2 28Mhz Oscillator 2Mbyte SSRAM 4 Push button Switches Figure 2 1 The DE2 70 board The DE2 70 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DE2 70 board e Altera Cyclone II 2C70 FPGA device e Altera Serial Configuration device EPCS16 e USB Blaster on board for programming and user API control both JTAG and Active Serial 4 We d d 886 3 5753170 ERED Ha 86 21 54151736 DE2 70 User Manual on WE 45 EERE 86 755 83298787 Http www 100y com tw AS programming modes are supported 2 Mbyte SSRAM e Two32 Mbyte SDRAM 8 Mbyte Flash memory e SD Card socket e 4 pushbutton switches e 18 toggle switches 18 red user LEDs 9 green user LEDs e 50 MHz oscillator and 28 63 MHz oscillator for clock sources e 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 10 bit high speed triple DACs with VGA out connector e 2 TV Decoder NTSC PAL SECAM and TV in connector e 10 100 Ethernet Controller with a connector e USB Host Slave Controller with USB type A and type B connectors e RS 232 transceiver and 9 pin connector PS 2 mouse

Chapter 2 Altera DE2

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