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µPD75518 USER'S MANUAL

1. 2 1 2 1 Piti FUNCTIONS use Ub EIL e D n RA 2 1 2 2 PIN FUNCHONS Einb 2 6 2 2 1 P00 P03 PORTO P10 P13 PORT1 P80 P83 PORTS P T503P 153 POR TIS 2 6 2 2 2 P20 P23 2 P30 P33 PORT3 P60 P63 PORTS P70 P73 PORT7 P90 P93 PORT9 P100 P103 10 P110 P113 o s Dot 2 7 2 2 3 P40 P43 PORTA P50 P53 PORT5 P120 P123 PORT12 130 133 PORT13 P140 P143 14 2 8 2 8 2095 m Te Dd SE cL ERE 2 8 ue ce Ld ere OE ME 2 8 cr MM PPP NUES 2 8 228 SCKO SOO SBO SIO SB1 SCK1 SO1 811 2 9 229 1 dec X Me 2 9 2510 1 1 1 oe e 2 9 22 08 WINS ou ed uada Lr ER dn NE 2 10 22 5 KRO KR3 KEUEKBIT 2 10 652 19 PO os taps E onu T AA Lea ir 2 10 2344 E 2 10 DOT CC 2 10 DOT IR NNNM 2 10 2 2 175 201 e 2 11 ci Ime s cru O 2 11 2 2 19 RESET ADULT 2 11 psg soc ep m a 2 12 2 2 21 MDO MD3 for uPD75P518
2. 5 Chapter 5 Peripheral Hardware Functions 5 8 3 Register Functions 1 Serial operation mode register 1 CSIM1 Figure 5 83 shows the format of serial operation mode register 1 CSIM1 CSIM1 is an 8 bit register which specifies a serial interface channel 1 operation mode and serial clock CSIM1 is manipulated using an 8 bit memory manipulation instruction Only the high order one bit can be manipulated independently Each bit can be manipulated using its name The RESET signal resets this register to 00H Figure 5 83 Format of Serial Operation Mode Register 1 CSIM1 Address Symbol 7 6 5 4 3 2 1 0 Serial clock selection bit W Serial interface operation enable disable specification bit W Remark W Write only Serial clock selection bit W CSIM1 1 CSIM10 Serial clock three wire serial I O mode SCK1 pin mode 0 0 External clock applied to SCK1 pin Input 0 1 Not to be set x 1 524 262 kHz or 375 kHz Note Output 2 fx 23 524 kHz or 750 kHz Note Note The values at 4 19 MHz and 6 0 MHz are indicated in parentheses Serial interface operation enable disable specification bit W Shift register operation Serial clock counter EOT flag 501 and 51 pins CSIE1 0 Shift operation disabled Cleared Held Used only for port 8 1 Shift operation enabled Count operation Can be set Used in each mode as well as for p
3. 5 149 5 8 6 Application of the Serial Interface Channel 1 5 151 5 9 5 152 5 9 1 Configuration of the A D Converter 5 152 5 9 2 A D Converter Operation sess 5 156 5 9 3 Notes on the Standby 5 159 5 9 4 Other Notes on Use 5 160 5 9 5 Application of A D 5 161 5 10 Bit Sequential Buffer 5 162 5 10 1 Applications of the Bit Sequential Buffer 5 163 Chapter 6 Interrupt 6 1 6 1 Configuration of the Interrupt Control Circuit 6 1 6 2 Types of Interrupt Sources and Vector Tables 6 3 6 3 Various Devices of the Interrupt Control Circuit 6 5 6 4 Interrupt Sequence eee sn enia 6 16 6 5 Multiple Interrupt Processing Control 6 17 6 6 Processing of Interrupts Sharing a Vector Address 6 19 6 7 Machine Cycles for Starting Interrupt Processing 6 21 6 8 Effective Use of Interrupts 6 23 TOC 6 uPD75518 User s Manua
4. nnn 4 13 Program Status Word F fmat einn nnns 4 14 Bank Select Register Format sss etnies 4 18 Data Memory Address Assigned to Digital VO Ports 5 1 Configurations of Ports 0 1 and 8 nnne 5 4 Configurations of Ports and n 0 to 3 5 5 Configurations of Ports 2 and 7 sss 5 5 Configurations of Ports 4 5 12 13 and 14 sse 5 6 Configuration 9 eee i a dte tet ia ds 5 7 Configurations of Ports 10 and 11 sss 5 8 Configuration of Port 5 8 Formats of Port Mode Registers sse enne 5 10 Format of the Pull up Resistor 5 5 18 TOC 9 Contents Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Figure 5 20 Figure 5 21 Figure 5 22 Figure 5 23 Figure 5 24 Figure 5 25 Figure 5 26 Figure 5 27 Figure 5 28 Figure 5 29 Figure 5 30 Figure 5 31 Figure 5 32 Figure 5 33 Figure 5 34 Figure 5 35 Figure 5 36 Figure 5 37 Figure 5 38 Figure 5 39 Figure 5 40 Figure 5 41 Figure 5 42 Figure 5 43 Figure 5 44 Figure 5 45 Figure 5 46 Figure 5 47 Figure 5 48 Figure 5 49 Figure 5 50 Figure 5 51 Figure 5 52 Figure 5 53 TOC 10 ON Timing of Pull up Resistors by Software
5. nnn nnns 5 94 Transfer Bit Switching Circuit sisse 5 95 Example of Two Wire Serial V O System Configuration 5 100 Timing of Two Wire Serial VO Mode sse 5 103 Operations of RELT and 5 104 Example of SBI System Configuration sse 5 108 Timing of SBI Transfer oed etui ber P cedet 5 110 B us Helease 5 111 uPD75518 User s Manual Figure 5 54 Figure 5 55 Figure 5 56 Figure 5 57 Figure 5 58 Figure 5 59 Figure 5 60 Figure 5 61 Figure 5 62 Figure 5 63 Figure 5 64 Figure 5 65 Figure 5 66 Figure 5 67 Figure 5 68 Figure 5 69 Figure 5 70 Figure 5 71 Figure 5 72 Figure 5 73 Figure 5 74 Figure 5 75 Figure 5 76 Figure 5 77 Figure 5 78 Figure 5 79 Figure 5 80 Figure 5 81 Figure 5 82 Figure 5 83 Figure 5 84 Figure 5 85 Figure 5 86 Figure 5 87 Figure 5 88 Figure 5 89 Figure 5 90 Figure 5 91 Figure 5 92 Figure 5 93 Figure 5 94 uPD75518 User s Manual Contents 3 4 Command Signal died HERR 5 111 Uc 5 112 Slave Selection Using an Address sse 5 112 COMMANG em 5 113 Data snis Ra e ia ei etta a E iA 5 113 Acknowledge 5 114 Busy and Ready Signals sss rennen 5 115 Operations of RELT
6. Remark The uPD75518 can also be used as a slave CPU 1 Register setting To set the three wire serial mode manipulate the following two registers Serial operation mode register 0 CSIMO Serial bus interface control register SBIC uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions a Serial operation mode register 0 CSIMO To use the three wire serial I O mode set CSIMO as shown below For details on CSIMO see 1 in Section 5 7 3 CSIMO is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIMO can be manipulated bit by bit When the RESET signal is input CSIMO is set to OOH In the figure below hatched portions indicate the bits used in the three wire serial mode Address 7 6 5 4 3 2 1 0 Symbol FEOH csiEo CSIMO4 CSIMO3 CSIMO2 CSIMo0 CSIMO Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark Read only W Write only Serial clock selection bit W CSIMO1 CSIMOO Serial clock SCKO pin mode 0 0 External clock applied to SCKO pin Input 0 1 Timer event counter output TO Output 1 0 fx 24 262 kHz or 375 kHz Note 1 1 fx 23 524 kHz or 750 kHz Note Note The values at 4 19 MHz an
7. sss eene 5 65 Table 5 9 Generation of Notes Using the Timer Pulse 5 70 Table 5 10 Differences between Channel 0 and Channel 1 sss 5 73 Table 5 11 Serial Clock Selection and Application In the Three Wire Serial I O Mode 5 94 Table 5 12 Serial Clock Selection and Application In the Two Wire Serial I O Mode 5 104 Table 5 13 Serial Clock Selection and Application In the SBI Mode 5 120 Table 5 14 Various Signals Used in the SBI Mode 5 125 uPD75518 User s Manual TOC 13 Contents 2 2 Table 5 15 Serial Clock Selection and Application sene 5 150 Table 5 16 Setting of SCC and inneren 5 157 Table 6 1 SOULCOS En 6 3 Table 6 2 Set Signals for Interrupt Request Flags sse 6 6 Table 6 3 Interrupt Processing Statuses of ISTO and 1 6 15 Table 6 4 Determination of an Interrupt Source 6 19 Table 7 1 Operation Statuses in the Standby sse 7 3 Table 7 2 Selection of a Wait Time With 7 7 Table 8 1 Statuses of the Hardware after a Reset 8 2 Table 9 1 Pin Furctiorns oe C ee tt 9 1 Table 9 2 Operating Modes RR 9 3 TOC 14 uPD75518 User s Manual Chapter 1 General The uPD
8. 5 106 5 7 7 SBI Mode Operation icto t eene re dead 5 107 1 SB f nctions iuit radere ea rr Uses 5 109 2 gt definition EC ees 5 110 3 Register setting sss 5 116 4 Serial clock selection 2 2 5 120 Signals HERE 5 121 6 Pin configuration sse 5 127 7 Address match detection method 5 128 8 Error detection entere iere RES 5 128 9 Communication operation 5 129 10 T ranster Start se ee mE het Ps 5 134 11 Notes on the SBI mode 5 135 12 eer etiem 5 136 5 7 8 Manipulation of SCKO Pin 5 143 5 8 Serial Interface Channel 1 5 145 5 8 1 Serial Interface Channel 1 Functions 5 145 1 Operation halt 5 145 2 Three wire serial 5 145 5 8 2 Serial Interface Channel 1 Configuration 5 145 5 8 3 Register FUNCHONS icio terit e Ferrar terat 5 147 1 Serial operation mode register 1 CSIM1 5 147 2 Shift register 1 5 148 5 8 4 Operation Halt 5 148 5 8 5 Three Wire Serial Mode Operations
9. addr1 0000H 5F7FH uPD75517 0000H 7F7FH uPD75518 uPD75P518 Branches to the address specified by the 15 bit immediate data addr1 This instruction is an assembler pseudo instruction and the assembler automatically replaces this instruction with the BR addr instruction BRA addr1 instruction BRCB Icaddr instruction or BR addr instruction as required at assembly time BR Function PC44 9 lt lt addr addr 0000H 3FFFH Transfers the 14 bit immediate data addr to the program counter PC then branches to the location addressed by the program counter A branch can occur to any location in the 16K byte program memory space 0000H to 3FFFH BR addr Function PC44 9 lt addr addr PC 15 to PC 1 2 to PC 16 Relative branch instruction with branch ranges of 15 to 1 and 2 to 16 from the current address The instruction is not affected by page or block boundaries uPD75518 User s Manual Chapter 10 Instruction Set BR PCDE Function 14 lt 14 8 PCz 4 lt D PC3 9 lt E Branches to the address specified by the program counter whose low order 8 bits PC7 9 have been replaced with the contents of the DE register pair The high order bits of the program counter are not affected Caution The BR PCDE instruction usually causes a branch within the page containing the instruction However if the first byte of the instruction code is located
10. P U R P U R P U R enable gt P cn P n PUR Data IN OUT 50 enable Type D Output disable IN P U R Pull Up Resistor Schmitt trigger input with hysteresis uPD75518 User s Manual P U R Pull Up Resistor Chapter 2 Pin Functions Figure 2 1 Pin Input Output Circuits 2 3 BI Fr Pe Data IN OUT Type D O P U R Pull Up Resistor P U R enable Output disable P U R P U R ch enable s Output disable Pm DHE re Data A disce D gt Output TT disable N ch IN OUT P U R Pull Up Resistor IN OUT Output disable I O circuit consisting of a push pull output of type D and a Schmitt triggered input of type B Type F C P U R fp fr re Data IN OUT Type D O P U R enable Output disable Type B P U R Pull Up Resistor Type F A P U R enable Data IN OUT Type D O Output disable P U R Pull Up Resistor 0 P U R Mask option IN OUT oeoo Data N ch Withstand voltage Output 10 V disable Input buffer with an intermediate withstand voltage of 10 V P U R Pull Up Resistor uPD75518 User s Manual Figure 2 1 Input Output Circuits 3 3 IN OUT Data N ch Withstand Output
11. Operating mode Operating mode HALT mode low speed operation low speed high speed Operating mode CPU operation lt 250 ms INT4 INT4 uPD75518 User s Manual 7 11 Chapter 7 Standby Function lt Sample program gt INTBT INT4 service program MBE 0 BTAND4 SKTCLR IRQ4 INT4 1 BR VSUBBT NO SKT 0 POO 1 BR PDOWN Power down SETI BTM 3 Start BT WAIT SKT IRQBT Wait for 250 ms BR WAIT SKT 0 0 BR PDOWN MOV A 0011B High speed mode MOV PCC A El IEn lt 1 RETI PDOWN MOV A 0 Lowest speed mode MOV PCC A DI IEn IEn lt 0 Reserve 46 machine cycles Note SETHLT HALT HALT mode NOP RETI VSUBBT IRQBT Processing at intermittent operation BR SETHLT Note See Section 5 2 3 for switching between the system clock and CPU clock Caution Before the system clock is changed from the main system clock to the subsystem clock a wait time sufficient for stable subsystem clock generation is required uPD75518 User s Manual Chapter 8 Reset Function The 75518 is reset by a RESET signal When reset the hardware is initialized as indicated in Table 8 1 Figure 8 1 shows the timing of reset operation Figure 8 1 Reset Operation by a RESET signal Wait approximately 21 8 ms 6 0 MHz Note RESET input Operating mode or standby mode HALT mode Operating m
12. Rem uPD75518 User s Manual ark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output Chapter 5 Peripheral Hardware Functions 3 Clock output mode register CLOM The CLOM is a 4 bit register to control clock output The CLOM is set by a 4 bit memory manipulation instruction No read operation is allowed on this register A RESET signal clears the CLOM to 0 disabling clock output Example CPU clock is output on the PCL P22 pin SEL MB15 or CLR1 MBE MOV 1000 CLOM A Figure 5 21 Format of the Clock Output Mode Register Address 2 1 0 Symbol Clock output frequency selection bit Frequency when fx 6 0 MHz output 1 50 MHz 750 kHz 375 kHz 93 7 kHz ESES fx 2 output 750 kHz fx 2 output 375 kHz fx 2 output 93 7 kHz Frequency when fx 4 19 MHz por Tarte Te 5 23 output 524 kHz 26 output 65 5 kHz Note is the CPU clock supply selected by PCC Clock output enable disable bit E Output disable Output enable Caution Be sure to write a 0 in bit 2 of the CLOM uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 4 Application to remote control output The clock output function of the 75518 is applicable to remote control output The frequency of the carrier for remot
13. acknowledge detection circuit 510 5 1 gt P02 SO0 SBO P01 SCKO gt 1 output latch Serial clock control circuit Serial clock selector INTCSIO 2 set signal lt TOUT flip flop from timer event counter External SCKO 0 2195 ay weibeig Or s 941614 suonounJ 5 Chapter 5 Peripheral Hardware Functions 1 Serial operation mode register 0 CSIMO CSIMO is an 8 bit register which specifies a serial interface operation mode serial clock wake up function and so forth See 1 in Section 5 7 3 for details 2 Serial bus interface control register SBIC SBIC is an 8 bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus SBIC is used mainly in the SBI mode See 2 in Section 5 7 3 for details 3 Shift register 0 SIOO SIOO is an 8 bit register which converts 8 bit serial data to parallel data and 8 bit parallel data to serial data SIOO performs transfer shift in phase with the serial clock Transfers operations are controlled by writing data to SIOO See 3 in Section 5 7 3 for details 4 SOO latch 500 is a latch to hold the levels of pins SOO and 580 or 510 and 581 which
14. Remark Although not listed in Figure 4 2 the BR PCDE and BR instructions can cause a branch to an address with only the low order 8 bits of the PC changed uPD75518 User s Manual 4 Chapter 4 Internal CPU Functions Figure 4 3 Program Memory Map uPD75518 and uPD75P518 A A 0000H Internal reset start address high order 6 bits Internal reset start address low order 8 bits ooo2H MBE RBE INTBT INT4 start address high order 6 bits Entry address INTBT INT4 start address low order 8 bits specified in CALLE BR BCDE 0004H INTO start address high order 6 bits BR instruction branch address INTO start address low order 8 bits Branch address Branch address 0006H MBE RBE INT1 start address high order 6 bits specified in specified in INT1 start address low order 8 bits BRCB BRA addr Icaddr instruction 0008H MBE RBE INTCSIO start address high order 6 bits instruction Branch address INTCSIO start address low order 8 bits specified in CALLA addr 000AH MBE RBE INTTO start address high order 6 bits instruction INTTO start address low order 8 bits Relative Branch branch address 000CH INTTPG start address high order 6 bits address specified in specified in add INTTPG start address low order 8 bits BR addr instruction 15 to 1 2 to 16 Branch address specified in CALL
15. uPD75518 User s Manual 6 21 Chapter 6 Interrupt Function 2 When IRQn is set during an instruction other than that described in 1 a When IRQn is set at the last machine cycle of the instruction being executed In this case an instruction preceded by the instruction being executed is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started An instruction other than interrupt control instruction A B C D A IRQn is set B The next instruction is executed 1 to 3 machine cycles to the instruction C Interrupt processing 3 machine cycles D Interrupt service routine is executed Caution When one or more interrupt control instructions follow an instruction preceded by the interrupt control instructions is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started When an instruction to be executed after setting IRQn is a DI instruction the interrupt request of the set IRQn is held b When IRQn is set earlier than the last machine cycle of the instruction being executed In this case after executing the instruction being executed an interrupt process ing of three machine cycles is executed then the interrupt service routine is started An instruction other than interrupt control instruction gt A IRQn is set C Interrupt
16. 2 1 185 ay 5 sjeublg 1 lt suonounJ 4 5 921 9 jenuew 51955 grcc adr Signal 5 Output device Master Definition Synchronous clock for outputting address command data ACK signal synchronous BUSY signal and so on Address command data is output during first 8 clock cycles Timing chart SBO SB1 Address A7 AO Master 8 bit data transferred in phase with SCKO after REL signal and CMD signal output s LT eee REL CMD SBO SB1 Command C7 CO Master 8 bit data transferred in phase with SCKO after only CMD signal is output with REL signal not being output SCKO 2 z CMD SBO SB1 8S 916165 Joye poyeiiul si JoJsueJ ASN 941 ul 2 VAS 19481691 eui en eA ay sseJppe AjUO 195 S OISOOUI Master slave Jeu amp is 0405 jo Buisu eui uo 195 8 bit data transferred in phase with SCKO with neither REL signal nor CMD signal being output 015008 0 dM 0 SBO SB1 Condition for output Execution of instruction to write data to SIOO when CSIE
17. BR PC 44 9 lt 11 The assembler selects an appropriate instruction from the BR addr BRA addr1 BRCB caddr and BR addr instructions laddr 3 addr 1 PCDE PC44 lt 0 PC43 0 lt 6 PC44 9 lt addr 7 Branch PC44 0 lt PC14 g DE PCXA BCDE Note PC44 9 lt 14 8 PC44 9 lt Boo CDE 11 BCXA Note PC14 9 lt CXA 11 BRA laddr1 PC44 9 lt 11 BRCB PC44 9 lt 13 12 1 9 8 nm N N m N O laddr 5 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt 6 SP 5 0 PC44 PC4s5 PCy PC44 0 1 0 lt addr SP lt SP 6 CALLA addri 3 3 5 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt 11 SP 5 0 PCy PC44 0 addr SP SP 6 CALLF 2 3 5 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt PC 9 SP 5 0 PC44 PC45 PCy PC44 9 lt 0000 faddr SP lt SP 6 RET 1 3 PC44 0 lt SP SP 3 SP 2 X PC44 PC45 PC42 SP 1 XX MBE RBE lt SP 4 SP lt SP 6 Subroutine stack control RETS 1 3 5 PC44 9 lt SP SP 3 SP 2 Unconditionally X PC44 PC45 PC42 SP 1 x x MBE RBE lt SP 4 SP lt SP 6 Then skip unconditionally RETI 1 3 PC44 0 lt SP SP 3 SP 2 X PC44 PC45 PC42 SP 1 PSW lt SP 4 SP 5 SP lt 6 Note Only lower three bits are valid i
18. 10 53 10 4 15 Special Instructions sse 10 53 uPD75518 User s Manual TOC 7 Contents Appendix A Development 15 11111 A 1 Appendix Masked ROM Ordering Procedure B 1 Appendix C Revision 5 C 1 Appendix D Instruction 1 1 22 11 1161 316 D 1 0 1 Instruction Index By FUNCTION D 1 0 2 Instruction Index Alphabetical Order D 4 Appendix E Hardware Index 1 E 1 Hardware Index Alphabetical Order with Respect to the Hardware Name E 1 E 2 Hardware Index Alphabetical Order with Respect to the Hardware Symbol esee E 3 TOC 8 uPD75518 User s Manual Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Fig
19. gt y P ch e Pull up resistor o 2 2 Output latch O g Output buffer Pmn 5 Corresponding bits of m 3 6 port mode register group n 0to3 Note For port 6n only Figure 5 4 Configurations of Ports 2 and 7 e Pull up resistor P ch Bit m of 1 poca l Key interrupt PMm 1 AA Input buffer lt lt Input buffer with hysteresis Note o E tbe o Pmo Output gt orm latch 1 opima gt Pm3 Output buffer PMm Bits 2 and 7 of port mode register group B m 2 7 Note For port 7 only uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 5 Configurations of Ports 4 5 12 13 and 14 Pull up resistor Mask option 6 6 4 i The 75 518 has buffer mask options 0 1 e 2 5 gt O PmO Pm1 Output latch Pm2 output buffer PMm Bit of port mode register group B m 4 5 Ports 4 and 5 Bit of port mode register group C m 4 5 6 Ports 12 13 and 14 5 6 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 6 Con
20. pin and the Vss pin is too long or noise is generated on the IC pin a potential difference may occur between the and the Vss pin This may cause your program to malfunction e Connect the IC pin to the Vss pin keeping the wiring as short as possible Keep the wiring as short as possible MDO MD3 for uPD75P518 only These pins are provided for the uPD75P518 only MDO to MD3 select a mode for program memory PROM write verify operation Vpp for uPD75P518 only This is a program voltage input pin for program memory PROM write verify operation For normal use connect this pin to Vpp keeping the wiring as short as possible Vpp This is the positive power supply pin Vss This is the ground pin uPD75518 User s Manual Chapter 2 Pin Functions 2 3 Pin Input Output Circuits Figure 2 1 shows schematic diagrams of the circuitry of the uPD75518 Figure 2 1 Pin Input Output Circuits 1 3 Type A Type D Data H P ch Fen OUT IN ro gt Output N ch disable nT Push pull output which can be set to high impedance output CMOS input buffer off for both P ch and N ch Type B Type E IN Pata IN OUT Type D O Output disable O I O circuit consisting of a push pull output Schmitt trigger input with hysteresis of type D and an input buffer of type A Type B C Type E B
21. specification Port mode register group B Address 7 6 Symbol 5 4 3 2 1 0 Port 2 P20 P23 I O specification Port 4 P40 P43 I O specification Port 5 P50 P53 I O specification Port 7 P70 P73 I O specification Contents of specification Input mode Output buffer off Output mode Output buffer on Remark Don t care 5 10 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 9 Formats of Port Mode Registers 2 2 Port mode register group C Address 7 6 5 4 3 2 1 0 Symbol FEEH 14 PM13 12 PM11 PM10 PMGC Port 9 P90 P93 I O specification Port 10 P100 P103 I O specification Port 11 P110 P113 I O specification Port 12 P120 P123 I O specification Port 13 P130 P133 I O specification Port 14 P140 P143 I O specification Contents of specification Input mode Output buffer off Output mode Output buffer on Note To develop a program these bits must be set to 0 They correspond to PM8 and PM15 While this chip is an input only device an emulator has I O ports uPD75518 User s Manual 5 11 Chapter 5 Peripheral Hardware Functions 5 1 3 Digital Port Manipulation Instructions All ports contained in the 75518 are mapped to data memory space so that all data memory manipulation instruc
22. sse 5 18 VO Timing of Digital 2 2 222200000000000000000 enn 5 20 Block Diagram of the Clock Generator sees 5 22 Format of the Processor Clock Control 5 25 Format of the System Clock Control 5 26 External Circuit for the System Clock 5 27 External Circuit for the Subsystem Clock 5 28 Examples of Oscillator Connections which should be Avoided 5 29 Changing the System Clock and CPU 2 0000000000000000 5 34 Configuration of the Clock Output Circuit sse 5 85 Format of the Clock Output Mode Register 5 36 Application to Remote Control Output sss 5 37 Configuration of the Basic Interval Timer eene 5 38 Format of the Basic Interval Timer Mode 5 40 Block Diagram of the Clock 5 44 Format of the Watch Mode Hegister sss nnns 5 45 Block Diagram of the Timer Event 5 47 Timing of Count 5 48 Format of the Timer Eve
23. uPD75518 User s Manual Chapter 10 Instruction Set 10 4 2 Table Reference Instructions MOVT XA PCDE Function lt ROM PC44 g DE Transfers the low order four bits of the table data in program memory to the A register and the high order four bits to the X register The table data is addressed by the program counter PC with its low order eight bits PC7 9 exchanged with the contents of the DE register pair The table address is determined by the contents of the program counter PC present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of the pseudo instruction This instruction is useful for consecutive table data references Program memory 43 0 Table Table data H data L Table address uPD75518 User s Manual 10 29 Chapter 10 Instruction Set Caution The MOVT XA PCDE instruction usually references table data in the page containing that instruction However when the instruction is located at address xxFFH table data in the next page is referenced instead of table data in the page containing that instruction Program memory 7 0 Page 2 02 0300H Page 3 For example if MOVT XA PCDE is located at a as shown above the table data in page 3 specified by the contents of the DE register pair is t
24. 80 15 When MBE 1 MBS 4 bit register Address specified by MB and HL indirect In this case MB 5 addressing Address specified by MB and HL HL In this case MBE MBS HL automatically increments the L register after addressing HL automatically decrements the L register after addressing DE Address specified by DE in memory bank 0 DL Address specified by DL in memory bank 0 8 bit register Address specified by MB and HL indirect In this case MB MBE MBS addressing Bit 0 of the L register is ignored Bit fmem bit Bit specified by bit at the address specified by fmem manipulation In this case addressing fmem FBOH FBFH interrupt related hardware FFOH FFFH I O ports pmem L Bit specified by the low order two bits of the L register at the address specified by the high order 10 bits of pmem and the high order two bits of the L register In this case pmem FCOH FFFH H mem bit Bit specified by bit at the address specified by MB H and the low order four bits of mem In this case 5 Stack Address specified by the stack pointer SP in memory addressing bank 0 1 2 or 3 selected by the stack bank select register SBS uPD75518 User s Manual 3 5 Chapter 3 Data Memory Operations and Memory 1 1 bit direct addressing mem bit In this addressing mode the operand of an instruction can directly specify any bit in the e
25. Input Also 8 Pin output used Function bit When reset circuit as 120 123 E N ch open drain 4 bit port x High level when a M PORT12 pull up resistor is M A Note 2 A pull up resistor can be provided provided or high bit by bit mask option Note 1 impedance Withstand voltage is 10 V in open drain mode P130 P133 N ch open drain 4 bit port x High level when a M PORT13 pull up resistor is M A Note 2 A pull up resistor can be provided provided or high bit by bit mask option Note 1 impedance Withstand voltage is 10 V in open drain mode P140 P143 N ch open drain 4 bit port x High level when a M PORT14 pull up resistor is M A Note 2 A pull up resistor can be provided provided or high bit by bit mask option Note 1 impedance Withstand voltage is 10 V in open drain mode P150 P153 Input AN4 AN7 4 bit input port PORT15 x Input Y A Note 1 The 75 518 does not contain pull up or pull down resistors specified by the mask option Note 2 The data in parentheses applies only to the uwPD75P518 uPD75518 User s Manual Chapter 2 Pin Functions Table 2 2 Non port Pin Functions 1 2 Note 1 Input Also Pin output used Function When reset circuit as type TIO Input External event pulse input for timer event counter C PTOO Output P20 Timer event counter output Input E B PCL Output P22 Clock output Input E B BUZ Output P23 F
26. 10 48 Internal bus 8 SET1 Note 1 8 TMO TMODO TOEO PORT2 0 Bit 2 of PGMB P20 Port 2 TO enable output input TMO6 TMO05 TMO4 TMO3 2 Modulo register 8 flag latch output signal mode To serial interface Match TOUT Comparator 8 flip flop P20 PTOO Output Reset buffet Input buffer Do To P13 gt 1 INTTO TIO Count register 8 gt IROTO Note 2 MPX set signal From the Clear signal clock generator Timer operation start signal RESET IRQTO clear signal ZZ Sc II 5 8 76 5 2 2 1 3 ou Jo YIO g 7z s 4 suonounJ 5 Chapter 5 Peripheral Hardware Functions 5 5 2 Basic Configuration and Operation of the Timer Event Counter The timer event counter has several operation modes A mode can be selected by the timer event counter mode register TMO The basic configuration and operation of the timer event counter are described below 1 2 The count pulse CP is selected by setting TMO and is set in the 8 bit count register TO TO is a binary 8 bit up counter incremented by one each time the CP is applied TO is cleared to 0 when a RESET signal is generated bit 3 of TMO is set to start the timer or a match signal occurs TO can be read at any time with an 8 bit memo
27. 5 60 5 6 2 Timer Pulse Generator Mode Register TPGM 5 61 5 6 3 Configuration and Operation of the Timer Pulse Generator 5 62 5 6 4 Application of the Timer Pulse Generator 5 68 5 7 Serial Interface Channel 0 5 73 5 7 1 Serial Interface Channel 0 Functions 5 73 1 Operation halt 5 73 2 Three wire serial 5 73 3 Two wire serial mode 5 74 4 Serial bus interface SBI 5 74 5 7 2 Configuration of Serial Interface Channel 0 5 74 1 Serial operation mode register 0 51 0 5 76 2 Serial bus interface control register SBIC 5 76 3 Shift register 0 100 5 76 4 SOO latClis ema ene 5 76 5 Serial clock selector 5 76 6 Serial clock counter 2 5 76 7 Slave address register SVA and address comparator 5 76 8 INTCSIO control 2 004000 0 5 77 9 Serial clock control 5 77 10 Busy acknowledge output circuit and bus release command acknowledge detection circuit 5 77 11 01 output latch 5 77 5 7 3 Register FUN
28. 6 mw p em pre o aw o 0 me e m m aw Te Bit sequential buffer 0 8580 Bit sequential buffer 1 BSB1 FC2H Bit sequential buffer 2 8582 R W FC3H Bit sequential buffer 3 8583 R W Only bit 7 can be manipulated Serial shift register 1 5100 Remarks 1 lExxx is an interrupt enable flag 2 ERQxxx is an interrupt request flag Chapter 3 Data Memory Operations and Memory Figure 3 7 uPD75518 3 4 Address Number of bits that Bit Hardware name um can be manipulated manipulation Komma 1 1 b3 1 bit write E 1 bit read Pull up resistor specification register group A POGA b6 1 bit read All bits allow bit manipula tion only Note In program development the following bits in port mode register group C PMGC must be set to 0 bO corresponding to 8 FEFH b3 corresponding to PM15 This is because ports are specified on the emulator while on the 75518 input ports are specified 3 26 uPD75518 User s Manual Figure 3 7 75518 I O Map 4 4 Chapter 3 Data Memory Operations and Memory Hardware name symbol FFOH FF1H FF2H Port 2 PORT2 Port 6 PORT6 dn E E EE Dm olm Dm Port 7 PORT7 Fre Port 8 PORTS FFCH Port 12 PORT12 wo L
29. A RESET signal clears IM2 to zero In this case the test flag IRQ2 is set by a rising edge on the INT2 pin INT2 can also be used to release the STOP and HALT modes A Schmitt triggered input is used for this pin 2 2 12 KRO KR3 Inputs Used Also for Port 6 KR4 KR7 Inputs Used Also for Port 7 KRO to KR7 are key interrupt input pins An interrupt is caused when parallel falling edges are detected on them The interrupt format can be specified with the edge detection mode register IM2 A RESET signal places these pins in the port 6 and 7 input modes 2 2 13 PPO Output Uses Also as Port 8 2 2 14 2 2 15 2 2 16 This is the pin for outputting a pulse signal from the timer pulse generator A PWM or square wave pulse signal can be output on this pin If no pulse output is needed the PPO pin can be used as a 1 bit output port When a RESET signal occurs or when the high impedance mode is set by the timer pulse generator mode register TPGM the PPO pin enters the input mode output high impedance state ANO AN3 AN4 AN7 Input Used as Port 15 These pins are analog signal inputs to the A D converter AVREF This is the reference voltage input pin for the A D converter AVss This is the ground pin for the A D converter Always use the same voltage as that of the Vss pin uPD75518 User s Manual Chapter 2 Pin Functions 2 2 17 X1 X2 These pins are used for connection to a crystal or c
30. Other than above 0 Approx 220 fx Approx 175 ms Approx 217 fy Approx 21 8 ms Approx 215 fy Approx 5 46 ms Approx 213 fy Approx 1 37 ms Use prohibited When fy 4 19 MHz BTM3 BTM2 1 Wait time Note indicates the value for fy 4 19 MHz 0 0 1 1 Other than above 0 Approx 220 fx Approx 250 ms Approx 217 fy Approx 31 3 ms Approx 215 fy Approx 7 82 ms Approx 213 fy Approx 1 95 ms Use prohibited Note This time does not include the time from the release of the STOP mode to the start of oscillation Cautions 1 The wait times used when the STOP mode is released do not include the time a in the figure below required before clock oscillation is started following the release of the STOP mode regardless of whether the STOP mode is released by a RESET signal or the generation of an interrupt Since the frequency has yet to settle at the start of oscillation if noise having a frequency higher than that being used is input that noise may function as a clock In this case the wait time may be shorter than the initially set time Set a longer interval until oscillation starts Waveform atthe X1 pin STOP mode release uPD75518 User s Manual Chapter 7 Standby Function 7 3 Operation after a Standby Mode Is Released 1 2 Ifa standby mode is released by a RESET signal normal reset operation is per
31. RELD Condition for being cleared RELD 0 Condition for being set RELD 1 1 The transfer start instruction The bus release signal REL is detected is executed 2 The RESET signal is entered 3 CSIEO 0 Figure 5 41 4 SVA does not match 5100 when an address is received Command detection flag R CMDD Condition for being cleared 0 Condition for being set CMDD 1 1 The transfer start instruction The command signal CMD is detected is executed 2 bus release signal REL 3 The RESET signal is entered 4 CSIEO 0 Figure 5 41 uPD75518 User s Manual 5 83 Chapter 5 Peripheral Hardware Functions Figure 5 42 Format of Serial Bus Interface Control Register SBIC 3 3 Acknowledge trigger bit W ACKT When set after transfer ACK is output in phase with the next SCKO After ACK signal output this bit is automatically cleared to 0 Cautions 1 Never set ACKT before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE 0 Acknowledge enable bit R W 0 Disables automatic output of the acknowledge signal ACK Output by ACKT is possible 1 When set before transfer ACK is output in phase with the 9th clock of SCKO When set after transfer ACK is output in phase with SCKO immediately following the set instruction execution Acknowledge detection flag
32. Undefined uPD75518 User s Manual Chapter 8 Reset Function MEMO 8 4 uPD75518 User s Manual Chapter 9 Writing to and Verifying Program Memory PROM The program memory in the uPD75P518 consists of a one time PROM which be written into only once or consists of an EPROM which can be erased and reprogrammed The memory capacity is as follows uPD75P518 32640 words x 8 bits Writing to and verifying the contents of the one time PROM is accomplished by using the pins shown in Table 9 1 Note that address inputs are not used instead the address is updated using the clock input from the X1 pin Table 9 1 Pin Functions Pin name Function X1 X2 Address update clock inputs used when writing to the program memory or verifying its contents The X2 pin is used to input the inverted signal of the X1 pin input MDO MD3 Operation mode selection pins used when writing to the program P30 to P33 memory or verifying its contents P40 to P43 low I O pins for 8 bit data used when writing to the program memory or order four bits verifying its contents P50 to P53 high order four bits Vpp Power voltage is applied to this pin During normal operation 2 7 to 6 0 V should be applied 6 V should be applied when writing to the program memory or verifying its contents Vpp Voltage is applied to this pin when writing to the program memory or verifying its contents normally Vpp electric potential Cautions 1 Pin
33. 10 1 3 String Effect Instructions With the uPD75518 two types of string effect instructions are available a MOV A n4 or MOV XA n8 b MOV HL n8 String effect means the locating of these two types of instructions at contiguous addresses Example AO MOV A 0 A1 MOV A 1 XA7 MOV XA 07 When string effect instructions are arranged as in this example if execution starts at address 0 the following two instructions are replaced with an NOP instruction If execution starts at address A1 the following one instruction is replaced with an NOP instruction That is only the instruction first executed is valid and any following instructions are processed as an NOP instruction By using string effect instructions a constant can be set in an accumulator the A register or the XA register pair or data pointer the HL register pair more efficiently uPD75518 User s Manual 10 5 Chapter 10 Instruction Set 10 1 4 Number System Conversion Instructions An application may need to convert the result of a 4 bit data addition or subtraction performed in binary to a decimal number A time related application may require sexagesimal conversion For this reason the instruction set of the uPD75518 contains number system conversion instructions for converting the result of a 4 bit data addition or subtraction to a number in an arbitrary number system a Number system conversion for addition Let m be a desired number system
34. 5 1 PSW 4 14 R RBE 4 17 RBS 4 18 RELD 5 83 RELT 5 83 S SA 5 155 SBIC 5 82 SBS 4 11 SCC 5 26 SIOO 5 85 SIO1 5 148 SKO SK1 SK2 4 16 SOC 5 154 SP 4 11 SVA 5 87 T TO 5 48 5 51 TMO 5 49 5 48 W WM 5 45 WUP 5 80 uPD75518 User s Manual
35. A memory bank is specified in the same way as the 4 bit direct addressing This addressing mode can be applied to the MOV XCH IN and OUT instructions Example 1 Eight bit data from port 4 and port 5 is transferred to addresses 20H and 21H and the original data at addresses 20H and 21H is output on ports 6 and 7 DATA EQU 020H CLR1 MBE MBE lt 0 IN XA PORTA XA lt PORT5 and PORT4 XA DATA XA lt gt 21H 20H OUT PORT6 XA Ports 7 and 6 lt XA Example 2 Eight bit data is latched into the serial interface shift register 0 5100 and the transfer data is set at the same time SEL 15 MBS lt 15 5100 XA lt gt 5100 3 8 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory 4 4 bit register indirect addressing rpa In this addressing mode the pointer general register pair specified in the operand of an instruction indirectly specifies a data memory space in units of four bits There are three types of data pointers One is the HL register pair which can specify any area in the data memory space when MB MBE MBS is specified The other two are the DE register pair and DL register pair with which memory bank 0 is always used regardless of how the MBE and MBS are specified More efficient programming is possible by selecting a data pointer according to a data memory bank to be used When the HL register pair is specified the L register can be increme
36. CSIMO is manipulated using an 8 bit memory manipulation instruction The higher three bits can be manipulated bit by bit Each bit can be manipulated using its name Each bit may or may not allow read and or write operation see Figure 5 41 Bit 6 allows bit test operation only any data written to this bit is invalid When the RESET signal is input this register is set to OOH Figure 5 41 Format of Serial Operation Mode Register 0 CSIMO 1 3 Address Symbol 7 6 5 4 3 2 1 0 CSIEO csimo4 CSIMO3 csimoz2 csimot CSIMOO FEOH CSIMO Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Signal from address comparator R Serial interface operation enable disable specification bit W Remark Read only W Write only 5 78 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 41 Format of Serial Operation Mode Register 0 CSIMO 2 3 Serial clock selection bit W CSIMO1 CSIMOO Serial clock SCKO pin mode 3 wire serial mode SBI mode 2 wire serial I O mode 0 0 Input clock externally applied to SCKO pin Input 0 1 Timer event counter output TO Output 1 0 fy 24 262 kHz or 375 kHz Note fy 26 65 5 kHz 93 8 kHz Note 1 1 fy 23 524 kHz or 750 kHz Note Note The values in parentheses are for fy 4 19 MHz or 6 0 MHz Serial int
37. Note 2 MS DOS versions 5 00 and 5 00A provide a task swap function This function however cannot be used in these software packages Remark The IE control program and the assembler can run only on the host machine under the uPD75518 User s Manual OS mentioned above jenuew 51955 8grcc adi Centronics interface _ et Host machine PC 9800 series IBM PC AT Symbolic debugging is possible 2 2 d 2 27 RS 232 C IE control program PG 1500 controller In circuit emulator IE 75000 R Emulation probe IE 75001 R Nete 1 EP 75516GF R IE 75000 R EM 80 pin conversion socket EV 9200G 80 User sysytem Product containing PROM PROM programmer LL PD75P518GF one time 75 518 WQFN PG 1500 Relocatable assembler Programmer adapter PA 75P516GF ete 2 PA 75P516K Note 3 0 5 22970260 52 024 000700 o 1591 505 65 89 20 3 po m mo 2 cz 70 TU lt m5 5 88 22 TU gt 96952 o 1 padi A Q 4 1001 Y xipueddy Appendix B Masked ROM Ordering Procedure After program development for the uPD75518 is completed the masked ROM is ordered by the following
38. 10 36 A HL 10 35 1 10 36 XA rp 10 36 addr 10 47 addr 10 49 A rpa 10 27 A mem 10 28 A reg1 10 28 XA HL 10 27 XCH XCH XOR XOR XOR XOR XOR1 XOR1 XOR1 XA mem 10 28 XA rp 10 28 A n4 10 38 A HL 10 38 rp 1 XA 10 38 10 38 CY fmem bit 10 44 CY pmem L 10 44 CY H mem bit 10 44 uPD75518 User s Manual A Acknowledge detection flag 5 84 Acknowledge enable bit 5 84 Acknowledge trigger bit 5 84 A D conversion mode register 5 153 B Basic interval timer 5 38 Basic interval timer mode register 5 39 Bit sequential buffers 5 162 BT interrupt enable flag 6 5 BT interrupt request flag 6 5 Bus release detection flag 5 83 Bus release trigger bit 5 83 Busy enable bit 5 84 C Carry flag 4 15 Clock output mode register 5 36 Command detection flag 5 83 Command trigger bit 5 83 Conversion completion detection flag 5 154 uPD75518 User s Manual Appendix E Hardware Index E 1 Hardware Index Alphabetical Order with Respect to the Hardware Name Conversion start direction bit 5 154 E Edge detection mode register 6 10 I Interrupt priority specification register 6 13 Interrupt status flag 4 16 6 15 INTO interrupt enable flag 6 5 INT1 interrupt enable flag 6 5 INT2 interrupt enable flag 6 5 I
39. 3 6 7 and 9 to 11 Ports 2 6 and 7 function as I O ports and also have the following functions Port 2 Timer event counter PTOO Clock output PCL Fixed frequency output BUZ Ports 6 and 7 Key interrupt input KRO KR3 KR4 KR7 Port 3 is a high current output It can directly drive the LED An I O mode is selected by the port mode register The I O mode of ports 2 7 and 9 to 11 can be selected in units of 4 bits and the I O mode of ports 3 and 6 can be selected bit by bit The use of built in pull up resistors can be software selected for ports 2 3 6 and 7 in 4 bit units This can be done by manipulating pull up resistor specification register group A POGA For ports 4 and 5 the use of built in pull up resistors can be specified bit by bit by mask option For port 9 the use of built in pull down resistors can be specified bit by bit by mask option Ports 6 and 7 can be paired for 8 bit I O A RESET input clears the output latches in the ports to zero places ports 2 3 6 7 10 and 11 in the input mode output high impedance state and drives port 9 low if pull down resistors are provided or causes port 9 to go into a high impedance state uPD75518 User s Manual 2 7 Chapter 2 Pin Functions 2 2 3 P40 P43 PORTA P50 P53 PORTS P120 P123 PORT12 P130 P133 PORT13 P140 P143 PORT14 N ch Open Drain I O 2 2 4 2 2 5 2 2 6 2 2 7 These pins are the I O pins of the N ch open drain 4 bit I O
40. 4 01101411110 8 10 11100 1 l lg l5 l4 lg lo H l A HL 11010010 XA rp 101010101100 1 PoP Po rp1 XA 101010101 1 0 0 0 PoP Po ADDC A HL 10101001 XA rp 101010102110 1 1 PoP rp1 XA 10101010110 1 0 PoP Po SUBS A HL 10101000 XA rp 1010101011 1 0 1 PoP Po rp1 XA 1010101011 1 0 0 PoP Po SUBC A HL 10111000 XA rp 101010101111 1 PoP Po rp1 XA 10101201011 1 1 0 PoP Po AND A n4 10011001001 1 l lo Hh p A HL 10010000 XA rp 101010101001 1 PoP Po rp1 XA 10101010100 1 0 PoP Po OR 4 10011001021 001 15 Hh lo A HL 10100000 XA rp 101010101010 1 PoP Po rp1 XA 1010101010 1 0 0 PoP Po XOR 4 10 011001010166 A HL 10110000 XA rp 10101010101 1 1 PoP Po rp1 XA 1010101010 1 1 0 PoP Po Accumulator A 10011000 1001100101011111 uPD75518 User s Manual 10 21 Chapter 10 Instruction Set Instruction Mnemonic Operand Instruction code B B2 B3 Increment INCS reg 1 0 0 0 RoR rp1 000 1 PoP 0 HL 001100100000010 mem 0000 0 1 05 06505 D4 D3 Do 0 Do DECS reg 1 0 0 1 RoR Ro rp 010101001 1 0 1 P2 P Po Comparison SKE reg n4 00 110101 15 l 0 RoR Ro HL n4 0011001011011 H lp AQ HL 0000000 XA HL 010101000011001 A reg 00110010000 1 RoR XA rp 01010100100 1 P2 P Po Carry flag SET1 CY 1100111 CLR1 CY 1100110 SKT CY 1010111 NOT1 CY 1010110 Memory bit SET1 me
41. CMDT and CMDD 5 121 Operations of RELT CMDT RELD and CMDD 5 5 121 Operation Of iie doe eliam egest exe eden etd levee ek 5 122 Operation OF ACKE tL ce eL ge ce al ave 5 123 Operation OF ACKD iini tos itat d Pe ERR RR EA Ea OR ded 5 124 Operation 5 speed edidi cde aea 5 124 Pin Gonflg ratlon ss s qud a bused caves HR 5 127 Adaress Transfer Operation from Master Device to Slave Device WUP S itii et tei ente tte be teme 5 130 Command Transfer Operation from Master Device to Slave Device 5 131 Data Transfer Operation from Master Device to Slave Device 5 132 Data Transfer Operation from Slave Device to Master Device 5 133 Example of Serial Bus Configuration essen 5 136 Transfer Format of the READ Command sese 5 138 Transfer Format of the WRITE and END 5 5 139 Transfer Format of the STOP Command sese 5 139 Transfer Format of the STATUS Command sese 5 140 Status Format of the STATUS Command sese 5 140 Transfer Format of the RESET Command eese 5 141 Transfer Format of the CHGMST Command 5 141 Master and Slave Operation in
42. Communication is completed when the selected slave is placed in the non selected state This state is caused in the following cases The selected slave is placed in the non selected state when the slave receives a RESET command from the master The device that is switched from the master to a slave with a CHGMST command is placed in the non selected state 5 137 Chapter 5 Peripheral Hardware Functions lt Command format gt The transfer format of each command is described below lt 1 gt READ command The READ command reads data from a slave One to 256 bytes of data can be read The data length is specified in a parameter by the master When OOH is specified as the data length the 256 byte data transfer is assumed Figure 5 73 Transfer Format of the READ Command Data Data Data Remarks M Output by the master 5 Output by the slave When the slave receives a transmission data count if it has data enough for transmit ting the specified number of bytes of data the slave returns ACK If the slave does not have enough data for transmission an error occurs ACK is not returned in this case The master sends ACK to the slave each time it receives one byte 5 138 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions lt 2 gt WRITE command END command STOP command These commands write data to a slave One to 256 bytes of data can be written The data length is specified in a para
43. Figure 5 32 Error at the Start of the Timer Count register Count pulse CP c Timer start Timer start 2 uPD75518 User s Manual Notes on the start of the timer Usually when the timer is started TMO 3 1 the count register TO and the interrupt request flag IRQTO are cleared However when the timer is placed in the operation mode and the setting of IRQTO and the start of the timer occur at the same time IRQTO may not be cleared This causes no problem if IRQTO is used for a vectored interrupt However if IRQTO is being tested a problem arises because IRQTO is set even if the timer is started Accordingly in a situation where the timer is started on such timing that IRQTO may be set the timer must be restarted after it is once stopped TMO 2 0 or timer start operation must be performed twice Example The timer is started on such timing that IRQTO may be set SEL MB15 MOV XA 0 MOV TMO XA Stop the timer MOV XA 4CH MOV TMO XA Restart or SEL MB15 0 3 SET1 TMO 3 Restart Chapter 5 Peripheral Hardware Functions 3 Error in reading the count register The contents of the count register can be read using an 8 bit data memory manipulation instruction at any time During operation by such an instruction all count pulse changes are held not to change the count register This means that if the count pulse signal source is applied to the
44. In the operation halt mode Slave CPU SCKO masked when CSIEO 0 8 bit data lt 2 gt When the serial clock is masked 0 1 TOUT transfer is after 8 bit transfer Half duplex asyn flip flop completed 3 When SCKO is high chronous transfer software control 1 0 fx 24 Middle speed serial transfer 1 1 fx 23 High speed serial transfer 4 Signals Figure 5 46 shows operations of RELT and CMDT Figure 5 46 Operations of RELT and CMDT 500 latch RELT CMDT uPD75518 User s Manual 5 Chapter 5 Peripheral Hardware Functions Switching between MSB and LSB as the first transfer bit The three wire serial I O mode has a function that can switch between the MSB and LSB as the first bit of transfer Figure 5 47 shows the configuration of shift register 0 SIOO and internal bus As shown in Figure 5 47 read or write operation can be performed by switching between the MSB and LSB This switching can be specified using bit 2 of serial operation mode register 0 CSIMO Figure 5 47 Transfer Bit Switching Circuit 7 6 Internalbus 4 4 4 3255 1 M 0 LSB first MSB first Read write gate Read write gate 4 500 latch 510 Shift resister 0 5100 o 00 lt SCKO uPD75518 User s Manual The first bit is switche
45. Information requesting the user s special attention Supplementary information Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Related Documents Documents related to the device Product Document 075517 uPD75518 uPD75P518 Data Sheet 2672 2706 2839 User s Manual This manual Application Note Basic IEM 1259 A D Converter IEA 1236 75X Series Selection Guide IF 1027 Documents related to development tools Document name Document No Hardware IE 75000 R IE 75001 R User s Manual EEU 1416 IE 75000 R EM User s Manual EEU 1294 EP 75516GF R EEU 1315 PG 1500 User s Manual EEU 1335 Software RA75X Assembler Package User s Manual Operation EEU 1346 Language EEU 1343 PG 1500 Controller User s Manual EEU 1291 Other documents Document name Document No Package Manual IEI 1231 SMD Surface Mount Technology Manual IEI 1207 Quality Grades on NEC Semiconductor Devices IEI 1209 Guide to Quality Assurance for Semiconductor Devices IEI 1202 Caution Theabove documents may be revised without notice Use the latest versions when designing an application system MEMO Summary of Contents Chapter 1 General 1 1 Chapter 2 Pin 2 1 Chapter 3 Data Memory Operations and Memory Map 3 1 Chapter 4 Internal CPU Functions e 4 1 Chapter 5 Peripheral Hardware
46. PWM pulse generation mode PWM pulse output to the PPO pin with an accuracy of 14 bits applicable for electronic tuning when used as an D A converter e Generation of interrupts at regular intervals 215 fy 5 46 ms At 6 0 MHz Note Note 4 19 MHz 215 fy 7 81 ms If pulse output is unnecessary the PPO pin can be used as a 1 bit output port 5 60 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 6 2 Timer Pulse Generator Mode Register TPGM The timer pulse generator mode register TPGM is an 8 bit register that controls operation of the timer pulse generator Figure 5 33 shows the format of the register TPGM is set using an 8 bit memory manipulation instruction Bit 3 enables or disables the transfer reloading of the timer pulse generator modulo register MODH and MODL contents to the modulo latch Bit 3 can be manipulated independently of the other bits By setting TPGM1 to 0 timer pulse generator operation can be stopped to decrease current consumption A RESET signal clears all bits to O Figure 5 33 Format of Timer Pulse Generator Mode Register 2 Address 7 6 5 4 3 1 0 Timer pulse generator operation mode selection bit 2 ymbol E Select PWM pulse generation mode TPGMO Select timer mode Timer pulse generator operation enable disable bit 0 Disable timer pulse generator operation TPGM1 1 Enable timer pulse generator operation Modulo register reload enab
47. RBE PORTn IME IPS RBS MBS BS PCC xx Chapter 10 Instruction Set A register 4 bit accumulator B register 4 bit accumulator C register 4 bit accumulator D register 4 bit accumulator E register 4 bit accumulator H register 4 bit accumulator L register 4 bit accumulator X register 4 bit accumulator Register pair XA 8 bit accumulator Register pair BC 8 bit accumulator Register pair DE 8 bit accumulator Register pair HL 8 bit accumulator Extended register pair XA Extended register pair BC Extended register pair DE Extended register pair HL Program counter Stack pointer Carry flag bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n n 0 to 15 Interrupt master enable flag Interrupt priority specification register Interrupt enable flag Register bank select register Memory bank select register Bank select register Processor clock control register Address bit delimiter Contents addressed by xx Hexadecimal data 10 9 Chapter 10 Instruction Set 3 Explanation of symbols used for the addressing area column MB MBE MBS MBS 0 1 2 3 15 0 MBE 0 MB 0 000H 07FH MB 15 FB0H FFFH og memory MBE 1 MB MBS MBS 0 1 2 3 15 ee MB 15 fmem FBOH FBFH FFOH FFFH MB 15 pmem FCOH FFFH A addr 0000H 3F7FH
48. SKE XA HL XA HL Example 2 The data memory of 00H to FFH is cleared to 0 CLR1 CLR1 MBE MOV MOV HL 04H LOOP MOV HL XA HL lt XA INCS INCS BR LOOP 3 12 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory 6 Bit manipulation addressing uPD75518 User s Manual This addressing mode is used to perform bit manipulations such as Boolean operations and bit transfer for each bit in the data memory space The 1 bit direct addressing mode can be applied only to the set reset and test instructions On the other hand the bit manipulation addressing enables a wide variety of bit manipulations such as Boolean operations using the AND1 OR1 and instructions bit transfers using the instruction and test and reset operations using the SKTCLR instruction There are three types of bit manipulation addressing The user can choose from these options according to the data memory address used a Specific address bit direct addressing fmem bit In this addressing mode peripheral equipment that frequently performs bit manipulations involving for example I O ports and interrupt flags can be processed at all times regardless of memory bank setting Accordingly the data memory addresses that allow this addressing mode to be used are FFOH to FFFH where I O ports are mapped and FBOH to FBFH where interrupt related hard ware is mapped Hardw
49. addr Current PC 15 to Current PC 1 addr Current PC 2 to Current PC 16 caddr 0000H OFFFH PC 4 15 12 0008 All models 1000H 1FFFH PC14 13 12 0018 All models 2000H 2FFFH PC14 13 12 0108 All models 3000H 3FFFH PC14 13 12 0118 All models Program memory 4000H 4FFFH PC14 13 12 1008 All models addressing 5000H 5F7FH PC14 13 12 1018 uPD75517 5000H 5FFFH PCi14 13 12 1018 75518 uPD75P518 6000H 6FFFH PCi14 13 12 1108 75518 uPD75P518 7000H 7F7FH 13 12 1118 75518 75 518 faddr 0000H 07FFH taddr 0020H 007FH 0000H 5F7FH uPD75517 addr1 0000H 7F7FH uPD75518 75 518 Remarks 1 MB represents an accessible memory bank 2 For 2 MB 0 regardless of the setting of MBE and MBS 3 For 4 and 5 MB 15 regardless of the setting of MBE and MBS 4 Each of 6 to 11 indicates an addressable area 10 10 uPD75518 User s Manual Chapter 10 Instruction Set 4 Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation S assumes one of the following values e When no skip operation is performed 0 When a 1 byte instruction or 2 byte instruction is skipped S 1 When a 3 byte instruction Note is skipped S 2 N
50. fmem bit lt 0 4 pmem L 2 2 pmem7 2 L3 2 bit L4 0 lt 0 5 H mem bit 2 2 H mems o bit lt 0 1 SKT mem bit 2 248 Skip if mem bit 1 3 mem bit 1 fmem bit 2 248 Skip if fmem bit 1 4 fmem bit 1 pmem L 2 248 Skip if pmem z 2 L3 bit L1 9 21 55 pmem L 1 5 H mem bit 2 248 Skip if H mems o bit 1 1 H mem bit 1 3 SKF mem bit 2 248 Skip if mem bit 0 3 mem bit 0 E fmem bit 2 2 5 Skip if fmem bit 0 4 fmem bit 0 5 pmem L 2 248 Skip if pmem z 2L3 bit L 9 0 5 pmem L 0 S H mem bit 2 248 Skip if H mems o bit 0 1 H mem bit 0 gt SKTCLR fmem bit 2 248 Skip if fmem bit 1 and clear 4 fmem bit 1 pmem L 2 248 Skip if pmem7 2 L3 2 bit Ly 9 1 and clear 5 pmem L 1 H mem bit 2 248 Skip if H mem3 9 bit 1 and clear 1 H mem bit 1 AND1 CY fmem bit 2 2 CY lt CYA fmem bit 4 CY pmem L 2 2 CY lt CYA pmem z o Ls bit L1 0 5 CY H mem bit 2 2 CY lt CYA H mems p bit 1 OR1 CY fmem bit 2 2 CY lt CYv fmem bit 4 CY pmem L 2 2 CY lt CYv pmem7 o L3 2 bit Ly 9 5 CY H mem bit 2 2 CY lt CYv H mems o bit 1 XOR1 CY fmem bit 2 2 CY lt CY fmem bit 4 CY pmem L 2 2 CY lt pmem7 o L3 2 bit Ly 9 b5 CY H mem bit 2 2 CY lt CY H mems3_o bit 1 uPD75518 User s Manual 10 15 Instruction Set Chapter 10 Instruction Set Instruc Mne Number Machine Address tion monic Operand of cycle Operation ing area Skip condition bytes
51. input output port utilization Serial bus interface SBI mode In this mode communication with multiple devices can be performed using two lines Serial clock SCKO and serial data bus SBO or SB1 This mode conforms to the NEC serial bus format In this mode the transmitter can output on the serial data bus an address for selecting a device subject to serial communication commands directed to the remote device and data The receiver can identify an address commands and data from received data by hardware This function enables more efficient input output port utilization as in the case of the two wire serial mode In addition this function can simplify the serial interface control portion of an application program Figure 5 39 Example of the SBI System Configuration Ms Master CPU Serial clock Slave CPU eee SCKO Address 1 580 581 Address gt Command L gt Data Address N 5 7 2 Configuration of Serial Interface Channel 0 Figure 5 40 shows the block diagram of the serial interface channel 0 uPD75518 User s Manual jenuew 5 1951 8rcc adr 92 9 Internal bus Bit manipulation Coincidence signal RELT D Q Bus release SET CLR 500 latch ACKT ACKE BSYE Busy acknowledge output circuit Bit test command
52. or high order interrupt occurrence uPD75518 User s Manual 6 17 Chapter 6 Interrupt Function 2 Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled That is when the interrupt processing program changes both IST1 and ISTO to 0 status 0 multiple interrupt processing is enabled This method is used when two or more interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed When changing IST1 and ISTO interrupts must be disabled beforehand with a DI instruction Figure 6 10 Multiple Interrupt Processing by Changing the Interrupt Status Flags Interrupt is disabled Interrupt is enabled Low or high order interrupt occurrence Normal processing status 0 IPS setting Low or high order interrupt occurrence Interrupt is disabled Modification of IST Interrupt is enabled Single interrupt High order interrupt occurrence Dual interrupts Triple interrupts Status 1 Status 2 uPD75518 User s Manual Chapter 6 Interrupt Function 6 6 Processing of Interrupts Sharing a Vector Address Interrupt sources INTBT and INT4 share a vector table so an interrupt source is selected as described below 1 2 Using only one interrupt The interrupt enable
53. 1 91 6 Hz to 11 7 kHz 0 0 1 0 128 N 1 fy 42 7 us to 5 45 ms fy 128 N 1 183 Hz to 23 4 kHz 0 1 0 0 64 N 1 fy 21 3 us to 2 73 ms fy 64 N 1 366 Hz to 46 9 kHz 0 1 0 0 0 32 N 1 fy 10 7 us to 1 37 ms fy 32 N 1 732 Hz to 93 8 kHz 1 0 0 0 0 16 N 1 fy 5 33 us to 683 us fy 16 N 1 1465 Hz to 188 kHz When fy 4 19 MHz MODL bits 2 6 Interrupt generation interval Square wave output frequency 6 5 4 3 2 fx 6 0 MHz fx 6 0 MHz 0 0 0 0 1 256 N 1 fy 122 us to 15 6 ms fx 256 N 1 64 Hz to 8 kHz 0 0 1 0 128 N 1 fy 61 0 to 7 81 ms fx 128 N 1 128 Hz to 16 kHz 0 0 1 0 0 64 N 1 fy 30 5 us to 3 91 ms fx 64 N 1 256 Hz to 32 kHz 0 1 0 0 0 32 N 1 fy 15 3 us to 1 95 ms fy 32 N 1 512 Hz to 65 kHz 1 0 0 0 0 16 N 1 fx 7 63 us to 977 us fx 16 N 1 1024 Hz to 131 kHz Cautions 1 A value other than the above cannot be set in MODL Bits 0 1 and 7 must be set to 0 2 Nis the value set in MODH 0 must not be set for Be sure to set a value from 1 to 255 for N 5 64 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 2 When the timer pulse generator is used in the PWM pulse generation mode Figure 5 36 shows the configuration of the timer pulse generator when it is used in the PWM pulse generation mode The PWM pulse generation mode is selected by setting TPGMO to 0 TPGM5 and TPGM7 are set to 1 to enable pulse output In the PWM mode the PWM pulse s
54. 1 and MBS 15 must be set when an IN OUT instruction is executed Remark The TBR and TCALL instructions are table definition assembler pseudo instructions of uPD75518 User s Manual the GETI instructions 10 17 Chapter 10 Instruction Set 10 3 Instruction Codes of Each Instruction 1 Explanations of the symbols for the instruction codes reg pair Qe Qi Qo reg pair Ns No IEW IETPG IETO IECSIO IEO 2 4 IE1 In Immediate data for n4 or n8 Dn Immediate data for mem Bn Immediate data for bit Nn Immediate data for n or IExxx Tn Immediate data for taddr x 1 2 An Immediate data for the address 2 to 16 relative to branch destination address minus one Sn Immediate data for the one s complement of the address 15 to 1 relative to the branch destination address 10 18 uPD75518 User s Manual Chapter 10 Instruction Set 2 Bit manipulation addressing instruction codes 1 the operand field indicates that there are three types of bit manipulation addressing fmem bit pnem L and H mem bit The table below lists the second byte 2 the above addressing of an instruction code corresponding to 1 1 pmem L 0 1 H mem bit 0 0 1 2 Second byte of instruction Accessible bits code fmem bit 1 0 B Bo Fo F4 Fo FBOH FBFH manipulatable bits Bo Fo Fi Fo 0 0 G Bo
55. 10 38 Instruction Set OR A HL Function A lt HL ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register OR XA rp Function XA lt XAvrp ORs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC then sets the result in the XA register pair OR rp 1 XA Function 1 lt rp 1vXA ORs the contents of register pair 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in register pair rp 1 XOR A n4 Function A lt Avn4 4 13 0 Exclusive ORs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The high order bit of an accumulator is inverted XOR A 1000B XOR A HL Function A Av HL Exclusive ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register XOR XA rp Function XA XAvrp Exclusive ORs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC then sets the result in the XA register pair XOR rp 1 XA Function lt rp 1v XA Exclusive ORs the contents of register pair 1 HL DE BC XA HL DE BC wi
56. 2 Bit Manipulation Instructions 20444040 10 4 10 1 3 String Effect Instructions 10 5 10 1 4 Number System Conversion Instructions 10 6 10 1 5 Skip Instructions and the Number of Machine Cycles Required for e nei eras 10 7 10 2 Instruction Set and Operation 10 8 10 3 Instruction Codes of Each Instruction 10 18 10 4 Functions and Applications of the Instructions 10 24 10 4 1 Transfer Instructions 10 24 10 4 2 Table Reference Instructions 10 29 10 4 3 Bit Transfer 10 33 10 4 4 Arithmetic Logical Instructions 10 34 10 4 5 Accumulator Manipulation 10 39 10 4 6 Increment Decrement Instructions 10 39 10 4 7 Compare 10 40 10 4 8 Carry Flag Manipulation 10 41 10 4 9 Memory Bit Manipulation Instructions 10 42 10 4 10 Branch 2 2 440 10 44 10 4 11 Subroutine Stack Control Instructions 10 48 10 4 12 Interrupt Control Instructions 2 2 10 51 10 4 13 I O Instructions aa aa aa ae 10 51 10 4 14 CPU Control
57. 7 can be set in units of four bits by port mode register group B PMGB The I O modes of port 8 to port 14 can be set in units of four bits by port mode register group C PMGC Each port functions as an input port when the corresponding bit of the port mode register is set to 0 and functions as an output port when the same corresponding bit is set to 1 When the output mode is selected by the port mode register the contents of the output latch appear on the output pins and so the contents of the output latch must be changed to a desired value before the output mode is set An 8 bit memory manipulation instruction is used to set port mode register group A B or C A RESET signal clears all bits of each port mode register to 0 This means that the output buffers are set off and all ports are placed in the input mode Example P30 P31 P62 and P63 are used as input pins and P32 P33 P60 P61 are used as output pins CLR1 MBE or SEL MB15 MOV XA 3CH MOV PMGA XA uPD75518 User s Manual 5 9 Chapter 5 Peripheral Hardware Functions Figure 5 9 Formats of Port Mode Registers 1 2 Port mode register group A Address 7 6 5 4 3 2 1 0 Symbol 63 PM62 PM61 PM60 PM33 PM32 1 PM30 FE8H PMGA P30 I O specification P31 specification P32 specification P33 I O specification P60 I O specification P61 I O specification P62 I O specification P63
58. 8 and 15 Ports 0 1 8 and 15 function as input ports and also have the functions described below e Port O Vectored interrupt 4 Serial interface I O SCKO 500 5 0 SIO SB1 e Port 1 Vectored interrupt input INTO INT1 Edge detection test input INT2 External event pulse input TIO for timer event counter Port 8 Timer pulse generator pulse output PPO Serial interface I O SCK1 501 51 Port 15 A D converter input to Input is always enabled for each pin of ports 0 1 8 and 15 regardless of the operation status of the other function of the pin Schmitt triggered inputs are used for the pins of ports 0 1 and 8 excluding P80 and P82 to prevent malfunction due to noise In addition a noise eliminator is provided for P10 See 2 of Section 6 3 Use of built in pull up resistors can be software selected for a set of three bits of port 0 to and for a set of four bits of port 1 P10 to P13 ata time This is done by manipulating pull up resistor specification register group A A RESET signal input places these pins in the input port mode uPD75518 User s Manual Chapter 2 Pin Functions 2 2 2 P20 P23 PORT2 I O Pins Used Also for PTOO PCL and BUZ P30 P33 P60 P63 PORT6 P70 P73 PORT7 P90 P93 9 100 103 PORT10 P110 P113 PORT11 Three State These pins are the I O pins of the 4 bit I O ports with output latches ports 2
59. A HL 10 35 XA rp 10 35 rp 1 XA 10 35 Appendix D Instruction Index SUBS A HL 10 35 SKE HL n4 10 40 SUBS XA rp 10 36 SKE A HL 10 40 SUBS rp 1 XA 10 36 SKE XA HL 10 41 SUBC A HL 10 36 SKE A reg 10 41 SUBC XA rp 10 36 SKE XA rp 10 41 SUBC rp 1 XA 10 37 AND A n4 10 37 Carry flag manipulation instructions AND A HL 10 37 SET1 CY 10 41 AND XA rp 10 37 CLR1 CY 10 41 AND rp 1 XA 10 37 SKT CY 10 41 OR A n4 10 37 NOT1 CY 10 41 OR A HL 10 38 OR XA rp 10 38 Memory bit manipulation instructions OR rp 1 XA 10 38 SET1 mem bit 10 42 XOR A n4 10 38 SET1 fmem bit 10 42 XOR A HL 10 38 SET1 pmem L 10 42 XOR XA rp 10 38 SET1 H mem bit 10 42 XOR rp 1 XA 10 38 CLR1 mem bit 10 42 CLR1 fmem bit 10 42 Accumulator manipulation instructions CLR1 pmem L 10 42 RORC A 10 39 CLR1 H mem bit 10 42 NOT A 10 39 SKT mem bit 10 42 SKT fmem bit 10 42 Increment decrement instructions SKT pmem L 10 42 INCS reg 10 39 SKT H mem bit 10 42 INCS 10 39 SKF mem bit 10 43 INCS 10 39 SKF fmem bit 10 43 INCS mem 10 40 SKF pmem L 10 43 DECS reg 10 40 SKF H mem bit 10 43 DECS rp 10 40 SKTCLR fmem bit 10 43 SKTCLR pmem L 10 43 Compare instructions SKTCLR H mem bit 10 43 SKE reg n4 10 40 AND1 CY f
60. AN2 O AN3 lt lt 4 150 lt 5 151 lt O 152 6 0 7 153 AVss P131 P132 P133 2 lt 7 76 75 7 ANO O O P140 AVreF O P141 142 d 61 lt P143 P113 lt gt 15 60 o RESET P112 lt lt 6 O X2 P1110 O X1 P110 O O IC P103 O lt gt 9 O XT2 P102 lt gt 10 EEEE 55 27997 P101 95959 Vss P100 O 5206 O POO INT4 P93 9990 P01 SCKO P92 14 TEE 51 0 Po2 soo sBo P91 15 OT 50 0O P03 SI0 SB1 ow wo P90 lt 16 DE 49 O P10 INTO SI1 P83 P11 INT1 SO1 P82 O O P12 INT2 SCK1 P81 O P13 TIO PPO P80 lt gt 20 45 0 20 KR7 P73 lt gt 21 44 0 P21 KR6 P72 O O P22 PCL KR5 P71 O O P23 BUZ KR4 P70 O 124 41 lt gt P30 P30 MDO Note 1 155515450505 oar 000 00 i0 D M oc n0 n Sf amp a 264236 P33 P33 MD3 Nete 1 P32 P32 MD2 Note 1 O P31 P31 MD1 Nete 1 O IC Internally connected Connect to keeping the wiring as short as possible Note 1 The pin name in parentheses applies to the uPD75P518 Note 2 Be sure to supply power to both Vpp pins The uPD75P518K is not intended for use in mass produced products it does not offer a sufficiently high level of reliability for suc
61. Avn4 A HL 1 1 A Av HL 1 XA rp 2 2 XA lt XAvrp rp 1 XA 2 2 rp lt rp1vXA XOR 4 2 2 lt Avn4 A HL 1 1 A lt Av HL 1 XA rp 2 2 XA lt rp 1 XA 2 2 rp lt rp XA uPD75518 User s Manual 10 13 Chapter 10 Instruction Set Instruc Mne Number Machine Address tion monic Operand of cycle Operation ing area Skip condition bytes 3 8 RORC A 1 1 CY lt lt CY lt E j NOT A 2 2 A lt A _ ANCS reg 1 1 5 lt 1 reg 0 5 1 14S lt 1 1 rp1 00H HL 2 2 5 HL lt HL 1 1 HL 0 5 mem 2 2 5 mem mem 1 3 mem 0 5 DECS reg 1 1 5 reg reg 1 reg FH rp 2 2 5 lt 1 rp FFH SKE reg n4 2 248 Skip if reg n4 reg n4 E HL n4 2 2 5 if HL n4 1 HL n4 2 A HL 1 1 5 if A HL 1 A HL E XA HL 2 2 5 Skipif XA HL 1 XA HL A reg 2 248 Skip if A reg A reg XA rp 2 248 Skip if XA rp 1 1 lt 1 855 1 1 CY lt 0 Es SKT CY 1 1 S Skip if CY 1 CY 1 NOT1 CY 1 1 CY lt CY 10 14 uPD75518 User s Manual Chapter 10 Instruc Mne Number Machine Address tion monic Operand of cycle Operation ing area Skip condition bytes SET1 mem bit 2 2 mem bit lt 1 9 fmem bit 2 2 fmem bit lt 1 4 pmem L 2 2 pmem7 o L3 2 bit Ly 9 lt 1 b5 H mem bit 2 2 H mems o bit lt 1 1 CLR1 mem bit 2 2 mem bit lt 0 3 fmem bit 2 2
62. Figure 6 4 VO Timing of a Noise Eliminatot 6 9 Figure 6 5 Format of Edge Detection Mode Registers sse 6 10 Figure 6 6 Configuration of the 2 and KRO to KR7 Circuits 6 12 Figure 6 7 Interrupt Priority Specification Register sees 6 14 Figure 6 8 Interrupt Processing Sequence sisse esistente 6 16 Figure 6 9 Multiple Interrupt Processing by a High order 6 17 Figure 6 10 Multiple Interrupt Processing by Changing the Interrupt Status Flags 6 18 Figure 7 1 Standby Mode Release Operation sse 7 5 Figure 8 1 Reset Operation by a RESET 000040 2 0000000000 8 1 TOC 12 uPD75518 User s Manual List of Tables 1 2 Table 1 1 Differences between uPD75P518 uPD75517 and 75518 1 5 Table 2 1 Digital O POort PINS isto th decere s eed ce apnd 2 1 Table 2 2 Nor port Pim FURIO perice o dte e EH E PEERS 2 4 Table 2 3 Recommended Connection of Unused Pins sse 2 16 Table 2 4 Selection of Pull up and Pull down Resistors sse 2 17 Table 2 5 Selection of Feedback Resistors 20 00 000000000000000 2 17 Table 3 1 Addressing 20 0442 2 2 2 241 00000000000 then anth
63. Functions 5 1 Chapter 6 Interrupt Function 6 1 Chapter 7 Standby Function eerie isle nhu 7 1 Chapter 8 Reset Function 8 1 Chapter 9 Writing to and Verifying Program Memory 9 1 Chapter 10 Instruction ien 10 1 Appendix Development A 1 Appendix Mask ROM Ordering Procedure B 1 Appendix C Revision History 1 1 1111 11 C 1 Appendix D Instruction D 1 Appendix E Hardware Index ccce E 1 uPD75518 User s Manual TOC 1 Contents MEMO TOC 2 uPD75518 User s Manual Contents Chapter 1 General 1 1 11 Function of the uPD75518 Sub Series Products 1 3 1 2 Ordering Information 1 4 1 3 Differences between the uL PD75P518 uL PD75517 WPD 75516 1 5 T 4 BIO CK iub aD GG IUE 1 7 1 5 Pin Configuration oia nin rri rn nra aguda asd aC da ad 1 8 Chapter 2 Pin
64. Hardware Functions Cautions 4 When the four bits of the PCC are set to 0001 fx 16 do not set SCC 0 to 1 Before switching the main system clock to the subsystem clock be sure to manipulate the PCC bits so other than 0001 is set When the system operates on the subsystem clock the PCC bits must also be other than 0001 3 System clock oscillator i The main system clock oscillator 6 0 MHz typical operates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins An external clock can also be input Input the clock signal to the X1 pin and the reversed signal to the X2 pin Figure 5 16 shows the external circuit for the main system clock oscillator Figure 5 16 External Circuit for the Main System Clock Oscillator a Crystal ceramic oscillation b External clock uPD75518 075518 ume qu V External D clock o xi x1 L x2 Crystal or ceramic resonator Caution When an external clock is used the STOP mode cannot be set This is because the X1 pin is connected to Vss in the STOP mode ii The subsystem clock oscillator operates with a crystal resonator 32 768 kHz standard connected to the XT1 and XT2 pins An external clock can also be input Input the clock signal to the XT1 pin and the reversed signal to the XT2 pin Figure 5 17 shows the external circuit for the subsystem clock oscill
65. In either mode all contents of the registers flags and data memory that are present immediately before the standby mode is set are preserved In addition the states of the output latches of the I O ports and the states of the output buffers are also preserved so that the states of the I O ports are to be processed to minimize the power consumption of the entire system Cautions 1 The STOP mode can be used only for the main system clock Subsystem clock generation cannot be terminated The HALT mode can be used for either the main system clock or the subsystem clock uPD75518 User s Manual 7 1 Chapter 7 Standby Function Cautions 2 A lower power consumption and lower voltage operation are enabled by switching standby modes or switching CPU and system clocks However a switching time as described in Section 5 2 3 is required before operation is started with a new clock after the clock is selected with the control register For this reason when the clock switching function is used together with a standby mode the standby mode must be set after a time needed for switching elapses 3 Configure I O ports for minimum power consumption in the stand by mode Be sure to connect signals which are high or low to input ports 7 2 uPD75518 User s Manual Chapter 7 Standby Function 7 1 Setting of Standby Modes and Operation Status Table 7 1 Operation Statuses in the Standby Mode STOP mode HALT mode Instruct
66. L 10 33 CY H mem bit 10 33 fmem bit CY 10 33 pmem L CY 10 33 H mem bit CY 10 33 10 32 XA BCXA 10 32 10 29 XA PCXA 10 31 10 53 10 39 10 41 OR OR OR OR 1 1 1 OUT OUT P POP POP PUSH PUSH R RET RETI RETS RORC S SEL SEL SET1 SET1 SET1 SET1 SET1 SKE SKE Appendix D Instruction Index A n4 10 37 A HL 10 38 rp 1 XA 10 38 XA rp 10 38 fmem bit 10 43 CY pmem L 10 43 CY H mem bit 10 43 10 52 PORTn XA 10 52 10 49 BS 10 50 rp 10 50 BS 10 50 rp 10 50 10 50 10 49 A 10 39 MBn 10 53 RBn 10 53 CY 10 41 fmem bit 10 42 mem bit 10 42 pmem L 10 42 H mem bit 10 42 A reg 10 41 A HL 10 40 Appendix D Instruction Index SKE SKE SKE SKE SKF SKF SKF SKF SKT SKT SKT SKT SKT SKTCLR SKTCLR SKTCLR reg n4 10 40 XA rp 10 41 XA HL 10 41 HL n4 10 40 fmem bit 10 43 mem bit 10 43 pmem L 10 43 H mem bit 10 43 CY 10 41 fmem bit 10 42 mem bit 10 42 pmem L 10 42 H mem bit 10 42 fmem bit 10 43 pmem L 10 43 H mem bit 10 43 STOP 10 53 SUBC SUBC SUBC SUBS SUBS SUBS T TBR TCALL IX XCH XCH XCH XCH A HL 10 36 rp 1 XA 10 37 XA rp
67. PCC is a 4 bit register for selecting a CPU clock with the low order two bits and for controlling the CPU operation mode with the high order two bits Figure 5 14 shows the format When bit 3 or bit 2 is set to 1 the standby mode is set When the standby mode is released by the standby release signal these bits are automatically cleared to return to the normal operation mode See Chapter 7 for details A 4 bit memory manipulation instruction is used to set the low order two bits of the PCC The high order two bits are set to 0 Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction respectively The STOP instruction and HALT instruction can always be executed regardless of MBE setting The CPU clock can be selected only while the processor is operated by the main system clock When the processor is operated by the subsystem clock the low order 2 bits of the PCC are invalidated and 4 is automatically set The STOP instruction can be executed only when the processor is operated by the main system clock A RESET signal clears the PCC to 0 Example 1 The machine cycle is set to 0 95 us at 4 19 MHz SEL MB15 MOV A 0011B MOV PCC A Example 2 The STOP mode is set A STOP instruction or HALT instruction must always be followed by an NOP instruction STOP NOP uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 14 Format of the Processor Clock Control Register
68. PROM Hardware PG 1500 A PROM programmer with which programs can be written into PROMs in a stand alone mode or by remote control from a host machine when connected with the accessory board and optional socket board Products programmable with the PG 1500 include commonly used PROMs 256K bit to 4M bit and single chip microcomputers containing a PROM PA 75P516GF PROM programmer adapter for the uPD75P516GF and uPD75P518GF This programmer is connected to the PG 1500 PA 75P516K PROM programmer adapter for the uPD75P516K and uPD75P518K This programmer is connected to the PG 1500 Software PG 1500 This program enables the host machine to control the PG 1500 controller under controller the serial interface and parallel interface Host machine Part number OS Distribution media product name PC 9800 series MS DOS 3 5 inch 2HD uS5A13PG1500 Ver 3 30 1 to 5 25 inch 2HD uS5A10PG1500 Ver 5 00A Note IBM PC AT PC DOS 5 25 inch 2HC uS7B10PG1500 Ver 3 1 Note MS DOS versions 5 00 and 5 00A provide a task swap function This function however cannot be used in these software packages Remark The PG 1500 controller can run only on the host machine under the OS mentioned above A 2 uPD75518 User s Manual Appendix A Development Tools Tools for debugging Hardware E 75000 R Note 1 IE 75000 R EM E 75001 R EP 75516GF R EV 9200G 80 Software IE control The IE 75000 R is an in circuit emulat
69. Sample program LOOP CLR1 MOV MOV MOV MOV MOV MOV1 MOV1 INCS BR RET MBE XA BUFF1 BSBO XA XA BUFF2 BSB2 XA L 0 CY BSBO L PORT3 0 CY L LOOP Set BSBO and BSB1 Set BSB2 and BSB3 CY lt specified bit in BSB Bit in port 3 lt CY lt 1 5 163 Chapter 5 Peripheral Hardware Functions 2 Data is transmitted in arbitrary serial transfer format 1 A serial transfer format shown in Figure 5 92 is used for data output P140 is used for serial data output and P141 is used for the clock The data to be transferred is already set BSB2 and BSB3 and bit of BSB1 is set to 1 and bit 2 is set to 0 Figure 5 92 Serial Transfer Format I S P140 Serial clock P141 1 2 3 4 5 7 8 9 lt Sample program gt MOV L 0FH CLR1 PORT14 0 Start transfer LOOP PORT14 1 CLK lt 0 MOV1 CY BSBO L MOV1 PORT14 0 CY Data output SET1 PORT14 1 CLK lt 1 DECS L SKE L 5 BR LOOP SET1 PORT14 0 End transfer 5 164 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 3 Data is transferred in arbitrary serial transfer format 2 A serial transfer format shown in Figure 5 93 is used for data transmission Transmission data is 16 bit serial data and is input and output on the P60 pin fx 4 19 MHz and the minimum instruction execution time is 1 us Figure 5 93 Serial Transfer Format 1
70. Skip if A HL and X HL 1 Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair and the contents of the X register match the data at the next address in data memory However if the contents of the L register are odd numbered an address with the lowest order bit ignored is specified SKE A reg Function Skip if A reg Skips the immediately following instruction if the contents of the A register match the contents of register reg X A H L D E B C SKE XA rp Function Skip if XA rp Skips the immediately following instruction if the contents of the XA register pair match the contents of register pair rp XA HL DE BC XA HL DE BC 10 4 8 Carry Flag Manipulation Instructions SET1 CY Function CY lt 1 Sets the carry flag CLR1 CY Function CY lt 0 Clears the carry flag SKT CY Function Skip if CY 1 Skips the immediately following instruction if the carry flag is set to 1 NOT1 CY Function CY lt CY Inverts the carry flag If it is 0 it is set to 1 or vice versa uPD75518 User s Manual 10 41 Chapter 10 Instruction Set 10 4 9 Memory Bit Manipulation Instructions SET1 mem bit Function mem bit lt 1 mem 07 0 OOH FFH bit By 9 0 3 Sets the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data me
71. a lower priority on the other hand the remaining interrupt request is held and the tested interrupt request is processed first As indicated in Table 6 4 the method to determine the sharing interrupt varies depending on whether the interrupt is high order or low order Table 6 4 Determination of an Interrupt Source For high order interrupt Disable the interrupt and test the interrupt request flag to which For priority is given ow order interrupt Test the interrupt request flag of the interrupt source to which priority is given uPD75518 User s Manual Chapter 6 Interrupt Function Example 1 Both INTBT and INT4 are used as high order interrupts and INT4 is given a higher priority DI SKTCLR IRQ4 BR VSUBBT EIRETI EI RETI VSUBBT SKTCLA IRQBT BR EIRETI BR EIRETI IRQ4 1 INT4 service routine IRQBT 1 Note IRQBTVIRQ4 0 INTBT service routine Note Always test those interrupts which are not assigned a higher priority Example 2 Both INTBT and INT4 are used as low order interrupts and INT4 is given a higher priority SKTCLR IRQ4 BR VSUBBT RETI VSUBBT IRQBT RETI IRQ4 1 INT4 service routine INTBT service routine uPD75518 User s Manual Chapter 6 Interrupt Function 6 7 Machine Cycles for Starting Interrupt Processing With the 75X series the following machine cycles are used to start the execution of the interrupt service routine after an interr
72. addr instruction Branch call 07FFH I a a Y address specified in GETI insturction OFFFH ji M ug GEM I c c CM bog we 1 Branch address specified in BRCB instruction gh a ete te euet eA tO Eee Branch address specified in 2FFFH BRCB caddr instruction SU Branch address specified in BRCB ruction A Branch address specified in BRCB caddr instruction APE 1 hehe eas E S ge Pe PS TEE Branch address specified in 5FFFH BRCB caddr instruction is joue ici CI M LP CI LE ae Branch address specified in 6FFFH BRCB cadar instruction OOODEIE os eeu rever uersus Zune e t Branch address specified in BRCB caddr instruction 7F7FH Y 1 Caution The start address of an interrupt vector shown in Figure 4 3 consists of 14 bits So the start address must be set within a 16K byte space 0000H to 3FFFH Remark Although not listed in Figure 4 3 the BR PCDE and BR PCXA instructions can cause a branch to an address with only the low order 8 bits of the PC changed uPD75518 User s Manual Chapter 4 Internal CPU Functions 4 3 Data Memory RAM 1024 Words x 4 Bits The data memory consists of a data area and peripheral hardwar
73. addressing mode again enables bit manipulation regardless of MBE and MBS setting Example 1 Pulses are output on the bits in the order from port 4 to port 7 P41 P73 MOV L 0 LOOP SET1 PORT4 L Bits 14 0 of ports 4 to 7 lt 1 CLR1 PORT4 L L1 9 of ports 4 to 7 lt 0 INCS L BR LOOP Example 2 When P30 15 high the 16 bit serial data applied to P31 is transferred to the bit sequential buffer BSB MOV L 0 LOOP SKT PORT3 0 P30 1 BR LOOP MOV1 CY PORT3 1 CY lt P31 1 BSB0 L CY BSB 110 lt CY WAIT SKF PORT3 0 P30 0 BR WAIT INCS L L lt L 1 BR LOOP uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory c Specific 1 bit direct addressing H mem bit This addressing mode enables any bit in the data memory space to be manipu lated In this addressing mode the high order four bits of the data memory address in the memory bank specified by MB MBE MBS are indirectly specified using the H register and the low order four bits and bit address are directly specified in the operand This addressing mode enables a wide variety of manipulations for each bit in the entire data memory space Example Bit 2 at address 32H FLAGS is reset if both bit at address FLAG1 and bit O at address 31H FLAG2 are set to O or 1 FLAG1 Jj FLAG3 FLAG2 FLAG1 EQU 30H 3 FLAG2 EQU 31H 0 FLAG3
74. an instruction 6 9 Interrupt Applications To use the interrupt function a main program must a Set a desired interrupt enable flag using the El IExxx instruction b Select an active edge when INTO or INT1 is used set IMO or IM1 c Set IPS when a level two interrupt high order interrupt is used can set IME concurrently d Set the interrupt master enable flag using the El instruction When the interrupt service program is used MBE and RBE are set in a vector table When an interrupt given a higher priority is processed however register banks need to be saved and set with appropriate values The RETI instruction is used to return from the interrupt service program uPD75518 User s Manual 6 23 Chapter 6 Interrupt Function 1 Interrupt enable disable lt Main program gt lt 1 gt Reset 1 lt 2 gt El IEO Interrupt disabled IET1 3 El 1 INTO and INTT1 enabled 4 DI IEO y INTT1 enabled lt 5 gt DI I Interrupt disabled 1 2 3 4 5 A RESET signal disables all interrupts Interrupt enable flags are set by the El IExxx instruction At this stage all interrupts are disabled The interrupt master enable flag is set by the El instruction At this stage INTO and INTT1 are enabled An interrupt enable flag is cleared by the DI IExxx instruction to disable INTO The DI instruction disables all interrupts uPD75518 User s Manual Chapter 6 Int
75. an interrupt service routine PUSH rp Function 5 1 lt SP 2 lt SP lt 5 2 Saves the contents of register pair rp XA HL DE BC to the data memory location stack addressed by the stack pointer then decrements the stack pointer The high order part of a register pair X D B is saved to the stack location addressed by SP 1 and the low order part L E C is saved to the stack location addressed by SP 2 PUSH BS Function SP 1 lt MBS SP 2 lt RBS SP lt SP 2 Saves the contents of the memory bank select register MBS and the register bank select register RBS to the data memory location stack addressed by the stack pointer then decrements the stack pointer POP rp Function rp SP lt SP 1 SP lt SP 2 Restores register pair rp XA HL DE BC with the data at the data memory location stack addressed by the stack pointer then increments the stack pointer The low order part of a register pair rp L E C is restored from the contents of SP and the high order part rpu X H D B is restored with the contents of SP 1 POP BS Function RBS lt SP MBS SP 1 SP SP 2 Restores the register bank select register RBS and the memory bank select register MBS with the data at the data memory location stack addressed by the stack pointer then increments the stack pointer uPD75518 User s Manual Chapte
76. and Interrupt Routines Normal processing Use register banks 2 and 3 with RBE 1 Level one interrupt processing Use register bank 0 with RBE 0 Level two interrupt processing Use register bank 1 with RBE 1 In this case the RBS needs to be saved and restored Multiple triple or more Save and restore the registers with PUSH or POP interrupt processing uPD75518 User s Manual 3 17 Chapter 3 Data Memory Operations and Memory Figure 3 4 Example of Register Bank Selection Main program Level one interrupt lt Level two interrupt lt Level three interrupt 0 in the 1 in the RBE O in the vector table vector table vector table PUSH BS H ae 1 SEL RB1 PUSH 1p RETI POP rp Y RETI Remark RB 2 RB 0 RB The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or restoring the RBS with the PUSH or POP instruction The RBE is set using the SET1 or CLR1 instruction The RBS is set using the SEL instruction Example SET1 RBE lt 1 CLR1 RBE lt 0 SEL RBO RBS lt 0 SEL RB3 RBS lt 3 The general register area of the uPD75518 can be used not only 4 bit basis but also on an 8 bit basis with register pairs This enables users to perform transfers arithmetic logical operations comparisons and increments and decrements at a speed comparable to that of an
77. are incorporated Memory bank enable flag MBE Memory bank select register MBS The MBS is a register used to select a memory bank With the 5518 the register can be set to 0 1 2 3 or 15 The MBE is a flag used to determine whether the memory bank selected using the MBS is valid As shown in Figure 3 1 when the MBE is set to 0 a certain memory bank is always selected regardless of the setting of the MBS When the MBE is set to 1 memory bank selection depends on the setting of the MBS thus enabling data memory space expansion In addressing data memory space the MBE is usually set to 1 MBE 1 and data memory in the memory bank specified in the MBS is operated However the MBE 0 mode or MBE 1 mode can be selected for each step of processing for more efficient programming Applicable program processing Effect MBE 0 mode Interrupt processing MBS save restoration becomes unnecessary Processing that repeats internal MBS modification becomes hardware and static RAM operations unnecessary Subroutine processing MBS save restoration becomes unnecessary MBE 1 mode Usual program processing uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Figure 3 1 Use of MBE z 0 Mode and MBE 1 Mode Main program lt Subroutine gt MBE 1 CLR1 MBE MBE 0 Internal hardware 2 00 1 and static RAM MBE RET
78. as well as for port 0 uPD75518 User s Manual 5 117 Chapter 5 Peripheral Hardware Functions b Serial bus interface control register SBIC To use the SBI mode set SBIC as shown below For details on SBIC see 2 in Section 5 7 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below hatched portions indicate the bits used in the SBI mode Address Symbol 7 6 5 4 3 2 1 0 FE2H BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC Bus release trigger bit W Command trigger bit W Bus release detection flag R Command detection flag R Acknowledge trigger bit W Acknowledge enable bit R W Acknowledge detection flag R Busy enable bit R W Remark R Read only Write only R W Read write Bus release trigger bit W RELT Control bit for bus release signal REL trigger output By setting RELT 1 the 500 latch is set to 1 Then the RELT bit automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Command trigger bit W CMDT Control bit for command signal CMD trigger output By setting CMDT 1 the 500 latch is cleared Then the CMDT bit is automatically cleared Caution Never clear SBO or SB1 during serial transfer Be sure t
79. at address xxFEH or XXFFH a branch to the next page instead of that page occurs Program memory 7 0 Page 2 02 02 gt 0300H Page 3 If the BR PCDE instruction is located at a or b in the figure above a branch to page 3 instead of page 2 occurs jumping to the low order 8 bits of the address specified by the contents of the DE register pair BR PCXA Function PCz4 lt X PC3 9 lt A Branches to the address specified by the program counter whose low order 8 bits have been replaced with the contents of the XA register pair The high order bits of the program counter are not affected Caution As with the BR PCDE instruction if the first byte is located at address xxFEH or xxFFH a branch to the next page instead of the page containing the instruction occurs uPD75518 User s Manual 10 45 Chapter 10 Instruction Set BR BCDE Function PC 44 9 lt 2 0 Branches to the address specified by the program counter whose bits have been replaced with the contents of the B o D and E registers BR BCXA Function 14 0 lt 2 0 Branches to the address specified by the program counter whose bits have been replaced with the contents of the C X and A registers BRA addr1 Function 14 0 lt addri 0000H 5F7FH uPD75517 0000H 7F7FH uPD75P518 Transfers the 15 bit immediate
80. be coded as they appear For immediate data a proper numeric value or label must be coded The abbreviations for registers and flags shown in Chapters 3 to 6 can be coded as labels in place of mem fmem pmem and bit However not all labels can be coded for the fmem and pmem Representation format reg regi rp 2 rp 1 n4 n8 mem bit fmem bit pmem addr addr1 caddr faddr taddr PORTn RBn MBn Description method X C H L X H L BC DE HL BC DE HL BC DE XA BC DE HL XA BC DE HL BC DE HL XA BC DE HL HL HL HL DE DL DE DL 4 bit immediate data or label 8 bit immediate data or label 8 bit immediate data or label Note 2 bit immediate data or label IST1 ISTO MBE RBE IExxx IRQxxx PORTn m n 0 to 15 m 0 to 3 BSBO PORTn n 0 4 8 12 0000 3 7 immediate data or label 0000H 5F7FH immediate data or label uPD7551 7 0000H 7F7FH immediate data or label uPD75518 uPD75P518 12 bit immediate data or label 11 bit immediate data or label 20H 7FH immediate data bit 0 0 or label PORTO PORT15 IEBT IECSIO IETO IEO IE1 IE2 IE4 IEW IETPG RBO RB1 RB2 RB3 MBO MB1 MB2 MB3 MB15 Note Only even address can be specified for 8 bit data processing uPD75518 User s Manual 2 Legend uPD75518 User s Manual PSW MBE
81. bit specified in operand 0 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit is 0 SKTCLR fmem bit SKTCLR pmem L SKTCLR H mem bit Function Skip if bit specified in operand 1 then clear Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit is 1 then clears the bit to 0 AND1 CY fmem bit AND1 CY pmem L AND1 CY H mem bit Function CY CY bit specified in operand ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag OR1 CY fmem bit OR1 CY pmem L OR1 CY H mem bit Function CY CYv bit specified in operand ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag uPD75518 User s Manual 10 43 Chapter 10 Instruction Set XOR1 CY fmem bit XOR1 CY pmem L XOR1 CY H mem bit Function CY lt bit specified in operand Exclusive ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag 10 4 10 Branch Instructions 10 44 BR addr1 Function PC 4 9 lt
82. can be controlled directly by software In the SBI mode SOO is set when the eighth clock of SCKO has been output See 2 in Section 5 7 3 for details 5 Serial clock selector The serial clock selector selects the serial clock to be used 6 Serial clock counter The serial clock counter counts the serial clock to be output or input during transfer and checks whether 8 bit data has been transferred 7 Slave address register SVA and address comparator In the SBI mode SVA is used when the uPD75518 is used as a slave device A slave sets the number assigned to it slave address in SVA The master outputs a slave address to select a particular slave Two data values a slave address output from the master and the value of SVA are compared with each other by the address comparator If a match is found the slave is selected In the two wire serial I O mode or SBI mode SVA detects an error when data is transferred with the 75518 operating as the master or a slave See 4 in Section 5 7 3 for details uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 8 INTCSIO control circuit The IRQCSIO control circuit controls interrupt request processing The circuit issues an interrupt request INTCSIO and set an interrupt request flag IRQCSIO in the following cases See Figure 6 1 Note In the three wire or two wire serial mode An interrupt request is issued whenever eight serial clocks are coun
83. circuit Vector table address generator Standby release signal 1in2412 J041u02 jo wesbeig 0 71 9 ainbi4 9 uoun 14 1914 Chapter 6 Interrupt Function 6 2 Types of Interrupt Sources and Vector Tables Table 6 1 lists the types of interrupt sources and Figure 6 2 shows vector tables Table 6 1 Interrupt Sources Interrupt source signal In out Priority Note 1 Vectored interrupt request vector table address interval signal from INTBT Reference time In 1 VRQ1 0002H basic interval timer INT4 Detection of both rising and falling edges INTO Rising falling edge Out 2 VRQ2 0004H INT1 detection specification Out 3 0006H INTCSIO Serial data transfer In 4 VRQ4 0008H completion signal INTTO Match signal between In 5 VRQ5 000AH programmable timer counter count register and modulo register INTTPG Match signal from In 6 VRQ6 000CH timer pulse generator INT2 Note 3 Rising edge Testable input signal detection for an Set IRQ2 and IRQW INT2 pin input signal or falling edge detection for either of KRO to KR7 pin input signals Note 2 INTW Note 3 Signal from puc L timer Note 1 The priority is used when two or more interrupt Note 2 See 3 in Section 6 3 for details on INT2 Note 3 These test sources are affected by corresponding interrupt enable fl
84. clock is selected SCKO is internally terminated when the 8th clock has been output and is externally counted until the slave enters the ready state 5 120 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 Signals Figures 5 61 to 5 66 show signals to be generated in the SBI mode and flag operations on the SBIC Table 5 14 lists signals used in the SBI mode Figure 5 61 Operations of RELT CMDT RELD and CMDD Master Transfer start request 5100 SCKO 500 latch DE i x 4 ee EN Wo CMDD Figure 5 62 Operations of RELT CMDT RELD and CMDD Slave Transfer start request Write to SIOO SCKO Br 7 8 500 latch RELT Master CMDT Master When address match is found RELD AL When address mismatch is found CMDD uPD75518 User s Manual 5 121 Chapter 5 Peripheral Hardware Functions Figure 5 63 Operation of ACKT SCKO 6 7 8 9 ACK signal is output during the first clock SBO 581 02 X 01 X vo ACK cycle immediately after ACKT is set ACKT When set during this period Caution Do not set the ACKT until the transfer is completed 5 122 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 64 Operation of ACKE a When ACKE 1 at time of transfer completion SCKO 2 e The ACK signal is output SBO 681 uum 0
85. control register SBIC a Serial operation mode register 0 CSIMO To use the SBI mode set CSIMO as shown below For details on CSIMO see 1 in Section 5 7 3 CSIMO is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIMO can be manipulated bit by bit When the RESET signal is input CSIMO is set to OOH In the figure below hatched portions indicate the bits used in the SBI mode Address 7 6 5 4 3 2 1 0 Symbol FEoH CSIEO CSIMO4 CSIMO3 CSIMO2 CSIMo0 CSIMO Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark Read only W Write only Serial clock selection bit W CSIMO1 CSIMOO Serial clock SCKO pin mode 0 0 External clock applied to SCKO pin Input 0 1 Timer event counter output TO Output 1 0 fx 24 262 kHz or 375 kHz Note 1 1 fx 23 524 kHz or 750 kHz Note Note The values at 4 19 MHz and 6 0 MHz are indicated in parentheses 5 116 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Serial interface operation mode selection bit W CSIM04 CSIMO3 CSIMO2 Shift register sequence 00 pin function 10 pin function 0 1 0 1007 0 lt gt 5 2 N ch P03 input Transfer starting with MSB op
86. etc SCKO gt SCK 500 580 SI SIO SB1 lt 500 lt Sample program gt master side CLR1 MBE MOV XA 10000011B MOV CSIMO XA Set transfer mode MOV XA TDATA MOV 5100 Set transfer data and start transfer LOOP SKTCLR IRQCSIO Test IRQCSIO BR LOOP MOV XA SIOO Read in receive data Chapter 5 Peripheral Hardware Functions 5 7 6 Two Wire Serial I O Mode 5 100 The two wire serial mode be made compatible with any communication format by programming In this mode communication is basically performed using two lines Serial clock SCKO and serial data input output SBO or SB1 Figure 5 48 Example of Two Wire Serial I O System Configuration 2 wire serial I O 2 wire serial I O Master CPU Slave CPU 075518 SCKO SCK 580 581 gt 580 581 Remark uPD75518 can also be used as a slave CPU 1 Register setting To set the two wire serial mode manipulate the following two registers Serial operation mode register 0 CSIMO Serial bus interface control register SBIC a Serial operation mode register 0 CSIMO To use the two wire serial I O mode set CSIMO as shown below For details on CSIMO see 1 in Section 5 7 3 CSIMO is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIMO can be manipulated bit by bit When the RESET signal is input CSIMO is set to OOH In the figure below hatched portions indicate the bi
87. flag for desired one of the two interrupt sources sharing a vector table is set to 1 and the interrupt enable flag for the other is cleared to 0 In this case the enabled IExxx 1 interrupt source causes an interrupt request When the interrupt request is accepted the interrupt request flag is reset The same operation as that of interrupts not sharing a vector address Using both interrupts The interrupt enable flags corresponding to the two interrupt sources are both set to 1 In this case the logical sum of the interrupt request flags for the two interrupt sources is used as an interrupt request In this case even if an interrupt request or interrupt requests caused by the setting of one or both of the interrupt request flags are accepted the interrupt request flag or flags are not reset Accordingly which of the two interrupt sources caused the interrupt needs to be determined using the interrupt service routine For this determination the DI instruction is to be executed at the start of the interrupt service routine and the interrupt request flags are checked with the SKTCLR instruction If both interrupt request flags are set an interrupt request remains even when one interrupt request flag is tested and cleared When this interrupt is given a higher priority the remaining interrupt request starts two level interrupt processing That is the interrupt request not to be tested is processed first When the interrupt is given
88. flop TOUT flip flop status to the PTOO pin The time out flip flop is inverted by a match signal received from the comparator The time out flip flop is reset to 0 when bit 3 of the timer mode register TMO is set to 1 A RESET signal clears the TOEO and the TOUT flip flop to 0 Figure 5 30 Format of the Timer Event Counter Output Enable Flag Address 3 FA2H TOEO Timer event counter output enable flag W 5 5 5 Operation Mode of the Timer Event Counter The timer event counter operates in the count operation disable mode or in the count operation mode depending on the setting of the mode register The following operations are possible regardless of the setting of the mode register lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Note uPD75518 User s Manual TIO pin signal input and test input test is possible for the other function P13 of the pin Output of the time out flip flop status to the PTOO Note Setting of the modulo register TMODO Reading from the count register TO Setting clearing and testing of the interrupt request flag IRQTO When the timer event counter output pin PTOO is used set dual purpose the P20 pin as shown below lt 1 gt Clear the output latch for P20 lt 2 gt Set port 2 to the output mode lt 3 gt Cancel the use of pull up resistor for port 2 Chapter 5 Peripheral Hardware Functions 1 Count operation disable mode This mod
89. generation must have been started After a time 32 machine cycles required to switch to the subsystem clock elapses SCC 3 is set to 1 to terminate main system clock generation After detecting the input of commercial power by using an interrupt SCC 3 is cleared to start main system clock generation After a time required for stable generation 5 0 is cleared to 0 to operate at the highest speed Note 1 At 4 19 MHz 31 3 ms Note 2 At 4 19 MHz 15 3 us Note 3 INT4 is useful uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 2 4 Clock Output Circuit 1 2 Configuration of the clock output circuit Figure 5 20 shows the configuration of the clock output circuit Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22 PCL pin to output remote control signals or to supply clock pulses a peripheral LSI device The procedure for outputting a clock pulse signal is as follows a Select a clock output frequency and disable clock output b Write a in the P22 output latch c Set the output mode for port 2 d Enable clock output Figure 5 20 Configuration of the Clock Output Circuit generator From the clock Output f x 2 buffer Selector 4 fx 2 gt PCL P22 1 28 PORT2 2 Bit 2 of PMGB Port 2 input CLOM3 CLOM output mode atc specification bit 4 Internal bus
90. group are located contiguously the string instructions following an executed instruction are processed as NOP instructions Example The data 5FH is set in the DE register pair MOV DE 5FH 10 24 uPD75518 User s Manual Chapter 10 Instruction Set MOV A rpa Function A lt rpa When rpa HL Skip if L 0 When HL Skip FH Transfers the data at the data memory location addressed by register pair rpa HL HL HL DE DL to the A register When HL automatic increment is specified as rpa automatically increments the contents of the L register by one after the data transfer and continues the operation until the contents are set to 0 Then skips the immediately following instruction When HL automatic decrement is specified as rpa automatically decrements the contents of the L register by one after the data transfer and continues the operation until the contents are set to FH Then skips the immediately following instruction MOV XA HL Function A lt HL X lt HL 1 Transfers the data at the data memory location addressed by the HL register pair to the A register and transfers the data at the next data memory address to the X register However if the contents of the L register are odd numbered an address with the low order bit ignored is specified Example The data at addresses 3EH and 3FH are transferred to the XA register pair MOV HL 3EH MOV XA HL MOV HL A Function
91. hann then 3 5 Table 3 2 Register Bank to Be Selected with the RBE and RBS 3 17 Table 3 3 Recommended Use of Register Banks with Normal Routines and Interrupt ROUTES cadeau eb ere Tua 3 17 Table 3 4 Addressing Modes Applicable to Peripheral Hardware Operation 3 22 Table 4 1 Stack Area to Be Selected by the Stack Bank Select 4 11 Table 4 2 PSW Flags Saved Restored in Stack Operation 4 14 Table 4 3 Carry Flag Manipulation Instructions esses sisse eee 4 15 Table 4 4 Information Indicated by the Interrupt Status Flag 4 16 Table 4 5 Register Bank to Be Selected with the RBE and RBS 4 19 Table 5 1 Types and Features of Digital VO Ports nennen 5 2 Table 5 2 VO Pin Manipulation Instructions esses 5 14 Table 5 3 Operations by I O Port Manipulation Instructions essen 5 16 Table 5 4 Specification of Internal Pull Up Pull Down Resistors 5 17 Table 5 5 Maximum Time Required to Change the System Clock and CPU Clock 5 32 Table 5 6 Resolution and Maximum Set Time sse 5 54 Table 5 7 Modulo Register Settings sisse nannten 5 64 Table 5 8 Basic and Secondary Periods
92. in bit in units of 8 bits units PORT6 4 bit I O Allows input or Ports 6 and 7 Also used as KRO to output mode setting may be paired in 1 or 4 bit units allowing data I O PORT7 Allows input or in units of 8 bits Also used as KR4 to KR7 output mode setting in units of 4 bits PORT8 4 bit input Allows read and test at any time Also used as PPO SCK1 regardless of the operation modes of SO1 and 511 dual function pins PORT9 4 bit I O Allows input or output mode setting The use of a pull down in units of 4 bits resistor can be specified by a mask option in bit units PORT10 4 bit Allows input or output mode setting PORT11 in units of 4 bits PORT12 4 bit Allows input or output mode setting The use of pull up PORT13 N channel in units of 4 bits resistors can be specified PORT14 open drain 10 V by mask options in bit units PORT15 4 bit input Allows read and test at any time Also used as AN4 to AN7 regardless of the operation modes of dual function pins Note This port can directly drive the LED 5 2 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Ports 3 and 4 can directly drive the LED Up to 200 mA peak value can flow at the same time in total for all pins The N ch transistors at the outputs of ports 4 5 and 12 to 14 withstand 10 V to allow effective interface with peripheral LSI devices having different power supply voltages In the uPD75518 a pull up resistor can be provided for
93. is used when no subsystem clock is used Caution Even if built in feedback resistors are provided when no subsystem clock is used operation is not affected except for increased power supply current 1 uPD75518 User s Manual 2 17 Chapter 2 Pin Functions MEMO 2 18 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Map The 75X architecture of the uPD75518 has the following features Internal RAM of up to 4K words x 4 bits 12 bit address Up to eight general registers x 4 bits x 16 banks Peripheral hardware expansibility To provide these features the following are used 1 Data memory bank structure 2 General register bank structure 3 Memory mapped I O This chapter explains these topics uPD75518 User s Manual 3 1 Chapter 3 Data Memory Operations and Memory 3 1 Data Memory Bank Structure and Addressing 3 1 1 Modes Data Memory Bank Structure In the 75518 addresses 000H to 3FFH data memory space are assigned to static RAM 1024 words x 4 bits and addresses F80H to FFFH are assigned to peripheral hardware such as I O ports and timers To address a 12 bit location in this data memory space 4K words 4 bits the uPD75518 uses such a memory bank structure that the low order eight bits are specified with an instruction directly or indirectly and the high order four bits are used to specify a memory bank To specify a memory bank MB two hardware items
94. latch bits are undefined Operation when the output mode is set When a test instruction bit input instruction or instruction for taking in port data on the internal bus in units of four or eight bits is executed output latch data is manipulated When instruction is executed to transfer the contents of the accumulator in units of four or eight bits the output latch data is rewritten and is output on the pins When the XCH instruction is executed the output latch data is transferred to the accumulator The contents of the accumulator are latched in the output latches and are output on the pins When the INCS instruction is executed the contents of the output latch incremented by 1 are latched in the output latch and are output on the pins When a bit output instruction is executed the specified bit of the output latch is rewritten and is output on the pin Chapter 5 Peripheral Hardware Functions Table 5 3 Operations by I O Port Manipulation Instructions Instruction Port and pin operation Input mode Output mode SKT Pin data is tested Output latch data is SKF tested MOV1 CY Pin data is transferred to CY Output latch data is transferred to CY AND1 CY An operation is performed on pin An operation is performed OR1 CY data and CY on output latch data and 1 CY CY IN A PORTn Pin data is transferred to the Output latc
95. mode MOV XA TDATA TDATA is transfer data storage address MOV 5100 Set transfer data and start transfer Caution A second or subsequent transfer can be started by setting data in 5100 MOV SIOO XA or 5100 075518 uPD7225G LCD controller driver etc SCKO SCK 500 5 0 Sl In this case the SIO SBI pin on the uPD75518 be used as an input uPD75518 User s Manual 5 97 Chapter 5 Peripheral Hardware Functions Example 2 Data is transmitted and received starting with the LSB on an external clock slave operation In this case the function of inverting the MSB LSB is used for shift register read write operation pPD75518 P01 SCKO SIO SB1 500 5 0 Other microcomputers lt SCK 500 gt SI lt Sample program gt Main routine CLR1 MBE MOV XA 84H MOV CSIMO XA MOV XA TDATA MOV SIOO XA EI IECSIO EI Serial operation halt MSB LSB invert mode external clock Set transfer data and start transfer Interrupt routine MBE 0 MOV XCH MOV RETI XA TDATA XA SIOO RDATA XA Exchange receive data with transmit data and start transfer Save receive data uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Example 3 Data is transmitted and received at high speed by using a transfer clock of 524 kHz at 4 19 MHz uPD75518 User s Manual 075518 master pPD75206
96. modes Bus release trigger bit RELT Sets the SOO latch Command trigger bit CMDT Clears the SOO latch Figure 5 42 Format of Serial Bus Interface Control Register SBIC 1 3 Address Symbol 7 6 5 4 3 2 1 0 FE2H BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC Bus release trigger bit W Command trigger bit W Bus release detection flag R Command detection flag R Acknowledge trigger bit W Acknowledge enable bit R W Acknowledge detection flag R Busy enable bit R W Remark R Read only W Write only R W Read write 5 82 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 42 Format of Serial Bus Interface Control Register SBIC 2 3 Bus release trigger bit W RELT Control bit for bus release signal REL trigger output By setting RELT 1 the 500 latch is set to 1 Then the RELT bit is automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the 500 latch is cleared Then the CMDT bit is automatically cleared Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Bus release detection flag R
97. nominal value the machine cycles calculated by fy 64fyr fy 8fy7 and 4 in Table 5 5 are longer than the machine cycle calculated by the nominal values of fy Therefore the wait time required to change the system clock and CPU clock should be longer than the machine cycle calculated by the nominal values of fy and fyt uPD75518 User s Manual 5 33 Chapter 5 Peripheral Hardware Functions 2 Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Figure 5 19 Figure 5 19 Changing the System Clock and CPU Clock Commercial ON power line voltage OFF pin voltage E Y RESET signal System clock CPU clock fx 6 0 MHz fxr 32 768 kHz Wait 21 8 ms Y fx fx fxr fx A 10 7 us 0 67 us 122 us 0 67 us Internal reset operation 1 2 lt 3 gt lt 4 gt A RESET signal starts CPU operation at the lowest speed of the main system clock 10 7 At 6 0 MHz Note 1 after a wait time 21 8 ms At 6 0 MHz Note 2 for stable oscillation The PCC is rewritten for highest speed operation after a time elapse which is sufficient for the voltage on the Vpp pin to be high enough for highest speed operation The removal of commercial power is detected using for example an interrupt input Note 3 then SCC O is set to 1 to operate with the subsystem clock In this case subsystem clock
98. of the string effect instruction before the GETI instruction is the same as that of the instruction referenced by the GETI instruction the effect of the string effect instruction is canceled and the referenced instruction is not skipped When the group of the instruction after the GETI instruction is the same as that of the instruction referenced by the GETI instruction the effect of the string effect instruction caused by the referenced instruction is valid and the instructions after the referenced instruction are skipped uPD75518 User s Manual 10 3 Chapter 10 Instruction Set 10 1 2 Bit Manipulation Instructions 10 4 With the uPD75518 a variety of instructions are available for bit manipulation a Bit setting b Bit clearing c Bit testing d Bit testing e Bit testing and clearing f Boolean operation g Bit transfer SET1 mem bit SET1 mem bit CLR1 mem bit CLR1 mem bit SKT mem bit SKT mem bit SKF mem bit SKF mem bit SKTCLR mem bit AND1 CY mem bit OR1 CY mem bit XOR1 CY mem bit MOV1 CY mem bit MOV1 mem bit CY mem bit represents a bit address addressed by using a bit manipulation addressing mode fmem bit pnem L or H mem bit Particularly all of these bit manipulation instructions can be used for the I O ports so that I O port manipulation can be performed in a very efficient manner uPD75518 User s Manual Chapter 10 Instruction Set
99. pair functions as an auxiliary data pointer Example 1 INCS HL HL HL 1 skip at HL 00H ADDS XA BC lt XA BC skip at carry SUBC DE DE XA CY MOV XA XA lt XA MOVT XA QPCDE lt 12 DE ROM reference table SKE XA BC Skip if XA BC Example 2 The value of the count register TO for timer event counter 0 is tested until it becomes greater than the value of the BC register pair CLR1 MBE NO MOV XA TO Read count register SUBS XA gt BC BR YES YES BR NO NO Chapter 3 Data Memory Operations and Memory Figure 3 5 General Register Configuration 4 bit Processing Register bank 0 RBE RBS 0 Register bank 1 RBE RBS 1 Register bank 2 RBE RBS 2 Register bank 3 RBE RBS 3 3 20 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Figure 3 6 General Register Configuration 8 bit Processing When 0 When RBEsRBS 1 Register bank 0 Register bank 1 When RBE RBS 2 When 3 Register bank 2 Register bank 3 uPD75518 User s Manual 3 21 Chapter 3 Data Memory Operations and Memory 3 3 Memory mapped I O The uPD75518 employs memory mapped I O which maps peripheral hardware such as t
100. ports 4 5 and 12 to 14 anda pull down resistor can be provided for port 9 bit by bit These ports can therefore be used as input pins for the key switches or key matrix uPD75518 User s Manual 5 3 Chapter 5 Peripheral Hardware Functions Figure 5 2 Configurations of Ports 0 1 and 8 80 SCKO INT4 Soo Internal 4 A SCKO gt ue Bit 0 of Df Lp POGA JE O POO INT4 O 1 5 P02 SO0 SBO 5 510 581 Input buffer Output buffer which can be switched to either push pull output N ch open drain output Pull up resistor gt P ch Bit 1 of POGA Input buffer or fx 64 fe lt e Lus O P11 INT1 T L Internal bus P12 INT2 O P13 TIO A AAAA y y 5 INT2 INT1 INTO Input buffer with hysteresis 51 501 SCK1 Internal SCK1 PPO A A y O P80 PPO d P81 SCK1 O P82 S01 d P83 SI Input buffer 5 4 uPD75518 User s Manual Figure 5 3 Configurations of Ports Chapter 5 Peripheral Hardware Functions 3n and 6n n 0 to 3 Input buffer 0 Key interrupt Input buffer with hysteresis Nete PMmn 1 Bit m of POGA gt
101. ports with output latches ports 4 5 and 12 to 14 Each pin is an intermediate withstand voltage 10 V I O so it is suitable for interface with a peripheral circuit operating on a different power supply voltage For each pin a pull up resistor can be provided by mask option A RESET input clears the output latch of each port to zero and drives each pin high if a pull up resistor is provided or places each pin in high impedance state The input mode is selected with the port mode register in 4 bit units Ports 4 and 5 and ports 12 and 13 are paired respectively for 8 bit I O TIO Input Used Also for Port 1 This is an external event pulse input pin for the programmable timer event counter A Schmitt triggered input is used for the TIO pin PTOO Output Used Also for Port 2 PCL BUZ This is the output signal pin of the time out flip flop for the programmable timer event counter Square wave pulses appear on this pin To output a signal from the programmable timer event counter the output latch P20 must be cleared to zero and the bit for port 2 in the port mode register must be set to 1 output mode The output is cleared to 0 by the timer start instruction Output Used Also for Port 2 This is the output pin of the programmable clock output circuit It is used to supply the clock pulse to a peripheral LSI circuit such as a slave microcomputer or A D converter A RESET signal clears the clock mode register CLOM to
102. register MBS The memory bank select register is a 4 bit register used to store the high order four bits of a 12 bit data memory address The contents of this register specify a memory bank to be accessed The uPD75518 allows memory banks 0 and 15 only to be specified The MBS is set with the SEL MBn instruction n 0 1 2 3 15 Figure 3 2 shows the range of addressing using MBE and MBS settings A RESET signal initializes the MBS to 0 2 Register bank select register RBS The register bank select register specifies a register bank to be used as general registers a register bank can be selected from register banks 0 to 3 The RBS is set by the SEL RBn instruction n 0 to 3 A RESET signal initializes the RBS to 0 4 18 uPD75518 User s Manual Table 4 5 Register Bank to Be Selected with the RBE and RBS uPD75518 User s Manual Chapter 4 Internal CPU Functions Register bank Bank 0 is always selected Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected Always 0 x Don t care Chapter 4 Internal CPU Functions MEMO 4 20 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 1 Digital I O Ports The uPD75518 contains digital I O ports port 0 to port 15 The uPD75518 employs memory mapped I O This means that all I O ports are mapped to data memory space All data memory manipulation instructions a
103. rising edge of SCKO uPD75518 User s Manual 5 129 OEL S jenuew 51955 81498 0417 Master device processing transmitter Program processing Hardware operation Transfer line SCKO pin SBO pin Slave device processing receiver Program processing Hardware operation PA Interrupt handling preparation for next serial transfer Set Clear Set ni Generate 52 Output Output Clear EHE Serial reception BUSY BUSY When SVA 5100 I Address gt 1 4 15 4 5 1 5591 89 6 4 2 suonounJ 5 jenuew 51955 8rcc adr Master device processing transmitter Program processing PI Interrupt handling preparation for next serial transfer 22 Hardware operation Transfer line SCKO pin _ 2 Command Slave device processing receiver Output Clear BUSY BUSY N MA et Hardware operation MDD 121 8 1 52 5 1 69 911614 suonounJ 5 cel S jenuew 51955 8grcc adr Master device processing transmitter
104. status of a MOS device is unpredictable when power is turned on Sincecharacteristicsofa MOS device are determined bythe amountofionsimplantedin molecules the initial status cannot be determined inthe manufacture process NEC hasno responsibility forthe output statuses of pins inputand outputsettings andthecontentsof registers at poweron However NECassures operation after reset and items for modesetting ifthey are defined When youturn ona device having areset function be sure to resetthe device first QTOP is a trademark of NEC Corporation MS DOS is a trademark of Microsoft Corporation PC DOS and PC AT are trademarks of IBM Corporation The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others The devices listed in this document are not suitable for use in aerospace equipment submarine cables nu
105. status of processing being performed can be changed by program control Caution The user must always disable interrupts with the DI instruction before manipulating this flag and must enable interrupts with the El instruction after manipulating this flag uPD75518 User s Manual 4 5 uPD75518 User s Manual Chapter 4 Internal CPU Functions Memory bank enable flag MBE The memory bank enable flag is a 1 bit flag used to specify the address information generation mode for the high order four bits of a 12 bit data memory address The MBE can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the MBE is set to 1 the data memory address space is expanded according to the setting of the MBS allowing all data memory space to be addressed When the MBE is reset to 0 the data memory address space is fixed regardless of MBS setting See Figure 3 2 A RESET signal automatically initializes the MBE by setting the MBE to the content of bit 7 at program memory address 0 In vectored interrupt processing the MBE is automatically set to the content of bit 7 in the vector address table for servicing the interrupt Usually the MBE is set to 0 in interrupt processing and static RAM in memory bank 0 is used Register bank enable flag RBE The register bank enable flag is a 1 bit flag used to determine whether to expand the general register bank configuration The RB
106. the HALT mode A STOP instruction sets bit 3 of PCC and a HALT instruction sets bit 2 of PCC STOP instruction or HALT instruction must always be followed by an NOP instruction When changing a CPU operation clock pulse with the low order two bits of PCC a time lag may occur from the time when PCC is rewritten to the time when the CPU clock signal is changed When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode is released it is necessary to rewrite PCC and set the standby mode after as many machine cycles as required to change the CPU clock pulse have elapsed In a standby mode the contents of all registers and data memory that are stopped during the standby mode including general registers flags mode registers and output latches are retained Cautions 1 When the STOP mode is set the X1 input is internally connected to Vss ground potential to suppress leakage at the crystal oscillator circuitry This means that the STOP mode cannot be used with a system that uses an external clock as the main system clock 2 Reset all the interrupt request flags before setting the standby mode If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists the initiated standby mode is released immediately after it is set see Figure 6 1 When the STOP mode is set however the 75518 enters the HALT mode immediately after the STOP instruction
107. the result is 1 the transmission is regarded as successful If the result is 0 the occurrence of a transmission error is assumed uPD75518 User s Manual 5 105 Chapter 5 Peripheral Hardware Functions 5 106 7 Application of two wire serial 1 mode A serial bus is configured and multiple devices are connected to it Example A system 15 configured with LPD75518 as the master to which a uPD75104 uPD75402A and uPD7225G are connected as slaves pPD75518 master Port SCKO 500 580 uPD7225G 9 CK Sl uPD75402A uPD75104 SCK SI SO The uPD75104 connects the SI and SO pins manipulates the serial operation mode register except when serial data is output and frees the bus by setting off the output buffer The SO pin of the 75402 cannot go into a high impedance state so that a transistor must be connected as shown in the figure to make open collector output appear on the pin When data is input 00H must be set beforehand in the shift register to set the transistor off The timing of data output by each microcomputer must be predetermined The p PD75518 which is the master microcomputer outputs a serial clock and all slave microcomputers operate with an external clock uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 7 7 SBI Mode Operation The SBI serial bus interface is a high speed serial interface t
108. triggered input is used for this pin 2 2 10 INTO INT1 Inputs Used Also for Port 1 These are edge detection vectored interrupt input pins INTO has a noise eliminator The edge to be detected can be selected using the edge detection mode registers IMO IM1 1 INTO bits 0 and 1 of IMO a Rising edge active b Falling edge active c Both rising and falling edges active d External interrupt signal input disabled 2 INT1 bit 0 of IM1 a Rising edge active b Falling edge active INTO has a noise eliminator Two different sampling clocks for noise elimination can be switched The acceptable width of a signal depends on the CPU clock INT1 is an asynchronous input and can accept a signal with some high level width regardless of what the CPU clock is A RESET input clears IMO and IM1 to zero selecting rising edge active The INT1 pin can also be used to release the STOP and HALT modes but the INTO pin cannot Schmitt triggered inputs are used for the INTO and INT1 pins uPD75518 User s Manual 2 9 Chapter 2 Pin Functions 2 2 11 INT2 Input Used Also for Port 1 This is a rising and falling edge active external test input pin When INT2 is selected with the edge detection mode register IM2 or when the signal applied to this pin goes high the internal test flag IRQ2 is set INT2 is an asynchronous input and can accept a signal with some high level width regardless of the operating clock of the CPU
109. zero disabling clock output then the pin is placed in the normal mode to function as a normal port Output Used Also for Port 2 This is a frequency output pin A fixed frequency 2 048 kHz output on this pin can be used for sounding the buzzer or trimming the system clock frequency This pin is used also as the P23 pin and can be used only when bit 7 WM7 of the clock mode register WM is set to 1 A RESET signal clears WM7 to 0 then this pin is placed in the normal operation mode as a general port uPD75518 User s Manual Chapter 2 Pin Functions 2 2 8 SCKO 500 5 0 SIO SB1 Three State I O Used Also as Port 0 SCK1 SO1 SH Three State I O Used Also as Port 8 These are I O pins for serial interface They operate according to the setting of the serial operation mode registers CSIMO CSIM1 A RESET signal stops serial interface operation and places these pins in the input port mode A Schmitt triggered input is used for each pin except P80 and P82 2 2 9 INT4 Input Used Also as Port 0 INT4 is an external vectored interrupt input pin which is rising edge active as well as falling edge active When a signal applied to this pin goes from low to high or from high to low the interrupt request flag is set INT4 is an asynchronous input and can accept a signal with some high level width or low level width regardless of what the CPU clock is The INT4 pin can also be used to release the STOP and HALT modes Schmitt
110. 0 Clock timer Mode register WM 0 0 Note A RESET signal causes data at addresses 08FH 0FDH in data memory to be undefined 8 2 uPD75518 User s Manual Chapter 8 Reset Function Table 8 1 Statuses of the Hardware after a Reset 2 2 Hardware RESET signal in a standby mode RESET signal during operation Serial interface Channel 0 Serial interface Channel 1 A D converter Clock generator clock output circuit Interrupt Digital ports Shift register 0 SIOO Operation mode register 0 CSIMO SBI control register SBIC Slave address register SVA 01 5 output latch Shift register SIO1 Operation mode register 1 CSIM1 Serial transfer end flag EOT Mode register ADM EOC SA register Processor clock control register PCC System clock control register SCC Clock output mode register CLOM Interrupt IRQ1 IRQ2 IRQ4 request flag Other than above IRQxxx Interrupt enable flag IExxx Interrupt master enable flag IME INTO INT1 and INT2 mode registers IMO IM1 IM2 Output buffer Output latch mode registers PMGA PMGB PMGC Pull up resistor specification register POGA Bit sequential buffers BSBO to BSB3 Held 0 Held Held 0 04H EOC 1 Undefined 0 Undefined 0 Off Clear 0 Held Undefined 0 0 Undefined 1 Undefined 0 0 04H EOC 1 Undefined 0 Undefined 0 0 0 0 Off Clear 0
111. 0H Since T 1 ms the value N to be set in modulo register H MODH is fy 32 x T 1 4 194304 x 106 32 x 1 x 10 3 1 130 072 Therefore N is set to 130 When N 130 the actual time is obtained as follows T 32 N 1 fx 32 130 1 4 194304 x 106 0 999 ms The error is 0 0596 Sample program CLR1 MOV MOV MOV MOV MOV MOV EI EI MBE XA 20H Select resolution MODL XA XA 82H Determine set value MODH XA XA 10011011B TPGM XA Start timer Enable interrupt IETPG Enable timer interrupt uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 2 The timer pulse generator is used for electronic tuning by converting the PWM pulse signal output on the PPO pin to analog voltage form Figure 5 38 shows a sample circuit which applies to a voltage synthesizer TV tuner Figure 5 38 Sample Circuit Applicable to TV Tuners 110 V 0 75518 22 100 pF uPD6252 25 0 22 uF 0 22 uF 0 22 uF Electronic uPC574J tuner Even in the above simple circuit configuration high performance including a ripple voltage of 2 mVp p and a response rate of 100 ms can be obtained If fx is 4 19 MHz the ripple voltage components include a 4 096 kHz component caused by the basic period and a 128 Hz component caused by the secondary period The 128 Hz component is very small and the frequency 256 Hz can be regarded as the lowes
112. 1 W1 1 15 W2 2 5 us T 20 us D15 When data is transmitted and received alternately in the above data transfer format only one signal line is needed for high speed data transfer as shown in Figure 5 94 Figure 5 94 Bus Configuration Example Master M Slave 1 S1 75518 P60 port Slave 2 S2 port 51 51 gt 52 52 51 16 bit data uPD75518 User s Manual 5 165 Chapter 5 Peripheral Hardware Functions lt Sample program for reception gt MOV CHECK SKT BR NOP NOP NOP MOV1 MOV NOP NOP INCS BR lt Sample program for transmission gt MOV LOOP SET1 MOV1 NOP MOV1 MOV WAIT INCS BR NOP NOP CLR1 INCS BR 5 166 L 0 PORT6 0 P60 1 CHECK NO YES CY PORT6 0 BSBO L CY L CHECK L 0 PORT6 0 P60 lt 1 CY BSB0 L CY lt transfer data PORT6 0 CY P60 lt data A 0EH Wait for 8 machine cycles A WAIT PORT6 0 P60 lt 0 L LOOP uPD75518 User s Manual Chapter 6 Interrupt Function The uPD75518 has seven vectored interrupt sources and two testable interrupt sources allowing a wide range of applications In addition the interrupt control circuitry of the 75518 has the following features for very high speed interrupt processing a An interrupt master enable flag IME and interrupt enable flag IExxx are provided to contro
113. 1 Serial transfer start request Nete 2 Flag operation IRQCSIO is set on rising edge of 9th clock of 5 1 Meaning of signal Timing of signal output on serial data bus Address of slave device on serial bus Directions and messages to slave device Numeric processed by slave or master device 2 2 9poW 195 ul pasp 5 5 cpL 6 914 1 suonounJ 5 Chapter 5 Peripheral Hardware Functions 6 Pin configuration The configurations of serial clock pin SCKO and serial data bus pin SBO or SB1 are as follows a SCKO Pin for serial clock I O 1 Master CMOS push pull output 2 Slave Schmitt input b 580 581 Pin for serial data Output to SBO or SB1 is an N ch open drain output and input is Schmitt input for both the master and a slave The serial data bus line must be externally pulled up because it has originally an N ch open drain output Figure 5 67 Pin Configuration Slave device LILI wu Cook outu Y Clock output 4 gt Cio kinbut Clock input Master device N ch open drain SBO SB1 i SBO SB1 N ch open drain 500 Serial data bus gt lt 500 TT Caution When data is received the N ch transistor must be turned off so FFH must b
114. 1 LOOP uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Figure 3 3 Updating Static RAM Addresses X OH Low order 4 bits OxH DL 4 bit transfer High order 4 bits Automatic decrement 4 bit DECSL manipulation 8 bit manipulation Y FxH Direct addressing Bit manipulation 4 bit transfer 8 bit transfer Automatic increment INCS L x FH DE 4 bit transfer H mem bit Bit manipulation uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory 5 8 bit register indirect addressing HL In this addressing mode the data pointer HL register pair indirectly specifies any area in the data memory space in units of eight bits The 4 bit data at the address determined with bit 0 of the data pointer bit 0 of the L register set to 0 and the 4 bit data at the address incremented by 1 are processed as a pair on an 8 bit basis with the 8 bit accumulator XA register pair A memory bank is specified in the same way as the 4 bit register indirect addressing with the HL register specified In this case MBE MBS This addressing mode can be applied to the MOV XCH and SKE instructions Example 1 A comparison is made to determine whether the value of the count register TO of timer event counter 0 is equal to the data at addresses 30H and 31H DATA EQU 30H CLR1 MBE MOV HL ZDATA MOV XA TO XA Count register 0
115. 1 Configuration of the Basic Interval Timer 5 38 5 3 2 Basic Interval Timer Mode Register BTM 5 39 5 3 3 Operation of the Basic Interval Timer 5 41 5 3 4 Application Examples of the Basic Interval Timer 5 42 TOC 4 uPD75518 User s Manual Contents 5 4 COCK TIME iiec bri tr iir rane adag ee 5 44 5 4 1 Configuration of the Clock 5 44 5 4 2 Watch Mode 5 45 5 5 Timer Event Counter eese 5 46 5 5 1 Configuration of the Timer Event Counter 5 46 5 5 2 Basic Configuration and Operation of the Timer Event 610101 5 48 5 5 3 Timer Event Counter Mode Register 5 49 5 5 4 Timer Event Counter Output Enable 5 51 5 5 5 Operation Mode of the Timer Event 5 51 5 5 6 Time Setting in the Timer Event Counter 5 53 5 5 7 Notes Timer Event Counter Applications 5 55 5 5 8 Applications of the Timer Event Counter 5 59 5 6 Timer Pulse Generator eere 5 60 5 6 1 Functions of the Timer Pulse
116. 102 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Command trigger bit W CMDT Control bit for command signal CMD trigger output By setting CMDT 1 the SOO latch is cleared Then the CMDT bit is automatically cleared Caution Never use bits other than RELT and CMDT in the two wire serial I O mode 2 Communication operation The two wire serial I O mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the serial clock SCKO Transmit data is latched on the 500 latch and is output on the 5 2 pin or SB1 pin starting with the MSB Receive data applied to the SBO pin or SB1 pin is latched in the shift register on the rising edge of SCKO When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSIO Figure 5 49 Timing of Two Wire Serial I O Mode SCKO 1 2 3 4 5 6 7 8 s SUE GS EF Ee qom IRQCSIO A A Completion of transfer Transfer operation is started in phase with falling edge of SCKO Execution of instruction that writes date to SIOO Transfer start request The 580 or 581 pin becomes N ch open drain when specified as the serial data bus so the voltage level on that pin must be pulled up externally When data is received the N ch trans
117. 11 11 100010 11 1 1 NS No 0100 1 11 1 1 1 0100 10 1 1 No 01110110110010 0 1 1 10 1 1 0N51 1 No 01110010110010 01 1 100 1 0N5 1 1 01110110100011 01110110110011 100000 01100100100 0NN 011001000 1 Ts T4 To T4 To uPD75518 User s Manual 10 23 Chapter 10 Instruction Set 10 4 Functions and Applications of the Instructions 10 4 1 Transfer Instructions MOV A n4 Function A 4 n4 13 0 0 FH Transfers the 4 bit immediate data n4 to the A register 4 bit accumulator The string effect group A can be utilized When MOV A n4 and or MOV XA n8 instructions are located contiguously the string instructions following an executed instruction are processed as NOP instructions Examples 1 The data OBH is set in the accumulator MOV A 0BH 2 Data to be output to port 3 is selected from 0 to 2 0 A 0 A1 MOV A 1 A2 MOV A 2 OUT PORT3 A MOV reg1 n4 Function regi lt 4 n4 13 0 Transfers the 4 bit immediate data n4 to register reg1 A X H L D E B C MOV rp n8 Function rp n8 n8 17 0 00H FFH Transfers the 8 bit immediate data n8 to register pair rp XA HL DE BC When XA or HL is specified as rp a string effect can be utilized There are two types of string effects group A MOV A n4 instruction and MOV XA 18 instruction and group B MOV HL n8 instruction When instructions in the same
118. 2 0 2 2 6 807 diiring the ninth clock cycle AL When ACKE 1 at this point b When ACKE is set after transfer completion SCKO 8 lol LJ LIPS Li SBO SB1 02 ACK The ACK signal is output during the first clock cycle immediately after ACKE is set ACKE gt When is set during this period and ACKE 1 at the falling edge of the next SCKO c When ACKE 0 at time of transfer completion SCKO The ACK signal is not output SBO SB1 ACKE A When ACKE 0 at this point d When ACKE 1 period is too short see LILILILIL The ACK signal is not ACKE gt When is set or cleared during this period and ACKE 0 at the falling edge of SCKO uPD75518 User s Manual 5 123 Chapter 5 Peripheral Hardware Functions Figure 5 65 Operation of ACKD a When ACK signal is output during the ninth SCKO clock i Transfer start request 580 581 ACKD Transfer start request c Clear timing for case where start of transfer is directed during BUSY Transfer start request 5100 SCKO SBO SB1 ACKD Figure 5 66 Operation of BSYE SCKO 6 7 8 9 SBO SB1 02 D1 Do BUSY BSYE When BSYE 1 at this point When reset operation is executed during this period and BSYE 0 at the falling edge of SCKO lt gt 5 124 uPD75518 User s Manual jenuew 5195
119. 2 12 2 2 22 for uPD75P518 only ttes 2 12 eet M tc NS MI E LC Seca 2 12 uPD75518 User s Manual TOC 3 Contents BOON A RR UU 2 12 2 3 Pin Input Output 2 13 2 4 Connection of Unused Pins 2 16 2 5 Selection of a Mask Option 2 17 Chapter 3 Data Memory Operations and Memory Map 3 1 31 Data Memory Bank Structure and Addressing Modes 3 2 3 1 1 Data Memory Bank Structure 3 2 3 1 2 Data Memory Addressing 3 4 3 2 General Register Bank Configuration 3 17 3 3 l Q 3 22 Chapter 4 Internal CPU 4 1 4 1 Program Counter 4 1 4 2 Program Memory 4 2 4 3 Data Memory RAM nenne 4 5 4 3 1 Data Memory 4 5 4 3 2 Specification of a Data Memory 4 7 4 4 General Register orn creer rina n t
120. 4 19 MHz and buzzer output is enabled CLR1 MBE MOV XA 84H MOV WM XA Set WM Figure 5 26 Format of the Watch Mode Register Address 7 6 5 4 3 2 1 0 Symbol DT T T one va F98H WM Count clock fw selection bit Operation mode selection bit Clock operation enable disable bit BUZ output enable disable bit Count clock fw selection bit Selects divided system clock output 128 Selects subsystem clock Operation mode selection bit NE Normal clock mode E sets IRQW at 0 5 s Advanced clock mode ae sets IRQW at 3 91 ms Clock operation enable disable bit Se emm 2000 BUZ output enable disable bit Disables BUZ output iT Enables BUZ output uPD75518 User s Manual 5 45 Chapter 5 Peripheral Hardware Functions 5 5 Timer Event Counter 5 5 1 Configuration of the Timer Event Counter The uPD75518 contains one timer event counter Figure 5 27 shows the configuration The timer event counter has the following functions a Programmable interval timer operation b Output of a square wave at a given frequency to the PTOO pin c Event counter operation d Frequency divider operation that divides an input to the TIO pin by N and outputs the result to the PTOO pin e Supply of the serial shift clock signal to a serial interface circuit f Function of reading the state of counting 5 46 uPD75518 User s Manual jenuew 51955 8rcc adr
121. 5 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Frequency divider The frequency divider divides the output fx of the main system clock oscillator to generate various clocks Treatment of the subsystem clock pins when not used If the subsystem clock is not required for low power consumption or clock operation the XT1 and XT2 pins must be treated as follows XT1 Connected to 55 or XT2 Open In these states however a little leakage current flows through the internal feedback resistor of the subsystem clock oscillator when the main system clock is stopped To prevent this the internal feedback resistor can be disconnected by a mask option In this case the XT1 and XT2 pins must also be treated as listed above Specify the mask option for the resistor when ordering the LSI device Chapter 5 Peripheral Hardware Functions 5 2 3 System Clock and CPU Clock Setting 1 Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the low order two bits of the PCC and the least significant bit of the SCC This switching is not performed immediately after the contents of the registers are rewritten but the system operates with the previous clock for some machine cycles Accordingly after this time period the STOP instruction must be executed or SCC 3 must be set to 1 to terminate main system clock generation Table 5 5 Maximum Time Required to Change
122. 5 8grcc adr 921 9 Signal name Bus release signal REL Master Definition Rising edge of SBO or SB1 when SCKO 1 Timing chart Condition for output RELT is set Flag operation RELD is set CMDD is clear ed Meaning of signal Indicates that CMD signal follows and data transmitted is address data Command signal CMD Master Falling edge of SBO or SB1 when SCKO 1 SCKO Ww SBO SB1 CMDT is set CMDD is set i Data transmitted after REL signal output is address ii Data transmitted with REL signal not being output is command Acknowledge signal ACk Low level signal output on SBO or SB1 during one SCKO clock cycle after serial reception is completed Busy signal BUSY Synchronous BUSY signal Low level signal output on SBO or SB1 after acknowledge signal Ready signal READY High level signal output on SBO or SB1 before serial transfer is started or after serial transfer is completed Synchronous BUSY output SCKO SBO SB1 D SBO SB1 DO lt gt 1 lt 2 gt ACKT is set BSYE 1 ACKD is set Indicates completion of reception Indicates that serial reception is disabled because processing is in progress 1 BSYE 0 2 Execution of instruction to write data to 5100 Transfer start request Indicates that serial reception is enabled
123. 75517 uPD75518 and uPD75P518 are 4 bit single chip microcomputers Their features include high speed operations a large number of I O lines and a variety of capabilities based on the 75X series architecture The uPD75517 and uPD75518 outperform their predecessor uPD75516 by increasing the ROM and RAM capacities of the LPD75516 and speeding up the instruction execution The uPD75P518 uses one time PROM or EPROM instead of built in mask ROM which is used in the uPD75518 for increased ROM capacity The one time PROM version allows the user to write programs once It can be used for small quantities of multiple products It is also useful to shorten product development time The EPROM version allows the user to write erase and rewrite programs It is best suited for system evaluation The wPD75517 75518 and uPD75P518 have the following features The uPD75P518K is not intended for use in mass produced products it does not offer a sufficiently high level of reliability for such applications The use of theuPD75P518K should be restricted to functional evaluation in experimental or trial manufacture Function for specifying the instruction execution time useful for high speed operation and power saving Built in A D converter operable on low voltage Eight channels with 8 bit resolution Successive approximation system 2 7 to 6 0 V Sixty four I O lines Two built in 8 bit serial interfaces Built in N
124. 8 bit microcomputer and thereby enables to program using mainly general registers 1 When used as a 4 bit register When the general register area is used on a 4 bit basis eight general registers the X A B C D E H and L registers are available in the register bank specified with RB 5 as shown in Figure 3 4 The A register functions as 4 bit accumulator which performs transfers arithmetic logical operations and comparisons The other general registers perform transfers comparisons and increments decrements with the accumulator uPD75518 User s Manual 2 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory When used as an 8 bit register When the general register area is used on an 8 bit basis the register pairs in the register bank specified by RBE RBS can be specified as XA BC DE and HL as shown in Figure 3 5 and the register pairs in the register bank that has the inverted value of bit 0 of the register bank RB can be specified as XA BC DE and HL thus providing up to eight 8 bit registers The XA register pair functions as an 8 bit accumulator which performs transfers arithmetic logical operations comparisons and increments decrements of 8 bit data The other register pairs perform transfers arithmetic logical operations comparisons and increments decrements with the accumulator The HL register pair functions mainly as a data pointer and the DE register
125. A 431 3 ms 31 3 ms INT4 INT4 soe POO INT4 HALT mode Low speed High speed STOP instruction uPD75518 User s Manual Chapter 7 Standby Function Sample program INT4 service program MBE 0 VSUB4 SKT BR SET1 WAIT SKT BR SKT BR MOV MOV MOV L MOV EI EI RETI PDOWN MOV MOV MOV MOV MOV MOV DI DI MOV MOV NOP STOP NOP RETI 0 POO 1 PDOWN Power down 3 Power on IRQBT Wait for 31 3 ms WAIT PORTO 0 Chattering check PDOWN A 0011B PCC A Set high speed mode Set port mode register PMGm XA A 0 Lowest speed mode PCC A XA 00H PMGA XA l O port high impedance PMGB XA PMGC XA IEO Disable INTO and INTTO IETO A 1011B BTM A Wait time 31 3 ms Set STOP mode uPD75518 User s Manual Chapter 7 Standby Function 2 Application of the HALT mode at fy 4 19 MHz fxr 32 768 kHz lt Intermittent operation under the following conditions gt The standby mode is set on the falling edge of INT4 and is released on the rising edge of INT4 n the standby mode intermittent operation is performed at intervals of 250 ms INTBT INT4 and are low order interrupts The lowest speed CPU clock is used for operation in the standby mode Timing chart gt IRE M Voltage on OV POO INT4 Intermittent operation
126. ADM1 ADM A ANO O Control circuit AN1 Sample and hold circuit AN2 O AN3 O Multi SA register 8 plexer AN4 Comparator AN5 O gt AN6 O AN7 Tap decoder AVner AAVN ANAV A NAVN 9 R 2 R R R R 2 Series resistor string AVss O 5 152 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 1 Pins of the A D converter a ANO to AN7 ANO to AN7 are the input pins for eight analog signal channels Analog signals subject to A D conversion are applied to these pins The A D converter contains a sample and hold circuit and analog input voltages are internally maintained during A D conversion Caution Do not apply voltage out of specification to ANO to AN7 inputs If a voltage higher than Vpp or lower than Vss is applied even when the maximum absolute rating is not exceeded the conversion result for an associated channel becomes unpredictable In addition the conversion results for other channels may be affected b A reference voltage for the A D converter is applied to this pin By using an applied voltage across AVngr AVss signals applied to ANO to AN7 are converted to digital signals c AVss The GND pin for the A D converter Always use the same voltage as that of the Vss pin 2 A D conversion mode register ADM The A D conversion mode register ADM is an 8 bit re
127. Address FB3H 3 2 1 0 Symbol PCC CPU clock selection bit Operation with fx 6 0 MHz 0 0 SCCO 1 is actual frequency at fx 6 0 MHz is actual frequency at fxr 32 768 kHz CPU clock frequency 010 fx 64 93 7 kHz fx 16 375 kHz fx 8 750 kHz fx 4 1 5 MHz Operation with f x 4 19 MHz 5 0 0 SCCO 1 is actual frequency at fx 4 19 MHz is actual frequency at 32 768 kHz 1 machine cycle CPU clock frequency 1 machine cycle 10 7 8 fxr 4 8 192 kHz 122 15 2 67 15 Not to set 1 33 8 fxi 4 8 192 kHz 0 67 us CPU clock frequency fx 64 65 5 kHz 1 16 262 kHz 110 fx 8 524 kHz fx 4 1 05 MHz 1 machine cycle CPU clock frequency 1 machine cycle 15 8 us fxr 4 8 192 kHz 122 1 91 fxt 4 8 192 kHz 122 0 95 Remarks 1 fx Output frequency from the main system clock oscillator 2 fxr Output frequency from the subsystem clock oscillator CPU operation mode control bits Normal operation mode HALT mode STOP mode Not to be set uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 2 System clock control register SCC The SCC is a 4 bit register for selecting CPU clock with the least significant bit and for controlling the termination of main system clock gener
128. Bits 3 and 2 are always set to 0 Remarks Only bit 3 can be manipulat Only bit 3 can be manipulated FAOH FA4H 6 Timer pulse generator modulo register MODH Clock mode register WM Timer event counter 0 mode register TMO Timer event counter 0 count register TO Timer event counter 0 modulo register TMODO Only bit 3 can be manipulat ed mem bit Note 1 In 4 bit manipulation RBS and MBS can be manipulated separately In 8 bit manipulation these two locations can be manipulated at a time with BS specified Note 2 TOEO Output enable flag W of timer event counter 0 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Figure 3 7 uPD75518 I O Map 2 4 Address Hardware name symbol R W can be manipulated manipulation fmem bit Manipulated with EI DI instruction Remarks Program status word PSW 2 Interrupt priority select register IPS Ree FB3H Processor clock control register PCC FB5H INT1 mode resistor IM1 PAK FB6H INT2 mode register IM2 PER FB7H System clock control register SCC mo mor aw O zB 28 TEE RE 2 d Bit 2 is always Bits 3 2 and 1 are always Bits 3 and 2 are always 0 Bits 2 and 1 are always 0 mem bit pmem L uPD75518 User s Manual 3 25 Uma ems wares
129. C to be set or wait using a software timer Read the SA register Caution Note 24 fy 3 81 at fy 4 19 MHz 5 156 There is a delay of up to 24 fy seconds 2 67 us at fx 6 0 MHz Note from the setting of SOC to the clearing of EOC after A D conversion is started EOC must be tested when a time indicated in Table 5 16 has elapsed after the setting of SOC Table 5 16 also indicates A D conversion times uPD75518 User s Manual Table 5 16 Setting of SCC and PCC Chapter 5 Peripheral Hardware Functions Setting values of SCC PCC A D conversion time Wait time from Wait time from SOC setting to SOC setting to SCC3 SCCO PCC1 PCCO EOC test A D conversion completion 0 0 0 0 168 fy seconds Note Waiting not 3 machine cycles 28 0 us at required fx 6 0 MHz 0 1 1 machine cycle 11 machine cycles 1 0 2 machine cycles 21 machine cycles 1 1 4 machine cycles 42 machine cycles 0 1 X X Waiting not required Waiting not required 1 X Conversion stopped Note 168 fx 40 1 us fy 4 19 MHz Remark x Don t care Figure 5 87 Timing Chart of A D Conversion SA register Previous data Time elapsed before 1 A D conversion starts A X 7 Sampling time Maximum of 2 fx s SOC Undefined Result of conversion lt A D conversion 168 fx s Note Note 168 fy 28 0 us fx 6 0 MHz 40 1 us fx 4 19 MHz
130. CB and CALLF instructions 2 When referencing two 1 byte instructions with a GETI instruction only the combinations listed in the table below are valid First byte instruction Second byte instruction MOV A HL INCS L DECS L MOV HL A INCS H DECS H XCH A HL INCS HL INCS E MOV A DE DECS E INCS D XCH A DE DECS D INCS DE MOV A QDL INCS L L DECS L XCH A DL INCS D L DECS D 10 2 uPD75518 User s Manual Chapter 10 Instruction Set Cautions 3 Branch and subroutine instructions can be referenced by the GETI instruction only when their destination addresses are in the 16K byte space 0000H to 3FFFH A branch or subroutine instruction to an address from 4000H to 5F7FH or 4000H to 7F7FH Note cannot be referenced by the GETI instruction Note 4000H to 5F7FH 75517 4000H to 7F7FH uPD75518 and 75 518 Since the PC is not incremented during execution of a GETI instruction control returns to the address next to the GETI instruction after the execution of the GETI instruction When the instruction before a GETI instruction has the skip function the GETI instruction is skipped in the same way as for other 1 byte instructions When the instruction referenced by a GETI instruction has the skip function the instructions after the GETI instruction are skipped When a string effect instruction is referenced by a GETI instruction the following results are obtained When the group
131. CH G Temperament Frequency Hz 440 446 16 493 88 523 248 554 368 587 328 662 256 659 248 698 464 739 984 783 984 830 608 Modulo register setting Output from PPO MODL MODH Frequency Hz Error Hz 00010000B 94H 439 8 0 2 0 045 00010000B 8CH 464 8 1 36 0 29 00010000B 84H 492 8 1 08 0 2296 00100000B F9H 524 29 1 04 0 20 00100000B EBH 555 39 1 02 0 18 00100000B DEH 587 77 0 442 0 075 00100000B D2H 621 2 1 06 0 1796 00100000B C6H 658 7 0 548 0 083 00100000B BBH 697 2 1 264 0 12 00100000B BOH 740 5 0 516 0 070 00100000B A6H 784 9 0 916 0 117 00100000B 9DH 829 7 0 908 0 11 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 4 A square wave output on the PPO pin is used as a baud rate genera tor for the serial interface The PPO is connected to SCKO as shown below pPD75518 Timer pulse generator PPO Serial interface ecko The timer pulse generator uses the main system clock whose frequency fx is divided by two as count pulse To obtain a baud rate of 9600 use a system clock whose frequency fx is 4 9142 MHz The mode register TPGM is set to 10111011B square wave output mode The modulo register is set as listed below Modulo register L MODL is setto 08H Baud rate Modulo register H MODH 9600 03H 4800 07H 2400 OFH 1200 1FH 600 3FH 300 7FH 150 FFH Caution In this a
132. CHONS 5 78 1 Serial operation mode register 0 CSIMO 5 78 2 Serial bus interface control register SBIC 5 82 3 Shift register 0 51 5 85 4 Slave address register 5 87 5 7 4 Operation Halt 5 88 5 7 5 Three Wire Serial Mode 5 90 1 Register setting cee 5 90 2 Communication operation 5 93 3 Serial clock selection 5 94 ee ecc e RE Hoe Etro 5 94 5 Switching between MSB and LSB as the first transfer 4 1 1 5 95 6 Transfer 5 96 7 Application of the three wire serial mode 5 97 5 7 6 Two Wire Serial Mode 5 100 1 Register 0 5 100 uPD75518 User s Manual TOC 5 Contents 2 Communication 5 103 3 Serial clock selection 5 104 4 2SIQM AIS 525545 ete eter rien tar e Ine 5 104 5 Transfer start i5 ede eene 5 105 6 Error deletion ix ie indeed 5 105 7 Application of two wire serial mode
133. Case of Error 5 142 SCKO PO1 Pin Circuit Configuration 22200002002 5 143 Block Diagram of the Serial Interface Channel 1 5 146 Format of Serial Operation Mode Register 1 CSIM1 5 147 Timing of the Three wire Serial 5 149 Block Diagram of the A D Converter sss 5 152 Format of the A D Conversion Mode 5 154 Timing Chart of A D Conversion 1 0 0000000000000 1 5 157 Relationship Ideal between Analog Input Voltages and Results of A D Conversion 222 1 esses essent nnne nns 5 158 Reducing Power Consumption in the Standby 5 159 Analog Input Pin Connection 5 160 Format of the Bit Sequential Buffer sees 5 162 Serial Transfer Format 1 esses rnnt rennen 5 164 Serial Transfer Format 11 5 165 Bus Configuration Example sisse sienne enint sitne 5 165 TOC 11 Contents 4 4 Figure 6 1 Block Diagram of Interrupt Control 6 2 Figure 6 2 Interrupt Vector Tabla s s dedi A ded denne Penates 6 4 Figure 6 3 Configurations of the INTO INT1 and INT4 Circuits 6 8
134. Do 0 Do FFOH FFFH manipulatable bits FCOH FFFH manipulatable bits Manipulatable bits of accessible memory bank uPD75518 User s Manual Bn Immediate data for bit Fn Immediate data for fmem Low order four bits of address Gn Immediate data for pmem Bits 2 to 5 of address Immediate data for mem Low order four bits of address 10 19 Chapter 10 Instruction Set Instruction Mnemonic Operand Instruction code B B2 B3 Transfer MOV A n4 1 1 1 d lo h Ip 1 14 00110 101 lo k lp 1 Ro Ry rp n8 0 0 0 1 PoP 1 l5 l4 l5 lo H lp A rpa 110005010 XA HL 010101000011000 HL A 1101000 HL XA 010101000010000 A mem 01000 1 1 D7Dg 05 04 93 Da D4 Do XA mem 0100 0 1 0 05 0605 04 D3 05 D4 Do mem A 00100 1 1 D7DgDs5 04 93 05 D4 00 mem XA 0010 0 1 050605 04 93 Do D4 Do A reg 001100101 1 1 1 88 XA rp 0101010010 1 reg1 A 0011002101 11 0 Ro R Ro 1 01010100101 0 PoP Po XCH A rpa 110105000 XA HL 010101000010001 A 011001 1 05 D 05 04 93 Da D4 Do 011001 00705 05 0403020 0 A reg1 1 0 1 1 RoR XA rp 01010100100 0 PoP Po Table MOVT XA PCDE 1010100 XA PCXA 1010000 XA BCDE 1010101 XA BCXA 1010001 Bit transfer MOV1 1j 0111101 2 51 0011011 2 10 20 uPD75518 User s Manual Chapter 10 Instruction Set Instruction Mnemonic Operand Instruction code By Bo B3 Arithmetic ADDS
135. E can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the RBE is set to 1 a set of general registers can be selected from register banks 0 to 3 depending on the setting of the register bank select register RBS When the RBE is reset to 0 register bank 0 is always selected as general registers regardless of the setting of the RBS A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program memory address 0 When a vectored interrupt occurs the RBE is automatically set to the state of bit 6 in the vector address table for servicing the interrupt Usually the RBE is set to 0 in interrupt processing Register bank 0 is used for 4 bit processing and register banks 0 and 1 are used for 8 bit processing Chapter 4 Internal CPU Functions 4 8 Bank Select Register BS The bank select register BS consists of a register bank select register RBS and memory bank select register MBS which specify a register bank and memory bank to be used respectively The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction respectively The contents of the BS can be saved to or restored from a stack memory eight bits at a time by using the PUSH BS POP BS instruction Figure 4 12 Bank Select Register Format Address s MBS d RBS Symbol F82H MBS3 MBS2 MBS1 MBSO RBS1 RBSO BS 1 Memory bank select
136. EC serial bus interface SBI The uPD75P518 can operate on the same supply voltage as the uPD75517 which uses mask ROM 2 7 to 6 0 V uPD75518 User s Manual 1 1 Chapter1 General The uPD75517 uPD75518 and uPD75P518 provide features suitable for control and therefore can be used for various applications as listed below VCR system control Audio equipment such as CD players Push button telephone Radio equipment Data terminal PPC Air conditioner 1 2 uPD75518 User s Manual Chapter1 General 1 1 Function of the uPD75518 Sub Series Products Product Item ROM in bytes RAM x 4 bits General registers Instruction Main system clock Subsystem clock I O lines Note 1 Total Number of CMOS input lines Number of CMOS lines Number of N ch open drain I O lines A D converter Operating voltage Timer counter Serial interface Stack bank selection register SBS Stack operation Vectored interrupt Test input Instruction set uPD75517 PD755148 wPD75P518 75516 75 516 24448 32640 32640 PROM 16256 16256 PROM 1024 512 4 bits x 8 or 8 bits x 4 x 4 banks 0 67 us 1 33 us 2 67 us or 10 7 us when operating at 6 0 MHz 0 95 us 1 91 us 3 82 us or 15 3 us when operating at 4 19 MHz 0 95 us 1 91 us or 15 3 us when operating at 4 19 MHz 122 us When operating at 32 768 kHz 64 16 Shared with INT SIO PPO and ana
137. EQU 32H 2 SEL MBO MOV H FLAG1 SHR 6 MOV1 CY H FLAG1 lt FLAG1 XOR1 CY H FLAG2 CY lt CY FLAG2 H FLAG3 CY FLAG3 lt CY uPD75518 User s Manual 3 15 Chapter 3 Data Memory Operations and Memory 7 Stack addressing This addressing mode is used for save restoration operation in interrupt processing or subroutine processing In this addressing mode the address indicated by the stack pointer SP of data memory bank 0 1 2 or 3 that is selected by the stack bank select register SBS is specified This addressing mode can be used for register save restoration operation using the PUSH or POP instruction as well as save restoration operation in interrupt and subroutine processing Example 1 A register is saved and restored in subroutine processing SUB PUSH XA PUSH HL PUSH BS Save MBS and RBS POP BS POP HL POP XA RET Example 2 The contents of the HL register pair are transferred to the DE register pair PUSH HL POP DE DE lt HL Example 3 A branch is made to the address indicated by the XABC register PUSH BC PUSH XA RET Branch to address XABC uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory 3 2 General Register Bank Configuration The uPD75518 contains four register banks each consisting of eight general registers X A B C D E H and L These registers are mapped to addresses OOH to 1FH in memory bank 0 of the data memory Fi
138. General 1 2 Ordering Information 1 Ordering information Part number Package On chip ROM uPD75517GF x 3B9 80 pin plastic QFP 14 x 20 mm Mask ROM uPD75518GF ooc 3B9 80 pin plastic QFP 14 x 20 mm Mask ROM uPD75P518GF 3B9 80 pin plastic QFP 14 x 20 mm One time PROM uPD75P518K 80 pin ceramic WQFN EPROM Remark xxx is a ROM code number 2 Quality grade Part number Package Quality grade uPD75517GF xxx 3B9 80 pin plastic QFP 14 x 20 mm Standard uPD75518GF xxx 3B9 80 pin plastic QFP 14 x 20 mm Standard uPD75P518GF 3B9 80 pin plastic QFP 14 x 20 mm Standard uPD75P518K 80 pin ceramic WQFN Not applied Remark xxx is a ROM code number Caution The Quality grade of the uPD75P518K is Not applied Use the uPD75P518K only for functional evaluation Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 1 4 uPD75518 User s Manual Chapter1 General 1 3 Differences between the PD75P518 75517 and 75518 The uPD75P518 differs from the 75518 in that it uses one time PROM or EPROM instead of masked ROM Table 1 1 lists the differences between the LPD75P518 uPD75517 and uPD75518 Always check these differences when intending to mass produce application system based on a masked ROM type after completing development using a PROM bas
139. HL lt A Transfers the contents of the A register to the data memory location addressed by the HL register pair MOV HL XA Function HL lt A HL 1 lt X Transfers the contents of the A register to the data memory location addressed by the HL register pair and transfers the contents of the X register to the next memory address However if the contents of the L register are odd numbered an address with the low order bit ignored is specified uPD75518 User s Manual 10 25 Chapter 10 10 26 Instruction Set MOV A mem Function lt mem Dz g 00H FFH Transfers the data at the data memory location addressed by the 8 bit immediate data mem to the A register MOV XA mem Function A lt mem X lt mem 1 07 0 00H FEH Transfers the data at the data memory location addressed by the 8 bit immediate data mem to the A register and transfers the data at the next address to the X register An even address can be specified with mem Example The data at addresses 40H and 41H are transferred to the XA register pair MOV XA 40H MOV mem A Function mem mem Dz g 00H FFH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate data mem MOV mem XA Function mem lt A mem 1 X mem 07 0 00H FEH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate data mem and tr
140. HL LOOP MOV XA HL First read MOV BC XA MOV XA HL Second read SKE XA BC BR LOOP To obtain a time required for stable system clock generation in releasing the STOP mode a wait function is available which stops the operation of the CPU until the basic interval timer overflows The wait time is fixed after a RESET signal is generated On the other hand a wait time can be selected by setting the BTM when the STOP mode is released with an interrupt occurrence In this case possible wait times are the same as the interval times shown in Figure 5 24 The BTM must be set before the STOP mode is set See Chapter 7 for details uPD75518 User s Manual 5 41 Chapter 5 Peripheral Hardware Functions 5 3 4 Application Examples of the Basic Interval Timer Example 1 Example 2 A basic interval timer interrupt is enabled and an interrupt generation interval of 1 95 ms when a clock of 4 19 MHz is used is set SEL MB15 MOV A 1111B BIM A Setting and start El Enable an interrupt El IEBT Enable a BT interrupt Use as a watchdog timer A program is divided into modules each of which can be executed within the time set in the BT and the BT and the interrupt request flag IRQBT are cleared when the execution of each module is completed If an interrupt occurs it is treated as a crash Set an interrupt occurrence interval to 7 8 ms at 4 19 MHz and divide a program into modules so that the execution time of each mo
141. Interface Channel 1 Functions The uPD75518 has two modes The functions of the two modes are outlined below 1 Operation halt mode This mode is used when serial transfer is not performed This mode reduces power consumption 2 Three wire serial I O mode 8 bit data transfer is performed using three lines Serial clock SCK1 serial output SO1 and serial input 511 The three wire serial 1 mode allows full duplex transmission so data transfer be performed at higher speed 8 bit serial transfer always starts with the MSB The three wire serial mode enables connections to be made with the 75X series 78K series and many other types of peripheral I O devices 5 8 2 Serial Interface Channel 1 Configuration Figure 5 82 shows the block diagram of the serial interface channel 1 uPD75518 User s Manual 5 145 9rL G jenuew 51955 grcc adr P83 SI1 5101 write signal serial start signal Internal bus Bit manipulation P82 SO1 Shift register 1 8 7 Serial operation mode register 1 8 P81 SCK1 0 gt Clear Set Serial clock selector CSIM1 A Bit manipulation Serial transfer end flag EOT fx 28 fx 24 1 Jeuueu2 ay jo Y20419 28 a4nbi4 suonounJ
142. Interrupt processing operations are 70 i d o MBE 0 is to be set in the vector table 1 0 1 RETI Y Remark MBE 1 MBE 0 The contents of the MBE are automatically saved or restored at the time of subroutine processing so that the MBE can be freely modified during subroutine processing In interrupt processing the MBE is automatically saved or restored and when interrupt processing is started the contents of the MBE can be specified for the interrupt processing by setting the interrupt vector table This speeds up interrupt processing The setting of the MBS can be modified for subroutine processing or interrupt processing by saving or restoring the MBS with the PUSH or POP instruction The MBE is set using the SET1 or CLR1 instruction The MBS is set using the SEL instruction Example 1 The MBE is cleared and a fixed memory bank is used CLR1 MBE MBE lt 0 Example 2 Memory bank 1 is selected SET1 MBE MBE lt 1 SEL MB1 MBS lt 1 uPD75518 User s Manual 3 3 Chapter 3 Data Memory Operations and Memory 3 1 2 Data Memory Addressing Modes With the 75X architecture of the uPD75518 seven addressing modes summarized in Figure 3 2 and Table 3 1 are available to address data memory space efficiently for each bit length of data to be processed These addressing modes enable more efficient programming Figure 3 2 Data Memory Organization and Add
143. KO Address 1 SBO SB1 Slave CPU 8 1 SCKO Address 2 SBO SB1 Slave IC SCKO Address N Caution To switch between the master and slave a pull up resistor is required also for the serial clock line because SCKO input output switching is performed between the master and slave asynchronously uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 1 SBI functions uPD75518 User s Manual Conventional serial methods provide only data transfer functions Therefore many ports and wires are required to identify chip select signals commands and data and to detect busy states when the serial bus is configured with multiple devices Also these processes are too burdensome to be controlled by software The SBI method can configure a serial bus with two signal lines Serial clock SCKO and serial data bus SBO or SB1 For this reason the number of ports on a microcomputer can be reduced and the wiring on a circuit board can be simplified SBI functions are described below a b c Address command data identification function Serial data is classified into three types Address command and data Address based chip select function The master selects a chip for a slave by address transfer Wake up function A slave can easily check address reception for chip select identification with the wake up function This function can be set or released by software When the wake up function is s
144. LLA CALLF A HL 10 35 rp 1 XA 10 35 XA rp 10 35 A n4 10 34 10 34 1 10 34 XA rp 10 34 8 10 34 A n4 10 37 A HL 10 37 rp 1 XA 10 37 XA rp 10 37 CY fmem bit 10 43 CY pmem L 10 43 CY H mem bit 10 43 addr1 10 44 BCDE 10 46 BCXA 10 46 PCDE 10 45 PCXA 10 45 laddr 10 44 10 44 laddr1 10 46 Icaddr 10 47 laddr 10 48 laddr1 10 48 10 48 CLR1 CY 10 41 CLR1 fmem bit 10 42 CLR1 mem bit 10 42 CLR1 pmem L 10 42 CLR1 H mem bit 10 42 D DECS reg 10 40 DECS rp 10 40 DI 10 51 DI 10 51 E El 10 51 EI IExxx 10 51 G GETI taddr 10 54 H HALT 10 53 IN A PORTn 10 51 IN XA PORTn 10 52 INCS mem 10 40 INCS reg 10 39 INCS rp1 10 39 INCS 10 39 uPD75518 User s Manual M MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV1 MOV1 MOV1 MOV1 MOV1 MOV1 MOVT MOVT MOVT MOVT N NOP NOT NOT1 uPD75518 User s Manual A mem 10 26 A reg 10 26 A n4 10 24 A rpa 10 25 10 26 mem XA 10 26 1 10 24 1 14 10 24 rp n8 10 24 1 10 27 10 26 XA rp 10 26 XA HL 10 25 HL A 10 25 HL XA 10 25 CY fmem bit 10 33 CY pmem
145. LT mode by RESET signal Wait jus 21 8 ms 6 0 MHz HALT instruction RESET signal Operating mode Operating mode HALT mode Je lt Oscillation Clock Note A wait time is approx 31 3 ms when operating at 4 19 MHz d Release of the HALT mode by the occurrence of an interrupt HALT instruction Standby release signal SH EEE Operating mode HALT mode Operating mode 3 E Oscillation Clock Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted IME 1 When the STOP mode is released by the occurrence of an interrupt a wait time is determined by the basic interval timer mode register BTM See Table 7 2 A time required for stable oscillation varies with the type of resonator used and the supply voltage at the time of STOP mode release Accordingly a wait time is to be selected according to each application and BTM is to be set before the STOP mode is set In particular because the oscillation settling time of the crystal is longer than that of the ceramic resonator set a longer wait time 7 6 uPD75518 User s Manual Chapter 7 Standby Function Table 7 2 Selection of a Wait Time with BTM When fx 6 0 MHz BTM3 BTM2 1 Wait time Note indicates the value for fy 6 0 MHz 0 0 1 1
146. NCS mem Function mem lt mem 1 Skip if mem 0 mem D7 9 00H FFH Increments the data at the data memory location addressed by the 8 bit immediate data mem If the result of increment produces data that is 0 the immediately following instruction is skipped DECS reg Function reg reg 1 Skip if reg FH Decrements the contents of register reg X A H L D E B C If the result of decrement produces reg FH the immediately following instruction is skipped DECS rp Function lt rp 1 Skip if rp Decrements the contents of register pair rp XA HL DE BC XA HL DE BC If the result of decrement produces rp FFH the immediately following instruction is skipped 10 4 7 Compare Instructions 10 40 SKE reg n4 Function Skip if 4 4 13 0 0 FH Skips the immediately following instruction if the contents of register reg X A H L D E B C match the 4 bit immediate data n4 SKE HL n4 Function Skip if HL 4 n4 13 0 Skips the immediately following instruction if the data at the data memory location addressed by the HL register pair match the 4 bit immediate data n4 SKE A HL Function Skip if A HL Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair uPD75518 User s Manual Chapter 10 Instruction Set SKE XA HL Function
147. NT4 interrupt enable flag 6 5 INTO interrupt request flag 6 5 INT1 interrupt request flag 6 5 INT2 interrupt request flag 6 5 INT4 interrupt request flag 6 5 M Memory bank enable flag 4 17 Memory bank select register 4 18 P Port mode register group A 5 9 Appendix E Hardware Index Port mode register group B 5 9 Port mode register group C 5 9 Port O to port 15 5 1 Processor clock control register 5 24 Program counter 4 1 Program status word 4 14 Pull up resistor specification register group A 5 17 R Register bank enable flag 4 17 Register bank select register 4 18 S SA register 5 155 Serial bus interface control register 5 82 Serial interface interrupt enable flag 6 5 Serial interface interrupt request flag 6 5 Serial interface operation enable disable specification bit 5 80 5 147 Serial operation mode register 0 5 76 Serial operation mode register 1 5 147 Serial transfer end flag 5 149 Shift register 0 5 85 Shift register 1 5 148 Signal from address comparator 5 80 Skip flag 4 16 Slave address register 5 87 Stack bank select register 4 11 Stack pointer 4 11 System clock control register 5 26 T Timer event counter count register 5 48 Timer event counter interrupt enable flag 6 5 Timer event counter interrupt request flag 6 5 Timer event
148. P 4 09 kHz SEL MB15 or CLR1 MBE MOV XA 01001100B MOV TMO XA lt 4CH Example 2 The timer is restarted according to the setting of the timer mode register SEL MB15 or CLR1 MBE SET1 TMO 3 TMO bit3 lt 1 Chapter 5 Peripheral Hardware Functions Figure 5 29 Format of the Timer Event Counter Mode Register Address Symbol 7 6 5 4 3 2 1 0 FAOH 05 04 TMO3 02 TMO Operation mode Count operation Halts retains the contents of counting Count operation Timer start specification bit When 1 is written to this bit the counter and the IRQTO flag are cleared Count operation starts if bit 2 has been set to 1 Count pulse CP select bit Frequency when fx 6 0 MHz 06 Count pulse CP Temwmweme _____ ESEA fx 2 5 86 kHz 28 23 4 kHz te fx 2 93 8 kHz fx 2 375 kHz Other setting Not to be set Frequency when fx 4 19 MHz 05 04 Count pulse CP EARRA TIO input rising edge EJES TIO input falling edge 219 4 09 kHz 29 16 4 kHz Other setting Not to be set 5 50 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 5 4 Timer Event Counter Output Enable Flag TOEO The t imer event counter output enable flag TOEO enables or disables output of the time out flip
149. P 3 lt PCz 4 SP 4 lt PC3 9 5 5 lt 0 14 PC13 12 SP 6 lt 1 8 PC44 lt 0 1 0 lt addr SP lt SP 6 addr 0000H 3F7FH CALLA addr1 Function 5 2 lt x x MBE RBE SP 3 lt PC7 4 SP 4 lt PC3 9 6 lt 0 14 1 PC42 5 6 lt 11 14 0 lt SP lt SP 6 Saves the contents of the program counter return address MBE and RBE to the data memory location stack addressed by the stack pointer SP then branches to the location addressed by the 14 bit immediate data addr after decrementing the stack pointer CALLF faddr Function SP 2 lt x x MBE RBE SP 3 lt PCz 4 SP 4 lt PCs 5 5 lt 0 14 PC13 12 SP 6 lt PC11 8 SP SP 6 PC14 9 lt 0000 faddr faddr 0000H 07FFH Saves the contents of the program counter PC Return address MBE and RBE to the data memory location stack addressed by the stack pointer then branches to the location addressed by the 11 bit immediate data faddr after decrementing the stack pointer Only the address range 0000H 07FFH 0 2047 can be called uPD75518 User s Manual Chapter 10 Instruction Set TCALL addr Function Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace a 3 byte CALL addr instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed in
150. PD75518 User s Manual The MOV XCH and SKE instructions as well as the IN and OUT instructions can be used for ports 4 5 6 and 7 that allow 8 bit manipulation As with 4 bit manipulation memory bank 15 must be selected in advance Example The data contained in the BC register pair is output on the output port specified by 8 bit data applied to ports 4 and 5 SET1 SEL IN MOV MOV MOV MBE MB15 XA PORT4 XA lt ports 5 4 HL XA HL lt XA BC XA lt BC HL XA Port L lt XA Chapter 5 Peripheral Hardware Functions Table 5 2 1 0 Pin Manipulation Instructions PORT 0 1 2 3 4 5 6 7 8 10 11 12 138 14 15 A PORTn Note 1 XA PORTn Note 1 PORTn A Note 1 PORTn XA Note 1 PORTn bit PORTn L Note 2 PORTn bit PORTn L Note 2 PORTn bit PORTn L Note 2 PORTn bit PORTn L Note 2 CY PORTn bit CY PORTn QL Note 2 PORTn bit CY PORTn L CY Note 2 CY PORTn bit CY PORTn QL Note 2 CY PORTn bit CY PORTn QL Note 2 CY PORTn bit CY PORTn QL Note 2 Note 1 MBE 0 or MBE 1 MBS 15 must be set before execution Note 2 The low order two bits of an address and bit address are indirectly specified using the L register uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 1 4 Digital Port Operation When a data memory manipulation instruction is executed for a digital I O port
151. Program processing Hardware operation Transfer line SCKO pin SBO pin Slave device processing receiver Program processing Hardware operation Interrupt handling preparation for next serial transfer Serial transmission Generate mE Stp IRQCSIO dr eu ACKD SCKO SEN ee x ACK BUSY READY n 4 1 5 1 0 6 4 suonounJ 5 jenuew 51955 8rcc adr 551 56 Master device processing receiver Program processing Hardware operation Transfer line SCKO pin SBO pin BUSY READY Slave device processing transmitter Program processing Hardware operation Stop SCKO Serial reception ie een Clear Serial Bye ena 5 Output Clear BUSY erial transmission IRQCSIO ACKDIBUsY BUS 1 5 84ed 12 96 ainbig 1 01 suonounJ 4 5 Chapter 5 Peripheral Hardware Functions 10 Transfer start Serial transfer is started by writing transfer data in shift register 0 5100 provided that the following two conditions are satisfied The serial interface operation enable disable bit CSIEO is set
152. R Condition for being cleared 0 Condition for being set ACKD 1 1 The transfer operation is started The acknowledge signal ACK is detected in 2 The RESET signal is entered phase with the rising edge of SCKO Busy enable bit R W BSYE 0 1 The busy signal is automatically disabled 2 Busy signal output is stopped in phase with the falling edge of SCKO immediately after clear instruction execution 1 The busy signal is output after the acknowledge signal in phase with the falling edge of SCKO 5 84 uPD75518 User s Manual Example 1 A command signal is output SEL SET1 MB15 CMDT Chapter 5 Peripheral Hardware Functions or CLR1 MBE Example 2 RELD and CMDD are tested to identify the types of received data and the types of processing accordingly By setting WUP 1 this interrupt routine is processed only when an address match is found SEL SKF BR SKT BR CMD DATA ADRS 3 Shift register 0 SIOO MB15 RELD IADRS CMDD IDATA or CLR1 MBE RELD test CMDD test Command analysis Data processing Address decode Figure 5 43 shows the configuration of peripheral hardware of shift register 0 SIOO is an 8 bit register which performs parallel serial conversion and serial transfer shift operation in phase with the serial clock Serial transfer is started by writing data to SIOO In transmission data written to SIOO i
153. SIO start address high order 6 bits instruction BRA laddr instruction NTCSIO start address low order 8 bits Branch address 000AH NTTO start address high order 6 bits specified in CALLA start address low order 8 bits instruction 000CH NTTPG start address high order 6 bits Branch Relative INTTPG start address low order 8 bits address branchaddress specified in specified in BR laddr addr instruction instruction 715 to 1 Branch 2 to 16 address specified in CALL addr instruction GETI instruction reference table Branch call address specified in GETI Vee EE insturction Branch address specified in BRCB instruction i eo a ce AUI Ed t 2000H Branch address specified in 2FFFH BRCB instruction oso reb Branch address specified in BRCB caddr instruction SERRE room am uote M RI cel Ae aito Ae Y Y 4000H A Branch address specified in BRCB caddr instruction AREER dl 5000H Branch address specified in p BRCB caddr instruction 5F7FH Y Y Caution The start address of an interrupt vector shown in Figure 4 2 consists of 14 bits So the start address must be set within a 16K byte space 0000H to
154. Slave CPU SBO or SB1 SCKO Slave IC SBO or SB1 SCKO Address 1 Address 2 Address N 5 136 uPD75518 User s Manual uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions b Explanation of commands Types of commands This example uses the following commands 1 READ command Transfers data from slave to master 2 WRITE command Transfers data from master to slave 3 END command Informs slave of WRITE command completion 4 STOP command Informs slave of WRITE command interruption b STATUS command Reads slave status 6 RESET command Sets currently selected slave as non selected slave 7 CHGMST command Passes master authority to slave lt Protocol gt The following protocol is used for communication between the master and slaves lt 1 gt lt 2 gt lt 3 gt The address of a slave with which the master intends to communicate is transmitted to select the slave chip select This starts communication The slave that has received the address returns ACK to engage in communication with the master The state of the slave is changed from the non selected state to selected state Commands and data are transferred between the master and the slave selected in lt 1 gt Command and data are transferred between the master and the selected slave on a one to one basis so the other slaves must be placed in the non selected state
155. TIO input as many count pulses as corresponding to the time required to execute the instruction are cut When an internal clock is used for the count pulse signal this problem does not occur because of synchronization with the instruction Accordingly in an attempt to read the contents of the count register with a count pulse signal applied to TIO the signal must have a pulse wide enough to avoid incorrect counting even if count pulses are cut That is the contents of the count register are held by a read instruction for one machine cycle so that a signal applied to the TIO pin must have a pulse wider than that External clock TIO Count pulse CP Read instruction A change in a count A count pulse is canceled pulse is placed on hold by the instruction by the instruction uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 4 Notes on changing the count pulse When the count pulse is changed by rewriting the contents of the timer mode register this takes effect immediately after the rewrite instruction is executed Re set instruction Re set instruction Clock A specified Clock A specified We 21 Count pulse A combination of clocks used for changing count pulse signals can generate a spike lt 1 gt or lt 2 gt count pulse as shown in the figure below In this case an incorrect count operation may occur or the contents of the cou
156. The vector table specified by VENTn n 1 to 6 is located at address 2n Example Vector tables are set for INTBT INT4 and INTTO VENT1 MBE 0 RBE 0 GOTOBT 5 MBE 0 1 GOTOTO 6 4 uPD75518 User s Manual 6 3 Various 1 uPD75518 User s Manual Chapter6 Interrupt Function Devices of the Interrupt Control Circuit Interrupt request flags and interrupt enable flags The following nine interrupt request flags IRQxxx corresponding to the interrupt sources seven actual interrupts and two test interrupts are provided INTO interrupt request flag IRQO Serial interface interrupt request flag IRQCSIO interrupt request flag IRQ1 Timer event counter interrupt request flag IRQTO INT2 interrupt request IRQ2 Timer pulse generator interrupt request flag IRQTPG INT4 interrupt request flag IRQ4 Watch timer interrupt request flag IRQW BT interrupt request flag IRQBT An interrupt request flag is set to 1 by an interrupt request and is automatically cleared to 0 when interrupt processing is performed However IRQBT and IRQ4 are cleared in a different way because these flags share a vector address See Section 6 6 The following nine interrupt enable flags IExxx corresponding to the interrupt request flags are provided INTO interrupt enable flag IEO Serial interface interrupt enable flag IECSIO INT1 interrupt enable flag IE1 Timer event counter interrupt enable fla
157. Three wire Serial 1 Mode SCK1 511 SO1 EOT p 1 2 3 4 5 6 7 8 Eo 1 1 Completion of transfer Transfer is started in phase with falling edge of SCK1 Execution of instruction that writes data to SIO1 Transfer start request uPD75518 User s Manual 5 149 Chapter 5 Peripheral Hardware Functions Table 5 15 Serial Clock Selection and Application Mode register Serial clock Timing for shift register R W and Application CSIMO CSIMO Source Masking of start of serial transfer 1 0 serial clock 0 0 External Automatically 1 In the operation halt mode Slave CPU SCK1 masked when CSIEO 0 0 1 TOUT 8 bit data lt 2 gt When the serial clock is masked flip flop transfer is after 8 bit transfer 1 0 fx 24 completed 3 When SCK1 is high Middle speed serial transfer 1 1 fx 23 High speed serial transfer An 8 bit transfer instruction is used to write to or read from shift register 1 The transfer starts with the MSB Example To transfer the RAM data specified by the HL register pair to SIO1 load the SIO1 data to the accumulator and start serial transfer MOV XA HL Fetch transmit data from RAM SEL MB15 orCLR1 MBE XCH XA SIO1 Exchange transmit data and receive data and start transfer 5 150 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 8 6 Application of the Serial Interface Channel 1 This section describes how to u
158. To be left open To be connected to Vss To be connected to Vss or Vpp To be left open To be connected to Vss uPD75518 User s Manual Chapter 2 Pin Functions Table 2 3 Recommended Connection of Unused Pins 2 2 Pin Recommended connection IC To be connected to Vss keeping the wiring as short as possible V pp Note To be connected to Vpp keeping the wiring as short as possible Note The pins indicated in parentheses are provided only for the wPD75P518 2 5 Selection of a Mask Option The following mask options are provided for pins For the uPD75P518 however pull x up or pull down resistors are not specified by the mask option The following pins of the uPD75P518 are always open 1 Specification of built in pull up and pull down resistors Table 2 4 Selection of Pull up and Pull down Resistors Pin Mask option P40 P43 lt 1 gt Pull up resistors provided lt 2 gt No pull up resistor provided P50 P53 Can be specified bit by bit Can be specified bit by bit P120 P123 P130 P133 P140 P143 P90 P93 lt gt Pull down resistors provided lt 2 gt No pull down resistor provided Can be specified bit by bit Can be specified bit by bit 2 Specification of built in feedback resistors for subsystem clock oscillation Table 2 5 Selection of Feedback Resistors Pin Mask option XT1 XT2 lt 1 gt Feedback resistors provided lt 2 gt No feedback resistors provided when a subsystem clock
159. USER S MANUAL NEC uPD75518 4 BIT SINGLE CHIP MICROCOMPUTER 75517 75518 uPD75P518 Document No IEU 1305E O D No IEU 743E Date Published January 1995 P NEC Corporation 1990 Printed in Japan Cautions on CMOS Devices Countermeasures against static electricity for all MOSs Caution When handling MOS devices take care so that they are not electrostatically charged Strong static electricity may cause dielectric breakdown gates Whentransporting or storing MOS devices use conductive trays magazine cases shock absorbers or metal cases that NEC uses for packaging andshipping Besureto ground MOS devices during assembling DonotallowMOS devices standon plastic plates or do nottouch pins Also handle boards on which MOS devices are mountedinthe same way 0 CMOS specific handling of unused input pins Caution Hold CMOS devices ata fixed input level Unlikebipolaror NMOS devices ifa CMOS deviceisoperated with no input anintermediate level input may be caused by noise This allows currentto flow in the CMOS device resulting ina malfunction Useapull upor pull down resistorto holdafixed inputlevel Since unused pins mayfunctionasoutput pinsatunexpectedtimes each unused pin should beseparately connectedtothe bo or GND pinthrough aresistor Ifhandling of unused pins is documented followthe instructions inthe document Statuses of all MOS devices at initialization Caution Theinitial
160. USY Signal from address comparator R COl Note Condition for being cleared COI 0 When the data in the slave address When the data in the register SVA does not match the data in the shift register register Condition for being set COI 1 register SVA matches the data in the shift slave address Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may result during transfer COI data written by an 8 bit manipulation instruction is ignored Serial interface operation enable disable specification bit W Shift register Serial clock IRQCSIO flag 500 5 0 SIO SB1 pins operation counter CSIEO 0 Shift operation Cleared Held Used only for port 0 disabled 1 Shift operation Count opera Can be set Used in each mode enabled tion as well as for port 0 Remarks 1 Each mode can be selected using CSIEO CSIM03 and CSIMO2 CSIEO CSIMO3 CSIMO2 Operation mode 0 Operation mode 1 0 Three wire serial mode 1 1 0 SBI mode 1 1 1 Two wire serial 1 mode 2 x Don t care 5 80 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Remarks 3 The P01 SCKO pin assumes any of the following states according to the state of CSIEO CSIMO1 and CSIMOO CSIEO CSIMO1 CSIMOO 01 5 pin state 0 0 0 Input port 0 0 1 High level output 0 1 0 0 1 1 1 0 0 High impeda
161. addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A m 10 1 5 Skip Instructions and the Number of Machine Cycles Required for a Skip The instruction set of the uPD75518 is designed to organize a program by testing a condition with the skip function When a skip instruction satisfies the skip condition the immediately following instruction is skipped to execute the instruction immediately after the skipped instruction A skip requires the following number of machine cycles a When the instruction to be skipped immediately following the skip instruc tion is a 3 byte instruction that is the BR addr or CALL adadr instruction 2 machine cycles b When the instruction to be skipped immediately following the skip instruc tion is an instruction other than the instructions described in a above 1 machine cycle uPD75518 User s Manual 10 7 Chapter 10 Instruction Set 10 2 Instruction Set and Operation 1 Operand identifier and description 10 8 The operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction Refer toRA75X Assembler Package User s Manual Language EEU 1343 for detailed information When there are multiple descriptions for an identifier one item is to be selected The uppercase letters and and signs are keywords which must
162. addresses 30H 3FH SEL MBO MOV D 2 MOV _HL 30H LOOP A QHL A lt gt 3 A DL lt gt 2x A lt gt 3x BR LOOP XCH XA HL Function A lt gt HL X lt gt HL 1 Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair and exchanges the contents of the X register with the data at the next memory address However if the contents of the L register are odd numbered an address with the low order bit ignored is specified uPD75518 User s Manual 10 27 Chapter 10 10 28 Instruction Set XCH A mem Function lt gt mem mem 07 0 00H FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem XCH XA mem Function A lt gt mem X lt gt mem 1 mem 07 0 00H FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem and exchanges the contents of the X register 1 with the data at the next memory address An even address can be specified with mem XCH A reg1 Function lt gt reg Exchanges the contents of the A register with register reg1 X H L D E B C XCH XA rp Function XA lt gt rp Exchanges the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC
163. after conversion The following combination of instructions adds the contents of an accumulator to data in memory HL then converts the result of the addition to number system m ADDS A 16 m ADDC A HL A CY lt A HL CY ADDS A m An overflow is set in the carry flag If the execution of the instruction ADDC A HL generates a carry the next instruction ADDS A m is skipped If no carry is generated ADDS A m is executed In this case the skip function of this instruction ADDS A m is disabled so that even if this addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A m Example accumulator is added to memory data in decimal ADDS A 6 ADDC A HL A CY lt A HL CY ADDS A 10 b Number system conversion for subtraction Let m be a desired number system after conversion The following combination of instructions subtracts data in memory HL from the contents of an accumu lator then converts the result of the subtraction to number system m SUBC A HL ADDS A m An underflow is set in the carry flag 10 6 uPD75518 User s Manual Chapter 10 Instruction Set If the execution of the instruction SUBC A HL generates no borrow the next instruction ADDS A m is skipped If a borrow is generated the instruction ADDS A m is executed In this case the skip function of this instruction ADDS A m is disabled so that even if this
164. ag bit 3 at address 3FH in data memory is set in bit 2 of port 3 FLAG EQU 3FH 3 SEL MBO MOV H FLAG SHR 6 lt high order 4 bits of FLAG MOV1 CY lt FLAG MOV1 PORT3 2 CY P32 lt CY uPD75518 User s Manual 10 33 Chapter 10 Instruction Set 10 4 4 Arithmetic Logical Instructions ADDS A n4 Function A A n4 Skip if carry n4 13 0 0 FH Adds the 4 bit immediate data n4 to the contents of the A register in binary then skips the next instruction if the addition generates a carry The carry flag is not affected This instruction when combined with the ADDC A HL or SUBC A HL instruction functions as a number system conversion instruction See Section 10 1 4 ADDS XA 18 Function XA lt XA n8 Skip if carry n8 17 0 00H FFH Adds the 8 bit immediate data n8 to the contents of the XA register pair in binary then skips the next instruction if the addition generates a carry The carry flag is not affected ADDS A HL Function A A HL Skip if carry Adds the data at the data memory location addressed by the HL register pair to the contents of the A register in binary then skips the next instruction if the addition generates a carry The carry flag is not affected ADDS XA rp Function XA lt XA rp Skip if carry Adds the contents of register pair rp XA HL DE BC XA HL DE BC to the contents of the XA register pair in binary then skips the n
165. ags like other interrupt sources However vectored interrupts are not issued uPD75518 User s Manual 6 3 Chapter 6 Interrupt Function Figure 6 2 Interrupt Vector Table Address 0002H INTBT INT4 start address high order 6 bits INTBT INT4 start address low order 8 bits 0004H INTO start address high order 6 bits INTO start address low order 8 bits 0006H INT1 start address high order 6 bits INT1 start address low order 8 bits 0008H INTCSIO start address high order 6 bits INTCSIO start address low order 8 bits 000AH INTTO start address high order 6 bits INTTO start address low order 8 bits 000CH INTTPG start address high order 6 bits INTTPG start address low order 8 bits The column of interrupt priority in Table 6 1 indicates a priority assigned when multiple interrupt requests occur concurrently or are held A vector table contains interrupt processing start addresses and MBE and RBE setting values during interrupt processing An assembler pseudo instruction VENTn is used to set a vector table Example A vector table is set for INTBT INT4 T T lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 1 gt Vector table at address 0002 lt 2 gt MBE setting value in interrupt service routine lt 3 gt RBE setting value in interrupt service routine lt 4 gt Symbol for indicating an interrupt service routine start address Caution
166. al Chapter 5 Peripheral Hardware Functions 5 Transfer start Serial transfer starts by writing transfer data into shift register 0 5100 provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIEO is set to 1 The internal serial clock is not operating after 8 bit serial transfer or SCKO is high Cautions 1 Setting CSIEO to 1 after writing data to the shift register does not start transfer 2 When data is received the N ch transistor must be turned off so FFH must be written to SIOO beforehand When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSIO 6 Error detection In the two wire serial mode the state of serial bus 580 581 being used for communication is loaded into the shift register SIOO of the transmitting device So a transmission error can be detected by the methods described below a Comparing SIOO data before start of transmission with SIOO data after start of transmission With this method the occurrence of a transmission error is assumed when two 5100 values disagree with each other b Using the slave address register SVA Transmit data is set in SIOO and SVA as well before the data is transmitted On completion of transmission the COI bit match signal from the address compa rator of serial operation mode register 0 CSIMO is tested If
167. al transfer is not performed which is set by setting 0 in CSIE1 This mode reduces power consumption Shift register 1 does not perform shift operation in this mode so the shift register can be used as a normal 8 bit register The RESET signal places the device in the operation halt mode The P82 SO1 and P83 51 pins function as input only ports The P81 SCK1 pin can be used as an input port by setting serial operation mode register 1 5 148 uPD75518 User s Manual 5 8 5 Chapter 5 Peripheral Hardware Functions Three Wire Serial I O Mode Operations The three wire serial mode is compatible in other modes used in the 75X series uPD7500 series and 78K series This mode is set by setting CSIE1 to 1 Communication is performed using three lines Serial clock SCK1 serial output SO1 and serial input 511 The three wire serial I O mode transfers data in eight bit units Bits are transferred serially in phase with the serial clock Shift register 1 is triggered on the falling edge of the serial clock SCK1 Transmit data is latched on the 501 latch and is output on the 501 pin Receive data applied to the 51 pin is latched in the shift register 1 on the rising edge of SCK1 When eight bits have been transferred operation of shift register 1 automatically terminates setting the serial transfer end flag EOT Setting the serial transfer end flag EOT cannot release the standby function Figure 5 84 Timing of the
168. ansfers the contents of the X register to the next memory address An even address can be specified with mem MOV A reg Function A lt reg Transfers the contents of register reg X A H L D E B C to the A register MOV XA rp Function XA lt rp Transfers the contents of register pair rp XA HL DE BC XA HL DE BC to the XA register pair Example The contents of the XA register pair are transferred to the XA register pair MOV XA XA uPD75518 User s Manual Chapter 10 Instruction Set MOV reg1 A Function regi A Transfers the contents of the A register to register reg1 X H L D E B C MOV 1 Function XA Transfers the contents of the XA register pair to register pair 1 HL DE BC XA HL DE BC XCH A rpa Function A lt gt rpa When rpa HL Skip if L 0 When HL Skip FH Exchanges the contents of the A register with the data at the data memory location addressed by register pair HL HL HL DE DL When HL automatic increment or HL automatic decrement is specified as rpa automatically increments or decrements the contents of the L register by one after the data exchange and continues this operation until the contents are set to 0 for HL or FH for Then skips the immediately following instruction Example The data at addresses 20H 2FH are exchanged with the data at
169. apter 5 Peripheral Hardware Functions 4 Slave address register SVA uPD75518 User s Manual The slave address register SVA is an 8 bit register for a slave to set its slave address number assigned to it SVA is manipulated using an 8 bit manipulation instruction SVA allows only write operation When the RESET signal is entered the value of SVA is undefined However the value of SVA is preserved when the RESET signal is entered in the standby mode SVA has the following two functions a b Slave address detection in the SBI mode SVA is used when the uPD75518 is connected as a slave device to the serial bus The master outputs a slave address to the connected slaves to select a particular slave Two data values a slave address output from the master and the value of SVA are compared with each other by the address comparator If a match is found the slave is selected At this time bit 6 COI of serial operation mode register 0 CSIMO is set to 1 If a match with received address data is not found the bus release detection flag RELD is cleared to 0 When WUP 1 wake up state detection IRQCSIO is set only when a match is found With this interrupt request the uPD75518 can be informed of a communication request transmitted from the master Error detection In the two wire serial I O mode or SBI mode SVA detects an error in either of the following cases When addresses commands or data is transferr
170. are mapped to these data memory areas can freely perform bit manipulations in the direct addressing mode at any time regardless of MBS and MBE setting Example 1 Example 2 Example 3 Value input to 2 is inverted and the result is output on P33 MOV1 CY PORTO 2 NOT1 CY MOV1 PORT3 3 CY The timer 0 interrupt request flag IRQTO is tested The request flag if set is cleared and P63 is reset SKTCLR IRQTO IRQTO 1 BR NO NO CLR1 PORT6 3 YES If both P30 and P41 are set to 1 P53 is reset P41 MOV1 PORT3 0 lt P30 AND1 PORT4 1 CYAP41 NOT1 CY CY CY MOV1 PORTS5 8 CY P53 lt CY Chapter 3 Data Memory Operations and Memory b Specific address bit register indirect addressing pmem L In this addressing mode the bits of peripheral hardware I O ports are indirectly specified using a register to allow continuous manipulations This addressing mode can be applied to data memory addresses FCOH to FFFH This range of data memory includes a bit manipulation memory area see Section 5 10 for more effective addressing in this mode as well as I O ports In this addressing mode the high order 10 bits of a 12 bit data memory address is directly specified in the operand and the low order two bits and bit address are indirectly specified using the L register Thus the use ofthe L register enables 16 bits four ports to be continuously manipulated This
171. ation with the most significant bit Figure 5 15 shows the format SCC 3 and SCC 0 are located at the same data memory address but both bits cannot be changed at the same time Accordingly SCC 3 and 5 0 are set using bit manipulation instructions SCC 3 and SCC 0 can be manipulated regardless of MBE setting Main system clock generation can be terminated by setting SCC 3 only when the subsystem clock is used for operation The STOP instruction must be used to terminate main system clock generation A RESET signal clears the SCC to 0 Figure 5 15 Format of the System Clock Control Register Address 3 2 1 0 Symbol FB7H 3 SCCO SCC RSEN Not to be set Subsystem clock Oscillation stopped Cautions 1 A time period of up to 1 fy7 is needed to change the system clock This means that to terminate main system clock generation SCC 3 must be set when the machine cycles indicated in Table 5 1 or more have elapsed after the clock is switched from the main system clock to the subsystem clock 2 When the main system clock is used for operation setting SCC 3 to stop clock generation does not enter the normal STOP mode 3 When SCC is set to 1 the X1 input pin is connected to Vss ground electric potential to prevent leakage in the crystal oscillator When an external clock is used as the main system clock never set SCC 3 to 1 5 26 uPD75518 User s Manual Chapter 5 Peripheral
172. ator uPD75518 User s Manual 5 27 Chapter 5 Peripheral Hardware Functions Figure 5 17 External Circuit for the Subsystem Clock Oscillator a Crystal oscillation b External clock uPD75518 uPD75518 D c 2102 V External E clock o xr E T XT1 XT2 Open XT2 Crystal Caution When the main system clock or subsystem clock oscillator is used conform to the following guidelines when wiring at the shaded portions of Figures 5 16 and 5 17 to eliminate the influence of the stray capacitance around the wiring The wiring must be as short as possible Other signal lines must not run in these areas Any line carrying a high pulsating current must be kept away as far as possible The grounding point of the capacitor of the oscillator must have the same potential as that of Vss It must not be grounded to a grounding pattern carrying a high current No signal must be taken directly from the resonator Take special care of the subsystem clock oscillator because it has low amplification to minimize current consumption Figure 5 18 gives examples of oscillator connections which should be avoided 5 28 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 18 Examples of Oscillator Connections which should be Avoided 1 2 a The wiring is too long pPD75518 c A high pulsating current is too c
173. be addressed In the MBE 1 mode MB MBS and specifiable data memory space can be expanded to the entire space This addressing mode can be applied to the MOV XCH INCS IN and OUT instructions Caution Less efficient program processing results if data associated with an I O port is stored in the static RAM area of bank 1 as in Example 1 The modification of the MBS as contained in Example 2 becomes unnecessary in the programming if data associated with an I O port is stored at addresses 000H to 07FH of bank 0 Example 1 The data contained in BUFF is output on port 8 BUFF EQU 11AH SET1 MBE SEL MB1 MOV A BUFF SEL 15 OUT PORT8 A BUFF located at address 11AH MBE 1 MBS 1 A BUFF MBS 15 PORT8 A Example 2 Data on port 4 is entered and is saved DATA1 DATA1 EQU CLR1 MBE IN A PORT4 MOV DATA1 A uPD75518 User s Manual DATA located at address MBE lt 0 A PORTA DATA1 A Chapter 3 Data Memory Operations and Memory 3 8 bit direct addressing mem In this addressing mode the operand of an instruction directly specifies any area in the data memory space in units of eight bits The operand can specify an even address The 4 bit data at the address specified in the operand and the 4 bit data at the address incremented by 1 are processed as a pair on an 8 bit basis with the 8 bit accumulator XA register pair
174. ble Serial bus interface 5 7 1 Serial Interface Channel 0 Functions The serial interface channel 0 of the uPD75518 has four modes The functions of the four modes are outlined below 1 Operation halt mode This mode is used when serial transfer is not performed This mode reduces power consumption 2 Three wire serial mode In this mode 8 bit data is transferred through three lines Serial clock SCKO serial output SOO and serial input SIO The three wire serial I O mode allows full duplex transmission so data transfer can be performed at higher speed The user can choose 8 bit data transfer starting with the MSB or LSB so devices starting with either the MSB or LSB can be connected The three wire serial mode enables connections to be made with the 75X series 78K series and many other types of peripheral I O devices uPD75518 User s Manual 5 73 Chapter 5 Peripheral Hardware Functions 3 4 Two wire serial mode In this mode 8 bit data is transferred through two lines Serial clock 5 and serial data bus SBO or SB1 By controlling output levels on the two lines by software communication with multiple devices is enabled The output levels of SCKO and SBO or SB1 can be controlled by software so the user can match an arbitrary transfer format This means that a line that has been required for handshaking to connect multiple lines can be eliminated for more efficient
175. caution concerning the machine cycle has been added to Table 5 5 Figure 5 38 has been modified The descriptions and figure in 4 of Section 5 6 4 have been modified A caution has been added to 4 of Section 5 6 4 The descriptions in 1 of Section 6 3 have been modified The sample programs given in Section 6 6 have been replaced Descriptions relating to the use of a crystal have been added to Section 7 2 A caution has been added to Table 7 2 The timing chart in 1 of Section 7 4 has been modified A caution concerning the switching system clock has been added to 2 of Section 7 4 Table 8 1 has been modified Section 9 5 has been added The version of MS DOS has been upgraded to 5 00A in Appendix A Therefore a caution concerning the upgrade has been added Appendix C has been added Major changes in this revision are indicated by stars in the margins MEMO Preface Readers This manual is intended for engineers who want to learn the capabilities of the uPD75517 uPD75518 and uPD75P518 to develop application systems based on them Purpose The purpose of this manual is to help users understand the hardware capabilities of the uPD75517 uPD75518 and uPD75P518 Guidance Readers of this manual should have general knowledge of the electronics logical circuit and microcomputer fields To understand the overall functions of the 1 PD75517 uPD75518 and uPD75P518 Read through all chapters
176. cessing the All 0 1 normal program 0 1 Status 1 Is processing a Only high order 1 0 low or high order interrupts interrupt 1 0 Status 2 Is processing a No high order interrupt 1 1 This status cannot be used This status is disabled uPD75518 User s Manual 6 15 Chapter 6 Interrupt Function 6 4 Interrupt Sequence When an interrupt occurs it is processed using the procedure shown Figure 6 8 Interrupt Processing Sequence in Figure 6 8 Interrupt INTxxx occurrence This sequence varies having been executed when IRQn was set See Section 6 7 2 machine cycles according to the instruction Start processing the interrupt service program IRQxxx setting Hold until is set Corresponding VRQn occurrence o Yes lt n Hold until IME is set Hold until process ing being executed is finished Is VRQn high order interrupt No Note 1 No Note 1 IST1 0 00 or 01 IST1 0 00 Yes If two or more VRQns occur select one VRQn according to Table 6 1 Selected Remaining VRQn VRQns Save contents of PC and PSW in stack memory and set data N te 2 in vector table corresponding to activated VRQn to PC RBE and MBE Change contents of ISTO and IST1 from 00 to 01 or from 01 to 10 Reset accepted IRQxxx pon Section 6 6 when those EID Sources s
177. clear reactor control systems and life support systems If customers intend to use NEC devices for above applications or they intend to use Standard quality grade NEC devices for applications not intended by NEC please contact our sales people in advance Application examples recommended by NEC Corporation Standard Computer Office equipment Communication equipment Test and Measurement equipment Machine tools Industrial robots Audio and Visual equipment Other consumer products etc Special Automotive and Transportation equipment Traffic control systems Antidisaster systems Anticrime systems etc M7 92 6 Major Changes Page Preface Preface P 1 1 and P 1 8 P 1 3 P 1 5 P 2 9 and P 2 10 P 2 12 P 2 17 5 5 5 33 5 69 5 71 6 6 6 20 7 6 7 7 7 9 7 12 P 8 3 P 9 7 P A 2 P C 1 Description Documents related to the development tools and other documents have been added A caution concerning the reliability of the uPD75P518K has been added Descriptions of the stack bank selection register SBS and stack operation have been added to Section 1 1 Section 1 3 has been added Descriptions of the release of the STOP and HALT modes have been added to Sections 2 2 10 and 2 2 11 The descriptions in Section 2 2 20 have been modified The recommended connections for IC and Vpp listed in Table 2 3 have been modified Figures 5 3 and 5 4 have been modified A
178. counter mode register 5 49 Timer event counter modulo register 5 48 Timer event counter output enable flag 5 51 Timer pulse generator interrupt enable flag 6 5 Timer pulse generator interrupt request flag 6 5 Timer pulse generator modulo register 5 62 W Wake up function specification bit 5 80 Watch mode register 5 45 Watch timer interrupt enable flag 6 5 Watch timer interrupt request flag 6 5 uPD75518 User s Manual Appendix E Hardware Index E 2 Hardware Index Alphabetical Order with Respect to the Hardware Symbol A ACKD 5 84 ACKE 5 84 ACKT 5 84 ADM 5 153 B BSBO BSB3 5 162 BSYE 5 84 BT 5 38 BTM 5 39 C CLOM 5 36 CMDD 5 83 CMDT 5 83 COI 5 80 CSIEO 5 80 CSIE1 5 147 CSIMO 5 78 CSIM1 5 147 4 15 EOC 5 154 EOT 5 149 IEO 6 5 IE1 6 5 IE2 6 5 uPD75518 User s Manual IE4 6 5 IEBT 6 5 IECSIO 6 5 IETO 6 5 IETPG 6 5 IEW 6 5 IMO IM1 2 6 10 IPS 6 13 IRQO 6 5 IRQ1 6 5 2 6 5 IRQ4 6 5 IRQBT 6 5 IRQCSIO 6 5 IRQTO 6 5 IRQTPG 6 5 IRQW 6 5 ISTO IST1 4 16 6 15 M MBE 4 17 MBS 4 18 MODH MODL 5 62 P 4 1 5 24 5 9 PMGB 5 9 PMGC 5 9 POGA 5 17 Appendix E Hardware Index PORTO PORT15
179. ction flag R Condition for being cleared 0 Condition for being set ACKD 1 1 The transfer operation is started The acknowledge signal ACK is detected in 2 The RESET signal is entered phase with the rising edge of SCKO uPD75518 User s Manual 5 119 Chapter 5 Peripheral Hardware Functions Busy enable bit R W BSYE 0 1 The busy signal is automatically disabled lt 2 gt Busy signal output is stopped in phase with the falling edge of SCKO immediately after clear instruction execution 1 The busy signal is output after the acknowledge signal in phase with the falling edge of 4 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register 0 CSIMO The serial clock can be selected out of the following four clocks Table 5 13 Serial Clock Selection and Application In the SBI Mode Mode register Serial clock Timing for shift register R W and Application CSIMO Source Masking of start of serial transfer 1 0 serial clock 0 0 External Automatically 1 In the operation halt mode Slave CPU SCKO masked when CSIEO 0 8 bit data lt 2 gt When the serial clock is masked 0 1 TOUT transfer is after 8 bit transfer Arbitrary speed flip flop completed 3 When SCKO is high serial transfer 1 0 fy 24 Middle speed serial transfer 1 1 fx 23 High speed serial transfer When the internal system
180. d 6 0 MHz are indicated in parentheses Serial interface operation mode selection bit W CSIM04 CSIMO3 CSIMO2 Shift register sequence 00 pin function 10 pin function 0 0 51007 lt gt XA SO0 P02 510 Transfer starting with MSB CMOS output Input 1 100 7 lt gt XA Transfer starting with LSB Remark x Don t care uPD75518 User s Manual 5 91 Chapter 5 Peripheral Hardware Functions Wake up function specification bit W WUP 0 Sets IRQCSIO each time serial transfer is completed Signal from address comparator R Condition for being cleared 0 Condition for being set COI 1 When the slave address register SVA When the slave address register SVA does not match the data of the shift register matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer data written by an 8 bit manipulation instruction is ignored Serial interface operation enable disable specification bit W Shift register operation Serial clock counter IRQCSIO flag 500 5 0 SIO SB1 pin CSIEO 1 Shift operation enabled Count operation Can be set Used in each mode as well as for port 0 b Serial bus interface control register SBIC To use the three wire serial mode set SBIC as shown below For details on SBIC se
181. d by changing the order of data bits written to shift register 0 5100 The shift operation order of SIOO is always the same Accordingly the first bit must be switched between the MSB and LSB before writing data to the shift register Chapter 5 Peripheral Hardware Functions 6 Transfer start Serial transfer is started by writing transfer data into shift register 0 SIOO provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIEO is set to 1 Theinternal serial clock is not operating after 8 bit serial transfer or SCKO is high Caution Setting CSIEO after writing data to the shift register does not start transfer When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSIO Example To transfer the RAM data specified with the HL register to SIOO load the 5100 data to the accumulator and start serial transfer MOV XA QHL Fetch transmit data from RAM SEL MB15 CLR1 MBE XA SIOO Exchange transmit data and receive data and start transfer 5 96 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 7 Application of the three wire serial I O mode Example 1 Data is transferred starting with the MSB on a transfer clock of 262 kHz in 4 19 MHz operation Master operation Sample program CLR1 MBE MOV 810000010 MOV CSIMO XA Set transfer
182. data addr1 to the program counter then branches to the location addressed by the program counter A branch can occur to any location in the entire program memory space 10 46 uPD75518 User s Manual Chapter 10 Instruction Set BRCB caddr Function 14 0 lt PC414 13 12 caddr11 0 caddr n000H nFFFH n 13 12 0 7 Branches to the address specified by the program counter whose low order 12 bits 11 have been replaced with the 12 bit immediate data caddr Caution The BRCB caddr instruction usually causes a branch within the block containing the instruction However if the first byte is located at address OFFEH or OFFFH a branch to block 1 instead of block 0 occurs Program memory 7 0 Block 0 OFFEH OFFFH gt b 1000H Block 1 If the BRCB caddr instruction is located at a or b in the figure above a branch to block 1 instead of block 0 occurs TBR addr Function Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace a 3 byte BR addr instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language addr 0000H SFFFH uPD75518 User s Manual 10 47 Chapter 10 Instruction Set 10 4 11 Subroutine Stack Control Instructions 10 48 CALL addr Function 8 2 lt x x MBE RBE S
183. ded Chapter 7 The descriptions of the handling of I O ports have been modified in Applications of the Standby Modes Descriptions of the IE 75001 R have been added Appendix A Sixth Documents related to the development tools and other documents have Preface been added A caution concerning the reliability of the uPD75P518K has been added Preface and Chapter 1 Descriptions of the stack bank selection register SBS and stack Chapter 1 operation have been added to Section 1 1 Section 1 3 has been added Descriptions of the STOP and HALT modes have been added to Chapter 2 Sections 2 2 10 and 2 2 11 The descriptions in Section 2 2 20 have been modified The recommended connections for IC and Vpp listed in Table 2 3 have been modified Figures 5 3 and 5 4 have been modified Chapter 5 A caution concerning the machine cycle has been added to Table 5 5 Figure 5 38 has been modified The descriptions and figure in 4 of Section 5 6 4 have been modified A caution has been added to 4 of Section 5 6 4 The descriptions in 1 of Section 6 3 have been modified Chapter 6 The sample programs given in Section 6 6 have been replaced uPD75518 User s Manual C 1 Appendix C Revision History Edition Major changes Revised chapter Sixth Descriptions relating to the use of a crystal have been added to Section 7 2 Chapter 7 A caution has been added to Table 7 2 The timing chart in 1 of Section 7 4 has b
184. dule is less then 7 8 ms SEL MB15 Initialization MOV A 1101B or CLR1 MBE MOV BTM A Setting and start EI EI IEBT Module 1 Processing completes within 7 8 ms Processing completes Module 2 within 7 8 ms Y Example 3 A wait time of 7 8 ms at 4 19 MHz is set for releasing the STOP mode with an interrupt SEL MB15 MOV A 1101B MOV BTM 1101B STOP Set STOP mode NOP uPD75518 User s Manual uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Example 4 The high level width of pulses applied to the INT4 interrupt pin both edges detected The pulse width is assumed not to exceed the value set in the BT The set value in the BT is 7 8 ms or longer lt INT4 interrupt routine MBE 0 LOOP MOV XA BT First read MOV BC XA Store data MOV XA BT Second read SKE A C BR LOOP MOV A X SKE A B BR LOOP SKT 0 POO 1 BR AA NO MOV XA BC Store data in data memory MOV BUFF XA CLR1 FLAG Data present clear the flag RETI AA MOV HL BUFF MOV A C SUBC A HL INCS L MOV A B SUBC A HL MOV B A MOV XA BC MOV BUFF XA Store data SET1 FLAG Data present set the flag RETI Chapter 5 Peripheral Hardware Functions 5 4 Clock Timer The uPD75518 contains one clock timer which has the following functions a The clock timer sets the test flag IRQW every 0 5 seconds The IRQW can release the standby mode b Eith
185. e 2 in Section 5 7 3 SBIC is manipulated using a bit memory manipulation instruction When the RESET signal is input SBIC is set to 00H In the figure below hatched portions indicate the bits used in the three wire serial mode Address 7 6 5 4 3 2 1 0 Symbol BSYE ACKT RELD CMDT RELT SBIC Bus release trigger bit W FE2H Do not use these bits in the three wire serial mode Command trigger bit W Remark W Write only 5 92 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Bus release trigger bit W RELT Control bit for bus release signal REL trigger output By setting RELT 1 the 500 latch is set to 1 Then the RELT bit automatically cleared to 0 Command trigger bit W CMDT Control bit for command signal CMD trigger output By setting CMDT 1 the 500 latch is cleared Then the CMDT bit is automatically cleared Caution Never use bits other than RELT and CMDT in the three wire serial I O mode 2 Communication operation The three wire serial mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the serial clock SCKO Send data is latched on the 500 latch and is output on the SOO pin Receive data applied to the SIO pin is latched in the shif
186. e area as shown in Figure 4 4 The data memory consists of the following memory banks with each bank made of 256 words x 4 bits Memory banks 0 1 2 and 3 data area Memory bank 15 peripheral hardware area 4 3 1 Data Memory Configuration Figure 4 4 Data Memory Map Data memory Memory bank A General 000H A register area 01FH 020H 0 OFFH y 100H 1 D I BAM Stack 1FFH M 1024 x 4 alee 200H 2 2FFH 300H 3 Y Y 3FFH Y A F80H A Peripheral 15 hardware area Y FFFH uPD75518 User s Manual 4 5 Chapter 4 Internal CPU Functions 1 2 Data area The data area consists of a static RAM and is used for storing data and as stack memory for subroutine and interrupt execution Battery backup enables the memory to hold data for a long time even if the CPU is stopped in the standby mode The data area can be manipulated with memory manipulation instructions The static RAM is mapped to memory banks 0 1 2 and 3 with each made up of 256 x 4 bits Bank 0 is used as a data area but can also be used as a general register area 000H to 01FH Whole locations in memory banks 0 1 2 and 3 OOOH to 3FFH can be used as a stack area The static RAM has a configuration of four bits per address However the memory can be manipulated in 8 bit units using an 8 bit memory manipulation instruction and in bit units using a bit manipulation instruction Note that an ev
187. e contents of the port specified by PORTn n 4 or 6 to the A register then transfers the contents of the next port to the X register Caution Only the number 4 or 6 can be specified as n Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred OUT PORTn A Function PORTn lt Na 2 7 9 14 Transfers the contents of the A register to the output latch of the port specified by PORTn n 2 7 9 14 Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set A number from 2 to 7 or 9 to 14 can be specified as n OUT PORTn XA Function PORTn lt A PORTn 1 Nao 4 6 Transfers the contents of the A register to the output latch of the port specified by PORTn n 4 6 then transfers the contents of the X register to the output latch of the next port Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Only 4 or 6 can be specified as n uPD75518 User s Manual Chapter 10 Instruction Set 10 4 14 CPU Control Instructions HALT Function PCC 2 lt 1 Sets the HALT mode This instruction is used to set bit 2 of the processor clock control register Caution The instruction immediately following a HALT instruction must be a NOP instruction STOP Func
188. e control output is selected by the clock frequency select bit of the clock output mode register Pulse output is enabled or disabled by controlling the clock output enable disable bit by software The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output Figure 5 22 Application to Remote Control Output Bit 3 of CLOM ee Bose aa N PCL pin output uPD75518 User s Manual 5 37 Chapter 5 Peripheral Hardware Functions 5 3 Basic Interval Timer The uPD75518 contains an 8 bit basic interval timer BT which has the following functions a Reference time generation four time intervals b Use as a watchdog timer for detecting program crashes c Selection of a wait time for releasing the standby mode and counting d Reading the count value 5 3 1 Configuration of the Basic Interval Timer Figure 5 23 shows the configuration of the basic interval timer Figure 5 23 Configuration of the Basic Interval Timer From the clock generator Clear signal 5 25 Clear signal 5 27 gt V Basic interval timer BT interrupt RE 9 8 bit frequency divider circuit request flag request 5 2 gt signal 5 2 Wait release signal for standby release Note Internal bus Note Instruction execution 5 38 uPD75518 User s Manual Chapter 5 Peripheral Ha
189. e is set when bit 2 of TMO is set to 0 In this mode count operation is not performed because count pulse CP supply to the count register is stopped 2 Count operation mode This mode is set when bit 2 of TMO is set to 1 In this mode a count pulse signal selected with bits 4 to 6 is supplied to the count register for count operation as shown in Figure 5 28 Timer operation is usually started by the following operations 1 A count value is set in the modulo register TMODO 2 An operation mode count clock and start instruction are set in the mode register TMO An 8 bit data transfer instruction is used to set the modulo register Caution A value other than 0 must be set in the modulo register Example The value 3FH is set in the modulo register of channel 0 SEL MB15 or CLR1 MBE MOV XA 3FH MOV TMODO XA Figure 5 31 Operation in the Count Operation Mode Internal clock INTTO IRQTO set signal Clear signal TOUT flip flop PTOO To serial interface Only for channel 0 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 5 6 Time Setting in the Timer Event Counter Timer set time period is value of the modulo register 1 divided by count pulse frequency selected by the timer mode register n 1 fop 1 resolution T SEC Timer set time seconds fcp Hz Count pulse frequency Hz n Value in the modulo regis
190. e written to SIOO beforehand The N ch open drain output can be turned off at any time during transfer However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off so there is no need to write FFH to SIOO before reception uPD75518 User s Manual 5 127 Chapter 5 Peripheral Hardware Functions 5 128 7 Address match detection method In the SBI mode communication starts when the master selects a particular slave device by outputting an address An address match is detected by hardware The slave address register SVA is available In the wake up state WUP 1 IRQCSIO is set only when the address transmitted by the master and the value held in SVA match Cautions 1 Whether a slave is selected is determined by detecting a match for a slave address received after bus release in the state of RELD 1 An address match is detected usually using an address match interrupt IRQCSIO generated when WUP is set to 1 So detect selection nonselection state by slave address when WUP is set to 1 When determining whether a slave is selected without using an interrupt when WUP is 0 do not use the address match detection method Instead use transfer of commands set in advance in a program 8 Error detection In the SBI mode the state of serial bus SBO or SB1 being used for communication is loaded into the shift register SIOO of the transmitting device So a transmiss
191. ed and no vectored interrupt is activated 1 The interrupt enable flag corresponding to an interrupt request flag controls interrupt enabling disabling uPD75518 User s Manual Chapter 6 Interrupt Function 5 Interrupt status flags The interrupt status flags ISTO and IST1 which are contained in the PSW indicate the status of processing currently executed by the CPU By using the content of these flags the interrupt priority control circuit controls multiple interrupts as indicated in Table 6 3 A 4 bit manipulation instruction or bit manipulation instruction can be used to set and reset ISTO and IST1 so that multiple interrupts are enabled by changing the current status of execution ISTO and IST1 can be manipulated on a single bit basis at any time regardless of MBE setting Before ISTO or IST1 is manipulated the DI instruction must be executed to disable interrupts then the El instruction must be executed to enable interrupts IST1 and ISTO as well as the other PSW bits are saved in the stack memory when an interrupt is accepted and the status of ISTO and IST1 changes to a status one level higher When a RETI instruction is executed the former values of IST1 and ISTO are resumed A RESET signal clears the content of the flag to 0 Table 6 3 Interrupt Processing Statuses of ISTO and IST1 IST1 ISTO Processing CPU operation Interrupts that After acceptance status can be accepted IST1 ISTO 0 0 Status 0 Is pro
192. ed type Table 1 1 Differences between the uPD75P518 uPD75517 and uPD75518 Item uPD75517 uPD75518 uPD75P518 Program memory 24448 x 8 bits 32640 x 8 bits 32640 x 8 bits Masked ROM Masked ROM One time PROM EPROM Data memory 1024 x 4 bits Pull up resistors for ports 4 and 5 Mask option None Pull up resistors for ports 12 to 14 Pull down resistor for port 9 Feedback resistor for subsystem Incorporated clock Pin function Pin 4 Vpp Pins 38 to 41 P33 P30 P33 MD3 P30 MDO Electrical characteristics Operating voltage range Operating temperature range Package Others The current drain and several other specifications are different for each product For details refer to the corresponding items in each data sheet Vpp 2 7 to 6 0 V 40 C to 85 80 pin plastic QFP 14 x 20 mm 80 pin plastic QFP 14 x 20 mm 80 pin ceramic WQFN Since each product has a different circuit scale and mask layout the noise immunity and noise radiation characteristics of each product are different uPD75518 User s Manual Chapter1 General Caution The PROM and masked ROM products have different noise immunity and noise radiation characteristics Do not use ES products for evaluation when considering switching from PROM based products to those using masked ROM upon the transition from preproduction to mass production CS products masked ROM products should be used in this case 1 6 uPD75518 User s Manua
193. ed with the uPD75518 operating as the master When data is transferred with the uPD75518 operating as a slave For details see 6 in Section 5 7 6 and 8 in Section 5 7 7 Chapter 5 Peripheral Hardware Functions 5 7 4 Operation Halt Mode The operation halt mode is used when serial transfer is not performed This mode reduces power consumption The shift register does not perform shift operation in this mode so the shift register can be used as a normal 8 bit register When the RESET signal is entered the operation halt mode is set The 02 500 5 0 pin and PO3 SIO SBI pin function as input only port pins The 1 5 can be used as an input port pin by setting the serial operation mode register Register setting To set the operation halt mode manipulate serial operation mode register 0 CSIMO For details on CSIMO see 1 in Section 5 7 3 CSIMO is manipulated with an 8 bit manipulation instruction Only the CSIEO bit of CSIMO can be independently manipulated CSIMO can also be manipulated using the name of each bit When the RESET signal is entered CSIMO is set to OOH In the figure below hatched portions indicate bits used in the operation halt mode Address 7 6 5 4 3 2 1 0 Symbol poe Serial clock selection bit W Net Serial interface operation mode selection bit W Wake up function specification bit Match signal from address comparator R Serial inter
194. een modified A caution concerning the switching system clock has been added to 2 of Section 7 4 Table 8 1 has been modified Chapter 8 Section 9 5 has been added Chapter 9 The version of MS DOS has been upgraded to 5 00A Therefore Appendix A a caution concerning the upgrade has been added 2 uPD75518 User s Manual Appendix D Instruction Index D 1 Instruction Index By Function Transfer instructions MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH XCH XCH uPD75518 User s Manual A n4 10 24 1 14 10 24 rp n8 10 24 A rpa 10 25 XA HL 10 25 HL A 10 25 HL XA 10 25 A mem 10 26 XA mem 10 26 10 26 mem XA 10 26 A reg 10 26 XA rp 10 26 reg1 A 10 27 rp 1 XA 10 27 A rpa 10 27 XA HL 10 27 A mem 10 28 XA mem 10 28 A reg1 10 28 10 28 Table reference instructions MOVT MOVT MOVT MOVT XA PCDE 10 29 XA PCXA 10 31 XA BCDE 10 32 XA BCXA 10 32 Bit transfer instructions MOV1 MOV1 MOV1 MOV1 MOV1 MOV1 fmem bit 10 33 CY pmem L 10 33 CY H mem bit 10 33 fmem bit CY 10 33 pmem L CY 10 33 H mem bit CY 10 33 Arithmetic logical instructions ADDS ADDS ADDS ADDS ADDS ADDC ADDC ADDC A n4 10 34 XA n8 10 34 10 34 XA rp 10 34 rp 1 XA 10 34
195. egister and clear the interrupt request flag 3 Configuration of the INT2 and KRO to KR7 key interrupt circuits Figure 6 6 shows the configuration of the INT2 and KRO to KR7 circuits IRQ2 is set at one of the following edges selected with the edge detection mode register IM2 a Detection of a rising edge of the INT2 pin input When a rising edge of the INT2 pin input is detected IRQ2 is set b Detection ofa falling edge of one ofthe KRO to KR7 pin inputs key interrupt One of the pins KRO to KR7 is selected to be used for an interrupt input pin with the edge detection mode register IM2 When a falling edge of an input signal applied to the selected pin is detected IRQ2 is set Caution If any of the selected pins has been supplied with a low level signal a falling edge appearing on another pin does not set IRQ2 Figure 6 5 c shows the format of IM2 A 4 bit memory manipulation instruction is used to set IM2 A RESET signal clears all bits to 0 and a rising edge is selected for INT2 uPD75518 User s Manual 6 11 21 9 51955 grcc adri INT2 P12 KR7 P73 KR6 P72 KR5 P71 KR4 P70 KR3 P63 KR2 P62 KR1 P61 KRO P60 Rising edge detection circuit Falling edge detection circuit Input buffer INT2 Selector IRQ2 set signal I
196. en address must be specified in an 8 bit manipulation instruction a General register area The general register area can be manipulated with either general register manipulation instructions or memory manipulation instructions Up to 32 4 bit registers are available Of the 32 general registers registers not used by the program can be used as a data area or stack area b Stack memory area The stack area can be allocated within a bank with the stack pointer SP The bank for the stack area is selected from the memory banks 0 1 2 and 3 with the stack bank select register SBS Stack area can be used as a save area for subroutine or interrupt execution Use memory manipulation instructions to manipulate the stack bank select register SBS and the stack pointer SP Peripheral hardware area The peripheral hardware area is mapped at addresses F80H to FFFH of memory bank 15 Memory manipulation instructions are used to manipulate the peripheral hardware area as well as the static RAM area Note that however the number of bits to be manipulated at a time varies according to the individual addresses Addresses to which no peripheral hardware is assigned cannot be accessed since such address locations contain no data memory uPD75518 User s Manual Chapter 4 Internal CPU Functions 4 3 2 Specification of a Data Memory Bank If the memory bank enable flag MBE enables bank specification MBE 1 a memory bank is specif
197. en drain I O 1 P02 input 5 1 N ch open drain 1 Wake up function specification bit W WUP 0 Sets IRQCSIO each time serial transfer is completed in each mode 1 Used in the SBI mode only to set IRQCSIO only when an address received after bus release matches the data in the slave address register wake up state SBO SB1 goes to high impedance state Caution When WUP 1 is set during BUSY signal output BUSY is not released In the SBI mode the BUSY signal is output until the next falling edge of the serial clock SCK appears after release of BUSY is directed Before setting WUP z 1 be sure to confirm that the SBO or SB1 pin is high after releasing BUSY Signal from address comparator R Condition for being cleared 0 Condition for being set COI 1 When the slave address register SVA When the slave address register SVA does not match the data of the shift register matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Serial interface operation enable disable specification bit W Shift register operation Serial clock counter IRQCSIO flag 500 5 0 SIO SB1 pin CSIEO 1 Shift operation enabled Count operation Can be set Used in each mode
198. er SVA When the slave address register SVA does not match the data of the shift register matches the data of the shift register Note can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Serial interface operation enable disable specification bit W Shift register operation Serial clock counter IRQCSIO flag 500 5 0 SIO SB1 pin CSIEO 1 Shift operation enabled Count operation Can be set Used in each mode as well as for port 0 b Serial bus interface control register SBIC To use the two wire serial mode set SBIC as shown below For details on SBIC see 2 in Section 5 7 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to 00H In the figure below the hatched portions indicate the bits used in the two wire serial I O mode Address 7 6 5 4 3 2 1 BSYE ACKT CMDD RELD CMDT Do not use these bits in the two wire serial mode 0 Symbol RELT SBIC Bus release trigger bit W FE2H Command trigger bit W Remark W Write only Bus release trigger bit W RELT Control bit for bus release signal REL trigger output By setting RELT 1 the 500 latch is set to 1 Then the RELT bit automatically cleared to 0 5
199. er the main system clock or the subsystem clock can be used to produce 0 5 second intervals c The fast forward mode produces an interval 128 times faster 3 91 ms which is useful for program debugging and testing d A fixed frequency 2 048 kHz can be output to P23 BUZ so that it can be used for sounding the buzzer and for system clock frequency trimming e The frequency divider can be cleared to start the clock from zero second 5 4 1 Configuration of the Clock Timer Figure 5 25 shows the configuration of the clock timer Figure 5 25 Block Diagram of the Clock Timer fw 256 Hz 3 91 ms E fw Selector INTW From the 128 32 768 kHz IRQW rom the i clock 32 768 kHz Selector Frequency divider set signal generator 3 o 5 us 32 768 kHz r 2 048 2 Clear signal Output buffer 12 P23 BUZ PORT2 3 Bit 2 of PMGB WM P23 output Port 2 input Internal bus The values in parentheses are for fy 4 194304 MHz and fxr 32 768 kHz 5 44 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 4 2 Watch Mode Register The watch mode register WM is an 8 bit register for controlling the clock timer Figure 5 26 shows its format An 8 bit memory manipulation instruction is used to set the watch mode register A RESET signal clears all bits to 0 Example Time is set using the main system clock
200. eramic resonator for main system clock generation An external clock can also be applied a Crystal ceramic oscillation b External clock 75518 uPD75518 V External uPD74HC04 3r x2 X2 Crystal or ceramic resonator 2 2 18 XT1 2 These pins are used for connection to a crystal resonator for subsystem clock oscillation An external clock can also be applied a Crystal oscillation b External clock 75518 75518 Vss External 10 li T XTI clock gt E 1 XT2 Open XT2 Crystal Remark When using no subsystem clock see 5 in Section 5 2 2 2 2 19 RESET This is the pin for active low reset input The RESET input is asynchronous When a signal with certain low level width is applied to the pin a RESET signal is generated to cause a system reset which has priority over any other operations The RESET signal is used for normal CPU initialize start operation and is also used to release the STOP or HALT mode A Schmitt triggered input is used for the RESET input pin uPD75518 User s Manual 2 11 Chapter 2 Pin Functions 2 2 20 2 2 21 2 2 22 2 2 23 2 2 24 IC The internally connected IC pin is used to set the LPD75518 to test mode for inspection prior to shipping In normal operation connect the IC pin to the Vss pin keeping the writing as short as possible When the wiring between the
201. erface operation mode selection bit W CSIM04 CSIMO3 CSIMO2 Operation Bit order of 500 pin SIO pin mode shift register function function 0 0 3 wire 1007 9 lt gt 00 02 510 serial Transfer start CMOS Input mode with MSB output 1 100 7 lt gt XA Transfer starting with LSB 0 1 0 SBI mode 51007 lt gt 5 2 input Transfer starting N ch open with MSB drain I O 1 P02 input 581 03 N ch drain 1 0 1 1 2 wire 1007 0 lt gt 5 2 input serial Transfer starting N ch open mode with MSB drain 1 P02 input 581 03 N ch open drain 1 Remark x Don t care uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 41 Format of Serial Operation Mode Register 0 CSIMO 3 3 Wake up function specification bit W WUP 0 1 Sets IRQCSIO each time serial transfer is completed in each mode Used in the SBI mode only to set IRQCSIO only when an address received after bus release matches the data in the slave address register wake up state SBO or SB1 goes to high impedance state Caution When WUP 1 is set during BUSY signal output BUSY is not released In the SBI mode the BUSY signal is output until the next falling edge of the serial clock SCKO appears after release of BUSY is directed Before setting WUP 1 be sure to confirm that pin SBO or SB1 is high after releasing B
202. errupt Function 2 Example of using INTBT INTO falling edge active and INTTO with out multiple interrupt processing Interrupts are all low order lt Main program gt Reset 8 RBE 1 MBE 0 lt gt SEL RB2 2 MOV A 1 MOV IMO A CLR1 3 EI IEBT INTO service program EI IEO EI IETO A 0 lt 4 gt INTO Status 1 pa 4 RETI Y 1 2 3 4 5 A RESET signal disables all interrupts setting status 0 RBE 1 is specified in the reset vector table and register banks 2 and 3 are selected by the SEL RB2 instruction INTO is set to be falling edge active Interrupts are enabled by the EI and EI IExxx instructions On the falling edge of INTO the INTO interrupt service program is started status is set to 1 and all interrupts are disabled RBE 0 is set and register banks 0 and 1 are used Control is returned from the interrupts by the RETI instruction status 0 is set again and interrupts are enabled Remark As shown in the example above when all interrupts are given lower priorities selecting uPD75518 User s Manual register banks 2 and 3 by setting RBE 1 and RBS 2 in the main program or selecting register banks 0 and 1 by setting RBE 0 in the interrupt program saves the user the trouble of saving restoring registers Chapter 6 Interrupt Function 3 Multiple interrupt processing with high order interrupt
203. esses 000H to 3FFH in memory banks 0 to 3 One of memory banks 0 to 3 is selected according to the value of the 4 bit stack bank select register SBS See Table 4 1 Table 4 1 Stack Area to Be Selected by the Stack Bank Select Register SBS Stack area SBS1 SBSO 0 0 Memory bank 0 0 1 Memory bank 1 1 0 Memory bank 2 1 1 Memory bank 3 The SP is decremented before a write Save operation to stack memory and is incremented after a read restoration operation from stack memory The SBS is set by a 4 bit memory manipulation instruction Note that the high order two bits SBS3 and SBS2 are always set to 00 Figures 4 9 and 4 10 show data saved to and restored from stack memory in these stack operations To place the stack area at a given location the SP can be initialized with an 8 bit memory manipulation instruction and the SBS can be initialized with a 4 bit memory manipulation instruction Both can be read from as well When the SP is initialized to OOH a stack operation starts at the high order address nFFH of memory bank n specified with the SBS A stack area must be within the memory bank specified with the SBS If a stack operation exceeds address nOOH the operation returns to address nFFH in the same bank Linear stacking beyond memory bank boundaries is enabled only by resetting the SBS A RESET signal causes the contents of the SP and SBS to be undefined Remember to initialize the SP and SBS to a desired value at t
204. et an interrupt IRQCSIO is generated when a match address is received For this reason in communication with multiple devices a CPU other than a selected slave can operate independently of serial communication d Acknowledge signal ACK control function e The acknowledge signal which is used to confirm the reception of serial data can be controlled Busy signal BUSY control function The busy signal which is used to post the busy state of aslave can be controlled 5 109 Chapter 5 Peripheral Hardware Functions 2 SBI definition The format of serial data and signal used in the SBI mode are described below Serial data to be transferred in the SBI mode is classified into three types Address command and data Figure 5 52 is a timing chart for transferring address command and data Figure 5 52 Timing of SBI Transfer Address transfer 581 BUSY Bus release signal Command transfer Command signal SBO SB1 Data transfer SCKO LI LILI LILI UUU LUI 58 _ The bus release signal and command signal are output by the master BUSY is output by a slave ACK is output by either the master or a slave Normally the device which received 8 bit data outputs ACK The master continues to output the serial clock from when 8 bit data transfer starts to when BUSY is released 5 110 uPD75518 User s Manual Chapter 5 Per
205. et to 1100B The modulo register is set to the following value 50 ms 244 us 205 CDH lt Sample program gt SEL MOV MOV MOV MOV EI EI MB15 XA 0CCH TMODO XA Set the modulo register XA 01001100B TMO XA Set the mode register and start the timer Enable an interrupt Enable a timer interrupt Remark In this application the TIO pin can be used as an input 2 An interrupt is caused when the number of pulses active high applied to the TIO pin reaches 100 The high order four bits of the mode register are set to 0000 to select the rising edge The low order four bits of the mode register are set to 1100B The modulo register is set to 99 100 1 Sample program SEL MOV MOV MOV MOV EI EI uPD75518 User s Manual MB15 XA 100 1 TMODO XA Set the modulo register XA 00001100B TMO XA Set the mode register IETO Enable INTTO Chapter 5 Peripheral Hardware Functions 5 6 Timer Pulse Generator 5 6 1 Functions of the Timer Pulse Generator The uPD75518 contains one either timer pulse generator that can be used as a timer or a pulse generator It has the following functions 1 Functions available when the timer pulse generator is used in the timer mode 8 bit interval timer operation using one of five clock sources occurrence of IRQTPG Square wave output to the PPO pin 2 Functions available when the timer pulse generator is used in the
206. ext instruction if the addition generates a carry The carry flag is not affected ADDS rp 1 XA Function rp lt 1 Skip if carry Adds the contents of the XA register pair to the contents of register pair rp 1 HL DE BC XA HL DE BC in binary then skips the next instruction if the addition generates a carry The carry flag is not affected Example The register pair is left shifted MOV XA rp 1 ADDS 1p 1 XA NOP 10 34 uPD75518 User s Manual Chapter 10 Instruction Set ADDC A HL Function A CY A HL CY Adds the data at the data memory location addressed by the HL register pair together with the carry flag to the contents of the A register in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset If the execution of this instruction generates a carry when this instruction is immediately followed by the ADDS A n4 instruction the ADDS A n4 instruction is skipped If no carry is generated the ADDS A n4 instruction is executed and the skip function of the ADDS A n4 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 10 1 4 ADDC XA rp Function XA CY lt XA rp CY Adds the contents of register pair rp XA HL DE BC XA HL DE BC together with the carry flag to the contents of the XA register pair in binary If the addit
207. face operation enable disable specification bit W Note status of the 1 5 pin is selectable Remark Read only W Write only Serial interface operation enable disable specification bit W Shift register operation Serial clock counter IRQCSIO flag 500 580 and SIO SB1 pins CSIEO 0 Shift operation Cleared Held Used only for port 0 disabled 5 88 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Serial clock selection bit W The P01 SCKO pin assumes the following state according to the setting of CSIMOO and CSIMO 1 CSIMO1 CSIMOO P01 SCKO pin state 0 0 High impedance 0 1 High level output 1 0 1 1 When clearing CSIEO during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSIO 2 Clear CSIEO 3 Clear the interrupt request flag IRQCSIO uPD75518 User s Manual 5 89 Chapter 5 Peripheral Hardware Functions 5 7 5 Three Wire Serial I O Mode Operations The three wire serial mode is compatible with other modes used in the 75X series uPD7500 series and 78K series Communication is performed using three lines Serial clock SCKO serial output 500 and serial input 510 Figure 5 44 Example of Three Wire Serial l O System Configura tion 3 wire serial I O 3 wire serial I O Master CPU Slave CPU 75518 SCKO gt SCK 500 gt SI 510 lt 50
208. figuration of Port 9 Bit 1 of port mode register group C PM9 d Output buffer gt P90 gt o 91 Output latch gt 92 gt P93 Internal bus Input buffer a lt lt _ lt 1 9 1 lt lt 1 lt lt 4 lt 9 0 Pull down resistor T Mask option The uPD75P518 has no mask options uPD75518 User s Manual 5 7 Chapter 5 Peripheral Hardware Functions Figure 5 7 Configurations of Ports 10 and 11 Input buffer lt lt A 5 O Pmo a T O 1 2 Output latch O Pm2 O Pm3 CMOS output buffer Bit of port mode register group C m 10 11 Figure 5 8 Configuration of Port 15 Input instruction Input buffer n lt AN4 P150 o 2 lt O AN5 P151 T 8 lt 152 lt lt AN7 P153 Y Y To A D converter 5 8 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 1 2 Mode Setting The I O mode of each port is set by the port mode register as shown in Figure 5 9 The I O modes of ports 3 and 6 can be set bit by bit by port mode register group A PMGA The I O modes of ports 2 4 5 and
209. for manipulating SCKO P01 pin output is explained below 1 Set serial operation mode register 0 CSIMO SCKO pin output mode When serial transfer is halted SCKO 1 2 Manipulate the 01 output latch by using a bit manipulation instruction Example To output one SCKO clock cycle by software SEL MB15 or CLR1 MBE MOV XA 00000011B f5 23 output mode MOV CSIMO XA CLR1 OFFOH 1 5 lt 0 SET1 1 SCKO P01 lt 1 Figure 5 81 5 01 Pin Circuit Configuration Address FFOH 1 1 5 0 To internal circuit output latch C L From the serial clock SCKO control circuit SCKO pin output mode The P01 output latch is mapped to bit 1 of address FFOH A RESET signal sets the output latch to 1 uPD75518 User s Manual 5 143 Chapter 5 Peripheral Hardware Functions Cautions 1 During normal serial transfer the P01 output latch must be set to 1 2 The P01 output latch cannot be addressed by specifying PORTO 1 as described below The address of the latch FFOH 1 must be coded in the operand of an instruction directly However MBE 0 or MBE 1 MBS 15 must be specified before the instruction is executed CLR1 1 Not allowed PORTO 1 CLR1 OFFOH 1 Allowed SET1 OFFOH 1 5 144 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 8 Serial Interface Channel 1 5 8 4 Serial
210. formation refer to RA75X Assembler Package User s Manual Language addr 0000 3 RET Function 11 lt SP x PC14 PC13 PC12 lt SP 1 lt SP 2 PC7 4 lt SP 3 x x MBE RBE lt SP 4 SP lt SP 6 Restores the program counter MBE and RBE with the data at the data memory location stack addressed by the stack pointer then increments the contents of the stack pointer Caution The program status word is not restored except MBE and RBE RETS Function 11 lt SP x 14 13 12 lt SP 1 PC3 9 lt SP 2 PC7 4 lt SP 3 x X MBE RBE lt SP 4 SP SP 6 Then skip unconditionally Restores the program counter MBE and RBE with the data at the data memory location stack addressed by the stack pointer then skips unconditionally after incrementing the contents of the stack pointer Caution The program status word is not restored except MBE and RBE uPD75518 User s Manual 10 49 Chapter 10 10 50 Instruction Set RETI Function 11 lt SP x PC44 PC13 12 lt SP 1 lt SP 2 PCz 4 lt SP 3 PSW lt SP 4 PSWy lt SP 5 SP lt SP 6 Restores the program counter and program status word PSW with the data at the data memory location stack addressed by the stack pointer then increments the contents of the stack pointer This instruction is used when control is returned from
211. formed If a standby mode is released by the occurrence of an interrupt request the contents of the interrupt master enable flag IME determines whether to perform a vectored interrupt when the CPU resumes instruction execution a When IME 0 If a standby mode is released execution restarts with the instruction NOP instruction immediately following the instruction used to set the standby mode The interrupt request flag is held b When IME 1 If a standby mode is released a vectored interrupt is executed after the two instructions following the instruction used to set the standby mode are executed However if the standby mode is released by INT2 or INTW input of a test signal no vectored interrupt occurs and the same processing as a above is performed 7 4 Applications of the Standby Modes When the standby modes are used the following steps are used 1 2 3 4 5 6 lt 7 gt Detect a standby mode setting factor such as power removal an interrupt input or port input INT4 is useful for power removal detection Configure I O ports for minimum power consumption Be sure to connect signals which are high or low to input ports Specify interrupts for releasing a standby mode INT4 is useful All interrupt enable flags not used for release are to be cleared Specify an operation to be performed after release IME is to be manipulated according to whether interrupt pr
212. g IETO INT2 interrupt enable flag IE2 Timer pulse generator interrupt enable flag IETPG INT4 interrupt enable flag IE4 Watch timer interrupt enable flag IEW BT interrupt enable flag IEBT An interrupt enable flag set to 1 enables the corresponding interrupt and an interrupt enable flag set to 0 disables the corresponding interrupt When an interrupt request flag and the interrupt enable flag are set to 1 a vectored interrupt request VRQn occurs This condition is also used to release a standby mode A bit manipulation instruction or 4 bit memory manipulation instruction is used to manipulate an interrupt request flag and interrupt enable flag A bit manipulation instruction allows direct manipulation regardless of MBE setting An interrupt enable flag can be manipulated using an EI IExxx instruction or DI IExxx instruction The SKTCLR instruction is usually used to test an interrupt request flag Example EI IEO Enable INTO DI IE1 Disable INT1 SKTCLR IRQCSIO Skip and clear IRQCSIO when it is set to 1 Chapter 6 Interrupt Function When an interrupt request flag is set using an instruction even if there is no interrupt request a vectored interrupt is executed in the same way as when an interrupt is requested Inputting a RESET signal clears the interrupt request flags IRQO IRQBT IRQCSI IRQTO and IRQW to 0 Since IRQ1 IRQ2 and IRQ4 are undefined after RESET signal input clear them to 0 using software Inputti
213. gister used to select analog input channels direct the start of conversion detect the completion of conversion and select the comparator bias voltage ADM is set using an 8 bit manipulation instruction Bit 2 EOC and bit 3 SOC can be manipulated on a bit by bit basis A RESET signal initializes ADM to 04H That is only EOC is set to 1 with all bits cleared to 0 Figure 5 86 shows the format of ADM uPD75518 User s Manual 5 153 Chapter 5 Peripheral Hardware Functions Figure 5 86 Format of the A D Conversion Mode Register Address Symbol FD8H ADM Comparator bias voltage selection AVner gt 0 6 ADM1 m AVner lt 0 65 Remark This bit may be set to either or 1 for 0 6Vpp lt AVner lt 0 65 Conversion completion detection flag R 0 Conversion under way Conversion completed Conversion start direction bit W Setting this bit to 1 starts conversion After conversion is started the bit is reset to 0 automatically Analog channel selection bit W ADM6 ADM5 ADM4 Analog channel N1 N2 4 5 6 7 A D conversion is started a maximum of 24 fy seconds 2 67 us at fy 6 0 MHz Note after SOC is set For details see Section 5 9 2 Note 24 fy 3 81 us at fy 4 19 MHz 5 154 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 3 Succe
214. gure 3 2 To specify a general register bank a register bank enable flag RBE and a register bank select register RBS are contained The RBS is a register used to select a register bank and the RBE is a flag used to determine whether a register bank selected using the RBS is to be enabled The register bank RB enabled at instruction execution is determined as RB 5 Table 3 2 Register Bank to Be Selected with the RBE and RBS Register bank Bank 0 is always selected Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected Always 0 x Don t care The contents of the RBE are automatically saved or restored at the beginning or end of subroutine processing so that the RBE can be freely modified during subroutine processing In interrupt processing the RBE is automatically saved or restored and when interrupt processing is started the contents of the RBE can be specified for the interrupt processing by setting the interrupt vector table Therefore as indicated in Table 3 3 by selecting a register bank depending on whether the processing is normal or interrupt the general register need not be saved and restored for the level one interrupt processing and only the RBS needs to be saved and restored for the level two interrupt processing thus speeding up interrupt processing Table 3 3 Recommended Use of Register Banks with Normal Rou tines
215. h bit by bit mask option Note 3 impedance Withstand voltage is 10 V in open drain mode P50 P53 Note 2 10 N ch open drain 4 bit I O port High level when a M PORTS pull up resistor is M A Note 4 A pull up resistor can be provided provided or high bit by bit mask option Note 3 impedance Withstand voltage is 10 V in open drain mode P60 KRO Programmable 4 bit I O port CO Input P61 KR1 PORTE P62 KR2 can be specified bit by bit P63 KR3 Pull up resistors can be provided by software in units of 4 bits P70 KR4 4 bit port PORT7 P71 KR5 A pull up resistor can be specified Input F A P72 KR6 by software in units of 4 bits P73 KR7 P80 4 bit input port PORT8 x Input E P81 I O SCK1 F P82 501 P83 Input 511 P90 P93 4 bit I O port PORT9 x Low level when a V A pull down resistor can be pull down resistor is provided bit by bit provided or high mask option Note 3 impedance P100 P103 4 bit port PORT10 Input E P110 P113 4 bit port PORT1 1 Input Note 1 circuits enclosed in circles have Schmitt triggered input Note 2 An LED can be driven directly Note 3 The uwPD75P518 does not contain pull up or pull down resistors specified by the mask option Note 4 The data in parentheses applies only to the wPD75P518 2 2 uPD75518 User s Manual Table 2 1 Digital I O Port Pins 3 3 Chapter 2 Pin Functions
216. h applications The use of theuPD75P518K should be restricted to functional evaluation in experimental or trial manufacture uPD75518 User s Manual Pin name P10 P13 P20 P23 P30 P33 P40 P43 P50 P53 P60 P63 P70 P73 P80 P83 P90 P93 P100 P103 P110 P113 P120 P123 P130 P133 P140 P143 P150 P153 TIO PTOO Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Timer input Timer output PCL BUZ SCKO SCK1 500 501 510 51 580 581 INT4 INTO INT1 INT2 KRO KR7 PPO ANO AN7 AV REF AVss X1 X2 XT1 XT2 RESET Vpp Vss MDO MD3 Vpp Write verify mode selection pin Program power supply Chapter1 General Clock output Fixed frequency output Serial clock I O Serial output Serial input Serial bus External vectored interrupt External vectored interrupt External test input Key interrupt input Pulse output Analog input Reference voltage for analog signals Ground for analog signals Main system clock oscillation Subsystem clock oscillation Reset input Positive power supply Ground Remark pins in parentheses are used in the 75 518 uPD75518 User s Manual Chapter1 General MEMO 1 10 uPD75518 User s Manual 2 1 Pin Functions Table 2 1 Digital I O Port Pins 1 3 C
217. h data is trans IN XA PORTn accumulator ferred to the accumulator MOV A HL MOV XA HL ADDS A HL An operation is performed on pin An operation is performed ADDC A HL data and the accumulator on output latch data and SUBS A HL the accumulator SUBC A HL AND A HL OR A HL XOR A HL SKE A HL Pin data is compared with the Output latch data is com SKE XA HL accumulator pared with the accumulator OUT PORTn A Accumulator data is transferred Accumulator data is OUT PORTn XA to the output latch with the transferred to the output HL A output buffers kept off latch and is output on the MOV HL XA pins XCH A PORTn Pin data is transferred to the Data is exchanged XA PORTn accumulator and accumulator data between the output latch XCH A HL is transferred to the output latch and accumulator XCH XA HL with the output buffers kept off INCS PORTn Pin data incremented by 1 is Output latch data is INCS HL latched in the output latch incremented by 1 SET1 The output latch data of a The output pin state is CLR1 specified bit is rewritten but modified according to the MOV1 the output latch data of the instruction SKTCLR other bits is undefined Represents an addressing mode PORTn bit or PORTnN L uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 1 5 Specification of Internal Pull Up Pull Down Resistors Each port excluding POO and the pins of
218. hapter 2 Pin Functions Note 1 Input Also 8 Pin output used Function bit circuit as type POO Input 4 4 bit input port PORTO P01 SCKO For P01 to pull up resistors F A 800 580 can be provided by software x Input SIO SB1 in units of 3 bits M C P10 Input INTO With noise x Input C elimination function P11 INT1 4 bit input port PORT1 P12 INT2 Pull up resistors can be provided P13 TIO by software in units of 4 bits P20 PTOO 4 bit I O port PORT2 x Input E B P21 Pull up resistors can be provided P22 PCL by software in units of 4 bits P23 BUZ P30 Note 2 I O MDO Nete 3 Programmable 4 bit port x Input E C P31 Note 2 MD1 Note 3 PORT3 P32 Note 2 MD2 Note 3 O can be specified bit by bit P33 Note 2 MD3 Note 3 Pull up resistors can be provided by software in units of 4 bits Note 1 circuits enclosed in circles have a Schmitt triggered input Note 2 An LED can be driven directly Note 3 The data in parentheses applies only to the uwPD75P518 uPD75518 User s Manual 2 1 Chapter 2 Pin Functions Table 2 1 Digital I O Port Pins 2 3 Note 1 Input Also 8 Pin output used Function bit When reset circuit as type P40 P43 Note 2 O N ch open drain 4 bit port Co High level when M PORTA pull up resistor is M A Note 4 A pull up resistor can be provided provided or hig
219. hare vector address Note 1 Note 2 ISTO and IST1 are the interrupt status flags bits 3 and 2 of the PSW See Table 6 3 An interrupt service program start address and MBE and RBE setting values at the start of interrupt are stored in each vector table uPD75518 User s Manual Chapter 6 Interrupt Function 6 5 Multiple Interrupt Processing Control The uPD75518 can handle multiple interrupts by either of the following methods 1 Multiple interrupt processing by a high order interrupt In this method the uPD75518 selects an interrupt source among multiple interrupt sources enabling double interrupt processing That is the high order interrupt specified by the interrupt priority specification register IPS is enabled when the processing status is 0 or 1 Other interrupts interrupts lower than the specified high order interrupt are enabled only when the status is O See Figure 6 9 When only one interrupt is used as a level two interrupt using this method saves the user the trouble of enabling or disabling interrupts during an interrupt processing and holds down the number of nesting levels to two Figure 6 9 Multiple Interrupt Processing by a High order Interrupt Normal Low or high order High order processing interrupt processing interrupt Status 0 Status 1 processing Status 2 Interrupt is disabled IPS setting Interrupt is enabled High order interrupt occurrence Low
220. hat conforms to the NEC serial bus format To allow communication with multiple devices on a single master and high speed serial bus using two signal lines the SBI has a bus configuration function added to the clock synchronous serial method So the SBI can reduce ports and wires on boards when multiple microcomputers and peripheral ICs are used to configure a serial bus The master can output on the serial data bus an address for selecting a device subject to serial communication commands directed to the remote device and data A slave can identify an address commands and data from received data by hardware This function simplifies the serial interface channel 0 control portion of an application program The SBI function is available with devices such as the 75X series and 78K series 8 and 16 bit single chip microcomputers Figure 5 51 is an example of the SBI system configuration when the CPU with a serial interface conforming to SBI or peripheral ICs are used In the SBI mode the serial data bus pin SBO or SB1 is an open drain output So the serial data bus line is placed in the wired OR state A pull up resistor is required for the serial data bus line uPD75518 User s Manual 5 107 Chapter 5 Peripheral Hardware Functions 5 108 Figure 5 51 Example of SBI System Configuration Serial data bus SBO SB1 SBO SB1 Slave CPU Master CPU Serial clock pex SCKO SC
221. he format of IM1 A 4 bit manipulation instruction is used to set IM1 A RESET signal clears all bits to 0 and a rising edge is specified to be detected c As shown in Figure 6 3 c the INT4 circuit accepts an external interrupt at uPD75518 User s Manual its rising and falling edges Chapter 6 Interrupt Function Figure 6 3 Configurations of the INTO INT1 and INT4 Circuits a Configuration of the INTO circuit INTO INTO P10 o Noise elimination Edge detection ts circuit circuit set signal 01 00 2 IMO Detection edge specification o fx 64 AZ Sampling clock selection Input buffer Internal bus b Configuration of the INT1 circuit INT1 Edge detection INT1 P11 circuit hon set signal V Input buffer Detection edge specification 4 Internal bus c Configuration of the INT4 circuit INT4 INT4 P00 Both edge 2 gt 4 detection circuit set signal Input buffer Internal bus 6 8 uPD75518 User s Manual Figure 6 4 I O Timing of a Noise Eliminator Chapter 6 Interrupt Function INTO Shaped output 2 1 to 2 times INTO a Shaped output INTO b Shaped output lt 3 gt Longer than 2 times INTO Shaped output 15 15 15 15 15 lt gt Shorter than sampling cycle Removed as noi
222. he start of a program uPD75518 User s Manual 4 11 Chapter 4 Internal CPU Functions Figure 4 8 Format of Stack Pointer and Stack Bank Select Register Address Symbol D oe To D T Ls Ts Ts 55 ses 000H KA SBS Memory bank 0 SP OFFH J 100H 7 Memory bank 1 SP 1FFH J 200H Memory bank 2 SP 2FFH J 300H O gt Memory bank 3 SP 3FFH J Example SP initialization Specify memory bank 2 as a stack area to start stack operation at address 2FFH SEL 15 CLR1 MBE MOV A 2 MOV SBS A Specify memory bank 2 as a stack area MOV XA 00H MOV 5 SP lt 00H 4 12 uPD75518 User s Manual Chapter 4 Internal CPU Functions Figure 4 9 Data Saved to Stack Memory PUSH instruction CALL CALLA or CALLF instruction Interrupt Stack Stack Stack SP 6 PC11 PC8 SP 6 PC11 PC8 0 2 PCO 7 PC4 Lower bits of pair register PC3 PCO Upper bits of pair register Note PSW CY 15 215 115 0 Figure 4 10 Data Restored from Stack Memory POP instruction RET or RETS instruction RETI instruction Stack Stack Stack SPo 11 SPD 11 PC8 0 14 1 12 PC7 1571 11570 MBE RBE Note C PSW CY SK2 SK1 SKO Note PSW other than the MBE or RBE is no
223. ied with the 4 bit memory bank select register MBS 0 1 2 3 15 If the MBE disables bank specification MBE 0 memory bank 0 or 15 is automatically selected according to the addressing mode Locations in a bank is addressed by 8 bit immediate data or a register pair For details on the selection of a memory bank and addressing see Section 3 1 For how to use the particular data memory areas see the following sections and chapter General register area Section 4 4 Stack memory area Section 4 6 Peripheral hardware area Chapter 5 uPD75518 User s Manual 4 7 Chapter 4 Internal CPU Functions 4 4 General Register 8 x 4 Bits x 4 Banks The general registers are mapped to particular addresses in data memory Four banks of registers are provided with each bank consisting of eight 4 bit registers B C D E H L X and A The register bank RB to be enabled at the time of instruction execution is determined by RB RBE RBS RBS 0 to 3 Each general register allows 4 bit manipulation In addition BC DE HL or XA serves as a register pair for 8 bit manipulation DL also makes a register pair as well as DE and HL These three register pairs can be used as data pointers In 8 bit manipulation the register pairs in the register banks 0 lt gt 1 2 lt gt 3 that have the inverted value of bit 0 of the register bank RB address can be specified as BC DE HL and XA in addition to the registe
224. ignal can be output on the PPO pin and IRQTPG can be set at intervals of a fixed time period 215 fy 5 46 ms At 6 0 MHz Note PWM pulses output by the 75518 are active low and have a precision of 14 bits This pulse signal is applicable for electronic tuning and control of a DC motor when itis converted to analog voltage through integration using an external low pass filter See Figure 5 37 The PWM pulse signal is generated by combining the basic period determined by 210 fx and the secondary period by 215 fy so that the time constant of the external low pass filter can be decreased Table 5 8 lists the basic and secondary periods by oscillator frequency Note At 4 19 MHz 215 fy 7 81 ms Table 5 8 Basic and Secondary Periods fx 6 0 MHz fy 4 19 MHz Basic period 210 fy 171 us 244 us Secondary period 215 fy 5 46 ms 7 81 ms The low level width of a PWM pulse depends on the 14 bit modulo latch value The upper 8 bits of the modulo latch are transferred from the 8 bits of MODH and the lower 6 bits of the latch are transferred from the upper 6 bits of MODL When the PWM pulse signal is converted to analog form in the configuration as shown in Figure 5 37 the voltage level of the analog output is obtained as follows Van Vref x Value of modulo latch 214 Vref Reference voltage of external switching circuitry uPD75518 User s Manual 5 65 Chapter 5 Peripheral Hardware Functions To prevent an incorrect PWM p
225. imer Mode Internal bus 8 MODL MODH 8 Modulo register H Modulo register L 8 8 TPGM3 Set to 1 INTTPG IRQTPG set signal A Output buffer T Selec flip flop tor PPO Set TPGM4 TPGM5 TPGM7 Frequency divider n a TPGM1 5 62 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Example 1 Set IRQTPG every 1 95 ms and output a high on the PPO pin CLR1 MBE or SEL MB15 MOV XA 00100000B MOV MODL XA MOV XA 0FFH MOV MODH XA MOV XA 10011011B MOV TPGM XA Timer start PPO lt 1 Caution When the timer operating in the timer operation mode is stopped IRQTPG may be set because the T flip flop is set Therefore the timer must be stopped with an interrupt being disabled then IRQTPG must be cleared Example 2 DI CLR1 MBE MOV XA 0 MOV TPGM XA CLR1 IRQTPG Figure 5 35 Timer Mode Operation Timing i Ly LI LILI LILI LILI LILI LILI CP Modulo register MODH N pes T flip flop TEN desi 1 PPO Set TPGM1 Generate IRQTPG uPD75518 User s Manual 5 63 Chapter 5 Peripheral Hardware Functions Table 5 7 Modulo Register Settings When fx 6 0 MHz MODL bits 2 6 Interrupt generation interval Square wave output frequency 6 5 4 3 2 fx 6 0 MHz fx 6 0 MHz 0 0 0 1 256 N41 fx 85 3 us to 10 9 ms fy 256 N
226. imers and I O ports to addresses F80H to FFFH data memory space as shown in Figure 3 7 This means that there is no particular instruction to control peripheral hardware but all peripheral hardware is controlled using memory manipulation instructions Some mnemonics for hardware control are available to make programs readable To manipulate peripheral hardware the addressing modes listed in Table 3 4 can be used Table 3 4 Addressing Modes Applicable to Peripheral Hardware Operation Applicable addressing mode Applicable hardware Bit Direct addressing mode specifying mem bit All hardware manipulation with MBE 0 MBE 1 MBS 15 allowing bit manipulation Direct addressing mode specifying fmem bit ISTO IST1 MBE RBE regardless of MBE and MBS setting EOT IExxx IRQxxx PORTn x Indirect addressing mode specifying BSBn x pmem L regardless of MBE and MBS setting PORTn x 4 bit Direct addressing mode specifying mem All hardware allowing 4 bit manipulation with MBE 0 or MBE 1 MBS 15 manipulation Register indirect addressing mode specifying HL with MBE 1 MBS 15 8 bit Direct addressing mode specifying mem All hardware allowing 8 bit manipulation even address with MBE 0 or MBE 1 manipulation MBS 15 Register indirect addressing mode specifying HL with the L register containing an even number with MBE 1 and MBS 15 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Figu
227. in phase with the falling edge of SCKO after 8 bit data transfer This signal may be synchronized with any clock of SCKO The transmitter checks if the receiver returns the acknowledge signal after 8 bit data transfer If the acknowledge signal is not returned after a specified period of time the transmitter can assume that the reception failed uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions f Busy signal BUSY and ready signal READY The busy signal informs the master that a slave is getting ready for data transfer The ready signal informs the master that a slave is ready for data transfer Figure 5 60 Busy and Ready Signals sp0 sB1 X Wck Busy READY In the SBI mode a slave notifies the master of the busy state by changing SBO or SB1 from high to low The busy signal is output following the acknowledge signal output by the master a slave The busy signal is set and released in phase with the falling edge of SCKO The master automatically terminates output of serial clock SCKO when the busy signal is released The master can transfer the next data when the busy signal is released and a slave enters the state in which the ready signal is to be output uPD75518 User s Manual 5 115 Chapter 5 Peripheral Hardware Functions 3 Register setting To set the SBI mode manipulate the following two registers Serial operation mode register 0 CSIMO Serial bus interface
228. ion error can be detected by the methods described below a Comparing SIOO data before start of transmission with SIOO data after start b of transmission With this method the occurrence of a transmission error is assumed if two SIOO values disagree with each other Using the slave address register SVA Transmit data is set in 5100 and SVA as well before the data is transmitted On completion of transmission the COI bit match signal from the address compa rator of serial operation mode register 0 CSIMO is tested If the result is 1 the transmission is regarded as successful If the result is 0 the occurrence of a transmission error is assumed uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 9 Communication operation In the SBI mode the master usually selects a slave device to communicate with from multiple devices by outputting the address of the slave to the serial bus After selecting a device to communicate with the master exchanges commands and data with the slave device thus establishing serial communication Figures 5 68 to 5 71 show the timing charts of data communication operations In the SBI mode the shift register performs shift operation on the falling edge of the serial clock SCKO Transmit data is held on the SOO latch and is output on the 5 2 or 581 03 pin starting with the MSB Receive data applied to the SBO or SB1 pin is latched in the shift register on the
229. ion for setting STOP instruction HALT instruction System clock at setting Main system clock Main system clock Subsystem clock Operation Clock generator Only the main system clock Only CPU clock is stopped with status is stopped oscillation continued Basic interval timer Operation is stopped Operation is possible Note IRQBT is set at reference time intervals Serial interface Operation is possible only when Operation is possible Note Channel 0 external SCKO input is selected for the serial clock Serial interface Operation is possible only when Operation is possible Note Channel 1 external SCK1 input is selected for the serial clock Timer event counter Operation is possible only when Operation is possible Note TIO pin input is selected for the count clock Watch timer Operation is possible only when Operation is possible fxr is selected for the count clock A D converter Operation is stopped Operation is possible Note Timer pulse generator Operation is stopped Operation is possible Note External interrupt INTO is disabled INT1 INT2 and INT4 are enabled CPU Operation is stopped Release signal Interrupt request signals transmitted out from hardware which are enabled by interrupt enable flags or RESET input Note Applicable only when the main system clock operates uPD75518 User s Manual 7 3 Chapter 7 Standby Function A STOP instruction is used to set the STOP mode and a HALT instruction is used to set
230. ion generates a carry the carry flag is set If no carry is generated the carry flag is reset ADDC rp 1 XA Function rp 1 CY lt rp 1 XA CY Adds the contents of the XA register pair together with the carry flag to the contents of register pair rp 1 HL DE BC XA HL DE BC in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset SUBS A HL Function A lt A HL Skip if borrow Subtracts the data at the data memory location addressed by the HL register pair from the contents of the A register then sets the result in the A register If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected uPD75518 User s Manual 10 35 Chapter 10 10 36 Instruction Set SUBS XA rp Function XA lt XA rp Skip if borrow Subtracts the contents of register pair rp XA HL DE BC XA HL DE BC from the contents of the XA register pair then sets the result in the XA register pair If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected Example Data memory is compared with register pair rp MOV SUBS XA rp mem 2 rp mem rp SUBS rp 1 XA Function 1 lt rp 1 XA Skip if borrow Subtracts the contents of the XA register pair from the contents of register
231. ipheral Hardware Functions a Bus release signal REL When the SCKO line is high the serial clock is not output the SBO or SB1 line changes from low to high This signal is called the bus release signal and is output by the master Figure 5 53 Bus Release Signal This signal indicates that the master is to send an address to a slave Slaves contain hardware to detect the bus release signal b Command signal CMD When the SCKO line is high the serial clock is not output the SBO or SB1 line changes from high to low This signal is called the command signal which is output by the master Figure 5 54 Command Signal LS w 580 581 o Slaves contain hardware to detect the command signal uPD75518 User s Manual 5 111 Chapter 5 Peripheral Hardware Functions c Address An address is 8 bit data and is output by the master to connected slaves to select a particular slave Figure 5 55 Address SCKO SBO SB1 Address Bus release signal Command signal The 8 bit data following the bus release signal or command signal is defined as an address A slave detects the condition for the addresses by hardware and checks whether the 8 bit data matches the number assigned to the slave slave address If the 8 bit data matches the slave address that slave is selected The selected slave continues to communicate with the master unti
232. ipheral Hardware Functions Figure 5 36 Block Diagram of the Timer Pulse Generator PWM Pulse Generation Mode Internal bus 8 8 MODH MODL Modulo register H 8 Modulo register L 8 MODH 8 MODL 6 Modulo latch 14 Output buffer PWM pulse generator PPO Frequency divider INTTPG TPGM5 TPGM7 IRQTPG set signal 215 fx 5 46 ms 6 0 MHz Note Note At 4 19 MHz 215 fy 7 81 ms Figure 5 37 Sample Configuration of D A Conversion Using uPD75518 75518 Switching Low pass TER signal circuit filter Van analog voltage 3 Static output to the PPO pin When pulse output is unnecessary the PPO pin can be used as normal static output In this case the output data is set in TPGM4 with 5 set to 0 and TPGM7 to 1 uPD75518 User s Manual 5 67 Chapter 5 Peripheral Hardware Functions 5 6 4 Application of the Timer Pulse Generator 1 The timer pulse generator is used as an interval timer which gener ates interrupts at 1 ms intervals when fy 4 194304 MHz From Table 5 7 an equation for setting the timer to 1 ms is selected Since N is an integer from 1 to 255 there is some difference between the set time and an actual time To obtain high resolution that is to suppress the difference as little as possible the value of N must be as large as possible T 32 N 1 fx modulo register L MODL 2
233. is executed then returns to the operation mode after the wait time specified by the BTM register has elapsed uPD75518 User s Manual Chapter 7 Standby Function 7 2 Release of the Standby Modes The STOP mode and HALT mode are released by a RESET signal or the generation of an interrupt request signal Note that is enabled with the interrupt enable flag Figure 7 1 shows how the STOP and HALT modes are released Note INTO is excluded Figure 7 1 Standby Mode Release Operation 1 2 a Release of the STOP mode by RESET signal Wait i approximately Note STOP instruction proximately L RESET signal Operating Operating mode STOP mode HALT mode mode 3 4 Oscillation No oscillation Oscillation Clock lt Note A wait time is approx 31 3 ms when operating at 4 19 MHz b Release of the STOP mode by the occurrence of an interrupt Wait Time set by BTM r STOP instruction Standby release signal Operating Operating mode STOP mode HALT mode mode gt 3 lt 3 lt Oscillation No oscillation Oscillation Clock gt lt Remark dashed line indicates the case where the interrupt request that releases the standby mode is accepted IME 1 uPD75518 User s Manual 7 5 Chapter 7 Standby Function Figure 7 1 Standby Mode Release Operation 2 2 c Release of the HA
234. is point using a diode with a low not higher than 0 3 V AVner ANO AN7 1 J 77 uPD75518 AVss c AN4 P150 to AN7 P153 pins The analog input pins AN4 to AN7 are also used for an input port PORT15 When any of AN4 to AN7 is selected for A D conversion no input instruction must be executed for PORT15 during A D conversion Otherwise the precision of conversion may deteriorate If a digital pulse signal is applied to a pin adjacent to a pin being used for A D conversion an expected A D conversion value may not be obtained because of coupling noise So no digital pulse signal should be applied to a pin adjacent to a pin being used for A D conversion uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 9 5 Application of A D Converter Example Select channel 0 ANO for analog input and set the following uPD75518 User s Manual SCC3 SCC0 0 0 PCC1 PCCO 21 0 Use middle speed mode Sample program TEST CLR1 MOV MOV NOP NOP SKT BR MOV MBE or SEL MB15 XA 08H XA lt 00001000B ADM XA Select ANO and start A D conversion Wait until EOC flag test Wait until EOC flag test EOC EOC flag test TEST XA SA XA A D conversion result 5 161 Chapter 5 Peripheral Hardware Functions 5 10 Bit Sequential Buffer 16 bit The bit sequential buffer BSB is special data memory for bit manipulations In particular the buffer allows bi
235. istor must be turned off so FFH must be written to SIOO beforehand The state of the 500 latch is output on the SBO SB1 pin so the SBO SB1 pin output states can be controlled by setting the RELT or CMDT bit However this operation must not be performed during serial transfer The output level of the SCKO be controlled by manipulating the PO1 output latch in the output mode internal system clock mode See Section 5 7 8 uPD75518 User s Manual 5 103 Chapter 5 Peripheral Hardware Functions 3 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register 0 CSIMO The serial clock can be selected out of the foll owing three clocks Table 5 12 Serial Clock Selection and Application In the Two Wire Serial I O Mode Mode register Serial clock Timing for shift register R W and Application CSIMO CSIMO Source Masking of start of serial transfer 1 0 serial clock 0 0 External Automatically lt 1 gt In the operation halt mode Slave CPU SCKO masked when CSIEO 0 0 1 TOUT 8 bit data lt 2 gt When the serial clock is masked Arbitrary speed flip flop transfer is after 8 bit transfer serial transfer 1 0 fy 26 completed 3 When SCKO is high Low speed 1 1 serial transfer 4 Signals Figure 5 50 shows operations of RELT and CMDT Figure 5 50 Operations of RELT and CMDT SOO latch RELT CMDT 5 104 uPD75518 User s Manu
236. ixed frequency output Input E B for buzzer or system clock trimming SCKO P01 Serial clock I O Input F A 500 5 0 P02 Serial data output or serial bus Input p B SIO SB1 Serial data input or serial bus I O Input M C INT4 Input Edge detection vectored interrupt input Either a rising or falling edge is detected INTO Input P10 Edge detection vectored Synchronous C interrupt input INT1 P11 The edge to be detected is Asynchronous selectable INT2 Input P12 Edge detection testable input Asynchronous C Rising edge detection KRO KR3 Input P60 P63 Parallel falling edge detection testable input Input P C KR4 KR7 Input 70 73 Parallel falling edge detection testable input Input SCK1 P81 Serial clock I O Input 501 P82 Serial data output Input E SH Input P83 Serial data input Input ANO AN3 Input Analog input to A D converter Y AN4 AN7 P150 Y A P153 AVREF Input A D converter reference voltage input EE Z AVss A D converter reference GND potential X1 X2 Input Connection to a crystal ceramic resonator for main system clock generation When external clock is used it is input to X1 and its inverted signal is input to X2 XT1 Input Connection to a crystal resonator for subsystem clock generation XT2 When external clock is used it is input to XT1 and XT2 is left open Note 2 Note 1 The circuits enclosed in ci
237. l Contents 6 9 Interrupt 6 23 Chapter 7 Standby 7 1 71 Setting of Standby Modes and Operation Status 7 3 7 2 Release of the Standby Modes 7 5 7 3 Operation after a Standby Mode Is Released 7 8 7 4 Applications of the Standby Modes 7 8 Chapter 8 Reset Function 8 1 Chapter 9 Writing to and Verifying Program Memory 9 1 9 1 Operating Modes when Writing to and Verifying the Program Memory 9 3 9 2 Writing to the Program 9 4 9 3 Reading the Program Memory 9 6 9 4 Erasing the Program Memory for the UPD75P518K Only 9 7 9 5 Screening One Time PROM Products 9 7 Chapter 10 Instruction etr 10 1 10 1 Unique Instructions 10 2 10 1 1 04 00 0 000 10 2 10 1
238. l jenuew 51955 8rcc adr 2 910 s WOH 10 1 N 81545 eui 01 Ajdde ui TIO P13 20 BUZ P23 O PPO P80 O SIO SB1 P03 O 500 5 0 02 O lt gt 5 01 SCK1 P81 INTO P10 O INT1 P11 O INT2 P12 INT4 P00 KR7 P73 ANO AN4 P150 AN7 P153 AVreF AVss Basic interval timer Timer event counter 0 Watch timer Timer pulse generator Serial interface 0 interface 1 Interrupt control Bit se quential buffer 16 A D converter Program counter 15 ROM oete 1 program memory Decode and control RAM data memory 1024 x 4 bits fx 2N Clock generator Clock divider CPU clock Stand by control Clock output control O O O PCL P22 XT1 XT2 X1 X2 RESET Vep Nete 2 Port 0 POO Port 1 P10 P13 weibeig 401g Nets M Pots 4 P50 P53 Pete 4 y P60 6 Ports 4 80 8 Porta 4 P90 P93 1 4 100 P103 pros n eso p133 15 K 4 150 P153 0 lt lt DD 55 Chapter 1 General 1 5 Pin Configuration Note 2 O P120 lt gt P121 O P122 O P123 lt gt P130 O
239. l disconnection is directed by the master Figure 5 56 Slave Selection Using an Address Not selected saves Not selected Not selected 4 Transmits address for slave 2 Selected 5 112 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions d Command and data The master sends commands to the slave selected by sending an address The master also transfers data to or from the slave Figure 5 57 Command SONO 1E lol laf 14 151 lel 17 18 SBO 581 c7 A C5 A C4 A C3 A C2 A C CO Command signal Command Figure 5 58 Data SEKO 1E lol 13 4 lsi lef 17 18 580 581 07K D8 D5 D3 X D2 A D1 A DO Data The 8 bit data following the command signal is defined as a command The 8 bit data without the command signal is defined as data The usage of commands or data can be selected optionally according to the communication specifications uPD75518 User s Manual 5 113 Chapter 5 Peripheral Hardware Functions 5 114 e Acknowledge signal ACK The acknowledge signal confirms the reception of serial data between the transmitter and the receiver Figure 5 59 Acknowledge Signal When output in phase with the 11th clock of SCKO SCKO 8 9 Hoj t1 580 581 CK When output in phase with the 9th clock of SCKO 9 580 581 The acknowledge signal is one shot pulse output
240. l whether to accept interrupts b An interrupt processing start address and the MBE and RBE for interrupt processing can be freely set using a vector table to speed up the practical start of the interrupt service program c By assigning a higher priority to a given interrupt source multiple interrupt processing is enabled with that interrupt d An interrupt request flag IRQxxx can be tested and cleared Generation of an interrupt can be checked by software e A standby mode STOP or HALT can be released by an interrupt request A release source can be selected using an interrupt enable flag 6 1 Configuration of the Interrupt Control Circuit Figure 6 1 shows the configuration of the interrupt control circuit Each hardware item is mapped to a data memory space uPD75518 User s Manual 6 1 jenuew 51955 grcc adr Internal bus terrupt enable flag IExx 3 gt IM1 INTBT e IRQBT B Both edge detection IRQ4 circuit Edge INTO Noise gt m s Edge INT1 pit detection IRQ1 D circuit INTCSIO gt IRQCSIO D INTTO IRQTO D INTTPG gt D INTW gt Raw D Rising edge NTE detection P12 detection KR7 P730 circuit NN XP 2 2 Priority control
241. le disable bit Disable reloading of modulo register TPGM3 z Enable reloading of modulo register PPO output latch data 0 Output 0 to PPO output latch TPGM4 1 Output 1 to PPO output latch PPO pin output selection bit static pulse Static output on PPO pin TPGM5 Pulse output square wave PWM on PPO pin PPO pin output enable disable bit 0 Disable output on PPO pin high impedance TPGM7 1 Enable output on PPO pin uPD75518 User s Manual 5 61 Chapter 5 Peripheral Hardware Functions 5 6 3 Configuration and Operation of the Timer Pulse Generator 1 When the timer pulse generator is used in the timer mode Figure 5 34 shows the configuration of the timer pulse generator when it is used in the timer mode The timer mode is selected by setting bit 0 of TPGM to 1 In the timer mode TPGM3 must be set to 1 allowing the modulo register to be reloaded at any time In the timer mode a prescaler is selected by the modulo register L MODL and a frequency or interrupt interval value is set by the modulo register H MODH The timer starts when TPGM 1 is set to 1 Figure 5 35 shows the operation timing for MODH setting and Table 5 7 lists frequencies and interrupt intervals that can be set The output to the PPO pin can be switched between the square wave output and static output To output a square wave set TPGM5 and TPGMT to 1 Figure 5 34 Block Diagram of the Timer Pulse Generator T
242. log input Seven lines can be pulled up by software 28 Four lines for LED driving 16 lines can be pulled up by software Four lines can be pulled down by mask option 20 Eight lines for LED driving Withstand voltage is 10 V 20 lines can be pulled up by mask option 20 Eight lines for LED driving Withstand voltage is 9 V 20 lines can be pulled up by mask option 8 channels with 8 bit resolution Successive approximation system Vpp 2 7 to 6 0 V Vpp 3 5 to 6 0 V Timer event counter Basic interval timer Timer pulse generator 14 bit PWM output enabled Clock timer 4 channels 2 channels standard serial bus interface SBl three wire SIO One channel General synchronous serial interface three wire SIO One channel Provided Not provided 3 byte stack 2 byte stack External 3 internal 4 External 1 internal 1 Clock test flag provided Parallel edge detection flag for key scan input provided The following instructions are added to the 75X high end model MOVT XA BCDE MOVT XA BCXA BRA addr1 75X high end BR IBCDE CALLA addr1 Operating power voltage Vpp 2 7 to 6 0 V Vpp 4 75 to 5 5 Package 80 pin plastic QFP 14 x 20 mm 80 pin ceramic WQFN Note 2 Note 1 No mask option is provided for the 75 516 or uPD75P518 Note 2 For the uPD75P516 and uPD75P518 only uPD75518 User s Manual 1 3 Chapter1
243. lose to the signal line pPD75518 High current b The signal lines cross PORTn n 0 to 15 pPD75518 d The current flows through the ground line of the oscillator The potential at points A B and C fluctuates 75518 T WE High current TIT Remark When wiring the subsystem clock read X1 and X2 as XT1 and XT2 respectively In this case a resistor must be added to XT2 in series uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 18 Examples of Oscillator Connections which should be Avoided 2 2 e A signal is taken directly from f The signal lines of the main system the resonator clock and subsystem clock are parallel and adjacent to each other pPD75518 pPD75518 rs TORT XT2 and XT1 are wired TT in parallel See the caution below for the countermeasure Remark When wiring the subsystem clock read X1 and X2 as XT1 and XT2 respectively In this case a resistor must be added to XT2 in series Caution In f of Figure 5 18 XT2 and X1 are wired in parallel This may cause the system to malfunction due to crosstalk noise in XT2 from X1 To prevent this XT2 and X1 must not be wired in parallel It is also recommended that the IC pin located between XT2 and X1 be connected to Vss pPD75518 2 10 X1 uPD75518 User s Manual 4
244. lt gt regi XA rp 2 2 XA lt gt rp 8 MOVT XA PCDE 1 3 XA lt PC14 94 DE RoM XA PCXA 1 3 XA lt PC14 94XA ROM 5 XA BCDE Note 1 3 lt Bo 9 CDE Rom 11 XA Q BCXA Note 1 3 XA lt Bo g4 CXA ROM 11 Note Only lower three bits are valid in the B register 10 12 uPD75518 User s Manual Chapter 10 Instruction Set Instruc Mne Number Machine Address tion monic Operand cycle Operation ing area Skip condition bytes MOV1 CY fmem bit 2 2 CY lt fmem bit 4 CY pmem L 2 2 CY lt pmem7 2 L3 2 bit L4 0 5 2 CY H mem bit 2 2 CY lt H mem3 bit 1 fmem bit CY 2 2 fmem bit CY 4 pmem L CY 2 2 pmem z 2 L3 bit L1 5 lt CY 5 H mem bit CY 2 2 H mems o bit lt CY 1 ADDS A n4 1 1 5 A A n4 carry 8 2 2 5 lt XA n8 carry A HL 1 1 5 lt A HL carry XA rp 2 2 5 lt XA tp carry rp 1 XA 2 248 rp lt rp XA carry ADDC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY lt XA rp4 CY rp 1 XA 2 2 rp1 CY lt 1 SUBS A HL 1 1 5 1 borrow XA rp 2 2 5 lt XA rp borrow 1 2 2 5 lt rp1 XA borrow 8 SUBC A HL 1 1 A CY A HL CY 1 5 XA rp 2 2 XA CY lt XA rp CY rp 1 XA 2 2 rp1 CY lt 1 x AND 4 2 2 lt 4 A HL 1 1 lt AA HL 1 XA rp 2 2 XA XA rp rp 1 XA 2 2 lt rp 1AXA OR 4 2 2 lt
245. lt 3 gt STATUS command The STATUS command reads the status of the current slave Figure 5 76 Transfer Format of the STATUS Command M S S S Data Command Remarks M Output by the master 5 Output by the slave The slave returns the status in the format shown in Figure 5 77 Figure 5 77 Status Format of the STATUS Command Status Bit indicating whether there is data ready for transmission 0 No transmit data 1 Transmit data of one byte or more Bit indicating whether the device is ready for data reception 0 No receive data storage area 1 Receive data storage area not smaller than one byte is present Bit indicating whether an error occurred 0 No error 1 Error occurred during previous transfer Bit indicating whether master can be changed or not 0 Master cannot be changed 1 Master can be changed When the master receives a status it returns ACK to the current slave 5 140 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions lt 4 gt RESET command The RESET command changes the currently selected slave to a non selected slave When a RESET command is transmitted any slave can be placed in the non selected state Figure 5 78 Transfer Format of the RESET Command M S RESET ACK Command Remarks M Output by the master S Output by the slave 5 CHGMST command The CHGMST command passes the master authority to the curre
246. m SET1 fmem bit SET1 pmem L SET1 H mem bit Function Bit specified in operand lt 1 Sets the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit CLR1 mem bit Function mem bit 0 mem 07 0 OOH FFH bit By 9 0 3 Clears the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem CLR1 fmem bit CLR1 pmem L CLR1 H mem bit Function Bit specified in operand 0 Clears the bit in data memory specified by bit manipulation addressing fmem bit pmem QL H mem bit SKT mem bit Function Skip if mem bit 1 Dz g 00H FFH bit By 9 0 3 Skips the immediately following instruction if the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 1 SKT fmem bit SKT pmem L SKT H mem bit Function Skip if bit specified in operand 1 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit is set to 1 10 42 uPD75518 User s Manual Chapter 10 Instruction Set SKF mem bit Function Skip if mem bit 0 Dz g 00H FFH bit By 9 0 3 Skips the immediately following instruction if the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 0 SKF fmem bit SKF pmem L SKF H mem bit Function Skip if
247. m bit 0 0 1 0 1 05 0605 D4 Do Dy Do manipulation teu 5 CLR1 mem bit 0 0 1 0 0 D7Dg 05 D4 D3 05 D4 Do 1 0011100 2 SKT mem bit 0 0 1 1 1 05 06 05 94 93 Da D4 Do 1 0111111 2 SKF mem bit 0 0 1 1 0 05 06 05 D4 Da Da D4 Do 1 0111110 2 SKTCLR 1 0011111 2 AND1 1 0101100 2 OR1 1 0101110 2 XOR1 1 0111100 2 10 22 uPD75518 User s Manual Chapter 10 Instruction Set Instruction _ Mnemonic Operand Instruction code B4 Bo Branch BR BRA BRCB Sub routine stack control CALLA CALLF RET RETS RETI PUSH POP yo IN OUT Interrupt El control DI CPU HALT control STOP NOP Special SEL GETI laddr addr PCDE PCXA BCDE BCXA laddri Icaddr laddr laddri rp BS rp BS A PORTn XA PORTn PORTn XA IExxx taddr 416 to 2 1 to 15 10101100 0 0 Ao o o a O o 1 S3 S2 S4 So 1100100000100 0100000000 0100000101 0100000001 o o o addr1 o oco 100 01 caddr gt 10101101 addr 1110110 addr1 0 faddr ___ gt o o e e e e 13073 13 4 0 0 1 PoP 1 01100100000111 00 1 PoP 0 01100100000110 1000
248. med in the verify mode 1 Pull low all unused pins to Vss by means of resistors Bring X1 to low level Apply 5 V to Vpp and Vpp Wait 10 us Select program memory address clear mode Apply 6 V to Vpp and 12 5 V to Vpp Select program inhibit mode Select verify mode Data is output sequentially one address at a time for each cycle of four clock pulses appearing on the X1 pin Select program inhibit mode Select program memory address clear mode 10 Apply 5 V to Vpp and to Vpp 11 Turn the power off The timing for steps 2 to 9 is shown below X1 P40 P43 P50 P53 MDO P30 MD1 P31 MD2 P32 MD3 P33 uPD75518 User s Manual Chapter 9 Writing to and Verifying Program Memory PROM 9 4 Erasing the Program Memory for the uPD75P518K Only The contents of data written into the 75 518 can be erased by exposing the window to ultraviolet radiation The wavelength of ultraviolet must be at least 250 nm To erase data completely the exposure must be 15 Ws cm ultraviolet intensity x erasure time When a commercial ultraviolet lamp wavelength of 254 nm intensity of 12 mW cm is used it takes 15 to 20 minutes to complete erasure Cautions 1 Exposing the window to direct sunlight or fluorescent light for a long time may cause erasure of data To protect data the upper window must be masked with a shielding cover film Shielding cover films are attached t
249. mem bit 10 43 D 2 uPD75518 User s Manual AND1 AND1 OR1 OR1 OR1 XOR1 XOR1 XOR1 CY pmem L 10 43 CY H mem bit 10 43 CY fmem bit 10 43 CY pmem L 10 43 CY H mem bit 10 43 CY fmem bit 10 44 CY pmem L 10 44 CY H mem bit 10 44 Branch instructions BR BR BR BR BR BR BR BRA BRCB TBR Subroutine stack conirol instructions addr1 10 44 laddr 10 44 10 44 PCDE 10 45 PCXA 10 45 BCDE 10 46 BCXA 10 46 laddr1 10 46 Icaddr 10 47 addr 10 47 CALL laddr 10 48 CALLA laddr1 10 48 CALLF lfaddr 10 48 TCALL addr 10 49 RET 10 49 RETS 10 49 10 50 PUSH rp 10 50 PUSH BS 10 50 POP 10 50 BS 10 50 uPD75518 User s Manual Appendix D Instruction Index Interrupt control instructions El 10 51 10 51 01 10 51 DI 10 51 I O instructions IN A PORTn 10 51 IN XA PORTn 10 52 OUT 10 52 OUT 10 52 CPU control instructions HALT 10 53 STOP 10 53 NOP 10 53 Special instructions SEL RBn 10 53 SEL MBn 10 53 GETI taddr 10 54 Appendix D Instruction Index D 2 Instruction Index Alphabetical Order A ADDC ADDC ADDC ADDS ADDS ADDS ADDS ADDS AND AND AND AND AND1 AND1 AND1 B BR BR BR BR BR BR BR BRA BRCB C CALL CA
250. meter by the master When OOH is specified as the data length the 256 byte data transfer is assumed Figure 5 74 Transfer Format of the WRITE and END Commands Command Data Data Data Command Remarks M Output by the master S Output by the slave If the slave has an enough area for storing receive data of the specified length the slave returns ACK If the slave does not have an enough area an error occurs ACK is not returned in this case The master transmits an END command when all data have been transferred The END command informs the slave that all data have been transferred correctly The slave accepts an END command even before data reception is uncompleted In this case the data received just before the acceptance of the END command becomes valid The master compares the contents of SIOO before transfer with the contents of SIOO after transfer to check whether the data has been output onto the bus correctly If the contents of SIOO disagree with each other the master interrupts data transfer by transmitting a STOP command Figure 5 75 Transfer Format of the STOP Command M S M S Data Command Data transfer interruption Data check error occurs Remarks M Output by the master S Output by the slave When the slave receives a STOP command the slave invalidates the most recently received one byte uPD75518 User s Manual 5 139 Chapter 5 Peripheral Hardware Functions
251. n the B register 10 16 uPD75518 User s Manual Chapter 10 Instruction Set Instruc Mne tion monic Operand Number of bytes Machine cycle Address Operation ing area Skip condition Subroutine stack Interrupt control CPU control Special PUSH POP El DI IN Note HALT STOP NOP SEL GETI rp BS rp BS 1 A PORTn XA PORTn RBn MBn taddr 1 2 Oo m nm nm m m Oo m nm N N N N N 1 8 2 lt rp SP lt SP 2 SP 1 lt MBS SP 2 lt RBS SP lt SP 2 rp lt SP 1 SP SP lt SP 2 MBS lt SP 1 RBS SP SP lt SP 2 IME IPS 3 1 IExxx 1 IME IPS 3 0 lt 0 lt PORTn 0 15 XA lt PORT 4 PORTn 4 6 PORTn lt A 2 7 9 14 lt XA n 4 6 Set HALT Mode PCC 2 1 Set STOP Mode PCC 3 1 No Operation RBS lt n n 0 3 MBS n nz0 1 2 3 15 For a TBR instruction 10 13 0 lt taddr 4 9 taddr 1 14 lt 0 For TCALL instruction SP 5 SP 6 SP 3 SP 4 lt x PC44 0 SP 2 lt x x MBE RBE 13 0 lt taddr 5 9 taddr 1 SP lt SP 6 0 Depends upon the referenced instruction For an instruction other than TBR and TCALL taddr taddr 1 Note MBE 0 or MBE
252. na 4 8 4 5 Accum l atOF 4 10 4 6 Stack Pointer SP and Stack Bank Select Register SBS 4 11 4 7 Program Status Word PSW 4 14 4 8 Bank Select Register BS 4 18 Chapter 5 Peripheral Hardware Functions 5 1 5 1 Digital WO 5 1 5 1 1 Types Features and Configurations of Digital I O Ports 5 2 5 1 2 VO Mode hti cbe ted 5 9 5 1 3 Digital Port Manipulation Instructions 5 12 5 1 4 Digital Port Operation 5 15 5 1 5 Specification of Internal Pull Up Pull Down Resistors 5 17 5 1 6 Timing of Digital 4 6 5 20 5 2 Clock 5 21 5 2 1 Clock Generator 5 22 5 2 2 Functions and Operations of the Clock Generator 5 23 5 2 3 System Clock and CPU Clock Setting 5 32 5 2 4 Clock Output Circuit essen 5 35 5 3 Basic Interval TIMER aai cedes conus sa rica Chiron ra ice ci 5 38 5 3
253. nce 1 0 1 Serial clock output High level output 1 1 0 1 1 1 uPD75518 User s Manual 4 When clearing CSIEO during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSIO 2 Clear CSIEO 3 Clear the interrupt request flag IRQCSIO Example 1 Example 2 fx 24 is selected as the serial clock serial interrupt IRQCSIO is generated each time serial transfer is completed and serial transfer is performed in the SBI mode with the SBO pin used as the serial data bus SEL MB15 or CLR1 MBE MOV 810001010 MOV CSIMO XA CSIMO 10001010B Serial transfer dependent on the contents of CSIMO is enabled SEL MB15 or CLR1 MBE SET1 CSIEO Chapter 5 Peripheral Hardware Functions 2 Serial bus interface control register SBIC Figure 5 42 shows the format of the serial bus interface control register SBIC SBIC is an 8 bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus SBIC is used mainly in the SBI mode SBIC is manipulated using a bit manipulation instruction SBIC cannot be manipulated using a 4 bit or 8 bit memory manipulation instruction Each bit may or may not allow read and or write operation Figure 5 42 When the RESET signal is input this register is set to OOH Caution Only the following bits can be used in the three wire and two wire serial I O
254. nd status 1 is set to disable all interrupts 4 When INTTO processing is completed status 0 is set again 5 INTCSIO and INT4 which have been disabled are enabled then control returns 6 30 uPD75518 User s Manual Chapter 7 Standby Function The uPD75518 provides a standby function to reduce the power consumption by the system The standby function is available in the two modes the STOP mode and HALT mode Differences between these two modes are as follows 1 STOP mode In the STOP mode the main system clock oscillator is stopped and the entire system stops The current used by the CPU is reduced to quite a low level In addition the contents of data memory can be preserved with a low supply voltage of down to Vpp 2 V that is this mode is effective to retain data memory with a very low current The STOP mode of the 75518 can be released by an interrupt request to enable intermittent operations However when the STOP mode is released a wait time is needed for stable oscillation Select the HALT mode when processing must be started immediately after an interrupt request 2 HALT mode In the HALT mode the CPU clock is stopped but the oscillation of the system clock oscillator continues In this mode the system uses more current than in the STOP mode However the HALT mode is suitable for starting processing immediately after an interrupt request or for intermittent operations such as watch operation
255. nd the timing of taking in pin data or output latch data on the internal bus Figure 5 12 I O Timing of Digital I O Ports a When data is input by a 1 machine cycle instruction 1 machine cycle Instruction T Manipulation instruction execution Input timing gt b When data is input by a 2 machine cycle instruction 2 machine cycles Instruction Manipulation instruction execution gt Input timing c When data is latched by a 1 machine cycle instruction Manipulation instruction execution Output latch output pin d When data is latched by a 2 machine cycle instruction Instruction Manipulation instruction execution Output latch output pin 5 20 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 2 Clock Generator The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode uPD75518 User s Manual 5 21 Chapter 5 Peripheral Hardware Functions 5 2 1 Clock Generator Configuration Figure 5 13 shows the configuration of the clock generator Figure 5 13 Block Diagram of the Clock Generator Basic interval timer BT Timer event counter Serial interface Clock timer Clock output circuit A D converter INTO noise eliminator Subsystem clock generator Clock timer Timer pulse generator Main system 1 8 to 1 4096 clock generator Frequenc
256. ng a RESET signal clears the interrupt enable flags to 0 disabling all interrupts Table 6 2 Set Signals for Interrupt Request Flags Interrupt Set signals for interrupt request flags Interrupt request enable flag flag IRQBT Set by a reference time interval signal from the basic IEBT interval timer IRQ4 Set by a detected rising or falling edge of an 4 00 4 pin input signal IRQO Set by a detected edge of an INTO P10 pin input signal IEO The detection edge is specified by the INTO mode register IMO IRQ1 Set by a detected edge of an INT1 P11 pin input signal IE1 The detection edge is specified by the INT1 mode register IM1 IRQCSIO Set by a serial data transfer completion signal for the serial IECSIO interface IRQTO Set by a match signal from timer event counter 0 IETO IRQTPG Set by a match signal from the timer pulse generator IETPG IRQW Set by a signal from the clock timer IEW IRQ2 Set by a detected rising edge of an INT2 P12 pin input signal IE2 or a detected falling edge of one of a KRO P60 KR7 P73 input signals 6 6 uPD75518 User s Manual Chapter 6 Interrupt Function 2 Configurations of the INTO INT1 and INT4 circuits a As shown in Figure 6 3 a the INTO circuit accepts an external interrupt at Note its rising or falling edge The edge to be detected can be selected The INTO circuit has a noise elimination function see Figure 6 4 called a noise eliminator using a sampling clock
257. ns All areas excluding 0000H and 0001H can be used as normal program memory 0000H to 0001H Vector address table for holding the MBE and RBE setting values and program start address at the time of a reset allowing a reset start at an arbitrary address within a 16K byte space OOOOH to 3FFFH 0002H to 000DH Vector address table for holding the MBE and RBE setting values and program start address for each vectored interrupt allowing interrupt processing to be started at an arbitrary address within a 16K byte space 0000H to 3FFFH 0020H to 007FH Table area referenced by the GETI instruction Note Note The GETI instruction can represent an arbitrary 2 byte or 3 byte instruction or two 1 byte instructions in 1 byte thus reducing the number of program bytes uPD75518 User s Manual Chapter 4 Internal CPU Functions Figure 4 2 Program Memory Map uPD75517 A A A 0000H Internal reset start address high order 6 bits Internal reset start address low order 8 bits 0002H NTBT INT4 start address high order 6 bits Entry address NTBT INT4 start address low order 8 bits specified in CALLF 0004H NTO start address high order 6 bits instruction BR BCDE NTO start address low order 8 bits Br an ch BR BCXA igh i address branch address 0006H NT1 start address high order 6 bits specified in bie NT1 start address low order 8 bits BRCB Branch address Icaddr specified in 0008H NTC
258. nt Counter Mode Register 5 50 Format of the Timer Event Counter Output Enable Flag 5 51 Operation in the Count Operation Mode sse 5 52 Error at the Start of the Timer sss esee 5 55 Format of Timer Pulse Generator Mode Register 5 61 Block Diagram of the Timer Pulse Generator Timer 5 62 Timer Mode Operation Timing sisse esent nnne nnn 5 63 Block Diagram of the Timer Pulse Generator PWM Pulse Generation Mode sss inneren nnns 5 67 Sample Configuration of D A Conversion Using 75518 5 67 Sample Circuit Applicable to TV 5 69 Example of the SBI System Configuration esses 5 74 Block Diagram of the Serial Interface Channel 0 5 75 Format of Serial Operation Mode Register 0 5 5 78 Format of Serial Bus Interface Control Register 5 82 Peripheral Hardware of Shift Register 0 sse 5 86 Example of Three Wire Serial I O System Configuration 5 90 Timing of Three Wire Serial VO Mode 5 93 Operations of RELT and
259. nt register may be destroyed So when the count pulse is changed bit 3 of the count mode register must be set to 1 and the timer must be restarted at the same time Re set instruction Re set instruction Clock A specified Clock B specified Clock A specified Clock B lt 1 gt lt 2 gt uPD75518 User s Manual 5 57 Chapter 5 Peripheral Hardware Functions 5 Operation after the modulo register is changed The contents of the modulo register are changed when an 8 bit data memory manipulation instruction is executed Count Pulse CP Modulo register Count register Match signal Match signal If the new value of the modulo register is less than the value of the count register the count register continues count operation until it overflows then it restarts count operation from 0 Accordingly if the new value m of the modulo register is less than the value n before it is changed the timer must be restarted after the contents of the modulo register are changed Count pulse CP Modulo register Count register 5 58 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 5 8 Applications of the Timer Event Counter 1 Timer 0 is used as an interval timer that generates interrupts at intervals of 50 ms The high order four bits of the mode register are set to 0100B to select maximum set time 62 5 ms The low order four bits of the mode register are s
260. nted or decremented by one in the automatic increment or automatic decrement mode each time an instruction is executed thus simplifying the program step Example The data at 50H to 57H is transferred to 110H to 117H DATA1 EQU 57H DATA2 EQU 117H SET1 MBE MBE lt 1 SEL MB1 MBS lt 1 MOV D DATA1 SHR4 D lt 5 MOV HL ZDATA2 AND OFFH HL lt 17H LOOP MOV A QDL lt DL XCH A HL A lt gt HL L lt L 1 BR LOOP The addressing mode using the HL register pair as the data pointer finds a wide range of operations such as data transfer operations comparison and I O The addressing mode using the DE register pair or DL register pair is applied to the MOV and XCH instructions This addressing mode combined with an increment decrement instruction for a general register or register pair enables data memory space addresses to be freely updated as shown in Figure 3 3 uPD75518 User s Manual 3 9 Chapter 3 Data Memory Operations and Memory Example 1 The data at 50H to 57H is compared with the data at 110H to 117H DATA1 DATA2 LOOP EQU EQU SET1 SEL MOV MOV MOV SKE BR DECS BR 57H 117H MBE MB1 D DATA1 SHR4 HL DATA2 AND OFFH A DL A HL A HL NO NO L YES L L 1 LOOP Example 2 The data memory of 00H to FFH is cleared to O LOOP CLR1 CLR1 MOV MOV MOV INCS BR RBE MBE XA 00H HL 04H HLA HL lt A HL HL lt HL
261. nternal bus S1D2412 Z4 01 PU ZLNI 8ui 10 9 9 9 19 uonoungJ 14 1914 4 uPD75518 User s Manual Chapter6 Interrupt Function Interrupt priority specification register IPS The interrupt priority specification register selects an interrupt with a higher priority from multiple interrupts using the low order three bits Bit 3 interrupt master enable flag IME specifies whether to disable all interrupts The IPS is set using a 4 bit memory manipulation instruction Bit 3 is set by an EI instruction and reset by a DI instruction When changing the low order three bits of the IPS interrupts must be disabled IME 0 beforehand A RESET signal clears all bits to O Figure 6 7 shows the format of the interrupt priority specification register Example DI Disable interrupts CLR1 MBE MOV A 1011 MOV IPS A Assign a higher priority to INT1 then enable interrupts Chapter 6 Interrupt Function Figure 6 7 Interrupt Priority Specification Register Address 3 2 1 0 IPS3 IPS2 IPS1 IPSO FB2H Symbol IPS High order interrupt selection All low order interrupt The listed vectored 1 VRQ1 interrupts are treated as high order interrupts VRQ2 INTO aM Jud VRQA INTCSIO This status is disabled Interrupt master enable flag IME All interrupts are disabl
262. ntire data memory space A particular memory bank MB is always used in this addressing mode In the MBE 0 mode when an address from 000H to 07FH is specified in the operand memory bank 0 MB 0 is always used When an address from F80H to FFFH is specified memory bank 15 MB 15 is always used Accordingly both the data area ranging from OOOH to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed in the MBE 0 mode In the MBE 1 mode MB MBS and specifiable data memory space can be expanded This addressing mode can be applied to four instructions bit set and reset instructions SET1 and CLR1 and bit test instructions SKT and SKF Example FLAG is set FLAG2 is reset and whether FLAGS is zero is tested FLAG1 EQU FLAG2 EQU FLAG3 EQU SET1 SEL SET1 CLR1 SKF OSFH 1 Bit 1 at address 3FH 087H 2 Bit 2 at address 87H 7 0 Bit 0 at address MBE MBE lt 1 MBO MBS 0 FLAG1 FLAG1 lt 1 FLAG2 FLAG2 0 FLAG3 FLAG3 0 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory 2 4 bit direct addressing mem In this addressing mode the operand of an instruction directly specifies any area in the data memory space in units of four bits As with the 1 bit direct addressing mode in the MBE 0 mode a fixed space consisting of the data area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can
263. ntly selected slave Figure 5 79 Transfer Format of the CHGMST Command M 5 S 6 Command Data Remarks M Output by the master S Output by the slave When the slave receives a CHGMST command the slave returns one of the following data to the master after checking whether the slave can receive the master authority OFFH Master changeable OOH Master not changeable The slave compares the contents of SIOO before transfer with the contents of SIOO after transfer If the contents of SIOO disagree with each other an error occurs ACK is not returned in this case If the master receives OFFH the master returns ACK to the slave and starts to operate as a slave The slave which transmitted OFFH starts to operate as the master when it receives ACK uPD75518 User s Manual 5 141 Chapter 5 Peripheral Hardware Functions lt Error occurrence gt If a communication error occurs the operation described below is per formed The slave reports the occurrence of an error by not returning ACK to the master If an error occurs during reception of data the slave sets the status bit for indicating error occurrence and cancels all command processing being performed When the transmission of one byte is completed the master checks for ACK from the slave If ACK is not returned from the slave within a predetermined period after transmission completion the occurrence of an error is assumed the master outpu
264. o FFDH Port 13 PORT13 FFEH Port 14 PORT14 FFFH Port 15 PORT15 Number of bits that Bit can be manipulated R W manipulation addressing R W fmem bit Note uPD75518 User s Manual KRO to KR7 are read only In 4 bit parallel input processing PORT6 or PORT7 is specified Chapter 3 Data Memory Operations and Memory MEMO 3 28 uPD75518 User s Manual Chapter 4 Internal CPU Functions 4 1 Program Counter PC 15 Bits The program counter is a 15 bit binary counter for holding program memory address information Figure 4 1 Program Counter Format Usually each time an instruction is executed the program counter is automatically incremented according to the number of bytes in the instruction Note that the reset start address must be set within a space of 16K bytes 0000H to 3FFFH because a RESET signal initializes program memory contents as follows PC13 PC8 lt low order six bits of address 0000H PC7 PCO lt contents of address 0001H PC14 lt 0 When a branch instruction BR BRA BRCB is executed immediate data indicating the branch destination and the contents of a register pair are set in all or some bits of the program counter When a subroutine call instruction CALL CALLA CALLF is executed or a vectored interrupt occurs the current contents of the program counter already incremented return address for fetching the next instructi
265. o UV EPROM products of NEC 2 For normal erasure operation the ultraviolet lamp must be set not more than 2 5 cm apart from the uPD75P518K Remark Degradation of the ultraviolet lamp or stains on the package window may cause an erasure operation to take a longer time 9 5 Screening One Time PROM Products NEC cannot execute a complete test of one time PROM product uPD78P518GF due to their structure before shipment It is recommended that you screen verify PROM products after writing necessary data into them and storing them at 125 C for 24 hours NEC offers a charged service called QTOP microcomputer service This service includes writing to one time PROM marking screening and verification Ask your sales representative for details uPD75518 User s Manual 9 7 Chapter 9 Writing to and Verifying Program Memory PROM MEMO 9 8 uPD75518 User s Manual Chapter 10 Instruction Set The instruction set of the uPD75518 is an improved and extended version of the instruction set used with the 7500 series which is the predecessor of the 75X series Succeeding the instruction set of the uPD7500 series the uPD75518 has quite new enhanced instruction set with the following features 1 Bit manipulation instructions allowing a wide variety of applications 2 Efficient 4 bit manipulation instructions 3 Eight bit data transfer instructions 4 GETI instruction for reducing program sizes 5 String effect inst
266. o clear SBO or SB1 before or after serial transfer 5 118 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Bus release detection flag R RELD Condition for being cleared RELD 0 Condition for being set RELD 1 1 The transfer start instruction The bus release signal REL is detected is executed 2 The RESET signal is entered 3 CSIEO 0 Figure 5 41 4 SVA does not match 5100 when an address is received Command detection flag R CMDD Condition for being cleared CMDD 0 Condition for being set CMDD 1 1 The transfer start instruction The command signal CMD is detected is executed 2 The bus release signal REL 3 The RESET signal is entered 4 CSIEO 0 Figure 5 41 Acknowledge trigger bit W ACKT When set after transfer ACK is output in phase with the next SCKO After ACK signal output this bit is automatically cleared to 0 Cautions 1 Never set ACKT before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE 0 Acknowledge enable bit R W 0 Disables automatic output of the acknowledge signal ACK Output by ACKT is possible 1 When set before transfer ACK is output in phase with the 9th clock of SCKO When set after transfer ACK is output in phase with SCKO immediately following the set instruction execution Acknowledge dete
267. ocessing is performed or not Specify a CPU clock to be used after release If the CPU clock is changed required machine cycles must elapse before the standby mode is set Select a wait time to be used when a standby mode is released Set a standby mode using a STOP or HALT instruction A standby mode when combined with the system clock switch function enables a lower power consumption and lower voltage operation uPD75518 User s Manual Chapter 7 Standby Function 1 Application of the STOP mode at fy 4 19 MHz lt Use of the STOP mode under the following conditions gt The STOP mode is set on the falling edge of INT4 and is released on the rising edge of INT4 INTBT is not used All ports have a high impedance when ports are externally configured for minimum power consumption at high impedance The INTO and INTTO interrupts are used forthe program but are not used to release the STOP mode After the STOP mode is released interrupts are enabled After the STOP mode is released the lowest speed CPU clock is used for operation A wait time used when the STOP mode is released is about 31 3 ms After the STOP mode is released another wait time of 31 3 ms is used for stable power supply operation The POO INT4 pin is checked twice to remove chattering lt Timing chart gt Voltage on wait operation operation Operating mode STOP mode CPU operation P 9 gt gt A
268. ode lt lt 4 gt lt Internal reset operation Note A wait time is approx 31 3 ms when operating at 4 19 MHz uPD75518 User s Manual 8 1 Chapter 8 Reset Function Table 8 1 Statuses of the Hardware after a Reset 1 2 Hardware RESET signal in a standby mode RESET signal during operation Program counter PC PSW Carry flag CY Skip flags SKO to SK2 Interrupt status flags ISTO IST1 Bank enable flags MBE RBE Low order 6 bits a address 0000H in program memory are set in PC13 8 and the data at address 0001H are set in PC7 0 Held 0 0 Bit 6 at address 0000H in program memory is set in RBE and bit 7 is Low order 6 bits at address 0000H in program memory are set in PC13 8 and the data at address 0001H are set in PC7 0 Undefined 0 0 Bit 6 at address 0000H in program memory is set in RBE and bit 7 is set in MBE set in MBE Data memory RAM Held Note Undefined General registers X A H L D E B C Held Undefined Bank select registers MBS RBS 0 0 0 0 Stack pointer SP Undefined Undefined Stack bank select register SBS Undefined Undefined Basic interval timer Counter BT Undefined Undefined Mode register BTM 0 0 Timer event counter Counter TO 0 0 Modulo register TMODO FFH FFH Mode register TMO 0 0 TOEO TOUT flip flop 0 0 0 0 Timer pulse generator Modulo registers Held Held MODH MODL Mode register TPGM 0
269. on are saved in the stack memory data memory indicated by the stack pointer then the jump destination address is loaded When a return instruction RET RETS RETI is executed the contents of the stack memory are set in the program counter uPD75518 User s Manual 4 1 Chapter 4 Internal CPU Functions 4 2 Program Memory ROM 24448 x 8 Bits 75517 32640 x 8 Bits 075518 and uPD75P518 As the program memory the uPD75517 is provided with a mask ROM of 24448 x 8 bits the uPD75518 with a mask ROM of 32640 8 bits and the uPD75P518 with a PROM of 32640 x 8 bits The program memory is used for storing programs an interrupt vector table GETI instruction reference table table data and so forth Figures 4 2 and 4 3 show the program memory maps Program memory is addressed by the program counter Table data can be referenced using the table reference instruction MOVT Figures 4 2 and 4 3 also show the allowable branch address ranges for the branch instructions and subroutine call instructions The BRA addr1 and the CALLA addr1 instructions allow a direct branch throughout the whole space The BR instruction allows a branch to addresses contents of the PC less 15 to one or plus two to 16 regardless of block boundaries The program memory is located at addresses 0000H to 5F7FH for the uPD75517 or 0000H to 7F7FH for the u PD75518 and uPD75P518 The following addresses are assigned to special functio
270. or to debug hardware and software when an application system using 75X series is developed The IE 75000 R is used in combination with an emulation probe This provision enables affective debugging when connected with the host machine and a PROM programmer The IE 75000 R EM is an emulation board for evaluating an application system using 75X series The IE 75000 R EM is used in combination with the IE 75000 R or IE 75001 R The IE 75000 R contains the emulation board The IE 75001 R is an in circuit emulator to debug hardware and software when an application system using 75X series is developed The IE 75001 R is used in combination with an optional emulation board IE 75000 R EM and an emulation probe This provision enables effective debugging when connected with the host machine and a PROM programmer EP 75516GF R is an emulation probe for the uPD75518 This probe is used in combination with the IE 75000 R or IE 75001 R The EV 9200G 80 80 pin conversion socket is attached to support easy connection with the user system This program enables the host machine to control the IE 75000 R or IE 75001 R program under the RS 232 C and Centronics interfaces Host machine Part number OS Distribution media product name PC 9800 series MS DOS 3 5 inch 2HD uS5A13IE75X Ver 3 30 1 to 5 25 inch 2HD uS5A101E75X Ver 5 00A Note 2 IBM PC AT PC DOS 5 25 inch 2HC uS7B101E75X Ver 3 1 Note 1 Maintenance service only
271. order interrupt INTTO occur concurrently INTBT is executed first If it is highly unlikely that a high order interrupt is requested during high order interrupt processing the DI IExx instruction need not be executed When a request for low order interrupt INTCSIO occurs during the high order interrupt processing INTCSIO is held On completion of the high order interrupt INTCSIO which is given a higher priority among the low order interrupts being held is executed On completion of the INTCSIO interrupt service program INTTO which has been held is executed Chapter 6 Interrupt Function 7 Enabling of level two interrupts enabling level two INTTO and INTO interrupts with INTCSIO and INT4 handled as level one interrupts lt Main program gt Reset A IETO E cent stalus lt INTCSIO service program gt 1 4 1 5 Status 1 CLR1 ISTO Y 1 INTCSIO DI 8 DI 4 Status 0 INTTO service program Status 0 Status 1 4 RETI Status 0 lt 5 gt El IECSIO El 1 4 RETI 1 When an INTCSIO interrupt not allowed to be a level two interrupt occurs the INTCSIO service program starts and status 1 is set 2 Status 0 is set by clearing ISTO INTCSIO and INT4 not allowed to be level two interrupts are disabled 3 When INTTO allowed to be a level two interrupt occurs the level two interrupt is executed a
272. ort 8 Caution Be sure to write 0 to bits 2 to 6 of the serial operation mode register uPD75518 User s Manual 5 147 Chapter 5 Peripheral Hardware Functions 2 Example To select fx 24 as the serial clock and to set the serial transfer end flag EOT to 1 each time serial transfer terminates SEL MB15 or CLR1 MBE MOV XA 10000010B MOV CSIM1 XA CSIM1 10000010B Shift register 1 SIO1 5101 is an 8 bit register which performs parallel serial conversion and serial transfer shift operation in phase with the serial clock Serial transfer is started by writing data to SIO1 In transmission data written to SIO1 is output on the serial output SO1 In reception data is read from the serial input SI1 into SIO1 Data can be read from or written to SIO1 using an 8 bit manipulation instruction When the RESET signal is applied during operation the value of SIO1 becomes undefined When the RESET signal is applied in the standby mode the value of SIO1 is preserved Shift operation is stopped after 8 bit transmission or reception is completed The timing for reading SIO1 and start of serial transfer writing to SIO1 is as follows When the serial interface operation enable disable bit CSIE1 is set to 1 except after data is written to shift register 1 When the serial clock is masked after 8 bit serial transfer When SCK1 is high 5 8 4 Operation Halt Mode The operation halt mode is used when seri
273. ote 3 instruction BR addr BRA laddr1 CALL addr and CALLA laddr1 instructions Caution The GETI instruction is skipped in one machine cycle One machine cycle is equal to one cycle of the CPU clock and four different machine cycles are available for selection according to the PCC setting See Section 5 2 2 1 uPD75518 User s Manual 10 11 Chapter 10 Instruction Set Instruc Mne Number Machine Address tion monic Operand of cycle Operation ing area Skip condition bytes MOV A n4 1 1 A n4 String effect A reg1 n4 2 2 regi n4 XA n8 2 2 XA n8 String effect A HL n8 2 2 HL n8 String effect B 2 8 2 2 2 n8 A HL 1 1 A HL 1 A HL 1 2 S lt HL then L lt L 1 1 L 0 A HL 1 2 5 lt HL then L lt 1 1 1 L FH A rpat 1 1 A 1 2 XA HL 2 2 XA lt HL 1 HL A 1 1 HL lt A 1 HL XA 2 2 HL lt XA 1 A mem 2 2 A mem 3 5 2 2 lt x9 2 2 mem 3 2 2 mem lt XA 3 A reg 2 2 reg XA rp 2 2 XA lt rp reg1 A 2 2 regi A rp 1 XA 2 2 rp lt XCH A HL 1 1 A lt gt HL 1 A HL 1 2 5 lt gt HL then L lt L 1 1 L 0 A HL 1 248 HL then L lt L 1 1 L FH A rpat 1 1 A lt gt 1 2 XA HL 2 2 XA lt gt HL 1 A mem 2 2 A mem 3 XA mem 2 2 XA lt gt mem A reg1 1 1
274. out an overflow or underflow that occurs when an arithmetic operation with a carry ADDC SUBC is executed The carry flag functions as a bit accumulator and therefore can be used to store the result of a Boolean algebra operation performed on the CY and a bit at a specified data memory bit address The carry flag is manipulated using special instructions independently of the other PSW bits A RESET signal causes the carry flag to be undefined Table 4 3 Carry Flag Manipulation Instructions Instruction mnemonic Carry flag operation processing Instruction SET1 CY Sets CY to 1 dedicated to CLR1 CY Clears CY to 0 carry flag NOT1 CY Inverts the state of CY manipulation SKT CY Skips if CY is 1 Bit transfer MOV1 1 CY Transfers the state of CY to a specified bit instruction MOV1 CY 1 Transfers the state of a specified bit to CY Bit Boolean AND1 CY 1 ANDs ORs or XORs CY with a specified bit instruction OR1 CY 1 then sets the result in CY XOR1 CY 1 Interrupt Interrupt execution Saves CY and all other PSW bits to handling stack memory in parallel Restores CY together with the other PSW bits from stack memory in parallel Remark 1 represents the following bit addressing fmem bit pmem L H mem bit Example Bit 3 at address 3FH is ANDed with P33 then the result is set in P50 MOV H 3H Set the high order 4 bits of the address in H registe
275. pair rp 1 HL DE BC XA HL DE BC then sets the result in register pair rp 1 If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected SUBC A HL Function A CY A HL CY Subtracts the data at the data memory location addressed by the HL register pair together with the carry flag from the contents of the A register then sets the result in the A register If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset If the execution of this instruction generates no borrow when this instruction is followed by the ADDS A n4 instruction the ADDS A n4 instruction is skipped If a borrow is generated the ADDS A n4 instruction is executed and the skip function of the ADDS A n4 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 10 1 4 SUBC XA rp Function XA CY Subtracts the contents of register pair rp XA HL DE BC XA HL DE BC together with the carry flag from the contents of the XA register pair then sets the result in the XA register pair If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset uPD75518 User s Manual Chapter 10 Instruction Set SUBC rp 1 XA Function rp 1 CY lt rp 1 XA CY Subtracts the content
276. ports 8 10 11 and 15 of the uPD75518 can be provided with an internal pull up or pull down resistor These resistors are specified as follows e Pull up resistor Software or mask option Pull down resistor Mask option only The software uses the pull up resistor register group A POGA to specify whether an internal pull up resistor is incorporated Table 5 4 shows how a pull up or pull down resistor is specified for each port pin Specification by software is based on the format given in Figure 5 10 Table 5 4 Specification of Internal Pull Up Pull Down Resistors Port pin name Specification of internal pull up pull down resistor Bit in Port 0 PO1 PO3 Note 1 Internal pull up resistors are specified by Bit 0 software in 3 bit units Port 1 P10 P13 Internal pull up resistors are specified by Bit 1 Port 2 P20 P23 software in 4 bit units Bit 2 Port 3 P30 P33 Bit 3 Port 6 P60 P63 Bit 6 Port 7 P70 P73 Bit 7 Port 4 P40 P43 An internal pull up resistor is specified Port 5 P50 P53 bit by bit by mask option Note 2 Port 12 P120 P123 Port 13 P130 P133 Port 14 P140 P143 Port 9 P90 P93 An internal pull down resistor is specified bit by bit by mask option Note 2 Note 1 The POO pin cannot be provided with a pull up resistor Note 2 The pins of ports 4 5 9 and 12 to 14 of the uPD75P518 cannot be provided with internal pull up or pull down resistors uPD75518 Use
277. pplication main system clock whose frequency is 4 9152 MHz is used When selecting CPU clock for the 75518 set the PCC to 0010B 1 machine cycle 1 63 us at 614 kHz or 0000B 1 machine cycle z 13 us at 76 7 kHz If the PCC is set to 0011B one machine cycle falls short of 0 95 15 the minimum value in the specifications uPD75518 User s Manual 5 71 Chapter 5 Peripheral Hardware Functions Sample program Data is output at 9600 baud starting with LSB CLR1 MBE MOV XA 08H Select output frequency band MOV MODL XA MOV 9600 baud MOV MODH XA MOV XA 10111011B MOV TPGM XA Start timer high output on PPO XA 1FH LSB PPO gt SCKO SOO gt H MOV SIOM XA Transfer start MOV XA DATA Transfer data set MOV 100 5 72 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 7 Serial Interface Channel 0 The uPD75518 has two channels of serial interface Channel 0 and channel 1 Table 5 10 lists the differences between channel 0 and channel 1 Table 5 10 Differences between Channel 0 and Channel 1 Serial transfer mode function Channel 0 Channel 1 3 wire serial I O Clock selection fy 24 1 23 TOUT fx 24 fy 23 flip flop external clock external clock Transfer method Start bit switchable Start bit MSB MSB LSB Transfer end flag Serial transfer end inter Serial transfer end rupt request flag IRQCSIO flag EOT 2 wire serial Available Not availa
278. procedure 1 2 lt 3 gt lt 4 gt uPD75518 User s Manual Advance notice of an order for masked ROM Give advance notice of masked ROM ordering to a special agent or NEC s Sales Department Preparation of media for ordering Use three UV EPROMs having the same contents or an 8 inch IBM format floppy disk in ordering a masked ROM For products with mask options prepare a mask option information sheet describing the mask option data Preparation of the required documents Prepare the following documents when ordering a masked ROM Masked ROM order sheet Masked ROM order check sheet Mask option information sheet for products with mask options Ordering Send a set of the media created in 2 and the documents created in 3 to a special agent or NEC s Sales Department by the date indicated in the advance notice Appendix B Masked ROM Ordering Procedure MEMO B 2 uPD75518 User s Manual Appendix C Revision History The revision history is shown below The chapter numbers in the revised chapter column indicate those of the corresponding edition Edition Major changes Revised chapter Fifth The figure Data Transmission from Slave Device to Master Device Chapter 5 has been modified A caution concerning the reduction of noise during A D conversion has been modified The figure Analog Input Pin Connection has been modified A caution concerning the standby mode has been ad
279. processing 3 machine cycles D Interrupt service routine is executed uPD75518 User s Manual Chapter 6 Interrupt Function 6 8 Effective Use of Interrupts The interrupt function can be used more effectively in the ways described below 1 MBE 0 is set for the interrupt service routine By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying MBE 0 in an interrupt vector table the user can code a program without being concerned with a memory bank If a program must use memory bank 1 for some reason save the memory bank select register using the PUSH BS instruction before selecting memory bank 1 2 Register banks are selected depending on whether the routine is a normal or an interrupt In anormal routine register banks 2 and 3 are used by specifying RBE 1 and RBS 2 In a level one interrupt processing register bank 0 is selected by specifying RBE 0 to save the user the trouble of saving and restoring registers In a level two interrupt processing RBE 1 is specified the register bank is saved using the PUSH BS instruction and register bank 1 is selected 3 Use of a software interrupt for debugging Setting an interrupt request flag using an instruction has the same effect as the occurrence of an interrupt Debug operation for irregular interrupts or concurrently occurring interrupts can be performed more efficiently by setting the interrupt request flags using
280. r MOV1 CY H 0FH 3 CY lt bit at AND1 _ 3 lt CYAP33 MOV1 5 0 P50 lt uPD75518 User s Manual 4 15 Chapter 4 Internal CPU Functions 2 Skip flags SK2 SK1 SKO The skip flags are used to store skip status and are automatically set or reset when the CPU executes an instruction The user cannot directly manipulate these flags by specifying an operand 3 Interrupt status flag IST1 ISTO The interrupt status flag is a 2 bit flag used to store the status of processing being performed Table 4 4 Information Indicated by the Interrupt Status Flag IST1 ISTO Status of processing Processing and interrupt control being performed 0 0 Status 0 Normal program processing is being performed Any interrupts are acceptable 0 1 Status 1 A lower or higher priority interrupt is being serviced Higher priority interrupts are acceptable 1 0 Status 2 A higher priority interrupt is being serviced No interrupts are acceptable 1 1 Not to be set The interrupt priority control circuit Figure 6 1 checks this flag to control multiple interrupts The contents of the IST1 and ISTO are saved as part of the PSW to stack memory if an interrupt is accepted then are automatically set to a one step higher status The RETI instruction restores the contents present before an interrupt occurs The interrupt status flag can be manipulated using a memory manipulation instruction and the
281. r 10 Instruction Set 10 4 12 Interrupt Control Instructions El Function IME IPS 3 lt 1 Sets the interrupt master enable flag bit 3 of the interrupt priority specification register to 1 to enable interrupts Whether to accept an interrupt is controlled with the corresponding interrupt enable flag El IExxx Function lt 1 Ns Noo Sets an interrupt enable flag IExxx to 1 to enable an interrupt xxx BT CSIO TO W TPG 0 1 2 4 DI Function IME IPS 3 lt 0 Resets the interrupt master enable flag bit 3 of the interrupt priority specification register to 0 to disable all interrupts regardless of the states of the interrupt enable flags DI IExxx Function lt 0 xxx Ns Noo Resets an interrupt enable flag to 0 to disable an interrupt xxx BT CSIO TO W TPG 0 1 2 4 10 4 13 1 Instructions IN A PORTn Function A lt PORTn 0 15 Transfers the contents of the port specified by PORTn n 0 15 to the A register Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set A number from 0 to 15 can be specified as n Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred uPD75518 User s Manual 10 51 Chapter 10 10 52 Instruction Set IN XA PORTn Function A lt PORTn X lt 1 4 6 Transfers th
282. r pairs BC DE HL and XA See Section 3 2 A general register area can be addressed and accessed as normal RAM regardless of whether it is used as a register uPD75518 User s Manual Chapter 4 Figure 4 5 General Register Format Internal CPU Functions Address 000H 001H 002H 003H 004H 005H 006H 007H 008H OOFH 010H 017H 018H O1FH Data memory 3 0 Register bank 0 C register B register Same as bank 0 Register bank 1 Same as bank 0 Register bank 2 Same as bank 0 Register bank 3 Y gt lt gt lt gt lt Figure 4 6 Register Pair Format One bank uPD75518 User s Manual Chapter 4 Internal CPU Functions 4 5 Accumulator In the 75518 the A register and XA register pair function as accumulators The A register is mainly used for 4 bit data processing instructions and the XA register pair is mainly used for 8 bit data processing instructions For a bit manipulation instruction the carry flag CY functions as a bit accumulator Figure 4 7 Accumulator Bit accumulator 4 10 uPD75518 User s Manual Chapter 4 Internal CPU Functions 4 6 Stack Pointer SP and Stack Bank Select Register SBS The uPD75518 uses static RAM as stack memory scheme and the 8 bit register holding the start address of the stack area is the stack pointer SP The stack area of the uPD75518 is located at addr
283. r s Manual 5 17 Chapter 5 Peripheral Hardware Functions Figure 5 10 Format of the Pull up Resistor Register Address 7 6 5 4 3 2 1 0 Symbol POGA Port 0 P01 to P03 Port 1 P10 to P13 Port 2 P20 to P23 Port 3 P30 to P33 Port 6 P60 to P63 Port 7 P70 to P73 T seam 0001 0 Do not use pull up resistors 1 Use pull up resistors Caution No pull up resistors are specified for the 75 518 by mask option Figure 5 11 shows the timing at which the use of pull up resistors is specified by setting of the pull up resistor register POGA Figure 5 11 ON Timing of Pull up Resistors by Software 2 machine cycles Instruction Pull up resistor setting instruction execution X After rewriting the contents of POGA to specify the use of pull up resistors execute NOP instructions before I O instructions in consideration of external load capacity 5 18 uPD75518 User s Manual uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Example Specify the use of pull up resistors for PORT1 then input the I O instruction SEL MOV MOV MB15 XA 02H Provide pull up resistors for PORT1 POGA XA 3 Wait for stabilization of the circuit in consideration of external load A PORT1 Chapter 5 Peripheral Hardware Functions 5 1 6 IO Timing of Digital Ports Figure 5 12 shows the timing of data output to an output latch a
284. ransferred to the XA register pair instead of that in page 2 Example The 16 byte data at addresses xxFOH xxFFH in program memory is transferred to addresses 30H 4FH in data memory SUB SEL MBO MOV HL 30H HL lt 30H MOV DE 0FOH DE lt FOH LOOP MOVT XA PCDE XA lt table data MOV HL XA HL XA INCS HL HL HL 2 INCS HL INCS E lt BR LOOP RET ORG xxFOH DB XxH xxH Table data 10 30 uPD75518 User s Manual Chapter 10 Instruction Set MOVT XA PCXA Function XA lt ROM PC14 g XA Transfers the low order four bits of the table data in program memory to the A register and the high order four bits to the X register The table data is addressed by the program counter PC with its low order eight bits PC7 9 exchanged with the contents of the register pair The table address is determined by the contents of the program counter present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction Caution As with MOVT XA PCDE when the instruction is located at address xxFFH table data in the next page is transferred uPD75518 User s Manual 10 31 Chapter 10 10 32 Instruction Set MOVT XA BCDE Function XA lt ROM Bo 9 CDE Transfers the low order four bits of the table data eight bits in p
285. rcles have a Schmitt triggered input Note 2 When the subsystem clock is not used see 5 in Section 5 2 2 2 4 uPD75518 User s Manual Chapter 2 Pin Functions Table 2 2 Non port Pin Functions 2 2 Note Input Also Pin output used Function When reset circuit as type RESET Input System reset input PPO P80 Timer pulse generator pulse output Input E MDO MD3 P30 P33 Provided only in uPD75P518 Input E C Selection of program memory PROM write verify mode IC m Internally connected Connect to Vss keeping the wiring as short as possible Vpp Provided only in uPD75P518 Program voltage application for program memory PROM write verify operation Normally connected to Vpp keeping the wiring as short as possible 12 5 V is applied for PROM write verify operation Positive power supply Vss GND potential Note circuits enclosed in circles have a Schmitt triggered input uPD75518 User s Manual 2 5 Chapter 2 Pin Functions 2 2 Pin Functions 2 2 1 PORTO P10 P13 PORT1 P80 P83 PORTS P150 P153 PORT15 Dual Function Pins Used Also for INT4 SCKO 500 580 and SIO SB1 Dual Function Pins Used Also for INTO INT2 and TIO Dual Function Pins Used Also for PPO SCK1 501 and 51 Dual Function Pins Used Also for AN4 AN7 These are the input pins of the 4 bit input ports Ports 0 1
286. rdware Functions 5 3 2 Basic Interval Timer Mode Register BTM The BTM is a 4 bit register for controlling operation of the basic interval timer A 4 bit memory manipulation instruction is used to set the BTM Bit 3 can be independently set using a bit manipulation instruction When bit 3 is set to 1 the basic interval timer is cleared and the basic interval timer interrupt request flag IRQBT is also cleared to start the basic interval timer A RESET signal clears the interval timer to 0 and the longest interrupt request signal generation interval time is set uPD75518 User s Manual Example 1 The interrupt generation interval is set to 1 95 ms at 4 19 MHz SEL 15 or CLR1 MBE MOV A 1111B MOV BTM 1111B Example 2 The BT and IRQBT are cleared to implement a watchdog timer SEL MB15 or CLR1 MBE BTM 3 Set bit 3 of BTM to 1 Chapter 5 Peripheral Hardware Functions Figure 5 24 Format of the Basic Interval Timer Mode Register Address 3 2 1 0 Symbol F85H BTM3 BTM2 BTM1 BTMO BTM Frequency when fx 6 0 MHz DONOR Interrupt interval time Input clock specification M A wait time for releasing standby 212 220 1 46 kHz 175 ms fx 2 21 ff 11 7 kHz 21 8 ms fx 2 46 9 kHz fx 2 188 kHz Other setting Not to be set Frequency when fx 4 19 MHz Input clock specification interval ime wait time for relea
287. re 3 7 summarizes the I O map of the 75518 The items in the figure have the following meanings Symbol Name representing incorporated hardware which can be coded in the operand field of an instruction R W Indicates whether the hardware allows read write operation R W Both read and write operations possible Read only W Write only Number of manipulatable bits Indicates the number of bits that can be processed at a time in hardware manipulation Bit manipulation is possible in units of the indicated number of bits 1 4 or 8 bits Particular bits can be manipulated For these bits see Remarks Bit manipulation is impossible in units of the indicated number of bits 1 4 or 8 bits Bit manipulation addressing Bit manipulation addressing applicable in hardware bit manipulation uPD75518 User s Manual 3 23 Chapter 3 Data Memory Operations and Memory Figure 3 7 75518 I O Map 1 4 at F80H F83H F84H F85H F86H Register bank select register F82H RBS Hardware name symbol b2 b1 Stack pointer SP Bank select register BS Memory bank select register MBS Stack bank select register SBS Basic interval timer mode register BTM Basic interval timer BT Timer pulse generator TPGM Timer pulse generator modulo register MODL Bit Number of bits that can be manipulated manipulation Bit 0 is always 0
288. re applicable to the ports of the 75518 enabling a wide range of control 8 bit and bit manipulation on a specified bit are enabled as well as 4 bit I O Figure 5 1 Data Memory Address Assigned to Digital I O Ports Address Symbol FFOH PORT 0 FF1H PORT 1 FF2H PORT2 FF3H PORT 3 FF4H PORT 4 FF5H PORT 5 FF6H PORT 6 FF7H PORT 7 FF8H PORT 8 FF9H PORT 9 FFAH PORT 10 FFBH PORT 11 FFCH PORT 12 FFDH PORT 13 FFEH P142 PORT 14 FFFH P152 PORT 15 uPD75518 User s Manual 5 1 Chapter 5 Peripheral Hardware Functions 5 1 1 Types Features and Configurations of Digital I O Ports Table 5 1 lists the types of digital I O ports Figures 5 2 to 5 8 show the configurations of the ports Table 5 1 Types and Features of Digital I O Ports Port name Function Operation and feature Remarks PORTO 4 bit input Allows read and test at any time Also used as INT4 regardless of the operation modes of SCKO 500 5 0 and dual function pins SIO SB1 PORT1 Also used as INTO to INT2 and TIO PORT2 4 bit I O Allows input or output mode setting Also used as in units of 4 bits PTOO PCL and BUZ Allows input or output mode setting in 1 or 4 bit units PORTA Note 4 bit I O Allows input or Ports 4 and 5 The use of pull up N channel output mode setting may paired resistors can be specified PORT5 Note open drain 10 V in units of 4 bits allowing data by mask options
289. ressing Range of Each Address ing Mode 000H 1 07FH OFFH 100H 1FFH 200H 2FFH 300H 3FFH FBOH FBFH FCOH FFOH FFFH Addressing mode Memory bank enable flag General resister Static RAM memory bank 0 mem mem bit MBE 0 HL mem bit DL Stack address ing 4 pmem fmem bit Data area Static RAM memory bank 1 F80H Stack area Data area Static RAM memory bank 2 Data area Static RAM memory bank 3 Not contained Peripheral hardware area memory bank 15 Don t care 54545554 uPD75518 User s Manual Chapter 3 Data Memory Operations and Memory Table 3 1 Addressing Modes Addressing Representation Specified address mode format 1 bit direct mem bit Bit specified by bit at the address specified by MB addressing and mem In this case When MBE 0 and mem 00H 7FH MB 0 80 15 When MBE 1 MBS 4 bit direct mem Address specified by MB and mem In this case addressing When MBE 0 and mem 00H 7FH MB 0 80 15 When MBE 1 MBS 8 bit direct Address specified by MB and mem mem even address addressing In this case When MBE 0 and 00 7 0
290. rogram memory to the A register and the high order four bits to the X register The table data is addressed by the low order three bits of the B register and the contents of the C D and E registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction MOVT XA BCXA Function XA lt ROM Bo 9 CXA Transfers the low order four bits of the table data eight bits in program memory to the A register and the high order four bits to the X register The table data is addressed by the low order three bits of the B register and the contents of the C X and A registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction uPD75518 User s Manual Chapter 10 Instruction Set 10 4 3 Bit Transfer Instructions MOV1 CY fmem bit MOV1 CY pmem L MOV1 CY H mem bit Function CY lt bit specified in operand Transfers the data memory bit specified by bit manipulation addressing fmem bit pnem L H mem bit to the carry flag CY MOV1 fmem bit CY MOV1 pmem L CY MOV1 H mem bit CY Function bit specified in operand CY Transfers the carry flag bit to the data memory bit specified by bit manipulation addressing fmem bit pnem L H mem bit Example The fl
291. ructions and number system conversion instructions for increased program efficiency 6 Table reference instructions suitable for successive references 7 1 byte relative branch instructions 8 NEC standard mnemonics designed for clarity and readability See Chapter 3 for the addressing modes applicable to data memory manipulation uPD75518 User s Manual 10 1 Chapter 10 Instruction Set 10 1 Unique Instructions This section outlines the unique instructions among the uPD75518 instruction set 10 1 1 GETI Instruction The GETI instruction converts any of the following instructions to a 1 byte instruction a Subroutine call instruction for the entire space b Branch instruction for the entire space c Arbitrary 2 byte instruction operating with two machine cycles Except the BRCB and CALLF instructions d A combination of two 1 byte instructions The GETI instruction references the table located at addresses 0020H to 007FH in program memory and executes referenced 2 byte data as an instruction of a b c or d above This means that 48 instructions consisting of a to d can be converted to 1 byte instructions Thus the GETI instruction can be used to convert frequently used instructions of a to d to 1 byte instructions to reduce the number of program bytes significantly Cautions 1 A 2 byte instruction which can be referenced by a GETI instruction must be a two machine cycle instruction Except the BR
292. ry manipulation instruction but cannot be written to The modulo register TMODO is an 8 bit register for determining the count of TO A value can be set in with an 8 bit memory manipulation instruction but cannot be read A RESET signal initializes TMODO to FFH The comparator compares the contents of TO with the contents of TMODO If they match the comparator generates a match signal and sets the interrupt request flag IRQTO Figure 5 28 shows the timing of count operation Figure 5 28 Timing of Count Operation Count pulse CP Modulo register TMODO Count register TO TOUT flip flop Reset _ 5 n Match IRQTO is set IRQTO is set A Timer start request TMO 3 1 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 5 3 Timer Event Counter Mode Register TMO The timer event counter mode register TMO is an 8 bit register for controlling the timer event counter Figure 5 29 shows its format An 8 bit memory manipulation instruction is used to set the timer event counter mode register Bit 3 is the timer start bit and can be set independently of the other bits Bit 3 is automatically reset to 0 when the timer starts operation A RESET signal clears all the bits of the timer mode register to 0 uPD75518 User s Manual Example 1 The timer is started in the interval timer mode with C
293. ry is described below high speed write is possible 1 10 11 12 13 14 15 16 Pull low all unused pins to Vss by means of resistors Bring X1 to low level Apply 5 V to Vpp and to Vpp Wait 10 us Select program memory address clear mode Apply 6 V to Vpp and 12 5 V to Vpp Select program inhibit mode Select write mode for 1 ms duration and write data Select program inhibit mode Select verify mode If write is successful proceed to step 10 If write fails repeat steps 7 to 9 Perform additional write for Number of repetitions of steps 7 to 9 x 1 ms duration Select program inhibit mode Increment the program memory address by inputting four pulses on the X1 pin Repeat steps 7 to 12 until the last address is reached Select program memory address clear mode Apply 5 V to Vpp and to Vpp Turn the power off uPD75518 User s Manual Chapter 9 Writing to and Verifying Program Memory PROM The timing for steps 2 to 12 is shown below X1 P40 P43 P50 P53 MDO P30 MD1 P31 MD2 P32 MD3 P33 Repeat x times Address increment Write Verify Additional write Data input Data outpu Data input uPD75518 User s Manual 9 5 Chapter 9 Writing to and Verifying Program Memory PROM 9 3 Reading the Program Memory The procedure for reading the contents of program memory is described below The read is perfor
294. s 1 So detect selection nonselection state by slave address when WUP is set to 1 b When determining whether a slave is selected without using an interrupt when WUP 0 do not use the address match detection method Instead use transfer of commands set in advance in a program c When WUP is set to 1 during BUSY signal output BUSY is not released In the SBI mode after release of BUSY is directed the BUSY signal is output until the next falling edge of the serial clock SCKO appears Before setting WUP to 1 be sure to confirm that the 580 or 581 pin is high after releasing BUSY uPD75518 User s Manual 5 135 Chapter 5 Peripheral Hardware Functions 12 SBI mode This section describes an example of application which performs serial data communication in the SBI mode In the example the 75518 can be used as either the master CPU or a slave CPU on the serial bus The master can be switched to another CPU with a command a Serial bus configuration In the serial bus configuration used for the example of this section auPD75518 is connected to the bus line as a device on the serial bus Two pins on the uPD75518 are used serial data bus 580 502 500 and serial clock SCKO P01 Figure 5 72 shows an example of the serial bus configuration Figure 5 72 Example of Serial Bus Configuration Master CPU 75518 SBO or SB1 SCKO Slave CPU 075518 580 581 SCKO
295. s not to be used for writing into or verifying the program memory are handled as follows Pins other than XT2 Connected to the Vss via the pull down resistor XT2 Open uPD75518 User s Manual 9 1 Chapter 9 Writing to and Verifying Program Memory PROM Cautions 2 For the 75 518 which has an erasure window cover film must be put on the window to shield the light except when the contents of the EPROM are to be erased 3 The uPD75P518GF with a one time PROM does have an erasure window so the contents of the program memory can not be erased with ultraviolet radiation 9 2 uPD75518 User s Manual Chapter 9 Writing to and Verifying Program Memory PROM 9 1 Operating Modes when Writing to and Verifying the Program Memory If 6 V is applied to the Vpp pin and 12 5 V is applied to the Vpp pin the uPD75P518 enters program memory write verify mode The specific operating mode is then selected by inputting signals to the MDO through pins as listed in Table 9 2 Table 9 2 Operating Modes Operating mode specification Operating mode Vpp Vpp MDO MD2 6 12 5 H L H L Program memory address clear mode L H H H Write mode L L H H Verify mode H X H H Program inhibit mode Remark X indicates L or H uPD75518 User s Manual Chapter 9 Writing to and Verifying Program Memory PROM 9 2 Writing to the Program Memory The procedure for writing to program memo
296. s of the XA register pair together with the carry flag from the contents of register pair 1 HL DE BC XA HL DE BC then sets the result in register pair 1 If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset AND A n4 Function A lt AAn4 n4 13 0 0 FH ANDs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The high order two bits of an accumulator are set to O AND A 0011B AND A HL Function A A HL ANDs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register AND XA rp Function XA XA rp ANDs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC then sets the result in the XA register pair AND rp 1 XA Function rp 1 lt rp 1AXA ANDs the contents of register pair rp 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in the specified register pair OR A n4 Function A lt Avn4 4 13 0 ORs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The low order three bits of an accumulator are set to 1 OR A 0111B uPD75518 User s Manual 10 37 Chapter 10
297. s output on the serial output SOO or serial data bus SBO or SB1 In receive operation data is read from the serial input SIO or SBO or SB1 into SIOO Data can be read from or written to SIOO by using an 8 bit manipulation instruction When the RESET signal is entered during operation the value of SIOO is undefined When the RESET signal is entered in the standby mode the value of SIOO is preserved Shift operation is stopped after 8 bit send or receive operation is completed uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Figure 5 43 Peripheral Hardware of Shift Register 0 N ch open drain output RELT Internal bus comparator CMDT Shift register 0 500 latch CSIMO Shift clock BUSY ACK The timing for reading SIOO and start of serial transfer writing to SIOO is as follows When the serial interface operation enable disable bit CSIEO 1 However the case where CSIEO is set to 1 after data is written to the shift register is excluded When the serial clock is masked after 8 bit serial transfer SCKO is high When reading from or writing to SIOO make sure that SCKO is high In the two wire serial I O mode and SBI mode the pins specified for the data bus are used for both input and output Because the configuration of output pins is N ch open drain write FFH in SIOO for devices that are to receive data uPD75518 User s Manual Ch
298. sabled the interrupt request flag is held When the interrupt is enabled by the EI instruction the INTO interrupt service program starts Same as 1 When the held INTCSIO flag is enabled the INTCSIO interrupt service program starts Chapter 6 Interrupt Function 5 Execution of held interrupts when two low order interrupts are requested concurrently lt Main program gt IETO IEO El INTO service program lt i gt INTO INTTO 2 RETI INTTO service routine RETI 1 When low order interrupts INTO and INTTO occur concurrently during execution of the same instruction INTO with a higher priority is executed first INTTO is held 2 When the INTO interrupt service program has been executed the RETI instruction is executed to start the interrupt service program for INTTO which has been held 6 28 uPD75518 User s Manual Chapter 6 Interrupt Function 6 Execution of held interrupts when an interrupt request occurs dur ing interrupt processing in the same condition as in 3 above lt Main program gt Reset IEBT IETO El IECSIO INTBT service program MOV A 9 MOV IPS A PUSH rp POP rp INTTO 3 RETI INTCSIO service program INTBT lt 4 gt RETI lt INTTO service program gt RETI uPD75518 User s Manual 1 2 lt 3 gt lt 4 gt When requests for high order interrupt INTBT and low
299. se Removed as noise Remark or 64 fx uPD75518 User s Manual Chapter 6 Interrupt Function Figure 6 5 Format of Edge Detection Mode Registers a INTO edge detection mode register IMO Address Symbol 3 2 1 0 IM03 EN 01 00 FB4H IMO Detection edge specification ESEJ Specifies rising edge ESES Specifies falling edge 1 0 Specifies both rising and falling edges 1 1 Ignored interrupt request flag is not set Sampling clock fx 64 at 10 7us 6 0 MHz or 15 3 4 19 MHz b INT1 edge detection mode register IM1 IM1 Specifies rising edge Specifies falling edge FB5H c INT2 edge detection mode register IM2 FB6H IM21 IM20 IM2 IM21 IM20 INT2 interrupt source Interrupt input pin Specifies rising edge of INT2 pin input INT2 1 4 Specifies falling edge of any of KRx pin KR2 6 inputs Caution is shown on the next page 6 10 uPD75518 User s Manual Chapter 6 Interrupt Function Caution Changing the edge detection mode register may set an interrupt request flag So disable the interrupts before changing the edge detection mode register Then clear the interrupt request flag with a CLR1 instruction and enable the interrupts When fy 64 is selected as a sampling clock pulse in changing IMO wait for 16 machine cycles after changing the mode r
300. se the serial interface channel 1 in the three wire serial mode with an example Usually communication using the serial interface is performed in the following steps lt 1 gt A transfer mode is set Data is set in CSIM1 2 Data is written to SIO1 then start of transfer is directed MOV SIO1 XA or XCH XA SIO1 in this case transfer is automatically directed Example Data is transferred starting with the MSB on a transfer clock of 262 kHz in 4 19 MHz operation master operation Sample program CLR1 MBE MOV 810000010 MOV CSIM1 XA Set transfer mode MOV XA TDATA TDATA is transfer data storage address MOV SIO1 XA Set transfer data and start transfer Caution A second or subsequent transfer can be started by setting data in SIO1 MOV SIO1 XA or XCH XA SIO1 075518 uPD7225G LCD controller driver etc SCK1 SCK SO1 SI In this case the 511 pin on the 4PD75518 can be used as an input uPD75518 User s Manual 5 151 Chapter 5 Peripheral Hardware Functions 5 9 A D Converter The pPD75518 contains an 8 bit analog digital A D converter that has eight analog input channels to 7 The A D converter employs the successive approximation method 5 9 1 Configuration of the A D Converter Figure 5 85 shows the configuration of the A D converter Figure 5 85 Block Diagram of the A D Converter Internal bus 9 ADM6 ADM5 ADM4
301. sequentially To check the function of an instruction in detail when the reader knows its mnemonics See the instruction index in Appendix D To refresh his or her memory of the function of an instruction when the reader does not know its mnemonic but almost understand the function See Section 10 2 to find the mnemonic of the instruction then see Section 10 4 to confirm its function To check the electrical characteristics of the 1 PD75518 Refer to the separate data sheet Unless there is a difference in function between the uPD75517 and uPD75518 or uPD75P518 only the uPD75518 is described in this manual The user of the 75517 or uPD75P518 should read uPD75518 as uPD75517 or uPD75P518 In descriptions common to the one time PROM product and EPROM product the term PROM is used to represent both products The uPD75P518K is not intended for use in mass produced products it does not offer a sufficiently high level of reliability for such applications The use of theuPD75P518K should be restricted to functional evaluation in experimental or trial manufacture Notation Data bit significance Active low Memory map address Note Caution Remark Numeric value Higher order bits on the left side Lower order bits on the right side xxx Pin and signal names are overscored Low order address on the upper side High order address on the lower side Explanation of an indicated part of text
302. sing standby 6 21 220 1 02 kHz 250 1 29 8 18 kHz 110 fx 2 2 fx 32 768 kHz 7 82 ms ay fx 2 2 3 131 kHz 1 95 ms Other Basic interval timer start control bit When 1 is written to this bit the basic interval timer operation starts the counter and the interrupt request flag are cleared When the operation starts this bit is automatically reset to 0 5 40 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 3 3 Operation of the Basic Interval Timer The basic interval timer BT is always incremented by the clock supplied from the clock generator and when it overflows the interrupt request flag IRQBT is set The count operation of the BT cannot be stopped One of four interrupt generation intervals can be selected by setting the BTM See Figure 5 24 The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of the BTM to 1 instruction for starting as an interval timer The count in the BT can be read using an 8 bit manipulation instruction Writing to the BT is inhibited Caution When reading the count from the BT execute a read instruction twice so that unstable data being counted will not be read If two read values are reasonable use the second one as the result If two read values are far apart from each other retry all over again Example The count in the BT is read SET1 MBE SEL MB15 MOV HL BT Set the address of BT in
303. ssive approximation SA register The SA register is an 8 bit register to hold the result of A D conversion SA is a read only register from which data is read with an 8 bit manipulation instruction No data can be bit manipulated in SA A RESET signal makes SA undefined SA is mapped to address FDAH Caution If A D conversion is started with bit 3 SOC of the ADM register set to 1 the result of conversion in SA is destroyed and SA becomes unpredictable until a new conversion result is stored uPD75518 User s Manual 5 155 Chapter 5 Peripheral Hardware Functions 5 9 2 A D Converter Operation Analog input signals subject to A D conversion are specified with bits 6 5 and 4 of the A D conversion mode register ADM6 ADM5 and ADM4 A D conversion is started by setting bit 3 SOC of ADM to 1 After that SOC is automatically cleared to 0 A D conversion is performed by hardware using the successive approximation method The resultant 8 bit data is loaded into the SA register Upon completion of A D conversion ADM bit 2 EOC is set to 1 Figure 5 87 shows the timing chart of A D conversion Select analog input channels and comparator bias voltage Direct start of A D conversion Wait 25 s 3 81 us at fx 4 19 MHz Conversion completed Yes Read result of A D conversion Set ADM6 ADM5 and ADM1 Can be set concurrently Set SOC Wait for EO
304. t the following processing is performed If the instruction immediately preceding the GETI instruction also has the string effect in the same group the execution of the GETI instruction cancels the string effect and the referenced instruction is not skipped If the instruction immediately following the GETI instruction also has the string effect of the same group the string effect of the referenced instruction remains valid and the next instruction is skipped uPD75518 User s Manual 10 55 Chapter 10 Instruction Set Example MOV HL amp 00H MOV XA FFH are replaced with GETI instructions CALL SUB1 SUB2 ORG 20H HLOO MOV HL 00H XAFF MOV XA FFH CSUB1 TCALL 5081 BSUB2 TBR SUB2 TE HLOO MOV HL 00H d BSUB2 BR SUB2 a CSUB1 CALL 5081 GETI XAFF XA FFH 10 56 uPD75518 User s Manual Appendix A Development Tools The following tools are available for the development of uPD75518 based systems Language processor RA75X Host machine Part number relocatable OS Distribution media product name assembler PC 9800 series MS DOSTM 3 5 inch 2HD uS5A13RA75X Ver 3 30 1 to 5 25 inch 2HD uS5A10RA75X L Ver 5 00A Note IBM PC ATTM PC DOS 5 25 inch 2HC uS7B10RA75X Ver 3 1 Remark The RA75X relocatable assembler can run only on the host machine under the OS mentioned above uPD75518 User s Manual A 1 Appendix A Development Tools Tools for writing into
305. t manipulations to be performed very easily by sequentially changing address and bit specifications So the buffer is useful in processing long data bit by bit This data memory consists of 16 bits and allows pmem L addressing with a bit manipulation instruction This addressing uses the L register for indirect bit specification In this case only by incrementing or decrementing the L register in a program loop the bit to be manipulated can be sequentially shifted for continued processing Figure 5 91 Format of the Bit Sequential Buffer Address Bit Symbol L register FC3H FC2H FC1H FCOH F L C L B L 8 L 7 L 4 L 3 L 0 5 162 Remarks 1 With pmem L addressing bit specification is shifted according to the L register 2 With pmem L addressing BSB can be manipulated at any time regardless of MBE MBS specification Data can also be manipulated by direct addressing The buffer can be used for applications such as continuous 1 bit data input or output operations by combining direct 1 bit 4 bit and 8 bit addressing with pmem L addressing In 8 bit manipulation the higher eight bits or lower eight bits are manipulated by specifying BSBO or BSB2 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 10 1 Applications of the Bit Sequential Buffer 1 16 bit data in certain data memory areas BUFF1 and BUFF2 in uPD75518 User s Manual memory bank 0 is output serially from bit 0 in port 3
306. t register on the rising edge of SCKO When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSIO Figure 5 45 Timing of Three Wire Serial 1 Mode SCKO SIO 500 IRQCSIO A Execution of instruction that writes data 10 5100 Transfer start request 1 QD 2 3 4 5 6 7 8 Xm XC Xo Kee Xe Yon Completion of transfer Transfer operation is started in phase with falling edge of SCKO uPD75518 User s Manual The SOO pin becomes a CMOS output and outputs the state of the SOO latch So the output state of the SOO pin can be manipulated by setting the RELT bit and CMDT bit However this manipulation must not be performed during serial transfer The output level of the pin can be controlled by manipulating the PO1 output latch in the output mode internal system clock mode See Section 5 7 8 Chapter 5 Peripheral Hardware Functions 3 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register 0 CSIMO The serial clock can be selected out of the foll owing four clocks Table 5 11 Serial Clock Selection and Application the Three Wire Serial I O Mode Mode register Serial clock Timing for shift register R W and Application CSIMO CSIMO Source Masking of start of serial transfer 1 0 serial clock 0 0 External Automatically lt 1 gt
307. t ripple component frequency As shown in Figure 5 38 the pulse signal output on the PPO is inverted by an external transistor The period of a low output on the PPO corresponds to the value written in the timer pulse generator modulo register The tuning voltage is preset with the AFC and horizontal synchronizing signals The resultant tuning data is written to the non volatile memory uPD6252 uPD75518 User s Manual 5 69 Chapter 5 Peripheral Hardware Functions 3 Musical notes are output on the PPO pin A square wave is output on the PPO pin at a given frequency The frequency of clock oscillation is set to 4 19 MHz Although various frequencies from 64 Hz to 131 kHz are possible by setting the timer pulse generator modulo register the resolution is restricted See Table 5 7 This means that generated notes have errors See Table 5 9 According to the table to generate a one octave higher tone the MODL value is doubled As shown in Table 5 7 to increase the resolution for fine tuning the value N must be as large as possible In Table 5 9 a large value is set in MODL to obtain a large value for N Sample program Tone la Output 440 Hz CLR1 MOV MOV MOV MOV MOV MOV MBE XA 10H Select output frequency MODL XA XA 94H 440Hz MODH XA XA 10101011B TPGM XA Start note output Table 5 9 Generation of Notes Using the Timer Pulse Generator Note La Ti Do Re Fa So A At
308. t saved restored Remark Data marked with is undefined uPD75518 User s Manual Chapter 4 Internal CPU Functions 4 7 Program Status Word PSW 8 Bits The program status word PSW consists of various flags closely associated with processor operations The PSW is mapped to addresses FBOH and FB1H in data memory space Four bits at address FBOH can be manipulated with a memory manipulation instruction Address FB1H cannot be manipulated with a normal data memory manipulation instruction Figure 4 11 Program Status Word Format Address FB1H FBOH gt Symbol Cannot be manipulated Can be manipulated Can be manipulated by an instruction specifically provided for controlling this flag All or some of PSW bits are saved to and restored from stack memory when a subroutine call instruction or a hardware interrupt is executed PSW flags to be manipulated at the time of a stack operation are listed in Table 4 2 Table 4 2 PSW Flags Saved Restored in Stack Operation Saved restored flag Save When a CALL CALLA or CALLF MBE and RBE are saved instruction is executed When a hardware interrupt occurs All PSW bits are saved Restore When a RET or RETS instruction is MBE and RBE are restored executed When a RETI instruction is executed All PSW bits are restored uPD75518 User s Manual Chapter 4 Internal CPU Functions 1 Carry flag CY The carry flag is a 1 bit flag used to store information ab
309. ted In the SBI mode When WUP7 Note 0 an interrupt request is issued whenever eight serial clocks are counted When WUP 1 an interrupt request is issued when values of SVA and SIOO match after an address is received WUP Wake up function specification bit bit 5 of CSIMO 9 Serial clock control circuit The serial clock control circuit controls the serial clock to be supplied to the shift register or controls the clock to be output to the SCKO pin when the internal system clock is used 10 11 uPD75518 User s Manual Busy acknowledge output circuit and bus release command ac knowledge detection circuit The busy acknowledge output circuit and bus release command acknowledge detection circuit output and detect control signals generated in the SBI mode These circuits do not operate in the three wire or two wire serial I O mode P01 output latch The P01 output latch generates serial clock by software after the eighth serial clock has been output When the RESET signal is entered this latch is set to 1 To select the internal system clock as the serial clock set the P01 output latch to 1 Chapter 5 Peripheral Hardware Functions 5 7 3 Register Functions 1 Serial operation mode register 0 CSIMO Figure 5 41 shows the format of serial operation mode register 0 51 0 CSIMO is an 8 bit register which specifies a serial interface channel 0 operation mode serial clock wake up function and so forth
310. ter n 0 Once the timer is set the interrupt request signal IRQTO is generated at set time intervals Table 5 6 indicates the resolution and maximum set time set when FFH is set in the modulo register of the timer event counter for each count pulse signal Example time interval of 30 ms is produced fx 4 194304 MHz In this case the mode with a maximum set time of 62 5 ms is used 30 ms 244 us 123 7BH Accordingly 7AH is set in the modulo register SEL MB15 MOV 7 MOV TMODO XA uPD75518 User s Manual 5 53 Chapter 5 Peripheral Hardware Functions Table 5 6 Resolution and Maximum Set Time When fx 6 0 MHz Mode register TMO6 05 04 When fy 4 19 MHz Mode register 06 05 0 0 04 Timer channel 0 Resolution Maximum set time 171 us 43 7 ms 42 7 us 10 9 ms 10 7 us 2 73 ms 2 67 us 683 us Timer channel 0 Resolution Maximum set time 244 us 62 5 ms 61 1 us 15 6 ms 15 3 us 3 91 ms 3 81 us 977 us uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 5 7 Notes on Timer Event Counter Applications 1 Time error at the start of the timer A maximum error of one count pulse CP cycle from a value calculated according to Section 5 5 6 occurs in a time period from the start of the timer 3 1 to the generation of a match signal This is because the count register is cleared not in phase with the CP as shown in Figure 5 32
311. th the contents of the XA register pair then sets the result in register pair rp 1 uPD75518 User s Manual Chapter 10 Instruction Set 10 4 5 Accumulator Manipulation Instructions RORC A Function CY lt Ao An 1 lt An lt n 1 3 Rotates the contents of the A register 4 bit accumulator through the carry flag one bit position to the right A CY 3 2 1 0 Before gt execution ur Ar RORC A After 1 olo 1lo execution NOT A Function A lt Obtains the one s complement of the A register 4 bit accumulator that is inverts each bit of the A register 10 4 6 Increment Decrement Instructions INCS reg Function reg reg 1 Skip if reg 0 Increments the contents of register reg X A H L D E B C If the result of increment produces reg 0 the immediately following instruction is skipped INCS rp1 Function lt 1 1 Skip if rp1 00H Increments the contents of register pair 1 HL DE BC If the result of increment produces rp1 00H the immediately following instruction is skipped INCS HL Function HL lt HL 1 Skip if HL 0 Increments the data at the data memory location addressed by the HL register pair the result of increment produces data that is 0 the immediately following instruction is skipped uPD75518 User s Manual 10 39 Chapter 10 Instruction Set I
312. the System Clock and CPU Clock Seting before Setting after switching PCC1 SCCO PCC1 PCCO 0 1 1 1 x x 1 machine 1 machine 1 machine fx 64fxt machine cycle cycle cycle cycles 3 machine cycles 4 machine 4 machine 4 machine Not to be set cycles cycles cycles 8 machine 8 machine 8 machine fx 8fxt machine cycles cycles cycles cycles 23 machine cycles 16 machine 16 machine 16 machine fx 4fxt machine cycles cycles cycles cycles 46 machine cycles 1 machine Not to be 1 machine 1 machine cycle set cycle cycle Remarks 1 Time indicated in parentheses is required when fy 6 0 MHz and fxr 32 768 kHz 2 x Don t care 3 CPU clock is supplied to the CPU The reciprocal of this frequency is a minimum instruction time defined as one machine cycle in this manual 5 32 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Cautions 1 When the four bits of the PCC are set to 0001B fy 16 do not set SCC 0 to 1 Before switching the main system clock to the subsystem clock be sure to manipulate the PCC bits so other than 0001B is set When the system operates on the subsystem clock the PCC bits must also be other than 0001B 2 The fluctuation of the ambient temperature around oscillator and the performance of a load capacity change fy and fxr In particular when fy is higher than the nominal value or is lower than the
313. the main system clock PCC 0 SCC 0 When the main system clock is selected the PCC can be set to select one of four CPU clocks 0 67 1 33 2 67 us and 10 7 us At 6 0 MHz Note 2 When the main system clock is selected the two standby modes STOP mode and HALT mode are available The SCC can be setto select the subsystem clock for very low speed low current operation 122 us At 32 768 kHz The value in the PCC does not affect the CPU clock When the subsystem clock is selected main system clock generation can be stopped with the SCC In addition the HALT mode can be used but the STOP mode cannot be used Subsystem clock generation cannot be stopped The clock to be supplied to peripheral hardware is produced by frequency dividing the main system clock signal The subsystem clock can directly be supplied only to the clock timer This enables the clock function and the buzzer output function which operate on the clock signal from the clock timer to continue operating even in the standby state When the subsystem clock is selected as the count clock of the clock timer the clock timer can continue to operate normally However other hardware cannot be used when the main system clock is stopped because they operate with the main system clock At 4 19 MHz 15 3 us At 4 19 MHz 0 95 us 1 91 us 3 82 us an 15 3 us Chapter 5 Peripheral Hardware Functions 1 Processor clock control register PCC The
314. the operation of the port and pins depends on the I O mode setting Table 5 3 This is because data taken in on the internal bus is the data input from the pins in the input mode or the output latch data in the output mode as obvious from the configurations of I O ports 1 Operation when the input mode is set 2 uPD75518 User s Manual Data from each pin is taken in when a test instruction such as the SKT instruction a bit input instruction by the MOV1 instruction or an instruction for taking in port data on the internal bus in units of four or eight bits such as an IN OUT arithmetic logical or comparison instruction is executed When an instruction the OUT or MOV instruction is executed to transfer the contents of the accumulator to a port in units of four or eight bits the data of the accumulator is latched in the output latch with the output buffers kept off When the XCH instruction is executed the data on each pin is loaded into the accumulator and the data in the accumulator is latched in the output latch with the output buffers kept off When the INCS instruction is executed the 4 bit data existing on the pins plus 1 is latched in the output latch with the output buffers kept off When an instruction such as the SET1 CLR1 MOV1 or SKTCLR instruction is executed to rewrite a data memory bit the output latch data of the specified bit can be rewritten according to the instruction butthe states of the other output
315. tion PCC 3 lt 1 Sets the STOP mode This instruction is used to set bit 3 of the processor clock control register Caution The instruction immediately following a STOP instruction must be a NOP instruction NOP Function Uses one machine cycle without performing an action 10 4 15 Special Instructions SEL RBn Function RBS lt N4 9 0103 Sets the 2 bit immediate data n in the register bank select register SEL MBn Function MBS lt n 0 1 2 3 15 Transfers the 4 bit immediate data n to the memory bank select register uPD75518 User s Manual 10 53 Chapter 10 Instruction Set GETI taddr Function taddr 5 0 0 20H 7FH When a table defined by the TBR instruction is referenced Note 13 0 lt taddr 5 9 taddr 1 PC44 lt 0 When a table defined by the TCALL instruction is referenced Note SP 2 x x MBE RBE SP 3 lt PCz 4 SP 4 lt PC3 9 5 5 lt x 14 12 SP 6 lt 11 8 PC44 lt 0 PC45 9 lt taddr s o taddr 1 SP SP 6 Whenatable defined by an instruction other than the TBR or TCALL instruction is referenced An instruction using taddr taddr 1 as its operation code is executed Note Only addresses 0000H to 3FFFH can be specified by the TBR and TCALL instructions The 2 byte data at the program memory addresses specified by taddr and taddr 1 is referenced and executed as an instruction Addresses 0020H
316. tions can be used Table 5 2 lists the instructions that are particularly useful for I O pin manipulation and their application ranges 1 Bit manipulation instructions For digital I O ports PORTO to PORT15 specific address bit direct addressing fmem bit and specific address bit register indirect addressing pmem L can be used This means that bit manipulation can be freely performed for these ports regardless of MBE and MBS settings Example P50 is ORed with P81 then the result is output to P61 MOV1 CY PORT5 0 CY lt P50 OR1 CY PORTS8 1 CY lt CYVP81 MOV1 PORT6 1 CY P61 lt CY 2 4 bit manipulation instructions All 4 bit memory manipulation instructions including the IN OUT MOV XCH ADDS and INCS instructions can be used However before these instructions can be executed memory bank 15 must be selected Example 1 The contents of the accumulator are output to port 3 SEL MB15 or CLR1 MBE OUT PORT3 A Example 2 The value of the accumulator is added to the data output on port 5 then the result is output SET1 MBE SEL MB15 MOV HL PORT5 ADDS A HL lt 5 MOV HL A PORT5 lt 5 12 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Example 3 Whether the data on port 4 is greater than the value of the accumulator is tested SET1 MBE SEL MB15 MOV HL PORT4 SUBS A HL lt PORTA BR NO NO YES 3 8 bit manipulation instructions u
317. to 007FH are used as a reference table area Data must be written to this area beforehand When a 1 byte instruction or 2 byte instruction is written its mnemonic can be used directly For a 3 byte call instruction or 3 byte branch instruction an assembler pseudo instruction TCALL TBR is used Only an even address can be specified as taddr 10 54 uPD75518 User s Manual Chapter 10 Instruction Set Caution All 2 byte instructions except the BRCB instruction and CALLF instruction set in the reference table must be 2 machine cycle instructions Pairs of 1 byte instructions can be set as indicated in the table below First byte instruction Second byte instruction INCS L MOV A HL L DECS L MOV HL A INCS H XCH A HL L DECS H INCS HL INCS E MOV A DE L DECS E INCS D XCH A DE L DECS D INCS DE MOV A DL INCS L L DECS L XCH A DL INCS D L DECS D The PC is not incremented during execution of a GETI instruction so that after a reference instruction is executed execution is resumed starting at the address immediately after the GETI instruction If the instruction immediately preceding a GETI instruction has the skip function the GETI instruction is skipped as with other 1 byte instructions If an instruction referenced with a GETI instruction has the skip function the instruction immediately following the GETI instruction is skipped If a GETI instruction references an instruction having a string effec
318. to 1 The internal serial clock is not operating after 8 bit serial transfer or SCKO is high Cautions 1 Transfer cannot be started by setting CSIEO to 1 after writing data to the shift register 2 The N ch transistor needs to be turned off when data is received So must be written to 5100 beforehand However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off So need not be written to 5100 beforehand for reception 3 If data is written to SIOO when the slave is busy the data is not lost Transfer is started when the busy state is released and input to SBO or SB1 goes high When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSIO Example When RAM data specified by the HL register is transferred to SIOO from which data is loaded into the accumulator at the same time and serial transfer is started MOV XA HL Extracts transmit data from RAM SEL MB15 or CLR1 MBE XA SIOO Exchanges transmit data with receive data and starts transfer 5 134 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 11 Notes on the SBI mode a Whether a slave is selected is determined by detecting a match for a slave address received after bus release in the state of RELD 1 An address match is detected usually using an address match interrupt IRQCSIO generated when WUP i
319. ts the ACK signal as a dummy Figure 5 80 Master and Slave Operation in Case of Error Processing by slave SBO Erroneous data ACK Processing by master r Reception is completed Error is assumed and processing is halted ACK wait time ACK from slave is checked gt Transfer is completed Error is assumed ACK check is started ACK is output 5 142 The following errors may occur Error that may occur on the slave side 1 Invalid command transfer format 2 Reception of an undefined command 3 Insufficient number of transfer data bytes for a READ command 4 Insufficient area to contain data for a WRITE command b Change in data during transmission of a READ STATUS or CHGMST command If any of the above types of errors occurs ACK is not returned Error that may occur on the master side If data transmitted with a WRITE command changes during transmission the master transmits a STOP command to the slave uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 7 8 Manipulation of SCKO Pin Output The SCKO P01 pin has a built in output latch so that this pin allows static output by software manipulation in addition to normal serial clock output The number of SCKO pulses can be software set arbitrarily by manipulating the output latch The 500 580 581 pin is controlled by manipulating the and bits of SBIC The procedure
320. ts used in the two wire serial mode uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions Address 7 6 5 4 3 2 1 0 Symbol FEOH CSIEO CSIMO4 CSIMO3 CSIMO2 CSIMO Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark Read only W Write only Serial clock selection bit W CSIMO1 CSIMOO Serial clock SCKO pin mode 0 0 External clock applied to SCKO pin Input 0 1 Timer event counter output TO Output 1 0 fy 26 65 5 kHz or 93 8 kHz Note 1 1 Note The values at 4 19 MHz and 6 0 MHz are indicated in parentheses Serial interface operation mode selection bit W CSIM04 CSIMO3 CSIMO2 Shift register sequence 00 pin function SIO pin function 0 1 1 31007 lt gt XA 5 2 N ch input Transfer starting with MSB open drain I O 1 P02 input 5 1 N ch open drain Wake up function specification bit W 0 Sets IRQCSIO each time serial transfer is completed uPD75518 User s Manual 5 101 Chapter 5 Peripheral Hardware Functions Signal from address comparator R Condition for being cleared 0 Condition for being set COI 1 When the slave address regist
321. uPD75518 User s Manual 5 157 Chapter 5 Peripheral Hardware Functions Figure 5 88 shows the relationship between analog input voltages and 8 bit digital data obtained by A D conversion Figure 5 88 Relationship Ideal between Analog Input Voltages and Results of A D Conversion FFH 9 FDH 5 5 2 9 a 4 c 4 8 T 4 03H 8 E 02H 01H 00H 00 1 2 3 253 254 255 256 256 256 256 256 256 Analog input voltage V 5 158 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 9 3 Notes on the Standby Mode The A D converter operates with the main system clock So its operation stops in the STOP mode or when the subsystem clock is used in the HALT mode A current flows through the AVngr pin even when the A D converter is stopped so that the current must be stopped to reduce overall system power consumption Since pin P113 has a higher drive capability than the other ports it can supply voltage directly to the pin see Figure 5 89 In this case however the actual AVgpgr voltage does not provide precision This means that the value resulting from conversion does not provide precision and can be used only for relative comparison In the standby mode outputting a low on P113 can reduce power consumption The P113 pin of the peripheral hardware emulator uPD75390 used for emulation has the same drive capabilit
322. ulse from being output by unstable modulo latch data being rewritten in the 75518 correct data can be written into MODH and MODL beforehand with 8 bit manipulation instructions then the written 14 bit data can be transferred to the modulo latch at one time This transfer is referred to as reloading and it is controlled by If is 0 reloading is disabled and if it is 1 reloading is enabled Follow the procedure below to rewrite the modulo latch contents 1 Clear TPGMS to disable reloading lt 2 gt Change the MODH and MODL contents 3 Set to 1 to enable reloading Cautions 1 If the modulo register H MODH is set to 0 the PWM pulse generator can not function normally So be sure to set MODH to a value from 1 to 255 2 If the lower 2 bits of the modulo register L MODL is read the read result is unpredictable 3 If the modulo latch is changed in a shorter period than the PWM pulse basic period 219 fy 171 us At 6 0 MHz Note PWM pulses do not change Note At 4 19 MHz 219 fy 244 us Example Decrease analog output voltage to the lowest level then increase it to the highest level CLR1 MBE MOV XA 01H MOV MODH XA MODH lt 01 MOV MODL XA MODL 01 MOV XA 10101010B MOV TPGM XA Enable PWM pulse output CLR1 TPGM 3 Disable reloading MOV XA 0FFH MOV MODH XA MOV MODL XA SET1 TPGM 3 Enable reloading uPD75518 User s Manual Chapter 5 Per
323. upt request flag IRQn is set 1 When IRQn is set during execution of an interrupt control instruction When IRQn is set during execution of an interrupt control instruction an instruction preceded by that instruction is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started Interrupt control instruction A IRQn is set B The next instruction is executed 1 to 3 machine cycles according to the instruction C Interrupt processing 3 machine cycles D Interrupt service routine is executed Remarks 1 An interrupt control instruction manipulates hardware address FBx in data memory which handles interrupt processings There are two types of interrupt control instruction a DI instruction and an El instruction 2 Three machine cycles required for the interrupt processing include the time to manipulate the stack when an interrupt is accepted Cautions 1 When a series of interrupt control instructions is executed an instruction preceded by the interrupt control instruction executed last is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started 2 When a DI instruction is executed in the period during which is set A in the figure or in the immediately following period B in the figure the interrupt request of the set IRQn is held until an El instruction is executed
324. ure 5 9 Figure 5 10 uPD75518 User s Manual List of Figures 1 4 Pin Input Output die edt a reae Eds 2 13 Use of MBE 0 Mode and MBE 1 Monde 3 3 Data Memory Organization and Addressing Range of Each Addressing Mod rincer ariii inai eaa ENE nnne niin 3 4 Updating Static RAM Addresses sss sene 3 11 Example of Register Bank Selection sse 3 18 General Register Configuration 4 bit 3 20 General Register Configuration 8 bit 3 21 uPDz5516 I O 2555 555 a 51565 555 3 24 Program Counter Format c vss e e aatis ado po a ores 4 1 Program Memory Map uPD75517 sss 4 3 Program Memory uPD75518 and uPD75P518 4 4 Data Memory 4 5 General Register 4 9 Register Formal eder Fui TTE 4 9 ACCUImulator Reb imus 4 10 Format of Stack Pointer and Stack Bank Select 4 12 Data Saved to Stack Memory sss 4 13 Data Restored from Stack
325. voltage disable TT410 V Input buffer with an intermediate withstand voltage of 10 V Chapter2 Pin Functions Y Y TT ing 1 AVss Reference voltage from voltage tap of serial resistor string P U R P U R enable IN OUT Data J gt N ch Output disable TT P U R Pull Up Resistor IN instruction Reference voltage from voltage tap of serial resistor string Dale IN OUT Output disable P D R Mark option 777 P D R Pull Down Resistor uPD75518 User s Manual Reference voltage Chapter 2 Pin Functions 2 4 Connection of Unused Pins Table 2 3 Recommended Connection of Unused Pins 1 2 Pin POO INT4 P01 SCKO P02 SO0 SBO 511 5 1 P10 INTO P12 INT2 P13 TIO P20 PTOO P21 P22 PCL P23 BUZ P30 P33 P30 MD0 P33 MD3 Note P40 P43 P50 P53 P60 KRO P63 KR3 P70 KR4 P73 KR7 P80 PPO P81 SCK1 P82 SO1 511 P90 P93 P100 P103 P110 P113 P120 P123 P130 P133 P140 P143 P150 AN4 P153 AN7 ANO AN3 XT1 XT2 AVREF AVss Recommended connection To be connected to Vss To be connected to Vss or Vpp To be connected to Vss Input state To be connected to Vss or Vpp Output state To be left open To be connected to Vss or Vpp Input state be connected to Vss or Vpp Output state
326. which removes pulses shorter than two sampling clock cycles Note as noise The INTO circuit may accept pulses which are longer than one sampling clock cycle and shorter than two cycles as interrupts depending on the sampling timing see Figure 6 4 2 a The circuit is sure to accept pulses equal to or longer than two sampling clock cycles as interrupts The INTO pin is supplied with sampling clock or 1 64 whichever is selected by bit 3 of the edge detection mode register 1 03 see a of Figure 6 5 Bit 0 IMOO and bit 1 IMO1 of the edge detection mode register are used to select a detection edge Figure 6 5 a shows the format of IMO A 4 bit memory manipulation instruction is used to set IMO A RESET signal clears all bits to 0 and a rising edge is specified to be detected When the frequency of a sampling clock is these cycles are equal to 2tcy When the frequency of a sampling clock is fy 64 these cycles are equal to 128 Cautions 1 Since the INTO input is sampled with a clock INTO does not operate in a standby mode 2 Input a pulse wider than two sampling clock cycles to the INTO P10 pin Otherwise the pulse is suppressed as noise by a noise eliminator when the pin is used as a port b As shown in Figure 6 3 b the INT1 circuit accepts an external interrupt at its rising or falling edge The edge detection mode register IM1 is used to select a detection edge Figure 6 5 b shows t
327. with INTBT handled as high order and INTTO and INTCSIO handled as low order SEL El EI EI 1 MOV MOV Reset 1 0 282 IEBT IETO IECSIO A 9 Status 0 IPS A INTTO service program 0 lt INTBT service program gt 1 lt 2 gt INTTO 4 SEL RB1 Status 2 5 SEL RB2 RETI Y 1 2 3 4 5 INTBT is given a higher priority by setting IPS and the interrupt is enabled An occurrence of INTTO with a lower priority causes the INTTO interrupt service program to start and change to status 1 disabling interrupts with lower priorities RBE 0 is set and register bank 0 is used An occurrence of INTBT with a higher priority causes two level interrupt processing and change to status 2 All interrupts are disabled RBE 1 and RBS 1 are set and register bank 1 is used Only registers to be used may be saved by the PUSH instruction RBS is set to 2 and the return status is set to 1 again uPD75518 User s Manual Chapter 6 Interrupt Function 4 Execution of held interrupts interrupt requests when interrupts are disabled lt Main program gt Reset IEO INTO service program 1 INTO 2 EI 3 INTCSIO RETI INTCSIO service program 4 IECSIO RETI uPD75518 User s Manual 1 2 3 4 If INTO is set when interrupts are di
328. y as the other port Accordingly as shown in Figure 5 89 AVREF observed during emulation is lower than observed on the 75518 and so the conversion result obtained during emulation is not equal to that on the nPD75518 Figure 5 89 Reducing Power Consumption in the Standby Mode Voo e P ch Note P113 H 777 AVREF 75518 AVss Note The drive capability of P ch is higher than that of other ports uPD75518 User s Manual 5 159 Chapter 5 Peripheral Hardware Functions 5 9 4 Other Notes on Use 5 160 a b ANO to AN7 input range Voltage out of specification must not be applied to ANO to AN7 inputs If a voltage higher than Vpp or lower than Vss is applied even when the maximum absolute rating is not exceeded the conversion result for the associated channel becomes unpredictable In addition the conversion results for other channels may be affected Noise protection To maintain 8 bit resolution the user should pay attention to noise that may be applied to the AVrer and ANO to AN7 pins Noise adversely affects operation to a greater extent when the analog input source has a higher output impedance As shown in Figure 5 90 a capacitor should be externally connected Figure 5 90 Analog Input Pin Connection C 100 1000pF C If it is anticipated that noise voltages do not fall in the vee range of Vss to clamp th
329. y divider 1 2 1 4 1 16 Oscillator disable signal Frequency divider 1 4 INTO noise eliminator Clock output circuit Internal bus HALT flip flop PCC2 PCC3 clear signal STOP flip flop Wait release signal from Q S lt RESET signal Standby release signal from interrupt control circuit Note Instruction execution Remarks fy Main system clock frequency Subsystem clock frequency CPU clock PCC Processor clock control register SCC System clock control register One clock cycle tcy of the CPU clock is equal to one machine cycle of an instruction Qr Ori ors 5 22 uPD75518 User s Manual Chapter 5 Peripheral Hardware Functions 5 2 2 Functions and Operations of the Clock Generator The clock generator generates the following clocks and controls the CPU operation modes such as the standby mode Main system clock fx Subsystem clock CPU clock Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register PCC and system clock control register SCC The function and operation of the clock generator are described in a to g below a b Note 1 Note 2 uPD75518 User s Manual A RESET signal selects the lowest speed mode 10 7 us At 6 0 MHz Note 1 for

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