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FIR II IP Core User Guide

1. 2014 12 15 Figure 4 23 Correct Input Format 11 valid cycles 9 invalid cycles areset diro Saeed xin_v 0 T I T xin_c 7 0 xin 0 7 0 SOS IOS TOT BI T 4 311213 1315 1517 xin 1 7 0 2 I 3 I M I 5 I 36 T V 1 38 T 19 1 20 T 21 1 22 T 15 LB 14 15 6 117 118 xout_v 0 xout 7 0 Spy pp I I ot ot TTT xout_0 17 0 3 13615 117 xout_1 17 0 2411321 18 1 24 T 0 xout_2 17 0 407 48 30 T 36 T xout_3 17 0 36 1 941 4221 48 T xout_4 17 0 72 1 801 5 1 0 xout_5 17 0 88 r w T 86 T 72 T xout_6 17 0 r tttr 1t2 rr78 r 81 xout_7 17 0 1207128 90 T 96 T 0 xout_8 17 0 B61 14 102 108 0 xout_9 17 0 521 160 114 7 1207 xout_10 17 0 168 176 126 T1327 Figure 4 24 Incorrect Input Format 11 valid cycles 0 invalid cycles If the number of invalid cycles is less than 17 the output format is incorrect areset xout_10 Altera Corporation DS TS VA TTT ABTS OAT 227 TST STS OTT TT OY 27 227 LOOT OTTOO OT OUT OTT OO T 017007 OTT ITTUTTT I 6 ILT oT I IE ITT T I 30 I368 0 T I 27 48 0 I I 54 1070 T I 66 I2 0 T I T8 L340 I I 20 r251 I 102 IOg 0 T I T PA 0 T I T26 II v I FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 Super Sample Rate 4 19 Figure 4 25 Correct Input
2. This result appears to be vertical but that is because the number of cycles is 1 so on each wire there is only space for one piece of data Figure 4 18 Four Channels on Four Wires with Double Clock Rate Input dk f VV J xnv xn 0f C y ay xIn 1 Figure 4 19 Four Channels on Four Wires with Double Clock Rate Output dk f VT VJ xut v TT x0ut Of C jy 0 xOut_1 15 Channels with 15 Valid Cycles and 17 Invalid Cycles Sometimes invalid cycles are inserted between the input data An example where the clock rate 320 sample rate 10 yields a TDM factor of 32 inputChannelNum 15 and interpolation factor is 10 In this case the TDM factor is greater than inputChannelNum The optimization produces a filter with PhysChanIn 1 ChansPerPhyIn 15 PhysChanOut 5 and ChansPerPhyOut 3 The input data format in this case is 32 cycles long which comes from the TDM factor The number of channels is 15 so the filter expects 15 valid cycles together in a block followed by 17 invalid cycles You can insert extra invalid cycles at the end but they must not interrupt the packets of data after the process has started If the input sample rate is less than the clock rate the pattern is always the same a repeating cycle as long as the TDM factor with the number of channels as the number of valid cycles required and the remainder as invalid cycles Altera Corporation FIR II IP Core Functional Description C Send Feedback UG
3. 34 Controller control signals xin v xn 0 7 0 FIR Filter Single Channel on Single Wire 4 3 FIR II IP Core Functional Description C Send Feedback Altera Corporation UG 01072 4 4 Multiple Channels on Single Wire 2014 12 15 Multiple Channels on Single Wire Figure 4 3 Multiple Channels on Single Wire Sink to FIR II IP core When transferring a packet of data over multiple channels on a single wire The data width of each channel is 8 bits FIR Compiler MegaCore Function sink ready Controller packet error ast sink error Avalon ast sink sop Streaming ast sink eo Istae SInk eop gt Signals Check xin 0 7 0 ast sink valid FIR Filter ast sink data 7 0 ast sink ready Multiple Channels on Multiple Wires In this example hardware optimization produces a TDM factor of 2 number of channel wires 3 and channels per wire 2 Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 Figure 4 4 Multiple Channels on Multiple Wires Multiple Channels on Multiple Wires 4 5 The sink interface to the FIR II IP core when transferring a packet of data over multiple channels on multiple wires The data width of each channel is 8 bits Number of channels 6 clock rate 200 MHz and sample rate 100 MHz FIR Compiler II MegaCore Function ast_sink_error Avalon Str
4. Fractional Write 2 301 16 3 601 Rate A 8 2 Interpolation 1 840 32 0 2 431 48 25 Interpolation Write 2 8 2 Interpolation Multiple 2 006 32 0 2 711 98 25 banks 3 8 2 Interpolation Multiple 2 704 32 0 2 990 100 25 banks 0 Write 8 2 Single rate 934 20 0 317 19 25 2 8 2 Single rate Write 1 053 20 0 704 12 25 1 8 1 Decimation 474 3 1 541 50 27 5 8 1 Decimation Write 559 3 1 574 58 2 3 8 1 Decimation Multiple 544 3 3 691 83 27 banks 5 8 1 Decimation Multiple 636 3 3 677 82 27 banks 5 Write 8 1 Fractional 1 165 5 4 1 715 205 27 Rate 5 8 1 Fractional Write 1 287 5 4 1 2770 198 207 Rate 5 8 1 Interpolation 381 5 0 433 42 24 8 8 1 Interpolation Write Bild S 0 540 26 25 0 8 1 Single Rate 493 10 0 191 18 24 9 8 1 Single Rate Write 624 10 0 563 26 25 1 About the FIR II IP Core Altera Corporation CJ Send Feedback UG 01072 1 8 FIR II IP Core Performance and Resource Utilization 2014 12 15 Decimation 3 28 9 1 super Decimation 404 20 398 43 28 sample 8 1 super Decimation Write 503 20 m 774 46 25 sample 6 1 Decimation Write 32 3 208 26 28 9 1 Half Decimation 234 3 192 29 28 Band 1 Half Decimation Write 225 90 J2 228 97 28 Band 5 1 Fractional 422 3 723 94 31 Rate 0 1 Fractional Write 516 3 787 86 29 Rate 2 1 H
5. lt my_ip gt _inst v or _inst vhd HDL example instantiation template You can copy and paste the contents of this file into your HDL file to instantiate the IP variation lt my_ip gt regmap If the IP contains register information the regmap file generates The regmap file describes the register map information of master and slave interfaces This file complements the sopcinfo file by providing more detailed register information about the system This enables register display views and user customizable statistics in System Console FIR II IP Core Getting Started send Feedback Altera Corporation 2 8 Simulating Altera IP Cores in other EDA Tools UG 01072 2014 12 15 el lt my_ip gt svd Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system During synthesis the svd files for slave interfaces visible to System Console masters are stored in the sof file in the debug section System Console reads this section which Qsys can query for register map information For system slaves Qsys can access the registers by name lt my_ip gt v or lt my_ip gt vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation mentor Contains a ModelSim script msim setup tcl to set up and run a simulation aldec Contains a Riviera PRO script rivierapro setup tcl to setup and run a simulation synopsys vcs
6. A IP Parameter Editor unnamed qsys users brossar unnamed qsys mE File Edit System Generate View Tools Help Parameters 00 a BERNER Block Symbol amp unsaved gt altclkctri 0 IE aaan amm altcikctri i Name altcikctrl E i 4 Anakan E Version 14 0 i Author Altera Corporation Altcikctri represents clock buffers that drive the Global Clock Network the Regional Clock Network nti and the dedicated External Clock path Ji Desenption no deseiaptiun Sie eT Mil ij Grou Basic Functions Clocks How do you want to use the ALTCLKCTRL For global clock E P Ping ae How many clock inputs would you like 11 i vum Altclkct Create ena port to enable or disable the clock network driven by this buffer d Altclkctrl How do you want to register the ena port pan C Ensure glitch free switchover implementation New IP Instance New IP Variation Your IP settings will be saved in a qsys file Create IP Variation Entityname unnamed Save in folder users jbrossar 141 sv source i for ALTCLKCTRL 14 0 la a i Target Device i ew BERE Twe ewe unknown R 0 3 Inf unsi e Info Your IP will be saved in users jbrossar 141 sv source unnamed qsys 5 o jenes lunsa Los New 4 f 0 Errors 0 Warnings i Specify your IP variation name and target device Files
7. 01072 2014 12 15 Parameters FIR II IP Core Performance and Resource Utilization Memory fmax ii era aki DSP 1 Half Decimation 3 45 Band 2 1 Half Decimation Write 343 3 0 327 18 45 Band 2 1 B Fractional 252 3 0 318 21 44 Rate 5 1 Fractional Write J lo 0 380 13 45 Rate 0 1 Half Fractional 140 2 0 185 13 45 Band Rate 0 1 Half Fractional Write 2 2 0 235 21 45 Band Rate 0 1 Interpolation 168 5 0 127 19 45 0 1 super Interpolation S 22 0 1 084 51 44 sample 6 l super Interpolation Write 870 32 0 1 774 136 45 sample 0 1 Interpolation Write ST S 0 196 5 45 0 1 Half Interpolation 253 3 0 292 9 45 Band 1 Half Interpolation Write 370 4 0 418 9 45 Band 9 1 Single rate 226 10 0 706 31 44 7 M Single rate 468 20 0 1354 53 45 ssample 0 1_ L Single rate Write 927 20 0 2 267 203 45 ssample 0 1 Single rate Write 524 10 0 1 391 31 50 0 1 Half Single rate 195 5 0 270 50 45 Band 1 Half Single rate Write SS 5 0 645 28 45 Band 2 About the FIR II IP Core CJ Send Feedback Altera Corporation 1 12 FIR II IP Core Performance and Resource Utilization Parameters DSP UG 01072 2014 12 15 MHz By ES ED Single rate Multiple 10 44 banks 9 1 Single rate Multiple 6
8. About the FIR II IP Core CJ Send Feedback Altera Corporation UG 01072 1 6 FIR II IP Core Performance and Resource Utilization 2014 12 15 soc i ins 1 Half Interpolation 3 31 Band 1 Half Interpolation Write 333 4 314 10 30 Band 2 1 Single rate 93 10 129 27 29 9 1 super Single rate 262 20 307 41 30 sample 9 1 super Single rate Write 373 20 687 40 30 sample 2 1 Single rate Write 228 10 519 16 30 0 1 Half Single rate 189 5 254 63 30 Band a 1 Half Single rate Write 272 J3 496 29 31 Band 1 Single rate Multiple 109 10 199 29 28 banks 3 1 Single rate Multiple 395 10 361 19 28 banks 2 Write Table 1 4 FIR II IP Core Performance Cyclone V Devices Typical expected performance using the Quartus II software with TUS V ZI devices Parameters DSP waran is MEKAN EA ee fmax MHz Decimation 1 607 24 1 231 27 3 8 Decimation Write 2 092 24 1 352 63 27 3 8 Fractional 1 852 16 3 551 309 25 Rate 4 8 Fractional Write 2 203 16 3 675 269 25 Rate 5 8 Fractional 1 951 16 3 543 421 22 Rate 7 Altera Corporation About the FIR II IP Core C Send Feedback UG 01072 Hic eax 2014 12 15 FIR II IP Core Performance and Resource Utilization MHz
9. Avalon ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries Such interfaces typically contain data ready and valid signals Avalon ST interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels The Avalon ST interface inherently synchro nizes multichannel designs which allows you to achieve efficient time multiplexed implementations without having to implement complex control logic Avalon ST interfaces support backpressure which is a flow control mechanism where a sink can signal to a source to stop sending data The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output Related Information e Avalon Interface Specifications FIR II IP Core Avalon ST Interfaces Avalon ST Sink Interface The sink interface can handle single or multiple channels on a single wire and multiple channels on multiple wires Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 Single Channel on Single Wire Figure 4 2 Single Channel on Single Wire Sink to FIR II IP Core When transferring a single channel of 8bit data FIR Compiler ll MegaCore Function Sink ast sink valid ast sink data 7 0 ast sink ready sink ready ARE
10. Cyclone IV GX Stratix V Stratix IV P Low Power MAX 10 b Memory Interfaces and Controllers Location Roots acds 15 0 139 nux64Ap alter a megafunctions altcikctri altcikctr fw tci gt Processors and Peripherals lj DATASHEET P University Program E Search for Partner IP x2 Open Component Folder Note The IP Catalog is also available in Qsys View IP Catalog The Osys IP Catalog includes exclusive system interconnect video and image processing and other system level IP that are not available in the Quartus II IP Catalog For more information about using the Qsys IP Catalog refer to Creating a System with Qsys in the Quartus II Handbook Specifying IP Core Parameters and Options You can quickly configure a custom IP variation in the parameter editor Use the following steps to specify IP core options and parameters in the parameter editor Refer to Specifying IP Core Parameters and Options Legacy Parameter Editors for configuration of IP cores using the legacy parameter editor FIR II IP Core Getting Started Altera Corporation CJ Send Feedback UG 01072 2 4 Specifying IP Core Parameters and Options 2014 12 15 1 Altera Corporation In the IP Catalog Tools gt IP Catalog locate and double click the name of the IP core to customize The parameter editor appears Specify a top level name for your custom IP variation The parameter editor saves the IP variation settings in a file named lt your_ip gt qsys Click
11. DSP Builder Design Flow DSP Builder shortens digital signal processing DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm friendly development environment This IP core supports DSP Builder Use the DSP Builder flow if you want to create a DSP Builder model that includes an IP core variation use IP Catalog if you want to create an IP core variation that you can instantiate manually in your design For more information about the DSP Builder flow refer to the FIR II IP Core Getting Started C Send Feedback Altera Corporation UG 01072 2 10 DSP Builder Design Flow 2014 12 15 Related Information Using MegaCore Functions chapter in the DSP Builder Handbook Altera Corporation FIR II IP Core Getting Started C Send Feedback FIR II IP Core Parameters 2014 12 15 UG 01072 X subscribe Send Feedback You define a FIR filter by its coefficients You specify the filter settings and coefficient options in the parameter editor The FIR II IP core provides a default 37 tap coefficient set regardless of the configurations from filter settings The scaled value and fixed point value are recalculated based on the coefficient bit width setting The higher the coefficient bit width the closer the fixed frequency response is to the intended original frequency response with the expense of higher resource usage You can load the coefficients from a file For example you can create th
12. Format 11 valid cycles 11 invalid cycles dk ae AeA EAI mama m me Lae areset xin_v 0 T I T I T xin d7 0 xin 0 7 0 TOT TITS TE 17138 13 1 10 1 31 1 1 Dtww2Zyw2 TtT5T IT xin 1 7 0 OB CE TI I 3 amp TT IT ET TT 2257221 5 LRR Cs 16 T Z xout_v 0 1 I iu I xout c 7 0 I 0 I E 0 I T 0 I T I 0 I T I 0 I T 1 0 T I 0 T T 0 I L T 0 1 T U I LI 1 0 I T 1 0 1 T T1 9 xout 0 17 0 IS TI1 I 17 I JO GFF xout_1 17 0 I27 B 18 124 OQ I3FFEBT xout 2 17 0 D40 148 130 136 1 9 I3FFDDT xout_3 17 0 156 164 1237 138 1 U I3FKFT xout 4 17 0 IZ 9 I3 T9 I T FECIT xout 5 17 0 38 96 196 177 I U 3FFB3T xout 6 17 0 LIUM T7 17 I9 I 3FFAST xout_7 17 0 L20 1028 90 T96 I 0 7 FFT xout_8 17 0 1361447 1021081 3FF89 xout_9 17 0 y52 TT155 TT2 TT 3FE7ET xout 10 17 0 LIS U5 IU6 12 I 3FFGUT You can insert extra invalid cycles at the end which mean the number of invalid cycles can be greater than 9 but they must not interrupt the packets of data after the process has started Super Sample Rate For a super sample rate filter the sample rate is greater than the clock rate In this example clock rate 100 sample rate 200 inputChannelNum 1 and single rate The optimization produces a filter with PhysChanIn 2 ChansPerPhyIn 1 PhysChanOut 2 and ChansPe
13. Multiplexing sscssussssacasssseosssnssessscnsnsentsssesanssnsnsssaveatesedacbsavensaisavsnitessbenssee 4 11 FIR II IP Core Multichannel Operation eese tntetee tenente ettet totes 4 12 Vectorized Inputs erc tere ter ER EUER B PR RH EI RI IS RENE ERE aa 4 12 Channeliza ti M 4 13 Altera Corporation FIR II IP Core User Guide TOC 3 Channel Input and Output Format bro pov rites nns aperta rti HH HHHH HAH HHH RR 4 15 FIR II IP Core Multiple Coefficient Ban Ks E ri eoi basab e ad titre bugie d AKAR 4 20 FIR II IP Core Coefficient Reloading cis aae etae rib crt ara rinde e Kya dp aid ais 4 21 Document Revision EHISEOLy eere peur p Diano rca e sn aepo S VER RENE SEDIS Qu eu Heke Lp uiv ER CUR DEO 5 1 Altera Corporation About the FIR II IP Core 2014 12 15 UG 01072 amp Subscribe CJ Send Feedback The Altera FIR II IP core provides a fully integrated finite impulse response FIR filter function optimized for use with Altera FPGA devices The II IP core has an interactive parameter editor that allows you to easily create custom FIR filters The parameter editor outputs IP functional simulation model files for use with Verilog HDL and VHDL simulators You can use the parameter editor to implement a variety of filter types including single rate decimation interpolation and fractional rate filters Many digital systems use signal filtering to remove unwanted noise
14. ast_source_data ast source sop ast source eop ast source channel ast source error ast source ready FIR II IP Core Functional Description C Send Feedback Altera Corporation UG 01072 4 8 FIR II IP Core Signals 2014 12 15 Figure 4 7 Timing Diagram of Multiple Channels on Multiple Wires The FIR IL IP core to the source interface when transferring a packet of data over multiple channels on multiple wires dk f VU U TA PY T A PA TT xQutv t AM Yz LLL xOut_d7 0 Of TY OY TY XT xOut_0 7 0 AT y EU y RT y BT YAZ Y Bz xut o X wp uguqu wYi xout 270 Eo f Foy E Y Fi YE YF y ast source valid Lo ast_source_data 7 0 __ XY AY Ayaa YY BZ y ast_source_data 15 8 X Yo yo yayn c T2 ast_source_data 23 16 X yT TY ery FI amp YR ast_source_sop J J ast_source_eop XV JON ast source channel X yoy yoy yoy ast_source_error 00 FIR II IP Core Signals Table 4 1 FIR II IP Core Signals with Avalon ST Interface HEZER KAM EKA NENNEN 7 CN NN Input Clock signal for all internal FIR II IP core filter registers reset n Input 1 Asynchronous active low reset signal Resets the FIR II IP core filter control circuit on the rising edge of Gk coeff_in_clk Input 1 Clock signal for the coefficient reloading mechanism This clock can have a lower rate than the system clock c
15. channel 2 Q 0 aa ji QQ input data channel 3 am y a y G input channel output valid I J output_data_wire_1 Y 00 y 0 Y dontare y OM d dmtae 00 y dg output data wire 2 output chanel The channel signal is used for synchronization and scheduling of data It specifies the channel data separation per wire Note that the channel signal counts from 0 to ChanCycleCount 1 in synchronization with the data Thus for ChanCycleCount 1 the channel signal is the same as the channel count enumerated from 0 to inputChannelNum 1 For a case with single wire the channel signal is the same as a channel count Figure 4 11 Four Channels on One Wire with No Invalid Cycles valid channel Y 0 I 1 y 2 I 3 y 0 y T Y 2 Y 3 Y data0 d c1 y Qo yy cw j d 1 d 1 yy qm Sm y For ChanWireCount gt 1 the channel signal specifies the channel data separation per wire rather than the actual channel number The channel signal counts from 0 to ChanCycleCount 1 rather than 0 to inputChannelNum 1 Figure 4 12 Four Channels on Two Wires with No Invalid Cycles vid m aS OS eT channel 0 ji 1 ji 0 1 j 0 I 1 ji 0 ji 1 ji data0 data1 y QUO G e 80 y cl gag yy 28 203 Y Notice that the channel signal remains a single wire not a wire for each data wire It counts from 0 to ChanCycleCount 1 Altera Corporation FIR II IP Core Functional
16. core quickly and easily e Generate time limited device programming files for designs that include IP cores e Program a device with your IP core and verify your design in hardware OpenCore Plus evaluation supports the following two operation modes Untethered run the design containing the licensed IP for a limited time e Tethered run the design containing the licensed IP for a longer time or indefinitely This requires a connection between your board and the host computer Note All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times out FIR II IP Core OpenCore Plus Timeout Behavior All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one IP core in a design the time out behavior of the other IP cores may mask the time out behavior of a specific IP core All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached If there is more than one IP core in a design a specific IP core s time out behavior may be masked by the time out behavior of the other IP cores For IP cores the untethered time out is 1 hour the tethered time out value is indefinite Your design stops working after the hardware evaluation time expires The Quartus II software uses OpenCore Plus Files ocp in your project directory to identify your use of the OpenCore Plus evaluation program After you activate th
17. meets all functional requirements but might still be undergoing timing analysis for the device family You can use it in production designs with caution Final support Altera verifies the IP core with final timing models for this device family The IP core meets all functional and timing requirements for the device family You can use it in production designs DSP IP Core Device Family Support Arria II GX Final Arria II GZ Final Arria V Final Arria 10 Final Cyclone IV Final Cyclone V Final MAX 10 FPGA Final Stratix IV GT Final Stratix IV GX E Final Altera Corporation About the FIR II IP Core C Send Feedback UG 01072 2014 12 15 DSP IP Core Verification 1 3 Stratix V Final Other device families No support DSP IP Core Verification Before releasing a version of an IP core Altera runs comprehensive regression tests to verify its quality and correctness Altera generates custom variations of the IP core to exercise the various parameter options and thoroughly simulates the resulting simulation models with the results verified against master simulation models FIR II IP Core Release Information Use the release information when licensing the IP core Table 1 2 Release Information mmm 7 X Version 14 1 Release Date December 2014 Ordering Code IP FIRII Product ID 00D8 Vendor ID 6AF7 Altera verifies that the current version of the Quartus II
18. name of the txt file containing the coefficient set In the txt file separate the coefficients file by either white space or commas or both Use new lines to separate banks You may use blank lines as the FIR II IP core ignores them You may use floating point or fixed point numbers and scientific notation Use a character to add comments Specify an array of coefficient sets to support multiple coefficient sets Specify the number of rows to specify the number of banks All coefficient sets must have the same symmetry type and number of taps For example bank 1 and 2 are symmetric 1 2 3 2 1 13431 bank 3 is anti symmetric 120 2 1 bank 4 is asymmetric 1 2 3 4 5 Note The file must have a minimum of five non zero coefficients 2 Click Apply to import the coefficient set Input and Output Options Table 3 3 Input and Output Options Input Options Input Data Type Signed Binary Specifies whether the input data is in a signed Signed Fractional binary ora signed fractional binary format Select Binary Signed Fractional Binary to monitor which bits the IP core preserves and which bits it removes during the filtering process Input Bit Width 1 32 Specifies the width of the input data sent to the filter Input Fractional Bit Width 0 32 Specifies the width of the data input into the filter when you select Signed Fractional Binary as your input data type Output Options Altera Corporat
19. required Each FIR II IP core in your design is internally vectorized to build multiple FIR filters in parallel Figure 4 9 Channelization of Two Channels with a TDM Factor of 3 A TDM factor of 3 combines two input channels into a single output wire inputChannelNum 2 ChanWireCount 1 ChanCycleCount 2 This example has three available time slots in the output channel and every third time slot has a don t care value when the valid signal is low The value of the channel signal while the valid signal is low does not matter dok N7 XJ dQ U LLLI LL n L input valid input data channel 0 _ co 0 ji 0 1 y 0 2 input_data_channel_1 input channel output valid TDM_output_data output channel ss Y 4 P FIR II IP Core Functional Description Altera Corporation CJ Send Feedback UG 01072 4 14 Channelization 2014 12 15 Figure 4 10 Channelization for Four Channels with a TDM Factor of 3 A TDM factor of 3 combines four input channels into two wires inputChannelNum 4 ChanWireCount 2 ChanCycleCount 2 This example shows two wires to carry the four channels and the cycle count is two on each wire The channels are evenly distributed on each wire leaving the third time slot as don t care on each wire dok 7 OT UNT UV o c STU STU TU input valid input data channel 0 00 y a f 2 input_data_channel_1 d input data
20. software compiles the previous version of each IP core Altera does not verify that the Quartus II software compiles IP core versions older than the previous version The Altera IP Release Notes lists any exceptions Related Information e Altera IP Release Notes Errata for FIR IL IP core in the Knowledge Base FIR II IP Core Performance and Resource Utilization Table 1 3 FIR II IP Core Performance Arria V Devices Typical expected performance using the Quartus II software with Arria V brak MHz me ins REZEK AM A i oP Decimation ud 24 1 232 64 About the FIR II IP Core Altera Corporation CJ Send Feedback UG 01072 1 4 FIR II IP Core Performance and Resource Utilization 2014 12 15 Decimation Write 2 120 24 1 298 30 8 8 Fractional 1 395 16 2 074 99 28 Rate 1 8 Fractional Write 1 745 16 211 91 28 Rate 2 8 Fractional 1 493 16 2 167 117 28 Rate 0 8 Fractional Write 1 852 16 2 287 116 2 Rate 0 8 Interpolation 1 841 32 2 429 52 28 2 8 Interpolation Write 1 994 32 2 826 41 27 8 8 Interpolation Multiple 2 001 32 2 737 74 27 banks 9 8 Interpolation Multiple 2 700 32 2 972 130 28 banks 2 Write 8 Single rate 932 120 318 20 27 8 8 Single rate Write 1 057 20 713 3 27 9 8 Decimation 329 3 321 33 30 1 8 Decimation Write 430 3 366 34 30 7 8 Decimat
21. the input but three wires at the output Any necessary multiplexing and packing is performed by the FIR II IP core The blocks connected to the inputs and outputs must have the same vector widths Vector width errors can usually be resolved by carefully changing the sample rates Channelization The number of wires and the number of channels carried on each wire are determined by parameterization which you can specify using the following variables clockRate is the system clock frequency MHz inputRate is the data sample rate per channel MSPS inputChannelNum is the number of channels Channels are enumerated from 0 to inputChan nelNum 1 The period or TDM factor is the ratio of the clock rate to the sample rate and determines the number of available time slots ChanWireCount is the number of channel wires required to carry all the channels It can be calculated by dividing the number of channels by the TDM factor More specifically e PhysChanIn Number of channel input wires e PhysChanOut Number of channel output wires ChanCycleCount is the number of channels carried per wire It is calculated by dividing the number of channels by the number of channels per wire The channel signal counts from 0 to ChanCycleCount 1 More specifically e ChansPerPhyIn Number of channels per input wire ChansPerPhyOut Number of channels per output wire If the number of channels is greater than the clock period multiple wires are
22. using block RAM enter a lower number such as a value in the range of 20 30 To use fewer block memories enter a larger number such as 100 To never use block memory for simple delays enter a very large number such as 10000 RA wd RD Implement delays of less than three cycles in LEs because of block RAM behavior Note This threshold only applies to implementing simple delays in memory blocks or logic elements You cannot push dual memories back into logic elements Using CDual Mem Dist RAM Threshold This threshold is trade off between small and medium RAM blocks This threshold is similar to the Using LEs Small RAM Block Threshold except that it applies only to the dual port memories The IP core implements any dual port memory in a block memory rather than logic elements but for some device families different sizes of block memory may be available The threshold value determines which medium size RAM memory blocks IP core implements instead of small memory RAM blocks For FIR II IP Core Parameters Altera Corporation CJ Send Feedback UG 01072 3 8 Using M RAM Threshold 2014 12 15 example the threshold that determines whether to use M9K blocks rather than MLAB blocks on Stratix IV devices 1 Set the default threshold value to implement dual memories greater than 1 280 bits as M9K blocks and dual memories less than or equal to 1 280 bits as MLABs 2 Change this threshold to a lower value such as 200 to implement
23. xOut c xOut 0 00 0 MJ Mj A6j ABj Moy Aj Aj xOut 1 00 VAT yA XV AS Y Ayy AD Y My ABY Ay xOut_2 00 AU Vy My ROY My AWY Ay AM xOut_3 0ST FIR II IP Core Multiple Coefficient Banks The FIR IL IP core supports multiple coefficient banks The FIR filter can switch between different coefficient banks dynamically which enables the filter to switch between infinite number of coefficient sets Therefore while the filter uses one coefficient set you can update other coefficient sets You can also set different coefficient banks for different channels and use the channel signal to switch between coefficient sets The IP core uses multiple coefficient banks when you load multiple sets of coefficients from a file RT Refer to Loading Coefficients from a File Based on the number of coefficient banks you specify the IP core extends the width of the ast sink data signal to support two additional signals bank signal bank1n and input data x14 signal The most significant bits represent the bank signals and the least significant bits represent the input data You can switch the coefficient bank from 0 to 3 using the bankIn signal when the filter runs Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 FIR II IP Core Coefficient Reloading 4 21 Figure 4 28 Timing Diagram of a Single Channel Filter with 4 Coefficient Banks d22 U LLL LLL Le Le 10y ast s
24. 0 71 119 40 fro 124 114 0 LT o coeff_in_data 15 0 1 5a 18 nos 34 i9 vof 105 1 coeff_in_address 11 0 6 7 8 T Lol u vo 5 7 cefinwe J xout_v 0 xout_0 19 0 0 3anis3dbe3qsaoqeaodgoed 11 16 2o zo 23 28 30 26 s 12 14 12 2 51 r kuz 13 82 61946614 0 58 18 106 34 119 via 105 n2 FIR II IP Core Functional Description Altera Corporation C Send Feedback Document Revision History 2014 12 15 UG 01072 X subscribe Send Feedback FIR II IP Core User Guide revision history HEKE KANI aes 2014 12 15 14 1 e Added full support for Arria 10 and MAX 10 devices Reordered parameters tables to match wizard e Updated loading coefficients from a file instructions August 14 0 Arria 10 e Added support for Arria 10 devices 2014 Edition e Added Arria 10 generated files description e Removed table with generated file descriptions June 2014 14 0 e Corrected TDM timing diagram TDM_output_data signal e Removed device support for Cyclone III and Stratix III devices e Added support for MAX 10 FPGAs e Added instructions for using IP Catalog November 13 1 Corrected coefficient file description dus e Removed device support for following devices e HardCopy II HardCopy III HardCopy IV E HardCopy IV GX e Stratix Stratix GX Stratix II Stratix II GX e Cyclone Cyclone II e Arria GX May 2013 13 0 Updated interpolation and decimation factor ranges November 12 1 Ad
25. 01072 2014 12 15 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4 17 Figure 4 20 Correct Input Format 15 valid cycles 17 invalid cycles areset dkeririrvirirvrirruunnnrrnriruuiuiinrrvuuiuiinrriruiuiinnrru xin v 0 I I 0 I xin c 7 0 xn 0 70 TITS TITS TIT TS I3 TUI TIT ZT BI MIT 5 g TI2131415 xout v 0 T I 0 xut c 7 0 TTZTUITIZTUTTTZIUITIZTUTTIZTUITIZIUTTIZTUTTI Z IUITIZTUTTIZIUTTIZTIUTITIZ xout_0 17 0 8 T TOT 24T 6 T 121 181 U BFFF FFF FFEB xout_1 17 0 3Z 40 48 24 30T 361 i EFFEBFF SFFDG xout_2 17 0 S501 641 727 427 487 540 FFOBFFCBFFCI xout_3 17 0 80 887 96 GUT 66 727 U J3FFRAFFBIBFFAC xout_4 17 0 104 TII 120 78 847 907 U BFEABFFOBFES7 Figure 4 21 Incorrect Input Format 15 valid cycles 0 invalid cycles If the number of invalid cycles is less than 17 the output format is incorrect areset dk 1A FALTALEAL FALTA FA TEFAL FATA FA FALTA FATA TA FATA TA TATATATATATATATATATATATATATATATATATAI xin v 0 xin d7 0 xin 0 7 0 LI1213141516 171819 IWITMIUIBGIMITITIZ2131415 16 I7 18 19 JITIUITG MTTS xout_v 0 T I L I I xout c 7 0 TIT 1 1 Z IUITIZIUTTITI2TIUTITIZ2IU0TITIZ2TIUTITT2TIO0TITI1I2101112101112 10 T1 xout_0 17 0 re r erare rrr 9 xout_1 17 0 BEPA O D EE D O S OE D 6 xout_2 17 0 361 G T ZT AZ a U xout_3 17 0 J 80T 881 96 601 651721 0 xout_4 17 0 IU A
26. 1 0 U 09 3 Me y 33 1778 Y M J8 Related Information Loading Coefficients from a File on page 3 3 FIR II IP Core Coefficient Reloading You access the internal data coefficients via a memory mapped interface that consists of the input address write data write enable read data and read valid signals The Avalon Memory Mapped Avalon MM interfaces operate as read and write interfaces on the master and slave components in a memory mapped system The memory mapped system components include microprocessors memories UARTs timers and a system interconnect fabric that connects the master and slave interfaces The Avalon MM interfaces describe a wide variety of components from an SRAM that supports simple fixed cycle read and write transfers to a complex pipelined interface capable of burst transfers In Read mode the IP core reads the memory mapped coefficients over a specified address range In Write mode the IP core writes the coefficients over a specified address range In Read Write mode you can read or write the coefficients over a specified address range You can use a separate bus clock for this interface When you do not enable coefficient reloading option the processor cannot access the specified address range and the IP core does not read or write the coefficient data Coefficient reloading starts anytime during the filter run time However you must reload the coefficients only after you obtain all the desired output data to avo
27. 71 10 0 1 228 50 45 banks 0 Write Altera Corporation About the FIR II IP Core C Send Feedback FIR II IP Core Getting Started 2014 12 15 UG 01072 amp Subscribe CJ Send Feedback Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license Some Altera MegaCore IP functions require that you purchase a separate license for production use However the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software After you are satisfied with functionality and perfformance visit the Self Service Licensing Center to obtain a license number for any Altera product Figure 2 1 IP Core Installation Path acds S m quartus Contains the Quartus ll software ip Contains the Altera IP Library and third party IP cores altera Contains the Altera IP Library source code IP core name gt Contains the IP core source files m Note The default IP installation directory on Windows is drive Valtera version number on Linux it is home directory gt altera version number Related Information e Altera Licensing Site e Altera Software Installation and Licensing Manual OpenCore Plus IP Evaluation Altera s free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores i
28. Contains a shell script ves_setup sh to set up and run a VCS simulation synopsys vcsmx Contains a shell script vcsmx setup sh and synopsys sim setup file to set up and run a VCS MX simulation cadence Contains a shell script ncsim setup sh and other setup files to set up and run an NCSIM simulation submodules Contains HDL files for the IP core submodule lt child IP cores gt For each generated child IP core directory Qsys generates synth and sim sub directories Simulating Altera IP Cores in other EDA Tools The Quartus II software supports RTL and gate level design simulation of Altera IP cores in supported EDA simulators Simulation involves setting up your simulator working environment compiling simulation model libraries and running your simulation You can use the functional simulation model and the testbench or example design generated with your IP core for simulation The functional simulation model and testbench files are generated in a project subdirectory This directory may also include scripts to compile and run the testbench For a complete list of models or libraries required to simulate your IP core refer to the scripts generated with the testbench You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts NativeLink launches your preferred simulator from within the Quartus II software Altera Corporation FIR II IP Core Getting Started C Sen
29. Description C Send Feedback UG 01072 2014 12 15 Figure 4 13 Four Channels on Four Wires Channel Input and Output Format 4 15 valid L channel 0 data Y 0 j em y 09 00 oU c7 data0 Y 0 d dO aB du dU ji data1 data1 SW 3m S0 30 sA au f Channel Input and Output Format The FIR II IP core requires the inputs and the outputs to be in the same format when the number of input channel is more than one The input data to the MegaCore must be arranged horizontally according to the channels and vertically according to the wires The outputs should then come out in the same order counting along horizontal row first vertical column second Eight Channels on Three Wires Figure 4 14 Eight Channels on Three Wires Input def Vl Vi J xn v xn oy oyayraoga j xn 11 G YG YG xn 21 YOY YX Figure 4 15 Eight Channels on Three Wires Output Four Channels on Four Wires df WS V7 VJ xOut v xOut 0 xut T GT 6 x0ut 2Y c cy Figure 4 16 Four Channels on Four Wires Input FIR II IP Core Functional Description CJ Send Feedback dk VI xn v xn OY 0 jJ xn 1X jJ xn 2Y Q xn 3X1 GY Altera Corporation UG 01072 4 16 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 2014 12 15 Figure 4 17 Four Channels on Four Wires Output dk V xout v xOut Oy C J xOout 1f C J xOut_2 QC xOut_3 G
30. FIR II IP Core User Guide C Subsetib UG 01072 101 Innovation Drive 2014 12 15 San Jose CA 95134 li LJ Send Feedback www altera com TOC 2 FIR II IP Core User Guide Contents About the PUR TD IP Cor 4 3 ii5i HESI M K k rk renees 1 1 Altera DSP IP Core Peatites soe eek mte dies tae im Od M A a 1 1 IIS UNE LG CMT iic M 1 2 DSP IP Core Device Family Support quoquc denda saepe tur ona apris eq PQR Pp risiedi iiia 1 2 DSP IP Core Vertical oia aen DD EUR Eciam extend bleus 1 3 FIR II IP Core Release Information aee ascuederierit obi edad b od E QU RANA ses eR YR e pc Grid HHR 1 3 FIR II IP Core Performance and Resource UtIlPzatloDi uu eese baia ita eee ds oni bes as m aea 1 3 FIR II IP Core Getting Started ausis steer rtr E ERR DRE Y YO NU HEN EKE YE UT OE URH UE KY S HE 2 1 Installingand Licensing IPICOTES C M 2 1 OpenCore Plus IP Evaluation ee e ERR aka ete E NER ER ANA ERA 2 1 FIR II IP Core OpenCore Plus Timeout DelaviOtus soi o a tard gehen ennt cn n 2 2 IP Catalog and Parameter Editor sl n e alek pri p tr ERAT NOM Mta SHEER HAV H N 2 2 Specifying IP Core Parameters and ODtiOnS E eee diio pntat tueur eed des 2 3 Piles Generated for Altera IP GOT S eiecit kaleka ala bukeke kake nasek Ed rini du 2 5 Simulating Altera IP Cores in other EDA Tolg uiae erer erer erer rexe ke kerkere rexek kerek Aker 2 8 DSP Builder Design PIOW
31. Generated for Altera IP Cores The Quartus II software generates the following IP core output file structure FIR II IP Core Getting Started C Send Feedback Apply preset parameters fors specific applications 2 5 View IP port and parameter details Altera Corporation 2 6 Files Generated for Altera IP Cores Figure 2 4 IP Core Generated Files lt your_ip gt cmp VHDL component declaration file lt your_ip gt _bb v Verilog HDL black box EDA synthesis file lt your_ip gt _inst v or vhd Sample instantiation template lt your_ip gt ppf XML 1 0 pin information file lt your_ip gt qip Lists IP synthesis files lt your_ip gt sip Contains assingments for IP simulation files your ip generation rpt IP generation report lt your_ip gt debuginfo Contains post generation information lt your_ip gt html Connection and memory map data lt your_ip gt bsf Block symbol schematic lt your_ip gt spd Combines simulation scripts for multiple cores lt your_ip gt v or vhd Top level simulation file f lt your_ip gt v or hd Top level IP synthesis file A HDL files gt an lt simulator_setup_scripts gt Table 2 1 IP Core Generated Files lt testbench gt _tb testbench system 4 testbench tb testbench files simulation files l
32. OK Specify the parameters and options for your IP variation in the parameter editor including one or more of the following Refer to your IP core user guide for information about specific IP core parameters e Optionally select preset parameter values if provided for your IP core Presets specify initial parameter values for specific applications e Specify parameters defining the IP core functionality port configurations and device specific features e Specify options for processing the IP core files in other EDA tools Click Generate HDL the Generation dialog box appears Specify output file generation options and then click Generate The IP variation files generate according to your specifications To generate a simulation testbench click Generate gt Generate Testbench System To generate an HDL instantiation template that you can copy and paste into your text editor click Generate HDL Example Click Finish The parameter editor adds the top level qsys file to the current project automatically If you are prompted to manually add the qsys file to the project click Project Add Remove Files in Project to add the file After generating and instantiating your IP variation make appropriate pin assignments to connect ports FIR II IP Core Getting Started C Send Feedback UG 01072 2014 12 15 Figure 2 3 IP Parameter Editor Files Generated for Altera IP Cores
33. OP UI U Figure 4 22 Correct Input Format 15 valid cycles 20 invalid cycles areset dk FA P Err ASAA Ar Ar AE A AAA AAAA TT T 2 T 2 7y ES JT FTLFy TEL FLTE TJ xin v 0 I I iu I xin d7 0 xin 0 7 0 ITS TET TE 17 13 TS T0 T31T 7T 3134 1551 8 r xout_v 0 1 T T xout_ 7 0 T T2 TT T3 12 et 19 T1131 2 LUTTTI2TVTTI12T0171312T17 17 xout 0 17 0 L 36124 T 2I 18 9 BFFFIBFFF2 xout_1 17 0 C32 40 28 247 307 361 0 prFEA 3FFDD xout 2 17 0 rar 64 72 42 48 34 0 BFFCFBFFCS xout_3 17 0 Ir 3013881961 60 661 72 0 BFFBABFFB3 xout_4 17 0 Co A 781 8900 GEFASBEFSE 22 Channels with 11 Valid Cycles and 9 Invalid Cycles An example where the clock rate 200 sample rate 10 yields a TDM factor of 20 inputChannelNum 22 and interpolation factor is 10 In this case the TDM factor is less than inputChannelNum The optimization produces a filter with PhysChanIn 2 ChansPerPhyIn 11 PhysChanOut 11 and ChansPerPhyOut 2 The input format in this case is 20 cycles long which comes from the TDM factor The number of channels is 22 so the filter expects 11 ChansPerPhylIn valid cycles followed by 9 invalid cycles TDM factor ChansPerPhyIn 20 11 Y FIR II IP Core Functional Description Altera Corporation C Send Feedback 22 Channels with 11 Valid Cycles and 9 Invalid Cycles UG 01072
34. alf Fractional 195 2 251 12 26 Band Rate 1 1 Half Fractional Write 26 7 2 299 15 25 Band Rate 2 1 Interpolation 262 5 296 25 25 2 1 super Interpolation 708 32 914 34 27 sample 2 1 super Interpolation Write 841 32 1 297 32 25 sample 9 1 Interpolation Write 400 5 382 12 25 8 1 Half Interpolation 288 3 456 13 29 Band i 1 Half Interpolation Write 331 4 315 9 29 Band 9 1 Single rate 87 10 142 14 25 3 1 super Single rate 258 20 315 33 26 sample 0 Altera Corporation About the FIR II IP Core C Send Feedback UG 01072 ee 2014 12 15 FIR II IP Core Performance and Resource Utilization Single rate 20 sample fmax MHz 27 4 Single rate Write 227 10 0 535 0 Single rate Band i 1 Half Single rate Write 274 5 0 506 19 27 Band 1 Single rate Multiple 110 10 0 187 41 25 banks 5 1 Single rate Multiple 375 10 0 349 32 25 banks 5 Write Table 1 5 FIR II IP Core Performance Stratix V Devices Typical expected performance using the Quartus II software with Stratix V BORNE devices fmax MHz Decimation 1 609 24 1 231 45 0 8 p Decimation Write 2 319 24 0 2 077 66 45 0 8 2 Fractional 1 350 16 0 2 099 88 44 Rate 8 8
35. annels with 4 coefficient banks ast_sink_data 9 8 BankIn 0 ast sink data 7 0 xln O ast sink data 19 18 BankIn 1 ast sink data 17 10 xln 1 ast sink data 29 28 BankIn 2 ast sink data 27 20 xln 2 ast sink data 39 38 BankIn 3 ast sink data 37 30 xln 3 ast sink sop Input 1 Marks the start of the incoming sample group The start of packet SOP is interpreted as a sample from channel 0 ast_sink_eop Input 1 Marks the end of the incoming sample group If data is associated with N channels the end of packet EOP must be driven high when the sample belonging to the last channel that is channel N 1 is presented at the data input FIR II IP Core Functional Description C Send Feedback Altera Corporation 4 10 FIR II IP Core Signals UG 01072 2014 12 15 ENLC EENLI ZEE NE HEKER ast sink error Input Error signal indicating Avalon ST protocol violations on the sink side e 00 No error 01 Missing SOP e 10 Missing EOP e 11 Unexpected EOP Other types of errors are also marked as 11 ast_source_ready Input The downstream module asserts this signal if it is able to accept data This signal is not available when backpressure is turned off ast_source_valid Output The IP core asserts this signal when there is valid data to output ast_source_channel Output Log number of channels per wire Indicates the index of the channel w
36. binary fractional number has the format sign integer bits gt lt fractional bits A signed binary fractional number is interpreted as shown below sign lt x integer bits gt lt y fractional bits Original input data sign x integer bits gt lt y fractional bits Original coefficient data sign i integer bits gt lt y y fractional bits Full precision after FIR calculation sign lt x integer bits y fractional bits Output data after limiting precision where i ceil log number of coefficients x x For example if the number has 3 fractional bits and 4 integer bits plus a sign bit the entire 8 bit integer number is divided by 8 which gives a number with a binary fractional component The total number of bits equals to the sign bits integer bits fractional bits The sign integer bits is equal to Input Bit Width Input Fractional Bit Width with a constraint that at least 1 bit must be specified for the sign FIR II IP Core Parameters Altera Corporation CJ Send Feedback P UG 01072 3 6 MSB and LSB Truncation Saturation and Rounding 2014 12 15 MSB and LSB Truncation Saturation and Rounding The output options on the parameter editor allow you to truncate or saturate the MSB and to truncate or round the LSB Saturation truncation and rounding are non linear operations Table 3 4 Options for Limiting Precision Bit Option Result Range Truncat In truncati
37. ble i signal low causes the FIR IL IP core to stop From the output side backpressure drives the enable i signal of the FIR IL IP core If the downstream module can accept data again the FIR II IP core is instantly re enabled When the packet size is greater than one multichannel the source interface expects your application to supply the count of data starting from 1 to the packet size When the source interface receives the valid flag together with the ata count 1 it starts sending out data by driving both the ast source sop and ast source valid signals high When data count equals the packet size the ast source eop signal is driven high together with the ast source valid signal If the downstream components are not ready to accept any data the source interface drives the source stall signal high to tell the design to stall Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 Figure 4 6 Multiple Channels on Multiple Wires Avalon ST Source Interface 4 7 The FIR II IP core to the source interface when transferring a packet of data over multiple channels on multiple wires FIR Compiler ll MegaCore Function Controller FIR Filter source stall source valid xOut v xOut c xOut_0 7 0 xOut_1 7 0 Only available xOut_2 7 0 Source Avalon Streaming SCFIFO when backpressure ast_source_valid
38. core Filter IP Catalog to Show IP for active device family or Show IP for all device families If you have no project open select the Device Family in IP Catalog Type in the Search field to locate any full or partial IP core name in IP Catalog Right click an IP core name in IP Catalog to display details about supported devices open the IP core s installation folder and view links to documentation Click Search for Partner IP to access partner IP information on the Altera website Figure 2 2 Quartus II IP Catalog IP Catalog i ES Device Family Cyclone V E GX GT SX SE ST H an isi d d eit dek deki de G r da Show IP only for target device a meme ERI Search for installed IP cores j v 45 Installed IP Refresh IP catalog Ctri R v Project Directory No Selection Available v Show IP for all device families v Library Show IP for active device family g lt Basic Functions P Arithmetic gt Bridges and Adaptors 7 Clocks PLLs and Resets amp ALTCLKCTRL penne Double click to customize right click for ALTCLKCTRL P PLL detailed information gt Configuration anc REM b 1 0 Add version 15 0 b Miscellaneous Detalls ALTCLKCTRL altcikctri gt On Chip Memory Altera Corporation gt Simulation Debug and Verification installed version 25 0 b DSP Supported Device Families Arria II GZ Arria V Arria V GZ Cyclone IV E Cyclone V b Interface Protocols Ama 10 Ama li GX
39. d Feedback UG 01072 2014 12 15 DSP Builder Design Flow 2 9 Figure 2 5 Simulation in Quartus Il Design Flow Quartus Il Design Flow Analysis amp Synthesis Fitter place and route TimeQuest Timing Analyzer Device Programmer Design Entry HDL Qsys DSP Builder EDA Netlist Writer Altera Simulation Models s Gate Level Simulation Post synthesis Post synthesis functional simulation netlist Post fit functional simulation netlist Post fit timing functional simulation Post fit functional simulation Optional Post fit simulation netlist timing simulation Note Post fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current version of the Quartus II software Altera IP supports a variety of simulation models including simulation specific IP functional simulation models and encrypted RTL models and plain text RTL models These are all cycle accurate models The models support fast functional simulation of your IP core instance using industry standard VHDL or Verilog HDL simulators For some cores only the plain text RTL model is generated and you can simulate that model Use the simulation models only for simulation and not for synthesis or any other purposes Using these models for synthesis creates a nonfunctional design Related Information Simulating Altera Designs
40. ded support for Arria V GZ devices 2012 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services NDS p AN 101 Innovation Drive San Jose CA 95134
41. dual memories greater than 200 bits as M9K blocks and dual memories less than or equal to 200 bits as MLAB blocks Note For device families with only one type of memory block this threshold has no effect Using M RAM Threshold This threshold is the trade off between medium and large RAM blocks For larger delays implement memory in medium block RAM M4K M9K or use larger M RAM blocks M512K M144K 1 Set the number of bits in a memory or delay greater than this threshold to use M RAM 2 Set a large value such as the default of 1 000 000 bits to never uses M RAM blocks Using Hard Multiplier Threshold This threshold is the trade off between hard and soft multipliers For devices that support hard multipliers or DSP blocks use these resources instead of a soft multiplier made from LEs For example a 2 bit x 10 bit multiplier consumes very few LEs The hard multiplier threshold value corresponds to the number of LEs that save a multiplier If the hard multiplier threshold value is 100 you are allowing 100 LEs Therefore an 18 x 18 multiplier that requires approximately 182 350 LEs is not transferred to LEs because it requires more LEs than the threshold value However the IP core implements a 16 x 4 multiplier that requires approximately 64 LEs as a soft multiplier with this setting 1 Set the default to always use hard multipliers With this value IP core implements a 24 x 18 multiplier as two 18 x 18 multipliers 2 Set a va
42. e coefficients in another applica tion such as MATLAB or a user created program save the coefficients to a file and import them into the FIR IL IP core Related Information Loading Coefficients from a File on page 3 3 Filter Specification Parameters Table 3 1 Filter Specification Parameters Filter Settings Filter Type Single Rate Specifies the type of FIR filter Decimation Interpolation Fractional Rate Interpolation Factor 1 to 128 Specifies the number of extra points to generate between the original samples Decimation Factor 1 to 128 Specifies the number of data points to remove between the original samples Number of Channels 1 128 Specifies the number of unique input channels to process Frequency Specification 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility o
43. e feature do not delete these files When the evaluation time expires the ast source data signal goes low Related Information AN 320 OpenCore Plus Evaluation of Megafunctions IP Catalog and Parameter Editor The Quartus II IP Catalog Tools IP Catalog and parameter editor help you easily customize and integrate IP cores into your project You can use the IP Catalog and parameter editor to select customize and generate files representing your custom IP variation Note The IP Catalog Tools IP Catalog and parameter editor replace the MegaWizard Plug In Manager for IP selection and parameterization beginning in Quartus II software version 14 0 Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores The IP Catalog lists installed IP cores available for your design Double click any IP core to launch the parameter editor and generate files representing your IP variation The parameter editor prompts you to specify an IP variation name optional ports and output file generation options The parameter editor generates a top level Osys system file qsys or Quartus II IP file qip representing the IP core in your project You can also parameterize an IP variation without an open project Altera Corporation FIR II IP Core Getting Started C Send Feedback UG 01072 2014 12 15 Specifying IP Core Parameters and Options 2 3 Use the following features to help you quickly locate and select an IP
44. eaming Interface Signals Check ast_sink_sop ast_sink_eop ast_sink_valid ast_sink_data 23 ast_sink_ready sink ready packet error xn 2 7 0 Controller FIR Filter FIR II IP Core Functional Description C Send Feedback Altera Corporation UG 01072 4 6 Avalon ST Source Interface 2014 12 15 Figure 4 5 Timing Diagram of Multiple Channels on Multiple Wires The sink interface to the FIR II IP core when transferring a packet of data over multiple channels on multiple wires The data width of each channel is 8 bits Number of channels 6 clock rate 200 MHz and sample rate 100 MHz dk AST Xl Xd Xf US Xd X 4 U Xd Xd t 1 ast sink valid aaa ast_sink_data 7 0 J 0 y B y M y 98 y yy E ast sink datayia oc y DO Y a ym yo y y ast sink data 23 16 ast sink sop _ J L A ast_sink_eop 1 xln_v7 J Ne xin _0 7 0 X jm y9m ymy By uy By xIn 1 7 0 X Lo yp yay vy cy my xIn 2 7 0 Avalon ST Source Interface The source interface can handle single or multiple channels on a single wire and multiple channels on multiple wires The IP core includes an Avalon ST FIFO in the source wrapper when the backpressure support is turned on The Avalon ST FIFO controls the backpressure mechanism and catches the extra cycles of data from the FIR II IP core after backpressure On the input side of the FIR II IP core driving the ena
45. efficient Data coefficient input width coeff_out_valid Output 1 Coefficient read valid signal coeff_out_data Output Coefficient Data coefficient output The coefficient in memory at width the address specified by coe in address FIR II IP Core Time Division Multiplexing The FIR II IP core optimizes hardware utilization by using time division multiplexing TDM The TDM factor or folding factor is the ratio of the clock rate to the sample rate By clocking a FIR II IP core faster than the sample rate you can reuse the same hardware For example by implementing a filter with a TDM factor of 2 and an internal clock multiplied by 2 you can halve the required hardware Figure 4 8 Time Division Multiplexing to Save Hardware Resources Clock Rate Sample Rate Read Write Clock Rate 2 x Sample Rate Read Serialize L gt T gt Deserialize Write FIR II IP Core Functional Description Altera Corporation send Feedback 4 12 UG 01072 FIR II IP Core Multichannel Operation 2014 12 15 To achieve TDM the IP core requires a serializer and deserializer before and after the reused hardware block to control the timing The ratio of system clock frequency to sample rate determines the amount of resource saving except for a small amount of additional logic for the serializer and deserializer Table 4 2 Estimated Re
46. hich the maximum None coefficient value equals the maximum possible value for a given number of bits Select None to read in pre scaled integer values for the coefficients and disable scaling Coefficient Data Signed Binary Specifies the coefficient input data type Select Type Signed Fractional Binary to monitor which bits Signed Eractional Binary are preserved and which bits are removed during the filtering process Coefficient Bit 2 32 Specifies the width of the coefficients The default Width value is 8 bits Coefficient 0 32 Specifies the width of the coefficient data input Fractional Bit Width into the filter when you select Signed Fractional Binary as your coefficient data type Frequency Response Display Edit Current Bank Import from file 0 Number of coefficient bank URL Specifies the coefficient bank to display in the coefficient table and frequency response graph Specifies the file from which to load coefficients Loading Coefficients from a File When you import a coefficient set the wizard shows the frequency response of the floating point coefficients in blue and the frequency response of the fixed point coefficients in red FIR II IP Core Parameters CJ Send Feedback Altera Corporation 3 4 Input and Output Options UG 01072 2014 12 15 The FIR II IP core supports scaling on the coefficient set 1 Click Import coefficients in the File name box specify the
47. hose result is presented at the data output ast source data Output Data width x number of channel output wires PhysChanOut FIR IL IP core filter output For a multichannel operation number of channel output wires gt 1 the least significant bits of ast source data are mapped to xout 0 of the FIR IL IP core filter For example xOut 0 7 0 gt ast source data 7 0 xOut L A J DIJ E gt ast source data l5 8 xOut 2 7 0 ast_source_data 23 16 ast source sop Output Marks the start of the outgoing FIR IL IP core filter result group If 1 a result corresponding to channel 0 is output asl soures COD Output Marks the end of the outgoing FIR II IP core filter result group If 1 a result corresponding to channels per wire N 1 is output where N is the number of channels per wire ast source error Output Error signal indicating Avalon ST protocol violations on the source side e 00 No error 01 Missing SOP e 10 Missing EOP e 11 Unexpected EOP Other types of errors are also marked as 11 Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 FIR II IP Core Time Division Multiplexing 4 11 ENCCENELCCUNEI NN NE CNN NN coeff in address Input Number of Address input to write new coefficient data coefficients coeff in we Input 1 Write enable for memory mapped coefficients coeff_in_data Input Co
48. id unpredictable results If you use multiple coefficient banks you can reload coefficient banks that are not used and switch over to the new coefficient set when coefficient reloading is complete You must toggle the coeff in areset signal before reloading FIR II IP Core Functional Description Altera Corporation C Send Feedback UG 01072 4 22 FIR II IP Core Coefficient Reloading 2014 12 15 the coefficient with new data The new coefficient data is read out after coefficient reloading to verify whether the coefficient reloading process is successful When the coefficient reloading ends by deasserting the coeff_in_we the input data is inserted immediately to the filter that is reloaded with the new coefficients The symmetrical or anti symmetrical filters have fewer genuine coefficients use fewer registers and require fewer writes to reload the coefficients For example only write the first 19 addresses for a 37 tap symmetrical filter When you write to all 37 addresses the IP core ignores last 18 addresses because they are not part of the address space of the filter Similarly reading coefficient data from the last 18 addresses is also ignored When the FIR uses multiple coefficient banks it arranges the addresses of all the coefficients in consecu tive order according to the bank number The following example shows a 37 tap symmetrical anti symmetrical filter with four coefficient banks e Address 0 18 Bank 0 e Address 19 37 Ba
49. in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU S RYA 101 Innovation Drive San Jose CA 95134 UG 01072 4 2 Avalon ST Interfaces in DSP IP Cores 2014 12 15 higher clock rate by driving the ast source ready signal of the FIR II IP core high and not connecting the ast_sink_ready signal The sink and source interfaces implement the Avalon ST protocol which is a unidirectional flow of data The number of bits per symbol represents the data width and the number of symbols per beat is the number of channel wires The IP core symbol type supports signed and unsigned binary format The ready latency on the FIR II IP core is 0 The clock and reset interfaces drive or receive the clock and reset signals to synchronize the Avalon ST interfaces and provide reset connectivity Related Information Avalon Interface Specifications For more information about the Avalon ST interface properties protocol and the data transfer timing Avalon ST Interfaces in DSP IP Cores Avalon ST interfaces define a standard flexible and modular protocol for data transfers from a source interface to a sink interface The input interface is an Avalon ST sink and the output interface is an Avalon ST source The Avalon ST interface supports packet transfers with packets interleaved across multiple channels
50. ink valid ast sink data 9 00 J 256 478 179 118 408 259 159 135 427 B3 79 122 481 39 5 48 29 262 bankin_0 1 02 LTYZ7Y7T3 0 T2731 07T 27 3 0 Ty 2 Ys 19091112 xin_0 7 0 0 31 7 m Mu 3 1 07 PA 8 79 79f T2 3T 161 451 24 T 83 6 xout v O U L1 xout_0 21 0 431127 Figure 4 29 Timing Diagram of a Four Channel Filter with 4 Coefficient BanksEach channel has a separate corresponding coefficient set The bank inputs for different channels are driven with their channel number respectively throughout the filter operation dk Wo A Ez s I TAY ay RN a NE TA pas RN s RN pm RN as RN A ast sink valid ast sink data 39 0 ets Us 55 Y 20 23 30 30 716 21 724 s IE E12 74 725 JU 26 X 729 720 80 7 13 bankin_0 1 0 0 xin 0 7 0 U 31 241 85 9 3 b 18 7 YE 2 Y 47 1 78 1 96 1 4 7 1 7 X 8 y 30 8 bankin 1 1 070 r xin_1 7 0 U 37 Y 9 Y 701 Y 8 y BZ 271 35 TS T2028 1 41 T_T aa y 0 1 33 bankin_2 1 0 0 rz xin 2 7 0 0 30 371 227 4 292 1721 75 1 U Uyp DI y 8 35 y D 32 3 2 Sa TV y 7 X 9 IY bankin 3 1 070 r3 xin 3 7 0 U IJ 396 y 33 f 29 CHI 3 2 y 75 ZX 4y 3 ZIX 8 4 Z y 9 8 X 15 YX xout_v 0 0 r xout_0 21 0 0 87 TT TAT y 16 aT S xout_1 21 010 us Y TO Y 157 Y 417 y S04 Y 364 TZ xout_2 21 0 0 36 83 33 ZI9 M8 1 407 J5 xout 3 2
51. ion FIR II IP Core Parameters C Send Feedback UG 01072 2014 12 15 Signed Fractional Binary 3 5 Output Data Type Signed Binary Specifies whether the output data is in a signed Sead Fractional binary ora signed fractional binary P Select uy Signed Fractional Binary to monitor which bits the IP core preserves and which bits it removes during the filtering process Output Bit Width 0 32 Specifies the width of the output data with limited precision from the filter Output Fractional Bit 0 32 Specifies the width of the output data with limited Width precision from the filter when you select Signed Fractional Binary as your output data Output MSB rounding Truncation Specifies whether to truncate or saturate the most Saturating significant bit MSB MSB Bits to Remove 0 32 Specifies the number of MSB bits to truncate or saturate The value must not be greater than its corresponding integer bits or fractional bits Output LSB rounding Truncation Rounding Specifies whether to truncate or round the least significant bit LSB LSB Bits to Remove 0 32 Specifies the number of LSB bits to truncate or round The value must not be greater than its corresponding integer bits or fractional bits Signed Fractional Binary The FIR IL IP core supports two s complement signed fractional binary notation which allows you to monitor which bits the IP core preserves and which bits it removes during filtering A signed
52. ion Multiple 395 3 483 44 31 banks 0 8 Decimation Multiple 510 3 472 40 29 banks 1 Write 8 Fractional 661 5 877 75 31 Rate 0 8 Fractional Write 788 5 936 98 30 Rate 9 Altera Corporation About the FIR II IP Core C Send Feedback UG 01072 2014 12 15 Parameters FIR II IP Core Performance and Resource Utilization Memory fmax _ i eim ie DSP Interpolation 5 27 8 8 1 Interpolation Write 514 5 540 p 27 8 8 1 Single Rate 493 10 191 20 27 8 8 1 Single Rate Write 633 10 588 1 p 8 1 Decimation 220 13 158 27 31 0 lsuper Decimation 404 20 400 41 30 sample 5 lsuper Decimation Write 505 20 785 35 30 sample 8 1 Decimation Write 318 3 208 26 30 9 1 Half Decimation 234 3 192 34 30 Band 1 Half Decimation Write 320 13 232 27 30 Band 1 Fractional 297 3 504 57 31 Rate 0 1 Fractional Write SONIS 563 56 31 Rate 0 1 Half Fractional 196 2 251 5 27 Band Rate 7 1 Half Fractional Write 266 2 301 15 28 Band Rate 0 1 Interpolation 266 5 290 30 27 8 l super Interpolation 717 32 903 45 30 sample 8 lsuper Interpolation Write 842 32 1 2281 48 30 sample 8 1 Interpolation Write 405 5 380 15 27 8
53. ion FIR II IP Core Parameters C Send Feedback UG 01072 2014 12 15 Using CDelay RAM Block Threshold 3 7 Device Family Menu of supported Specifies the target device family devices Speed grade Fast medium slow Specifies the speed grade of the target device to balance the size of the hardware against the resources required to meet the clock frequency CDelay RAM Block Integer Specifies the balance of resources between LEs Small Threshold RAM block threshold in bits CDual Mem Dist Integer Specifies the balance of resources between small to RAM Threshold medium RAM block threshold in bits M RAM Threshold Integer Specifies the balance of resources between medium to large RAM block threshold in bits Hard Multiplier Integer Specifies the balance of resources between LEs DSP Threshold block multiplier threshold in bits The default value is 1 Symmetry Option Symmetry Mode Non Symmetry Specifies whether your filter design uses non Sommer symmetric symmetric or anti symmetric coefficients y The default value is Non Symmetry Anti Symmetrical These topics describe the memory and multiplier threshold trade offs and provide some usage examples Using CDelay RAM Block Threshold This threshold is the trade off between simple delay LEs and small ROM blocks If any delay s size is such that the number of LEs is greater than this parameter the IP core implements delay as block RAM To make more delays
54. lter xOut 0 gt ast sink error gt t xn n 1 xOut m 1 ast source error m ast_sink_read bankin n 1 p ast_source_ready FIR II IP Core Interfaces and Signals The IP core uses an interface controller for the Avalon ST wrapper that handles the flow control mechanism The IP core communicates control signals between the sink interface FIR filter and source interface via the controller When designing a datapath that includes the FIR II IP core you might not need backpressure if you know the downstream components can always receive data You might achieve a O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to
55. lue of approximately 300 to keep 18 x 18 multipliers hard but transform smaller multipliers to LEs The IP core implements a 24 x 18 multiplier as a 6 x 18 multiplier and an 18 x 18 multiplier so this setting builds the hybrid multipliers that you require 3 Set a value of approximately 1 000 to implement the multipliers entirely as LEs Essentially you are allowing a high number 1000 of LEs to save using an 18 x 18 multiplier 4 Set a value of approximately 10 to implement a 24 x 16 multiplier as a 36 x 36 multiplier With the value you are not even allowing the adder to combine two multipliers Therefore the system has to burn a 36 x 36 multiplier in a single DSP block Altera Corporation FIR II IP Core Parameters C Send Feedback FIR II IP Core Functional Description 2014 12 15 UG 01072 amp Subscribe CJ Send Feedback The FIR II IP core generates the Avalon ST register transfer level RTL wrapper Figure 4 1 High Level Block Diagram of FIR II IP core with Avalon ST Interface FIR Compiler Il MegaCore Function ast sink valid control signals control signals ast_source_valid Controller P ast source data ast sink data i gt gt control signals ast_source_so xin v xOut v ep ast sink sop gt ast source eop Sink xin 0 xOut c Source gt ast_sink_eop bankl iR ast_source_channel ankIn O Fi
56. n simulation and hardware before purchase You need only purchase a license for MegaCore IP cores if you decide to take your design to production OpenCore Plus supports the following evaluations O 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 2 2 FIR II IP Core OpenCore Plus Timeout Behavior Prinses e Simulate the behavior of a licensed IP core in your system e Verify the functionality size and speed of the IP
57. nk 1 e Address 38 56 Bank 2 e Address 57 75 Bank 3 The following example shows a 37 tap non symmetrical anti symmetrical filter with 2 coefficient banks e Address 0 36 Bank 0 e Address 37 73 Bank 1 If the coefficient bit width parameter is equal to or less than 16 bits the width of the write data is fixed at 16 bits If the coefficient bit width parameter is more than 16 bits the width of the write data is fixed at 32 bits Figure 4 30 Timing Diagram of Coefficient Reloading in Read Write modeWith nine coefficients a JuuuuvuvwvuuuuuwuyVWuwvwuyuwuwywuuywWWwWYWWWwWVWW coeff in areset J coeff in addres 110 71 jen Ga l Xs ofa jsf fo l fats fof fs J coeff in data 15 0 1 1451 50 7 1121432 fae 1 oa 4124 2 coeff in we 0 coeff out data 15 0 0 26 25 13 Yao J127 so o 2e oY 4 50 7 Kn one f 1 fos fas 4s coeff out valid Ol The IP core performs a write cycle of 9 clock cycles to reload the whole coefficient data set To complete the write cycle assert the coe in we signal and provide the address from base address to the max address together with the new coefficient data Then load the new coefficient data into the memory corresponding to the address of the coefficient The IP core reads new coefficient data during the write cycle when you deassert the coe in we signal When the coeff_out_valid signal is high the read data is available on c
58. nputs Altera Corporation The data inputs and outputs for the FIR II IP core blocks can be vectors Use this capability when the clock rate is insufficiently high to carry the total aggregate data For example 10 channels at 20 MSPS require 10 x 20 200 MSPS aggregate data rate If you set the system clock rate to 100 MHz two wires are required to carry this data and so the FIR II IP core uses a vector of width 2 This approach is unlike traditional methods because you do not need to manually instantiate two FIR filters and pass a single wire to each in parallel Each FIR II IP core block internally vectorizes itself For example a FIR II IP core block can build two FIR filters in parallel and wire one element of the vector up to each FIR The same paradigm is used on outputs where high data rates on multiple wires are represented as vectors The input and output wire counts are determined by each FIR II IP core based on the clock rate sample rate and number of channels The output wire count is also affected by any rate changes in the FIR II IP core If there is a rate change such interpolating by two the output aggregate sample rate doubles The output channels are then packed FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 Channelization 4 13 into the fewest number of wires vector width that will support that rate For example an interpolate by two FIR II IP core filters might have two wires at
59. oeff out data Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 FIR II IP Core Coefficient Reloading 4 23 Figure 4 31 Timing Diagram of Coefficient Reloading in Write mode In this mode the IP core loads one coefficient data The new coefficient data 123 loads into a single address 7 de PL UI AJ A Pe A J Pee 14140147 coeff_in_areset_ coeff in address 11 0 1 N 7 i coeff in data 15 0 0 Y 123 o coeff in we 0 Figure 4 32 Timing Diagram of Coefficient Reloading in Read mode When the coeff_in_address is 3 the IP core reads coefficient data at the location the coefficient data 80 is available on coeff_out_data when the coeff_out_valid signal is high w S P A UU i CJ i LJ ee a coeff in areset coeff in address 11 0 a 3 a coeff_out_data 15 0 0 I 0 80 coeff out validfol Figure 4 33 Timing Diagram of Multiple Coefficient Banks It is a symmetry 13 tap filter The IP core reloads coefficients data of bank 1 address 7 13 while the filter is running on bank 0 When the coefficient reloading is completed bank 1 is used to produce an impulse response of the filter and you can observe the new coefficient data 58 18 106 from bank 1 on the filter output a UU UU UU UU Ur xin v 0 bankin O 0 xin 07 0 51 14 48 33 11211251 1
60. oeff_in_areset Input 1 Asynchronous active high reset signal for the coefficient reloading mechanism ast_sink_ready Output 1 FIR filter asserts this signal when can accept data in the current clock cycle This signal is not available when backpressure is turned off ast_sink_valid Input 1 Assert this signal when the input data is valid When ast sink validis not asserted the FIR processing stops until you re assert the ast sink valid signal Altera Corporation FIR II IP Core Functional Description C Send Feedback UG 01072 2014 12 15 FIR II IP Core Signals 4 9 HEME KZK EKEN NE CO NN ast sink data Input Data width Sample input data For a multichannel operation Bank width x number of channel input wires gt 1 the least signifi the number of cant bits of ast_sink_data are mapped to x1n 0 of channel input the FIR II IP core filter THIS For example PhysChanIn pe ast sink data 7 0 gt xln_0 7 0 where ink 15 8 xin 1 7 Bank width ast sink data 15 8 xln_1 7 0 Log2 Number ast_sink_data 23 16 gt xln 2 7 0 of coefficient i SE s la For multiple coefficient banks the most significant bits of the channel data are mapped to the bank input signal and the LSBs of the channel data are mapped to the data input signal For example Single channel with 4 coefficient banks ast_sink_data 9 8 gt BankIn 0 ast sink data 7 0 gt xln 0 Multi channel 4 ch
61. on the filter disregards specified bits e MSB Saturate In saturation if the filtered output is greater than the maximum positive or negative value that can be represented the output is forced or saturated to the maximum positive or negative value Truncat Same process as for MSB LSB E Round The output is rounded away from zero Figure 3 1 Removing Bits from the MSB and LSB Bits Removed from MSB Bits Removed from LSB Bits Removed from both MSB amp LSB D15 D15 D11 D15 D14 D14 D10 D14 D13 D3 gt D12 D12 D11 D9 D10 gt D8 D1 V eM D9 D4 DO b1 D8 D3 D3 D2 p2 Do Full Lined hjul Limited hjul Limited Pregision Precision Pregision Precision Precision Precision Memory and Multiplier Trade Offs When the Quartus II software synthesizes your design to logic it often creates delay blocks The FIR II IP core tries to balance the implementation between logic elements LEs and memory blocks M512 M4K M9K or M144K The exact trade off depends on the target FPGA family but generally the trade off attempts to minimize the absolute silicon area used For example if a block of RAM occupies the silicon area of two logic array blocks LABs a delay requiring more than 20 LEs two LABs is implemented as a block of RAM However you want to influence this trade off Table 3 5 Implementation Options Resource Optimization Settings Altera Corporat
62. p Fractional Write 1 771 16 0 2 291 78 45 Rate 0 8 2 Fractional 1 457 16 0 2 213 88 44 Rate 4 8 p Fractional Write 1 873 16 0 2 418 89 45 Rate 0 8 2 Interpolation 1 777 32 0 2 303 15 44 4 8 2 Interpolation Write 2 081 32 0 3 009 26 45 0 8 2 Interpolation Multiple 1 825 32 0 2 173 39 43 banks 0 About the FIR II IP Core Altera Corporation CJ Send Feedback UG 01072 1 10 FIR II IP Core Performance and Resource Utilization 2014 12 15 Interpolation Multiple 2 652 192 2 842 42 banks 4 Write 8 Single rate 920 20 0 332 2 44 4 8 Single rate Write 1 359 20 0 1 323 1 45 0 8 Decimation 340 3 0 324 25 45 0 8 Decimation Write 463 3 0 457 29 45 0 8 Decimation Multiple 466 3 0 569 42 45 banks 0 8 Decimation Multiple Sy J 0 567 41 45 banks 0 Write 8 Fractional 709 5 0 870 45 45 Rate 0 8 Fractional Write 852 5 0 991 65 45 Rate 0 8 Interpolation 216 5 0 197 13 45 0 8 Interpolation Write 361 5 0 290 po 45 0 8 Single Rate 483 10 0 212 4 44 7 8 Single Rate Write 783 10 0 894 4 45 0 1 Decimation 215 13 0 175 10 45 0 1 super Decimation 547 20 0 1 1167 88 45 sample 0 1 super Decimation Write 989 20 0 2 214 105 45 sample 0 1 Decimation Write 331 3 0 310 7 45 0 Altera Corporation About the FIR II IP Core C Send Feedback UG
63. r liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 3 2 Filter Specification Parameters UG 01072 2014 12 15 Clock Frequency 1 500 Specifies the frequency of the input clock MHz Clock Slack Integer Enables you to control the amount of pipelining independently of the clock frequency and therefore independently of the clock to sample rate ratio Input Sample Rate Integer Specifies the sample rate of the incoming data MSPS Coefficient Options Coefficient Scaling Auto Specifies the coefficient scaling mode Select Auto to apply a scaling factor in which the maximum None i coefficient value equals the maximum possible value for a given number of bits Select None to read in pre scaled integer values for the coefficients and disable scaling Coefficient Data Signed Binary Specifies the coefficient input data type Select Type 3 Signed Fractional Binary to monitor which bits Be caterer are preserved and which bits are removed during the filtering process Coefficient Bit 2 32 Specifies the width of the coefficients The default Width value is 8 bit
64. rPhyOut 1 Figure 4 26 Super Sample Rate Filter clkRate 100 inputRate 200 with inChans 1A0 is the first sample of channel A A1 is the second sample of channel A and so forth dk fU i54 LI UM uL Lf xui xin v J xn 0 Y A A2 y M4 YAS y A y A0 y A2 YAM YAMS y A8 y A20 y A22 A24 Mey A28 xOut 0 00 AO Vg Mj Ae j AB Y AIO Y Aj AM xOut_1 00 I Y4 AS Y Av Y AD Y ATT Y Ay A5 FIR II IP Core Functional Description Altera Corporation CJ Send Feedback er UG 01072 4 20 FIR II IP Core Multiple Coefficient Banks 2014 12 15 Figure 4 27 Super Sample Rate Filter clkRate 100 inputRate 200 with inChans 2If inputChannelNum 2 ger f f LJ XT A LT VU VU hdi LJ eee 0 QA xin v xn OX oy Vy A4 y AG y A8 Y A0 Y AV Y M24 Y M6 y AIS A20 y A22 y A24 y A26 y A28 y xn 1A 9 e Y XNYA AL AB A5 TAT YAW TRT J A3 M5 J A7 T A9 y xn 3 A 98 6A jM AT YAS A5 TAT AID TRT A3 YAS Y AJ AS xOut v xOut c xOut 0 00 0 MJ Mj Aeg ABj Moy Aj Aj xOut 1 00 Al yA Y 5y Ayy Ny My ABY Aij xOut_2 00 YAU Vy My ey My AWY Ay AY git 3T4 2 TO dk f f f WV UVU A Le Lu A A A707 0Q xln_v_ xn 0X oy Vy A4 y AG y A8 y A0 AT2 Y A14 Y Ale y AIS Y A20 y A2 y A24 y A26 YX A28 y xn 1 3 9 amp AM AM FL TYA TAS TAT TY AW T RT T A3 M5 X AS xn 3 A 9 6A jM AT YAS A5 TAT A9 TT A3 YAS Y AJ AS xOut v J
65. s Coefficient 0 32 Specifies the width of the coefficient data input Fractional Bit Width into the filter when you select Signed Fractional Binary as your coefficient data type Coefficients Reload Options Coefficients Reload Turn on this option to allow coefficient reloading This option allows you to change coefficient values during run time When this option is turned on additional input ports are added to the filter Base Address Integer Specifies the base address of the memory mapped coefficients Read Write mode Read Write Read Write Specifies the read and write mode that determines the type of address decode to build Flow Control Altera Corporation FIR II IP Core Parameters C Send Feedback UG 01072 2014 12 15 Coefficient Parameters 3 3 Back Pressure Support Turn on this option to enable backpressure support When this option is turned on the sink signals the source to stop the flow of data when its FIFO buffers are full or when there is congestion on its output port Coefficient Parameters Table 3 2 Filter Specification Parameters Coefficient Options L th Band Filter All taps Specifies the appropriate L band Nyquist filters Half band Every Lth coefficient of these filters is zero counting out from the center tap 3rd 5th Coefficient Scaling Auto Specifies the coefficient scaling mode Select Auto to apply a scaling factor in w
66. s connected and parameter assignments lt my_ip gt _generation rpt IP or Qsys generation log file A summary of the messages during IP generation lt my_ip gt debuginfo Contains post generation information Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect lt my_ip gt qip Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software Contains information about the upgrade status of the IP component lt my_ip gt csv lt my_ip gt bsf A Block Symbol File bsf representation of the IP variation for use in Quartus II Block Diagram Files bdf lt my_ip gt spd Required input file for ip make simscript to generate simulation scripts for supported simulators The spd file contains a list of files generated for simulation along with information about memories that you can initialize lt my_ip gt ppf The Pin Planner File ppf stores the port and node assignments for IP components created for use with the Pin Planner lt my_ip gt _bb v You can use the Verilog black box _bb v file as an empty module declaration for use as a black box lt my_ip gt sip Contains information required for NativeLink simulation of IP components You must add the sip file to your Quartus project
67. sel once eei ye er yii Waki bie adim nnana 2 9 FIR DIP Core Parameters 3 1 Filter Specification Parameters aieo yt d dl min Hx o Wel a NAYE Wu yin d derandin 3 1 Coefficient Parameters i4i raserede kn anda n le keki G kel ud at dala dl G kik dn 3 3 Loading Coefficients trom a Fil i lt i 4 lc444q4 1 5y1x5 45 pote bnt Qui op Ubera ed a s wan y Va s wan 3 3 InputiandOutputOptions PR 3 4 Signed Fractional BinATy ui eit RI DOR INR RV RR INE MEUM RE 3 5 MSB and LSB Truncation Saturation and Rounding eerte 3 6 Memory and Multiplier Trade DIEs asset siena qunm pendisse ge tiae AER Hek IR RR 3 6 Using CDelay RAM Block Threshold rrr trente d nik a rhon duis 3 7 Using CDual Mem Dist RAM Threshold ssi eiecit eti cr iren erm dE 3 7 Using M BAM LBresholdou soner 44y 050an eti nb bi an k cha ER ea Kek dede ka EKE derk kK d 6 3 8 Using Hard Multiplier Threshold secerni IEEE n pup qub 3 8 FIR II IP Core Functional Description eee eee eere eene nennen 4 1 FIRI IP Core Interfaces and 5Ipmals asses ut pa aod tige ui UN ekin tt tA UE Aon un Ne 4 1 Ayalon ST Interfaces in DSP IP COresS eee eee e eres QA HE pH Nee vea PANEL HHHH AKAR 4 2 FIR II IP Core Avalon ST IBEerfaCGs uiuis pita mein enr DANSE ORI MEA ada RARE RU aa ake kk 4 2 FIRILIP Gore Signals citis ded Ht Dai i AU qudd MIN IMS 4 8 FIR II IP Core Time Division
68. sources Required for a 49 Tap Single Rate Symmetric FIR II IP core Filter Clock Rate Sample Rate Logic Memory Bits TDM Factor MHz MSPS 72 72 0 1 2230 25 144 72 1701 13 468 2 288 72 1145 7 504 4 72 36 1701 13 468 2 FIR Il When the sample rate equals the clock rate the filter is symmetric and you only need 25 multipliers When you increase the clock rate to twice the sample rate the number of multipliers drops to 13 When the clock rate is set to 4 times the sample rate the number of multipliers drops to 7 If the clock rate stays the same while the new data sample rate is only 36 MSPS million samples per second the resource consumption is the same as twice the sample rate case IP Core Multichannel Operation You can build multichannel systems directly using the required channel count rather than creating a single channel system and scaling it up The IP core uses vectors of wires to scale without having to cut and paste multiple blocks You can vectorize the FIR II IP core If data going into the block is a vector requiring multiple instances of a FIR filter teh IP core creates multiple FIR blocks in parallel behind a single FIR II IP core block Ifa decimating filter requires a smaller vector on the output the data from individual filters is automatically time division multiplexed onto the output vector This feature relieves the necessity of gluing filters together with custom logic Vectorized I
69. t EDA tool setup scripts f HDI files UG 01072 2014 12 15 lt your_ip gt qsys System or IP integration file your ip sopcinfo Software tool chain integration file your ip tb qsys Testbench system file f lt your testbench tb csv your testbench gt tb spd ee Delon my ip qsys The Qsys system or top level IP variation file my ip is the name that you give your IP variation system sopcinfo Describes the connections and IP component parameterizations in your Qsys system You can parse its contents to get requirements when you develop software drivers for IP components Downstream tools such as the Nios II tool chain use this file The sopcinfo file and the system h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave Different masters may have a different address map to access a particular slave component Altera Corporation FIR II IP Core Getting Started J send Feedback UG 01072 2014 12 15 Files Generated for Altera IP Cores 2 7 PE nadi RT SE FEE lt my_ip gt cmp The VHDL Component Declaration cmp file is a text file that contains local generic and port definitions that you can use in VHDL design files lt my_ip gt html A report that contains connection information a memory map showing the address of each slave with respect to each master to which it i
70. to provide spectral shaping or to perform signal detection or analysis FIR filters and infinite impulse response IIR filters provide these functions Typical filter applications include signal preconditioning band selection and low pass filtering Figure 1 1 Basic FIR Filter with Weighted Tapped Delay Line xin gt Tapped Delay Line uu Coefficient Multipliers Adder Tree To design a filter identify coefficients that match the frequency response you specify for the system These coefficients determine the response of the filter You can change which signal frequencies pass through the filter by changing the coefficient values in the parameter editor Altera DSP IP Core Features 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibilit
71. y or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ANU amp RYA 101 Innovation Drive San Jose CA 95134 UG 01072 1 2 FIR II IP Core Features 2014 12 15 Avalon Streaming Avalon ST interfaces DSP Builder ready Testbenches to verify the IP core IP functional simulation models for use in Altera supported VHDL and Verilog HDL simulators FIR II IP Core Features Exploiting maximal designs efficiency through hardware optimizations such as e Interpolation e Decimation e Symmetry e Decimation half band e Time sharing Easy system integration using Avalon Streaming Avalon ST interfaces Memory and multiplier trade offs to balance the implementation between logic elements LEs and memory blocks M512 M4K M9K M10K M20K or M144K Support for run time coefficient reloading capability and multiple coefficient banks User selectable output precision via truncation saturation and rounding DSP IP Core Device Family Support Altera offers the following device support levels for Altera IP cores Table 1 1 Preliminary support Altera verifies the IP core with preliminary timing models for this device family The IP core

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