Altera Cyclone II FPGA board User Manual - FPGA-DEV
Contents
1. EMT MEE EE sl Vec 3 3V S oeeob olelelelo ofolololo ooo e Voc 3 3V i TY 1 8 deg 344 498903989 da TT RT z SATS 4 3 E N a dass 3 il l 299 Ae aa Q 9 S 2 S lt z al NE ENEEE adaddadag all 7 3 dd dde dd Fo i 4 4 B 8 E gliaol o cole o jo Ene RRR RER Fees ce sazz RR gl aaa ER LRR SSBS Biles olololole elelelela ooo Soo e 9oololeejljsjejololojololeleleleotoo Vec 3 3V A BL a E ES ERAS Feleseg ellela olealelsisls sco 8 esse el ssp eBags s 83 F scs sljejs a Slejalss 88egeelelesS saesSsBsssesseesspe ol lololslslelo See e slos a Sej SSe col oo o SesgleeBseses oojejoo alslala2 EE ECE EEC CEE Ade atados dede pippe e EEEE rE Eeee CEEE Eeee dun ei sell as ui d Dl um CONS MM Si Wi HM TH d wn 70680134 post acs 7 i29GL12 H Z amp ezaztzozuzzonzoezouzezaozozr zuzezozozezoOgnzozozozauzozaos oes9ZOLZ zez z uzz ozozozozazozozezozaozezozozgonzezouzozuzu zez Q DQ21 EADRI 8 16 SDA amp 1 A2 Bn 3 Dis SD BA 110 a DOGS DO96 EST Asados OS RS BSRSSSoctOU2. concer 6 hiscere 6 Expansion COMO ii 6 A A P 7 Physical dimensions and expansion header positions essere 7 SEEMS Uf WP seent 8 FPGA d sign SoftWare iii ss 8 USB drivers installati sida 8 FPGA pin allocation file ai 8 FPGA configuration ia 8 FPGA configuration via USB interface i 8 FPGA configuration from the flash memory ooooocccocccoconononconncoonnconnnono nono nonnocnnnnnnncconccnnos 9 FPGA configuration via JTAG li 9 TEAG CHUN a 10 Fl sh m mory progran A A 10 NIOS M ex mple SOPLO Sy Stemi soni 11 e OE O A 11 CISTI GCSE O A o E IE E 11 USB Tesi 11 A 11 Document revisions and Changes a ERN D RD e cupa e Sr N o EUR e DRE BYE 12 CTA ccr M 12 Schematics and component diagrams sudden 13 www fpga dev de fpga dev web de Introduction Thank you for your interest in Cyclone II based FPGA board This development board for an experienced user combines many powerful features at very fair price The possible application range covers stand alone experiments on the one side and operation as a part of a commercial product on the other side Features make this FPGA board unique among other development boards are e Small size of the FPGA board only 96x68 mm makes it possible to use it in the end application as a daughter board e 172 Cyclone II I O pins are exclusively available at the e
3. Each memory segment is large enough for storage exactly one FPGA configuration Unused segments can be used for any other purposes Note Configure the FPGA from the flash memory only when a flash segment with a valid configuration data is selected FPGA configuration via JTAG The pin configuration of JTAG connector complies with the Altera specifications You can use both the original Altera USB Blaster and the compatible one from terasIC www terasic com tw Note The usage of a JTAG adapter is the only way to e In circuit debugging of a NIOS II system e Using the Signal Tap II logic analyzer e Programming flash memory www fpga dev de fpga dev web de JTAG chain The JTAG chain carried out at JTAG connector consist of Xilinx configuration CPLD and Altera Cyclone II FPGA The configuration CPLD is already programmed there is no need for any modifications of its function If you use a JTAG adapter in conjunction with Altera Software please note The Altera Software reports the configuration CPLD as an unknown device It s not a malfunction or a bug it does not impact usage of Altera Software Flash memory programming The programming of flash memory requires a JTAG adapter a working NIOS II design contained in fpga nios2_ sys test and installed NIOS II IDE Software Following steps have to be done to program the flash memory with a configuration file at address 0x0 1 Start Quartus II Programmer ap
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5. Ir EP2C35F672C8N K CAB9TO601A KOREA flash memory Cyclone II FPGA FPGA board components bottom side 2x precision connectors with 2 54mm pitch SDRAM socket USB controller 25MHz oscillator Ethernet controller S 900000 5000000 PI m jJ Oly m ZI Sl m oF 715 E 00000000000000000000000000000 0 0 0 fpga dev web de 3x user LEDs USB connector miniSD Card socket LAN connector 1 2V switch regulator configuration CPLD DIP switches 00000000000000000000000000000000 www fpga dev de fpga dev web de Altera Cyclone Il FPGA The used Altera Cyclone II FPGA EP2C35F672C8N contains in total 33 216 LE LE LUT DFF 483 kbit memory 35 embedded multipliers and 4 PLLs Configuration CPLD The CPLD can configure FPGA with one of 8 selectable configuration files which can be programmed into flash memory Flash memory The 16 MByte large flash memory device can hold up to 8 FPGA configuration files and application specific data The flash device is connected through 16 bit wide data bus to FPGA miniSD Card socket Flash cards for the miniSD Card Socket are available today with capacities up to 4 GByte SDRAM memory socket SODIMM socket accepts laptop SDRAM memory modules with capacity up to 256 MByte The data bus to the FPGA is 64 bit wide which results in 1 GByte sec maximum total data rate USB controller The integrated high speed USB controller CY7C68013 communic
6. C1 C10 Q 68uF 6 3V D2 30BQ015 100uF eV 220uF 10V VCC PLL1 Vcc 3 3V GND PLL1 GND PLL1VCCD PLL1 zu sel a lt o o 1 l a a Z o EP2C35F672 N R o ra Fe YO 88 Si Vcc 1 2V O ra x1 xxx x 2 2 2 2 zZ zZ a a a tj lt a aj gt z tj Y O tj Y a al EEEERESEEESEEEEEEESESESEEEES aaa AANA aa Fe P BBBBOBODODODODODODODODODODODO Begegs Buses ssesess sees C43 044 045 046 047 048 049 050 051 052 053 054 055 096097 APS APC SSS SS O SS SSS SSS gt EN SS RSS SS SS SS Sees 1nF 1nF 1nF 1nF 10nF 10nF 10nF 10nF 100nF 100nF 100nF 100nF 1uF 1uF 1uF QU MOUFR ces ssepe TES CENTS canoa nda ani n ECT EY EUER da ELE LEV ELE LETT ELE ETLEY EE E ELE E E ul c2z2zceceeceececececccccccececececccc PA A AA n A e ir LA a A A AS A ARA 5oo0000000000000000000000000000000000000000000000000000 S eo 8 NZ Vcc 3 3V Vcc 3 3V O O M uw 000000000000000 oo a OO0O0O0O0O0O0O0000020 lt OO tE P freee e ae 9 2 C60 C61 C62 c63 ce4 ces5 ces C67 ces C69 C70 071 C72 073 074 5075 g C79 ES 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 10uF 10uF 10uF qo 25 100nF a OG 5 20 lt lt EERS VA Vcc 3 3V Vcc 2 5V Voc 3 3V Voc 3 3V Voc 3 3V Q Q Vcc 3 3V Voc 3 3V O O O O O wow DO Ss O Sg xx S N Fo 30 3 E 8 Os Vo zz qo os on 00 ed 20 ER 9a V VCC PLL2
7. 5 PKTEND SD4 a Rs Rte R177 Ate Aro E pin IONREFBINO IO LVDS131P SD4 sp 48 EL Sie veni IO LVDS19P IO LVDS131N PATI 503 14 gps Skel soni GOR BOR BOR ooaoao9990o0oo0 IO LVDS19N IO LVDS132P pue Spr H SD2 EEDIO H3 ae a H orvos1sP IO LVDS132N 800 g 01 EEck 20 Vv 4 kl o wg HH oLvosten IONREFBGNO EE 8 spo EECS EL 2 A20 4 O LVDS17P o IO 164 CMD C101 C102 BLOCK 2 AT IOLVDST7N lot vpsissP H28 ag INT CMD 3x TOO pros 5 eeose p i rc m S 17 4 FADRO TOW 38 OR sn o al A Hi Be 5 10174 pa M 4 IOLVDS14P IO LVDS135N mU andere net E f 10154 5 2 AE IO LVDS14N IO LVDS136P na 40 PW_RST LED2 3B iM I0 124 RESET HE lot vbstaP 10 LVDS136N HE TEST LED 2 51 T 26 O 163 10104 Ado IOLVDS13N IOLVDS137P EDS UGIK a oa oe UB iot vpsi2P IOLVDS137N FLAGO 1064 UZ iot vpSt2N IO LVDS138P V24 paran x mo oTa pa A E U5 iopasL4 iot vbsiaeN V23 EDS EYSCHR 7 1011 18ck2 O o 1044 2 ae IO LVDS11P CDPCLK1 IOILVDS139P CDPCLK4 We Vec 3 3V Do I0 14 1 GCK3 i e 10 3 4 gate AB y1 QLVDSTIN IO LVDS139N y 53 SD DET o DE 8710101 10 84 5 m 10 101 VDS140P N23 E CE 90151 m m 10 5 4 Hia As Di IO LVDS10P IO LVDS140N 555 FD5 20 10171 1024 6 I LVDS10N 10 pas s 0121 IOLVDS9P IOLVDS141P 10k IOLLVDSSN IO LVDS141N R23 IOLVDS amp P IOLLVDS142P r3 IOLLVDSBN IO LVDS142N IOLVDS7P IOLLVDS143P BLOCK 3 Tc IO IOLVDS7N IO LVDS143N 1008 A PT 10 IOLVDS144P TDO 82 5 OVREFB1N1 IO LVDS144N
8. EP4 and EP8 Content of packets received through EP2 endpoint is read via FIFO interface and stored in assigned FIFO After that the data is send back through EP6 endpoint The same procedure is applied to endpoints EP4 and EP8 Note You can test the quality of the USB connection with Cypress tool CyBulk CD content cpld configuration CPLD programming file data_sheets data sheets of used components docs this file fpga IP component for connection of Ethernet controller to NIOS II FPGA pin allocation file fpga nios2_sys_ test NIOS II example system usb USB drivers and documentations of Cypress USB controller usb firmware firmware sources of USB controller usb programmer source codes of Windows FPGA programming tool usb programmer Release Windows FPGA programming tool 11 www fpga dev de fpga dev web de Document revisions and changes revision date Changes 1 00 10 11 2007 initial version Trademarks Cyclone II NIOS II Signal Tap II and Quartus II are trademarks of Altera Corporation CyBulk is a trademark of Cypress ComView is a trademark of TamoSoft 12 www fpga dev de fpga dev web de Schematics and component diagrams IC1 CON1 Voc 5V LM2596S ADJ L1 Voc 1 2V Vcc 5V IC2 Voc 3 3V Vcc 1 2V Vcc 1 2V POWER 5V LD1085D2T Q Q een PEE 4 L2 L3 Feedback ferrite bead ferrite bead Vcc 1 2V
9. GND PLL2 VCCA PLL2 GND PLL2 4 4 4 4 4 4 4 GND VCCO GND VCCO GND VCCO GND VCCO GND Vec 1 2V Vcc 1 2V O O L4 ferrite bead L5 ferrite bead cc 1 2V Vcc 1 2V Vcc 1 2V O O O VCC_PLL3 VCC_PLL4 GND_PLL2 VCCD_PLL2 GND_PLL3 VCCA_PLL3 GND PLL3 VCCD PLL3 GND PLL4 GND PLL4 VCCD PLL4 l a lt o o gt l a a z o N R oO ra e a 9 N A Lu 1C3 6 EP2C35F672 GND PLL3 N e 9 5 5 5 5 5 5 E l I GND VCCO GND VCCO GND VCCO GND VCCO GND VCCO Vcc 3 3V O XC9572XL VQ64 1C5 2 M1 MOUNT HOLE M2 MOUNT HOLE M3 MOUNT HOLE M4 MOUNT HOLE itle Altera Cyclone II Board Size Document Number A3 2 2 Date Wednesday April 18 2007 Rev Sheet 1 of 1
10. communicate with FPGA absolutely synchronous in one single clock domain User I O A debounced push button can be used for direct user input detection The released user button is identified by logic low 0 volt and pressed one by logic high 3 3 volt For simple outputs three user LEDs are provided on the FPGA board Each LED is driven directly by a pin of the FPGA Driving related pin to a logic low 0 volt turns the LED on Reload button Pushing the reload button SW1 clears the configuration data inside FPGA Immediately after releasing the reload button the FPGA is reconfigured by CPLD with a configuration contained in flash if the DIP switch 4 in the ON position Expansion connectors User circuits can be connected to FPGA through two expansion connectors on the bottom of the board J6 and J7 with 2 54 mm pitch and through four surface mounted connectors on the top of the board J2 J7 Four different signal types are available at expansion connectors 1 FPGA I Os FPGA in and outputs the signal direction is application specific and defined by the user 2 FPGA I Os or PLL output same as type one additionally these pins can be used as PLL clock output 3 FPGA or PLL clock inputs input only FPGA pins allow direct clock sourcing to PLL circuits 4 Power supply connectors 5V 3 3V and power ground The following table lists the availability and count of the first three pin types at different expansion connect
11. test This example system was developed to check the function of all components contained at the FPGA board The results of the check subroutines are indicated via the user LEDs The top level entity file of the example NIOS Il system is CMpgaWios2 sys testXtop level vhd Memory test Memory test tests the connection and integrity of flash and SDRAM memories For a successful SDRAM test insert a 256 MByte memory module into SDRAM socket The user LED 1 D4 turns on if SDRAM test succeeds The user LED 2 D5 indicates a succeeded flash memory test Note Memory test erases all contents in flash and SDRAM memory Ethernet test After Ethernet controller initialisation every received data package generates a processor interrupt The interrupt service routine reads the Ethernet packet data from DM9000A and sends its content immediately back to sender Every call of interrupt service routine changes the state of the user LED 3 The target IP address of the Ethernet controller is set by initialisation routine to 01 60 6E 11 02 0F Note You can use Ethernet packet sniffer and generator like CommView from TamoSoft to generate and receive Ethernet packets USB test A VHDL component is instantiated in NIOS II example system for USB controller test This component is not connected to NIOS II example system It consist of two 512 Byte large FIFOs and realises a simple echo application One FIFO serves endpoints EP2 and EP6 the other
12. 0600000000000000000000090 III 14 00 puce rg JTAG 47 00 4x 03 00 68 00 64 50 63 00 54 50 9 00 All dimensions are in millimetres www fpga dev de fpga dev web de Setting up operations FPGA design software Altera Cyclone II EP2C35 FPGA is supported by the free Altera Quartus II Web Edition design software Please visit www altera com for further information and download USB drivers installation Install Cypress USB drivers before using the FPGA board USB interface Execute the usb SETUP_FX2LP_DVK_1004 exe for installation Many tools firmware examples and documents needed for successful and fast development of own CY7C68013 firmware and PC applications are installed too FPGA pin allocation file All pin allocations of the FPGA are contained in Mpga pin assignments qsf FPGA configuration You can configure the Cyclone II FPGA in three different ways e Via USB interface e With content from the flash memory e Via JTAG interface Let s have a look on every of these possibilities FPGA configuration via USB interface As earlier mentioned the E7PROM is preprogrammed with a small firmware for the 8051 MCU of the USB controller This firmware uses internal endpoint 1 for FPGA configuration data reception After reception the configuration data is shifted by 8051 MCU in serial manner PS mode into FPGA Please follow the
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15. OBSOOUS0GG ARO N A CER ERE RRE aaa saga nos 2533282855 SESS OUS QUIS CERT QUE FADRO Ei a Ser ssc A AD Ep ru A22 DQ15 A 1 ix SD BAD BAT DQe3 DOZ DOSE IO ASDO GBESBROBBBSSR BH BB PAIN AAA PANAS 55DA unn III OODOOOODOOOOOOD IOPLL2 OUTP SD BAD FIFOADRO SCL SCL At A21 para LE 254 Bao Dase H36 D3 1 ioNCSO eee ee eee ee GA BA BBO eee ee ee eB eee casa PB Bee BBB kako kas Peek QQnddnadOobdOnnOnnOOnrOROdOnddnadOnAROE Beca cera cae oda IO LVDS100P we a 34 A20 D4 6 D13 SD A12 0 4 DOST lO 18 B 23333360333334 SS 33 3333333333333333 333 Y gt 333332333338322 2203 3333333333 33333333339333333333333333 Y 33333303333333 D23 DOMB7 FD15 A ps A20 DOIS Fs D12 SDA 112 412 bas D0 10 19 pa OL VDS49PICRC ERROR 124 1 OI SE i i J9 LA A O pollice Se a E a Sass O SS IO LVDS100N Daz FDi4 FDIS AE A19 Dai Lom SD ATO A11 paso 122 5 659 DG37 ES IO LVDS49N CLKUSR 09900901090005 900 GH 809009009050909900009080 2909090005905088 250 9090000900002000090906005090000905900909009802 9909090420900909090 IO LVDS101P Dass FDIS FD14 DIP3 A18 pati Pete SD AS 7 A10 Dass 128 DASS DOMET IO PLL3 OUTP Ej 8 2 2 2 5 xxo E E Care ge ee IOMLVDS101N Dae ED 0 rp13 PAO INTO 39 A17 Dato Da SDAS A9 pase 26 Seer 10 17 IO PLL3 OUTN 8 2 a amp 39 559 8 2 to A 7 FD 22 FD12 PATINTI 34 psa o 4 8 S 98 3385 3 48 36 A5 pz 418 Das D8 SD A7 104 48 DQ57 DO56 DOMBA Io DS 2 z E 3 G DoS E 10 VDS102P FE DOS FOTO eran cen PRAVIS DONE aia A15 pas d aas E AT Dass D
16. OES DOE 1O LVDS48N 3 5 5 3 55 559 9 8 IO LVDS102N S M us FD10 PA7 FLAGD SLCS 2 PONS ATS A14 BG His SD AS 03 Ag Doss 100 recs DOF G5 ion vosa7P g x 8 s882 2 101 VDs103P B2 5 A Ae 46 rpg AT A13 DO6 ES D5 SD A4 39 AS DQ54 Fog poss Dass 3 O LVDS47N lt 3 IO LVDS103N ese SD AS ED FDB AN A12 Das Da EEE A4 Das3 Hai pas DOS IO LVDS46P d o9 IOLLVDS104P DONES FDS FD7 Das Hi 0 A3 Dase 94 F4 ILL VDS46N IO LVDS104N 4 FD6 ATO H4 D3 SD A2 DOST O p D26 0056 FDS P pas H4 pz SAT a a2 DO51 DOD 16 16 2H lot vbsasP IOLVDS105P D28 coo Ye FDS paz Al DQso IO LVDS45N IO LVDS105N FD4 AB H3 Di SD AO 9 DO49 DOMBI F7 Daze FDS MINLUSB_CON2 pat AD Daas 10 IONREFBSNO FD3 Dao paag A Boss IOIVREFB2NO IO LVDS106P B 0 FD 3 ES Doa 4 Boaz 8 iot vbsaaP IOrLvbstosn Ez DQMB2 n 19 Fpi D Hi 3 p A5 DQMB7 8 DO46 IO 54 4 DQ60 FDO 8 i NAE M DOMES DOMB7 Daas DAS bre 1O LVDS44N IOLVDSTO7P 8 FDO A3 Voc 3 3V DOMBS g DQMB6 DO45 Daa 10 14 HE to IO LVDS107N os SLRD AD o D MBA 4 DOMBS DQ44 34 D43 1033 EL O LVDS43P 1O LVDS108P SIWA SLRD pH baa 1868 AT DOMES DOMB4 DQ43 dG 1O LVDS43N IO LVDS108N HIEO ro SLWR 65556 AD DOMB DOMB3 DQ42 DOT pos S7 ionvos42P IO LVDS109P E Re DOMBT DaMB2 DQ41 DO40 Dass 57 IOLVDS42N iot vbsiooN E28 O2 SYSCHR 13 gt IFOLK nd 10k DOMED DOMBI paso DO Dae IO LVDS41P IO LVDS110P NIB mE DQMBO DQss 22 IOLVDSAIN IO LVDS110N SLOE Ret 8 4 ICE B D038 DQO 6 DOST PKTEN
17. T 10k Dats 9 Meson ia DATI 8 ET SW DIP 4 Aa para Pal ae o2 10 10 past DA DAT icso bars aie Oa IO LVDS29P lonvpsi2ip 25 DATO 8 pare HA 13 IO LVDS29N IO LVDSi21N H2S Dort 42 Bart 1107 fo iot vpsizap M22 10 82 ES Veiis paro 11 Bato 19 21 MA lon vbsesP O vostzan Mea FDE on oc 43 3 g DOS 51 M M19 25MHz 1 Dos E 9 22 a iot vpseeiopoto Oh vostzsn 20 10 79 E paz 12507 M2 IO LVDS27N lonvpsizap N20 0 78 SYSELK nn t Ak Das DoE cua 1 N2 PCLKO LVDSCLKOP INPUT 3 IO LVDSi24N M21 57 2 iiD Dos 1550 Ni CLK1 LVDSCLKON INPUT 3 lotvpsizsp MAS croce R14 47R Das HE IO LVDS125N FY SuD LeD 330R DQ3 CLK2ILVDSCLK1P INPUT 3 ks IOLVDSi26P DPCLK7 N23 00 Dae pa DE EL CLASLVDSCLKINIINPUT poem 1O LVDS126N NE4 nay Ign Dai 509 ES OL VDS26P DPCLK1 CLK4 LVDSCLK2P INPUT 3 N25 Sane jee TUR Dao p2 OMWDS2EN CLKS LVDSCLK2N INPUT 3 N26 EE LEC sore BS O LVDS25N CLK6 LVDSCLK3P INPUT 3 4 528 SYSCLK S015 22T spis TX a DE Bs OLVDS24P CLK7 LVDSCLK3N INPUT 3 4 528 p3 EH SD14 H F d Fe 10 iot vpszsP Ovos LVOSZ N P24 sbi 28 Sp12 il We P 13 io vpseN Io vostzap B28 DATE ANO sp1 sores H 10 BL ion vDseaP IO LVDSi28N B24 27 spio 2 u eo P8 IO LVDS22N Cee 0828 epo AX HE E IOLVDS21P IO LVDS129P His ESI SD8 a Wi IOLVDS21N IO LVDS129N 72 spg 807 Ax pl t 2 Y XC9572XL Voe4 BH lonvoszor 1O LVDS130P ELY ET SD6 a ON ONT AY CY O ou OCU E O A6 47 O LVDS2ON IO LVDS130N
18. ates with 480Mbits sec with a PC or another proper USB host Preprogrammed E PROM already contains firmware for 8051 based microcontroller of the CY7C67013 The firmware configures the endpoints as follows endpoint direction FIFO count x block size EP2 out 2 x 512 Byte EP4 out 2 x 512 Byte EP6 in 2 x 512 Byte EP8 in 2 x 512 Byte The general programmable interface of USB controller FPGA USB is configured as 16 bit wide slave FIFO interface The FIFO interface is clocked with 25 MHz which allows net transfer of 50 Mbyte sec between FPGA and USB controller The firmware programmed vendor and product IDs are reserved for development intentions only idVendor 0x04B4 idProduct 0x1004 You must change these IDs if you use the FPGA board as a part of a commercial product You can use delivered FPGA configuration tool for FPGA configuration over USB interface without any JT AG adapter www fpga dev de fpga dev web de Ethernet controller The FPGA board provides 100 10MBit Ethernet support via Davicom DM9000A Ethernet controller chip This makes in fact a very simple and FPGA logic resources saving connection to Ethernet networks possible Crystal oscillator The 25 MHz reference clock is generated by crystal oscillator Q1 This clock signal is provided to FPGA FIFO interface of USB controller and Ethernet controller The usage of a reference clock makes sure that all components can
19. lower instructions for the FPGA configuration via USB 1 Shove DIP switch 4 in OFF position Clear current configuration by pressing reload button Connect PC and FPGA board through USB cable Start FPGA configuration tool Choose the raw bit configuration file rbf Pho paupe The configuration procedure starts immediately after file selection dialog is closed and lasts about 5 seconds A success message confirms finished FPGA configuration At the same time the yellow LED turns on Note Once FPGA configuration procedure starts await a success or failure message before next attempt www fpga dev de fpga dev web de FPGA configuration from the flash memory The flash memory can contain up to 8 selectable configuration files for standalone FPGA configuration The configuration starts after the power supply is applied to the FPGA board and the highest DIP switch 4 is in ON position The lower DIP switches 1 3 determine address range in the flash memory which is used for loading configuration data The loaded configuration data is shifted in serial manner into FPGA PS mode The lower 8 MByte of flash memory are segmented in address ranges as follows configuration address range switch position 0 0x00 0000 0x0f ffff 1 0x10 0000 0x1 f ffff 2 0x20 0000 0x2f ffff 3 0x30 0000 0x3f ffff 4 0x40 0000 0x4f ffff 5 0x50 0000 0x5 f ffff 6 0x60 0000 0x6f ffff 7 0x70 0000 0x 7f ffff
20. ors conn signal type 1 2 3 J2 20 0 1 J3 20 0 1 J4 19 1 1 J5 21 0 0 J6 43 0 1 J7 42 1 1 2 165 2 5 Note All these 172 FPGA I Os are exclusively available at expansion connectors they are not shared with any other FPGA board device or circuit www fpga dev de fpga dev web de Power supply The FPGA board is power supplied through the CONI connector The centre of the power supply plug must be positive 5 volt and the barrel must be negative ground As an alternative you can use power pins 2 4 both positive and ground pins of expansion connector J6 to supply power to the FPGA board The power supply must provide a regulated voltage of 5 volt 410 min 1 ampere The FPGA Board components require either 1 2 volt supply FPGA core or 3 3 volt supply FPGA I Os SDRAM USB Ethernet flash etc These voltages are provided by a high efficient switch regulator 1 2 volt and linear regulator 3 3 volt Both regulators deliver currents up to 3 ampere The real current requirement depends on the following factors e Configuration loaded into FPGA e SDRAM memory usage e Current drawn by user expansion circuits supplied through FPGA board Important There is no power supply reverse polarity protection circuit on FPGA board Wrong power supply polarity will damage FPGA board components Physical dimensions and expansion header positions 96 00 92 50 74 00 06
21. plication from NIOS II IDE Tools Quartus II Programmer 2 Configure FPGA with fpga nios2_sys_test nios2_sys_test sof file Auto Detect double click at file field of EP2C35 Select file Start lt gt Quartus II Programmer Chain1 cdf File Edit Options Processing Help E Hardware Setup USB Blaster USB 0 Made TAG Enable real time ISP to allow background programming for MAX II devices Pest E none UNKNOWN_ 496040 00000000 dy Auto Detect 3 Start Flash Programmer application from NIOS II IDE Tools Flash Programmer and select the desired FPGA configuration file and destination address range offset IV Program FPGA configuration data into hardware image region of Flash memory FPGA Configuration SOF c Yfpgalnios2_sys_testinios2_sys_test sof Browse Hardware Image Custom y Memory flash y Offset oxo Program a file into Flash memory File CAProjektelCyclone 2 BoardYfpgalnios2 sys testinios2 sys test rbf Memory Flash z Offset oxo IV validate Nios II system ID before software download Apply Revert 4 Push Program Flash The Flash Programmer window will automatically close All output messages will appear at console window of NIOS II IDE 10 www fpga dev de fpga dev web de NIOS I example SOPC system The enclosed CD contains an example NIOS II system for Quartus II v7 2 CDROM path CMpgaWios2 sys
22. s eel S agel es Ls sllelss 2 Elsa e Sis leo N 1 A SEE Sree resco Ses E EE SS AS mee B _ 2 olajoleje R7 3 R74 roan TDO Ma FPGA TDI T TMS 5 6 ojolelololelele ol ofelejelole efe efelele elelclololelololelelele ope a opel e elll ololaizo ofle o Bleje o ooo R26 1 330R D4 SMDLED tox 10k La TMS 8 MELI TMS me TCK TDI E 10 mg Se esse sb sess seb ee L E abad Alen o assess ias Besse deeoee soces esee ce oe ss slalsplslels ls 5 s siens E olololololelolelalalola ofolololo olelalolelo oll ls oleo 7 c 5 R26 3 330R D6 SMDLED V Y E d RE il 3 5 SE ERE ELE z 4499339995 an 8 E 8 53994999 sind Suda 3 8 2 x 8 E z Fi 32 34 dediddddad dad ido dolo 5e L H H gt 3 4 4 a D tot 4 i i a 8 l5 o Vec 3 3V gt Voc 3 3V asse ssess sisse selee 2 olll ololelolo ololelelo olblolelo o itle Altera Cyclone II Board ize Document Number 1 2 lustom Date Monday April 23 2007 Bheet 1 of 1 Ll Sd IL 899 499 999 G91 SY 4193 99 292 192 093 LI DENN BE een eee s ea e Tha C3 L HS 14 lt 949 gt asn ER NEST z 71 Os s OH G x dl us 9424 Jrora ds LI E Jzota in gru MS g3 le E N TE i paj DB n Z19 a i a ey m A a n 1 n ma Bog E LS zel Ly o y M al 9 88 a Oo NL rn gt sup Gp de 5 to co LL LLIE 1L T IIL IL 1L 7 ser3s 0013
23. www fpga dev de fpga dev web de Altera Cyclone Il FPGA board User Manual Disclaimer This product and its documentation are supplied on an as is basis and no warranty as to their suitability for any particular purpose is either made or implied No claims will be accepted for damages howsoever arising as a result of use or failure of this product Your statutory rights are not affected This product or any variant of it is not intended for use in any medical appliance device or system in which the failure of the product might reasonably be expected to result in personal injury This document provides preliminary information that may be subject to change without notice Copyright 2007 Valerij Matrose All rights reserved www fpga dev de fpga dev web de Content EO OEE a e m 2 o a EA O O E 3 Description of the FPGA Board oa 3 A Mf ectetuer rescued A Ee rod copine err cmt odi et neis 3 FPGA board components top ld 4 FPGA board components bottom side sse eene 4 Altera Cyclone M BPO osa eR MEIN brs SERERE UN UR ORR QU REIR QU RR ERN UNE UIS T tM MER QN RUD GUE 5 Configuration CPED Pec 5 Flash MEMO a i n 5 m S IAL SOC c E N ENESES 5 SDRAM memory socket odo 5 Ma A mom EN DRM MOINDRE M E 5 EAST SOOM MSE e sogna psa nor tul Ee adu MISI ER eas iaeaea EaR 6 Crystal oscillator dT 6 IN ro T
24. xpansion connectors e More than a half of these I Os are connected to common connectors with 2 54 pitch and high duty gold plated precision contacts e Two controllers for the world most used data buses Ethernet and USB already soldered on FPGA board e One SODIMM SDRAM memory socket for up to 256 Mbytes SDRAM module e l6Mbytes flash memory e Integrated power conditioning Description of the FPGA board Block diagram 2x RM2 54 conns 10 100 Mbit miniSD Card Fast Ethernet Socket Controller PHY lo 4x SMD conns cm DM9000A i 84 I Os Y gt 25 MHz OSC SDRAM SODIMM adar Altera Cyclone Il leck Socket 4 d0 d63 FPGA ctrl ctr 128 or 256 MByte EP2C35F672C8 rea High Speed USB 2 0 Interface d0 d15 1 f Controller Ex dcr T CY7C68013 Flash Memory 16 MByte Configuration L 4 3x User LED S29GL128 CPLD lt fg XC9572XL User Button 4 A Power Supply t iion 3 3V 3A Reload Button _ DIP Switches JTAG 1 2V 3A www fpga dev de FPGA board components top side power LED power supply connector JTAG connector 3 3V regulator reload button user button conf state LED 4x SMD connector sameaa am ETE EE AL d campa emmo amne lne Moo Cyclone
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