Home

Sbc6713e User's Manual

1. d Q ZlL 0 1 9 0 S2v 0 0020 0210 0000 N o o 4 262 ME Sbc6713e User s Manual e MINOS NO 10 c5 DO foie C e ROO OO gt c NN O DANDO Com iA an 28 06 oO o Saad ESOP so y NA A OO o oD NA CER c 00 jo OOC 2000505 MOM e Na aN o oo Oooo 0 125 D ES 82 0 LEG No o DNI o ggz 006 009 ost DO c 0 Q 205
2. A 28 Sounds Group ot en EEG EE ERNST aan ada 29 Gott Load GOUD rerin EP 29 Ibm O 29 Terminal Emulator Command Line Switches ccccccccccesscsssesseesesseeesecseceseeseeeseceeeesecaeeesecseeeseceeeeseceeesaeeneesseeeesaees 29 Applets for SBC6713e Basebo rd ee eaa o GERENS EET te GER T eee di ee Eres 30 Board Finder Utility Sbc6713eFinder exe essen enne neret enne 30 Target Project Copy Utility CopyCocsProject exe esses nennen nnne nne tenente nnne 31 Flash Conversion Utility PromImage exe sees ener nennen ne nnne enne nennen nnne 32 Flasi Burn arose nee heme S te dee EN Dd HERR en aaa 32 Usage cona a PROPER GERIT ER ERN EIE A NOR gaa RUPEE CREAN AREE EN EU FEET RI CARE DERNIERE 33 Custom Logic Developmelit eee pie deni NIRE TIN TE PEISI RREE AER SEINEN E I SUP IEEE S eoo T Meo pots eMe doch OV ELVIS Wares tont titers a td dle eco 37 Target Devices coser TR RENS P I ERR AU RR rrr bees 37 Code Development Tools 512 Rr ette etie tee tete ate vetus eee eee rig 38 Steps to Successful Us et tn ERU ENSE e Og RN tu er e RE HE e NOSE ce 38 Using FPGA Framewotk eet ERRORES EEG TEES ER nt RET eu RE uis tere ee ERR het 38 UART Overview RS232 Asynchronous Serial Port essere 40 Developing FPGA Firmware a eee IEEE EUR D IR ER D SNNT ceeds E DE
3. M d Single Board Computer Hardware Features sese nennen nennen nn ron nn neret rennen innen inneren 41 Digital Signal PtoCessot 4 2 cie ree reote P qe qe eet idee ee dina 41 DSP Extetnal Memory eene et dee teet en oU 41 DSPM ea a ER ERROR 42 DSP3JTAG Debugger Support uode ee e operit aed ap e E D EIS 42 The Pismo ClassLabr ty 4 deerat tenet de dete uA RA ee een 42 SIUE 43 NotJustdor C EXperts sn Albal ci 44 Analog l O Streams d e hee SR n aie e t atu e e brides 44 Stream Objects and Device Drivers ere leads 45 Hardware Isolation and Independence tto ER UR GS P ERE e Greer dion 45 Stream VO Types ett ene PEE A E UNT Ree teta et e e NES reti 45 Stream Butter Model cotra tuni dtt rnt EE eve ei de E aur ud iyi nbe qoe dde cus 46 Stream Iternalsz onte teer p Pte RE re ret eH e qe her tee erre dern 47 Multitasking Friendly as 47 Using Analog Streams in an Application sess ener eren enn nennen tenerent nen 47 Selecting the Stream Object g ee e CURES RO SU WEE Ut ust Ree e re e oed 48 Selecting and Configuring Hardware i nest e e Re e e YR E e i eme eed 49 Selecting and Configuring Clocks uen eset E IU URSI EE a eed 49 Selecting and Configuring THggers see tee ia 50 Selecting Pretriggering Ms e er RENI E SEU ERU ENIRO D aaa 50 Interr pt Handling e p RUNE RU UE RUNE Re Nee
4. O ps to 9469500 ps wave default ajaja sbe6713_top_tb uul ce2_n 1 TIERS D FFFFF 0 FFFFF 0 o noo 0 RE crore oa dd 0 T o d o od o T LZ FESTUS Cursor 1 1941663 ps ak RL Figure 31 Omnibus Writes And Reads Sbc6713e User s Manual 164 Burst Reads And Writes There are also Testbench Procedures for Burst Accesses Bellow is the example code for Burst Reads This sample code gives you an access to program different burst counts 32 bit data words procedure burst_read constant ce_space integer constant burst count integer constant address bit vector 23 downto 0 is variable i integer variable acnt std logic vector 1 downto 0 begin wait until eclk in event and eclk in 1 case ce space is when 0 gt ceO0 n lt 0 after 2 ns cel m lt 1 ce2 n 1 ce3 n lt 1 when 1 gt ce0 n lt 1 cel n lt 0 after 2 ns ce2 n e Lt ce3 n lt 1 when 2 gt ce0 n lt 1 cel n lt TLE ce2 n lt 0 after 2 ns ce3 n lt 1 when 3 gt ce0 n lt 1 cel n lt 1 ce2 n 1 ce3 n lt 0 after 2 ns when others gt ce0 n lt 1 celon etr ce2 n lt 1 ce3 n lt 1 end case address strobe control acnt acnt 1 are n lt 0 after 2 ns ea to stdlogicvector address 21 downto 2 after 2 ns wait until eclk in event and eclk in 1 acnt acnt
5. 185 JP4 Module 0 Pin JP5 Pin Numbers Sbc6713e User s Manual PIN1 PIN3 PINS PIN PING PIN11 PIN13 PIN PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 JPSA MDR 100PIN JP4 Module 0 Pin JP5 Pin Numbers PINZ PIN4 PING PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PINSO 186 The following table shows the interconnections between the JP8 OMNIBUS slot and JP5 OMNIBUS IO connector JP8 Module 1 Pin JP5 Pin Numbers JP8 Module 1 Pin JP5 Pin Numbers 62 12 61 10 59 58 37 55 54 53 52 51 Sbc6713e User s Manual 187 JP5B MDR 100PIN PIN 1 PINS PINS PIN PIN9 PIN11 PIN13 PIN PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PINS7 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 9 8 7 6 5 4 3 2 1 Sbc6713e User s Manual PIN2 PINA PINS PINS PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN3O PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PINSO 188 JP6 7 9 10 OMNIBUS Bus Connectors Connector Types AMP 05 Subminiature D male Number of Connections 50 Mating Connector AMP 173279 3 The following table gives the pin numbers and functions for the JP6 OMNIBUS slot 0 and JP9 OMNIBUS slot 1
6. a Tuck Left This operation can optionally be initiated via the button 3 EA Tuck Right Form Tuck Right repositions the main application window to the bottom right of the Windows desktop This operation can optionally be initiated via the button The Help Menu Help Usage Instructions displays online help detailing use of the application including command line arguments gt Dsp Form Help This operation can optionally be initiated via the button al Z Ex E m Pi ine Help About this Program displays a dialog containing program revision and tech support contact information Options Tab The Options tab seen below contains controls to allow user customization of the appearance and operation of the terminal emulator Sbc6713e User s Manual 27 RTDX Terminal CPU_1 3 lol xl File Dsp Form Help alga a aaa e 2 Display gt Sounds v Errors fi 0 Polling Interval mS Y Suspend AlwaysOnTop vw Pause on Plot v Alerts JV Clear On Restat JV Log Scrolled Text Font Debugger Rtdx Heterogeneous gt DS560 Multi T arget y Board Jox400 Buffer Size bytes cPu 1 zi Cpu fi Rtdx Buffers Cof Loain Resetbefoe JV Run after Terminal Log Options Console initialized Dre 0 000 Figure 7 RtdxTerminal Options Display Group Controls within the Display group box govern the visual appearance of the terminal emulator as detailed below
7. essere enne nennen enne enne ne nnne nennen nnne 13 Innovative Integration Web Sttes eene eem airada 13 Typographic Convehtlofs oie ir eti a p te reme te nete Tete etie edet ure ier nsu eve 13 MWandows EnstallatIOI ase cases scutes tdo Host Hardware Requirements nes deed eta E ede ri rede e e ee ie dust a ies te e een Ies 15 Software Installation Lr 15 Starting the Installation osen nenir nr tee eie RR e eere e E ER e Pe TR E d Ree SEE 16 The Installer Program idi ee e e D Re HE enue 17 Tools Registrations ssi ede reete a e e E CE RAE C eet D de eed e E Er Ln EE P e EUR dae 19 Bus Master Memory Reservation Applet ooooonconoconnnnocnnonooonoonconocononnconncononnonn non nro n nro n rn r non neret tenenti enn inneren 19 Hardware Installation AA ia 20 After PoWer p eer IR A di 21 JTAG Hardware Installation dal JTAG Emulator Hardware Installation for DSP boards Only nnne 22 PCT Pod Based Emulator Installation iaa gan bela se 22 Baseboard Installation dei E ad e e ee Ee Een ente Oe IR ERG 23 A Few Considerations BEFORE Powet up ccccsccssssssesssseseeseceseeseeeaeesecesecseeeseccesseseeecseseaeeseeaecsesesecaeeeaeeeeesaeenseeaeensteeaes 23 It caninot be overemphasized ii e e RED RH e RH ONERE EDO GE EPIRI 23 After Powet p z e Aetnae in i eet tet m Adice 24 Code Composer Studio Setup with II Jtag sese enne nne nnne E nennen innen nennen nnne 24 Setting up for a single processor with Spectr
8. A dimensional schematic and the board layout is displayed on the following page Please review these drawings to familiarize yourself with the circuit board s configuration and connections JP OMMJBUE 1 0 eco 000 1000000 PIE LAM PRICES ae JTAE ml i n 22258 APIA APP BROT AHER JP13 BTL3 MAPA 4P13 ATLA Waara APL BIBITAL 150 MZ3 TEST OMT PLA ERT amp LK Stehn ENABLE P18 EXT JM Bebe ENPBLE JPZ 3TMELINLIELOCKLINE NESET LTD Pa UT ARAE JPLI ETHEIM TL Sbc6713e User s Manual 203 Board Layout Rev C A dimensional schematic and the board layout is displayed on the following page Please review these drawings to familiarize yourself with the circuit board s configuration and connections i o 2 9 N N 5 c 5 a S a o 9 o o o 2 O 2 x wn Sa 33 Sa i ad as ash 9 r sf o D Z8 z 8 zo g TY nz oz amp 5 2 Soe 268 Sof 3 E 2 o A o y c c z o az o INE 2 al o la o lt x o e amp a Tun x E m c TO pum o a a Annum So jL gt mmm E S SO TTT ee a T ejj Oo gt ST CTT TT a E TTT Y 2 mi y Pa Pa 0zx TT TTT 7 o gt 2 2 gt Yes 5 p ED gt g ed vn gt n 2 g o at pe 4 v3 g Q c 9 D gt x 33 vos E 3 a uU a O T 22538 d
9. Hdr LoadFrom Buf printf Cmd d d Sd d n Hdr Type Hdr ArgO Hdr Argl Hdr Arg2 else int Data Buf IntAddr printf PktSz d x x x n Buf Ints Data O Data 1 Data 2 bool Ok true for int i 1 i Buf Ints it if Data i OxEEEEO000 i Ok false if Ok printf OkMn else printf Ok false y MsgRecvThread ReceiveLoop tpNormal Sbc6713e User s Manual 67 class MsgSendThread Thread priority public Methods void Execute int cCount 0 ys int Toggle true while Terminated Transfer XI ry IntBuffer Buf 1000 int Data Buf IntAdder for ant 2 lr r Buf Ints itt Data i OxCCCCOO00 i Sleep 500 Send Command or User message if Toggle Xfr SendCommand 0x009 cCount OxDEED OxABBA printf SendCmd Sd d Sd d n 0x09 cCount 1 0 0 else Data 0 cCount Xfr Send Buf printf SendPkt Sd d Sd d n Buf Ints cCount 1 0 0 Toggle Toggle y MsgSendThread SendLoop tpNormal void IIMain RecvLoop Resume SendLoop Resume Sleep SYS FOREVER Details on methods and data members are found in the online help Sbc6713e User s Manual C Terminal I O The terminal emulator is a Host PC application which provides a C language compatible terminal emulation facili
10. Figure 44 Xilinx Parallel Cable IV Top View Courtesy of Xilinx b Rl Figure 45 High Performance Ribbon Cable Courtesy Of Xilinx Slave Serial JTAG INIT NC 14 13 GND NC NC 12 5 95 11 GND DIN TDI 10 J9 GND DONE TDO 8 u 2 7 GND CCLK TCK 6 u o 5 GND PROG TMS 4 3 GND Vref Vref 2 1 dici JP25 3 3V POND b2 5 INTF_SP2 TMS 4K 7 2 BPiSB 4 ay INTF_SP2_TCK 1K g 3 RP103C gt DGND O3 3V DENS INTF SP2 TDO BOND INTF SP2 TDI K 5 4 RPIOSD o3 3y DGND 1 12 012 x DGND 13 14 px HEADER2X7_2MM Figure 47 SBC6713e JP25 Spartan IIe 300K 600K JTAG Connector Note After loading the logic through JTAG if you power cycle the card or if you hit the board reset then the Spartan Ile is loaded with the logic you had in Flash ROM Sbc6713e User s Manual 167 CAUTION The user SHOULD make sure that Xilinx Parallel Cable IV Target Interface Connector signal assignments matches with the Innovative header JP25 on SBC6713e for Spartan IIe If by mistake the user connects the Xilinx cable incorrectly there is a very good chance of damaging the SBC6713e card and Xilinx POD Declaration Of ChipScope Core in VHDL The ChipScope core is simple to use Just connect up the signal for observation to the data ports the trigger signals to trig and the clock The number of ports and triggers is defined when you create the debug core in the ChipScope tool Here s a core we used in debug shown
11. IntBuffer amp Acquire Cursor 0 Requested true Available Acquire return Snaps Sbc6713e User s Manual 43 protected Fields volatile int FCount Data bool Requested Semaphore Available IntBuffer Snaps int Cursor int CaptureEvents Methods void Execute echo input to output while Terminated AIn Get FCount If main thread wants a block copy it to him if Requested continue int Residual Snaps Ints Cursor int Chunk std min Residual AIn Buffer Ints Snaps Copy AIn Buffer Cursor Chunk Cursor Chunk if Cursor CaptureEvents Requested false Available Release y LoopThread Loop tpHigher Not Just for C Experts Note that even if you re not a C maven the code is quite clear and understandable In fact one of the benefits of using C is that while it helps to mitigate and manage complexity to support creation of larger more sophisticated applications it is calls to legacy C functions newly written C functions Assembler functions and C functions called methods within C4 programs You need not fully understand all of the enhanced capabilities and features of C in order to fully exploit the features of the class libraries provided in Pismo Analog I O Streams often simply used as a better dialect of the C language C is essentially a superset of C As such
12. Properties to invoke the Properties Dialog for Connection C714 x05510 Emo pomos Tes 23 Under the Connection Name amp Auto generate board data file with extra configuration file Data File tab the Connection Configuration r CCStudio divers ipcipod cfg Name edit box should match the emulator selected in the System Configuration Pane of the dead Browse previous window Change the mJ amp amp Configuration File combo box to Auto generate board data file with extra configuration file Change the Configuration File edit box to lt drive gt Cstudio Drivers IIPciPo d cfg lt drive gt is the letter for the drive onto which CCS is installed 24 Click the Connection Properties tab Set the I O port value for the driver to virtual device address 21x 0x0 and click Finish Connection Name amp Data File Connection Properties Property Value 25 The main Code Composer Studio Setup window is a now back in focus The processor must now be configured To do this select the processor as shown in the System Configuration Pane in our example CPU_1 Right click CPU_1 and select Properties Change property value as necessary in the right column 26 The Processor Properties screen will be presented Click GEL File click the ellipsis and navigate to the Innovative Integration board install directory Canc
13. TMS320C6710 Driver Location CAGCCStudiotdriversisdgobxus Driver Revision 05 27 400 Driver Description C62 9 C67xx Emulator for Windows 98 2000 ME NT XP User Description None Processor s Supported TMS320C520x TMS220C670x TMS3200624 TMS320C87 1 Capabilities Single stepping Breakpoint hiding Run profiling Step profiling Multiple processors Synchrongus tun Global breakpoints RIDX Multiple board support Run froma breakpoint Cache bypassed reads Target Disconnect Emulator Reset 29 TMS320C6710_0 C Innovative P25M II6x gel IET XOSSEO Emulator Sbc6713e User s Manual 30 Setting up for Multi Processors with Spectrum Digital USB Jtag For the multi processor setups use the following type setup This includes the SBC6713e Quadia Q6x type Innovative boards The SBC6713e board shown will be similar in setup with the other boards The differences will be in the types of processors and the number added First remove any previous setups in the CCS Setup application Add one of the USB SD type driver System Configuration Available Connections Connection Description SD510USB Emulator a EA Other 510 Class Emul Other 510 Class Emulator Connection Processor s Supported BE Other 560 Class Emul Other 560 Class Emulator Connection TMS320F 2400 ES Other Simulator Other Simul
14. tr o 5 eow O O i 3 345537 RxD31 RxD3O RADI Ra 1 39 442 43 RxD2T RxD26 RxD25 R024 I 45 46 48 49 tz Rao RxD21 Rxb20 5555455 RxDI9 RXDIB RxDI7 RxDIG_ I_ 57 58 60 61 mois RxDI4 BR J Ooo 63 64 66 67 RxDIT RADIO RADO ps I 69 70 72 73 RxDT RxD6 RuDs Rup E AA TN Sbc6713e User s Manual 194 1 DGND Denn 3 RxNnpy N POND RXDIA N 9 3 3V 1 Q Rx suspeno_ PEND 3 RX STROBE S R17 DNP RX STROBE DGND 15 R19 R20 RX PlIO2 17 U13 169 gt 169 AX PIO1 19 3 8V MC100EPT21D 2l O 8 1 23 ia avee NCI pz RX PSTROBE P 25 e BESTT ax PS TROBE 27 NC3 DH AX SYNC N 29 GND VBB AX DVALID_N 31 Benn RX Dat 33 R21 35 249 RX D28 DGND 37 RX D27 39 RX D24 Deno 7 DGND RX D23 45 RX D20 DEND n RXD19 51 RX D16 Denn 55 RX DiS 57 AX D12 Deno i RXDH 63 65 RX D8 DGNDI a RX D 69 RX D4 Deno 7 RX D3 75 77 RX DO DENDH g Figure 52 FPDP JH2 Rx Port Connector Sbc6713e User s Manual JH2 P50E 080P1 S1 TG AENODDANOOODAN in Re Ned De pes gt ajo v 0 oeov000000000 000000 1 d 1 1 1 2 2 2 RX STROBE DGN DGND DGND DGND DGND DGND DGND RX_D30 RX D29 RX D26 RX D25 RX D22 RX D21 RX D18 XD RX D14 HX D13 RX D10 HX D9 RX D6 AXD 195 JP2 SyncLink ClkLink Connector Types 0 1 double row shrouded header Number of Co
15. QRBYPASS 38 bit GEL File NA Master Slave NIA Create Board Eg Factory Boards EW Custom Boards Modify Properties lt lt Add Multiple Remove Remove Al Select the system node to add a new board to the system configuration a Sbc6713e User s Manual 33 Borland Builder Setup and Use Following the normal installation of the Innovative Integration toolset components numerous VCL components and C classes are automatically added to the BCB IDE Additionally Innovative recommends that the following IDE and project options be manually changed in order to insure simplified use and proper operation Automatic saving of project files and forms during debugging File Edit Search View Project Run Component Database Tools GExperts Window Help fe Da a a pa B Ed e El a Sta Environment Options R Editor Options te Debugger Options p ja ge T 31 Select Tools Environment Options from the main BCB toolbar 32 This will invoke the Environment Options dialog Environment Options Environment Variables Type Library CORBA C Builder Direct Inter Preferences Designer Object Inspector Palette Librar Autosave options IV Editor files IV Project desktop Compiling and running IV Show compiler progress Beep on completion IV Cache headers on startup Warn on package rebuild IV Hide designers
16. These options insure that projects are built with minimal dependencies on external DLLs See the FAQ What DLLs do I have to deploy with my newly created executable in the Troubleshooting chapter for details on which DLLs must be deployed with user written executables Appropriate library and include paths 40 Click on the Directories Conditionals tab 41 Click the ellipses next to the Include Path edit box to invoke the Include Path editor dialog Add entries for Armada ArmadaMatador OpenWire loComp and Pismo as shown below then click OK to accept these edits 42 Next click on the ellipses next to the Library Path edit box to invoke the Library Path editor dialog Add entries for Armada ArmadaMatador OpenWire IoComp and Pismo as shown below then click OK to accept these edits These changes insure that the standard Armada headers and object files are available to projects during compilation Note that these paths may either be added to the default BCB project by editing these options without first opening a specific project or to specific projects after opening them The advantage of the former is that the settings are automatically present on all subsequently created projects Sbc6713e User s Manual Project Options for Logger6 exe BCB include BCB includeSwel BCB Ar E BCB Projects Lib BCB Mib obj BCB lib El cacao Rogen ein Directories BCB uinclude
17. ye 5 on a x A 2 onu E L c gt 2 30 om X og ner 5 E m amp Rea 4 J A Zo D22 53 Nn 2 gt zOotz amp e a Oo m zm TW OL 2 62 a 2 5 a amp o a o a ivi lt ms E g e gE 5 e o a a T u Es e Eine e Za Nn a 53 AS 2 a a E 5 T GEF E t VEG EOcr Sg 4 29 cog o x COS E ey ae c vg ses U COD x o o0 na Dre OTe 5 o T ve o g E og A a a a c rad 2gs 0 agi a 5 A a a Ego ED amp m S N Heri OC 5 Hos a qm a rod SE Y i2 esc Sse zz a m v nen v m m x FEN Lu Lu nm nm Oo oo Ke Ke gt N m a a co a a a yh Figure 57 Mechanical Drawing Board Revision C Sbc6713e User s Manual 204 600 on SCeeCeeeeeees 6 0 0 0 0 0 0 6 0 940 s eeeeeeeeeeee eeeccccccccc o CTI m CTO ul6 C45 Ys N NI 30VA 3 8 A A UE 00 9 OGIS e so o 2 AY 1 9 Ls 1896 i ej o ee 4 e IH i ee NN WI ee 059 7 m z NLT ET e 0000000000000 000000000 000000 OROTAN e e e gt e e e tut e 9 ee e e eese e 9 e e e s e e OST ee o e eses e e e bd e T Bess e 9 OS z eto a le o e o ost Z e m
18. 34 Download Client tab This is another infrequently used maintenance function to be employed only when instructed by the release notes or by Innovative Integration s Tech Support This tab updates the DM642 coprocessor client program This program is in charge of all Host lt gt Target communications loading of firmware into the two FPGAs at startup and launching of C6713 applications The format of the client program is a binary image of a COFF file produced using the Innovative PromImage applet Below is a screen shot of Download Client tab Network Settings Dwld Loader D wld Client Dwid LAN Logic DwidINTF Logic Dwld Application WARNING Downloading a faulty client program will cause system failure CAlnnowativesSBC6713 Coprocessor Examples Clent client bin Download Client Download LAN logic firmware This tab is used to upgrade the LAN logic device s firmware This logic image should be updated only under specific instructions by Innovative Tech Support using an Innovative supplied firmware image If this firmware image is corrupted the consequences are not as bad as with the Client and Loader programs since the LAN firmware can be reprogrammed using CCS running ReLANlogic out If you are working on a Rev C PCB then CCS will need to be setup again to by pass the C6713 DSP with a scan depth of 46 the C6713 is the first DSP on the scan path Also before booting the SBC6713e card a jumper need
19. 6 EXO C HEX BIN i BATCH CMD TT Swap Bits Pe BATCH CMD 4 BATCH CMD Memory Fill Value 2 Hex Digit FF ip BATCH CMD dee BATCH CMD PROM File Name FILE_NAME de CMD o d CMD Location c projects sbe671 3 intf_logic Browse d BATCH CMD i BATCH CMD eet BATCH CMD i BATCH CMD pees BATCH CMD lt Back Wee p BATCH CMD Back Cancel Help For Help press F1 Prom Formatter Figure 38 PROM Configuration In PROM Configuration Select Parallel PROM Select EXO as File Format Memory Fill Value OxFF Provide a File Name Sbc6713e User s Manual 161 C Untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help Deij AE E a ge Boundary Scan Stave Serial SelectMAP Desktop Configuration Specify Parallel PROM Device I Auto Select PROM Select a Parallel PROM Density BK he Welcome to iMPACT The intellige it BATCH CMD Pee BATCH CMD pee BATCH CMD Jr BATCH CMD ee BATCH CMD pes BATCH CMD peer BATCH CMD i BATCH CMD Je BATCH CMD ieee BATCH CMD Pee BATCH CMD ee BATCH CMD I BATCH CMD ite BATCH CMD Ir BATCH CMD i BATCH CMD per BATCH CMD ite BATCH CMD ee BATCH CMD For Help press F1 Number of Data Streams Loading Direction Prom Formatter Figure 39 Select Auto Select PROM ioe BATCH CMD ire BATCH CM i BATCH CMI dee BATCH CMD For Help pre
20. At the bottom of the display Flash info read OK should be displayed Click on the Flash Tab e Then click on the Image File button and browse to the binary file that is to be downloaded to the target DSP flash e Next adjust the Start Sector combo box to 1 and the End Sector combo box to 7 e Then click on the Burn button to start the download The downloading progress should be displayed At the bottom of the display Burn Completed should be displayed Sbc6713e User s Manual 177 5 Testing the burned bin file baseboard32 e Torun the application from the target DSP turn the power off disconnect the JTAG amp serial port and turn the power back on Alternately with the serial cable attached you may click on the Boot Embedded Application speed button on the terminal emulator to launch the embedded application rather than the embedded Talker baseboard6x e Torun the application from the target DSP turn the power off install jumper JP24 and turn the power back on Alternately with the serial cable attached and JP24 installed you may click on the Reset Dsp speed button on the terminal emulator to launch the embedded application rather than the embedded Talker baseboard6711 e Torun the application from the target DSP turn the power off install jumper JP11 and turn the power back on Alternately with the USB cable attached and JP11 installed you may click on the Reset Dsp speed button on the te
21. BCB include wel BCB Armada BCB ArmadaM atador BCB Openwire BCB JMinnovative BCB MoComp BCB Pismo Sbc6713e User s Manual 36 SBC6713e Product Migration Single Board Computer Hardware Features The hardware complement has changed on production SBC6713e baseboards between revisions B and C The nature of these changes are summarized below Table 1 Production Hardware Changes Rev B vs C Peripheral Rev B Rev C C6713 DSP SDRAM size 16 MB 32MB C6713 DSP clock speed 225 MHz 300 MHz DM642 DSP SDRAM size 16 MB 32 MB As a consequence of these changes the Pismo support libraries and application programs must incorporate appropriate changes in order to insure proper operation as detailed below Once the appropriate changes are made all libraries and example programs must be recompiled in order to put the changes into effect SBC6713e software releases greater than 0 61 have been compiled to accommodate Rev C hardware Consequently only users of revision B or earlier hardware need be concerned with implementing the changes below Changes to SDRAM initialization The larger 32 MB SDRAM devices on the revision C boards utilize a different row format than the 16 MB devices on the earlier board Consequently the EMIF Control register value must be changed Additionally running the DSP at 300 instead of 225 MHz necessitates a change to the EMIF Timer register Table 2 SDRAM Register Changes Registe
22. C6711 Code Composer Studi File Edit View Project Debug Profiler GEL OJ E Projects Click Project New on the menu bar to create a new DSP project Recent Project Files gt 81 Projectcreation x Specify the location for the new project and its s A E name In this example a new project called Test is being created in the Sbc6711 j Executable out y F 2 ore EIE zi Pismo Examples directory Change the EE e location to accommodate your board type and a processor type Y Files E 45 T6x gel After the new project has been created it will E Projects appear in the CCS project window under the 2 Test pjt Projects folder ebug Profiler GEL Option Tools PBC DSP E Close Visual Linker Recipe Saye Cubes ActiveX Document Saye As Saye All Click File New DSP BIOS Configuration to create a new TCF file for use in the project Load Program Load Symbol Add Symbol Reload Program Load GEL Data gt Workspace File 1 0 Print Ctrl P Print Preview New DSP BIOS Configuration COOK cs csa ce Select Platform Description mus dum Select a platform to see its description ti platforms dsk6416 PEPI EED sietima cdris plam daercioi s Select the relevant template for the baseboard mua maus A from the list in the New DSP BIOS Configuration ti platforms evmDM420 Prey E Browse Platforms dialog
23. IX PSTROBE P TX PSTROBE N R15 249 Sbc6713e User s Manual 3 3V R14 169 R16 249 DGND Figure 51 FPDP JH1 Tx Port Connector TX NRDY N X DIR N TX susPEND NPGND TX PIO2 TX PIO1 TX SYNC N X DVALID N X_D31 TX_D28 X D27 TX D24 TX D23 TX D20 TX D19 TX D16 X D15 TX D12 TX D11 TX D8 X D7 TX D4 X D3 TX DO JH1 P50E 080P1 S1 TG DGND DHDARNOCADANOCADAN c c co eo co e ie a a 2 m ojo ASS oo amp m o o o a o 1 1 1 1 1 2 2 2 2 2 DGND DGND DGND DGND DGND DGND DGND DGND TX STROBE DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND tx pao TX D29 DGND ty D26 TX Dos DGND y poo X D21 DGND tx pig X D17 DGND TX D14 TX DTS DGND zy pig TX DS DGND rx D6 TX D5 DGND zy pp DI DGND 193 JH2 FPDP Receive Port Connector Connector Types PSOE 080P1 S1 TG Number of Connections 80 Mating Connector P25E 080S TGF Manuf 3M The following table gives the pin numbers and functions for the JH2 connector JH2 Function Direction from SBC6713e 1 3 4 5 6 8 10 Digital Ground 12 14 16 18 20 22 24 26 28 30 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 2 fess 0i p mwbovyw O CE 5 fems t Bo Rx suspend t woo COTO o o CE m mrwew Es msmN
24. Polling Interval specifies the period in milliseconds between queries for data received from the DSP via the JTAG RTDX interface Lower numbers increase performance but increase Host CPU load Always on Top specifies that the terminal application should always remain visible atop other applications on the Windows desktop This check box controls whether the terminal emulator is forced to remain a foreground application even when it loses keyboard focus This is useful when running stdio based code from within the Code Composer environment when it s preferable to make terminal visible at all times The terminal will remain atop other windows when this entry is checked Select the entry again to uncheck and allow the terminal emulator window to be obscured by other windows Clear on Restart specifies whether the terminal display and log will be automatically cleared whenever the DSP is restarted Pause on Plot specifies whether standard I O will be suspended following display of graphical information in the Binview applet which is automatically invoked via use of the Pismo library Plot command If enabled standard I O may be resumed by clicking the cy button Log Scrolled Text specifies whether text information which scrolls off screen on the Terminal tab is appended to the Log display If enabled standard I O performance will degrade slightly during lengthy text outputs Sbc6713e User s Manual 28 Font button invokes a fon
25. Sbc6713e User s Manual 197 JP23 JTAG Debugger Connector Rev C Connector Types Shrouded header pin 6 removed for key Number of Connections 14 Mating Connector AMP 746285 2 The following table gives the pin numbers and functions for the JP8 connector Rev B JP8 ONLY connects to the 6713 DSP JTAG port RevC and onward The JTAG path for the DSP and DM640 have been combined into a single scan path with the 6713 first followed by the DM640 Table 21 JTAG Debugger Connector JP8 Function Direction from SBC6713e moo e CO E Jie PROCESSOR JTAG HEADER DSP TMS DSP TRST DGND DM642_TDO DSP_TCK DSP_EMUO amp gt DSP_EMU IDC14VM JTAG Figure 55 JP23 JTAG Debugger Connector Sbc6713e User s Manual 198 JP22 Power Input Connector Connector Types 6 pin locking power connector Molex 43045 0602 Number of Connections 6 Mating Connector Molex 43025 0600 and contacts The following table gives the pin numbers and functions for the JP22 connector Table 22 Power Input Connector gt Mop PwWRpowersonor o Jag Figure 56 Power Connector Pin Positions side view from front of connector showing connector keying and locking tab along with printed circuit board position Note Matting connector may be numbered differently Sbc6713e User s Manual 199 JP3 Asynchronous Serial Port Connector Connector Types Shroud
26. addr O 00003320 size 0x7bal Loading lt hi addr 040000b4c0 size 0x00c0 Loading lt args gt addr 0x00003918 size 0x0004 Loading lt text gt addr 0x0000b580 size 0x626e0 Loading lt cinit addr 0xa0001178 size 0x1834 Loading lt pinit addr 0xa0000054 size 0x0024 Loading lt sysinit gt addr 0xa0002ae0 size 0x03c0 Loading lt gblinit gt addr 0xa0002f0c size 0x0028 Loading lt consb addr 0xa0002f38 size Ox4fd1 Loading lt ttdx_text gt addr 0xa0008360 size 0x1120 Loading lt trcdata addr 0xa0008348 size 0x000c Loading lt log gt addr 0xa0009a10 size 0x0018 Loading LOG system buf addr 0xa0009b00 size 0x0100 Loading lt sts gt addr 0xa0009c00 size 0x0030 Loading lt trace gt addr 0xa0009c30 size 0x4000 COFF translation complete Total bytes 492756 Result Succeeded creating C DataAcquisitionNode Examples Analogin Debug 4nalogin bin A FlashBurn FlashBurn exe is a windows application that enables the user to update firmware exo logic images or an embedded application COFF images into the Sbc6713e flash It enables the user to choose whether to boot up the C6713 DSP using the user s embedded application or to boot the default Innovative Integration benign program The user can reverse option at any time This is an important feature useful when testing or deploying an embedded application The tool also enables use of static IP or DHCP server assign
27. connectors The functions for JP9 are identical to those of JP6 except where noted Table 16 OMNIBUS Bus Connectors 21 43 40 45 Address bus 2 8 39 26 27 Reset active low 37 5 MHz IOMOD4 7 decoded selects active low active low 25 23 Analog 15V OMNIBUS 12V Analog 15V OMNIBUS 12V Analog 5V Analog 5V Sbc6713e User s Manual Direction from SBC6713e I open collector 189 The following table gives the pin numbers and functions for the JP7 OMNIBUS slot 0 and JP10 OMNIBUS slot 1 connectors Table 17 I O Module Bus Connectors JP7 Function JP10 Function Direction from SBC6713e Address bus 9 13 eR 2 19 20 49 Digital ground O power 50 i UM B 17 wakwgeo O Momem O Module tigger o Processor mer tana o Module riegerin Exemdwgei o Analog 15V OMNIBUS O power 12V Sbc6713e User s Manual 190 JP1 Digital I O Connector Connector Types Number of Connections Mating Connector 0 1 double row shrouded header center bump polarized Thomas and Betts 609 5027 AMP 1 746285 0 JP1 IDC50VM DXO 1d b2 DXI DX2 35 4 DX DX4 5d 56 D X5 DX6 Ta 58 DX DX8 99 10 DX DX10 115 5 12 DXt1 DX12 137 14 DX13 DX14 156 616 DX15 DX16 175 518 DX17 DX18 197 20 X19 DX20 217 22 DX21 DX22 237 124 DX23 DX24 250 26 X25
28. pkChunkHeader Header 1 16384 bytes or the remaining of the image file lt 16384 Header 1 0 b ACK from Target int aSendPacket 3 aSendPacket 0 pkChunkHeaderAck aSendPacket 1 0x00 aSendPacket 2 0x00 c Host sends Data chunk and Target ACKs it aSendPacket 0 pkChunkDataAck aSendPacket 1 0x00 aSendPacket 2 0x00 4 c will continue until last chunk of data sent when this happens Host will send following command packet 0 pkLogicDownloadDone packet 1 0 packet 2 0 5 Target will acknowledge this command aSendPacket 0 pkLogicDownloadDoneAck aSendPacket 1 int status ibOk ibBadXmitChecksum ibBadBurnChecksum aSendPacket 2 0x00 enum PakTypes k kIntfLogicDownloadRequest kLogicDownloadRequestAck k k jogicDownloadDone jogicDownloadDoneAck kChunkHeader kChunkHeaderAck kChunkDataAck kLoaderDownloadRequest kTalkerDownloadRequest ote 0 0 UO 0 o S OD Sbc6713e User s Manual anLogicDownloadRequest 0x 79 pkAppDownloadRequest y enum ImageBurnStatus ibOk ibBadXmitChecksum ibBadBurnChecksum 6 Host closes socket Please refer tp SRecord_Mb cpp and BinFile Mb cpp so that you may see how we parse the different data files also refer to NetImageLoad_Mb cpp Sbc6713e User s Manual 80 Building a Target DSP Project Building a project suitable for a Matad
29. 1 are n lt 1 after 2 ns aoe n lt 0 after 2 ns acnt 10 for i in 1 to burst count 1 loop wait until eclk in event and eclk in 1 if acnt 00 then are n lt 0 after 2 ns else are n lt 1 after 2 ns end if Sbc6713e User s Manual 165 acnt acnt 1 end loop wait until eclk in event and eclk in 1 ce0 n lt 1 cel m lt 1 cea n lt 1 ce3 n lt 1 ea lt others gt H after 2 ns wait until eclk in event and eclk in 1 finish burst write are n lt 1 awe n 1 aoe n lt 1 ed lt others gt H after 2 ns end burst read Figure 32 VHDL Procedure For DSP Burst Read Access wave default EER File Edt View Insert Format Tools Window oS Ga AA XC A LAB E ASAS B bcB713 top Ib pdp_twfpdp_config Dnnora a 000 of ABAS000 0 sbob713 top Ib uut insl pd rx wen a Ban apeg Cursor 69000ps 12763781 ps to 13918512 ps Figure 33 Data Read From FPDP Tx FIFO And Data Write to FPDP Rx FIFO Sbc6713e User s Manual 166 Wave default File Edit View Insert Format Tools Window sus bRa Ret e wi QQ amr E E 8 m 8 sbcB713 lop th wt fpdp bud FFFFFFFF Cursor 1_ 376500 ps EX H 21616099 ps to 22770930 ps Figure 34
30. Then use the TermFile Open method to open the file for access on the host using the desired open attributes if File Open wave bin w b term lt lt nOutput file open error Program terminating lt lt endl term monitor This method returns a Boolean indicating success if the file open is successful To store data into the file or retrieve data from the file use the Write or Read methods respectively For example transferred File Write char amp Buffer 0 10000 writes 10000 bytes of Buffer into the disk file When disk operations have been completed the file should be closed using the TermFile Close method Sbc6713e User s Manual 70 Detailed Host Target Communication Overview This chapter explains protocol details on how the Host Transfer communication is performed thus being a guide for those wanting to develop custom host libraries You may want to have the Malibu files NetTransfer_Mb cpp and Sbc6713e Mb cpp files opened The documentation in this chapter is according to the client firmware version 3 8 in your Sbc6713e target DSP board The name client bin is misused since the DSP board is really the server Clarification The Sbc6713e acts as a Server the Malibu library Host PC software behaves as a Client We use an ACE SOCK Stream object called client to open communication sockets close sockets and to send and receive data Please refer to The ACE Programmers Guide
31. click the JTAG radio button and then click the Debugger button to browse to the location of your JTAG debugger software usually c composer cc_app exe if you re using Code Hammer or c ti cc bin cc_app exe if you re using Code Composer Studio and click Open Next click on the Script File button to browse to the location of the Flasher gel file located in the root directory of the board specific Zuma libraries ie c baseboard6711 Flasher gel and click Open Under most circumstances you should enable the Autorun Script check box as well With this feature enabled the specified Code Composer GEL script file is automatically executed as the debugger is started A default script file has been provided and is located in the root directory of the Zuma Toolset installation This GEL file automatically initializes the target DSP downloads the Flasher out support executable and launches it using the debugger Run Free command In rare circumstances you may elect to disable the Autorun Script option When this feature is disabled BURN will automatically launch the debugger when you click the Run button but you must manually load and run the F1asher out executable For example this option is useful when using a debugger other than Code Hammer Sbc6713e User s Manual 174 Flash ROM Download To download using the Talker in flash ROM click on the Flash ROM radio button and then click on the Coff File button to browse to the location of the
32. extended periods without software intervention This means latency must be increased data may be in the queue for some time until additional data forces it out to the application Of course if the application does not process the data as fast as it arrives data will eventually be lost Sbc6713e User s Manual 45 Burst Streams use a different model Here data movement is on demand instead of asynchronous If no request for action by the application is received the Stream is idle This type of Stream is more common for non Analog I O such as the FifoPort or PCI busmastering but the CaptureInStream implements a burst type I O model on the analog hardware Stream Buffer Model Each Stream uses data buffer class objects to pass data between its hardware and the application These buffers are all the same size Passing data between Streams is simple if the buffers are chosen to be the same size Ain Get Aout Put Ain Buffer Buffer transfers are efficient because the data buffers are not copied at any time during the transfer process By default Streams allocates three buffers two internal and one swap buffer If desired the number of internal buffers in the pool may be modified prior to opening the Stream by assigning a new value using the BufferCount method Instantiate the analog stream objects AnalogOutStream Aout Aout BufferCount 5 AnalogInStream Ain Ain BufferCount 5 This code forces the Stream to alloca
33. s gt 9 o CEx CN 5C i ERI mt OD is Bep Xr 1 keh A L 9 EA 21 2 X Address i 11 i 9 ED 31 0 _ Write Data i _ _ AOE SDRAS SSOEt i q NIE fe SG aks Se O ES ARE SDCAS SSADSt gt K 10 i ee Ea i D gt l 6 1 6 any MO 0 A t AOE SDRAS SSOE ARE SDCAS SSADS and AWE SDWE SSWE operate as AOE identified under select signals ARE and AWE respectively during asynchronous memory accesses Figure 15 DSP Asynchronous Write Timing Courtesy of Texas Instrument For slow speed devices such as configuration and control registers asynchronous access are used in the Framework Logic Asynchronous accesses provide the most flexibility in timing control and are the easiest to use in most designs albeit the slowest The EMIF control registers in the DSP allow the programmer to define SETUP STROBE and HOLD lengths for the Sbc6713e User s Manual cycle that give a programmability to the access timing For more control the ARDY signal allows the logic designer to insert additional wait states to the STROBE timing as needed For the high speed data paths in the Framework logic burst accesses from the DSP provide the highest data rates The EMIF configuration registers are set for SBSRAM memory interface timings and in the logic the FIFOs respond to these signals to deliver data in continuous bur
34. src_array 0 DestinationAddr int dest_array 50 Cfg ElementCount 50 ElementIndex 1 Cfg FrameCount 0 FrameIndex 1 Ed AddLink Cfg Ed LinkTcIntInstall 0 Isr Binder Sbc6713e User s Manual 59 Ed TcIntClear This EDMA operation will trip a terminal count interrupt when all data has been moved InitArrays Ed TcIntEnable true qdma not done true Ed Submit We software initiate the EDMA here but if this EDMA were using EINT4 7 then an external int hardware pulse would remove need for Ed Set below Ed Set while qdma_not_done Need to sync L2 cache with the of SDRAM so that CPU can see the data CACHE clean CACHE L2 dest array sizeof dest_array Transfer the second transfer block Ed Set while qdma_not_done Need to sync L2 cache with the of SDRAM so that CPU can see the data CACHE clean CACHE L2 dest array sizeof dest_array The above example sets up a two block linked transfer triggered by software A TC Interrupt is configured to signal the completion of each block in the transfer The mainline waits for each block transfer to finish as notified by the interrupt handler Then the next block transfer is triggered by a second call to Set The Cache functions are required to assure that the cache and memory contents are back in synchronization Linked and Chained blocks EDMA transfers may span multiple transfer blocks On the com
35. you may freely intermix The Analog I O is for most applications the most important feature of the SBC6713e baseboard Most of the peripherals on the hardware are related to Analog I O Most of the configuration options are related to Analog I O It is the part that causes the most problems in development Sbc6713e User s Manual 44 To maximize the chances for success the Pismo library provides a set of classes that hide all of the details of data acquisition From the application level the user simply processes buffers of data The details of hardware and software management are isolated from the application Stream Objects and Device Drivers Data I O in DSP BIOS is accessed and controlled via custom device drivers Access to the device driver is controlled by a Stream class These drivers are dynamically installed by the Stream when needed by the user application From the point of view of the application the stream control class provides all of the user interface function needed to configure and operate the I O operation Table 5 Device Driver and Stream Classes Device Driver Class Stream Class Description AnalogInputDriver AnalogInStream Streamed Input from an analog source Continuous data flow with buffering Data flow stops only via trigger control AnalogOutputDriver AnalogOutStream Streamed Output to an analog source Continuous data flow with buffering Data flow stops only via trigger control CaptureInputDriver
36. 1 1 1 1 1 MI 1 Kl 1 4 5 5 3 22 K20 Input Inout InOut now 3 o zi Pinout Pinout Pinout Pinout Pinout Pinout Pinout inoue mou uos uou mouw Pinout Pinout Pinout Pinout Pinout Pinout Pinout Pinot Pinout i i i i i mi mi i i i i i i i i i iei e i 2 2 2 2 2 23 31l31l2 21 21 231I31I21 21 21 31 I31I213213 oj ojojojojoj oj olojo o Oo Oo O Oo O O O O O O ceieje eileigejeijieijseiecicieleijleijeieileigeijeijelec 2 I i I I i I i Description Ready Signal from module 0 Ready Signal from module 1 Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Module 0 Data Interrupt 0 from module 0 Interrupt 1 from module 0 Module 0 timer 0 clocks output selection Module 0 timer 1 clocks output selection Module 1 Data Module 1 Data 59 Signal Name modl_data lt 2 gt modl_data lt 3 gt modl_data lt 4 gt Assigned Pin J20 G22 F2
37. 50 Figure 22 FIFO Component Instantiation eese ertet ttet teten tutae ente tne tne ENESES SEENEN ENESES tn ennt nana 50 Figure 23 Using the FIFO Interrupt Eltern Iti e b e de e Be c e E e teria ernest 51 Figure 24 DSP Burst Read and Writes ueteri A e PE NE EU ae Hotte eed 51 Figure 25 BUFGDLL Schematic Courtesy of Xilinx eese nennen enne enne nnn nnns 52 Figure 26 Clock Period Constraints vi unen Ere tete eU eg e e PU be e e ien do Rt 52 Figure 27 DSP Signals Timing Constraints i 2 eripe la 53 Figure 28 IO Standard Constraints i a ro eo t o ien Ie Ete Eae edet ieget e ede neta 53 Figure 29 VHDL Procedure for Simulating a DSP Async Access ener 163 Figure 30 VHDL Testbench Code For Omnibus recessisse etee tette edens tete tatnen tn a tne Phe nonne einst 163 Figure 31 Omnibus Writes And ReadS oooinononnnnncnnonicnnnnnnnnnnnnnnnonnonnnnonnonnn n a tnt none a a i rennes enne 164 Figure 32 VHDL Procedure For DSP Burst Read Access ennennennenneteenne tnter enne ene 166 Figure 33 Data Read From FPDP Tx FIFO And Data Write to FPDP Rx FIFO eene nen 166 Figure 34 DSP Burst Reads From FPDP Rx FIFO eese nete entrent tne tee nente enne trennen 167 Figure 35 Burst Wntes And Re ads era A Ronee pde age eese edt idees iuda 167 Figure 36 Sample For Simulating DSP Interrupt Servicing sess 167 Figure 37 Click on PROM File Option peores E
38. 63 Communication between Host PC and DSP Co Processor sese nnne enne ene 64 Communication between Host PC and DSP Target Processor sse enne nnne 66 Go M Knie 69 Target SoftWare ieri i ire 69 ABETO aE I EE E T T T TA T 69 Sbc6713e User s Manual Detailed Host Target Communication sccccssccsssscssssccssssccssssccscscscsssscsscssssscssescssscsccssssscssssssccseeee T OVA oen ep a Rd e eb AH eR qi que ne RE 71 L COEF file downlad fix 35 erento p a eqq eese eee e p noes 71 IE Sending data to Target ise AA a ee Me ee A eres ec E reas 72 All Data Packets intended to reach the Target C6713 must have an even size of 32 bit words and a minimum A e S de hg ea eat dhe cea tas EQ ene wastes Eee pe sen e get pest ee pde deceit ses 74 II Receiving data from Late ipee en reete De i 74 III Sending RESET command to Target enne en enne nnnn ns 76 IV Requ sting Board information etes tete ei ne en Rn te ge ot e e tent T V Write Board information ees een an deatur e IR EE ep Ant te ire e een ee o aii T XT Burning Firmwate erac tote teet etel een a e v a et a ur et eO QV 78 Building a Target DSP Project E S L Writing a Program 5st ia 86 Host Tools for Target Application Development sese nnne nnne enne nnne nnns 86 Components of Target Code cpp tcf emd pjt sssssssssssssssssssssees
39. At the end of the installation process you will be prompted to register Regi ion Inf 1 E Hen erant If you decide that you would like to register at a later time click User Name Register Later First Email When you are ready to register click Start All Programs Innovative Ades Board Name Applets Open the New User folder and launch reactor NewUser exe to start the registration application The registration i Ded form to the left will be displayed Area Code Number Extension Fax Before beginning DSP and Host software development you must estaba register your installation with Innovative Integration Technical Tm support will not be provided until registration is successfully Name completed Additionally some development applets will not operate Address until unlocked with a passcode provided during the registration City State process Country Postal Code It is recommend that you completely fill out this form and return it to Innovative Integration via email or fax Upon receipt Innovative Integration will provide access codes to enable technical support and Y Hep E Register Now RegisterLater unrestricted access to applets Product Board M6713 X Figure 4 ToolSet registration form Bus Master Memory Reservation Applet At the conclusion of the installation process ReserveMem exe will run except for SBC products This will allow y
40. CaptureInStream Burst Input from an analog source Data flow is discontinuous filling each buffer requested and stopping ServoBase ServoIntf Continuous low latency analog capture and playback suitable for performance servo control applications Event at a time application data processing Stream FpdpInStream Burst Input from the FPDP hardware Stream FpdpOutStream Burst Output to the FPDP hardware Hardware Isolation and Independence The Analog and the Capture driver allow a single Stream to be used with different analog hardware In the SBC6713e for example Omnibus modules allow a wide variety of analog choices on a single baseboard Each of the Stream classes can be attached to a particular module and will automatically configure itself to use that hardware The Servo driver provides low latency interrupt driven data processing suitable for real time control applications albeit at the expense of high CPU usage It is currently implemented only for the Servol6 module The FpdpInStream and FpdpOutStream drivers provide communications with external Front Panel Data Port devices Stream I O Types There are two distinct categories of Streams implemented within Pismo Continuous and Burst Continuous Streams use the model that the input or output 1s a continual process whether periodic or not Thus in order to avold data loss when the application is momentarily busy internal buffering is provided so that the hardware may operate for
41. Code Composer Studio debugger or via the terminal emulator Code Composer Studio may be used for both code authoring and code debugging Details of constructing projects for use on Innovative DSP platforms are given in the above section of this chapter Do not confuse the creation of target applications code running on the target DSP processor with the creation of host applications code running on the host platform The TI tools generate code for the TI DSP processors and are a separate toolset from that needed to create applications for the host platform which would consist of some native compiler for the host processor such as Microsoft s Visual C or Borland Builder C for IBM compatibles To create a completely turnkey application with custom target and host software two programs must be written for two separate compilers While Innovative supports the use of Microsoft C C for generation of host applications under Windows with sample applications and libraries we do not supply the host tools as part of the Development Environment For more information on creating host applications see the section in this manual on host code development This section supplies information on the use of the development environment in creating custom or semicustom target DSP software It is not intended as a primer on the C language For information on C C language basics consult one of the primer books available at your local bookstore Components
42. DSP Burst Reads From FPDP Rx FIFO burst write 2 32 FPDP FIFO X a5a50000 write some data into the FPDP FIFO burst read 2 64 FPDP FIFO Read Data from FPDP Rx FIFO Figure 35 Burst Writes And Reads print print CHECKING INTERRUPT set the interrupts polarity and type async access 1 0 X 000400 X 00000000 async access 1 0 X 000300 X 00000000 select interrupts async access 1 0 X 000900 X 40100000 async access 1 0 X 000500 X C0010000 async access 1 0 X 000600 X 00020000 async access 1 0 X 000700 X 00040000 async access 1 0 X 000800 X 00000080 async access 1 0 X 000A00 X 00080000 set all interrupts active low set interrupts to edge sensitive nmi int ext clk 0 using ack d int int4 mod0 int0 using ack d int int5 mod0 intl int6 modl intO0 int7 modl intl dma int fpdp rx fifo interrupt Figure 36 Sample For Simulating DSP Interrupt Servicing Sbc6713e User s Manual 167 Loading the Logic Image For the SBC6713e usually an EXORMacs format text file must be generated from the output BIT file produced by the place and route process This is done by opening the PROM File Formatter utility from within the ISE and converting the BIT file into an EXO file The PROM properties must be set to byte wide and EXORMacs to generate the required EXO file Once the properties are set the EXO file is generated in the s
43. DX26 276 28 DX2 Dx28 297 30 DX29 DX30 316 32 X3 O 335 b34 1 ri 359 536 m EXT DIG RD CLK RP9A 8 1 100 375 538 A Li 395 5 40 Li O 41 b 42 1 LI 439 b44 m O 459 b46 CJ Li A76 b48 Li pvcc o Bo p39 peNp The following table gives the pin numbers and functions for the JP1 connector Table 18 Digital I O Connector sa CCT PR 38 48 Not used 7 Sbc6713e User s Manual 191 JH1 FPDP Transmit Port Connector Connector Types PSOE 080P1 S1 TG Number of Connections 80 Mating Connector P25E 080S TGF Manuf 3M The following table gives the pin numbers and functions for the JH1 connector JH1 Function Direction from SBC6713e 1 3 4 5 6 8 10 Digital Ground 12 14 16 18 20 22 24 26 28 30 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 fp msme CAN p ewon o mpw 0 Bo nsan o m mms CA Ds mmo CN ps mumexp A m mrwww CON ps msww O CO 1 rowan b 3345537 most mox mb nom O0 39 40 42 43 TxD27 owe mos mp Jo 454549 TxD23 mox mb npo Jo 51 52 54 55 mbi mom mor O0 57 8 60 61_ TxD15 TxD 14 mb noo Jo 53 64 66 67 mbi mpm mo mps 0 O 9 7 75 mb mp mbs mpa O 15 70 1879 TxD3 TaD mp o Sbc6713e User s Manual 192 R13 169
44. FAA Output mempmbsb rsen Goelo KIT impar Reser te Loge U ns nective ow uz Output Rewestsmi uaR F19 synclink_extimer_t lt 0 gt InOut Synclink Multi Card Timing Synchronization PULL UP Counters Run through external inputs readable through DSP InOut Synclink Multi Card Timing Synchronization Counters Run through external inputs readable through DSP InOut Synclink Multi Card Timing Synchronization Counters Run through external inputs readable through DSP synclink_extimer_t lt 3 gt B19 InOut Synclink Multi Card Timing Synchronization PULL UP Counters Run through external inputs readable through DSP _ extimer_t lt 1 gt P synclink extimer_t lt 2 gt PULL UP synclink extimer_t lt 4 gt InOut Synclink Multi Card Timing Synchronization Counters Run through external inputs readable through DSP PULL UP InOut Synclink Multi Card Timing Synchronization Counters Run through external inputs readable through DSP synclink extimer t 5 PULL UP Sbc6713e User s Manual Signal Name Assigned Input Description Pin Output ONFIG PROHIBIT C2 ProhibitContraint Prohibit Contraint NFIG PROHIBIT H19 ProhibitContraint NFIG PROHIBIT H20 ProhibitContraint C xs TT conr PRONI wy Prohibit Contains CONFIG PRONI mo Prohibit Contains cona Pron us ProhibitC
45. Flasher out file This file is usually located in the root of the board specific Zuma libraries directory ie c baseboard6711 Flasher out Downloading the Flash Support Code Close Code Composer if you had been using the debugger click on Debug Run Free before exiting To download the flash support executable Flasher out click on the Run button The program will deliver the Flasher out executable image into the Target using the selected method When the support code has been download and is running the status bar will display Flash Info read OK If you have difficulty running the support executable refer to the Common Problems section for troubleshooting suggestions Flash Page When the support code has been downloaded and is running the status bar will display Flash Info read OK Next you may burn binary images into the Flash ROM of the target DSP Click on the Flash tab to change to the Flash Burn page seen below 5 Burn Of x File Help Target Talker Flash Info B xamples T arget E MBE D bin Image File Range Start End Erase 1 isl Sector El Sector EI 0 Offset Bum Click on the Image File button to select the binary image file that is to be burned into the DSP flash Note that BURN is incapable of burning DSP COFF executables OUT files directly You must use the other tools in the Zuma Toolset specifically CodeWright TIDeps and the TI HEX Conversion Util
46. Huston Johnson Syyid Addison Wesley for questions regarding ACE source The Ace Wrappers are free source Mint 32 bit word short 16 bit word byte 8 bit word I COFF file download This procedure downloads an executable file to the target DSP board It uses socket number 1007 NetCoffLoadThread Mb cpp and Sbc6713e Mb cpp can be used as references to understand the following explanation Protocol After establishing and opening the socket with the target board the Host will do the following 1 Senda pkDownloadRequest command to target The data buffer looks like the following int packet 3 packet 0 pkDownloadRequest packet 1 0 packet 2 0 This is a 4 word 32 bit words buffer pkDownloadRequest 0xA0 2 Wait for an ACK command from Target The ACK command is a 3 word buffer buf 0 pkDownloadRequestAck buf 1 Size in bytes expected buf 2 byte count received from host Sbc6713e User s Manual 71 3 Host will parse the CoffFile and send it in chunks of 16384 words for each packet it expects an ACK command from the Target Each Host to Target transmission is composed of a header packet and a data packet Header Packet looks as following Header 0 pkSectionHeader Header 1 PacketAddr Header 2 PacketSize The Data Packet contains the opcodes being downloaded to target Please read CoffFile Mb cpp to understand how the data file is parsed When EOF
47. Loader program resurrects the COFF image into DSP memory and launches it The PromImage exe applet supports conversion of COFF executable images into proprietary Innovative Loader format This data format has been developed to circumvent a boot limitations in the TI C6000 family which is incapable of booting COFF images directly This applet automatically accommodates the endianness of the COFF image Optionally the bss section of the generated image may be cleared This increases the image size but is generally required in order to mimic the load time behavior of Code Composer Studio in which the application was likely debugged In addition to binary images the applet also supports generation of images translated into C compatible source code containing initialized data arrays This is useful in applications which dynamically reconfigure logic from within target application code Prom Image Creator File Help Settings cb ata amp cquisitionNodeE xampless amp naloglnD ebug 4nalogln out Coff File Clear Bss F Header File Generation Data Type I Epa Es char C short int lol x Make 27226 symbols String table size 292378 54 sections unswapped format little E data No reloc Loading hwi vec addr O 00000000 size 0200 Loading switch addr O 00001810 size 0x0108 Loading stack gt addr 000001918 size 0 2000 Loading lt bios
48. MB 255 Non paged pool size MB 4 Status Ok Update Help Exit Ready 22 To reserve this memory the registry must be updated using the ReserveMemDsp applet If at any time you change the number of or rearrange the baseboards in your system then you must invoke this applet to reserve the proper space for the busmaster region See the Help file ReserveMemDsp hlp for operational details Data Analysis Applets Binary File Viewer Utility Bin View exe BinView is a data display tool specifically designed to allow simplified viewing of binary data stored in data files or a resident in shared DSP memory Please see the on line BinView help file in your Binview installation directory Sbc6713e User s Manual d BinView c vista vistat 1 dump bin Dl x IC marr FTBOG Q Time Frequency Text Summary Server lt Zoom Out Zoomin gt gt gt ae Amplitude vs Offset 20 cho Counts e9 e e D 10 20 30 40 50 60 70 80 2390 100 Offset Span 100 Analyze ChO 7 Samples 4096 23 Target Programming Applets Target Project Copy Utility CopyCcsProject exe The CopyCcsProject exe applet is used to copy all project settings from a known good template project into a new DSP Code Composer project This simplifies new project development by eliminating the multi step process of copying the myriad individual project settings from a source project i
49. Makefile Export to Makefile Add Files to Project Save Close Source Control Compile File Build Rebuild All Stop Build Show Dependencies Scan All Dependencies Configurations Build Op File Specific Options Function Level Options Recent Project Files g q fr C Wista Examples T est D ebug d DEBUG mv6710 Build Options for Test pjt Ax General Compiler Linker Link Order Basic Target Version Generate Debug Info Full Symbolic Debug 3 gt Opt Speed vs Size Speed Most Critical no ms Opt Level None E Program Level Opt None y Build Options for AnalogCapture pjt BE General Compiler Linker Link Order Link order x t Add to link order list Files without link order AnalogCapture CDB AnalogCapturecfg cmd AnalogCapturectg s62 AnalogCapturecfg c c AnalogCaptureT est cpp ee o Code Composer Studio Debug Profiler GEL Option Tools PBC DSP BIOS Wir Sas ee los Ca gall 1 r Debua y Boxes Sbc6713e User s Manual Click the menu Project Build Options to invoke the compiler Build Options dialog Then select the Files Category then enter the pathspec to the Examples opt file in the Examples directory to the Options File edit box Click on the Link Order tab then add Examples cmd to the Link Order List Click the Incremental Build button to rebuild the template app
50. analog IO and other peripherals make the SBC6713e well suited for a variety of application such as communications baseband processing ultrasound applications multi axis controllers for high speed servos RADAR SONAR applications communications signal processing and many data acquisition applications The baseboard has a variety of features that make it easy to develop high performance systems On card very low noise power supplies provide clean power for analog peripherals installed into either Omnibus I O site Other features include 32 bits of programmable digital IO advanced clocking mechanisms multi card triggering and clock sharing plus a flexible timebase for data sampling and timer counters The SBC6713e features a close to 100 Mb s Ethernet bus interface for high data bandwidth to the host PC system Digital Signal Processor The SBC6713e baseboard uses the TMS320C6713 DSP operating at 300 MHz This DSP is a 32 bit floating point device The DSP interfaces to the memory and peripherals on the baseboard through its external memory interface EMIF which has programmable definitions for the memory interface timing DSP External Memory The SBC6713 baseboard provides 32 Mbytes of SDRAM memory mapped to the 6713 DSP CE0 memory space This memory provides space for program and data storage as well as storage space for data acquired generated by the baseboard analog hardware This memory is programmed to operate at 75 MHz regardless of
51. below ICON core signal declarations signal control0 std logic vector 35 downto 0 ILA core component declaration component ila port control in std logic vector 35 downto 0 clk in std_logic data in std logic vector 55 downto 0 trig0 o4dn std logic vector 2 downto 0 end component ILA core signal declarations signal control std logic vector 35 downto 0 signal clk std logic signal data std logic vector 55 downto 0 signal trigO std logic vector 2 downto 0 Figure 48 Chip Scope Core Declarations Here is its instantiation during a debug session i icon icon port map controlO gt control0 Sbc6713e User s Manual 168 port map control gt control clk gt clk data gt data trig0 gt trig0 trig0 0 lt cel n q trig0 1 fpdp rx fifo rd trigOd 1 lt wdt Wr trig0 2 lt ce2 n clk lt e clk data 0 lt fpdp tx config 0 data 2 downto 1 fpdp tx config 2 downto 1 data 3 not fpdp tx fifo int data 4 not fpdp rx fifo int data 5 lt fpdp wrfifo control wr data 6 lt fpdp rdfifo control wr data 7 lt dsp data oe n 0 data 8 lt fpdp rx fifo rd data 12 downto 9 dsp int s data 13 not fpdp tx config 0 fpdp reset data 14 fpdp tx fifo wr data 46 downto 15 fpdp rx do data 55 downto 47 fpdp rfifo count data 27 downto 15 lt others gt
52. box Create New Platform Sbc6713e User s Manual 82 I o Estimated Data Size 2765 Est Min Stack 5 3 system umentation Scheduling B Synchronization m Input Output E CSL Chip Support Library ista CPU_1 C6711 Code Composer Stud File Edit View Project Debug Profiler GEL C Sel Test pit 7 Debug Files GEL Files G U6x gel B Projects E Testa DS Ge Inc Lib C3 se Add Files Scan All Dependencies Build Clean Export Makefile Set as Active Project Open For Editing Save Close Configurations Options v Allow Docking Hide Float In Main Window Add Files to Project Look in Test J e amp e E3 Test tcf Configuration File tcf Ln 8 21x Look in S Test z e Oc Debug Fiename fescioomd Fies of type Linker Command File cmd Coca Sbc6713e User s Manual By default this TCF will be named Configurationl Save it as Test TCF Though the TCF and its support files have been created on disk you must manually add them to the Test project Right click on Test pjt in the Project window to invoke the project hot menu Click Add Files to add a file to the project Select the the newly created Test tcf for addition to the project This will implicitly add the auto generated files Testcfg s62 Testcfg s64 for Velocia cards and Testcfg_c c to the project as well Right click on Test pjt i
53. character level data traffic between the Host and the Target DSP Alternately the RtdxTerminal implementation uses the JTAG RTDX bus to accomplish this task Only one of these implementations is provided for each DSP board Check the Program Files Innovative subdirectory to determine which of these tools is provided with your Dev Kit package Target Software All of the features of the terminal emulator are accessed through the two classes Termlo and TermFile Termlo provides the basic streaming interface which allows text messages to be formatted and streamed out to the terminal emulator as well streaming in strings and numeric values from the terminal emulator for consumption by target application code The TermFile class provides a mechanism allowing target applications to open host disk files perform read and write accesses and subsequently close these files See the Files cpp example for illustrative usage of each of these classes and their functions Tutorial Using the terminal emulator during target software development is simple The first step is to instantiate a Termlo object through which all terminal I O will be performed This occurs implicitly within the cio object as a create on first use behavior Use the methods within the Termlo class to format text strings and then stream them to the the terminal emulator applet cio bold 7Demonstrate file I Onn normal endl Note the use of manipulators such as bold a
54. data file Browse 1 Co Browse Diagnostic Arguments o Next gt Cancel Hit next or move to the next tab Sbc6713e User s Manual 28 This address should match up with the address in the SdConfig exe utility Connection Name amp Data File Connection Properties Property Value USB Emulator address is 0x510 y Change property value as necessary in the right column tees Now we add a processor Each if the II boards have different processors so match up the closest one for your board Available Processor Typ Driver Location fh IMS320F2400 CACCStudiotdriverstsdgo24xusb dvr f Mis320F2800 CACCStudioViriverstsdgo28xusb dvr MA misa20c5400 CACCStudioWriversisdgoS4xusb dvr A Tws320c5500 CACCStudioldrivers sdgoSSxxush dvr TMS320C5400 CACCStudio Wdriverstsdgob400ush_11 dvr f TMS820C8200 CAGCStudiotdriverstsdgoBxushb dvr f TMS320C8700 CACCStudiowrivers sdgo6xusb dvr f TMES20C5210 CACCStudioWdriversisdgoBxusb dyr CACCStudiolWriversisdgabxusbdyr f TMS320C6720 CACCStudioViriversTsdgo87 2x USB dvr War 1 CACCStudloViriversYsdgoarm11usb dvr MARI CACCStudiotdriversisdaoarm usb dvr A ARMS C CCStudio driverstsdgoarmSush dvr See nemen caso Drag a device to the left to add to the currently selected board Use the property sheet to find the Gel file from Innovative for your specific board Sbc6713e User s Manual TW Factory Boards Pi Custom Boards fb Create Bosra
55. eclk in event and eclk in 1 end if XXX while ardy 0 or ardy L and ce0_n 0 loop wait until eclk in event and eclk in 1 end loop wait until eclk in event and eclk in 1 are n lt S17 awe n lt 1 wait until eclk in event and eclk in 1 aoe n lt 1 after 2 ns ce0 n lt 1 cel n 1 ceo lt Ty ce3 n lt 1 ea lt others gt H after 2 ns ed lt others gt H after 2 ns gap end async_access Figure 29 VHDL Procedure for Simulating a DSP Async Access module 0 tests print print MODULE 0 TEST write module 0 iomodl in async mode async access 3 0 X 010000 X 12345678 read module 0 iomodl in async mode async access 3 1 X 010000 X 00000000 write module 0 iomodl in async mode async access 3 0 X 010000 X 87654321 read module 0 iomodl in async mode async access 3 1 X 010000 X 00000000 write module 0 iomodl in async mode async access 3 0 X 010000 X 09876543 read module 0 iomodl in async mode async access 3 1 X 010000 X 00000000 write module 0 iomodl in async mode async access 3 0 X 010000 X 345678AB read module 0 iomodl in async mode async access 3 1 X 010000 X 00000000 Figure 30 VHDL Testbench Code For Omnibus Sbc6713e User s Manual 163 Omnibus Interface Omnibus is an open standard that allows customers to
56. eene nnne nenne nennen enne nnne 51 Table 10 Stream object Retrigger Methods esses enne eerie enne 51 Table 11 Interrupt Lock Classes nien ae HR ERN E ERIT EUIS REEL GE iene Ree Ue Eg S 54 Table 12 SBC6713e Example Programs eet a Pe E eU e HRS 61 Table 13 Pismo Example Programs aseo e acid 90 Table 14 I O Standard LVTTL um iib hire o i Dr c et d tede tena 53 Table 15 Common Problems when Embedding Code in Flash ROM essere 178 Table 16 OMNIBUS Bus Connectors tiep petet ena eL ER tig Deae vata yeah cop dade tenta ae en eC BR E SNR et rele 189 Table 17 O Module Bus Connectors aienea e nne iaaa i e trennen s enne 190 Table 18 Digital 1O Connector A RE REN MU n ees 191 Table 19 SyncLink Connector nennen nnne i a e RR enne eterne nnne ener entretien 196 Table 20 Processor Serial Port Connector ea eeeeieeee S ether then enne tette tst teens a 197 Table 21 JTAG Debugger Connector nennen nenne nente ESENES SES nnne nn rra nennen enne nnne 198 Table 22 Power Input Connector esessessssesseseeseeeeeneene neret nnne tnit innert trennen etre enne nne ner enne ennt nennen 199 Table 23 Asynchronous Serial Port Connectors inesse enne enne nne nnne E E nennen rennen 200 Table 24 Xilinx JTAG Connector for XC2S600E FG456 sse nne tenen e nnns 201 Table 25 Xilinx JTAG Connector for XC2S50E TQ144 isses nennen rennen trennen trenes
57. f filespec Use the f switch to force the terminal emulator to load and run the specified COFF file The filespec field should be a standard Windows file specification including both the path and file name as a unit to allow the user to force the terminal emulator to download the specified file to the target DSP board as soon as the terminal emulator is loaded This field is particularly useful in situations where the the terminal emulator is shelled to from within an other Host applications to facilitate the automatic execution of target applications employing standard I O Applets for SBC6713e Baseboard lol Board Finder Utility Sbc6713eFinder exe Opin In the factory default configuration the Innovative Sees Integration Sbc6713e DSP board obtains an IP address from 1921680100 gg 1921690109 Eng the DHCP server on your network Consequently it is EBSEHEFGUPE necessary to scan the network to discover the IP address of P Address each newly added board This utility serves that purpose 192 168 0 102 sbcB713 118 innovative dsp com Enter the Start and End addresses for the internal network to which the SBC6713e is attached Insure that the SBC6713e is powered and that the network activity indicator on the board is flashing indicating network activity Then click the Scan button to snoop the network All boards discovered during the scan will be listed in the Scan Found Boards
58. handlers The user then never needs to work in the CDB editor to provide handlers The standard Pismo handlers contain code that will call a user s installed interrupt handler function if one is provided While this adds a small amount of latency to the interrupt the DSP BIOS overhead per interrupt call is still much greater and dominates the total time per interrupt In general the BIOS environment is not suited for extremely high interrupt rates Luckily the use of DMA to acquire data from FIFOs on peripherals means that high rate interrupt handlers are not needed Pismo uses a special object a Binder to group a handler function and its arguments in a way that can be properly called by the standard handler One form of Binder is used to attach a stand alone function and its arguments another form allows the binding of an Object a member function of that object and its arguments This form of binder can allow a class object instance variable to act as a handler for interrupts Here is an example from the Messages example of defining a binder for a timer interrupt Timer Interrupt Handler Function void OnTimerFired int arg Binder Object for Timer typedef void IntFtnType int arg FunctionHandler IntFtnType int TimerBinder OnTimerFired 0 And attaching the binder to an interrupt Set up a real time clock to send commands to host on Target channel Irq Timer0 intTimerO Timer0 Install TimerBind
59. in a registered data source ASYNC DATA that is fed to the final data mux In the Framework Logic code the async data mux is as shown process async data mux status reg nmi status int4 status dio q uart int reg uart d fpdp tx bitio in mod din timer2 rd timerl rd timer0 rd begin case async data mux is when 00000000000000 gt async data mod din when 11000000000000 gt async data status reg when 10100000000000 gt async data nmi status when 10010000000000 gt async data int4 status when 10001000000000 gt async data dio q when 10000100000000 gt async data uart int reg when 10000010000000 gt async data uart d when 10000001000000 gt async data fpdp tx bitio in when 10000000100000 gt async data fpdp rx frame count when 10000000010000 gt async data lt X 0000000 amp 00 amp fpdp tx pio when 10000000001000 gt async data lt X 0000000 amp 00 amp fpdp rx pio when 10000000000001 gt async data lt X 00 amp timer cnt0 q when 10000000000010 gt async data X 00 amp timer cntl q when 10000000000100 gt async data X 00 amp timer cnt2 q when others gt Sbc6713e User s Manual 48 async_data lt mod_din end case end process The final data mux picking between the FPDP Rx FIFO data or the asyc data is process reset e clk ce2_n ea begin i
60. less to prevent damage to the Spartan IIE from overvoltage or electrostatic damage Input signals above 5V will be clamped to 5V and can sink 1A of current for short periods Do not use this as a signal limiting mechanism however since 1t is meant for protection only Clock Domains Judicious choice of clock domain boundaries and careful handling of any transition across the clock boundaries is crucial to a reliable design Past experience has shown that more problems occur on this topic than any other In the SBC6713e design the EMIF clock is 75Mhz fixed rate EMIF clock goes through DLL which provide zero propagation delay low clock skew between output clock signals distributed throughout the device and advanced clock domain control These dedicated DLLs can be used to implement several circuits which improve and simplify system level design Sbc6713e User s Manual 51 CLKDLL CLKO CLK9O CLK180 CLK270 CLK2X CLKDV LOCKED DS001_25 032300 Figure 25 BUFGDLL Schematic Courtesy of Xilinx Constraints There are several important classes of constraints used by the Framework Logic timing pin placement and IO standards These constraints are shown in the ucf user constraint file that is used during the fitting process Timing Constraints The timing constraints defined cover the clocks used in the design and the external device signal timing Clock period period constraints are used to cover most of the logic sin
61. located in the root directory of the Zuma Toolset This small pre written executable provides all of the Flash I O access functions necessary to allow the BURN utility to interact with the target Flash ROM The Talker page contains a number of window controls used to specify the mechanism to use to deliver the FLASHER OUT support executable into the target DSP Two methods are currently supported JTAG and downloading via the existing Talker in Flash ROM Sbc6713e User s Manual 173 Burn olx File Help Target Talker Flash Info gt Download Method C JTAG ec app ese Debuager J Autorun Script C SBC32 Flasher gel Senph ele Flash ROM C ASBC32 Flasher out Coff File Run Target Open OK You must use the JTAG download method whenever the target DSP Flash ROM does not contain a viable bootable image of the Talker program In the default factory condition the target contains a bootable Talker which is used by application programs through the DLL and device driver to download executable programs to the target DSP If this Talker image has been erased or corrupted you must use the JTAG download method If the Talker is still viable in Flash then you may use either of the download method The Talker method is the preferred method especially in circumstances where a JTAG debugger is unavailable such as when performing in the field software updates JTAG Download To download using JT AG
62. monitor with a logic analyzer Built in Test Modes Another good way to debug your design is to have built in test modes in the logic If you plan ahead for test then you can more quickly validate your design later and spot problems When you finish the design if the test generators and checkers can be left in the design they are there later as production debug or test In many designs test pattern or data generators are invaluable since they provide known data into the FPGA so that the output is known If the data source is analog in the real design substituting perfect data is nice because it helps spot Sbc6713e User s Manual 165 problems that may be hidden in the noise The test pattern may be an easily recognized stream like incrementing numbers that are easy to check in the logic or on the test equipment Also its easier to test the extreme cases of the design that may be difficult to reproduce with real signals Also data checkers in the logic sprinkled through the data chain help to spot the source of problems If you have a missing timing constraint or a clock domain issue these can be hard to catch since they may be rare A data checker gives you a way to look for bad data and then trigger ChipScope or the logic analyzer In many cases rare errors are impossible to catch without this sort of data checker This technique has save a lot of time for big designs Xilinx ChipScope Xilinx offers an excellent tool for debugg
63. nee eee sd Re ear dee e alates 168 Figure 38 PROM Confundido 161 Figure 39 Select Auto Select PRO Mv emerit a Ro eR ER Ree ee i E OR HER 162 Fig re 40 Select the BIT files get Tt RR RH AC ae nee DE ETUR eee 163 Figure 41 PROM Fil Genera di erede eie a eet e RC ERROR Re See 164 Figure 42 Flash Image Burner ee a tpe ee a RE Gp HR rd 165 Figure 43 Chip Scope Big Piola 166 Figure 44 Xilinx Parallel Cable IV Top View Courtesy of Xilinx sss 167 Figure 45 High Performance Ribbon Cable Courtesy Of Xilinx sss 167 Figure 46 Xilinx Cable Interface Connector Courtesy Of Xilinx sess 167 Figure 47 SBC6713e JP25 Spartan IIe 300K 600K JTAG Connector eese enne 167 Sbc6713e User s Manual Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Chip Scope Core Declarations A oi 168 Chip Scope Core Instantiation and User eeneiige AE E EEE E EEG T 169 Chip Scope Analyzet Screen ShOt eter Paces O ER R ED RR eI RA Ea 169 FPDP JHI TX Port Bono M 193 FPDP JHZ RX Port enum M 195 JP2 SyncLink Connector Pin Orientation enne enne nere enne nnne 196 JP13 JP15 DSP SerialPort ConnectOr noe ine RIO RO PI 197 JP23 JTAG Debugger Connector isi etes eae iras 198 Power Connector Pin Positions side view from front of connector showing connector keying and locking tab along with
64. of Target Code cpp tcf cmd pjt In general DSP applications written in TI C require at least three files a cpp file or source file containing the C source code for the application a cmd file or command file which contains the target specific memory map and build data needed by the linker a tcf file or command database file which specifies the properties of the BIOS operating system used within the application and a pjt file project file which centralizes all project specific options settings and files There may also be one or more asm assembler source files if the user has coded any portions of the application in assembly language Sbc6713e User s Manual 86 Edit Compile Test Cycle using Code Composer Studio Nearly every computer programming effort can be broken down into a three step cycle commonly known as the edit compile test cycle Each iteration of the cycle involves editing the source either to create the original code or modify existing code followed by compiling which compiles the source and creates or builds the executable object file and finally downloading and testing the result to see if it functions in the desired fashion In the Innovative Integration development system these stages are accomplished within the Code Composer integrated development environment IDE By using Code Composer Studio these stages of the programming cycle are accomplished entirely within the ID
65. or 0 to result in a debounced output of that value Once a debounced switch is sensed any change in the switch value from its previous state results in a serial word being sent to the DSP McBSP serial port that reports all switch values currently and some status This transmission is ONLY done ifa change is sensed o ie TUS YT O OS down is depressed 1 up is depressed 1 select is depressed IT EN Note that it is possible for multiple switches to be simultaneously The McBSP receive port should be configured as Frame sync input active low 8 bits wide frames the data byte Data 8 bit clocked on falling edges of the clock MSB received first Clock input falling edges used for frame and data This timing diagram shows the serial data transmission from the logic to the DSP with the UP button true Sbc6713e User s Manual 181 Display Interface The display controller Solomon SSD0323 has a synchronous serial data interface that is adapted to use with the TI DSP serial port McBSP The McBSP transmit port is used as both an adapter and display command and control The McBSP should be configured to transmit a 16 bit word with a frame active during the data transmission The McBSP should continuously source the serial clock at 3 33 MHz maximum The frame is sent by the McBSP and is active low The adapter receives the data and parses the data word If the data is addres
66. ping Sbc6713 C105 innovative dsp com The DOS prompt will display the IP address of the card between square brackets Below is a screen shot of Network Settings tab Network Settings Dwid Loader Dwld Client Dwld LAN Logic Dwld INTF Logic Dwld Application IP Info Use dynamic IP DHCP Settings 192 168 0 68 IP address 255 255 255 0 Subnet mask 192 168 0 1 Gateway IP address 0 0 0 0 DNS Server IP address innovative dsp com Domain Name Update IP settings to ROM Download Loader tab This is a tab that is not usually used unless instructed by Innovative Integration s release notes or Tech Support This tab will update the loader program which launches the DM642 client application during cold start initialization If an inappropriate binary file is loaded using this tab window your card will have to be returned for repair Burning an incorrect Loader program will cause the card not to boot up and not to be accessible via Code Composer Please read carefully the label of each button you may press all of them are labeled differently to avoid this type of errors Below is a screen shot of this tab Network Settings Dwld Loader Dwld Client Dwld LAN Logic Dwid INTF Logic Dwld Application WARNING Downloading a faulty loader will cause system boot problems C lnnovative SBC671 3 Coprocessor Examples Loader LOADER bin Download Loader Sbc6713e User s Manual
67. pr ER 52 Interrupts in a C Environment ennnen e a r dd eroe ig 52 The Pismo Solution 2 inar ertt ote n o Re n dad 53 GFrrEl aE 54 Interr pt Lock Classes coccion the RI eer e HOP RD ERE EE RI N E GER REST 54 Interrupt Binder Templates etes tete ee e IR cal cu UT Ee Le ER RE ERES eee dogs 54 Class InterruptHandler 5 2 trier e ce ECT ERE RR OREL ERE EREMO PERDE 54 Class ClassMemberHandler Template sess enne ener enne nnn nnne 54 Class FunctionHandler Template coincida 55 EDMA and QDMA Handling sessi eene nennen SES ennt rne ner etre nen enn ener nri enne nennen 56 Class Dmasettihgs enne pre Pee REUS ee cir ERE pete D hei ee E phe E qs tu MEE 56 ClassOdmas diem erede E tute E E SEERA EN 56 AAA E O NA 58 Linked and Chained bDIOCKS cies eseeseesesseeseeseeceecuccscesecneesecsecsecsessessesseesesscseeceseeseseeceeesecaecaeesessesaeesseecaeenatenaes 60 Class EdinaMaStets emu O 60 SBC6713e Example Programs roeas erae aan nenne RR RR RR R RON RAN E RR R nter nennen nere nente enne 61 The Next Step Developing Custom Code cccccccccescssessessseeseesseeseesseesecceesecaeeseensecsecesecseeesecesenseseneeseceaeeaeenaeeseeaeeneeeaeensaes 62 Communication with the Host eii ec erro ia OO aul LC seas 63 Packetized Message InterfaGe A tc
68. printed circuit board position eene nnne nnne n enne nennen rennen 199 Figure 57 Sbc6713e User s Manual Mechanical Drawing Board Revision C essen 204 10 Introduction Real Time Solutions Thank you for choosing Innovative Integration we appreciate your business Since 1988 Innovative Integration has grown to become one of the world s leading suppliers of DSP and data acquisition solutions Innovative offers a product portfolio unrivaled in its depth and its range of performance and I O capabilities Whether you are seeking a simple DSP development platform or a complex multiprocessor multichannel data acquisition system Innovative Integration has the solution To enhance your productivity our hardware products are supported by comprehensive software libraries and device drivers providing optimal performance and maximum portability Innovative Integration s products employ the latest digital signal processor technology thereby providing you the competitive edge so critical in today s global markets Using our powerful data acquisition and DSP products allows you to incorporate leading edge technology into your system without the risk normally associated with advanced product development Your efforts are channeled into the area you know best your application Vocabulary What is the SBC6713e The SBC6713e is Innovative Integration s stand alone baseboard architecture that integrates modul
69. run using the terminal emulator applet which may be invoked using the terminal emulator shortcut located within the target board program group created during the Pismo Libraries installation process In the terminal emulator download the test out file The program runs and outputs the message Hello World to the terminal emulator window If errors are encountered in the process Code Composer Studio detects them and places them in the build output window If the error occurred in the compiler or assembler such as a C syntax error the cursor may be moved to the offending line by simply double clicking on the error line within the build output window and the error message will be displayed in the Code Composer Studio status bar If the linker returns a build error the build output window shows the error file From this information the linker failure can be determined and corrected For example if a function name in a call is misspelled the linker will fail to resolve the reference during link time and will error out This error will be displayed on the screen in the build output window Note Be sure to start the terminal emulator BEFORE starting Code Composer to avoid resetting the DSP target in the midst of the debugging session If the terminal emulator is not yet running and you wish to run the Test object file perform the following steps Execute Debug Run Free to logically disconnect the DSP from the debugger software 2 Te
70. source may support none or one or any number of all the possible UI interface classes An interface can be accessed by the conversion function for each of the UI interface classes If an interface is not supported the conversion function returns a null pointer The following code sample shows the use of conversion functions and multiple interface classes The DDS clock source is in use It supports both the ClockRateUI interface which allows changing the clock frequency and the ClockSyncUI interface which allows configuration of the SyncLink ClockLink master hardware to drive the DDS clock signal off the baseboard for use as a source on another board Set Clock Rate allowed on DDS ClockRateUIPtr Aln Clock gt Rate 50000 ClcokSyncUIPtr Aln Clock gt SyncLinkChannel scSyncLink0 Each line can be read from the inside out AIn Clock returns the current clock UI object This object is input into the clock conversion function ClockRateUIPtr and converted into the ClockRateUI interface Finally the Rate method of this class is called to set the rate of the clock to 50 000 Hz Selecting and Configuring Triggers The Analog Stream objects allow the user to configure the triggering method used during the run Triggering features are divided into four parts e Pretriggering Handling data before the start trigger e Start Trigger How to start data taking e Stop Trigger How to stop data taking e Retriggering How to h
71. tee d laeti Laser i Abe eade Re Se i eara DERE US 23 Binary File Viewer Utility BinView exe eese nennen enne nnne nennen entente nnne ener enn enne nennen 23 Target Programming Applets ccccecsscesseesseeseesceeseeseeesecsceesecsceesececeesecsessesesecseeesecsaeeaecsaeeaecesecaesesesaeeaeceeeseseeeeeseteeeenaes 24 Target Project Copy Utility CopyCcsProject cxe cccescccscssssesesseeeseeseeeseeeeeeeesecnsecseeesececeseceeeeseceeesseseeeeseeeseeeeeseeneeeeed 24 Demangle Utility Demangle exe eesessseseseeseeeeeeeeneen enne enne nnne enne nnne eerte nr rennen 24 COFF Section Dump Utility CoffDump exe sssessssssseseeseeeeeneen enne nennen nn ron nnne enne n nennen nnne 24 JTAG Diagnostic Utility JtagDiag eXx ooooooncninnnonnoonconnonncononnncnnonnncnnonn rn nennen ennt E nn Ea E AREE nen 25 RtdxTerminal Terminal Emulator eese eee netnennennetnetne nee nnenne teen narran narnia 25 Important Note ettet ro Eee egi e eme re batteries ere eet A eie diia 25 Terminal Emulator Men Commands ioco a eie eee ipo 25 Phe TEE REX e EM 26 The DSB MEM it hee e o edem le Pedo gua petu E Ene te ER DE eee ete ee eee 26 The Ford M nu J eoe ote eee ee ento ae rH e A nal ae eR echas teer eei 27 The Help Menu decet eoe eiie e Pee E bets E a eon OO 27 Options Tab aeo Ian ta e iM pede Tta ce EE Gi E AN ER dc ede 27 Sbc6713e User s Manual IECIT
72. the Please wait message is not displayed the DM642 coprocessor would have finished downloading the Client It takes more to program the Client than the Loader You may see a message displaying Bad burn checksum since your Talker program is not the latest this message can be ignored At this point is a good time to close either FlashBurn exe applet or CCS r and do a hardware reset on the Sbc6713e card Once you have done this Continue with step 3 3 Changes to Flash Information Section The Flash Information Section is a place in flash memory that contains information about the PCB version of the Sbc6713e card plus information regarding the IP internet protocol settings of the card A new field has been added to this section hence the need of running this program 1 On rdtx terminal program icon right click and select properties Inside the Target box at the end of the line please type cpu CPU 2 That line will attach rtdx terminal to CPU 2 We assume that you have name this way in CCS r Setup CPU 1 C6713 CPU 2 DM642 Sbc6713e User s Manual 39 2 3 Do Debug Reset CPU Do GELMI Function Initialize Target Execute Load and run C Innovative Sbc67 13e Coprocessor FlashLoad FlashLoad out When the program prompts for revision please type the revision of the card 1 e B or C Once finished close CCS r and rtds terminal program and reboot the Sbc6713e card If you chose DHCP you may fi
73. the DSP core clock rate The initialization of all external memory spaces are defined within the file HdwLibNIIInit cpp and include the correct parameters for the type of SDRAM used on the baseboard including refresh timing as well as timings for all syne and async peripherals and should not be modified Sbc6713e User s Manual 41 DSP Initialization For proper operation of the external peripheral on the baseboard the external memory interface control registers must be configured prior to use of the external memory interface Applications built under the Pismo Toolset libraries will automatically initialize the registers appropriately using code within HdwLib IIInit cpp For those customers who need to initialize the registers manually please refer to the EMIF register initialization values within the IIInit cpp source file to obtain the required register values If different the specific values in IIInit cpp supercede those listed in the table below Please note that the initialization is order sensitive and should be performed in the order given in the table below Table 4 C6713 DSP EMIF Control Register Initialization Values osre oerooo www somm ooroo wm Ispxr oxorsooo20 wosdr pcr oemwos fosso During the development process code may be downloaded to the SBC using a JTAG debugger or via the Ethernet interface After development is complete the debugged application image may be pla
74. the calls to Generate and Put Generate uses signal generator classes to write a signal pattern into the buffer Put enqueues the data for output Data output will not actually begin until the buffer queue is essentially filled with data This avoids under runs of the output For input Streams the Get method starts streaming at the first call These buffer methods should be repeated to keep the streams flowing After use of a device is complete it is closed using the Stream Close method Note that in the above example the type of module used matters very little in the finished application Simply by changing a single constant this code can be rebuilt to work on any module that supports Analog output The module specific details are handled by the Pismo library internally Selecting the Stream Object Each Stream object is used to manage input or output on a single Omnibus module Multiple module applications need to use separate instances of the stream for each module site The Stream object is associated with a module site by the constructor allowing access to the hardware for configuration AnalogInStream AIn Omnibus mSite0 The AnalogInStream provides continuous streaming input All data is delivered to the ring of internal buffers and from there to the application AnalogOutStream allows continuous streaming output to an output device The application must deliver data as fast as it is consumed to avoid buffer underruns S
75. to be installed You may type a path or click Change to browse for or create a directory If left unchanged the install will use the default location of C Mnnovative 3 Typically most users will perform a Full Install by leaving all items in the Components to Install box checked If you do not wish to install a particular item simply uncheck it The Installer will alert you and automatically uncheck any item that requires a development environment that is not detected on your system 4 Click the Install button to begin the installation Note The default Product Filter setting for the installer interface is Current Only as indicated by the combo box located at the top right of the screen If the install that you require does not appear in the Product Selection Box 1 Change the Product Filter to Current plus Legacy Sbc6713e User s Manual 17 Each item of the checklist in the screen shown above has a sub install associated with it and will open a sub install screen if checked For example the first sub install for Quadia Applets Examples Docs and Pismo libraries is shown below The installation will display a progress window similar to the one shown below for each item checked Quadia Documentation Thank you for choosing Quadia Installing Documentation Figure 3 Progress is shown for each section Sbc6713e User s Manual 18 Tools Registration
76. to do movement to and from hardware to memory so that hardware interrupt rates rarely exceed 1 KHz The net effect is that virtually all of the bandwidth of the CPU is available for application processing without requiring any application DMA programming Multitasking Friendly The Stream classes support efficient cooperation in multitasking applications Any function that requires a delay to complete will block using DSP BIOS functions that release other OS threads for efficient utilization of the processor Using Analog Streams in an Application The AnalogInStream AnalogOutStream and CaptureInStream all allow fast data movement between the application and the hardware in different modes Once associated with a hardware device they allow all configuration and control of the session to take place through the methods of the Stream Every Stream must consider these questions to make a functioning application e Which stream to use Input vs Output or Continuous vs Burst e Which hardware to use and in which hardware mode e Which clock source to use and with what parameters e Which triggering mode to use and with what parameters Once these are taken care of using the Stream to perform the Analog I O is a simple matter Consider the code fragment below which illustrates all of the steps necessary to fully initialize and stream a stream a continuous 1 kHz sine wave to the analog outputs present on a SD16 Omnibus module attached to an
77. trennen innen nnne ener innere enne 176 InfoPages R ened 176 Example Burn Sequence cceccesccesceseeeseeseeeseesecenecseeeseesceesecseceseceeessesececsesesecsesesecsceseceeeeseceeeeaeceseseeeseseeneeeeseneeesseeenes 177 b seboatd32 7 ote eta t need EE E ose o Det TE 178 baseboard6xz RT 178 Daseboardo Tli PET 178 Common Problems when Embedding Code essere nnne enne nnns 178 OLED Display AAA Mesi D scriptiOto coU T IND SR INO I ICI RU d ENSE nSenNu 180 Buiton Interface e 181 Display Int rface TEN A ada D EO 182 Serial nU aia A E E a 182 Data Command PaM ienei URN EE O TER GN ERE tea EOE erence E 183 Required steps tU dc 184 A AE E E E EE EE E E Connector pinouts atico 185 JP4 JP8 OMNIBUS I O Connectors cccceeccccceessccessscccesscecceseecessseccesscecescecesssecessseeceseecesssecesseccesseeeesescessssseeeeees 185 JP5 OMNIBUS VO Connectors ii eerta e t teen e dpa im t tede es 185 JP6 7 9 10 OMNIBUNS BusS ConnectOtS rr reet ettet re i Ert re ree I EE ee eyes 189 JP Digitali I OxsConnector iu ee retener taped eiie ee eee ide e RECO NO ED et Le EO eds 191 JH1 EPDP Transmit Port Connector tete t ue DEUS EE E Ee S YER 192 JH2 FPDP Receive Port Connectot erede E EE is 194 JP2 SyncLank ClIkEink uni tete ia eet rd vt Ye 196 JP13 JP15 Processor Serial Port Connec
78. up for the environment is included in the npl file Constraints for the example logic are sbc6713 top ucf and should be applied to the sbc6713 intf vhd file which is the top of the design The constraints have the pin assignments I O standards and some basic timing constraints for the framework Compilation is usually easy and users who are familiar with Xilinx ISE can start by verifying that the provided design recompiles Just click on the synthesis then Implement then generate program ming file buttons to get through the design process Watch out for the warnings such as timing constraints violation as these may really mean that your design would not work at speed These are viewed in the report files The tool issues many warnings along the way these can be ignored for the sample logic Sbc6713e User s Manual 40 Note If you are unfamiliar with Xilinx ISE see the Xilinx tutorial on using it accessed from the help button on the top of the application Once you have successfully complied and installed the software your development can begin by editing out code you don t need and deleting the associated constraints You will have to keep the constraints associated with pin all assignments whether or not you use that function as pins are fixed by the board design Here is a summary of the steps to follow Steps to follow to logic Builds 1 2 Install Xilinx ISE 6 0 or above Unzip the Framework Logic into a suitable direc
79. wish to use from the host disk and program the Flash AM29LV320DT Reset the card in order to load the current logic in Spartan Ile Below is the picture of FlashBurn utility Sbc6713e User s Manual 164 1 Flash Image Burner Baseboard UID 192 168 0 128 Connected PTET TTT TTT TT TTT TT Cient fiare version INTF firmware version LAN firmware version Flash Image Burner v1 1 Dwid Loader Dwld Client Dwld LAN Logic Dwid INTF Logic Dwld Application C Projects SBCB 1 341 am Download INTF Logic Figure 42 Flash Image Burner In order to burn logic the user needs to have an IP address dedicated to SBC6713e As the user click on download internally DM642 moves the data from SDRAM to the Flash to its specified sector Then after user needs to provide a board reset to load the current logic into FPGA Spartan He For further information about FlashBurn utility and its libraries please refer to Pismo Toolset Debugging Custom Logic It is inevitable that the logic will require some debugging and it is best to have a strategy for debug before you actually use the hardware Debugging on actual hardware is difficult because you have poor visibility into the FPGA internals There are several techniques that have worked for us on projects Xilinx ChipScope built in test modes and judicious use of testpoints SBC6713e has three testpoints in the logic these are unused and may be connected to signals you want to
80. 0 data 28 dsp dll locked data 29 lt reset n data 30 lt reset data 31 lt wdt count 20 data 32 lt wdt en data 33 lt 1 when wdt reset 1 and wdt en data 34 lt wdt Wr data 55 downto 35 wdt count control lt control0 Figure 49 Chip Scope Core Instantiation and Use dsp force reset 1 else 0 Once the core is in the design you can then trigger on different conditions just as you would use a logic analyzer If connect up all the signals in the problem area only one compilation is needed to get the core into the design for debug Once you get it all working you have a logic analyzer inside the FPGA Here s sample view gs 777 ousted x om riri fl En Ce 1311188 Tar a E ul TOTES LII LU IU Lt LH Ld STR A AAA amesisss amaia ATTE i nl in iu mi Figure 50 Chip Scope Analyzer Screen Shot For more information see the Xilinx Website Sbc6713e User s Manual EDIT 169 Sbc6713e User s Manual 170 Creating a Binary File When using single board computers such as the baseboard32 or baseboard6711 it is possible to embed application code into Flash ROM so that the application begins executing immediately after power up In order to accomplish this you must first create a Code Composer project build it and then debug test it by downloading it with the terminal emulator and Code Composer The standard
81. 2 Input Description Output modl_data lt 5 gt modl_data lt 6 gt modl_data lt 7 gt modl_data lt 8 gt modl_data lt 9 gt modl_data lt 10 gt modl_data lt 11 gt modl_data lt 12 gt modl_data lt 13 gt modl_data lt 14 gt modl_data lt 15 gt modl_data lt 16 gt modl_data lt 17 gt modl_data lt 18 gt modl_data lt 19 gt modl_data lt 20 gt modl_data lt 21 gt modl_data lt 22 gt modl_data lt 23 gt modl_data lt 24 gt modl_data lt 25 gt modl_data lt 26 gt modl_data lt 27 gt modl_data lt 28 gt Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Module 1 Data Omnibus Module Address Omnibus Module Address noia e Output Sbc6713e User s Manual Omnibus Module Address Omnibus Module Address Omnibus Module Address Omnibus Module Address 60 Signal Name an Input Description Output EET A CAE meras rs Output Omnibus Module Adres mod_rw M4 Output Read active high and Write active low to module mod wins H2 impar MohieTrigerz i mod tig n gt us impr Mode Triggers i fami
82. 202 Sbc6713e User s Manual List of Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figures Mista Vertical cd 16 innovative Install PLOMO A A Se a es 17 Progressds shown for cach se A oe ented 18 ToolSet O abia 19 Bus Master CONO UT tn UE 19 Installation complete A A eee ee 20 Rtdx Terminal Options iii tad 28 FPGA Framework Overview a tede la Gra e te ee np opp a Rn B yg de anata eric da 38 Framework Logic Block Diagr tm 5 me a F EE 39 UART Block Diagram 3 taeciner ato e ROUTER ED CEU T E Ede e HIE 40 Figure 11 Logic Files and Hierarchy iti a err a 42 Figure 12 Map R sults z iui ui ut ea CHE e p e ERROR WR ERGO E etico e 43 Figure 13 PAR Results aene teo eH rar e Ur e tac eam er deed 44 Figure 14 DSP Asynchronous Read Timing Courtesy of Texas Instrument 45 Figure 15 DSP Asynchronous Write Timing Courtesy of Texas Instrument 45 Figure 16 DSP SBSRAM Read Timing Courtesy of Texas Instruments esses 46 Figure 17 DSP SBSRAM Write Timing Courtesy of Texas Instruments eene 47 Figure 18 EMIF B Data Bus Read Interface Diagram nennen ennetnetetnennenne trennen enne 48 Figure 19 Data MUR 4 datei b tua idet ot ae Hte ten dte dope Eo econtra td 49 Figure 20 Incoming DSP Data dut dacote date dst te act oe e n te e deren tet uen 50 Figure 21 DSP Controls Sign ls coeee e e E HELL Be t LR REG pn lee e RE S a nes
83. 7 PULL U dio 8 PULL U dio 9 PULL U dio 10 PU dio 11 PU dio 12 PU dio 13 PU dio 14 PU dio 15 PU dio 16 PU dio 17 PU dio 18 PU dio 19 PU dio 20 PU dio 21 PU dio 22 PU dio 23 PU dio 24 PU dio 25 PU dio 26 PU dio 27 PU dio 28 PU dio 29 PU dio 30 PU dio 31 PU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU LLU P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P dsp int 4 Interrupt to DSP dsp int 5 Interrupt to DSP Sbc6713e User s Manual 54 Signal Name dsp_int 6 dsp_int 7 dsp rd fifo int dsp reset dsp t0 dsp t1 dsp wr fifo int a H t ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ea 17 ea 18 ea 19 ea 20 ea 21 eclk in ed 0 ed 1 ed 2 ed 3 ed 4 ed 5 ed 6 ed 7 ed 8 ed 9 Sbc6713e User s Manual AB3 P J A AA A A A A A A A A Assigned Input Description Output Interrupt to DSP Interrupt to DSP Input Interrupt from Inter processor FIFO Spartan Ie 50K nput Interrupt from Inter processor FIFO Spartan Ile 50K Data terminal ready from UART mw fE CTE MIF ADDRESS MIF ADDRESS EMIF ADDRESS Input E E E E MIF ADDRESS IF ADDRESS IF ADDRESS IF ADDRESS EMI
84. BC6713e EMIF B memory decodings are arranged so that CEO is Synchronous DRAM SDRAM CE2 is a burst memory space for FPDP FIFO and the Inter processor FIFO for the 6713 is mapped to CE2 as a burst memory device allowing very high rate transfers with the DM642 whereas CEl and CE3 are Asynchronous and the wait states are controlled by hardware ready Generally speaking the async peripherals are not used as high speed devices since this is inherently a slow access protocol the sync burst memory interface is at least 4x faster The following diagrams show the DSP access timing for burst reads and writes Sbc6713e User s Manual 44 Setup 2 Strobe 3 Not Ready Hold 2 eot VVV YV VY YV UYU VY YV V V gt IK 1 29 TEX Y J f 1 9 H gt k 2 BE 3 0 BE i A I 4 9 t 2 EA 21 2 X Address a i 1 1 il ITE i 2 E SR ED 31 0 T L mo 1 Read Data RiT Ri AOE SDRAS SSOEt i 4 4 5 c rt gt le 5 ARE SDCAS SSADSt y Ro ES ae rs s AWE SDWE SSWE 7 a Rcs y 4 6 A 6 i ARDY C C0 C Nn t AOE SDRAS SSOE ARE SDCAS SSADS and AWE SDWE SSWE operate as AOE identified under select signals ARE and AWE respectively during asynchronous memory accesses Figure 14 DSP Asynchronous Read Timing Courtesy of Texas Instrument Setup 2 Strobe 3 Not Ready Hold 2 euosr IAS AIA AINA ILI NO k
85. BIOS Use of Pismo ClockBase objects for timebase control emulator Uart BCB DSP BIOS The Next Step Developing Custom Code In building custom code for an application Innovative Integration recommends that you begin with one of the sample programs as an example and extend it to serve the exact needs of the particular job or at least refer to the examples to see how some functions are done Since each of the example programs illustrates a basic data acquisition or DSP task integrated into the target hardware it should be fairly straightforward to find an example which roughly approximates the basic operation of the application It is recommended that you familiarize yourself with the sample programs provided The sample programs will provide a skeleton for the fully custom application and ease a lot of the target integration work by providing hooks into the peripheral libraries and devices themselves Sbc6713e User s Manual 62 Communication with the Host Overview Some applications for the Sbc6713e baseboard involve communication with the host CPU in some manner During development applications are routinely downloaded from the host following a target reset even if there is no further Host communications afterwards Some applications need to interact with a host program during the lifetime of the program This may vary from a small amount of information to acquiring large amounts of data Some examples e
86. Code Composer build process will generate a out file which is suitable for use within the terminal emulator or Code Composer but is unsuitable for placement in Flash ROM Once you have a viable out file it must be converted into a binary file before it can be burned into the target DSP card s Flash ROM The process of converting an out file into a binary file bin is target specific baseboard31 baseboard32 and baseboard54 targets To briefly describe this conversion process the out file from the Code Composer project will be converted to a a0 file using a hex converter and a cmd file The a0 file is a readable ASCII version of the out file Then this intermediate a0 file is converted to a bin file using a hex to bin converter hex2bin exe provided in your release To accomplish this conversion quickly and easily Innovative Integration has provided a template application mk that can be modified to convert your file This template is located in the target DSP card s root directory To convert your out file into a bin file to be burned to the Flash ROM proceed as follows 1 To start off you must have a viable out file ie yourfile out 2 Next you will have to create a mk file for the out to bin conversion using the template provided application mk e Copy the template application mkfile in C N I I Target Board gt to the directory where yourfile out resides and rename it to yourfile mk Open this new file wit
87. DP Receiver Data fpdp rx dvalid n active FPDP Rx Data Valid i e Data is Valid from FPDP low tx n B7 a 7 4 B6 6 6 6 BS 5 5 B4 11 10 fpdp rx nrdy n Rx not ready until the FPDP reset is deasserted fpdp rx p strobe i FPDP Rx Strobe ut ut fpdp rx pio 1 The PIO signals are programmable I O lines fpdp rx suspend n Y11 Output This signal suspends the data flow when the Rx FIFO is nearly full fpdp rx sync n FPDP Rx receives sync n to begin fpdp rx pio 0 The PIO signals are programmable T O lines AA16 i Y16 Sbc6713e User s Manual 57 Signal Name Assigned Input Description Output P FPDP Tx transmit data fpdp tx do 15 FPDP Tx transmit data V fpdp_tx_do lt 14 gt fpdp tx do 16 ABI5 FPDP Tx transmit data FPDP Tx transmit data in 14 14 fpdp_tx_do lt 17 gt fpdp tx do 18 FPDP Tx transmit data fpdp_tx_do lt 19 gt FPDP Tx transmit data fpdp_tx_do lt 20 gt FPDP Tx transmit data fpdp_tx_do lt 21 gt AB16 FPDP Tx transmit data W16 20 18 i 18 W17 AA Y oap doc22s wis Output FPDP Tx transmit da S S Hp sedeo wir Ow FPDP Tx transmit daa fpdp tx do 31 FPDP Tx transmit data fpdp tx dvalid n Data Valid assertion indicates that data bus has valid data fpdp tx n strobe AAI7 Output This Strobe is the negative version of the differential IOSTANDARD PECL data strobe LVPECL fpdp_tx_p_ strobe
88. DSP The requirements of this buffer are the following 10 Needs to contain at least two 32 bit words The driver currently does not handle buffers smaller than two 32 bit words i e three bytes etc 11 The number of of 32 bit words in your data buffer needs to be a multiple of two i e even number of 32 bit words 12 Target to Host data packet send n recv_n Just as with the Command receive operation the Host will first post a receive using recv_n ACE SOK Stream method then it will decode the packet type i e xcSend or xcSendCommand after sending and ack packet back to Target DSP it will post another receive using recv_n with the information gotten from the header i e it will pass the number of bytes is expecting to receive Host needs to send packet acknowledgments for every packet received this also includes the one for a Header packet Communication between Host PC and DSP Target Processor The following section describes how to communicate between a Host PC and the C6713 from the perspective of the C6713 DSP We previously discussed communications between Host and DSP Co Processor The SBC6713e is capable of handling two types of data packets 1 User data packets 2 Command data packets There is a different C method to handle the transmission of these two types of message d Transfer Send Buffer amp buffer 2 Transfer SendCommand short CommandId int Arg0 int Argl int Arg2 In the SendComman
89. E The project features of Code Composer Studio support component file editing and compilation stages along with allowing the executable result to be downloaded and tested on the target hardware This fully integrated programmers environment is more user friendly then the basic command line interface which comes standard with the TI tools Automatic projectfile creation When a project is created opened modified built or rebuilt the Code Composer Studio dependency generator automatically generates a project makefile named lt project file gt pjt located in the project directory which is capable of rebuilding the project s output file from its components This file is automatically submitted to the internal make facility whenever you click on build or rebuild within Code Composer Studio The make facility automatically constructs the output file by recompiling the out of date source files including the dependencies contained within those source files Rebuilding a Project It is sometimes necessary to force a complete rebuild of an output file manually such as when you change optimization levels within a project To force a project rebuild select Project Rebuild All from the Code Composer Studio menu bar IIMain replaces main Due to restrictions within Dsp Bios not all BIOS features may be safely used within main since it is called early in the system initialization sequence To circumvent this limitation Pismo automatically c
90. ED eed 40 Logic Files and Hierarchy eee RERO ISI PER RR INN SEIEN I sure cus eee 41 Fitting Results for the ErameworlceLogic eene n eem asa 42 Adding functionality to the Framework Logic sess nennen nennen 44 Logic Design Methods and Code Development nennen eren nnne nenne nnne nnns 44 DSP Interface DOg106 onion OSTEN EN NR E Uy Ne REED Na 44 DSP EMIE Data Read IBterface ii et 47 DSP EMIF Write Interface cedit a ER CER UTER EH EU REO HD CORR 49 Digital TO from the Spartan IIE iicet e ee aa eo dn 51 Clock Domaitis 2er pe ete e RO e p d oet pae M er E Oi eot n HER 51 Constraints utere rU ete d RO A ERa ad 52 Taming Constraints TT 52 TO St ndard Constraints 7 2 1 It nein ree ER ER GF PRO RIT ERO GEHE Uer paints 53 Pin Constraints A A Cie D REO A Er ages 53 Pin Assignments For Spartan ITE 300K 600K esses eene nnne nnne entrent nnne narran eren nnns 53 MMU AON terse Aid LEUR TIS 161 Required Software and Hard ware cccccccccessesscessesseeseeeseeseeeseeseecsecsecesecseeeaeceeesecneeeaecesesseseseceseseceeeseeeseeeeeeaeeensneeene 161 Setting INSI lessen eene nennen enr ESE ENESE ene nene rn enr enn eterne eterne nnn enne n nennen 161 SERIA MESI re minene i E E a a a e a E a aaa 161 Janna NUI RM 161 Modifying the Simulations essere enne enne enne rne nennen teen RR RR On RR nn nn rr nn ESES ESSES nnne 162
91. F ADDRESS mw fE mw fE ETE mu IF ADDRESS IF ADDRESS IF ADDRESS IF ADDRESS EMIF ADDRESS mw mw CTE CTE IF ADDRESS IF ADDRESS IF ADDRESS IF ADDRESS EMIF ADDRESS mw fE CTE E IF ADDRESS IF ADDRESS xternal EMIF input clock in K5 L5 18 15 B15 3 L22 B3 E8 5 E7 B4 4 C8 C7 3 B7 7 6 8 B8 B10 10 9 C9 E9 F9 C10 D10 E10 F10 wow fE mou TE E E E IF DATA IF DATA IF DATA MIF DATA MIF DATA EMIF DATA mou E mow E E MIF DATA MIF DATA MIF DATA 55 Signal Name Assigned Input Description Pin Output ed 10 EMIF DATA ead D EMIF DATA ed 12 A12 EMIF DATA ed 13 B12 EMIF DATA ed 14 C12 EMIF DATA ed 15 D12 EMIF DATA ed 16 E12 EMIF DATA ed 17 EMIF DATA ed 18 EMIF DATA ed 19 EMIF DATA ed 20 EMIF DATA ed 21 EMIF DATA ed 22 EMIF DATA ed 23 EMIF DATA ed 24 EMIF DATA EMIF DATA EMIF DATA Sbc6713e User s Manual Signal Name Assigned Input Description P Output I iip dnd ib p rx dnd dp rx din ib p rx dis ibdp rx din ibd rx dinQo ibd rx din ibdp rx din 2 ib p rx dina dp rx ding Ans put FPDP Receiver Daa AA Y W AA fpdp_rx_din 25 A fpdp rx din 26 FPDP Receiver Data FPDP Receiver Data fpdp rx din 27 fpdp rx din 29 A fpdp rx din 28 ws Hpu FPDP Receiver Data gt z fpdp rx din 30 ABI ipu FPDP Receiver Data fpdp rx din 31 AAI Imput FP
92. Innovative Integration Sbc6713e User s Manual Sbc6713e User s Manual The Sbc6713e User s Manual was prepared by the technical staff of Innovative Integration on February 5 2009 For further assistance contact Innovative Integration 2390 A Ward Ave Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2009 by Innovative Integration All rights are reserved VSS Distributions Sbc6713e Documentation Manual Sbc6713eMaster odm FXXXXXX Rev 1 0 Table of Contents INTO UCHON e RN LL Real Time Solutions iii mode isn iecit eta ue m ie Recent e aby 11 Mocabulary 5 sss Meere timide eq e ses dh edet eee HN RES 11 What isthe SBC671967 teet reete dd ete eee oerte e ea een 11 Whats CE Builder2 snot dette dtt tto e pe E eg er Eee tee 12 What is Microsoft MS V 23 ots cs dee ete te t Ta ettet pete pe peregre e dea 12 What kinds of applications are possible with Innovative Integration hardware sese 12 Why do I need to use Malibu with my Baseboard 2 2 0 ccecccescesceescesseeseeeeesecseeeseeseeesecseeesecaeeeaeeaesaeeeeeeaeeeeeeeenseeaes 12 Finding detailed information on Malibu ccceccescesscessesseeeceeeesecescesecesecsecesecsecesesseeesecseeesecseeeaeeeeeseceseeaseneeeeenseeaes 12 Online Help ehe nang E ERR NO IM 13 Innovative Integration Technical Support
93. JTAG gate count for IOBs 15 072 Peak Memory Usage 123 MB Figure 12 Map Results The Place and Route Step results are taken from the sbc6713 top par report Timing analysis is shown for the design It is important to review this report to find timing errors The PAR report shows how the design performed against each defined timing constraint For further analysis the timing analyzer tool can be used to pinpoint the source of each problem The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is 0 The AVERAGE CONNECTION DELAY for this design is 15 932 The MAXIMUM PIN DELAY IS 10 608 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is 8 674 Listing Pin Delays by value nsec d 2 00 d 4 00 d 6 00 lt d lt 8 00 d 11 00 d gt 11 00 Timing Score 441574 WARNING Par 62 Timing constraints have not been met Asterisk preceding a constraint indicates it was not met This may be due to a setup or hold violation Sbc6713e User s Manual 43 Constraint Requested Actual Logic Levels TS J TO J MAXDELAY FROM TIMEGRP J CLK 30 000ns 14 022ns 5 TO TIMEGRP J CLK 30 nS TS U TO J MAXDELAY FROM TIMEGRP U CLK 15 000ns 5 062ns il TO TIMEGRP J CLK 15 nS TS FPDP Rx Control MAXDELAY FROM TIMEGR 10 000ns 12 055ns 7 P FPDP Rx Control TO TIMEGRP FFS 10 ns Figure 13 PAR Results Adding functionality to the Framework Logic The framework logic is a starting point for the more advanced logic t
94. ORE eclk in IN 6 ns BEFORE eclk in Sbc6713e User s Manual 52 NET ce2 n OFFSET NET ce3 n OFFSET IN 6 ns BEFORE eclk in IN 6 ns BEFORE eclk in Figure 27 DSP Signals Timing Constraints IO Standard Constraints Each pin is defined for its appropriate IO standard The Xilinx default standard is LVTTL so it is common to leave those out and define only the exceptions Do not change the IO standard as defined as this may cause damage to the devices NET ardy LOC D5 IOSTANDARD LVTTL NET are n LOC C5 IOSTANDARD LVTTL NET awe n LOC D7 IOSTANDARD LVTTL NET cel n LOC B6 IOSTANDARD LVTTL NET ce2 n LOC C6 IOSTANDARD LVTTL NET ce3 n LOC C4 IOSTANDARD LVTTL Figure 28 IO Standard Constraint Pin Constraints Each pin has a placement defined in the UCF file as required by the circuit board design DO NOT CHANGE these assignments as damage may occur to the Quixote They must be used on all compiles NET eclk in LOC C11 IOSTANDARD LVTTL Pin Assignments For Spartan IIE 300K 600K Table 14 I O Standard LVTTL Signal Name Assigned Input Description Pin Output Feel_n activelow ns impar Memory space enable Grom DSP Ma Sbc6713e User s Manual Signal Name Assigned Input Description Pin Output dio 0 PULL U dio 1 PULL U dio 2 PULL U dio 3 PULL U dio 4 PULL U dio 5 PULL U dio 6 PULL U dio
95. OS drivers Analog output driven from emulator analog input AnalogCapture terminal DSP BIOS Repeatedly start Analog Input Streaming to capture points emulator Useful for high rate input AnalogIn terminal DSP BIOS Analog capture into DSP memory Samples sent to host emulator and saved for analysis AnalogOut terminal DSP BIOS Analog waveform playback from pre calculated buffer in emulator DSP memory ASnap BCB VC DSP BIOS Full rate analog capture to memory then send to host via 7 VC8 busmastering Illustrates data capture and target host NET communication with commands and data packets CommonCDB N A N A Shared CDB file for all examples DioData terminal DSP BIOS Use of the board Digital I O emulator Edma terminal DSP BIOS Use of Pismo Edma and Qdma wrapper classes with emulator installable interrupt handlers FftFloat terminal DSP BIOS Use of floating point FFTs emulator Files terminal DSP BIOS Use of C Standard I O library emulator FirFloat terminal DSP BIOS Use of FIR filters emulator Sbc6713e User s Manual 61 Example Host Target Illustrates Fp terminal DSP BIOS emulator FpEcho terminal DSP BIOS Use of FPDP driver to flow data through loopback emulator connector Messages BCB DSP BIOS VC 7 Servo terminal DSP BIOS Use of the PISMO Servo class for servo application emulator Swi terminal DSP BIOS Use of Pismo SoftInt class for software interrupts emulator Timer terminal DSP
96. Ormmibus Intetface esed map te dean dim Ed Eee epe sphere tines anksusea ehescasesates 164 Burst Reads And VE HITS ticas 165 Loading the Logic Im ge 5 eoe dete id ia exo 168 FlashBurn Utility s e tete dec ete edet co ON E EE DAR dvd cous bte OR PASSE RUE VES 164 Deb gging Custom Logics ce 5e e edet e ete Pee late i MEET se RE e o t eR UE 165 Built in Lest Modes 425 ue to tie e te REI De AR Ede Rer tee ede bee tee re Ede de d pe ie BER ears 165 Pelias ER EEE 166 Declaration Of ChipScope Corem VHDL seese eeann eet iris 168 Creating a Binary FO eT DT baseboard3 1 baseboard32 and baseboard54 targets nennen 171 Sbc6713e User s Manual baseboard67 and baseboard6711 Targets sss eene nennen tenen nnne nnne nennen 172 The Flash Barn Utility ein oe n REGI EE RI RE HUN C ERN NUR NU UIN 172 Target E 172 Talker Page ED DIOC E EE EEE T EEA T E E A 173 JTAG Downloadi ai 174 Flash ROM Download e eniro d Per Gr A ER e Ea ER HU ERA Ce RR EARLIER E 175 Downloading the Flash Support Code sessi n nennen enne 175 Flash Pages P M 175 Controlling Region of Erase ele T GAIN Ere HERE er Eee Pese e ree tegi 175 Re burning the Talker Tae ia ges ee indi 176 A 176 Burning a User Written Application essere enne eerte
97. Passing parameters to the program at start time e Receiving progress information and results from the application e Passing updated parameters during the run of the program such as the frequency and amplitude of a wave to be produced on the target e Receiving alert information from the target e Receiving snapshots of data from the target e Sending a sample waveform to be generated to the target These different requirements require different levels of support to efficiently accomplish The simplest method supported is a mapping of Standard C I O to the terminal emulator applet that allows console type I O on the host This allows simple data input and control and the sending of text strings to the user The next level of support is given by the Packetized Message Interface This allows more complicated medium rate transfer of commands and information between the host and target It requires some software support on the host unlike the use of standard I O Packetized Message Interface The DSP and Host are interconnected via a 1OBASE T 100BASE T Ethernet communications link for the interchange of commands and information The Pismo libraries provide a packet based message system between the target and host software These packets can provide a simple yet powerful means of sending commands and information across the link Sbc6713e User s Manual 63 Communication between Host PC and DSP Co Processor Even though the SBC6713e uses
98. Pismo library provides a set of class objects that meet this problem These lock objects disable a particular interrupt or all interrupts in a region and restore the state to what it was on entry when the lock object is destroyed If the object is created on the stack any means of exiting the block in which the object is defined will cause the cleanup code to be called Calls to these objects properly nest as well Table 11 Interrupt Lock Classes Lock Class Interrupts Affected TI Class Library InterruptLock One IRQ CSL GlobalIntLock All interrupts CSL HwiGlobalIntLock All interrupts DSP BIOS Interrupt Binder Templates The Binder system can be thought of as a more flexible and powerful version of a function pointer variable allowing a user callback function to be called indirectly without knowing more than the interface to the function Since the binder objects are templates the type of the function and its arguments are not fixed but can be of any type Also member functions can be bound to an interrupt which a callback function can never do The Binder system is powerful yet in practice is quite simple to use This system illustrates the power of the C language to contain a complicated system in a simple to use package Class InterruptHandler This class is a base class for the ClassMemberHandler and FunctionHandler templates It provides the interface the Pismo system uses to call the interrupt handler Class ClassMemberHandler Te
99. SBC6713e baseboard SD16 module at 50 kHz using namespace II TIMain Illustrate Omnibus Output AnalogOutStream Aout Omnibus mSite0 void IIMain Load Module onto site 0 LoadModule Omnibus mSite0 Omnibus mtSD16 Use default clock DDS Set Clock Rate ClockRateUIPtr Aout Clock Rate 50000 Output on all channels Aout Channels gt EnableAll Size the buffers Aout Events 5000 Sbc6713e User s Manual 47 Aout BufferCount BuffersPerSec 3 Open the streams Aout Open 7 Stream loop bool run true while run Aout Generate Aout Put Terminate streaming Aout Close Examining the above code you can see the application uses an AnalogOutStream since it is an output program The next interesting line is the call to LoadModule This informs the system of which module is plugged in on Omnibus mSite0 where the stream is also attached With the attachment of the module to the stream the stream object can configure hardware clock and trigger settings The next several lines configure the Stream clock rate the channel configuration and the stream buffer count and buffer size Then comes the Stream Open method which activates the device driver in DSP BIOS Afterwards the Stream Control method may be used to perform any necessary device specific initialization and or control functions Data flow begins with
100. Target page contains two controls used to select the DSP type being used and its target number as shown below Sbc6713e User s Manual 172 Burn Biel ES File Help Target Talker Flash Info None Type ll Number Click on the Number combo control and select the number of the DSP target you re using usually 0 It is important to remember that for single boards targets zero corresponds to COMI and target one corresponds to COM2 etc Next click on the Type combo control to display a list of supported targets then select your DSP type After you have selected the DSP type the applet will attempt to open the target device driver to establish communication with the target The status of this attempt is displayed in the status bar at the bottom of the Burn applet window If the driver is successfully opened Target Open OK click on the Talker tab to proceed If the target driver does not successfully open check the parameters being requested and the installation of your DSP Also close any other open applications such as the terminal emulator EXE which could have previously opened the DSP device driver Due to Windows restrictions only a single application may open a com port device at a time Talker Page To support all single board DSP targets similarly BURN must download a simple DSP support executable to the target before an embedded application may be burned into the Flash ROM This executable is FLASHER OUT
101. Y17 Output This Strobe is the positive version of the differential IOSTANDARD PECL data strobe LVPECL fpdp_tx_pio lt 0 gt The PIO signals are programmable T O lines fpdp_tx_pio lt 1 gt The PIO signals are programmable T O lines fpdp_tx_suspend_n AA19 Input This signal suspends the data flow when the Rx active low FIFO is nearly full fpdp tx sync n U12 Output FPDP Tx provides a sync pulse to synchronizing active low data transfers in different modes Sbc6713e User s Manual 58 Signal Name iordy_n lt 0 gt active low iordy_n lt 1 gt active low mod0_data lt 0 gt mod0_data lt 1 gt mod0_data lt 2 gt mod0_data lt 3 gt mod0_data lt 4 gt mod0_data lt 5 gt mod0_data lt 6 gt mod0_data lt 7 gt mod0_data lt 8 gt mod0_data lt 9 gt mod0_data lt 10 gt mod0_data lt 11 gt mod0_data lt 12 gt mod0_data lt 13 gt mod0_data lt 14 gt mod0_data lt 15 gt mod0_data lt 16 gt mod0_data lt 17 gt mod0_data lt 18 gt mod0_data lt 19 gt mod0_data lt 20 gt mod0_data lt 21 gt mod0_data lt 22 gt mod0_data lt 23 gt mod0_data lt 24 gt mod0_data lt 25 gt mod0_data lt 26 gt mod0_data lt 27 gt mod0_data lt 28 gt mod0_data lt 29 gt mod0_data lt 30 gt mod0_data lt 31 gt mod0_int lt 0 gt mod0_int lt 1 gt mod0_timer lt 0 gt mod0_timer lt 1 gt modl_data lt 0 gt modl_data lt 1 gt Sbc6713e User s Manual T3 P in 1 2 3 3 3 M3 3 K3 3 2 W2 2 2 2 2 2 2 M2 2 K2 2 1 WI 1
102. able for development of Windows applications of any type Armada extends the MSVC IDE through the addition of dynamically created MSVC compatible C classes specifically tailored to perform real time data streaming functions What kinds of applications are possible with Innovative Integration hardware Data acquisition data logging stimulus response and signal processing jobs are easily solved with Innovative Integration baseboards using the Malibu software There are a wide selection of peripheral devices available in the Matador DSP product family for all types of signals from DC to RF frequency applications video or audio processing Additionally multiple Innovative Integration baseboards can be used for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards for high performance signal processing Why do I need to use Malibu with my Baseboard One of the biggest issues in using the personal computer for data collection control and communications applications is the relatively poor real time performance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at processing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rat
103. acket 0 pkinfoRequestAck aSendPacket 1 Interface logic version aSendPacket 2 Lan logic version aSendPacket 3 Client version running on DM642 Co Processor aSendPacket 4 Board serial number aSendPacket 5 Board version aSendPacket 6 Static IP or DHCP usage bool From here on data is sent as null terminated strings aSendPacket 7 Static IP address even if using DHCP we send the saved static address aSendPacket 11 Mask aSendPacket 15 Gateway address aSendPacket 19 DNS aSendPacket 23 Domain name aSendPacket 199 string termination 0 Host closes socket V Write Board information This is used to write certain information to the Target board like IP information and to boot Innovative s Benign program or a custom program stored in flash You can also write the Serial Number of the board and board revision this operation is not suggested since Serial Number and Board Revision are used to set the MAC address of the board this command is only for use in house Host opens socket number 1022 Host sends a write request packet int packet 200 Data to send packet 0 pkWriteNetInfo To set IP addr mask etc packet 1 ip addr 0 mask NO gateway NO dns 0 domain 0 use static IP Y N 0 As you can see the information following the packet type is a group of null terminated strings Sbc6713e User s Manual TT OR the Hos
104. ality These functions are available on the menu bar located at the top of the the terminal emulator main window Speed button Sbc6713e User s Manual 25 equivalents for each of the menu options are also available on the button bar located immediately Rtdx Ter beneath the menu bar The following is a description of each menu entry available in the terminal File Dsp For emulator and its effects The File Menu File Load provides for COFF Common Object File Format program downloads from within the terminal emulator When selected a file requester dialog box is opened and the full pathname to the COFF filename to be downloaded is selected by the user Clicking Open in the file requester once a filename has been selected will cause the requester to close and the file to be downloaded to the target and executed Clicking Cancel will abort the file selection and close the requester with no download taking place This operation can optionally be initiated via the al button File Reload Reloads and executes the COFF file last downloaded to the target It provides a fast means to re execute the application program most recently loaded into the target board This operation can optionally be initiated via the d button NOTE File Load and File Reload functions use the JTAG debugger and Code Composer Studio in order to effect the program download File Save saves the textual contents of the Terminal and Log ta
105. alled Some examples have no host component and some use the terminal emulator applet as the host Host examples are written in C either under Sbc6713e User s Manual 89 Borland Builder or Microsoft MSVC or both Target examples are written using CCS 3 3 and DSP BIOS Note that not all of the examples listed below are available for all targets Table 13 Pismo Example Programs Example Host Target Illustrates FftFix terminal emulator DSP BIOS Use of Fourier class to perform forward and inverse FFTs FirFix terminal emulator DSP BIOS Use of BlockFir class to perform FIR filter functions Edma terminal emulator DSP BIOS Use of Pismo Edma and Qdma wrapper classes with installable interrupt handlers Files terminal emulator DSP BIOS Use of C Standard I O library CpulnRate BCB DSP BIOS Use of Target to Host message and data packet passing via MSVC PCI bus CpuOutRate BCB DSP BIOS Use of Host to Target message and data packet passing via MSVC PCI bus LinkPort BCB DSP BIOS Use of LinkPort driver to flow data between all processor in mesh Swi terminal emulator DSP BIOS Use of Pismo SoftInt class for software interrupts Timer terminal emulator DSP BIOS Use of Pismo ClockBase objects for timebase control The Next Step Developing Custom Code In building custom code for an application Innovative Integration recommends that you begin with one of the sample programs as an example and
106. an Ethernet link the C6713 doesn t get involved in any TCP IP protocol related work this is handled by a dedicated co processor Brief details of the communication protocol There are basically two aspects of the communication protocol the host and the target co processor The host libraries Malibu libraries use a common domain software called the ACE toolkit a good source of information can be found in 1 C Network Programming Mastering Complexity with ACE and Patterns Douglas C Smith Stephen D Huston Addison Wesley The ACE toolkit handles all TCP IP protocol implementations There are two packet types 1 Command packet 2 Data packet These two packet types use the same ACE SOCK Stream methods send_n and recv_n which transmit and receive data buffers of exactly n bytes 1 We will not explain how the details of the ACE toolkit implementation rather the structure of the data buffer passed to these methods and the handshake protocol used between host PC application and Sbc6713e co processor 7 Host to Target command packet send n recv n Host send n command packet 77 Target Host recv_n lt lt command ack Target At a high level the Host will use the following ACE SOCK Stream method please refer to NetTransferThread Mb cpp in Malibu library as a help to understand more of the details there is also a chapter that goes into the details of host target communicat
107. andle interval before next start trigger Selecting Pretriggering Modes The pretrigger control for a stream consists of the following methods Table 7 Stream object Pretrigger Methods Method Description IsPretriggerTypeSupported Returns True if the pretrigger mode is allowed on the hardware SetPretriggerType Change pretrigger to the selected mode Pretrigger Returns the pretrigger interface for the mode Table 8 Stream object Start Trigger Methods Method Description IsStartTriggerTypeSupported Returns True if the start trigger mode is allowed on the hardware SetStartTriggerType Change start trigger to the selected mode Sbc6713e User s Manual 50 StartTrigger Returns the start trigger interface for the mode Table 9 Stream object Stop Trigger Methods Method Description IsStopTriggerT ypeSupported Returns True if the stop trigger mode is allowed on the hardware SetStopTriggerT ype Change stop trigger to the selected mode StopTrigger Returns the stop trigger interface for the mode Table 10 Stream object Retrigger Methods Method Description IsRetriggerTypeSupported Returns True if the retrigger mode is allowed on the hardware SetRetriggerType Change retrigger to the selected mode Retrigger Returns the retrigger interface for the mode Trigger configuration presents the same problem as the clock configuration except more so Triggering consists of four parts each of which can be indepe
108. application using fast Ethernet Overview The SBC6713e Logic Frame work is the basis for custom logic application development This Framework allows the FPGA designers to begin with a known working design that illustrates analog IO and DSP interfacing techniques The custom application is then fit within the framework and includes the application specific code In many cases the standard methods for moving data to the DSP are retained so that custom software is minimized Target Devices SBC6713e has as its user programmable logic a Xilinx Spartan IIE 600K gates FPGA The Spartan Ile FPGA have many resources in addition to the logic gates such as embedded RAM blocks delay locked loop DLLs and flexible IO standards that are used in the provided logic The Xilinx device used for analog logic is XC2S600E 6FG456C Sbc6713e User s Manual 37 Code Development Tools Developing logic code for this FPGA is done using the Xilinx ISE Toolset and the Framework logic provided The Framework logic is delivered in VHDL language along with the control files for the Xilinx ISE software to allow the user to modify and compile the logic Simulation files are provided for use with MentorGraphics ModelSim A macro for the testbench is provided to compile and load the simulation When using ModelSim it is required to compile and reference the library files for unisim simprim and xilincorelib for the simulation to load properly Steps to S
109. arized high performance analog and digital peripherals with two high performance DSP and peripheral cores The SBC6713e is a derivative of the SBC6711 Pantera having an Ethernet port instead of a USB port The more common and flexible Ethernet port provides greater throughput approaching 100Mb s compared to the slower USB port The baseboard includes an onboard TMS320C6713 DSP with 32 MB cached SDRAM The DSP accesses to the entire baseboard peripheral complement directly as memory mapped devices The baseboard supports speeds approaching 100 Mbit sec a packet message based Ethernet bus interface two variable function Omnibus I O module sites dedicated Front Panel Data Port FPDP and SyncLink buses for inter board connectivity a precision DDS timebase to serve as an accurate programmable clock source from DC 25 MHz and a programmable digital I O port Because of the onboard DSP the baseboard is capable of performing data collection servo or other real time processing and data movement automatically without Host PC CPU involvement Sbc6713e User s Manual 11 What is C Builder C Builder is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the Builder IDE through the addition of functional blocks VCL components specifically tailored to perform real time data streaming functions What is Microsoft MSVC MSVC is a general purpose code authoring environment suit
110. ass If a UI interface is not supported the conversion function returns a null pointer The following code sample shows the use of trigger conversion functions and multiple interface classes The AD40 module is in use It supports several different Pretrigger and StartTrigger modes In the example we wish to use Counted Pretriggering and Threshold Start Triggering This example for an AD40 uses pretriggering and start triggering Set triggers Stream gt SetPretriggerType TriggerManager ptCounted Stream gt SetStartTriggerType TriggerManager stThreshold Configure Pretrigger to 500 counts Sbc6713e User s Manual 51 CountedPretriggerPtr Stream Pretrigger PretriggerCounts 500 Set start threshold to 1 volts VoltageThresholdPtr Stream gt StartTrigger gt ThresholdLevel 5 ConfigurableTriggerPtr Stream gt StartTrigger gt Type ttEdge ConfigurableTriggerPtr Stream gt StartTrigger gt Polarity tpPositive Counted Pretriggering allows the preservation of data samples before the start trigger fires Normally the first data point read was taken just after the start trigger fires With Counted Pretriggering N samples before the trigger fires are output when the trigger fires In the example below the pretrigger is set to return 500 samples from before the trigger The AD40 Threshold mode supports two interfaces VoltageThreshold and ConfigurableTrigger VoltageTh
111. ator Connection Mena ES SDS10 eid SD510 Emulator Connection TM8320C5500 10USB Emulator 3D510USB Emulator Connection TMS320C8400 ES SDDSKUSB Emulator SDDSKUSB Emulator Connection TMS32006200 EET Simulator TI Simulator Connection TMS320C6700 E TI XDS510 Emulator TI XDS510 Emulator Connection TMS320C6210 IE TI XDS560 Emulator TI XDS560 Emulator Connection TMS320C6710 TMS320C6720 ARM11 ARM ARMS gt Create Board EX Factory Boards E Custom Boards Remove Remove All lt lt Add Multiple Modify Properties Drag a device driver to the left to add a board to the system You will see the following screen Fill out the name of the board you are using this can be any name you like Connection Name amp Data File Connection Properties Connection SD510USB Emulator Name Mv Multi Proc JAuto generate board data file hz Browse id Browse Diagnostic Arguments Nest Cancel Sbc6713e User s Manual 31 Hit next or move to the next tab This address should match up with the address in the SdConfig exe utility Emulator 10 Port USB Emulator address is 0x510 Now we add a processor Each if the II boards have different processors so match up the closest one for your board E My System f TMS320F 2400 CACCStudioWriversisdgo24xusb dvr i f TM5320F2800 CACCStudio driversisdgo28xush dvr f Tws320c5400 CACCStudiotdriversYsdgoS4x
112. b uut right button Joled int tb oled intf vhd tb uut choose button oled int tb oled int vhd tb uut bit count Joled int tb oled intf vhd tb uut nop oled intf tb oled int vhd tb uut frame s oled intf tb oled intf vhd tb uut sr b Ll ee ee ar O ee Data Command Pacing There is NO pacing method used on the serial port Transmissions to the adapter therefore must not be done any faster than every 11 uS for data words or 8 uS for command words to the display Adapter commands require 1 uS between serial receptions These timings assume a 3 33 MHz serial clock max recommended rate so adjust them as necessary for other serial clock rates Sbc6713e User s Manual 183 Required steps to use the display 1 Reset the adapter board This is done by writing a serial word with bit 13 true This bit is NOT sticky you need write it only once true 2 Turn on the display power Allow 100 mS for stabilization 3 Reset the display 4 Begin display initialization as described in the SSD0323 manual Sbc6713e User s Manual 184 Appendices Connector pinouts JP4 JP8 OMNIBUS I O Connectors AMP 05 Subminiature D male AMP 173280 3 JP5 OMNIBUS I O Connectors The following table shows the interconnections between the JP4 OMNIBUS slot 0 and JP5 OMNIBUS IO connector JP4 Module 0 Pin JP5 Pin Numbers 8 9 c eec 6 jes Sbc6713e User s Manual p e I
113. bc6713e User s Manual 48 The CaptureInStream is a new type of driver that is used to emulate manual capturing of data to a buffer In this mode the analog hardware is inactive until a buffer is presented for filling When this occurs an acquisition is started that will fill the presented buffer after which data taking is stopped The process repeats for each buffer presented In the capture mode no processing is taking place when data is not requested This is a major difference from AnalogInStream Also if the buffer is sized to be smaller than the analog hardware s own FIFO or storage each buffer will be a snapshot dump of the FIFO contents This makes capture useful for snapshots of very high rate analog input faster than the module can be read There is no way to take continuous data sets larger than a single buffer in capture mode There will be a gap between any two captures AnalogInStream should be used for continuous applications Selecting and Configuring Hardware The Sbc6713e supports Omnibus Modules allowing multiple hardware configurations on the same baseboard Modules are attached to an Omnibus site by a call to LoadModule Load Module onto site 0 LoadModule Omnibus mSite0 Omnibus mtSD16 Once a module is loaded it can be accessed by the stream object s Module method This returns a generic pointer that can be converted to an exact module pointer to allow its methods to be called The functions that do thi
114. bedding into sector one of the flash ROM on the target board Note baseboard67x must be equipped with version 1 2 or later of Talker in order to use these image files The Flash Burn Utility The Flash ROM programming utility BURN EXE provides the capability to embed debugged application code within the flash ROM onboard Target DSPs which feature FLASH ROM Currently this includes each of the Innovative Integration single board computers the baseboard31 baseboard32 baseboard54 baseboard62 baseboard67 and baseboard6711 products Refer to the hardware manual for your DSP target to determine whether FLASH ROM is available on your system The utility supports both the 29F010 and 29F040 ROMs and provides special support for users with JTAG links between the host and the target in order to support programming The PROM utility contains only two menus File and Help plus four tabbed page controls labeled Target Talker Flash and Info Currently the Help menu is used to invoke help contents and the application About box which indicates the revision of the application The File menu provides access to the Options dialog which controls the timeout on JTAG loads and flash erase byte values discussed later In addition to the ability to convert Ascii hex text files into binary files suitable for consumption by the Burn utility The following is a brief description of the functions available under each of the primary tabs Target Page The
115. ber of 32 bit words otherwise the inter processor FIFO is not able to process it Also you already specified the amount of bytes you were sending in the previous header packet if you do not follow this then there is a great chance of confusion between the client and server programs Target replies with an ACK int buf 3 buf 0 CommStatusCode buf 1 Received Byte count buf 2 Received Byte count All Data Packets intended to reach the Target C6713 must have an even size of 32 bit words and a minimum of 4 words enum XfrCmdTypes xcSend 0xB0 xcSendCommand xcSendData xcClose xcSendDataData enum CommStatusCodes NetworkTimeoutErr 0x0 Success TargetTimeoutErr TargetErr UnknownErr CommAborted xcSendDataData is no longer used It is important to understand that this operation is Host initiated so the DM642 DSP will wait first on Host activity then it will forward the data to the C6713 DSP the C6713 DSP program must be expecting to receive this data otherwise Host PC will timeout within 5 seconds of no response that is in the case of Malibu II Receiving data from Target The port number used from this operation is 1009 This is the only port the Target DSP C6713 is able to send data to Host There are other ports sockets used where the Target Co Processor DM642 sends data to Host As a reference please have the file NetTargetTransfer_Mb cpp opened The concept Your Host code
116. bs to a user specified file File Print prints the textual contents of the Terminal and Log tabs to a user specified printer File Exit closes the emulator application terminating console emulation The DSP Menu Dsp Run causes the terminal emulator to bring the target board into a cold start Rtdx Terminal uninitialized condition This is functionally identical to performing Debug Run within Dsp Form He Code Composer Studio 3 Run This operation can optionally be initiated via the frs button Restart Reset Dsp Halt causes the terminal emulator to suspend DSP program execution This is functionally identical to performing Debug Halt within Code Composer Studio This operation can optionally be initiated via the mf button Dsp Restart rewinds the DSP program counter to the application entry point usually c int00 This is functionally identical to performing Debug Restart within Code Composer Studio This operation can optionally be initiated via the El button Sbc6713e User s Manual 26 Dsp Reset causes the terminal emulator to bring the target board into a cold start uninitialized condition This is functionally identical to performing Debug Reset Dsp within Code Composer Studio This operation can optionally be initiated via the io button The Form Menu Form Tuck Left repositions the main application window to the bottom left of the Windows desktop gt Dsp Form Help
117. cation To burn a user written application select as the starting Sector and adjust the ending sector to the uppermost available sector less any reserved sectors used as data storage within your DSP application program The Offset field should be set to zero for all target board types Info Page Detailed autoselect information read from the Flash ROM is available on this Info Tab This information is utilized internally by the BURN applet You need not enter information on this tab Sbc6713e User s Manual 176 Burn PIS ES File Help Target Talker Flash Info Flash Device Information Burned packet 49 49 Example Burn Sequence The following is a typical example of burning a binary file bin into the target card s Flash ROM l Run the Flash ROM programming utility BURN EXE from the Start Menu Programs lt Target Board gt Burn Click on the Target Tab Then click on the Number combo box and select the number of the DSP target you are using usually 0 e Next click on the Type combo box and select the target DSP type At the bottom of the display Target Open OK should be displayed Click on the Talker Tab e In this example from the two download methods the Flash ROM method is selected Click on the lt Coff File button and browse to the root directory of the Zuma Toolset and find the Flasher out file e Then click on the Run button
118. ce they define the clock rate for all flip flops connected to that clock These period constraints then cover most of the logic paths used in a synchronous design Here are the clock period constraints used by the Framework Logic NET eclk in TNM NET eclk in TIMESPEC TS eclk in PERIOD eclk in 13 ns HIGH 50 NET fpdp tx clk TNM NET fpdp tx clk TIMESPEC TS fpdp tx clk PERIOD fpdp tx clk 20 ns HIGH 50 NET Xin s TNM NET Xin s TIMESPEC TS Xin s PERIOD Xin s 271 ns HIGH 50 NET fpdp rx p strobe i TNM NET fpdp rx p strobe i TIMESPEC TS fpdp rx p strobe i PERIOD fpdp rx p strobe i 13 ns HIGH 50 Figure 26 Clock Period Constraints Figure 19 shows that EMIF clock eclk in is constrained to 13 ns giving a small margin for a 75MHz bus External devices require an additional constraint to be sure that we get the signal on chip and to its destination in time Since the external chip such as the DSP may have a delay from the clock edge to when we get the signal an additional constraint is defines the amount of time after the clock that the signal is given to the logic This type of constraint is used on the DSP control signals such as CE ARE AWE and addresses to guarantee that setup timings are met a Timing Group is defined for these signals with a timing constraint for the group NET are n OFFSET NET awe n OFFSET NET aoe n OFFSET IN 6 ns BEFORE eclk in IN 6 ns BEF
119. ced into Flash ROM so that it will begin execution during SBC power up The DSP reset is controlled by a dedicated reset controller onboard the SBC When an application program is available in FLASH ROM the built in loader software loads the user application software from onboard Flash ROM directly into target memory space as the target powers up Software tools are provided to facilitate reprogramming the target application image DSP JTAG Debugger Support Standard TMS320 family JTAG debugger operation is supported by each baseboard An external debugger connector is supplied that allows use of industry standard JTAG debugger hardware from Innovative Texas Instruments and other third party suppliers The DSP is the only device in the scan path Software for JTAG debugging and code development is TI Code Composer Studio The Pismo Class Library Innovative Integration s Pismo is a software class library allows the developer to fully exploit the advanced hardware features of the Innovative DSP product lines and to reap all the benefits from Texas Instrument s DSP BIOS Operating system Every board peripheral has been carefully integrated into the OS and its functionality encapsulated in a device driver Sbc6713e User s Manual 42 that can readily be controlled within DSP BIOS applications including PCI interface analog I O external bus and memory serial ports and other I O devices Pismo provides extensive C class support for e Dy
120. choing keystrokes These two lines are where custom code could be inserted The following do loop sequence simply echoes keys typed at the terminal emulator back to the terminal display until the Esc key is pressed When Esc is pressed the cio monitor function effectively terminates the program except that interrupts are still active and interrupt handlers if they had been installed would still execute properly The test program is very simple but it contains the basic components of a typical DSP application as well as the initialization needed to interact with the terminal emulator Use of Library Code Library routines can be compiled and linked into your custom software simply by making the appropriate call in the source and adding the appropriate library to the linker command file Refer to the library reference within the Pismo online help for library location information on each class and method In general user software needs to include the relevant library header file in source code The header files define prototypes for all library functions as well as definitions for various data structures used by the library functions The files HdwLib h and UtilLib h should be included within all programs The file DspLib h should be included if a program uses functions in the DspLib signal processing library Example Programs Under baseboard Examples in the install directory the baseboard s example programs are inst
121. condition is met the Host will send a final command to start the program on the Target packet 0 pkDownloadDone packet 1 0 packet 2 0 II Sending data to Target It is important to have a little background on how the two DSPs that are in the target Sbc6713e communicate Basically there is a piece of logic in between the two DSPs we called it the LAN FPGA The function of this FPGA is to serve as a data FIFO between the two DSPs So whenever the Host PC wishes to send data to the C6713 it will first be processed by the DM642 and then it will be moved to the FIFO the FIFO is only 256 words deep so the DM642 CoProcessor will wait until the C6713 reads the contents of the FIFO If the C6713 does not read data from the FIFO i e because its application code does not do so then the DM642 will block on this Send and thus will not be able to process more data on such socket number The DM642 software architecture is Multi threaded so other aspects of its software will still run The same process happens when the C6713 wants to send data to the Host PC if the host PC does not reads it then the C6713 eventually will block on a Send Another important aspect if you choose to use Malibu it is important that before closing your application you send a notification to the C6713 that you are closing and that you expect your last command back this way if you have a pending Receive on a Thread you created your threa
122. ctly Thank you from Innovative Integration 1 805 578 4260 www innovative dsp com Shutdown Now Shutdown Later Figure 6 Installation complete Click the Shutdown Now button to shut down your computer Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section Hardware Installation Hardware Installation Now that the software components of the Development Package have been installed the next step is to configure and install your hardware Detailed instructions on board installation are given in the Hardware Installation chapter following this chapter IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even permanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the specific hardware information for airflow requirements Sbc6713e User s Manual 20 After Power up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compliant allowing Windows to detect them and auto configure at start up Under rare circumstances Windows will fai
123. d receive will be satisfied with this last command and thus your application will close normally References on the following explanation can be found in NetTransferThread_Mb cpp and Sbc6713e Mb cpp This is the only method available to send information any kind to the Target TMS320C6713 DSP All other data is processed by the Target DM642 CoProcessor The procedure is as follows 1 Host computer opens port number 1008 This includes configuring the correct type of address INET creating a Connector object and creating a Stream object This is a TCP IP connection oriented protocol 2 Inthe Malibu libraries we create a Thread object that will Wait for application code to request a data packet or command packet to be sent if there is no data to send and 45 seconds have elapsed the Host sends a close command and waits for an ACK sent by Target If you are writing your own library you may or may not send this packet to the target DSP this close command will be processed by the DM642 and will not reach the C6713 DSP Close packet sent from Host to Target int ClosePacket 5 Sbc6713e User s Manual 72 ClosePacket 0 xcClose ClosePacket 1 0 ClosePacket 2 0 ClosePacket 3 0 ClosePacket 4 0 ACK packet sent from target to host If the DM642 is on a waiting for the C6713 to read pending data int buf 3 buf 0 xcClose buf 1 0 buf 2 0 3 Now the real p
124. d method The Commandld must be a number less than 49152 0xC000 a Commandld with a higher number will conflict with IDs reserved for the system There is one method used to receive data This method makes use multitasking BIOS routines Transfer Recv RecvType amp which Buffer amp Buffer When the above function returns a command or a message packet may have been received The call set the which parameter with the type that did arrive command or packet Commands are a four word block with several fields To simplify the Sbc6713e User s Manual 66 interpretation of this command the TransferPacketHeader class can be used to isolate the fields of the message In the code below the Hdr is a transfer packet header The data is loaded into it from the buffer Buf and the data fields extracted for use here by the print function Hdr LoadFrom Buf printf Cmd 3d d d d n Hdr Type Hdr ArgO Hdr Argl Hdr Arg2 The following piece of code illustrates the three Transfer methods used to communicate with the Host PC class MsgRecvThread Thread priority public Methods void Execute while Terminated Transfer Xfer IntBuffer Buf TransferPacketHeader Hdr new NullTHLIntf amp Hdr Transfer RecvType which Xfr Recv which Buf Wait for message to arrive from host Will block thread until a good message is received received if which Transfer rtCommand
125. d completion notification via either an interrupt or a polling function Because the system state is saved in the object transfers can be predefined and saved to be posted at a later time An additional feature of EDMA is the ability to build complicated transfers by linking EDMA transfer blocks or by chaining EDMA transfers together For more information on EDMA see the TI Peripheral Guide As with all DMA objects the Edma object uses one or more internal DmaSettings object to define the transfer One block is allocated for the primary transfer and one for each linked block The Settings method provides access to the primary transfer block s settings object The LinkSettings similarly allows to one of the link blocks s DmaSettings object Each of these can be used to call DmaSetting s own configuration functions or configurations can be loaded from a second object with the Load method Ed is a Edma object here we change the destination address Ed Settings DestinationAddr int dest_array 0x10 The EDMA transfer can be attached to one of a number of channels To attach an EDMA to a hardware interrupt use the channel with the same number as the hardware interrupt For example to attach an EDMA to external interrupt 4 use the EDMA channel 4 For EDMA before a transfer can be initiated the parameters are loaded into the EDMA PRAM registers This is performed by the Submit method which loads the PRAM with the transfer in
126. d in the online help with the description of each module Interrupt Handling In DSP BIOS all hardware interrupts are intended to be managed by a DSP BIOS hardware manager This manager allows user functions to be called as part of the interrupt process while still cooperating with DSP BIOS As a part of the configuration process the user can direct the HWI manager to call a user function Interrupts in a C Environment In a system using C this means of attaching interrupts leads to several difficulties A minor problem is that of name mangling C creates a new name for every function created in order to allow overloaded functions The DSP BIOS configuration does not understand the new name and results in a linker error There is a simple work around for this extern CT void MyHandlerFunction void arg Sbc6713e User s Manual 52 This declares to the compiler to create a standard C symbol name for this function MyHandlerFunction which can be used by to the DSP BIOS configuration tool A more fundamental problem is that this mechanism does not allow the interrupt handling function to be changed during the life of the program Also this handler function may not be a class member function This restriction can make designing a class object that handles interrupts awkward The Pismo Solution The solution implemented in the Pismo environment is to take over all interrupt handling by providing a full set of standard
127. de process do not turn the power off on the card nor do a hardware reset Reason The new firmware will configure new EMIF values and if for some reason you end up with a pair of Loader Talker that are not configuring the same EMIF values the card will not boot In this document when making reference to Talker and or Client they both refer to the same program 1 Changes to Loader program The Loader program is in charge of the initial boot up this program also sets the correct values of EMIF registers for the DM642 It is very important that both Loader and Client programs are in sync i e they both get updated on this release Below are two ways you can upgrade the client progem Option 1 Upgrade running ReLoader out 43 Open CCS r for CPU 2 this is the Coprocessor DSP 44 Do Debug Reset CPU Do GELNI Function Initialize Target Execute 45 Load C Innovative Sbc67 13e Coprocessor ReLoader out and run it until it displays Done in the stdout window of CCS r Option 2 Upgrade Loader using FlashBurn applet Sbc6713e User s Manual 38 1 Open FlashBurn exe applet type the IP address of your card in the UID box click on Connect button Since you probably have an old version of the Talker program the Connect button will not turn green but will stay red 2 After six seconds all download buttons will become enabled Select Dwld Loader tab Now you are in the area that downloads the Loader bin file Clic
128. design application specific modules to use with SBC6713e The Omnibus slots are accessed as memory mapped peripherals with the SBC6713e providing four decoded chip select signals per slot for a total of eight on SBC6713e Please refer to table 15 for SBC6713e I O bus memory mapping Each module site provides 32 bit wide data bus connection to the processor s data bus with 12 bit of low order address signals for additional decoding Omnibus accesses are synchronous to a single clock MOD_CLK and start and stop on the falling edges of that clock All accesses are defined by activity on the IOMOD_ n x decoded chip select signals As we can see in figure 23 an access is active when one of the IOMOD n x signals is low The bus is completely inactive when all IOMOD n x signals to all available omnibus sites are high The minimum bus access length is two clocks and there is a one clock dwell time between accesses The IORDY n x active low ready is generated by Omnibus modules which are responsible to terminate bus accesses to their respective memory mapped areas This allows each module to individually determine timing for bus accesses to the memory space in which it is installed MOD RW is read and write signal where read is active high and write is active low For more information about Omnibus Modules please go to www innovative dsp com Support Application Notes OMNIBUS Modules Or http www innovative dsp com support appnotes htm
129. e Composer Setup utility Cpu specifies the identifier of the specific DSP to be used in RtdxTerminal stdio communications This combo box is populated with all available CPUs present on the baseboard as configured using the Code Composer Setup utility Terminal Emulator Command Line Switches The terminal emulator also provides the following command line switches to further modify program behavior The switches must be supplied via the command line or within Windows shortcut properties see the Installation section for more information and will override the default behavior of the applet Multiple instances of the terminal emulator may be invoked simultaneously in order to support installations utilizing multiple target boards Instances of the terminal emulator after the first loaded instance must be configured via command line switches in order to properly communicate with their associated target board boardtype Use the board switch to force an instance of the terminal emulator to communicate with a specific type of target board boardtype Supported board types are those configured using the Code Composer Setup utility such as C64xx Rev 1 1 XDS560 Emulator Sbc6713e User s Manual 29 cpu cputype Use the cpu switch to force an instance of the terminal emulator to communicate with a specific CPU on a target board Supported CPU types are those configured using the Code Composer Setup utility such as CPU 1 or CPU A
130. eLogic300 Sbc67 1 3intf300 exo for a 300e unit Click on Download INTF Logic button Once the Please wait message is not displayed the DM642 coprocessor would have finished downloading the image Here there is no reason to see Bad burn checksum since your Talker program is now the latest To download the LAN image switch to Dwld LAN Logic tab Browse to C Innovative Sbc6713e ReLanLogic Sbc6713LAN exo Click on Download LAN Logic button Once the Please wait message is not displayed the DM642 coprocessor would have finished downloading the image Here there is no reason to see Bad burn checksum since your Talker program is now the latest You are done There are more features on FlashBurn exe Please take a moment to read the section on applets of this manual Thank you for choosing Innovative Integration products Sbc6713e User s Manual 40 About the Baseboard Single Board Computer Hardware Features The SBC6713e baseboard features a TMS320C6713 digital signal processor with 32 Mbytes of SDRAM memory To complement this core one or two modular Omnibus I O modules may installed into the onboard I O sites A wide variety of I O modules are available to address myriad application requirements The combined baseboard module system serves a variety of applications including servo applications data acquisition stimulus response measurements and many others The tight coupling of the DSP
131. ed addressing of the board Flash Image Burner Connect Flash Image Burner 2 0 Client firmware version INTF firmware version LAN firmware version Network Settings Dwld Loader Dwid Client Dwld LAN Logic Dwid INTF Logic Dwld Application WARNING Downloading a faulty loader will cause system boot problems Loader bin El al Sbc6713e User s Manual 32 Usage FlashBurn exe is composed of a main window and six tab windows Flash Image Burner The main window is located at the upper half of the Baseboard UID application s GUI Its purposes are Tenes pp pup XL AME 3 e A A Flash Image Burner 2 0 e To establish a communication with the Sbc6713e a i card Client firmware version 2 2 INTF firmware version 4 0 500E e Display firmware versions LAN firmware version C Display progress bar when downloading a program Display error messages Connect button Use the Connect button to establish communications with your target board In order to establish communications you must first enter the IP address of the Sbc6713e with which communications is to be established into the Baseboard UID combo box Use the Sbc6713eFinder applet to discover the IP address if necessary If you have an earlier version of the coprocessor DM642 client program i e before version 2 2 the connect button will remain red and after six seconds all download buttons tab windows w
132. ed header Number of Connections 10 Mating Connector AMP 746285 1 The following table gives the pin numbers and functions for the JP3 connector Table 23 Asynchronous Serial Port Connector Go mex meets 0 s emms o fo pemo mw R5232 TXD RS232 RxD RS232 CTS RETA JP12 Power Test Connector Rev C 1 3 5 T 9 E HEADER5X2 Sbc6713e User s Manual 200 JP25 Xilinx JTAG Connector i e XC2Sx00E FG456 Rev C 2x7 14 position 2MM Connector Model Part No 87832 1420 Please visit www xilinx com for more information regarding making a cable for Xilinx JTAG or it can be purchased from Xilinx The following table gives the pin numbers and functions for the JP25 connector Table 24 Xilinx JTAG Connector for XC2S600E FG456 5 weserk S memme 1 3 CN 1K RP103B RP103C RP103D HEADER2X7_2MM Sbc6713e User s Manual 201 JP21 Xilinx JTAG Connector i e XC2S50E TQ144 Rev C Connector Types Shrouded header Number of Connections 20 The following table gives the pin numbers and functions for the JP25 connector For more information regarding the cable please visit www xilinx com Table 25 Xilinx JTAG Connector for XC2S50E TQ144 e ICO o 5 awsmmi 5 awsmiws 0 s uexsmik CA PHY TRST LAN SP2 TCK lt IDC20VM DGND Sbc6713e User s Manual 202 Board Layout Rev B
133. eee eene nennen nnne nennen nnne 86 Edit Compile Test Cycle using Code Composer Studio essere enne 87 Automatic projectfile Creation eiae eee tereti OR HR e e d d e d rti ree edet ip ce eT 87 Rebuilding a Project ertet me eter eee eee d RR HA RU Ee E e e iC ERU 87 IIMain replaces main dede eerte eee ie er etri toners dtes i e i ve 87 Running the Target Exec table 2 desee ve edet e e Hes n detti ied e te d e ET 87 Notez ome mierda e bo i aves caste eig e eem e oed rie E eripiet ue es 88 Anatomy of a Target Program e a da ie dea 88 UseofdTabr ry Code eo nueces rte ee nete eei eiut men teer torem eer A E edd 89 Example Programs See ee A eae med urere uS aeta e 89 The Next Step Developing Custom Code ssssssseseeseeeeeee ener n nennen enne 90 Developing Host ADppHBCatlOlls ie seno cet ivo qune Deae pur ky Ve tuna pL eEx SS xMe e ety e Ee ux ean Ue sen As qux Id TeVdpeUpM eo aes au LO Borlarnd Tu rbo C C eiie De e rd ld e Ae eaae ehe ie e re c e ER 15 Microsoft Visual Studio 2005 23 x nas icti a anak Sealed i eta ena cg 17 O REN D Common Applets 2 no aos 20 Registration Utility NewUser exe ssesessesesseseeeeeeeenenn ennemi tree nn enne nne nnne nnne terere rentre rere enne 20 Reserve Memory Applet ReserveMemDsp exe cccccescescesssessesseeseeeseceecesecceeseeesecseseseeseceseeseeeseeaeeeseceeeeneeeneeeensatees 22 Data Analysis Applets ede tete reb te esee d
134. el Sbc6713e User s Manual 25 typically C Innovative BoardName and select Il6x gel Click OK xi Property Value C Mlnnovative SBCB713eMII6x L N A Master Slave Change property value as necessary in the right column Summary Cancel 27 Click Save amp Quit to save the configuration and exit the setup tool You will then be prompted to launch Code Composer Studio Note For multi target boards such as the Quadia one processor should be added for each device in the JTAG scan path Note The SBC6713e has 2 DSPs a C6713 and a DM642 Typically the DM642 should be set to BYPASS by selecting BYPASS from the Available Emulator Types control within the setup utility and drag it into the System Configuration control Once this is done the following screen will be presented Set the Number of bits in the instruction register to 38 and click OK Bypass Setup 21x Bypass BYPASS Number of bits in the instruction register 38 H If you encounter difficulty launching CCS 28 Run the JtagDiag exe utility Start All Programs Innovative Common Applets JTAG Diagnostics to reset the debugger interface 29 Run the board Downloader utility Start All Programs Innovative lt Board Name gt lt Applets gt Open the Downloader Folder and double click Downloader exe and press the Boot button Light Bulb icon to boot a defau
135. er Timer0 Enable false Turn on the clock at 5 hz DspClock Tclk0 50 0 150 0 Timer0 Enable true In the example TimerBinder is an object that collects the handler function OnTimerFired and its argument 0 This object 1s passed into an Irq object associated with the TCLKO interrupt When the timer interrupt fires the handler will be called with its argument The binder is a template allowing any type of argument to be used with an interrupt handler Sbc6713e User s Manual 53 Class Irq Class Irq is an object that can be created to manage a specific interrupt It has functions to set clear enable and disable the interrupt and also allows a handler to be installed that will be called whenever the interrupt fires In the above code see how all functions involving the interrupt were encapsulated in the methods of the Timer0 class object Interrupt Lock Classes A common need in a program is the ability to disable a particular interrupt or all interrupts in a portion of the program The standard means of standalone functions an disable followed by a enable interrupts has a few problems The first is that the means does not nest well If a function blocking interrupts 1s nested in a second one interrupts will be re enabled at the wrong time A second is that if the function has multiple return paths each must have the re enable code in it The introduction of C exceptions makes this problem even worse The
136. extend it to serve the exact needs of the particular job Since each of the example programs illustrates a basic data acquisition or DSP task integrated into the target hardware it should be fairly straightforward to find an example which roughly approximates the basic operation of the application It is recommended that you familiarize yourself with the sample programs provided The sample programs will provide a skeleton for the fully custom application and ease a lot of the target integration work by providing hooks into the peripheral libraries and devices themselves Sbc6713e User s Manual 90 Developing Host Applications Developing an application will more than likely involve using an integrated development environment IDE also known as an integrated design environment or an integrated debugging environment This is a type of computer software that assists computer programmers in developing software The following sections will aid in the initial set up of these applications in describing what needs to be set in Project Options or Project Properties Borland Turbo C BCB10 Borland Turbo C Project Settings When creating a new application with File New VCL Forms Application C Builder Change the Project Options for the Compiler Project Options Compiler bcc32 C Compatibility Check zero length empty base class Ve Check zero length empty class member functions Vx In our example Host Applicatio
137. f reset 1 then dsp data out others 0 elsif rising edge e clk then if ce2 n 0 then dsp data out fpdp rx do else dsp data out async data end if end if end process Notice that the data 1s selected simply on the basis of the registered EMIF B CE2 signal Decoding for the read data 1s thus fast and simple As a last step the data is enabled to drive the data bus for the reads This is done using a simple tri state output buffer OBUFT ed i lt dsp data out i when dsp data oe n 0 0 else Z The output enable signal is a decode of the registered control signals dsp data oe n i lt 0 when aoe select 1 else 1 Figure 19 Data Mux This DSP read interface has been successfully used in the Framework Logic to provide data to the DSP at burst rates using a 75 MHz EMIF clock The pipelined nature of the code allows the FPGA to meet timing and reduces many timing issues encountered because of the complex nature of the readback mechanism The latency for the Framework Logic is X cycles as set in the EMIF control registers DSP EMIF Write Interface In general writes are much easier than reads because we can pipeline the control signals and data to reduce the timing problems In the Framework logic the incoming data is immediately registered in the IOB pins to catch the data a Incoming DSP Data process reset e clk cel n q ce3 n begin if reset 1 then pdo l
138. formation Unlike QDMA this does not start the transfer itself The transfer will be initiated when the associated hardware interrupt occurs If using software triggering use the Set function to initiate a transfer One Set call is required for each link block in the transfer Each Edma transfer allocates blocks from the PRAM pool to configure its Link blocks These blocks are a limited resource and the allocation may fail If the failure occurs the IsValid function will return false If a terminal count interrupt is not used a call for WaitForComplete will delay until the completion occurs TestComplete will return a flag that can be used to check completion without blocking Sbc6713e User s Manual 58 Edma transfers may be configured to generate Terminal Count interrupts on completion of any and all blocks in the transfer Which TC bit is signaled is configured in each settings block This means there can be different handlers for different blocks in the transfer A user supplied handler similar to an interrupt handler can be associated with the terminal count interrupt by a call to the TeIntInstall or LinkTcIntInstall method The Link function is used to install a handler for one of the link blocks as opposed to the primary block The DMA system shares a single interrupt for all TC interrupts and the system will call the installed handler when the particular bit in the TC register becomes set The handler installer require
139. h a text editing program like Notepad 3 Edit the new mk file as follows e Change the OUTPUT and OUTPUT BASE to the desired output name for the bin file For example to convert yourfile out to yourfile bin edit this template file in the following manner OUTPUT yourfile out OUTPUT BASE yourfile e You must also be sure that the application cmd and the hex2bin files are found by the new convertyourfile To do this 1 Change the HEX ARGS to point the where the application cmd file is ie if you have copied this file to the examples target directory then you must change HEX ARGS application cmd Sbc6713e User s Manual 171 2 Similarly you must point to the location of the hex2bin file in the HEX2BIN variable e Then save the changes and close the editing program Note It is always a good idea to remove or rename any old bin file of the same name to ensure a new bin file is created 4 Opena DOS prompt and CD to the directory where the yourfile out and the Convertyourfile mk files reside Type nmake f yourfile mk and press Enter This will create the yourfile bin in the same directory baseboard67 and baseboard6711 Targets Run the supplied applet PromImage exe Browse to your application out file then click the Make button to generate the image file The auto generated image file will have the same name as the input out file but will be named with the bin extension This file is suitable for em
140. hat will be your SBC6713e application logic It is suggested that you begin by simply recompiling this logic and verifying that you can recreate the framework logic as delivered see steps above This will verify that you have all the libraries and FPGA compilation tools required to move ahead on your design Once you have successfully recompiled the logic it is now possible to begin adding and replacing the simple logic with your application code This is done by modifying the top VHDL to include your sub functions then modifying the test bench code to adequately stimulate your design Innovative Integration strongly recommends that you fully simulate your design before putting this logic into the SBC6713e Spartan Ile 300K or 600K FPGA This will not only save time in debugging but could also prevent simple errors from causing serious damage to the module A tool like ModelSim is generally required for this high density complex logic design that give full visibility into the logic behavior prior to actual synthesis Many pre written logic functions are available to assist in logic development from Xilinx and other vendors These logic functions may be viewed at the Xilinx web site http www xilinx com ipcenter index htm These logic functions include basic math filters FFTs and other functions that are useful in logic designing with the Xilinx Spartan Ile FPGAs Logic Design Methods and Code Development DSP Interface Logic The S
141. hd Logic Cores FPDP DLL Framework fpdp dll vhd VHDL File Counters Constraints counters vhd Fitting Results for the Framework Logic The Framework logic consumes about 21 of the logic for the Spartan Ie 600K device The results of the mapping process as taken from the sbc6713_top mrp report are as shown Notice the memory consumed during the compile is 123MB for this design Sbc6713e User s Manual Design Summary Number of errors 0 Number of warnings 13 Logic Utilization Total Number Slice Registers 2 942 out of 13 824 21 Number used as Flip Flops 2 939 Number used as Latches 3 Number of 4 input LUTs 3 166 out of 13 824 22 Logic Distribution Number of occupied Slices 2 655 out of 6 912 38 Number of Slices containing only related logic 2 655 out of 2 655 100 Number of Slices containing unrelated logic 0 out of 2 655 0 See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs 3 435 out of 13 824 24 Number used as logic 3 166 Number used as a route thru 17d Number used as Shift registers 98 Number of bonded IOBs 312 out of 325 96 IOB Flip Flops 170 IOB Latches 18 Number of Block RAMs 12 out of 72 16 Number of GCLKs 4 out of 4 100 Number of GCLKIOBs 2 out of 4 50 Number of DLLs 2 out of 4 50 Number of BSCANs 1 out of 1 100 Number of RPM macros 2 Total equivalent gate count for design 271 664 Additional
142. he OS is 64 bit or 32 bit and runs the appropriate installation for each environment It is important that this script be run to launch an install When installing on a Vista OS the dialog below may pop up In each case select Install this driver software anyway to continue gt Don t install this driver software You should check your manufacturer s website for updated driver software for your device Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information v See details Figure 1 Vista Verificaton Dialog Sbc6713e User s Manual 16 The Installer Program After launching Setup you will be presented with the following screen Please select a product to install ITE ET rue U C Innovative 3 Change Components to Install for Quadia Quadia Applets examples Docs and Pismo libraries Malibu Host libraries utilites Docs drivers amp DLLs Bin View Data graphing and analysis tool CodeHammer JTAG support for Code Composer Studio Innovative Components C Builder Support Product Registration ONE TENE Using this interface specify which product to install and where on your system to install it Figure 2 Innovative Install Program 1 Select the appropriate product from the Product Menu 2 Specify the path where the development package files are
143. he Qdma object uses an internal DmaSettings object to define the transfer The Settings method provides access to the object to allow calling the DmaSettings classes own configuration functions or configurations can be loaded from a second object with the Load method Q is a Qdma object here we change the destination address Q Settings DestinationAddr int dest array 0x10 For QDMA a transfer is initiated when the parameters are loaded into the QDMA registers This is performed by the Submit method which starts the preconfigured transaction or loads the passed in configuration and submits it Only one Qdma transfer may be active in the system at one time Multi threaded applications must arbitrate Qdmas as appropriate If a terminal count interrupt is not used a call for WaitForComplete will delay until the completion occurs TestComplete will return a flag that can be used to check completion without blocking Qdma transfers may be configured to generate Terminal Count interrupts on completion of the transfer Which TC bit is signaled is configured in the settings block A user supplied handler similar to an interrupt handler can be associated with the terminal count interrupt by a call to the TeIntInstall method The DMA system shares a single interrupt for all TC interrupts and the system will call the installed handler when the particular bit in the TC register becomes set The handler installer requires an Interrup
144. her on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance responsible solely for real time tasks Much the same as a dedicated video subsystem is required for adequate display performance dedicated hardware for real time data collection and signal processing is needed This is precisely the focus of our baseboards a high performance state of the art dedicated digital signal processor coupled with real time data I O capable of flowing data via a 64 bit PCI bus interface The hardware is really only half the story The other half is the Malibu software tool set which uses state of the art software techniques to bring our baseboards to life in the Windows environment These software tools allow you to create applications for your baseboard that encompass the whole job from high speed data acquisition to the user interface Finding detailed information on Malibu Information on Malibu is available in a variety of forms e Data Sheet http www innovative dsp com products malibu htm e On line Help Sbc6713e User s Manual 12 Innovative Integration Technical Support nnovative Integration Web Site www innovative dsp com Online Help Help for Malibu is provided in a single file Malibu chm which is installed in the Innovative Documentation folder during the default installation It provides de
145. hold int r level out fpdp fifo threshold int active lev gt vcc burst len rx fifo burst Sbc6713e User s Manual OUT std logic VECTOR 31 downto 0 50 new_len gt fpdp rdfifo control wr tp gt open Figure 23 Using the FIFO Interrupt Filter This filter component takes in the threshold level interrupt as fpdp fifo threshold int r and asserts it until the a burst length is read from the FIFO The interrupt given to the DSP DMA controller is fpdp fifo threshold int A counter in the code counts to the burst length using the ad fifo rd signal Decoding for the FPDP Rx read FIFO accesses is a simple register that is true when CE2 and AOE are true and when DSP address 21 is not selected dsp ce2 burst rd lt 1 when aoe_n 0 and dsp addr 21 0 and ce2 n 0 else 0 dsp ce2 burst wr lt 1 when ce2n q 0 and awe n q 0 0 and dsp addr q 21 0 else cor Figure 24 DSP Burst Read and Writes Digital IO from the Spartan ITE There are 32 bits of digital IO from the Spartan IIE to the IDC50 connector These are configured as a simple LVTTL register with software programmed direction on a nibble basis in the Framework logic A number of logic standards can be programmed into the Spartan for high speed use such as LVDS and low voltage TTL as constrained by the Spartan HE chip pins These pins are 5V compatible Protection devices on each pin limit the voltage to 5V or
146. ill be enabled This happens because earlier client programs did not support two communication sockets added starting with version 2 2 Despite this behavior this tool is still useful when used in conjunction with the earlier client versions Once you update your board to v2 2 of the client program FlashBurn exe will be able to display the revision of the firmware components in the Sbc6713e card Below is a screen shot of how it looks when connected to a Sbc6713e with Client version 2 2 Sbc6713e User s Manual 33 Network Settings tab On Network Settings tab you may choose to use static IP settings or use DHCP protocol where your IP sever will assign an IP address to the SBC6713e card To enable use of a static IP address enable the Static IP checkbox fill in the static IP information located in the Settings group box then press the Update IP settings to ROM button You may switch between the two at any time Once you update close FlashBurn exe application and re open to establish communications with the card again i e it has new IP address If your board has Client program 2 2 or later and you have run the RtdxTerminal program FlashLoad out on the DM642 DSP the network co processor you may follow the following procedure to find your board s IP address On a DOS prompt window simply ping sbc6713 Sbc6713e PCB rev Serial Number innovative dsp com So if the PCB rev is C and Serial Number is 105 then
147. ing FPGA designs call ChipScope This tool works over the FPGA JTAG port using any of the standard Xilinx JTAG cables Software on the PC connects to a ChipScope logic core that you embed in your logic This is an optional tool from Xilinx and is not included in the standard ISE software For its cost of under 1000 we have found it well worth the money Target Device Under Test Host Computer with ChipScope Pro Software User Function Board Under Test Figure 43 Chip Scope Big Picture The ChipScope core allows you to monitor internal FPGA signals that you have connected using triggers based on a set of trigger signals you have attached A master clock connection is required for the core as well In order to debug custom logic using ChipScope the user might need to burn the logic several times so we have provided a JTAG JP25 connector which is directly connected to Spartan IIe 300k 600K it helps the user to load the logic as many times as needed Sbc6713e User s Manual 166 STATUS e Xl LI NX CONNECTOR SIGNALS 0 1 inch 2mm JTAG or Serial i Vref Vref Gnd Top View Parallel CableTZ ed zes mee E Model DLC7 tek felccuk T tw ls Power 5V 0 2A woh pone tex ce oa Serial JG 12345 Tol DIN Ws PROG iz Made in USA CE TMS PROG Grd
148. insure that the DTR output from the PC is de asserted since it controls target reset Further insure that the baseboard s CTS serial input line is de asserted since the Talker Sbc6713e User s Manual 178 The application works properly from within Code Composer Studio but does not run or is erratic when embedded Sbc6713e User s Manual asserted during cold boot On the baseboard62 insure that the boot jumper JP24 is installed You burned the application at an incorrect offset or starting at a sector other than 1 The application burn image was created improperly Inspect the A0 file and insure that the target image has an appropriate boot record Be sure to convert the AO file into binary using the Options dialog for consumption by the Burn applet On the baseboard62 and baseboard54 targets be sure to locate the const and cinit sections into the ROM so that they may be resurrected at boot time The Target may still be held by the JTAG Run the JTAG Diagnostic utility and then select the lt Reset gt button to release the target The bss section of your application is not automatically initialized to zero Modify your linker command file to zero fill the bss section Your embedded application may be too large Use the Coff Dump utility to inspect the size of the OUT file to verify that it can fit into the seven residual 16 kByte sectors in the AMD 29F010 64 kByte sectors in the F040 179 OLED Disp
149. ion protocol implementation client send n MyDataBuff sizeof MyDataBuff amp timeout The previous method will return 1 if the send method timed out Sending a command from host to target or target to host does not require to send a header packet prior to sending the command we will talk about header packets later in this section A Command packet 1s composed of five 32 bit words A command packet has the following structure Packet 0 xcSendCommand Packet type Packet 1 CommandId Command ID Packet 2 Arg0 User defined arguments Packet 3 Argl Packet 4 Arg2 enum XfrCmdTypes xcSend 0xBO xcSendCommand xcSendData xcClose xcSendDataData Sbc6713e User s Manual 64 After Host has sent the command packet it will post a receive with the following ACE SOCK Stream method int ackBuff 3 client recv n ackBuff sizeof ackBuff amp timeout Acknowledgment packets are Three 32 bit words This 1s the information one should expect from the Target side ackBuff 0 CommStatus see Sbc6713e Mb h for these codes ackBuff 1 count number of previously received bytes ackBuff 2 count number of previously received bytes When Host received the command acknowledgment command transfer is understood to be completed Note Even though the command sent from Host to Target DSP is five 32 bit words the buffer containing the command that is sent from the Co Processor to the Target DSP is only Fou
150. ional Library Directories Innovative Lib Vc8 If anything appears to be missing view any of the example sample code Vc8 projects Summary Developing Host and target applications utilizing Innovative DSP products is straightforward when armed with the appropriate development tools and information Sbc6713e User s Manual Applets The software release for a baseboard contains programs in addition to the example projects These are collectively called applets They provide a variety of services ranging from post analysis of acquired data to loading programs and logic to a full replacement host user interface The applets provided with this release are described in this chapter Shortcuts to these utilities are installed in Windows by the installation To invoke any of these utilities go to the Start Menu Programs lt lt Baseboard Name gt gt and double click the shortcut for the program you are interested in running Sbc6713e User s Manual 19 Common Applets Registration Utility NewUser exe Some of the Host applets provided in the Developers Package are keyed to allow Innovative to obtain end user contact information These utilities allow unrestricted use during a 20 day trial period after which you are required to register your package with Innovative After the trial period operation will be disallowed until the unlock code provided as part of the registration is entered into the applet After using the Ne
151. ity to create a viable binary image before attempting to burn an application into Flash ROM Example embed able projects for each II single board target are available on the Innovative web site at www innovative dsp com Controlling Region of Erasure Adjust the Start Sector and End Sector combo boxes within the Start and End group boxes to control the location within the target flash in which the image is to be placed Note that this controls only the range of sectors erased prior to attempting to burn the application into Flash Sbc6713e User s Manual 175 The number of sectors actually needed is determined by the size of the binary image file The BURN applet performs a range check to insure that your image will actually fit into the erased sectors You must be sure to erase a sufficient number of sectors to contain your entire application image Re burning the Talker Image To burn or re burn the factory Talker image select 0 as both the starting and ending Sector On all targets except C32 based targets select 0 as the Offset On C32 targets the Offset should be set to 0x1000 Warning Avoid burning application code other than the factory Talker image into sector zero On some targets notably the baseboard62 it may be impossible to initialize the JTAG debugger on a target board containing an invalid boot image This situation can only be corrected by shipping the target DSP back to the factory for rework Burning a User Written Appli
152. k on the browse button and go to C Innovative Sbc6713e Coprocessor Loader bin 3 Click on Download Loader button Once the Please wait message is not displayed the DM642 coprocessor would have finished downloading the Loader You may see a message displaying Bad burn checksum since your Talker program is not the latest this message can be ignored 2 Changes to the Coprocessor Talker a k a Client Several minor bug fixes and feature additions have been implemented in the coprocessor Talker code Below are two ways you can upgrade the Talker program Coprocessor firmware Option 1 Upgrade running ReTalker out 1 Open CCS r for CPU_2 this is the Coprocessor DSP 2 Do Debug Reset CPU Do GELMI Function nitialize Target Execute 3 Load C Innovative Sbc6713e Coprocessor ReTalker out and run it until it displays Done in the stdout window of CCS r Option 2 Upgrade using FlashBurn applet 1 Open FlashBurn exe applet type the IP address of your card in the UID box click on Connect button Since you probably have an old version of the Talker program the Connect button will not turn green but will stay red 2 After six seconds all download buttons will become enabled Select Dwld Client tab Now you are in the area that downloads the Client bin file Click on the browse button and go to C Innovative Sbc6713e Coprocessor Client bin 3 Click on Download Client button Once
153. l to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section Sbc6713e User s Manual 21 JTAG Hardware Installation JTAG Emulator Hardware Installation for DSP boards Only First the emulator hardware must be configured and installed into your PC The emulator hardware is described in the table below Pod based Uses a special ribbon cable with integrated line drivers to connect the target DSP emulation signals to the JTAG debugger card Usable on 3 3 volt or 5 volt designs Including C54x and C6x PCI Pod Based Emulator Installation To install the PCI pod based emulator follow the instructions below 5 Perform the board installation in an ESD or static safe workstation employing a static dissipative bench mat Wear a properly grounded wrist strap or other personal anti static device Stand on an anti static mat or a static dissipative surface 6 Shut down Windows power off the host system and unplug the power cord 7 Touch the chassis of the host computer system to dissipate any static charge 8 Remove the card from its protective static safe shipping container being careful to handle the card only by the edges 9 Touch the chassis of the PC to dissipate any built up static charge 10 Securely install the JTAG board in an available PCI slot in the host computer 11 Connect the JTAG pod to the host pod cable Connect the host
154. lay Adapter Description This assembly provides an interface from a TI McBSP to an OSRAM Pictiva OLED graphic display using a Solomon SSD0323 display controller This adapter supports OSRAM displays OS128064 that are 128 by 64 pixels An optional power supply on the adapter board may be used with displays assemblies that do not have a built in display power supply This adapter is for use with a serial data interface and a navigation switch assembly The display adapter translates serial data from the DSP McBSP port into serial data and commands for the display and adapter Read back of the 5 buttons used for navigation includes debounced switch event data to the DSP via an serial word transmitted back to the DSP Interface Logic Display Controls Power Supply Transmit Serial port interface OSRAM Display f Button Navigation Receive interface Buttons Sbc6713e User s Manual 180 Button Interface The display adapter supports a navigation button assembly that has five switches integrated into a single button assembly The five buttons UP DOWN RIGHT LEFT SELECT are integrated into a joystick like button assembly with a single keycap that swivels and depresses The switch is ITT Cannon TPA The buttons are debounced by sampling the button position with a clock equal to the DSP McBSP clock divided by 2 13 For a 3 MHz clock this is about a 2 7 mS sample period The switch must be sampled 16 consecutive times at 1
155. lication It should compile and link without errors 85 Writing a Program The basic program given in the example above includes a Main function 11Main DSP BIOS the OS used in the Pismo library uses code inserted after exiting from the normal C language main to initialize features of DSP BIOS This means that some language features are not available then To avoid these problems the Pismo library provides a main function and uses it to create a single thread This thread when executed calls the IIMain function Inside of this thread all DSP BIOS is initialized and ready for use It is required that the user include this function and use it as the equivalent of the old main process function in C Host Tools for Target Application Development The Innovative Integration Pismo Toolset allows users of Innovative DSP processor boards to develop complete executable applications suitable for use on the target platform The environment suite consists of the TI Optimizing C Compiler Assembler and Linker the Code Composer debugger and code authoring environment as well as Innovative s custom Windows applets such as the terminal emulator Code Composer Studio is the package used to automate executable build operations within Innovative s Pismo Toolsets simplifying the edit compile test cycle Source is edited compiled and built within Code Composer Studio then downloaded to the target and tested within either the
156. list MEA AAA ide Sbc6713e User s Manual Target Project Copy Utility CopyCcsProject exe The CopyCcsProject exe applet is used to copy all project settings from a known good template project into a new DSP Code Composer project This simplifies new project development by eliminating the multi step process of copying the myriad individual project settings from a source project in a newly created project Source Project Destination Project Directory C Conejo Examples Scope m Destination Project Name Scope include HdwLib h include UtilLib h using namespace II void IIMain Scan Path Diagnostic Utility JtagScanpath exe The JtagScanpath exe applet is a simple GUI front end to the powerful Texas Instruments XdsProbe exe command line utility The utility is of value in debugging JTAG debugger installation and reliability problems The tool is capable of performing comprehensive scan integrity tests for both the Innovative Code Hammer and the TI XDS560 emulators The complete reference to available tests and features is listed on the application Help tab c MiNcc binNxdsprobe exe r fllPciPod cfg pO i Reset the controller This utility will load the emulator adapter lI PciPad dll This utility has selected a XD S510 class product This utility will operate on port address OsO This utility will atte
157. lt target application Sbc6713e User s Manual 26 30 Restart Code Composer Studio Sbc6713e User s Manual 27 Setting up for a single processor with Spectrum Digital USB Jtag First remove any previous setups in the CCS Setup application Add one of the USB SD type driver System Configuration SD510USB Emulator Available Connections Connection Description a Ea Other 510 Class Emul Other 510 Class Emulator Connection Processors Supported Eg Other 560 Class Emul Other 560 Class Emulator Connection TMS320F2400 Other Simulator Other Simulator Connection TMS320F 2800 EA S0510 Emulator SD510 Emulator Connection WAEEPHES ADU P TMS320C5500 3B Emulator SD510USB Emulator Connection TMS320C5400 MA SDDSKUSB Emulator SDDSKUSB Emulator Connection TMS320C6200 EATI Simulator TI Simulator Connection TMS320C6700 GTI XDS510 Emulator TI XDS510 Emulator Connection TMS320C6210 Egi TI XDS560 Emulator TI XDS560 Emulator Connection TMS320C6710 TMS320C6720 ARM11 ARM ARMS Create Board Eg Factory Boards E Custom Boards Hemove All lt lt Add Multiple Drag a device driver to the left to add a board to the system You will see the following screen Fill out the name of the board you are using this can be any name you like Connection Name amp Data File Connection Properties Connection SD510USB Emulator VERS My P25M Auto generate board
158. mage using the button Burn this image into flash using the Download Application button Finally enable the Boot embedded app checkbox and click Write setting to ROM If for some reason your application does not behave the way you expected you can always revert back to use the benign program by simply unselecting the check box and then by pressing the Write setting to ROM button Below is a screen shot of this tab window Network Settings Dwld Loader Dwld Client Dwld LAN Logic Dwld INTF Logic Dwld Application c innovative examples mpProjhapp bin Bl Boot embedded app Download Application White setting to ROM Sbc6713e User s Manual 36 Custom Logic Development Embedded data acquisitions servo control stimulus response and signal processing jobs are easily solved with the SBC6713e baseboard using the supplied Pismo software There are wide selection of peripheral devices available as plug in omnibus modules for many types of signals from DC to RF frequency applications or audio processing SBC6713e is a high performance flexible stand alone DSP board with Ethernet connectivity loaded with I O peripherals 300Mhz floating point C6713 DSP gives an open platform with several omnibus available off the shelf daughter cards with a wide choice of A D and D A and also supporting simple EMIF bus interface to custom I O daughter cards System level integration is facilitated with on board digital DDS timeba
159. mdBuf CmdBuf CmdBuf LAs 2 3 Data Packet Header int XfrPacket 5 XfrPacket 0 XfrPacket 1 XfrPacket 2 XfrPacket 3 XfrPacket 4 pkRecvPacketRequest Buf Bytes Number of bytes to follow In the next N A transaction Host must get ready to N A receive this next data N A If your Host code does not receive any data once you have requested it and supposing that nothing has gone wrong with the hardware then you may implement an application level protocol that is you send commands to the C6713 read previous section Send Data to Target to request status then using this Socket port you should receive your DSP status if you still receive no data later then either your application protocol is not implemented correctly or the hardware is in a bad state You may choose to send a reset command using the reset command port socket number to the DM642 and try to reconnect few seconds 4 Hostsends ACK packet to Target Reply 0 Reply 1 Reply 2 pkRecvRequestAck 0 0 5 If Target previously sent a Command Packet then operation ends here DM642 will close its socket if Host closed its socket Dm642 will then go into a wait state and it will stay there until Host re establishes communications Sbc6713e User s Manual 75 6 If Target had sent a Data Packet Header then Target now sends its Data Buffer to Host Ho
160. mplate This template allows the binding of a member function of a class object with the object to call and an argument of any type In this example the IsrHandler class is bound to a timer interrupt class IsrHandler Sbc6713e User s Manual 54 public IsrHandler Binder this amp IsrHandler MyHandler amp Tally Tally 0 ClassMemberHandler lt IsrHandler unsigned int gt Binder void MyHandler unsigned int tally tally 1 if tally 0x7f 0 rtdx lt lt Isr tally lt lt tally lt lt endl private Data unsigned int Tally E Instantiate a concrete instance of above class IsrHandler Isr void IIMain Dynamically create an Irq object tripped from onchip timer 0 Irq Timer0 intTimerO Bind and install the interrupt vector Timer0 Install Isr Binder Program onchip timer 0 to signal at 100 Hz Timer0 Enable false DspClock Clock 100 150 true 0 Timer0 Enable true Use RTDX event log to monitor progress rtdx Enabled true rtdx Message from within IIMain endl Go to sleep while 1 TSK yield In the above example the handler uses a int argument to pass out information from the interrupt routine Class FunctionHandler Template This template allows the binding of stand alone function with an argument of any type In this example the OnTimerFired function is bound to a timer interrupt Timer Interr
161. mpt to reset the controller This utility has successfully reset the controller Illera said ala The JTAG IR register for a AF The JTAG IR register for a cl The JTAG IR register for a lc The JTAG IR register for a CE The older TI DSP devices wit include the C4x C5x C8x Cz The newer TI DSP devices m include the VC33 C54 CB2 1 The TI DSP devices with Ice include the C27x C28 C55 2 e Ces Version lIPciPod cfg Y Use configuration file Standard Test 0 Port Address Ox5533ccaa Data Patten Scan Controller Iterations Iv Reset Scan Path Jv Scan Path Integrity Perform the scan path leng Analysis Tests Broken Path Embedded Hardware The test for the JTAG IF inst DS 580 Only The JTAG IR instruction scar ds560 out I7 Use Emulator Program The test for the JTAG DR byt Tests eeded Clock Range MHz The JTAG DR bypass scan p r Clk Selection 1 20 None Center Bounds The scan path appears to cor If the scan path consists of or Probe returned result code 0 Sbc6713e User s Manual 31 Flash Conversion Utility PromImage exe Innovative boards capable of booting from Flash ROM include a small application program called Loader which begins execution on system cold start If a valid Innovative Loader COFF image is identified in Flash ROM and if the boot jumper on the board is installed then this
162. n a newly created project a al Demangle Utility Demangle exe The Demangle applet is designed to simplify use of the TI dem6x exe x command line utility When building C applications the built in symbol CAToro Examples ASnap Debug ASnap map mangler in the TI compiler renders symbolic names unreadable such that Demangle View missing or unresolved symbol errors displayed by the linker no longer correlate to the symbol names within your code To work around this limitation enable map file generation within your CCS project Then browse to the map file produced by the linker using the Demangle utility The utility will display proper symbol names for all unresolved externals Undefined bots COFF Section Dump Utility CoffDump exe CoffDump exe parses through a user selected COFF file all x File Window stored on the hard disk and ascertains the complete Dumping C Vista Examples VEcho Debug VEcho out to file C iVistaYExamplesYiVEcho memory consumption by the DSP program Memory NDabiig Vilcho 1st DUMP completeted normally usage for each of the sections defined in the applications command file are tabularized and the results are written to the Windows NotePad scratch buffer Sbc6713e User s Manual 24 JTAG Diagnostic Utility JtagDiag exe 01 x JtagDiag exe is used to re initialized the JTAG scan path interface which connects JTAG information the Code Hammer debugger s PCI
163. n the project window click Add Files then select the the newly created Test cmd for addition to the project 83 21x Look in C3 Target z e E e Be File name HdwLib lib Files of type Object and Library Files 077 Cancel Help VA Vista CPU 1 C6711 Code Composer Studio File Edit Object View Project Debug Profiler GEL Option Tools P DSP BIOS Configuration Close Visual Linker Recipe Save Gris Activex Document Save As Save Fill 5 Test CDB Load Program Estimated Data Size 2765 Est M Load Symbol G System Add Symbol m Instrumentation TT x Save in S Test gt e er E3 Pomme etm Save as type MET Cancel include Pismo h using namespace II Application mainline void IIMain Sbc6713e User s Manual Right click on Test pjt in the project window select Add Files then browse to the Examples directory and select Examples cmd for addition to the project Add an new C source file to the project Click File New Source File to create an empty source document Rename the new source document to Test cpp To use the Pismo libraries you must use C files and the C compiler even if you intend to restrict your own coding to the C subset of C Type the boilerplate code below into your source file This is the minimum code needed for any Pismo C application 84 New Open Use External
164. namic creation and runtime control of tasks e Simplified management of and access to all TI Chip Support Library CSL and DSP BIOS API functions including Semaphores Mutexes Mailboxes Timers Edma Qdma Atoms McBsp Timebases Counters etc Foundation base classes for DMA driven device driver development e Templatized queues e Partial standard template library functionality via STLPort For example the code fragment below uses the Pismo IntBuffer class to initialize a QDMA quick DMA to perform a memory to memory move of a constant value 0 into a 4096 word buffer at Src then to copy the source buffer Src to the destination buffer Dst Create a source buffer of 0x1000 integers IIBuffer Src 0x1000 Initialize the source buffer with zeros Src Set 0 Create a destination buffer of 0x1000 integers IIBuffer Dst 0x1000 Dst Copy Src Simple To Use In the same way peripheral specific class libraries dramatically simplify access to board specific peripheral features For example the code fragment below illustrates real time processing and display of analog input signals running on the SBC6713e DSP board equipped with an Omnibus module within a separate thread of execution class LoopThread public Thread public LoopThread IIPriority priority Thread priority FCount 0 Cursor 0 Requested false int Count return FCount void Resize int size CaptureEvents size Snaps Resize size
165. nce of EdmaMaster is created at program initialization It is accessed by calling the static member function EdmaMaster Object Sbc6713e User s Manual 60 EdmaMaster contains several functions dealing with the EDMA PRAM This is a memory region shared among all EDMA objects giving a common storage for configuration blocks This is a limited resource so be wary of allocating many Edma blocks and not releasing them The method ClearPram clears all the PRAM blocks in a single operation EdmaMaster contains several functions dealing with the EDMA PRAM This is a memory region shared among all EDMA objects giving a common storage for configuration blocks This is a limited resource so be wary of allocating many Edma blocks and not releasing them Also available are functions to give access to the area at the end of the PRAM that is not used by the system This scratchpad memory might be of use as a shared memory pool in an application SBC6713e Example Programs Under Sbe6713e Examples in the install directory the baseboard s example programs are installed Some examples have no host component and some use the terminal emulator applet as the host Host examples are written in C either under Borland C Builder or Microsoft MSVC or both Target examples are written using CCS 3 x and DSP BIOS Table 12 SBC6713e Example Programs Example Host Target Illustrates AEcho terminal DSP BIOS Use of DSP BI
166. nd normal to force formatting of the text string as it is streamed to the host Termlo features many such manipulators to perform functions such as setting text color setcolor clearing to end of line Sbc6713e User s Manual 69 clreol clearing the screen cls and so forth Other manipulators are available to format numeric values as they are streamed to the host For example the phrase term lt lt Hello lt lt hex lt lt showbase lt lt 4660 lt lt dec displays the string Hello 0x1234 on the console display converting the integer value 4660 as a hexadecimal number on the target prior to streaming it to the host Other manipulators are available providing extensive control over the display of floating point numbers as well as integer values It is also frequently necessary to obtain input from an operator during the run time execution of a target application For example it may be necessary to prompt for a sample rate at which analog I O is to be streamed The code fragment below illustrates the necessary technique Prompt the user term lt lt Enter a float lt lt flush float x2 Eat user input term gt gt x2 The stream manipulator gt gt is overloaded to allow streaming directly into floating point integer and string variables directly from the terminal emulator To perform file input and output from within target applications first instantiate a TermFile object as below TermFile File
167. nd out the IP address of your Sbc6713e card simply bi pinging the Sbc s name Example in the DOS prompt type ping Sbc6713 C101 innovative dsp com this name is provided your card is a Rev C PCB and the serial number is 101 If your PC is not configured for to use DNS you make have to run an IP scan to find the IP address of your card If you chose static IP address you may ping the card using the IP address you provided 4 Changes to the Firmware Several minor bug fixes and feature additions have been implemented in the Interface and LAN FPGAs Use the FlashBurn applet and the supplied Interface and Lan logic images to update the firmware on your baseboard Below are the instructions 1 2 3 4 5 6 Open FlashBurn exe applet type the IP address of your card in the UID box click on Connect button This time Connect button should turn green unless UID box has the wrong IP address All download buttons will become enabled Select Dwld INTF Logic tab Now you are in the area that downloads the interface logic image There are two types of interface logic depending on the card you have purchased If the S N is 115 or greater then you may have a 600e logic If you have doubts as to what is loaded on your card please contact Tech Support The other kind has a 300e logic device Click on the browse button and go to C Innovative Sbc6713e ReLogic600 Sbc67 1 3intf600 exo for a 600e unit or C Innovative Sbc67 13e R
168. ndently set In addition there are far more ways of defining triggers than there are for defining parts of a timer For example the start of data flow on Omnibus modules can be based off of an external digital signal the value of the data on an input channel by software command or be automatic Pretrigger and Stop trigger options are also numerous A class that had methods for all these features would be large complex and would usually have most of its functions inoperative without giving the application any feedback Trigger configuration 1s also complicated by Module differences Even the same type of trigger can differ in on different modules For example an external start trigger may allow the condition of the input signal edge or level triggering positive or negative polarity be changed Another module might not support changing these features being always positive edge triggered Another example is that threshold triggering might be able to be triggered of any selected channel or it might be restricted to a predetermined channel The triggering configuration system uses trigger interface objects to allow configuration of the triggering modes There are four access functions Pretrigger StartTrigger StopTrigger and Retrigger giving interface objects for use Each of these objects supports none or one or any number of Trigger UI interface classes for configuration each of which can be exposed by a conversion function for the cl
169. nnections 14 Mating Connector AMP The SyncLink connector allows SBC6713e to synchronize to external hardware or other Innovative cards The following table gives the pin numbers and functions for the JP2 connector Table 19 SyncLink Connector ceWmkows Jo 1 owwmkow o0 ESOS CUT 1 ceWwkm 5 smmmspni u s Dita ETT Power s Digital gromd Power 5 smamspn vo un syne bus pind iu smambupns i5 smamkupna i JPZ SYNC5 6_100 DGND OcLOCKLINK IN N CLKLINK OUT N PLOCKURE IN P CLKLINK OUT P IDC14VM Figure 53 JP2 SyncLink Connector Pin Orientation Sbc6713e User s Manual 196 JP13 JP15 Processor Serial Port Connectors Connector Types 2 mm double row header Number of Connections 10 Mating Connector Samtec SQT style for board board applications The following table gives the pin numbers and functions for the JP15 McBSP 0 and JP13 McBSP 1 connectors Pin functions of JP15 are identical to those of JP13 except where noted Table 20 Processor Serial Port Connector s igi 33v piiisv mw O 5 pmi pwmsv ew O 5h m e 87331 1020 Figure 54 JP13 JP15 DSP Serial Port Connector
170. ns if not checked an access violation will occur when attempting to enter any event function Le Access Violation OnLoadMsg Execute Load Message Event Because of statement Board gt OnLoadMsg SetEvent this Applicationlo DoLoadMsg Change the Project Options for the Linker Project Options Linker ilink32 Linking uncheck Use Dynamic RTL In our example Host Applications if not unchecked this will cause the execution to fail before the Form is constructed Error First chance exception at xxxxxxxx Exception class EAccess Violation with message Access Violation Process exe nnnn Other considerations Project Options Compiler bcc32 Output Settings check Specify output directory for object files n release build Release debug build Debug Paths and Defines add Malibu Pre compiled headers uncheck everything Linker ilink32 Output Settings check Final output directory release build Release debug build Debug Paths and Defines ensure that Build Configuration is set to All Configurations add Lib Bcb10 change Build Configuration to Release Build add lib bcb10 release change Build Configuration to Debug Build add lib bcb10 debug change Build Configuration back to All Configurations Packages uncheck Build with runtime packages Sbc6713e User s Manual 16 Microsoft Visual Studio 2005 Microsoft Visual C 2005 version 8 Project Properties When creating a ne
171. nu Command Sbc6713e User s Manual Text in this style represents C variables Text in this style represents C identifiers such as class function or type names Text in this style indicates a key on your keyboard For example Press ESC to exit a menu Text in this style represents menu commands For example Click View Tools Customize 14 Windows Installation This chapter describes the software and hardware installation procedure for the Windows platform WindowsXP and Vista Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an IBM or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor CPU is strongly recommended since AMD and other clone processors are not guaranteed to be compatible with the Intel MMX and SIMD instruction set extensions which the Armada and Malibu Host libraries utilize extensively to improve processing performance within a number of its components The host system must have at least 128 Mbytes of memory 256MB recommended 100 Mbytes available hard disk space and a DVD ROM drive Windows2000 or WindowsXP referred to herein simply as Windows is required to run the developer s package software and are the target operating systems for which host software development is supported Software Installati
172. ogress at the same time The EDMA has a pool of blocks that may be used to define simultaneous complex transfers Class DmaSettings The DmaSettings class manages an image of the settings registers used to configure a QDMA or EDMA transfer It provides properties to read and set the individual fields of the registers saving the user the effort of masking bits and shifting data It even provides functions that preconfigure some commonly used transfers saving even more programmer effort The following code fragment shows how the setter functions are used to set up for a transfer The DmaSettings class returns a reference to self on all setter functions allowing multiple parameters to be set on a single line DmaSettings Cfg Cfg Priority DmaSettings priHigh ElementSize DmaSettings is32bit Cfg SourceIncr DmaSettings Incr DestinationIncr DmaSettings Incr Cfg TCInt true TCCode 1 FrameSync true Cfg SourceAddr int amp src array 0 DestinationAddr int dest array 50 Cfg ElementCount 50 ElementIndex 1 Cfg FrameCount 0 FrameIndex 1 Class Qdma This class manages the posting of Qdma requests It contains functions to allow configuration of a transfer initiating a transfer and completion notification via either an interrupt or a polling function Because the system state is saved in the object transfers can be predefined and saved to be posted at a later time Sbc6713e User s Manual As with all DMA objects t
173. on The development package installation program will guide you through the installation process Note Before installing the host development libraries VCL components or MFC classes you must have Microsoft MSVC Studio version 9 or later and or Codegear RAD Studio C version 11 installed on your system depending on which of these IDEs you plan to use for Host development If you are planning on using these environments it is imperative that they are tested and known operational before proceeding with the library installation If these items are not installed prior to running the Innovative Integration install the installation program will not permit installation of the associated development libraries However drivers and DLLs may be installed to facilitate field deployment You must have Administrator Privileges to install and run the software hardware onto your system refer to the Windows documentation for details on how to get these privileges Sbc6713e User s Manual 15 Starting the Installation To begin the installation start Windows Shut down all running programs and disable anti virus software Insert the installation DVD If Autostart is enabled on your system the install program will launch If the DVD does not Autostart click on Start Run Enter the path to the Setup bat program located at the root of your DVD ROM drive i e E Setup bat and click OK to launch the setup program SETUP BAT detects if t
174. on run Docking IV Auto drag docking Pressing the Control key while ngine Minimize on Run dragging will prevent window docking v Background compilation 33 Click the Preferences Tab 34 Check Editor files and Project desktop under Autosave Options so that project files are automatically saved each time a project is rebuilt and debugged 35 Click OK Sbc6713e User s Manual 34 Static binding of built executables 36 Click on Project Options on the main BCB toolbar to invoke the Project Options dialog Directories Conditionals Packages Tasm CORBA Compiler Advanced Compiler C Pascal Linker 37 Click the Linker tab Linking Warnings v Create debug information C All 38 Uncheck the Use Dynamic RTL checkbox mi lle ss RUM I Use debug libraries PE file options Min stack size 0x0 e import library bi 39 Next click on the Packages tab and uncheck the Build with runtime packages checkbox aed er gem Directories Conditionals Packages m Design packages Borland ActionB ar Components Borland amp DO DB Components Borland Base Cached ClientD ataset Borland BDE DB Components Borland C Builder COM Server Com Borland C Builder Internet Explorer K K K KRKK c program files borland cbuilder6 Bin c Add Remove M Runtime packages Build with runtime packages
175. onstructs a default thread running within normal priority and starts this thread automatically The entry point function in this thread is called IIMain and all Pismo applications must define this function This function is intended to replace main in your application programs You may safely call any BIOS function within IIMain Running the Target Executable The test program may be converted into a simple Hello World example by using the built in standard I O features within Pismo Bring up the Test cpp source file edit screen Scroll down the source file by using cursor down button until you reach the 11Main function Edit it as follows include HdwLib h include UtilLib h cio init cio lt lt Hello World lt lt endl Sbc6713e User s Manual 87 cio monitor You can now compile the new version by executing Build from the Project menu or by clicking on its toolbar icon This causes Code Composer Studio to start the compiler which produces an assembly language output The compiler then automatically starts the assembler which produces a obj output file test obj Code Composer Studio then invokes the TI Linker using the testcfg cmd file which is located in the project directory This rebuilds the executable file using the newly revised test obj If no errors were encountered this process creates the downloadable COFF file test out which can be run on the target board At this point the program may be
176. ontaine CONFIG PROHIBIT va Prohibit Contains CowmGPoompm wn Prohibit Contains Conr PRONI we Prohibit Contains ICowmGPompm wo Prohibit Contains Sbc6713e User s Manual 62 Simulation The test files are used in the simulation and testing of the Framework code The testbench file is SBC6713 top tb vhd and it uses several components for testing that are defined by the other model files These model files are very simple and are only for simple testing More complex models may be needed to adequately model more advanced uses The testbench contains a set of simulation steps that exercise various functions on the framework logic for basic interface testing Behavioral procedures have been written to simulate the DSP timing for sync and async memory accesses that are useful in simulating data movement Also the steps to setup the logic for data streaming support are shown so that interrupt servicing DMA or CPU accesses trigger and event log use are illustrated Required Software and Hardware Recommended Software Mentor Graphics ModelSim 5 7e or higher Recommended Hardware Pentium 3 or better at 500 MHz with 512M of RAM Setting Up the Simulation The files unzipped from the Framework Logic archive contain all the source and macro files needed You will normally need to make a ModelSim project reflecting your exact directory structure although an m
177. or or Velocia baseboard requires a particular setup of the project E CS Project Copy Utility iini xi ie Deiiren Pie Name Scope jo E vamples Scope le HdWLib k le UrilLib h amespace II void IIMain By far the easiest way to create a new DSP project is by using an existing project as a template The CopyCcsProject applet provided in the Pismo Toolset automates this task To use this utility select an existing Code Composer project as the Source Project typically one of the example programs supplied in the Pismo Toolset Next select the directory into which you wish the new project to be created using the Destination Project Directory edit control Then edit the Destination Project Name for the newly created project Finally click the Copy button to create the new project from the template The new project may be opened and used within Code Composer Alternately you may follow the manual steps below to create a new target DSP project The project name used below is called Test but you should name your project appropriately for your application Sbc6713e User s Manual ista CPU_1 C6711 Code Compo File Edit view Project Debug Profiler asali eej oo Start Code Composer Studio In the default configuration the project window will contain no projects but will contain the default Innovative supplied board initialization GEL file ista CPU_1
178. ou to set the memory size Reserve Memory for Dsp needed for the busmastering to occur properly This applet may be run from Combined DSP Board sage the start menu later if you need to change the parameters Rsv Region Size MB For optimum performance each Matador Family Baseboard requires 2 MB of memory to be reserved for its use To reserve this memory the registry must be updated using the ReserveMem applet Simply select the Number y of Baseboards you have on your system click Update and the applet will Non paged pool size MB 256 update the registry for you If at any time you change the number of boards Status Ok in your system then you must invoke this applet found in Start All Programs Innovative lt target board gt Applets Reserve Memory Update Help Exit After updating the system exit the applet by clicking the exit button to Ready resume the installation process Configuration Total physical memory MB 2047 Figure 5 BusMaster configuration Sbc6713e User s Manual 19 At the end of the install process the following screen will appear Installation The installation is complete Shut down your computer and install your board s then reboot your computer The drivers should load automatically and your board will become available Please refer to your Hardware Software Manual for instructions on hardware installation prior to powering the machine back on to make certain everything is plugged in corre
179. ource directory Please refer to the pictures below C Untitled Configuration Mode iMPACT Dag 8 X En cas E NU Boundary Scan Slave Serial SelectMAP Desktop Configuration Prepare Configuration Files want to create a System ACE File PROM File Boundary Scan File Welcome to iMPACT The intellige pe BATCH CMD setPreference i BATCH CMD setPreference jj BATCH CMD setPreference i gt BATCH CMD setPreference ij BATCH CMD setPreference i BATCH CMD setPreference Joe BATCH CMD setPreference i BATCH CMD setPreference per BATCH CMD setPreference ie BATCH CMD setPreference i BATCH CMD setPreference i BATCH CMD setPreference i BATCH CMD setPreference Ie BATCH CMD setPreference Ae BATCH CMD setPreference jj BATCH CMD setPreference i BATCH CMD setPreference j BATCH CMD setPreference Hunc Carel Hop Figure 37 Click on PROM File Option Sbc6713e User s Manual 168 C Untitled Configuration Mode iMPACT File Edi Yiew Mode Due X Ge ee ee ee 3 Boundary Scan Slave Serial SelectMAP Desktop Configuration Prepare PROM Files want to target a Xilinx Serial PROM Parallel PROM Xilinx PROM with Design Revisioning Enabled Welcome to iMPACT The intellige T Compress Data et E E PROM File Format pee BATCH CMD C MCS C TEK UFP C format i BATCH CMD i BATCH CMD
180. p peripherals for the Framework Logic Most designers integrate application specific features into the standard memory mapping to preserve as much software as possible Also the memory decoding and data interface to the DSP are architected in the logic to support the burst or asynchronous memory interfaces Sbc6713e User s Manual 39 Note SBC6713e External Memory Map Table 13 UART Overview RS232 Asynchronous Serial Port The SBC6713e implements a single asynchronous full duplex serial port channel with RS232 drivers compatible with standard PC serial port interfaces The serial port is implemented in the application FPGA as a logic function and uses a RS232 transceiver Figure 10 UART Block Diagram UART Xmitsublk Parallel Serial 32x8 FIFO T CPU Interface Flow Control sid RS232 Driver Rcvrsublk Transmitter Parallel Serial 1 8432 MHz Crystal 32x8 FIFO Developing FPGA Firmware Spartan IIe is designed for the SBC6713e using VHDL coding and were compiled under Xilinx ISE 6 2 3 XST synthesis The example debug logic design is a project loadable by opening ISE and preforming a Project Open on the sbc6713 intf npl file in the logic root directory The design directory path originally used to house this project hierarchy was c projects sbc6713 intf_logic It is recommended that the customer s installation duplicate this directory configuration in order to avoid problems with Xilinx tools Set
181. pecific hardware information for airflow requirements A Few Considerations BEFORE Power up Double check all connections before applying power Ensure that the JTAG and baseboard cards seated correctly in the slot It cannot be overemphasized Double check your cabling BEFORE connecting to the baseboard DO NOT hot plug the cables Hot plugging cables can cause latch up of components on the card and damage them irreparably Be aware that the cables to analog inputs are an important part of keeping signals clean and noise free Shielded cables and differential inputs where applicable help to control and reduce noise Sbc6713e User s Manual 23 After Power up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compliant allowing Windows to detect them and auto configure at start up Under rare circumstances Windows will fail to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section The next section is NOT used with the Non DSP products If the board you are installing is a Non DSP product the installation is complete Code Composer Studio Setup with II Jtag To setup Code Composer Studio and activate the Innovative Integration supplied CodeHammer JTAG board driver the Code Composer Studio Setup Utility must be run Since the Code Hammer debugger is XDS510 compatible Code Composer Studio se
182. pf file is provided You will also need to compile the Xilinx unisim simprim and core libs and point to them in ModelSim Set the project default to VHDL 93 if you intend to compile in ModelSim using the project manager Loading the Testbench The simulator used from within ISE is Mentor Graphics ModelSim and support files for using the testbench from within environment are included We recommend that you run ModelSim using the macro files provided as a standalone operation and not from within ISE This is because we have several models that do not get compiled if you run from ISE The macro files are the tb_sbc6713 do and wave do files for compilation and waveform visualization respectively The tb_sbc6713 do file compiles the files in the necessary order and loads the simulation Running the Simulations Once you have executed the macro files in ModelSim the simulation is ready to run A time period of 100 us is usually enough to see it start Sbc6713e User s Manual 161 Modifying the Simulations The testbench file provides sample code to begin your simulations Accesses are shown to each peripheral from the DSP and how to control the peripherals such as Omnibus FPDP UART etc In the code are several procedures that simulate DSP accesses and can be used to simulate both async and burst DSP access to the logic The following code shows the DSP async access procedure with the correct timing and its use in the testbench Below i
183. pletion of the primary transfer the first link block is loaded into the primary block and initiated When this block completes the next linked block is loaded and so on A link block can form a loop but it is important to remember that the primary block can never be part of a loop Since it is overwritten by the first linked transfer this transfer can only occur once Because of this to make a loop of two transfers requires three blocks to be configured The primary block contains the first transfer the first link the second transfer and the third is a repeat of the first transfer that 1s linked back to the first link block Link blocks are allocated by a call to AddLink This call automatically configures the preceding block to link to this newly added block It returns the index of the newly added block that can be used in order to configure the link block To form a closed loop in a block chain call LinkBackTo This connects the final block in the chain back to the block whose index is given in the argument Transfer chaining is a mechanism for having a transfer trigger another on completion The ChainTo and ChainEnable methods set up a chaining relation between two transfers Note that on the TI C671x processor the second transfer must be configured on channels 8 11 Class EdmaMaster This class acts as a holder for functions and information common to all EDMA interrupts instead of associated with a single EDMA channel Only one insta
184. plug in board with the target DSP Use this utility prior to invoking Code Composer Studio to insure that the communications DOETSCHSTDI link is viable and clear This utility is also convenient in confirming that the Code ES Hammer installation is complete and correct PCI JTAG Access Test 31 dE Exit RtdxTerminal Terminal Emulator This applet provides a C language compatible standard I O terminal emulation facility for interacting with the Termlo library running on an Innovative Integration target DSP processor Display data is routed between the DSP target and this Host the terminal emulator applet in which ASCII output data is presented to the user via a terminal emulation window and host keyboard input data is transmitted back to the DSP The terminal emulator works almost identically to console mode terminals common in DOS and Unix systems and provides an excellent means of accessing target program data or providing a simple user interface to control target application operation during initial debugging RtdxTerminal is implemented as an out of process extension to Code Composer Studio Consequently it must be used in conjunction with CCS and a JTAG debugger it cannot operate stand alone The terminal emulator is straightforward to use The ibd terminal emulator will respond to stdio calls asgima a ajaja e 2 automatically from the target DSP card and should be r
185. pod cable to the connector located on the end bracket of the JTAG PCI plug in board Sbc6713e User s Manual 22 Baseboard Installation To install the baseboard 12 Perform the board installation in an ESD or static safe workstation employing a static dissipative bench mat Wear a properly grounded wrist strap or other personal anti static device Stand on an anti static mat or a static dissipative surface 13 Shut down Windows and power off the host system and unplug the power cord 14 Touch the chassis of the host computer system to dissipate any static charge 15 Remove the card from its protective static safe shipping container being careful to handle the card only by the edges 16 Touch the chassis of the PC to dissipate any built up static charge 17 Connect the 14 pin connector on the JTAG PCI pod to the DSP board JTAG connector Non DSP board users skip this step 18 Securely install the baseboard into an available PCI slot in the host computer IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even permanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the s
186. r 32 bit words The packet type in this case xcSendCommand is removed from the data buffer and a special method is used to relay this buffer to the Target DSP There is currently a restriction on the number of 32 bit words the inter processor communication Fifo can handle and that is the amount of 32 bit words in a packet has to be an even number 8 Target to Host command packet send n recv_n Host recv n lt lt command packet _ Target Host send n command ack gt gt Target The packet structure for command packet and ACK packet are the same as previously discussed 9 Host to Target data packet send n recv n Host send n packet header 7 Target Host recv n lt lt command ack Target Host send n packet data gt gt Target Host recv_n lt lt command ack Target The ACE SOCK Stream methods to receive and send are the same as the ones used when sending a command The packet header buffer is an array of five 32 bit words and has the following structure Packet 0 xcSend Packet type Packet 1 Buffer size Size in bytes Sbc6713e User s Manual 65 Packet 2 0 Packet 3 0 Packet 4 0 The ACK packet is the same as with the command ack packets The second time the send n method is invoked one will use a buffer with raw data this is the user data to send across to the Target
187. r Rev B Rev C Control 0x57225000 0x53338000 Timer 0x000002ee 0x00000350 These values are referenced within several source files Each must be edited and recompiled in order to effect the required changes The affected source files are Innovative Sbc6713eWdwLibWIInit cpp Innovative Sbc6713eVZenLibWIInit cpp and InnovativeMI6x gel The IIInit function is affect within the cpp files and the Startup method is affected within the gel file Sbc6713e User s Manual 37 Changes to Phase Locked Loop initialization The code which initializes the phase locked loop must be changed to accommodate running at 300 MHz instead of 225 MHz Table 3 PLL Register Changes Register Rev B Rev C PLLM 0x0006 0x0008 PLLDIV3 0x8002 0x8003 These values are referenced within several source files Each must be edited and recompiled in order to effect the required changes The affected source files are Innovative Sbc6713e HdwLib IIInit cpp and Innovative Sbc6713e ZenLib IIInit cpp Only the InitPIHl function is affected within these files Changes to Application Programs All DspBios applications include a CDB file to contain static initialization information including the processor speed in MHz Each CDB must be edited using the TI provided Configuration Editor to modify the CPU speed to 300 MHz when using rev C boards The value to be edited is located on the System Global Settings property page Upgrading the Firmware NOTE Once you begin the upgra
188. reshold configuration allows the threshold to be set in volts with the ThresholdLevel method In the above example the hardware is configured to trigger at half a volt The ConfigurableTrigger Ul interface allows signals to be specified as Type edge or level and Polarity positive or negative In the example above the trigger is configured for a positive going edge This means that when the signal crosses the threshold from below to above the start trigger will fire A crossing from above the threshold to below it will not fire the trigger Each line can be read from the inside out Stream gt StartTrigger returns the current start trigger UI object This object is input into the trigger conversion function ConfigurableTriggerPtr and converted into the ConfigurableTrigger interface Finally the Type method of this class is called to set the trigger type to ttEdge The trigger modes a module supports and the UI interfaces its supported modules support are very module dependent It is quite common to have to use several conversion functions to configure a trigger mode It is also common for a trigger to be unconfigurable exposing no trigger UI classes Similarly many modules support several triggering modes Other modules support only the default unconfigurable combination of no Pretriggering Always start Never stop and no Retriggering The description of the modes a module supports and the UI interfaces a module supports in each mode are liste
189. rminal emulator to launch the embedded application rather than the embedded Talker Common Problems when Embedding Code There are several problems frequently encountered when ROMing code If you encounter one of the symptoms listed below attempt the corrective action listed before calling Innovative technical support Table 15 Common Problems when Embedding Code in Flash ROM Symptom Possible Corrective Actions Inadvertently overwritten the Re burn the Talker per above Talker in sector 0 Code Hammer cannot initialize Verify that the I O address specified in the Code Composer setup is the target correct and that the JTAG board is properly connected to the DSP board Configure and run the Innovative JTAGDIAG EXE utility to reset the debugger hardware Code Composer Studio users should also run the XDS510 Reset Utility using the same I O address as entered into JTAGDIAG EXE to initialize the Studio Debugger The target may be held in reset Verify that the boards device driver is installed and operational Code Composer versions prior to 4 01 are incapable of communicating with C67xx processors Also v4 01 is better able to recover from invalid images burned into sector 0 on baseboard6711 DSPs Contact LI for upgrade information The embedded application will The target is being held in reset For single board targets not boot disconnect serial port 1 to the host and reboot If serial port 1 must be connected
190. rminate the Code Composer Studio application 3 Invoke the terminal emulator application 4 Restart the Code Composer Studio application This outlines the basics of how to recompile the existing sample programs within the Code Composer Studio environment Anatomy of a Target Program While not providing much in the way of functionality the test program does demonstrate the code sequence necessary to properly initialization the target The exact coding however is very specific to the I I C Development Environment target boards and is explained in this section in order to acquaint developers with the basic syntax of a typical application program m HELLO CPP Test file program for target board my include Pismo h Sbc6713e User s Manual 88 IIMain CLO lt lt init cio lt lt Hello World lt lt endl cio lt lt nEchoing keystrokes lt lt endl char key do cio gt gt key cio lt lt key lt lt flush while key Oxlb cio monitor The two lines of the program that being with a are include statements which include the header files for the hardware and utility I O libraries These include prototypes for all the library classes within Pismo The cio lt lt init invocation will setup the standard monitor I O interface and reset the terminal window The next lines perform the basic standard I O functions of printing Hello World amp E
191. rocess begins here To begin send packet header to target int Packet 5 Packet 0 xcSend or xcSendCommand or xcClose Packet 1 Size of Data Buffer in bytes OR CommandID Packet 2 0 Packet 3 0 Packet 4 0 CommandID in case of xcSendCommand Size in case of xcSend 0 in case of xcClose A CommandID is your own application enum which will be interpreted in your C6713 DSP application ACK packet sent from target to host int buf 3 buf 0 CommStatusCode buf 1 Received Byte count This is 20 bytes 5 words buf 2 Received Byte count If the command sent from Host was xcSendCommand or xcClose then the operation completes with the ACK packet sent from Target to Host PC If the command sent from Host to Target in the packet header was xcSend then the next applies 4 Host sends a Packet Header to Target int Header 3 Header 0 xcSendData Header 1 Size of Data Buffer to follow in bytes Header 2 0 Target Sends ACK to Host PC ACK packet sent from target to host int buf 3 buf 0 CommStatusCode Sbc6713e User s Manual 73 buf 1 Received Byte count This is 12 bytes 3 words buf 2 Received Byte count 5 Host PC sends data packet to Target it does not require additional formatting this is your own application data and the complete contents of the data is intended to reach the C6713 DSP This packet has even num
192. s an Interrupt Binder Object See Interrupt Binder Templates on page 54 as an argument to associate a handler function or method and argument for the interrupt forwarding mechanism of Pismo A second pair of functions TcIntDeinstall and LinkTcIntDeinstall removes any installed handler for the TC bit used by the block Once installed TC interrupts for the entire transfer may be enabled or disabled by a call to TcIntEnable The following example shows a full Edma transfer with TC interrupt handling In this example a class member function is bound to handle the interrupt response class Dmalsr public typedef void IntFtnType void fallow DmaIsr Binder this amp DmaIsr MyHandler NULL void MyHandler void fallow qdma_not_done false ClassMemberHandler DmaIsr void gt Binder y Dmalsr Isr void EdmaTest Edma Ed Ed Settings Priority DmaSettings priHigh ElementSize DmaSettings is32bit Ed Settings ElementIndex 1 ElementCount 50 FrameIndex 1 FrameCount 0 Ed Settings TCInt true TCCode 1 FrameSync true Ed Settings SourceAddr int amp src_array 0 SourceIncr DmaSettings Incr Ed Settings DestinationAddr dest_array DestinationIncr DmaSettings Incr Define a linked DmaSettings Cfg Cfg Priority 1 ElementSize 0 SourceIncr 1 DestinationIncr 1 Cfg TCInt true TCCode 1 FrameSync true Cfg SourceAddr int amp
193. s an example for Omnibus with Asynchronous accesses procedure async access constant ce space integer constant rw std logic constant address bit vector 23 downto constant data bit vector 31 downto 0 is begin wait until eclk in event and eclk in case ce space is when 0 gt ceO0 n lt 0 after 2 ns cel n lt TL ce2 m lt 1 ce3 n lt 1 when 1 ce0 n lt 1 cel n lt 0 after 2 ns ce2 n 1 ce3 n lt 1 when 2 ce0 n lt 1 cel n lt S15 ce2 n lt 0 after 2 ns ce3 n lt 1 when 3 ce0 n lt 1 cel m lt ILY ce2 n 1 ce3 n lt 0 after 2 ns when others gt ce0 n lt 1 cel n lt 1 ce2 n lt 1 ces m lt 1 end case this is a setup of one cycle if rw else end if ea lt to stdlogicvector address 21 downto 2 if rw else end if 1 then aoe n lt 0 after 2 ns aoe n lt 1 0 then ed to stdlogicvector data ed lt others gt H wait until eclk in event and eclk_in One if rw else cycle access 1 then are n lt 0 after 2 ns Sbc6713e User s Manual 0 115 after 2 ns 115 after 2 ns 162 awe n lt 0 after 2 ns end if wait until eclk in event and eclk in 1 wait until eclk in event and eclk in 1 if ce space 2 then printval ed sample point from dsp wait until
194. s are called Module Conversion Functions Module Conversion Functions are provided for all supported Omnibus modules See the online help for the module class for a description of these functions An example of the use of these functions SD16 sdl6 A4D4 a4d4 SD16Ptr Aln Module Gives valid SD16 object A4D4Ptr AIn Module Returns 0 not an A4D4 Note that a module conversion function will fail if the conversion can not take place Selecting and Configuring Clocks On attachment of the stream to a module the Clock configuration system becomes active It consists of the following methods Table 6 Stream object Clock Methods Method Description IsClockSourceSupported Returns True if a clock source is allowed on the hardware SetClockSource Change clock source to the selected source Clock Returns an interface object that allows the configuration of the Clock source The User Interface object returned by the Clock method is used to configure the selected clock source The possible ways a clock can be configured depends strongly on the type of source For example an internal clock such as the DDS can have the Sbc6713e User s Manual 49 clock frequency programmed An external clock can not Rather than provide a complicated set of functions many of which may not work for a clock source we instead separate each distinct part of the User Interface into separate interface classes The interface object for a clock
195. s to be in place JP16 Below is a screen shot of Download LAN firmware tab window Network Settings Dwld Loader Dwld Client Dwld LAN Logic Dwld INTF Logic Dwld Application CAlnnovative SBC6 13_Coprocessor Examples T alkerksbcb71 3L N exo Download LAN Logic Download INTF logic firmware This tab may be routinely changed by users planning on expanding modifying on the the Sbc6713e logic If for some reason the exo file you downloaded makes the card inoperable just download again a known good exo file or if the card is unable to boot follow the procedure described above where you would have to run the ReLogic 600 out or ReLogic 300 out depending on the board configuration from CCS Code Composer Studio Below is a screen shot of Download INTF firmware tab window Network Settings Dwld Loader Dwld Client Dwid LAN Logic Dwld INTF Logic Dwld Application C Pantera sbc671SintfB00E exdl Download INTF Logic Sbc6713e User s Manual 35 Download Application This window is capable of loading an application program that will run on the C6713 DSP once it boots The board may be configured to either boot your embedded application or the default Innovative Integration benign program via the Boot embedded app checkbox To enable use of a user supplied embedded application use PromImage to convert your application to binary bootable format Then browse to this i
196. se external clock input multi card sync FPDP port data links 4MB flash ROM and watchdog One Spartan IIE FPGA of up to 600K gates is available for implementing custom logic interfaces and accelerated signal processing In the FPGA it is possible to process data at very high rates Begin by analyzing your application to identify the operations that are high speed and lower speed Higher speed signal processing operations should be targeted at the FPGA provided that they are of manageable complexity Typical FPGA operations include FIR filters down conversions specialized high speed triggering and data sampling and FFTs All of these functions are deterministic mathematical functions that are suitable for the FPGA Data formatting protocols and control functions are typically more easily implemented on the DSP The SBC6713e has two FPGAs on it Xilinx Spartan IIE 50K gates and Xilinx Spartan IIE 600K system gates The Spartan Ile 600K gates is used for the analog interfacing and as the computational logic on the board Whereas Spartan IIe 50K gates behaves as an Inter processor FIFO between TMS32DM642 and TMS320C6713 and full interrupt support for DMA transfers from either processor the logic for this Spartan Ile is not provided The analog logic which resides in Spartan ITE 300K 600K gates is provided in source form to assist in custom application developments The FPGA logic images may be downloaded to Spartan IIe as part of the software
197. sed to the display bit 15 1 the data is sent to the display If it is a command to the display then the lower byte is sent to the display as an 8 bit transmission If it is data for the display then the data is sent with a NOP command 0xE3 automatically appended to it as required by the controller Serial Word Format The serial data word format is as follows Pa ram Mem f 7 0 Display command See SSD0323 data sheet for command set or data word 13 Noted Display power 1 2 on 0 off default Display reset reset default 14 Display CMD 1 bits 7 0 are display data 0 bits 7 0 are display command 15 Device select 1 this data word is for the adapter 0 this data word is for the display An example transaction is shown here The DSP has sent a data word of OxCOAA representing that the display should receive a data byte of OxAA The data is then immediately sent to the display as a 16 bit transmission of data OxAA followed by a NOP command Sbc6713e User s Manual 182 foled_inttith_oled intl vhd_th te data i th oled_inthvhd_tbyauletes Jbled inti tb oled intl hd Ibluut ds Yoled_inth tb oled int vhd tb uutzclk Joled_intl tb oled int yhd Ibuu Jaled imf tb olad int vhd A AMAR le oled int hd tb sclk rojed inif 1b aled ihi vhd_th uut emd oled inti tb oled int vhd tb uut sdo doled intl tbi olad int hd bul
198. sends a request data command to the DM642 CoProcessor the DM642 in turn goes to its FIFO see explanation on the beginning of this chapter and blocks on data from the C6713 the Host code in our implementation has a Timeout feature thus if the C6713 has no data to send it will generate a Timeout event to inform the host application code that no data has been received the host code may opt to halt the pending receive request or ignore the event and keep on waiting in our implementation we keep on posting network receives with 5 second timeouts until data is received or until the application code requests a Halt 1 Host opens connects to port 1009 This includes configuring the correct type of address INET creating a Connector object and creating a Stream object This is a TCP IP connection oriented protocol Sbc6713e User s Manual 74 2 Host sends data request to Target int xReply 3 xReply 0 xcRecvPosted xReply 1 0 xReply 2 0 3 Target Co Processor receives this request and blocks on data to be received to C6713 When the C6713 has data to send to Host the DM642 un block requirement will be satisfied and a Data Packet Header OR Command Packet will be sent to Host Command Packet int XfrPacket 5 pkRecvCommandRequest XfrPacket 0 XfrPacket 1 XfrPacket XfrPacket XfrPacket mmama 2 3 4 OR CmdBuf 0 CmdBuf received from C6713 C
199. ss F1 Sbc6713e User s Manual mm oo mm ud Data Stream 0 Add Device Look in C3 INTF_LOGIC 7 e oer Ee 3 projnav work 1 C3 nao Gest J 16550 Gicspro E mppr _result dir O simulation Filename sbc6713_top bit Files of type All Design Files zl Cancel Prom Formatter 162 Figure 40 Select the BIT file Sbc6713e User s Manual 163 O untitled dies Generation Mi edel iMPACT tput Help ee eel sg System ACE PROM Formatter iter SVF STAPL xsvr i BATCH CMD setPreference ES Add Device File Data Stream D Starting Address Max 8 Hex Digits 7 Now start adding device file s Add File i BATCH CMD setPreference pee BATCH CMD setPreference PROM File Generation i BATCH CMD setPreference Je BATCH CMD setPreference peer BATCH CMD setPreference pee BATCH CMD setMode pff ive BATCH CMD setMode pff D Do you want to generate file now Click Finish t pou Click Cancel to go to user screen GUI Add one device For Help press F1 Figure 41 PROM File Generation Note Please do the visual inspection of Spartan Ile 1 e either 300E or 600E and load the logic accordingly FlashBurn Utility Prom Formatter To load the new EXO file into Spartan lle 300K 600K use the FlashBurn exe utility included in the Pismo Toolset Within the program read in the EXO file you
200. st must be prepared to receive this larger buffer C6713 should only send even number of 32 bit words to Host PC since the Inter Processor FIFO cannot deal with odd number of 32 bit words and also internally the DSPs have and algorithm to to send data as bursts which only deals with even number of words and at a minimum 4 words 7 Host then sends an ACK packet to Target Reply 0 pkRecvDataAck Reply 1 0 Reply 2 0 enum PakTypes pkRecvCommandRequest 0xC0 pkRecvPacketRequest pkRecvRequestAck pkRecvData pkRecvDataAck III Sending RESET command to Target 1 Open socket number 1023 Send Command to Target int packet 3 packet 0 pkMasterReset packet 1 0 packet 2 0 2 Target sends back ACK packet int aSendPacket 3 aSendPacket 0 pkMasterResetAck aSendPacket 1 0 aSendPacket 2 OF 3 Host closes all communications with Target enum PakTypes pkFirmwareInfoRequest 0x50 pkBootAppInfoRequest pkNetInfoRequest pkSetBootApp pkWriteNetInfo pkInfoRequestAck pkWriteBdRev pkMasterReset pkMasterResetAck NAK Sbc6713e User s Manual 76 IV Requesting Board information 1 Host opens socket number 1021 and sends the following command to Target int packet 3 packet 0 pkFirmwareInfoRequest packet 1 0 packet 2 0 Target then sends the following information and is subject to change int aSendPacket 200 aSendP
201. sts In the burst mode one data point 32 bits wide is provided for each clock As can be seen from the read and write burst timing diagrams data is at least two cycles latent from the control signals for reads and may be zero for writes The Framework Logic uses a latency of X for reads and X for writes Data bursts can be of any length and the Framework logic accommodates any burst length needed Normally this is set by the DMA channel eclkouT A _ f _ _ NASA NS NS COS L 4 Ls 3 EA 21 2 6 gt 7 ED 31 0 Cor X G2 X 03 X Q4 k 8 K I 8 ARE SDCAS SSADSt SS ot 9 K s AOE SDRAS SSOEf eee CO AWE SDWE SSWEt t ARE SDCAS SSADS AOE SDRAS SSOE and AWE SDWE SSWE operate as SSADS SSOE and SSWE respectively during SBSRAM accesses Figure 16 DSP SBSRAM Read Timing Courtesy of Texas Instruments Sbc6713e User s Manual 46 ECLKOUT ct 1 a CEx 9 2 3 BESOI m X BE1 X BE X BE X BEA X y 4 j 5 EA 21 2 gt 1 11 ED 31 0 Xai X o X a3 X a4 X 0 Q Q Q Q ht 8 pl 8 ARE SDCAS SSADSt TYCO Vf AOE SDRAS SSOEt 12 12 AWE SDWE SSWEt No ee gu accesses Figure 17 DSP SBSRAM Write Timing Courtesy of Texas Instruments Since there are very few timing adjustments in the DSP EMIF control for sync registers logic designers should be aware that burst in
202. t others gt 0 elsif rising edge e clk then pdo lt ed end if end process Sbc6713e User s Manual 49 Figure 20 Incoming DSP Data All the control signals from DSP get registered in address decoder module Example is shown here process e clk reset begin if reset 1 then cel n q i lt 1 awe n q i 1 are n q i lt TES aoe n q i lt 1 elsif e clk event and e clk 1 then cel n q i lt cel n awe n q i awe n are n q i are n aoe n q i aoe n end if end process end generate Figure 21 DSP Controls Signals The FIFOs in the logic are implemented for FPDP interface using Xilinx CoreLib functions The FIFO component VHDL instantiation is shown here component fifo 512x32 fwft Port reset in std_logic din IN std logic VECTOR 31 downto 0 wr en IN std logic wr Clk IN std logic rd en IN std logic rd clk IN std logic fifo reset IN std logic dout full OUT std logic not empty OUT std logic wr count OUT std logic VECTOR 8 downto 0 rd count OUT std logic VECTOR 8 downto 0 end component Figure 22 FIFO Component Instantiation The FIFO interrupt filter as contained in the fifo_util vhd file is shown in use here Eri mE E FIFO Level Filtering inst fifo rd int filt fifo level flt Port Map rst gt fpdp reset clk gt clk fifo_en gt fpdp fifo rd level in fpdp fifo thres
203. t Binder Object See Interrupt Binder Templates on page 54 as an argument to associate a handler function or method and argument for the interrupt forwarding mechanism of Pismo A second function TcIntDeinstall removes any installed handler Once installed TC interrupts may be enabled or disabled by a call to TcIntEnable The following example shows a full Qdma transfer with TC interrupt handling In this example a class member function is bound to handle the interrupt response class Dmalsr public typedef void IntFtnType void fallow DmaIsr Binder this amp DmaIsr MyHandler NULL void MyHandler void fallow qdma_not_done false ClassMemberHandler DmaIsr void gt Binder y Dmalsr Isr void IIMain DmaSettings Cfg Cfg Priority 1 ElementSize 0 SourceIncr 1 DestinationIncr 1 Cfg TCInt true TCCode 0 Sbc6713e User s Manual 57 Cfg SourceAddr int src array DestinationAddr int dest array Cfg ElementCount 100 ElementIndex 1 Cfg FrameCount 0 FrameIndex 1 Qdma Q Cfg This QDMA operation will trip a terminal count interrupt when all data has been moved Q TcIntInstall Isr Binder InitArrays Q TcIntEnable true qdma not done true Q Submit while qdma not done 7 Class Edma This class manages the posting of EDMA requests It contains functions to allow configuration of a transfer initiating a transfer an
204. t may send the following packet int packet 200 Data to send packet 0 pkSetBootApp packet 1 Boolean value true Boot customer s app from flash Another supported command for use In House only as this causes the MAC address of the board to change int packet 200 Data to send packet 0 pkWriteBdRev packet 1 Board revision as ASCII character packet 0 Board serial number as short 3 Target then sends following ACK packet int aSendPacket 3 aSendPacket 0 pkInfoRequestAck aSendPacket 1 0 aSendPacket 2 0 VI Burning Firmware This command is used to load new firmware i e new interface or lan logic new client program new customer s application program 1 Host opens socket number 1020 2 Host sends Command Packet as following int Packet 3 Packet 0 Download request type Packet 1 Image size in bytes Packet 2 Image Checksum sum of contents of all image bytes 3 Target sends ACK packet to Host int aSendPacket 3 aSendPacket 0 pkLogicDownloadRequestAck aSendPacket 1 0x00 aSendPacket 2 0x00 Sbc6713e User s Manual 78 4 The image file is sent in data buffers of less or equal to 16384 bytes in size The process is that the Host will send a Packet Header then will wait for ACK then it will send the Data Buffer portion of that header and wait for an ACK a Host to Target int Header 3 Header 0
205. t selection dialog which allows selection of user specified font within the Terminal and Log text controls Bkg Color button invokes a color selection dialog which allows selection of user specified background color within the Terminal and Log text controls Sounds Group Controls within the Sounds group box govern the audible prompts generated by the terminal emulator as detailed below Errors if enabled file I O and other errors encountered during operation generate an audible tone Suspend if enabled suspension of standard I O such as following plotting via Binview generate an audible tone Alerts if enabled alert conditions encountered during standard I O such as upon display of the ASCII bell character generate an audible tone Coff Load Group Controls within the Coff Load group box govern behavior surrounding a COFF executable download Reset Before if enabled the Code Composer Debug Reset DSP behavior is executed before attempting to download the user specified COFF file Run After if enabled the Code Composer Debug Run behavior is executed immediately following the download of a user specified COFF file Debugger Group Controls within the Debugger group box specify the target DSP with which RTDX communications is established Board specifies the board hosting the target DSP to be used in RtdxTerminal stdio communications This combo box is populated with all available board types configured using the Cod
206. tailed information about the components contained in Malibu their Properties Methods Events and usage examples An equivalent version of this help file in HTML help format is also available online at http www innovative dsp com support onlinehelp Malibu Innovative Integration Technical Support Innovative includes a variety of technical support facilities as part of the Malibu toolset Telephone hotline supported is available via Hotline 805 578 4260 8 00AM 5 00 PM PST Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Also feel free to register and browse our product forums at http forum iidsp com which are an excellent source of FAQs and information submitted by Innovative employees and customers Innovative Integration Web Site Additional information on Innovative Integration hardware and the Malibu Toolset is available via the Innovative Integration website at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text Typeface Meaning S barg Text in this style represents text as it appears onscreen or in code It ource Listing also represents anything you must type Boldface Text in this style is used to strongly emphasize certain words Text in this style is used to emphasize certain words such as new Emphasis terna Sbc6713e User s Manual 13 Cpp Variable Cpp Symbol KEYCAPS Me
207. te five internal buffers The size of data buffers may be specified explicitly using the Stream Events method This latter method sizes the buffers such that they can contain the at least the specified number of acquisition events where an event is defined as one sample from all enabled A D or D A channels This simplifies most buffer processing algorithms since all buffers are guaranteed to contain an integral number of samples from all enabled channels The product of the buffer size and the number of buffers gives the load carrying capacity of the system For example the originally allocated three buffers per stream each sized at 0x1000 bytes running at 44 1 kHz equates to a load carrying capacity of 0x1000 bytes buffer x 3 buffers 44100 samples sec 2 bytes sample 139 mS Whereas in the second example with six buffers per driver pool 0x1000 bytes buffer x 6 buffers 44100 samples sec 2 bytes sample 278 mS Data integrity can thus be preserved at the expense of additional memory utilization Burst Streams place data into the buffer provided No buffering is used and data acquisition is halted when the provided data buffer is filled Sbc6713e User s Manual 46 Stream Internals The DSP CPU used on the SBC6713 is powerful and fast yet the Stream classes improve performance even further by drastically reducing CPU use for data movement The available DMA channels in the C6000 DSPs are fully exploited
208. terfaces require that the logic levels be minimized to meet timings The SBC6713e logic has a simple data decoding and mux structure that allows the burst memories high speed while penalizing slower async devices with a extra cycles for decoding and data delivery Adding new read back registers therefore should be done in a small memory region requiring minimum logic The DSP memory is easily subdivided into memory types such as async and burst by using different CE spaces The DSP gives four CE signals for each EMIF that have timings as defined by the software EMIF control registers please refer to the Memory Map Table 13 DSP EMIF Data Read Interface The Framework logic is designed to support full data rate from the the high speed devices with the slower speed devices subordinate The following diagram shows an overview of the logic for the EMIF data path Sbc6713e User s Manual 47 ARE AOE Register Rd Figure 18 EMIF B Data Bus Read Interface Diagram The first thing to notice in the diagram is that the control signals are all immediately registered as they enter the logic This improves the timing by grabbing the signals at the IOB registers and allowing the internal decoding to use the registered signals A simple decoding of the memory spaces then enables the FPDP Rx data FIFO or the ASYNC_DATA sources The async data sources have been selected from a large case statement using minimal address decoding that results
209. tors sess eene n nenne rennen eres ee enne a nein 197 JP23 JTAG Debugger Connector Rev C sessi enne neret tenente nennen enn 198 JP22 Power Input CONNECT ta rte t tre ese e e P e te prO are eee eta 199 JP3 Asynchronous Serial Port Connector essen enne enne nnne terere ener enne 200 JP12 Power Test Connector Rev Clio cous T Ete t re rng 200 JP25 Xilinx JTAG Connector i e XC2Sx00E FG456 Rev C sessi 201 JP21 Xilinx JTAG Connector i e XC2S50E TQ144 Rev C sse tentent tenerent 202 BoardsLayout Rev B n epe ra INI UND BENIN EEG E E EO E ees 203 Board Layout Rev a PETI UNIES 204 Sbc6713e User s Manual List of Tables Table 1 Production Hardware Changes Rev B VS C nennen enne nnne etre 37 T ble2 SDRAM Register Changes RR NR SE A P o eth 37 Tables PLL Register Changes esee te e UR IRR Rt ua e dnm RU 38 Table 4 C6713 DSP EMIF Control Register Initialization Values 42 Table 3 Device Driver and Stream Classes 2 2 eee eee t eiae ni ed aat BE ate d 45 Table 6 stream object Clock Methods 5 eee a 49 Table 7 Stream object Pretrigger MethodS ooooococccnnnninnnocooonoonconnonncnnnonrcnnncnn ron rro n ron rn ron ron enne nnne nnne n etre ener 50 Table 8 Stream object Start Trigger Methods esses eren nnne nennen nnne erret 50 Table 9 Stream object Stop Trigger Methods sssssssssssesseseeseeeeneeer
210. tory Open the ISE project sbc6713 intf npl Recompile and refit the logic The resultant output file will be sbc6713_intf bit Intermediate report files are sbc6713 intf bld NGD Build report sbc6713 intf mrp MAP report and sbc6713 intf par Place and Route Report The PAR file shows a timing summary None of these files should include errors only warnings The warnings can be safely ignored Generate a PROM image as an exo file using Xilinx Impact Use one bitstream starting at 0x0 with Motorola S Record EXO format for the bit file sbc6713_intf bit The PROM size my be set to auto Logic Files and Hierarchy Within the ISE environment the logic for the SBC6713e has a structure as shown in the figure below Sbc6713e User s Manual 41 Figure 11 Logic Files and Hierarchy TOP SBC6713 intf vhd Constraints SBC6713 top ucf FIFO FPDP Rx a fodp_rx vhd fifo_512x3_fwft vhd Filter fifo_util vhd FPDP Tx fpdp_tx vhd FIFO fifo_512x32_fwft vhd DSP Interrupts Filter dsp_interrupts vhd fifo_util vhd Filter fifo_util vhd UART uart vhd Clock Control clkcntrl vhd Address Decoder CPU Interface FIFO address_decoder vhd if vhd E posi fifo vhd Receiver Subblock Reel revrsublk vhd ERG ver OMNIBUS receiver vhd omnibus vhd Transmit Subblock FIFO xmitsublk vhd fifo vhd Post Scaling post_scaling vhd Transmitter transmitter vhd ECLK DLL eclkin_dll v
211. tos on doled int tb oled mtl vhd tb tuutiup button oled_inth tb oled inti vhd tb uut dewn button oled init oled Intl vhd_thvuuteft button oles int tb olad int vhd tb uut siahl button Acled inti tb oled int vha toun choose button toled Intt th oled ntf vhd tb uut bit cour Zoled intf tb oled int yhd Tb uut nop doled intl th olad_inthvhe_tb uut trame_s Jpled inti tb oled mtl vhd tb uut sr 7oled intF tb aled mtf vhd tB uut reset gled intf h oled intf yhd Ib uut data for display M M CATA 25 REESE E E 3 ua t mi al i i 1 TL aa ries mur eI COA TS na gt SSS SS Se oe Sow a wee od A HW uM A LE A s S For commands sent to the display the adapter logic only sends an 8 bit word to the display The following transaction shows the DSP sending a command to the display of 0x8055 A command of 0x55 is subsequently sent to the DSP co o e on oled_intf_tb_oled_intf_vhd_tb tx_data oled_intf_tb_oled_intf_vhd_tb uut fsx oled_intf_tb_oled_intf_whd_tb uut dx oled_intf_tb_oled_intf_whd_tb uut clk oled_intf_tb_oled_intf_vhd_tb uut fsr oled_intf_tb_oled_intf_whd_tb uut dr oled_intf_tb_oled_intf_vhd_tb sclk oled int tb oled int vhd tb uut cmd oled int tb oled intf vhd tb uut sdo oled intf tb oled int vhd tb uut cs n oled intf tb oled intf vhd tb uut up button oled int tb oled int vhd tb uut down button oled intf tb oled int vhd tb uut left button oled intf tb oled int vhd t
212. tup must be configured to use the XDS510 driver for the C6xxx To do this 19 Launch the Code Composer Studio Setup Utility and remove the default simulator driver from the System Configuration right click the default simulator in the System Configuration pane and select Remove 20 Click the C6xxx XDS driver from the Available Emulator Types lol xl E a File Edit View Help control within the setup utility and drag it into the System Configuration control SO C571 X0S510 Emulator C671x XDS510 Emulator System Configuration Available Processor Driver Location Driver Location CAC CStudioltdriversttixds6000 dvr f TMS320C520x fe TMs320C670x f TM5320C621x f TMs320C671x BYPASS ES EISE Diagnostics Utility 2 Once your emulator is added a list of Available Processors is presented Add the appropriate processors for your board as shown in the example The example shows a set up that is configured for an SBC6713e baseboard The C671x emulator is selected as the baseboard uses the TMS320C6713 DSP VO Port 0x0 Eg Factory Boards Ei Custom Boards Create Board Remove Remove Add Multiple Modify Properties Drag a device to the left to add to the currently selected board dh Sbc6713e User s Manual 24 22 Right click on the C6xxx XDS emulator in the System ixi Configuration Pane and select Connection Name amp Data File Connection Properties
213. ty for interacting with the Termlo Pismo library running on an Innovative Integration Matador family DSP processor Using the terminal emulator it is possible to develop and debug target DSP code while deferring development in Host application code By using simple streaming I O functions within a target application during development DSP algorithms can be developed independently from Host applications Later when a custom Host application code is written the DSP standard I O functions may be deleted from the target application and the target application will no longer be dependent on the terminal emulator or the target Termlo libraries Note that it is currently not possible to use the terminal emulator simultaneously with a custom Host application Streaming methods such as lt lt and gt gt are dispatched by the Termlo object to route text and data between the DSP target and the Host the terminal emulator terminal emulator applet Text strings are presented to the user via a terminal emulation window and host key board input data is transmitted back to the DSP The terminal emulator works almost identically to console mode terminals common in DOS and Unix systems and provides an excellent means of accessing target program data or providing a simple user interface to control target application operation Two different implementations of the terminal emulator exist The UniTerminal implementation utilizes the communications bus in order to effect
214. uccessful Use 1 You must have a simulation tool Innovative provides files for ModelSim If you don t simulate it is unlikely you will successfully complete the logic design within your lifetime 2 Estimate the logic usage for your application 3 Define the clock domains in the design and methods to transition them FIFOs work great 4 Identify crucial timing constraints Plan the logic method to meet them Pipelining is usually a good approach 5 Until your simulation works your hardware will not work Debugging on real hardware is very timing consuming Perform real timing simulations wherever possible Using FPGA Framework As a starting point here is a big overview of what is attached to the Spartan lle FPGA Figure 8 FPGA Framework Overview The Framework Logic block diagram is shown below Sbc6713e User s Manual 38 OMNIBUS Interface EMIF B Digital 1 0 SyncLink and Timers and ClockLink Controls DDS Signals SyncLink and External Counters UART FPDP Tx FPDP Control Async Data Mux Figure 9 Framework Logic Block Diagram As can be seen in the block diagram the EMIF B is used as the interface to the analog I O The EMIF B memory space is decoded so that control and configuration registers are mapped as well as burst FIFOs for the high speed data paths Please refer to memory map Table 13 of SBC6713e for external peripherals and memory see TI peripheral manual for TMS320C6713 for on chi
215. um Digital USB Jtag esses 28 Setting up for Multi Processors with Spectrum Digital USB Jtag sess eee 31 Borland Builder Setup aind UW se crc os oeste tet e e e ete ati eee ha BI AR Ede 34 Automatic saving of project files and forms during debugging eessssesesssssrssessresessessrsessestsessrsesesseseeseessseessee 34 Static binding of built executables resone ane a E E E A nnne nnne nnne E TRR 35 Appropriate library and include paths sss eene enne enne enne enne nne tnter n nennen 35 SECG67 136 Product MUST ION rc e 7 Single Board Computer Hardware Features cccceccessesssesseeseestcesecseeesecseeesecseeesecsaesseceaeeseceaeeseeesececeseceeseaeseeeneeensaeeensatees 37 Changes to SDRAM initialization nennen enne enne innen ene enin enne nn enne 37 Changes to Phase Locked Loop initializatiOM ooooconncnnnnocnoonnonnonnconcnnncnnnnnnonncnnnonncnnnnnnn enne nnne nnne nnns 38 Changes to Application Programs e eq erento ee st ap deba bep seing tes 38 Upgrading tlie Firmware A ee Pee RUE S ue lea ce D deer hee A Gee ee riu 38 1 Changes to Loader program eic qned etre taa 38 2 Changes to the Coprocessor Talker a k a Client enne enne 39 Sbc6713e User s Manual 3 Changes to Flash Information Section conaire ta a E E EEE A E E ER R 39 4 Changes tothe Firmware noc e eR PRONTI I RE E SOR OER 40 Abo t th rtg ee D
216. unning before the DSP application is executed in order for the program run to proceed normally The DSP eee E program execution will be halted automatically at the ppt m first stdio library call if the terminal emulator is not ins erem OK ae Aka executing when the DSP application is run since file zord ak at 10 diese standard I O uses hardware handshaking The stdio output is automatically printed to the current cursor location with wraparound and scrolling and console keyboard input will also be displayed as it is echoed back from the target Press any key to display disk file The terminal emulator also supports Windows file I O ma AA using the TermFile library object Termal piens Restarting DSP Files out Connected Running 36 813 Important Note Before using the terminal emulator you must register your Pismo Toolset Until you do so usage will be restricted to a 20 day trial period for the terminal emulator and other applets contained in the Toolset To register fill out the contents of the Registration Form then click on the Register Now button This will print a Registration report which must be faxed to Innovative Integration Innovative Integration will E mail you an Access Code which must be typed into the Registration Form for all the features to be enabled Terminal Emulator Menu Commands The terminal emulator provides several menus of commands for controlling and customizing its function
217. upt Handler Function void OnTimerFired int arg Binder Object for Timer typedef void IntFtnType int arg FunctionHandler IntFtnType int TimerBinder OnTimerFired 0 Sbc6713e User s Manual 55 This is the installation of the handler in the program Set up a real time clock to send commands to host on Target channel Irq Timer0 intTimerO Timer0 Install TimerBinder Timer0 Enable false Turn on the clock at 5 hz DspClock Tclk0 50 0 150 0 Timer0 Enable true EDMA and QDMA Handling The TI C6000 processor supports a rich powerful DMA engine to move data without CPU intervention There are two kinds of DMA allowed One EDMA is full featured but can take some time to set up QDMA is TT s facility for quick DMA movement of data It 1s similar to a normal DMA transfer except that it is software triggered and performs only a single transfer No linking of blocks is permitted with QDMA It also is faster to initiate as only a few registers need to be set to start a new transfer Both kinds of DMA use a set of registers to define the configuration of a DMA transfer By properly configuring the settings many different transfer types can be performed such as interelaved data two dimensional arrays and so on See the TI Peripheral Library guide for more information on configuring EDMA and QDMA The QDMA has a single set of configuration registers so only one QDMA may be in pr
218. usb dvr f TMS320C5500 CaCCStudioldriversvsdgoSSxxusb dvr f Tws320c6400 CcacCsStudiotriversisdgoB400usb_11 dwr f Tws320c6200 CACCStudio driversisdgobxush dvr f TMS320C6700 f Tws320c6210 CaCCStudiotdriversvsdgo amp xusb dvr caccstudiowriversisdgoBxusb dwr C ACCStudioWriversisdgoBxush dvr f Tws320c6720 CACCStudiotdriversisdgo67 2xUSB dvr fe sni C ACCStudio drivers sdgoarm 1usb dvr ARM C ACCStudioldriversisdgoarm7usb dvr fe nv BYPASS Ccaccstudiowriversisdgoarm9usb dwr Sbc6713e User s Manual Use the property sheet to find the Gel file from Innovative for your specific board Property Value C Mnnovative SBCB713e llbx N Master Slave Change property value as necessary in the right column Summary Cancel Close the processor and choose another processor This will be a bypass for the DM642 Set the bypass for 38 bits For TMS6713 bypass use 42 bits on the first processor the second processor will be a 64xx and the gel file from II for the DM642 For the Quadia use another C6400 type processor totaling 4 processors All 4 will use the same GEL file from II Bypass Name Number of bits in the instruction register 36 H Your system will look similar to this Save the configuration and quit System Configuration E My System My Multi Processor f Tws320ce710 0 BYPASS 0 Current Proccesor Type Driver Location Device Type Bypass 38 bit
219. w application with File New Project with Widows Forms Application New Project Project types Templates Visual C isual Studio installed templates ATL CLR SB ASP NET Web Service General mon Console Application MFC SQL Server Project Smart Device A Windows Forms Control Library Win32 EH Other Languages My Templates Other Project Types Search Online Templates A project for creating an application with a Windows user interface Class Library FE CLR Empty Project GEI Windows Forms Application a Windows Service Name lt Enter_name gt Location Cisome folder wv Browse Solution Create new Solution Add to Source Control Sbc6713e User s Manual Y Create directory For solution 17 Project Properties Alt F7 Configuration Properties El Project Defaults Configuration Type Application exe Use of MFC Use Standard Windows Libraries Use of ATL Not Using ATL Minimize CRT Use in ATL No Character Set Use Unicode Character Set Common Language Runtime support Common Language Runtime Support clr Whole Program Optimization No Whole Program Optimization C General Additional Include Directories Malibu PlotLab Include for graph scope display Code Generation Run Time Library Multi threaded Debug DLL Mdd Precompiled Headers Create Use Precompile Headers Not Using Precompiled Headers Linker Addit
220. wUser exe applet to provide Innovative Integration with your registration information you will receive Sbc6713e User s Manual Registration Information E User Name ra lilt Lag Henderson p Emai Address Telephone Country Code Area Code Number Extension Fax pe Code Number Company Name Innovative Integration Address City State Country Postal Code Product Board Viste El Access Code 935846148 2 Help ES Register Now Ok 20 The unlock code necessary for unrestricted use of the Host applets A WSC tech support service code enabling free software maintenance downloads of development kit software and telephone technical hot line support for a one year period Sbc6713e User s Manual 21 Reserve Memory Applet ReserveMemDsp exe Each Innovative PCI based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use depending on the rates of bus master transfer traffic which each baseboard will generate Applications operating at transfer rates in excess of 20 MB sec should reserve additional contiguous busmaster memory to ensure gap free data acquisition Sbc6713e User s Manual Reserve Memory for Dsp Baseboard 4 f si Number Installed Matador family Type System 2048 y BM Region Size KB 2048 sz Rsv Region Size KB M Configuration Total physical memory

Sbc6713e User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents