Texas Instruments DEM-DAI3010 User's Manual
Contents
1. WW 1 2 FT SW006 swoo5 FMTO FFC DSS109 085108 ou 3 VW Sr J 9AMEP1 CLKO 4 14 L ok MODE BEE css 1 67 814 MDAT Perea en ae COPY C H u mono e L SO Lo ws 418 1 oe E L M 10 Ll anno 5015 MN A core RA002 EE E 47k x3 1 20 L Bis gt Vcc ech SCLK 2 lt p 19 A 3 18 17 BCK 4 17 10 uF 16V 5 16 6 15 LRCK 7 TX DATA 8 N 13 9 12 0004 0174096 ano q 4 A 0005 74HCT244 CN001 4 FFC 10AMEP1 ADFLG ADFLG gt BRATEO BRATEO 2 BRATEN 9 9 51004 BFRAME __ 5 EMFLG FT1E 2M 1 Clock mode select tO R003 3 Ee _ tal CKTRNS 47k 004 AAA Su Y cule 470 1 28 det ADFLG CKSEL BRSEL AW D 2 27 Autd A 0001 BRATEO UNLOCK 188133 3 C010 CSBIT tL 9 1 1 0011 tour URBIT 5 077 Nk 008 4 25 16v EMFLG 04 10uF po SWoo2 5 24 10 O al Firm 46 A 6 2 co19 C005 Sine penn g2. 1 5 vi Chapter 1 Description The DEM DAI3010 is an evaluation board for the PCM3010 24 bit 96 KHz ADC and 192 kHz DAC stereo codec This board includes not only the PCM3010 but also analog I O terminals analog filter circuits and an S PDIF digital I O circuit that is useful for codec evaluation S PDIF I O circuits consist of a 24 bit 96 kHz digital audio interface receiver DIR1703 and a digital audio interface transmitter DIT4096 and include optical TOSLINK and coaxial S PDIF digital connectors Removing shorting plugs from the pins of a header breaks the connection between the S PDIF I O circuits and the PCM3010for easier PCM3010 device evaluation Topic Page ber Block Diagram aa 1 2 1 2 Use of the DEM DAI39010 1 3 1 3 Settings and Connections for Basic Operation 1 4 1 42 Shela DE HOUSE 1 5 Block Diagram 1 1 Block Diagram Figure 1 1 DEM DAI3010 Block Dlagram System Clock X tal Frequency Data Format Clock Mode System Clock SW003 5 004 JP001 DAC Output S PDIF Input L ch Output LPF IN EN PCM3010 DIR1703 Slave Only Rech Output COAX IN 0 LPF 0 ADC Input 24 576 MHz JP105 L ch 1Vrms 33 S PDIF Output L ch 2Vrms LPF OPT OUT DIT4096 JP106 R ch 1Vrms COAX OUT 74HCT244 89 R ch 2Vrm
3. 12k 119 100pF ANN C117 330pF R117 4 7k W R111 R109 SC cct 3 3k 2 4k H 121 E 10uF 4 PLAN N JP105 Wz nev De 2 Ae C123 3 Las 18 peo SCH 27 tournev NE i Q U102 nev OPA2134PA c125 0102 2 2 10uF 16V OPA2134PA 1 2 CN103 Aer RCA R114 1 2k C120 100pF C118 R118 4 7k Rito CN102 22 2 4k RCA pj ER le JP106 S CH i AN de 16 1 AAA EX HL 124 1800pF 55 CH 10 16 0103 5 4 7k u 0103 OPA2134PA ous OPA2134PA 2 2 27 10uF 16V 12 dE CN104 O 0104 2198 128 PCM3010 Can 10UF neu R105 15k 10uF C127 C101 AV neu O 1uF 1 gt 24 10uF Vint Voom TR GEN 109 JP103 2 23 101 VINR 22 135 d 22 C130 Vrer o 1200F 4 21 ame EZ G mz z R103 5 Vcc1 AGND2 QU 16Y ik C107 120pF C132 6 mm HUF 2 R107 CN105 T AGND1 DEMPO JP101 6e AN 27 tourney 6 9 2 100 RCA gisi 1 8 2 9 0 1uF 8 17 3 EMT PDWN 1 105 9 16 7 103 1200 TEST SCKI DD OPA2134A 10 15 92000 12 LRCK 14 Di 14 O AVcc 12 13 R120 R121 oo GH 0134 101 102 FFC 48MEP1 em 0 220 0 1uF TOUR 16V JP103 104 FFC 2BMEP1 m Wr 4 4 ev C102 10uF R106 15k Ze EHS nev Mu gt R119 220
4. 23 006 T JP001 10uF 10uF T R005 7 22 12 co12 FFC10 LO FILT H SMERI 16V LS nev 1M 8 21 0 068uF 1 xT RST CH co 9 20 05 24 576MHz CKTRNS DIN 8200pF LT on PX 1 x2pcs TT 1 19 SE Come C007 11 18 oH BCKO BCK BFRAME o 18 18p F 12 17 c020 DOUT RX DATA EMFLG o e Er 0003 REG1117 3 3 lt SCFO URBIT 2 IN 3 hev 001 INL seg 6 t d GND ch 5 E 1 CO 04 Com j 1 0002 DIR1703 de on pote 1 ei 14 COAXin gt Vcc 0003 2 13 100 16 Do R001 oH MIO _ gt 51 am F 3 12 om Rooz Y a xB 3 7 20 okm 2 2k 5 10 XB 3 7 20 TX DATA 6 Y 9 el Ho put SOK 0001 Wa pg ewoo BCK 9 74HCU04 RID ZM LRCK MOTHER gt TRX DATA rrorLERcK Hot 0 777 Printed Circuit Board and Schematic 2 7 2 8
5. A C110 104 Aco JP107 2157575 JP102 FFC 12BMEP1 2 2 9 4 120 oe FMT1 R102 GND 3 Se 27 DEMPO 5108 C108 120pF 2 1k CR SCLK Se 1 JP102 BCK SW101 e PDWN v2 lo DSS105 1 4 0106 U101 1200pF RX DATA 1200pF op OPA2134A 2 2 o Printed Circuit Board and Schematic DEM DAI3010 Schematics Figure 2 5 DEM DAI3010 Regulator Connector and Ext F 056 B2P VH CN055 CN054 CN053 CN052 CN051 Von banana jack banana jack banana jack banana jack banana jack Black Red Blue Green Orange AVcct 2 1 0051 057 REG1117 3 3 FFC 2BMEP1 3 OUT IN GND T ose C053 E 1 L co55 cost C054 056 ap dp 100uF 100uF lt 100uF 10 16 d 16 JE Hey CN060 57LE 40360 7700 D3 S 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Ee 9 99 91919 19 20 22 E F 27 2 E 31 32 3 34 35 36 062 0054 y 7
6. DAI3010 at shipping 1 3 1 2 2 Howto Connect Power Supplies to the DEM DAI3010 1 3 1 3 Settings and Connections for Basic Operation 1 4 154 gt Setting FUNCUONS ora a 1 5 1 4 1 Function Setting Switches and Header 1 5 1 4 2 Detailed Explanation of Function Setting Switches and Header Pins 1 6 Printed Circuit Board and Schematic 2 1 2 1 DEM DAI3010 Printed Circuit Board 2 2 2 2 DEM DAI3010 Schematics 2 5 Figures DEM DAI3010 Block Dlagram 1 2 DEM DAI3010 SIIKSCreen u vend saree en Lee n ren 2 2 DEM DAI3010 Top View 2 3 DEM DAI3010 Bottom 2 4 DEM DAI3010 Analog Section 2 5 DEM DAI3010 Regulator Connector and Ext IF_ 2 6 DEM DAI3010 Digital Section Digital Audio Interface 2 7 Initial Settings of the DEM DAI3010 at Shipping 1 3 Power Supply Terminals and Supply Voltage Depending on CNO57 Setting 1 3 Switches and Header Pins of the DEM DAI3010
7. THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES Tl currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the EVM User s Guide and specifically the EVM Warnings and Restrictions notice in the EVM User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For further safety concerns please contact the application engineer Persons handling the product must have electronics training and observe good laboratory practice standards No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 15 V and the output voltage range of 15 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are qu
8. kit being sold by Tl is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use As such the goods being provided may not be complete in terms of required design marketing and or manufacturing related protective considerations including product safety measures typically found in the end product incorporating the goods As a prototype this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may not meet the technical requirements of the directive Should this evaluation kit not meet the specifications indicated in the EVM User s Guide the kit may be returned within 30 days from the date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO
9. 49 5 INSTRUMENTS DEM DAI3010 User s Guide April 2003 DAV Digital Audio Speaker SLEU036 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right
10. 4LVC244 051 C244 20 Swo53 i 47kx5 5 2 lt p 9 U052 pen 2 KEE 8 E 179 3 AW MDI 4 7 e A e MDO 3 4 1 4 3 MDI 6 1 5 JEDE C087 ANA a gt gt t 0 1uF C058 ML gt 10uF My SE 11113 lt 6V 9 2 CN05 8 IT 5 10 1 RCA A GND y R052 374 614 2 AN SW051 e FT1D 2M SW052 307 Optical REC out FT1D 2M A lt REC out TROO1 oS y DIT REC out select DA 02 DIT out C061 DIT out oe Wee OPT COAX out TORX179P select COAXin gt 1 C059 2 3 4 5 0 1uF C060 our T 16V ad CN059 RCA pj 97 R053 75 2 6 Figure 2 6 DEM DAI3010 Digital Section Digital Audio Interface DEM DAI3010 Schematics
11. 5 006 Because system clock frequency is 256 fs the ADC section operates at fs 96 kHz To operate the ADC section at a different fs the crystal X001 connected to DIR1703 must be changed The system clock setup can be changed if required The load capacitance used with the crystal is dependent on the crystal properties Therefore when the crystal is changed the capacitance of C006 and C007 must be selected to match the crystal specification When S PDIF I O is not used the PCM3010 is evaluated alone Remove all shorting plugs attached to 107 Setting Functions Data and a clock are supplied to the PCM3010 side of JP107 Setup FMTO and FMT1 of SW101 according to the data format to be used J Setup DEMPO and DEMP1 of SW101 for the desired de emphasis of the DAC section and PWDN for the power down setting 1 4 Setting Functions All functions of the devices PCM3010 DIR1703 DIT4096 on the DEM DAI3010 are controlled by DIP switches or header pins on this PCB Therefore the DEM DAI3010 does not require a microcontroller or software to transmit data to internal function setting registers For specific information on any device see the data sheet for that device 1 4 1 Function Setting Switches and Header Pins Table 1 3 Switches and Header Pins of the DEM DAI3010 SW JP No SW001 Item Shape Toggle switch S PDIF input selection optical coax SW002 SW003 SW004 Reset of DIR1703 a
12. 5 V and 15 V power supplies Power is supplied to this board by five binding posts one each for Vcc 5 V AVcc 15 15 V and two for ground from stabilized dc power supplies Vpp 3 3 for the PCM3010 is normally generated by an onboard voltage regulator IC from Vcc 5 but it is possible to supply 3 3 V directly do so open CN057 then supply V to 056 and 5 V to CNO54 If 3 3 V is supplied externally 5 V must still be provided to CNO54 in order to supply the analog section of the PCM3010 To avoid latch up of the PCM3010 ensure that Voc and Vpp are powered up simultaneously Table 1 2 Power Supply Terminals and Supply Voltage Depending on CN057 Setting Power Terminal CN051 orange CNO052 green CN053 blue CN054 red CN055 black CNO56 2 pin connector CN057 Closed Default 057 Open 15 V 15V 0 V ground 0 V ground 15 V 15 V 5V 5V 0 V ground 0 V ground Open no connection 3 3V Description 1 3 Settings and Connections for Basic Operation 1 3 Settings and Connections for Basic Operation The PCM3010 is an LSI codec containing an ADC and a DAC Connections and settings depend on the evaluation object ADC or DAC and the setup should be checked carefully Following are example settings for three typical evaluation situations Note that when using S PDIF I O the optical and coaxial input corresponds to fg 96 kHz When the DAC section of PCM3010 i
13. Products BAL HIHI x S PDIF input 2 2 DEM DAI3010 Printed Circuit Board Figure 2 2 DEM DAI3010 Top View 2 3 Printed Circuit Board and Schematic DEM DAI3010 Printed Circuit Board Figure 2 3 DEM DAI3010 Bottom View EI DIETA 2 4 2 2 DEM DAI3010 Schematics Figure 2 4 DEM DAI3010 Analog Section DEM DAI3010 Schematics
14. ed to the PCM3010 Setting Functions CN057 Vcc supply selection for the PCM3010 This jumper determines whether Vcc for the PCM3010 is supplied from a 3 3 V regulator on this board 0051 or via an external power supply terminal 056 In the initial setting Vcc is supplied from the onboard regulator When Vcc for the PCM3010 is to be provided by an external power supply the jumper is removed from CN057 and 3 3 V is supplied to CNO56 If 3 3 V is supplied externally 5 V must still be provided to CNO54 in order to supply the analog section of the PCM3010 To avoid latch up of the PCM3010 ensure that Vcc and Vpp are switched on simultaneously at start up Description 1 9 Chapter 2 Printed Circuit Board and Schematic This chapter presents the DEM DAI3010 printed circuit board and schematics Topic Page 21 DEM DAI3010 Printed Circuit Board 2 2 2 2 DEM DAI3010 Schematics 2 5 2 1 DEM DAI3010 Printed Circuit Board 2 1 DEM DAI3010 Printed Circuit Board Figure 2 1 DEM DAI3010 Silkscreen input _ a put Loch output Sch Siren input Rech Lech Vree g YA aro e Wy ait mt L PF 1 Rev Direct 6487 e 301 from Texas Instruments 5 Burr Brown
15. estions concerning the input range please contact a Tl field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a field representative During normal operation some circuit components may have case temperatures greater than 55 C The EVM is designed to operate properly with certain components above 55 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated EE O N aA Contents DESCHIPTION uuu ETA d Re usus ed eer Tue ute 1 1 ha Block Diagram uns see are an pene agai en 1 2 1 2 Use of the 1 010 1 3 1 2 1 Initial Settings of the DEM
16. nd DIT4096 Format and system clock setting of DIR1703 Pushbutton switch 4 pole DIP switch Output clock selection of DIR1703 X tal Auto PLL SW005 SW006 Format and system clock setting of DIT4096 Toggle switch 4 pole DIP switch Channel status data setting of DIT4096 SW051 SW101 S PDIF output selection optical coax 10 pole DIP switch Toggle switch Setting of PCM3010 format de emphasis power down JP001 5 pole DIP switch 2x5 header Crystal frequency and system clock setting of DIR1703 JP107 JP101 Connection of S PDIF I O circuit and PCM3010 2x7 header 2 2 header Cutoff frequency setting of DAC output filter L ch JP102 2 2 header Cutoff frequency setting of DAC output filter R ch JP103 JP104 Cutoff frequency setting of DAC output filter L ch 2x1 header 2x1 header Cutoff frequency setting of DAC output filter R ch JP105 Selection of L ch ADC input terminal CN101 CN103 JP106 2 2 header Selection of R ch ADC input terminal CN102 CN104 CN057 The way of power supply of PCM3010 Vpp 3 3 V 2 2 header 2x1 header Note Therelation between the DIP switch setting ON OFF and the setting of the IC input portis printed on the PCB The DIP switch H position does not always set the IC input port level HIGH Toggle switch settings are printed on the PCB Description 1 5 Setting Functions 1 4 2 Detailed Explanation of Function Setting Switches a
17. nd Header Pins SW001 Switch to select S PDIF input connector optical coaxial Selection of the S PDIF signal that is routed to the DIR1703 DIN port SW002 Reset switch for the DIR1703 and DIT4096 Pushing this switch resets the DIR1703 and DIT4096 to the initial state A reset circuit operates at the time of power supply connection resetting the DIR1703 and DIT4096 automatically Therefore it is not usually necessary to operate this switch SW003 Switch for setting the DIR1703 system clock and output data format SCF1 SCFO System Clock L L 128 fs L H 256 fs initial stting H L 384 f H H 512 f FMT1 Output Data Format L L 16 bit right justified MSB first L H 24 bit right justified MSB first H L 24 bit left justified MSB first H H 24 bit 125 initial setting SW004 Switch for setting the DIR1703 output clock source Position Output Clock SCK BCK LRCK X tal Crystal clock PLL PLL clock Auto PLL PLL locked crystal PLL unlocked Note When using the DIR1703 as a master clock for the ADC this switch must be set to X tal When inputting S PDIF data demodulated by the DIR1703 into the DAC set this switch to Auto or PLL SW005 Switch for setting the DIT4096 system clock and input data format Note that the OFF state of this switch sets a HIGH level CLK1 CLKO System Clock L L Not used L H 256 fg initial setting H L 384 15 H H 512 5 Setting Functions FMT1 FMTO Input Data F
18. or other Tl intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice Tl is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated EVM IMPORTANT NOTICE Texas Instruments provides the enclosed product s under the following conditions This evaluation
19. ormat L L 24 bit left justified MSB first L H 24 bit 125 initial setting H L 24 bit right justified MSB first H H 16 bit right justified MSB first SW006 Switch for setting channel status data of the DIT4096 Note that the OFF state of this switch sets a HIGH level Channel status data can set up if needed Moreover it is also possible to connect a microcontroller to 002 and to write in channel status data with the microcontroller See the DIT4096 data sheet TI literature number SBOS225 for details about the contents of a setting SW051 Switch to select the S PDIF output connector optical coaxial An S PDIF output connector is chosen from optical 0052 and coaxial CNO58 The optical and coaxial output terminals cannot be used simultaneously SW101 Switch for setting the functions of the PCM3010 All the functions of PCM3010 are set up with this switch Functions that can be set are the audio serial data format the DAC section de emphasis and power down control EMT DAC Input Data Format ADC Output Data Format L L 24 bit right justified MSB first 24 bit left justified MSB first L H 16 bit right justified MSB first 24 bit left justified MSB first H L 24 bit left justified MSB first 24 bit left justified MSB first H H 24 bit 125 initial setting 24 bit 125 initial setting DEMP1 DEMPO DAC De Emphasis L L De emphasis ON 44 1 kHz L H De emphasis OFF initial setting H L De emphasi
20. requency of the LPF inserted in the DAC output is chosen by these jumpers The initial setting all pins shorted is 54 kHz at the time of shipment The cutoff frequency with all JP101 JP104 jumper pins open is 108 kHz JP105 JP106 Selection of ADC input connectors CN101 and CN102 or CN103 and CN104 There are two pairs of ADC input connectors One pair is coupled to the PCM3010 through capacitors C121 C122 The other pair is connected through a 103 kHz cutoff LPF and a 6 dB amplifier The input connectors are chosen by JP105 and JP106 When the jumpers are on Direct IN then the left and right channel inputs on CN103 and CN104 respectively bypass the LPF When the jumpers are 6 db LPF then the left and right channel inputs on CN101 and CN102 respectively go through the LPF to the PCM3010 ADC Full Scale Input Connector No Details L ch 2 V rms CN101 L ch ADC input with LPF R ch 2 V rms CN102 R ch ADC input with LPF L ch 1 V rms CN103 L ch ADC input without LPF R ch 1 V rms CN104 R ch ADC input without LPF JP107 Connection of PCM3010 and S PDIF I O circuits This is the header pin which connects the clock input and data I O of the PCM3010 with an S PDIF I O circuit All pin positions have shorting plugs installed at the time of shipment For evaluating the PCM3010 with other DSPs DIRs and DITs JP107 jumpers are removed Connection to the alternative devices is made through the row of JP107 pins that is wir
21. s System Clock Data Format Channel Status System Clock Data Format Power Down 15 V gt LPF Circuits 5V PCM3010 Vcc and DIR1703 DIT4096 TOSLINK 057 3 3V PCM3010 Vpp 3 3V 1 2 Use of the DEM DAI3010 Use of the DEM DAI3010 DEM DAI3010 is shipped with standard settings preset Therefore connecting power supplies 15 V 15 and 5 V is the only requirement to prepare the board for use unless nonstandard settings are desired 1 2 1 Initial Settings of the DEM DAI3010 at shipping Table 1 1 Initial Settings of the DEM DAI3010 at Shipping Item Power supply voltage Power supply terminals Connection of PCM3010 and S PDIF I O DIR1703 system clock SCK DIR1703 output audio data format DIR1703 crystal clock frequency DIT4096 system clock SCLK DIT4096 input audio data format PCM3010 system clock PCM3010 I O audio data format PCM3010 power down function PCM3010 de emphasis function DAC PCM3010 DAC cutoff frequency PCM3010 ADC input terminal selection Initial Setting at shipping 15 V 15 V and 5 V close CN57 CN51 CN55 open CN56 DIR1703 and 0174096 connected with JP 107 256 fs 12s 24 576 MHz load capacitance 18 pF 256 fs 125 Automatic selection no setting required 125 Disabled Disabled 54 kHz JP101 JP104 are closed CN101 CN102 2 V rms input with LPF 1 2 2 How to Connect Power Supplies to the DEM DAI3010 The DEM DAI3010 requires 5 V 1
22. s ON 48 kHz H H De emphasis ON 32 kHz PDOWN Power Down Control L Power down mode H Nomal operation initial setting JP001 Setup of the crystal frequency and system clock for the DIR1703 When the system clock and the frequency of the crystal for the DIR1703 are changed shorting plug is inserted in only one position of JP001 according to the following tables In order to avoid the loss of a shorting plug which is not being used the plug is put in the header pin position labeled as OPEN Because 24 576 MHz is used for a quartz crystal and the system clock is set as the 256 fs output in initial setting at the time of shipment the shorting plug is attached in the CSBIT position Description 1 7 Setting Functions JP001 setting table DIR1703 system clock and crystal frequency fs in X tal Mode 128 fs 256 fs 384 fs 512 fs BRSEL Jumper Position 32 kHz 4 096 MHz 8 192 MHz 12 288 MHz 16 384 MHz BFRAME 44 1kHz 5 6448 MHz 11 2896 MHz 16 9344 MHz 22 5792 MHz EMFLG 48 kHz 6 144 MHz 12 288MHz 18 432 MHz 24 576 MHz OPEN jumper 88 2kHz 11 2896 MHz 22 5792 MHz 33 8688 MHz 45 1584 MHz URBIT 96 kHz 12 288 MHz 24 576 MHz 36 864 MHz 49 152 MHz CSBIT Sample of a of JP001 setting Target system clock 256 fs and fg 48 kHz in the X tal mode In the preceding table the frequency listed where the 256 fg column intersects the 48 kHz row is 12 288 MHz JP101 JP104 Cutoff frequency setting of DAC output post LPF The cutoff f
23. s evaluated with S PDIF input signal the PCM3010 operates as a slave of the DIR1703 PLL clock Close all pins of JP107 with shorting plugs Input an S PDIF signal into the optical 0053 or coaxial CNO59 connector CN105 L ch and CN106 R ch are the analog signal outputs Choose an S PDIF input terminal optical coaxial with the S PDIF input switch SW051 Set the clock mode switch SW004 to PLL or Auto The cutoff frequency of the LPF can be changed by JP101 JP102 JP103 and JP104 All these jumpers are shorted at the time of shipment which sets the cutoff frequency to 20 kHz When the ADC section of PCM3010 is evaluated with S PDIF output signal the PCM3010 operates as a slave of the DIR1703 crystal clock Short all pins of JP107 with shorting plugs Connect an analog signal to CN101 CN102 using an LPF or to CN103 CN104 using only a coupling capacitor without an LPF Select the analog input terminal by changing by the settings of JP105 and JP106 Setup at the time of shipment is for CN101 and CN102 A Toslink 0052 a pin jack 058 are the S PDIF digital output terminals Select the digital output connector by setting the S PDIF output switch SWO51 Simultaneous use of optical and coaxial outputs is impossible Set the clock mode switch SW004 to X tal The X tal mode of DIR1703 is used as a master clock for the ADC and DIT Set up the channel status data using
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