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Intel S3420GP User's Manual

1. CPU Power connector Description Description A Slot 1 32 Mbit 33 MHz PCI Q System FAN2 and System FAN 3 B Slot 2 PCI Express Gen1 x1 x4 connector R CPU connector Intel Server Board S3420GPLX only C Intel RMM3 Connector Intel Server Board S CPU Fan connector S3420GPLX only D Slot 3 PCI Express Gen1 x4 PCI Express T USB SSD connector Gen2 compliant E Slot 4 PCI Express Gen2 x4 x8 connector U SAS Module connector Intel Server Board x8 connector Intel Server Board S3420GPLX S3420GPLX only only F Slot 5 PCI Express Gen2 x8 x8 connector V System FAN 1 G Slot 6 PCI Express Gen2 x8 x16 connector W IPMB H CMOS battery X SATA SGPIO l Ethernet and Dual USB COMBO Y HSBP J Ethernet and Dual USB COMBO Z USB Floppy K System FAN 4 AA Six SATA ports L Video port BB Internal USB Connector M External Serial port CC Front Panel Connector N Main Power Connector DD Internal Serial Port O P DIMM slots Revision 1 0 Intel order number E65697 003 Overview IntelP amp P Server Board S3420GP TPS 2 2 2 Intel Server Board S3420GP Mechanical Drawings ETHERNETLOGAL USB COMBO a 3 PLACES Jurper Header 5 PLACES p GCMALIMM3 CONNECTOR 4 PIN POSER CONSECTCR 24 PIN FRONT PAMEL PIN PORER CONNECTOR INTERNAL 056 INTERNAL US SATA CONNECTOR PLACES 4 PIM Ire CONNECTOR HSBP COMMECTOR 30P10 CONNECTOR INTERMA
2. 80 Table 53 Front Panel Status LED Behavior Summary 84 Table 54 POST Code Diagnostic LED Location 2nnrnennnnnnnnnnnnnnvnnvnnnnnnvnnnnnnannnnennnnennnnennnnennenn 85 Table 55 Server Board Design Specifications eese nnne 86 Table 56 Intel Xeon Processor TDP Guidelines ccccesccssesssecsescsescsescseseeceeeeseseeeeeseeenees 88 Table E Load Ratings Tendida cid det 88 Table 58 Voltage Regulation Limits eo tees eet RE dario 89 Table 59 Transient Load Requirement sss enne 89 Table 60 Capacitve Loading Conditions einer eee 90 Table 61 Ripple and Noise u u a eie eese stance dis He keine 90 Table 62 Output Voltage Timing soi Er eh IER Reb DREAM a 91 Table 63 Tur On Off TIMING P Pm 92 Table 64 Over Current Protection OCP u nnnc inne 93 Table 65 Over voltage Protection OVP Limits 1arnnnnnnnnnnnnnnnvnnnnnvnnnrrnnnnnnnnnvnnennnrnnnnnnnnnnnnn 93 Table 66 Integrated BMC Core Gensors cece cece eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeres 105 Revision10 WWW Xi Intel order number E65697 003 List of Tables IntelPEP Server Board S3420GP TPS Table 67 POST Progress Code LED Example ssssssrsresrrtrrrttrrttnrtnnttnnrnnnnnnn nenn nnna Ennn Ennn nenna 109 Table 68 Diagnostic LED POST Code Decoder eect eteeeeeeeeeeeeseeeeeeeeeeeeeeeeeees 109 Table 69 POST Error Messages and Han
3. 27 Table 9 BIOS Setup Page Layout 36 Table 10 BIOS Setup Keyboard Command Bar sese 37 Table 11 Setup Utility Main Screen Fields u 39 Table 12 Setup Utility Advanced Screen Display Fields 000nnnnennneeeneeeee nenene neneeese ereenn eee 41 Table 13 Setup Utility Processor Configuration Screen Fields 42 Table 14 Setup Utility Memory Configuration Screen Fields 0 eeeeeeeeeeeseeeseeeneeeeeeees 45 Table 15 Setup Utility Mass Storage Controller Configuration Screen Fields 46 Table 16 Setup Utility Serial Ports Configuration Screen Fields 48 Table 17 Setup Utility USB Controller Configuration Screen Fields suus 49 Table 18 Setup Utility PCI Configuration Screen Fields 51 Table 19 Setup Utility System Acoustic and Performance Configuration Screen Fields 52 Table 20 Setup Utility Security Configuration Screen Fields 53 Table 21 Setup Utility Server Management Configuration Screen Fields 55 Table 22 Setup Utility Console Redirection Configuration Fields sss 57 Table 23 Setup Utility Server Management System
4. Jr lr lr E Jr rs DIMM_C3 Correctable ECC error encountered ision 1 0 Intel order number E65697 003 Appendix D POST Code Errors Response Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause after 10 occurrences Pause Pause Pause Pause Pause Pause Pause 115 Appendix D POST Code Errors IntelPEP Server Boa Error Code 85A7 85A8 85A9 85AA 85AB 85AC 85AD 85AE 85AF 8601 8602 8603 8604 9000 9223 9226 9243 9246 9266 9268 9269 9286 9287 9288 92A3 92A9 92C6 92C7 92C8 94C6 94C9 9506 95A6 95A7 95A8 9609 9641 9667 9687 96A7 96AB 96E7 0xA022 0xA027 0xA028 0xA421 116 DIMM_D1 Uncorrectable ECC error encountered PCI component encountered a read error Intel order number E65697 003 rd S3420GP TPS Response Pause Pause Pause Pause Pause Pause Pause Pause Pause No Pause No Pause No Pause No Pause Pause No Pause No Pause No Pause
5. Advanced USB Configuration Detected USB Devices Total USB Devices i USB Controller Enabled Disabled Legacy USB Support Enabled Disabled Auto Port 60 64 Emulation Enabled Disabled Make USB Devices Non Bootable Enabled Disabled USB Mass Storage Device Configuration 10 seconds 20 seconds 30 seconds 40 Device Reset timeout seconds Mass Storage Devices Mass ige devices one line device gt Auto Floppy Forced FDD Hard Disk CD ROM USB 2 0 controller Enabled Disabled Figure 21 Setup Utility USB Controller Configuration Screen Display Table 17 Setup Utility USB Controller Configuration Screen Fields ee USB Information only Shows the number Devices of USB devices in the system USB Controller Enabled Enabled All onboard USB controllers are turned on and Disabled accessible by the OS Disabled All onboard USB controllers are turned off and inaccessible by the OS Legacy USB Enabled USB device boot support and PS 2 emulation for USB Grayed out if the USB Controller is Support Disabled keyboard and USB mouse devices disabled Auto Auto Legacy USB support is enabled if a USB device is attached Port 60 64 Enabled 1 0 port 60h 64h emulation support Grayed out if the USB Controller is Emulation Disabled Note This may be needed for legacy USB keyboard disabled support when using an OS that is USB unaware Make USB Enabled Exclude USB in Boot Table Grayed out if the USB Controller is
6. Enabled Display the logo screen during POST Disabled Display the diagnostic screen during POST Enabled Go to the Error Manager for critical POST errors Disabled Attempt to boot and do not go to the Error Manager for critical POST errors System Date has configurable fields for Month Day and Year Use Enter or Tab key to select the next field Use or key to modify the selected field System Time has configurable fields for Hours Minutes and Seconds Hours are in 24 hour format Use Enter or Tab key to select the next field Use or key to modify the selected field Information only Displays the total physical memory installed in the system in MB or GB The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs If enabled the POST Error Pause option takes the system to the error manager to review the errors when major errors occur Minor and fatal error displays are not affected by this setting The Advanced screen provides an access point to configure several options On this screen the user selects the option they want to configure Configurations are performed on the selected screen and not directly on the Advanced screen To access this screen from the Main screen press the right arrow until the Advanced screen is chosen 40 Intel order number E65697 003 Revision 1 0 IntelPEP Server Board S3420GP TP
7. or rotes 51M NO PIM THES HOLE COMPONENT ZOME 9 PLACES On 400 16MM GROUND PADS PLACES COMPONENT HEIGHT amp ESTSICION 0 250 mar 5 PLACES COMPONENT HEIGHT RESTRICION 0 50 X 4 380 9 6900 te MAX COMPONENT HEIGHT MAX COMPONENT HEIGHT THEN WAY COMPONENT HEIGHT 0 130 3 30MM mat COMPONENT HEIGHT OMPOSENT HEIGHT SESTRICION 200 WAX 12 0 056 42MM 4 PLACES PLATED MEA FOR ANCHORS SOLDERING 2 098 2 Sum MAX COMPONENT HEIGHT 1 0 158 4 0344 CPU HEATSINE MOUNTING HOLE 1 0 121 3 aam CPU ILM WOURTING HOLE COMPONENT HEIGHT RESTRICION 200 MAN D 00M mar COMPONENT HEIGHT ST 44480 Mar COMPONENT HEIGHT 9 370 9 30301 MAX COMPONENT HEIGHT QAT I 2000 mar COMPONENT HEIGHT PCH HEATSINK CLIP AR 3 11 800 C15 due MAX COMPONENT HEIGHT IEATSIMK ANCHOR SOLDERING ARE NO COMPONENT ALLOMED PLACES amp 00 0 DOW mat COMPONENT HEIGHT Z SEA E AE Zl 1 go 236 8 000 NO COMPONENT ZONE FOR 420 OM CARD SETENTION DN N NN NN N F VIA WN I RED E 100 2 Same Z COMPONENT HEIGHT RESTRICION 0 rat N NES 773 Z 2 P DARC MAX COMPONENT HEIGHT 0 000 z H MAX COMPONENT HEIGHT FOR AIR ur 0 2365 4900 Mar COMPONENT HEIGHT O 122 2 5400 MAX COMPONENT HEIGHT FOR 4 MODULE Figure 7 Intel Server Board S3420GP Primary Side Keepout Zone 10 R
8. s D IntelPEP Server Board S3420GP TPS PIA Platform Information Area This feature configures the firmware for the platform hardware PLD Programmable Logic Device PMI Platform Management Interrupt POST Power On Self Test 120 Revision 1 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Glossary Definition Power Supply Management Interface PWM Pulse Width Modulation Op QuickPath Interconnect Random Access Memory Reliability Availability Serviceability Usability and Manageability Reduced Instruction Set Computing Reduced Media Independent Interface Read Only Memory RTC Real Time Clock Component of ICH peripheral chip on the server board SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read Only Memory SEL System Event Log Server Input Output System Management BUS Server Management Interrupt SMI is the highest priority non maskable interrupt Server Management Mode Server Management Software Simple Network Management Protocol Server Platform Services Streaming SIMD Extensions 2 Streaming SIMD Extensions 3 Streaming SIMD Extensions 4 To Be Determined Thermal Design Power Thermal Interface Material UART Universal Asynchronous Receiver Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface URS Unified Retention System UTC Universal time coordinare VID Voltage Identification Vol
9. 9 4 Power Supply Output Requirements This section is for reference purposes only The intent is to provide guidance to system designers to determine a power supply for use with this server board This section specifies the power supply requirements Intel used to develop a power supply for the Intel Server System SR1630GP and SR1630HGP The following tables define two power and current ratings for this 350 W power supply The combined output power of all outputs should not exceed the rated output power The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions Table 57 350 W Load Ratings Voltage Minimum Continuous Maximum Continuous Peak 14A pu ev ETT fm A x 1 Notes 1 Maximum continuous total DC output power should not exceed 350 W 2 Peak total DC output power should not exceed 400 W 3 Peak power and peak current loading should be supported for a minimum of 12 seconds 4 Combined 3 3 V 5 V power should not exceed 100 W 88 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Design and Environmental Specifications 9 4 1 Grounding The grounds of the power supply output connector pins provide the power return path The output connector ground pins are connected to the safety ground power supply enclosure This grounding is designed to ensure passing the maximum allowed common mode noise
10. Readabl e Value Offsets Event Data Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset R T 105 Appendix B Integrated BMC Sensor Tables IntelP amp P Server Board S3420GP TPS Sensor Name Platform Sensor Event Event Offset Contrib Assert Readabl Event Rearm Applicabilit Type Reading Triggers To System De e Data y Type Status assert Value Offsets nc Voltage Threshold Degraded BB 1 1V P1 Vccp 02h 01h u I c nc HER Nl R T A fatal nc Voltage Threshold Degraded BB 1 1V P2 Vccp 02h 01h u I cnc raq R T A fatal nc Voltage Threshold Degraded BB 1 5V P1 DDR3 EEN Sch u l c nc 1 R T A fatal NC Stand by Voltage Threshold Degraded 02h 01h fu I c nc SNOR R T A BB 1 5V P2 DDR3 fatal nc uM i i fatal nc m um 8 i fatal nc hd um 8 i fatal Voltage Generic Ot kimit i BB Vbat 02h en exceeded Non fatal Trig Offset A X 106 Revision 1 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Appendix B Integrated BMC Sensor Tables Sensor Name Platform Sensor Event Event Offset Contrib Assert Readabl Applicabilit Type Reading Triggers To System De e y Type Status assert Value Offsets nc Voltage Threshold Degraded SES 02h 01h lu lenc il o Non fatal nc Voltage Threshold Degraded BB 5 0V STBY 02h 01h u c nc FSR fatal NC Voltage Threshold Degraded RE 02h 01h lu fene I C Non fa
11. 2 5 GT s point to point DMI interface to PCH LGA 1156 pin socket Two memory channels with support for 1066 1333 MHz ECC Unbuffered UDIMM or ECC Registered RDIMM Intel amp Xeon amp 3400 Series only DDR3 Intel Server Board S3420GPLX and S3420GPLC Up to 2 UDIMMs or 3 RDIMM Intel Xeon 3400 Series only per channel 32 GB max with x8 ECC RDIMM 2 Gb DRAM and 16 GB max with x8 ECC UDIMM 2 Gb DRAM Intel Server Board S3420GPV Up to 2 UDIMMs per channel 16 GB max with x8 ECC UDIMM 2 Gb DRAM Chipset Intel Server board S3420GPLX Support for Intel 3420 Chipset Plaftorm Controller Hub PCH ServerEngines LLC Pilot II BMC controller Integrated BMC PCI Express switch Intel Server board S3420GPLC Support for Intel 3420 Chipset Platform Controller Hub PCH ServerEngines LLC Pilot II BMC controller Integrated BMC External connections DB 15 video connectors DB 9 serial Port A connector Four ports on two USB LAN combo connectors at rear of board Internal connections Two USB 2x5 pin headers each supporting two USB 2 0 ports One 2x5 Serial Port B header Six SATA II connectors One Intel amp SAS Entry RAID Module AXX4SASMOD connector One SAS mezzanine slot supports for optional Intel Remote Management Module 3 Revision 1 0 1 Intel order number E65697 003 Overview IntelPEP Server Board S3420GP TPS Feature AJ20 AJ440 Description 232 Add in PCI
12. 3 2 3 Publishing System Memory cen e e ege EEN daten 17 3 2 4 Support for Mixed speed Memory Modules 18 3 2 5 Memory Map and Population Rules essen 18 3 3 Intel 3420 ChipSebPO ELA ost oot tA DNG CM Me 21 3 4 VO SUD Yi E 21 3 4 1 PCI Express Interface AAA 21 3 4 2 Serial ATA SUPPO u uuu et rte rere E e et o ea x bedroht than 22 3 4 3 USB 2 0 Suppott eerte Le eR o ERR ER RE ra SE 22 3 5 Optional Intel SAS Entry RAID Module AXXASASMOD aa 23 3 6 Integrated Baseboard Management Controller 23 3 6 1 Integrated BMC Embedded LAN Channel 25 3 6 2 Optional RMM3 Advanced Management Board sseeeeeeeeeeeeeeeeerrreessrrrrrrrnseeseeene 25 3 6 3 el Dee CEET 26 3 6 4 Floppy Disk Controller a eene nennen 26 iv Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Table of Contents 3 6 5 Keyboard and Mouse Support annrnnnnrnnnrnnnrnnnrnnnnnnnrnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnennnr 26 3 6 6 ET Mer e EE 27 3 7 Video Support iot i EH Fe bebe e de P de eR GR T DEPO comes e ER 27 3 7 1 ideg Modes HERE 27 3 7 2 Dual VIO ii A A 27 3 8 Network Interface Controller NIC a 28 3 8 1 GigE Controller 82574k E 28 S802 EC PHY3825 8DM u dte a osten aei dak acne gs netu onc aee sa 28 3 8 3 MAG Address Definifi iiu irisa tot
13. 3 8 1 GigE Controller 82574L The 82574 family 82574L and 82574IT are single compact low power components that offer a fully integrated Gigabit Ethernet Media Access Control MAC and Physical Layer PHY port The 82574 uses the PCI Express architecture and provides a single port implementation in a relatively small area so it can be used for server and client configurations as a LAN on Motherboard LOM design External interfaces provided on the 82574 e PCle Rev 2 0 2 5 GHz x1 e MDI Copper standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASETX and 10BASE T applications 802 3 802 3u and 802 3ab e NC SI or SMBus connection to a Manageability Controller MC e EEE 1149 1 JTAG note that BSDL testing is NOT supported 3 8 2 GigE PHY 82578DM The 82578 is a single port Gigabit Ethernet Physical Layer Transceiver PHY It connects to the Media Access Controller MAC through a dedicated interconnect The 82578DM supports operation at 1000 100 10 Mb s data rates The PHY circuitry provides a standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab The 82578 operates with the Platform Controller Hub PCH chipset that incorporates the MAC The 82578 interfaces with its MAC through two interfaces PCle based and SMBus The PCle main interface is used for all link speeds when the system is in an active state S0 while the SMBus is used only when the syste
14. 81 7 1 1 Clearing the CMOS vivan diia 81 7 1 2 Clearing the PASSION arverett 81 7 2 Integrated BMC Force Update Procedure 82 7 3 ME Force Update Jumper 82 7 4 BIOS Recovery JUDO aset ten Etico ti Oops t ament sta 83 8 Intel Light Guided Diagnostics retenta aaa 84 8 1 System Status LED yes uisi ho het tite erotica atenderte 84 8 2 Post Code Diagnostic LEDS ds 85 9 Design and Environmental Specifications esee 86 9 1 Intel Server Board S3420GP Design Specifications a a 86 9 2 Board level Calculated MTBF sss enne 86 9 3 Server Board Power Requirements 87 9 3 1 Processor Power Support 88 9 4 Power Supply Output Requirements essen 88 9 4 1 A A EE 89 mw Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS 9 4 2 NAS ui et etg Au i dd 9 4 3 le 9 4 4 Voltage Requisito 9 4 5 Dynamic Lodi dile 9 4 6 Capacitive Loading avanse as 9 4 7 E E E le Stability EE 9 4 8 Common Mode e 9 4 9 Ripple NOIS z a nn e 94 10 Timing Requirements e aan istae etate 9 4 11 Residual Voltage Immunity in Standby Mode AA 9 44 12 Protection Circula 10 Regulatory and Certification Information l nennen 10 1 Prod
15. Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto CLTT OLTT Altitude 300m or less 301m 900m 901m 1500m Higher than 1500m Set Fan Profile Performance Acoustic Figure 23 Setup Utility System Acoustic and Performance Configuration Screen Display Table 19 Setup Utility System Acoustic and Performance Configuration Screen Fields Setupltem Options Help Text Set Throttling Auto Auto Throttling mode Note The OLTT Mode CLTT Closed Loop Thermal Throttling Mode option is shown for OLTT Open Loop Thermal Throttling Mode inrormanonal purposes only If the user selects OLTT the BIOS overrides that selection if the system can support CLTT OLTT is configured only when UDIMMs without Thermal Sensors are installed Altitude 300m or less 300m or less 980ft or less Note This option is 301m 900m Optimal performance setting near sea level not available on 901m 1500m 301m 900m 980ft 2950ft some models Higher than 1500m Optimal performance setting at moderate elevation 901m 1500m 2950ft 4920ft Optimal performance setting at high elevation Higher than 1500m 4920ft or greater Optimal performance setting at the highest elevations 52 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Setupltem Options Help Text Set Fan Profile Performance Performance Fan control prov
16. Devices Non Disabled Enabled This removes all USB Mass Storage devices disabled Bootable as Boot options Disabled This allows all USB Mass Storage devices as Boot options Revision 1 0 49 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS Setupitem Options Help Text Device Reset USB Mass Storage device Start Unit command timeout Grayed out if the USB Controller is timeout Setting to a larger value provides more time for a mass disabled storage device to be ready if needed One line for each Auto Auto USB devices less than 530 MB are emulated as Hidden if no USB Mass storage mass storage Floppy floppies devices are installed device in system Forced Epp Forced FDD HDD formatted drive are emulated as a Grayed out if the USB Controller is H FDD e g ZIP drive disabled ard Disk CD ROM This setup screen can show a maximum of eight devices on this screen If more than eight devices are installed in the system the USB Devices Enabled shows the correct count but only displays the first eight devices here USB 2 0 Enabled Onboard USB ports are enabled to support USB 2 0 mode Grayed out if the USB Controller is controller Disabled Contact your OS vendor regarding OS support of this disabled feature 5 3 2 2 6 PCI Screen The PCI Screen allows the user to configure the PCI add in cards onboard NIC controllers and video options To access th
17. The BIOS supports memory modules of mixed speed by automatic selection of the lowest common frequency of all memory modules DDR3 DIMM Each DDR3 DIMM advertises its lowest supported clock speed through the TCKMIN parameter in its Serial presence Data SPD The BIOS uses this information to arrive at the common lowest frequency that satisfies all installed DDR3 DIMMs This section describes the expected outcome on the installation of DDR3 DIMMs of different frequencies in the system for a given user selected frequency The following rules apply fall three single rank dual rank RDIMM slots are populated on a channel the BIOS forces a global common frequency of 800 MHz f two quad rank RDIMM are populated on one channel the BIOS forces a global common frequency of 800 MHz f one quad rank RDIMM are populated on one channel the BIOS forces a global common frequency of 1066 MHz If a maximum of only two DIMM slots are populated in the system among all channels and one or more DIMMs support DDR3 frequency greater than 1333 MHz the BIOS forces a global common frequency of 1333 MHz 3 2 5 Memory Map and Population Rules The following nomenclature is followed for DIMM sockets Note Intel Server Board S3420GP may support up to three DIMM sockets per channel Table 3 Standard Platform DIMM Nomenclature Channel A Channel B Al A2 A3 Bl B2 B3 18 Revision 1 0 Intel order number E65697 003 In
18. The sever board provides up to six SATA connectors The pin configuration for each connector is identical and defined in the following table Table 43 SATA Connector Pin out J1H4 J1H1 J1G1 J1H3 J1G3 J1F4 Pin SignalName Description 6 SATASAS RXP C Positive side of receive diferential pair 6 5 4 SAS Connectors The Intel Server Board S3420GPLX provides one SAS connector The pin configuration is identical and defined in the following table Table 44 SAS Connector Pin out J2H1 Pin Signal Name Description 1 je SATA SAS RX N C Negative side of receive differential pair e SATA SAS RX PC Positive side of receive differential pair 6 5 5 Serial Port Connectors The server board provides one external DB9 Serial A port J8A1 and one internal 9 pin serial B header J1B2 The following tables define the pin outs 72 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Connector Header Locations and Pin outs Table 45 External Serial A Port Pin out J8A1 Pin SignalName Description 3 SPA SOUT N TXD Transmit data G SPA DSR DSR data setready S SPACTS CTS dearosenj S SPB_CTS CTS clearto send 8 SPB RI RI Ring indicate 9 SPB ENN Enable N 6 5 6 USB Connector There are four external USB ports on two NIC USB combination Section 5 5 2 details the pin out of the connector Two 2x5 connector o
19. configuration space This is based on the selection of Maximize Memory below 4 GB in the BIOS Setup If this is set to Enabled the BIOS maximizes usage of memory below 4 GB for an operating system without PAE capability by limiting PCI Express Extended Configuration Space to 64 buses rather than the standard 256 buses This is done using the MAX BUS NUMBER feature Revision 1 0 17 Intel order number E65697 003 Functional Architecture IntelP amp P Server Board S3420GP TPS offered by the Intel S3420 I O Hub and a variably sized Memory Mapped UO region for the PCI Express functions 3 2 3 2 High Memory Reclaim When 4 GB or more of physical memory is installed physical memory is the memory installed as DDR3 DIMMs the reserved memory is lost However the Intel 3420 chipset provides a feature called high memory reclaim which allows the BIOS and operating system to remap the lost physical memory into system memory above 4 GB the system memory is the memory the processor can see The BIOS always enables high memory reclaim if it discovers installed physical memory equal to or greater than 4 GB For the operating system the reclaimed memory is recoverable only if the PAE feature in the processor is supported and enabled Most operating systems support this feature For details see the relevant operating system manuals 3 2 3 3 ECC Support Only ECC memory is supported on this platform 3 2 4 Support for Mixed speed Memory Modules
20. 84F3 84F4 84FF 8500 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 852A 852B 852C 852D 852bE 852F 8540 8541 8542 8543 8544 8545 8546 8547 8548 114 Processor 01 Failed FRB 3 Timer DIMM A3 failed Self Test BIST DIMM A4 failed Self Test BIST DIMM B1 failed Self Test BIST DIMM B2 failed Self Test BIST DIMM B3 failed Self Test BIST DIMM B4 failed Self Test BIST DIMM C1 failed Self Test BIS DIMM C2 failed Self Test BIST DIMM C3 failed Self Test BIST DIMM C4 failed Self Test BIST DIMM D1 failed Self Test BIST DIMM D2 failed Self Test BIST DIMM D3 failed Self Test BIST p Intel order number E65697 003 rd S3420GP TPS Response Pause Pause Pause Pause Pause No Pause No Pause Pause Pause Pause Pause No Pause No Pause Pause Pause Pause Pause Pause Pause No Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Revision 1 0 IntelPEP Server Board S3420GP TPS Error Code 8549 854A 854B 854C 854D 854E 854F 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 856A 856B 856C 856D 856E 856F 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 858A 858B 858C 858D 858E 858F 85A0 85A1 85A2 85A3 85A4 85A5 85A6 Rev DIMM D3 Disabled Je
21. F9 EFI Optimized Boot Enabled If enabled the BIOS only loads Disabled modules required for booting EFI aware Operating Systems Boot Option Retry Enabled If enabled this continually retries non Disabled EFI based boot options without waiting for user input If all types of bootable devices are installed in the system the default boot order is CD DVD ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV Boot Entry Vector Device 6 EFI Shell and EFI Boot paths pope m fcc 5 3 2 6 1 Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order To access this screen from the Main screen select Boot Options Delete Boot Options Boot Options Delete Boot Option Delete Boot Option Select one to Delete Internal EFI Shell Figure 29 Setup Utility Delete Boot Option Screen Display Table 25 Setup Utility Delete Boot Option Fields Options Help Text 60 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Setupitem Options Help Text Delete Boot Option Select one to Delete Remove an EFI boot option from the Internal EFI Shell boot order 5 3 2 6 2 Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks To access this screen from the Main screen choose Boot Options gt Hard Disk Order Boot Options Hard Disk 1 lt Availabl
22. Information Fields 58 Table 24 Setup Utility Boot Options Screen Fields cceseeeeseeeeeeeeeeeeeeeeeeeeseeneeeeeeeeseeees 59 Table 25 Setup Utility Delete Boot Option Fields 60 Table 26 Setup Utility Hard Disk Order Fields 61 Table 27 Setup Utility CDROM Order Fields sse 61 Table 28 Setup Utility Floppy Order Fields ennenen ennnen renerne nnne ennnen nnen annn nn ennnen 62 Table 29 Setup Utility Network Device Order Fielde esses 63 Table 30 Setup Utility Boot Manager Screen Fields ek ENEE 63 Table 31 Board Connector Matrix ccccccceeeeeeeeeeeeeeeeeeeeeeeeeee eee geeeeeeeeseeeeeeeseeeeeeeseeeeeeeeeeees 65 Table 32 Baseboard Power Connector Pin out LUOAT 66 x Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS List of Tables Table 33 SSI Processor Power Connector Pin out GC 66 Table 34 Intel RMM3 Connector Pin out J2C1 ccccescscscscssesescscsesavecsesesesececscsesaacseseeeeseaesees 66 Table 35 LPC IPMB Header Pin out J1H2 ENEE 67 Table 36 HSBP Header Prut J1J1 rera a ead betur estt mo vider Gian emet rs 67 Table 37 SGPIO Header Pin out J1J9 a i tune 67 Table 38 Front Panel SSI Standard 24 pin Connector Pin out J1C1 68 Tab
23. Main screen select Server Management 54 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Main euis Security Server Management Boot Options Boot Manager Assert NMI on SERR Enabled Disabled Assert NMI on PERR Enabled Disabled Resume on AC Power Loss Stay Off Last state Reset Clear System Event Log Enabled Disabled FRB 2 Enable Enabled Disabled O S Boot Watchdog Timer Enabled Disabled O S Boot Watchdog Timer Policy Power off Reset O S Boot Watchdog Timer Timeout 5 minutes 10 minutes 15 minutes 20 minutes ACPI 1 0 Support Enabled Disabled Plug amp Play BMC Detection Enabled Disabled gt Console Redirection System Information Figure 25 Setup Utility Server Management Configuraiton Screen Display Table 21 Setup Utility Server Management Configuration Screen Fields Setup Item Options Help Text Comments Assert NMI on SERR Enabled On SERR generate an NMI and log an error Disabled Note Enabled must be selected for the Assert NMI on PERR setup option to be visible Assert NMI on PERR Enabled On PERR generate an NMI and log an error Disabled Note This option is only active if the Assert NMI on SERR option is Enabled selected Resume on AC Power Stay Off System action to take on AC power loss recovery Loss Last state Stay Off System stays off Reset Last State System returns to the same state before the AC power los
24. No Pause No Pause No Pause No Pause No Pause No Pause No Pause Pause Pause No Pause No Pause No Pause No Pause Pause No Pause No Pause No Pause No Pause No Pause No Pause Halt Halt Halt No Pause Halt Pause No Pause No Pause Halt Revision 1 0 IntelPEP Server Board S3420GP TPS Appendix D POST Code Errors OxA5A1 PCI Express component encountered a SERR error OxA5A4 PCI Express IBIST error OxA6A0 DXE boot services driver Not enough memory available to shadow a legacy option ROM POST Error Beep Codes The following table lists POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users on error conditions The beep code is followed by a user visible code on POST Progress LEDs Table 70 POST Error Beep Codes POST Progress Code 3 Memory error Multiple System halted because a fatal error related to the memory was detected Revision 1 0 117 Intel order number E65697 003 Appendix E Supported IntelP amp P Server Chassis IntelPEP Server Board S3420GP TPS Appendix E Supported Intel Server Chassis The Intel Server Board S3420GP is supported in the following Intel server chassis Intel Server Chassis SR1630 Intel Server Chassis SC5650UP 118 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Glossary Glossary This appendix contains important terms used in this document For ease of use numeric entri
25. a 10 500 UN A d N 2 246 6 251 0 000 0 001 E 2 061 0 64 1 55 e MIT VE z HH D as 81 E m E d h U i i i i x d 8 500 215 46 S Ki s Z S S S Figure 5 Intel Server Board S3420GP Major Connector Pin Location 1 of 2 8 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Overview 120 755 WO ai l 284 691 Ki 0 000 19 000 4 200 0 500 5 08 1 82 0 845 21 46 1 300 33 020 2 15 54 410 na ta utu 65 710 3 100 93 080 3 910 33 31 4 600 116 840 5 505 139 43 5 150 146 254 5 143 rp i 38 24 pigie p 7 5 80 en NA o EE D 8 147 320 ppp sn s 87 Cist 103 147 961 1310 185 4741 1 100 195 5401 1 134 AS 195 3301 e s E E E a TITI a mitt 5 250 205 5501 5 303 210 546 Hi Li 3 000 228 60 8 410 213 414 1205 4901 gt Wire wv 3 decades Js pssst r BI 2 Figure 6 Intel Server Board S3420GP Major Connector Pin Location 2 of 2 Revision 1 0 9 Intel order number E65697 003 Overview IntelP amp P Server Board S3420GP TPS 9 060 1 241 MAX COMFONENT HEIGHT 5 PLACES FOR Faw HEADER OWPOMENT HEIGHT RESTRIC ION 0 043 Mar x SG 1 I8 3 0201 CPU V HEATSINK WOZATING HOLE COMPONENT HEIGHT AESTRICION 200 MAY SBS SV MAN nm
26. boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits 9 2 Board level Calculated MTBF This section provides results of MTBF Mean Time Between Failures testing done by a third party testing facility MTBF is a standard measure for the reliability and performance of the board under extreme working conditions The MTBF was measured at 20000 hours at 35 degrees Celsius The following table shows the MTBF for the server boards as configured from the factory Product Code Calculated MTBF Operating Temperature Intel Server Board S3420GPLX 335000 hours 35 degrees C Intel Server Board S3420GPLC 335000 hours 35 degrees C 86 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Design and
27. delay Delay from AC being applied to all output voltages N A 2500 Msec being within regulation Tvout_holdup Duration for which all output voltages stay within Msec regulation after loss of AC Measured at 80 of 21 N A maximum load Towok_holdup Delay from loss of AC to de assertion of PWOK 20 N A Msec Measured at 80 of maximum load Tpson on delay Delay from PSON active to output voltages within Msec EE 5 400 regulation limits Tpson_pwok Delay from PSON deactive to PWOK being de N A 50 Msec asserted Tpwok_on Delay from output voltages within regulation limits 100 500 Msec to PWOK asserted at turn on T pwok off Delay from PWOK de asserted to output voltages Msec 3 3 V 5 V 12 V 12 V dropping out of regulation 1 N A limits T pwok low Duration of PWOK being in the de asserted state Msec during an off on cycle using AC or the PSON 100 N A signal Tsb_vout Delay from 5 VSB being in regulation to O Ps 50 1000 Msec being in regulation at AC turn on T5VSB holdup Duration for which the 5 VSB output voltage stays 70 N A Msec within regulation after loss of AC AC Input H Tyout_holdup i I I I T V out I I I Tac on delay ide I 4 e i i I i I t 1 Tsb on delay lt S lt Tpwok on i Took off i gt Tsb on delay Tpwok on gt i Tpwok off PWOK og i Tpwok holdup d gt Tpson pwok I d 1 i i I l
28. generic or a sensor specific response Assertion De assertion Enables Assertion and de assertion indicators reveal the type of events the sensor generates As Assertions De De assertion Readable Value Offsets Readable Value indicates the type of value returned for threshold and other non discrete type sensors Readable Offsets indicate the offsets for discrete sensors that are readable with the Get Sensor Reading command Unless otherwise indicated all event triggers are readable Readable Offsets consist of the reading type offsets that do not generate events Event Data Event data is the data that is included in an event message generated by the sensor For threshold based sensors the following abbreviations are used R Reading value T Threshold value Revision 1 0 103 Intel order number E65697 003 Appendix B Integrated BMC Sensor Tables IntelPEP Server Board S3420GP TPS 104 Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states Rearming the sensors can be done manually or automatically This column indicates the type supported by the sensor The following abbreviations are used to describe a sensor A Auto rearm M Manual rearm Default Hysteresis The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysteresis for the sensor which can be 1 or 2 positiv
29. includes the sum of all DDR3 DIMMs that failed Memory BIST during POST or were disabled by the BIOS during memory discovery phase to optimize memory configuration Current Configuration Information only Displays one of the following Independent Mode System memory is configured for optimal performance and efficiency and no RAS is enabled Sparing Mode System memory is configured for RAS with optimal effective memory Revision 1 0 45 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS Comments Current Memory Information only Displays the speed the memory is running at Speed DIMM XY Displays the state of each DIMM socket present on the board Each DIMM socket field reflects one of the following possible states Installed There is a DDR3 DIMM installed in this slot Not Installed There is no DDR3 DIMM installed in this slot Disabled The DDR3 DIMM installed in this slot was disabled by the BIOS to optimize memory configuration Failed The DDR3 DIMM installed in this slot is faulty malfunctioning Spare Unit The DDR3 DIMM is functioning as a spare unit for memory RAS purposes Note X denotes the Channel Identifier and Y denote the DIMM Identifier within the Channel 5 3 2 2 3 Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA SAS controller when it is present on the baseboard midplane or backplane of an Intel system To access this
30. key scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboards but will have the same effect F9 Setup Defaults Pressing F9 causes the following to display Load Optimized Defaults Yes No If Yes is highlighted and Enter is pressed all Setup fields are set to their default values If No is highlighted and Enter is pressed or if the lt Esc gt key is pressed the user is returned to where they were before F9 was pressed without affecting any existing field values lt F10 gt Save and Exit Pressing lt F10 gt causes the following message to display Save configuration and reset Yes No If Yes is highlighted and Enter is pressed all changes are saved and the Setup is exited If No is highlighted and Enter is pressed or the lt Esc gt key is pressed the user is returned to where they were before F10 was pressed without affecting any existing values Revision 1 0 37 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS 5 3 1 4 Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen It displays the major menu selections available to the user By using the left and right arrow keys the user can select the menus listed here Some menus are hidden and
31. levels The power supply is provided with a reliable protective earth ground All secondary circuits are connected to protective earth ground Resistance of the ground returns to chassis does not exceed 1 0 mQ This path may be used to carry DC current 9 4 2 Standby Outputs The 5 VSB output is present when an AC input greater than the power supply turn on voltage is applied 9 4 3 Remote Sense The power supply has remote sense return ReturnS to regulate out ground drops for all output voltages 3 3 V 5 V 12 V 12 V and 5 VSB The power supply uses remote sense to regulate out drops in the system for the 3 3 V 5 V and 12 V outputs The power supply must operate within specification over the full range of voltage drops from the power supply s output connector to the remote sense points 9 4 4 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise All outputs are measured with reference to the return remote sense signal ReturnS Table 58 Voltage Regulation Limits Parameter Tolerance Minimum Normal ET 56 15 5 5 11 40 12 00 12 60 10 10 13 20 12 00 10 80 5VsB YES 9 4 5 Dynamic Loading The output voltages remain within limits for the step loading and capacitive loading specified in the following table The load transient repetition ra
32. operation Revision 1 0 21 Intel order number E65697 003 Functional Architecture IntelP amp P Server Board S3420GP TPS When operating with two PCI Express controllers each controller can operate at either 2 5 GT s or 5 0 GT s The PCI Express architecture is specified in three layers Transaction Layer Data Link Layer and Physical Layer The partitioning in the component is not necessarily along these same boundaries 3 4 2 Serial ATA Support The Intel 3420 Chipset has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 3 0 GB s 300 MB s The SATA controller contains two modes of operation a legacy mode using I O space and an AHCI mode using memory space Software that uses legacy mode does not have AHCI capabilities The Intel 3420 Chipset supports the Serial ATA Specification Revision 1 0a The Ibex Peak also supports several optional sections of the Serial ATA II Extensions to Serial ATA 1 0 Specification Revision 1 0 AHCI support is required for some elements 3 4 2 1 Intel Matrix Storage Technology The Intel 3420 Chipset provides support for Intel Matrix Storage Technology providing both AHCI see above for details on AHCI and integrated RAID functionality The industry leading RAID capability provides high performance RAID 0 1 5 and 10 functionality on up to six SATA ports of PCH Matrix RAID support is provided to allow mul
33. registers Embedded Controller via SMBus 34 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface 5 BIOS User Interface 5 1 Logo Diagnostic Screen The logo Diagnostic Screen displays in one of two forms e If Quiet Boot is enabled in the BIOS setup a logo splash screen displays By default Quiet Boot is enabled in the BIOS setup If the logo displays during POST press Esc to hide the logo and display the diagnostic screen e Ifa logo is not present in the flash ROM or if Quiet Boot is disabled in the system configuration the summary and diagnostic screen displays The diagnostic screen displays the following information e BIOS ID e Platform name e Total memory detected Total size of all installed DDR3 DIMMs e Processor information Intel branded string speed and number of physical processor identified e Keyboards detected if plugged in e Mouse devices detected if plugged in 5 2 BIOS Boot Popup Menu The BIOS Boot Specification BBS provides for a Boot Popup Menu invoked by pressing the F6 key during POST The BBS popup menu displays all available boot devices The list order in the popup menu is not the same as the boot order in the BIOS setup it simply lists the bootable devices from which the system can be booted When a User Password or Administrator Password is active in Setup the password is to access the Boot Popup Menu 5 3 BIOS Setup util
34. screen from the Main menu select Advanced Mass Storage Advanced Mass Storage Controller Configuration Intel Entry SAS RAID Module Enabled Disabled Configure Intel Entry SAS RAID Module LSI Integrated RAID Intel ESRTII Onboard SATA Controller Enabled Disabled ENHANCED COMPATIBILITY AHCI SW Configure SATA Mode RAID gt SATA Port 0 Not Installed Drive Info gt SATA Port 1 Not Installed Drive Info gt SATA Port 2 Not Installed Drive Info gt SATA Port 3 Not Installed Drive Info gt SATA Port 4 Not Installed Drive Info gt SATA Port 5 Not Installed Drive Info Figure 19 Setup Utility Mass Storage Controller Configuration Screen Display Table 15 Setup Utility Mass Storage Controller Configuration Screen Fields Setupltem Options Help Text BI Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Setupltem Options Help Text Enabled Disabled Intel Entry SAS RAID Module Configure Intel Entry SAS RAID Module RAID Intel ESRTII Enabled or Disable the Intel SAS Entry RAID Module LSI Integrated LSI Integrated RAID Supports RAID 0 RAID 1 and RAID fe as well as IT JBOD mode Intel ESRTII Intel Embedded Server RAID Technology II which SE RAID 0 RAID 1 RAID Unavailable if the SAS Module AXX4SASMOD is not present Note This option is not available on s
35. that support Detection Disabled plug and play loading of an IPMI driver Do not enable if your OS does not support this driver ACPI 1 0 Support Enabled Enabled Publish ACPI 1 0 version of FADT in Root Needs to be Enabled for Disabled System Description Table Microsoft Windows 2000 This may be required for compatibility with OS support versions that only support ACPI 1 0 Console Redirection View Configure console redirection information and Takes the user to the settings Console Redirection Screen System Information View system information Takes the user to the System Information Screen 5 3 2 4 1 Console Redirection Screen The Console Redirection screen allows the user to enable or disable console redirection and to configure the connection options for this feature To access this screen from the Main screen select Server Management Console Redirection Server Management Console Redirection Console Redirection Disabled Serial Port A Serial Port B Flow Control None RTS CTS Baud Rate 9 6k 19 2k 38 4k 57 6k 115 2k Terminal Type PC ANSI VT100 VT100 VT UTF8 Legacy OS Redirection Disabled Enabled Figure 26 Setup Utility Console Redirection Screen Display 56 Revision 1 0 Intel order number E65697 003 Setup Item Console Redirection Flow Control Baud Rate IntelPEP Server Board S3420GP TPS BIOS User Interface Table 22 Setup Utility Console Redirection Configuration Fi
36. to IBMC JTAG interface LAN interface ACPI interface 3 4 1 0 Sub system Intel 3420 Chipset PCH provides extensive I O support 3 4 1 PCI Express Interface Two different PCI E configurations on single board are dependent on different board SKUs e Intel Server Board S3420GPLX One PCI E X16 slot connected to the PCI E ports of CPU Two PCI E x8 slots and one SAS module connected to PCI E ports of PCle switch One PCI E X8 slot and one PCI E x4 slot connected to the PCI E ports of PCH e Intel Server Board S3420GPLC One PCI E X16 slot and one PCI E X8 slot connected to the PCI E ports of CPU One PCI E x8 slot connected to the PCI E ports of PCH e Intel Server Board S3420GPV lt TBD gt There is one 32 bit 33 MHz 5 V PCI slot Compatibility with the PCI addressing model is maintained to ensure all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The initial recovered clock speed of 1 25 GHz results in 2 5 Gb s direction which provides a 250 MB s communications channel in each direction 500 MB s total This is close to twice the data rate of classic PCI The fact that 8b 10b encoding is used accounts for the 250 MB s where quick calculations would imply 300 MB s The external graphics ports support 5 0 GT s speed as well Operating at 5 0 GT s results in twice as much bandwidth per lane as compared to 2 5 GT s
37. 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Regulatory and Certification Information 10 2Product Regulatory Compliance Markings The server board is provided with the following regulatory marks Regulatory Compliance Region Marking UL Mark USA Canada AY C US E139761 EMC Marking Class A CANADA ICES 003 CLASS A BSMI Marking Class A Taiwan gt D33025 EUER GE PRISA ER c EHR EA gt TESEI gt CREEN gt ERAS KE E LEE PRE C tick Marking Australia New Zealand RRL MIC Mark Korea CPU S3420GP A Country of Origin Exporting Requirements MADE IN xxxxx Provided by label not silk Screen Model Designation Regulatory Identification s3420GP PB Free Marking Environmental Refer to Jedec Standard J STD609 o China Recycling Package China Marking Zi Marked on packaging label L Revision 1 0 97 Intel order number E65697 003 Regulatory and Certification Information IntelP amp P Server Board S3420GP TPS Other Recycling Package Other Recycling Marking Package Marks Marked on packaging label LAY S Corrugated Recycles Other Recycling Package CA Lithium Perchlorate Perchlorate Material Special handling may Marking insert apply See Marked on packaging www dtsc ca gov hazardouswaste perchlorate This notice is required by California Code of label Regulations Title 22 Division 4 5 Chapter 33 Best Management Practices for Perc
38. 03 IntelP P Server Board S3420GP TPS Jumper Blocks firmware update process fails due to ME not being in the proper update state the server board provides an Integrated BMC Force Update jumper J1F 1 which forces the ME into the proper update state The following procedure should be completed in the event the standard ME firmware update process fails Power down and remove the AC power cord 2 Open the server chassis For instructions see your server chassis documentation Move jumper from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 4 Close the server chassis Reconnect the AC cord and power up the server Perform the ME firmware update procedure as documented in the README TXT file that is included in the given ME firmware update package same package as BIOS Power down and remove the AC power cord Open the server chassis Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server 7 4 BIOS Recovery Jumper The following procedure boots the recovery BIOS and flashes the normal BIOS Turn off the system power Move the BIOS recovery jumper to the recovery state Insert a bootable BIOS recovery media containing the new BIOS image files Turn on the system power o SS The BIOS POST screen will appear displaying the progress
39. 1 No connection 6 5 2 Rear NIC and USB connector The server board provides two stacked RJ 45 2xUSB connectors side by side on the back edge of the board J6A1 J5A1 The pin out for NIC connectors are identical and defined in the following table Table 41 RJ 45 10 100 1000 NIC Connector Pin out J5A1 Pin Signal Name Pin Signal Name 1 P5V USB PWR75 2 USB PCH 11 FB DN 3 USB PCH 11 FB DP 4 GND 5 P5V USB PWR75 6 USB PCH 10 FB DN 7 USB PCH 10 FB DP 8 GND 9 P1V9 LAN2 R 10 NIC2 MDIP lt 0 gt 11 NIC2 MDIN lt 0 gt 12 NIC2 MDIP lt 1 gt 13 NIC2 MDIN lt 1 gt 14 NIC2 MDIP lt 2 gt 15 NIC2 MDIN lt 2 gt 16 NIC2 MDIP lt 3 gt 17 NIC2 MDIN lt 3 gt 18 GND 19 LED NIC2 1 20 P3V3 AUX 21 LED NIC2 LINK100 R 0 22 LED NIC2 LINK1000 2 Table 42 RJ 45 10 100 1000 NIC Connector Pin out J6A1 Revision 1 0 71 Intel order number E65697 003 Connector Header Locations and Pin outs IntelPEP Server Board S3420GP TPS Pin Signal Name Pin Signal Name 1 P5V USB PWR75 2 USB PCH 11 FB DN 3 USB PCH 11 FB DP 4 GND 5 P5V USB PWR75 6 USB PCH 10 FB DN 7 USB PCH 10 FB DP 8 GND 9 P1V8 PHY VCT R 10 NIC1 MDIP lt 0 gt 11 NIC1 MDIN lt 0 gt 12 NIC1 MDIP lt 1 gt 13 NIC1 MDIN lt 1 gt 14 NIC2 MDIP 2 15 NIC1 MDIN 2 16 NIC2 MDIP lt 3 gt 17 NIC1 MDIN lt 3 gt 18 GND 19 LED NIC1 LINK ACT O R 20 P3V3 AUX 21 LED NIC1 2 22 LED NIC1 LINK1000 1 6 5 3 SATA
40. 2 A six DIMM configuration DIMM socketsA1 A2 A3 B1 B2 and B3 performs better than a three DIMM configuration DIMM sockets A1 A2 and A3 e The Intel Remote Management Module 3 Intel RMM3 connector is not compatible with the Intel Remote Management Module Product Order Code AXXRMM or Intel Remote Management Module 2 Product Order Code AXXRMM2 Clear the CMOS with the AC power cord plugged in Removing the AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after the CMOS clear procedure is followed and AC power is re applied If this happens remove the AC power cord wait 30 seconds and then re connect the AC power cord Power up the system and proceed to the F2 BIOS Setup utility to reset the needed settings Normal Integrated BMC functionality is disabled with the force Integrated BMC update jumper set to the enabled position pins 2 3 The server should never be run with the Integrated BMC force update jumper set in this position and should only be used when the standard firmware update process fails This jumper should remain in the default disabled position pins 1 2 when the server is running normally When performing a normal BIOS update procedure the BIOS recovery jumper must be set to its default position pins 1 2 102 Revision 1 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Appendix B Integ
41. 20GP TPS List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 viii Intel Server Board S3420GPLX Picture sess 3 Intel Server Board S3420GP Layout I entrent nene 4 Intel Server Board S3420GP Key Connector and LED Indicator IDENTIFICATION 6 Intel Server Board S3420GP Hole and Component Positions 7 Intel Server Board S3420GP Major Connector Pin Location 1 of 2 8 Intel Server Board S3420GP Major Connector Pin Location 2 of 2 9 Intel Server Board S3420GP Primary Side Keepout Zone sss 10 Intel Server Board S3420GP Secondary Side Keepout Zone 11 Intel Server Board S3420GP Rear UO Layout 12 Intel Server Board S3420GP Functional Block Diagram For S3420GPLX 13 Intel Server Board S3420GP Functional Block Diagram From S3420GPLC 14 Intel Server Board S3420GP Functional Block Diagram From S3420GPV 14 Integrated BMC Hardware te de Ee ERE Ur deb HI LR Io ELE a 25 Server Management Bus SMBUS Block Diag
42. 3 LED 2 LED 1 LED 0 8h 4h 2h th 8h 4h 2h th Status 2N OFF ON OFF ON OFF ON OFF 1 0 1 0 1 1 0 0 Results Ah Ch Upper nibble bits 1010b Ah Lower nibble bits 1100b Ch the two are concatenated as ACh Table 68 Diagnostic LED POST Code Decoder Checkpoint Diagnostic LED Decoder Description O On X Off Upper Nibble Lower Nibble Revision 1 0 109 Intel order number E65697 003 Appendix C POST Code Diagnostic LED Decoder IntelP amp P Server Board S3420GP TPS MSB LSB 8h 4h 2h 1h 8h 4h 2h h LED 7 6 5 H4 A3 2 1 0 Host Processor 0x04h X X X X X O X X Early processor initialization flat32 asm where system BSP is selected Ox10h X X X O X X X X Power on initialization of the host processor Boot Strap Processor Ox11h X X X O NX X X O Host processor cache initialization including AP Ox12h X X X O X X O X Starting application processor initialization 0x13h X X X O X X O O SMM initialization Chipset 0x21h X X O X X X X O initializing a chipset component Memory 0x22h X X O X X X O X Reading configuration data from memory SPD on FBDIMM 0x23h X X O X X X O 0 Detecting presence of memory 0x24h X X O X X O X X Programming timing parameters in the memory controller 0x25h X X O X X O X O Configuring memory parameters in the memory controller 0x26h X X O X X O O X Optimizing memory controller settings 0x27h X X O X X O O O Ilni
43. 3420GP TPS Functional Architecture The BIOS supports USB 2 0 mode of operation and as such supports USB 1 1 and USB 2 0 compliant devices and host controllers During the pre boot phase the BIOS automatically supports the hot addition and hot removal of USB devices and a short beep is emitted to indicate such an action For example if a USB device is hot plugged the BIOS detects the device insertion initializes the device and makes it available to the user During POST when the USB controller is initialized it emits a short beep for each USB device plugged into the system as they were all just hot added Only on board USB controllers are initialized by BIOS This does not prevent the operating system from supporting any available USB controllers including add in cards 3 4 3 2 Legacy USB Support The BIOS supports PS 2 emulation of USB keyboards and mouse During POST the BIOS initializes and configures the root hub ports and searches for a keyboard and or a mouse on the USB hub and then enables the devices that are recognized 3 5 Optional Intel SAS Entry RAID Module AXXASASMOD The Intel Server Board S3420GPLX provides a SAS Mezzanine slot J2H1 for the installation of an optional Intel SAS Entry RAID Module AXX4SASMOD Once the optional Intel SAS Entry RAID Module AXX4SASMOD is detected the x4 PCI Express links from the PCI switches to the SAS Mezzanine slot The optional Intel SAS Entry RAID Module AXXASASMOD includes a SA
44. 4 Loading BIOS Deraulls sa eee NSS U eG e REN 63 6 Connector Header Locations and Pin OutS rrwrrxnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnennnnnnnr 65 6 1 Board Connector ee DEE 65 6 2 Power Connectors P KEES gie de 65 6 3 System Management Headers eese nnne nennen 66 Revision WMM Intel order number E65697 003 Table of Contents IntelP amp P Server Board S3420GP TPS 6 3 1 Intel Remote Management Module 3 Intel RMM3 Connector 66 6 3 2 LCP IPMB FIeaderu eaaet tpud Seeds 67 6 3 3 HSBP Header um RE RU aos 67 6 3 4 S PIO Heder MY 67 6 4 Front Control Panel Connector eene 68 6 4 1 Power EI Le Te WE EE 68 6 4 2 Reset BUON ves 69 6 4 3 NM BO St NE 69 6 4 4 System Status Indicator LED iii Lad 69 6 5 OCOMNECIONS un n es re a utere e a se e be ets 71 6 5 1 VGA Corinector uuu uu ua uu ERO FERRE iia 71 6 5 2 Rear NIC and USB connechor enne 71 6 5 3 SA A UC I I RITU MD M 72 6 5 4 SAS COMMECIONS ata Ga 72 6 5 5 Serial Port Confnactors eade bac riada 72 6 5 6 USB Connector ere te pte tote te A hg ese trt rg nan E a EVE 73 6 6 PCI Express Slot PCI Slot Riser Card Slot 75 6 7 Fan Fleaders Ee tt Tenore ee n edt E ce tup HI TERI ER ER REN UU wes 79 FEM AA 80 T 1 CMOS Clear and Password Reset Usage Procedure
45. AN USB Media Redirection Remote USB media access over LAN WS MAN Full SMASH profiles for WS MAN based consoles 3 6 3 Serial Ports The server board provides two serial ports an external DB9 serial port connector and an internal DH 10 serial header The rear DB9 serial A port is a fully functional serial port that can support any standard serial device The Serial B port is an optional port accessed through a 9 pin internal DH 10 header J1B1 You can use a standard DH 10 to DB9 cable to direct serial A port to the rear of a chassis The serial B interface follows the standard RS 232 pin out as defined in the following table Table 6 Serial B Header J1B1 Pin out H 5 Signal Name Serial Port B Header Pin out DCD DSR RX RTS TX CTS DTR RI GND mro OOO Dom d OOO ojl o N O Q O N gt 3 6 4 Floppy Disk Controller The server board does not support a floppy disk controller interface However the system BIOS recognizes USB floppy devices 3 6 5 Keyboard and Mouse Support The server board does not support PS 2 interface keyboards and mouse However the system BIOS recognizes USB specification compliant keyboard and mouse 26 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Functional Architecture 3 6 6 Wake up Control The super I O contains functionality that allows various events to power on and power off the sys
46. BIOS User Interface Advanced Processor Configuration Processor Socket Processor ID Processor Frequency Microcode Revision Current QPI Link Speed QPI Link Frequency Intel Turbo Boost Technology Enhanced Intel SpeedStep Tech Intel Hyper Threading Technology Core Multi Processing Execute Disable Bit Intel Virtualization Technology Intel VT for Directed UO Interrupt Remapping Coherency Support ATS Support Pass through DMA Support Hardware Prefetcher Adjacent Cache Line Prefetch Enabled Disabled Enabled Disabled Enabled Disabled All 1 2 Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled IntelPEP Server Board S3420GP TPS Figure 17 Setup Utility Processor Configuration Screen Display Table 13 Setup Utility Processor Configuration Screen Fields Help Text Information only Processor CPUID Processor Frequency Information only Current frequency of the processor Information only Frequency at which the processor are currently running Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Setup Item Options Help Text Microcode Revision Information only Revision of the loaded microcode L1 Cache RAM Information only Size of the Processor L1 Cache L2 Cache RAM Information only Size of the Processo
47. Card PCI Intel amp Server Board S3420GPLX Express Card Slot1 One 5V PCI 32 bit 33 MHz connector Slot2 One PCI Express Gen1 x4 x1 throughput connector Slot3 One PCI Express Gen1 x8 x4 throughput connector Slot4 One PCI Express Gen2 x8 x4 throughput connector Slot5 One PCI Express Gen2 x8 x8 throughput connector Slot6 One PCI Express Gen2 x16 x8 throughput connector Intel amp Server Board S3420GPLC S3420GPV Slot1 One 5V PCI 32 bit 33 MHz connector Slot3 One PCI Express Gen1 x8 x4 throughput connector Slot5 One PCI Express Gen2 x8 x8 throughput connector Slot6 One PCI Express Gen2 x16 x8 throughput connector Video Onboard ServerEngines LLC Pilot II BMC Controller ntegrated 2D Video Controller 64 MB DDR2 667 MHz Memory Onboard Hard Drive Support for six Serial ATA II hard drives through six onboard SATA II connectors with SW RAID 0 1 5 and 10 Intel amp Server Board S3420GPLX Upto four SAS hard drives through option Intel SAS Entry RAID Module AXX4SASMOD card One Gigabit Ethernet device 82574L connect to PCI E x1 interfaces on the PCH Intel amp Server Board S3420GPLX S3420GPLC One Gigabit Ethernet PHY 82578DM connected to PCH through PCI E x1 interface Server Management Onboard LLC Pilot II Controller iBMC Integrated Baseboard Management Controller Integrated BMC IPMI 2 0 compliant Integrated 2D video controller on PCI E x1 Int
48. Environmental Specifications 9 3 Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel Server Board 53420GP including voltage and current specifications and power supply on off sequencing characteristics The following diagram shows the power distribution implemented on this server board GROSSE POINT POWER DIAGRAM m ge Tei ES EE DS eee za ser 1 83A 17 6A 0 165A 0 26A 0 1A 0 2A 0 004A 0 3A 0 455A 0 284A P1V05 PCH E 5 51A Figure 36 Power Distribution Block Diagram Revision 1 0 87 Intel order number E65697 003 Design and Environmental Specifications IntelP amp P Server Board S3420GP TPS 9 3 1 Processor Power Support The server board supports the Thermal Design Power TDP guideline for Intel Xeon processor The Flexible Motherboard Guidelines FMB were also followed to help determine the suggested thermal and current design values for anticipating future processor needs The following table provides maximum values for Icc TDP power and TcaAse for the Intel Xeon 3400 Series processor Table 56 Intel Xeon Processor TDP Guidelines TDP Power Maximum Toast Jee Maximum 67 0 C
49. GP that uses the Intel Xeon 3400 Series processor has a system status indicator LED on the front panel This indicator LED has specific states and corresponding interpretation as shown in the following table Revision 1 0 69 Intel order number E65697 003 Connector Header Locations and Pin outs IntelPEP Server Board S3420GP TPS Table 39 System Status LED Indicator States Color State Criticality Green Solid on Ok System booted and ready Green 1 Hz blink Degraded System degraded Non critical temperature threshold asserted Non critical voltage threshold asserted Non critical fan threshold asserted Fan redundancy lost sufficient system cooling maintained This does not apply to non redundant systems Power supply predictive failure Power supply redundancy lost This does not apply to non redundant systems Correctable errors over a threshold of 10 and migrating to a spare DIMM memory sparing This indicates the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED should light up Amber 1 Hz blink Non critical Non fatal alarm system is likely to fail CATERR asserted Critical temperature threshold asserted Critical voltage threshold asserted Critical fan threshold asserted VRD hot asserted SMI Timeout asserted Amber Solid on Critical non Fatal alarm system has failed or shutdown recoverable Thermtrip asserted Non recoverable temperature threshold asserte
50. Hardware 3 6 1 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10 100 network interfaces Interface 1 This interface is available from either of the available NIC ports in system that can be shared with the host Only one NIC may be enabled for management traffic at any time To change the NIC enabled for management traffic please use the Write LAN Channel Port OEM IPMI command The default active interface is port 1 NIC Interface 2 This interface is available from the optional RMM3 which is a dedicated management NIC that is not shared with the host For these channels support can be enabled for IPMI over LAN and DHCP For security reasons embedded LAN channels have the following default settings IP Address Static All users disabled 3 6 2 Optional RMM3 Advanced Management Board On the Intel Server Board S3420GPLX provides RMM3 module RMM3 advanced management board serves two purposes Revision 1 0 25 Intel order number E65697 003 Functional Architecture IntelPEP Server Board S3420GP TPS e Give the customer the option to add a dedicated management 100 Mbit LAN interface to the product e Provide additional flash space enabling the Advanced Management functions to support WS MAN and CIMON Table 5 Optional RMM3 Advanced Management Board Features Feature Description KVM Redirection Remote console access via keyboard video and mouse redirection over L
51. L US FAM HEADER 5 PLACES UX POWER COMMECTOS SAS MODULE CONECTOR DORS DIMM CONNECTOR 6 PLACES INTERNAL USBIFOR IEPHYR CARDI Figure 3 Intel Server Board S3420GP Key Connector and LED Indicator IDENTIFICATION 6 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Overview v 155L3 961 SASERCARD WODUNTI SG HOLE 3 PLACES v 14813 76 CPU WR HEATSINK MOUNTING HOLE 2 PLACES 3 153 80 09 0 1557 4 03 CPU HEATS 186 MOUNTING HOLE 4 PLACES 4 785 zl zai 5 221 132 62 5 957 EL 154 94 151 32 p 143513 08 T r Y 1243 20 CPU SOCHET ILM MOUNTING HOLE 3 PLACES HOLE FOR AS0 0M CARD SETEATION 1 349 18 68 1 138 1 623 Us zi 1193 63 1 930 121 431 5 350 277 33 9 200 5 042 233 68 223 58 en w E 3 os 5 z n lt 3 Fs g Sz zz g s Figure 4 Intel Server Board S3420GP Hole and Component Positions Revision 1 0 7 Intel order number E65697 003 Overview IntelP amp P Server Board S3420GP TPS EI m eo lt m mnc n EI m o Ss e Ww m a m 9 fF m 2 m n nw o ov OF eran euo EE 9 7 x oe nano e mo ooo oc T Me owoe T mu Ts NEO Do om en x on w Lat KC mm ov gn onm Le at Tee Te Tee e Le e ms pr Ki IF ra TS OM ON ONON OM ecc lt lt no mo ao ma nu eae us Po e il t 1 1 1 V 19 230
52. LEVEL SHIFT DOR channel A DORA channel B VREFDQ VREFDQ Inlet Ar temp ISL90727 ISL90728 7 Ox5C 0x7C au DDR3 CH 1 DIMM 1A DDR3 CH2 SS DIMM 2A DIMM 1B Bm 0x42 DIMM 28 Qx AR XDP DIMM 1C 0x48 DIMM 2C e 0xAA LEVEL SHIFT REPEATER P3V35B P3V3DC LEVEL SHIFT P3V3SB PSVDC LEVEL SHIFT P3V3SB PSVSB NC PSU PECI GFX LEVEL SHIFT Video poc P3V3DC PSVDC Conn TAJ SM Bus 1 SM Bus 5 SM Bus 0 Figure 14 Server Management Bus SMBUS Block Diagram 4 1 Feature Support 4 1 1 30 IPMI 2 0 Features Integrated Baseboard Management Controller Integrated BMC IPMI Watchdog timer Messaging support including command bridging and user session support Chassis device functionality including power reset control and BIOS boot flags support Event receiver device The Integrated BMC receives and processes events from other platform subsystems Field replaceable unit FRU inventory device functionality The Integrated BMC supports access to system FRU devices using IPMI FRU commands Revision 1 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Platform Management System event log SEL device functionality The Integrated BMC supports and provides access to a SEL Sensor device record SDR repository device functionality The Integrated BMC supports storage and access of system SDRs Sensor device and sensor scanning monitoring The Integr
53. P lt 4 gt GND PETN3 P2E CPU C S6 TXN 4 GND GND GND P2E CPU S6 RXP 4 RSVD NC P2E CPU S6 RXN lt 4 gt PRSNT2 N NC GND GND NC End of x4 End of x4 B33 PETP4 P2E CPU C S6 TXP lt 3 gt A33 RSVD NC B34 PETN4 P2E CPU C S6 TXN 3 A34 GND GND B35 GND GND A35 PERP4 P2E CPU S6 RXN lt 3 gt B36 GND GND A36 PERN4 P2E CPU S6 RXP lt 3 gt B37 PETP5 P2E CPU C S6 TXP lt 2 gt A37 GND GND B38 PETN5 P2E CPU C S6 TXN lt 2 gt A38 GND GND Revision 1 0 Intel order number E65697 003 75 Connector Header Locations and Pin outs IntelPEP Server Board S3420GP TPS B39 GND GND A39 PERP5 P2E CPU S6 RXN lt 2 gt B40 GND GND A40 PERN5 P2E CPU S6 RXP lt 2 gt B41 PETP6 P2E CPU C S6 TXP lt 1 gt A41 GND GND B42 PETN6 P2E CPU C S6 TXN 1 A42 GND GND B43 GND GND A43 PERP6 P2E CPU S6 RXN lt 1 gt B44 GND GND A44 PERN6 P2E CPU S6 RXP 1 B45 PETP7 P2E CPU C S6 TXP 0 A45 GND GND B46 PETN7 P2E CPU C S6 TXN 0 A46 GND GND B47 GND GND A47 PERP7 P2E CPU_S6 RXN lt 0 gt B48 PRSNT2_N NC A48 PERN7 P2E CPU S6 RXP lt 0 gt B49 GND GND A49 GND GND End of x8 End of x8 B50 PETP8 NC A50 RSVD NC B51 PETN8 NC A51 GND GND B52 GND GND A52 PERP8 NC B53 GND GND A53 PERN8 NC B54 PETP9 NC A54 GND GND B55 PETN9 NC A55 GND GND B56 GND GND A56 PERP9 NC B57 GND GND A57 PERN9 NC B58 PETP10 NC A58 GND GND B59 PETN10 NC A59 GND GND B60 GND GND A60 PERP10 NC B61 GND GND A61 PE
54. PIO General Purpose UO Gunning Transceiver Logic HPA Host Physical Address HSC Hot swap Controller Hertz 1 cycle second Inter Integrated Circuit Bus Intel Architecture m D w Input Buffer Revision 1 0 119 Intel order number E65697 003 Glossary Term Definition I O Controller Hub CMB Intelligent Chassis Management Bus Internal Error I m D UO and Firmware Bridge Independent Loading Mechanism Clm lt IMC Integrated Memory Controller Interrupt I O Acceleration Technology IOH I O Hub MPO Internet Protocol Intelligent Plattorm Management Bus Intelligent Plattorm Management Interface IR o Infrared In Target Probe 1024 bytes Keyboard Controller Style Keyboard Video Mouse Local Area Network Liquid Crystal Display Local Directory Authentication Protocol LED Light Emitting Diode Low Pin Count Logical Unit Number MAC Media Access Control 1024 KB Memory Controller Hub MD2 Message Digest 2 Hashing Algorithm Message Digest 5 Hashing Algorithm Higher Security Management Engine MMU Memory Management Unit Milliseconds Memory Type Range Register Mux Multiplexor Network Interface Controller NMI Nonmaskable Interrupt OBF OEM Ohm Unit of electrical resistance Over voltage Protection PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging o c 15 c E c T e o I e 2 al m a o 3 D 2 2 Di o K
55. RN10 NC B62 PExP11 NC A62 GND GND B63 PETN11 NC A63 GND GND B64 GND GND A64 PERP11 NC B65 GND GND A65 PERN11 NC PETP12 GND PETN12 GND GND PERP12 GND PERN12 PETP13 GND PETN13 GND GND PERP13 GND PERN13 PETP14 GND PETN14 GND GND PERP14 GND PERN14 PETP15 GND PETN15 GND GND PERP15 PRSNT2 N PERN15 RSVD GND 76 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Three PCI Express x8 connectors J2B2 J3B1 and J4B2 Signal B1 ET ET JTAG2 TCK SMCLK JTAGS TDI B6 SMDAT JTAG4 TDO GND JTAGS TMS 3 3V A15 GND B15 HSON 0 RESERVED HSOP 1 25 B25 HSON 2 A HSIP 2 GND One PCI Express X4 connector J2B1 Revision 1 0 Pin A26 A27 A28 A29 A30 A31 HSIP 2 GND GND HSIP 3 HSIN 3 GND RESERVED RESERVED GND GND HSIP 5 Intel order number E65697 003 Connector Header Locations and Pin outs B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B48 B49 B17 B18 B19 B20 GND HSOP 3 HSON 3 GND PRSNT2 GND PRSNT2_N GND PETP1 PETN1 77 Connector Header Locations and Pin outs IntelPEP Server Board S3420GP TPS Pir Sem me De me e wp mer e De me Le me om me ee fer pas wer D REFCLK ms omme as x A34 FRAME es Se Les era ns Au S
56. S BIOS User Interface Advance d Security Server Management Boot Options Boot Manager Processor Configuration Memory Configuration Mass Storage Controller Configuration Serial Port Configuration USB Configuration PCI Configuration System Acoustic and Performance Configuration Figure 16 Setup Utility Advanced Screen Display Table 12 Setup Utility Advanced Screen Display Fields Setupiem Help Text Processor Configuration View Configure processor information and settings Memory Configuration View Configure memory information and settings Mass Storage Controller Configuration View Configure mass storage controller information and settings Serial Port Configuration View Configure serial port information and settings USB Configuration View Configure USB information and settings PCI Configuration View Configure PCI information and settings System Acoustic and Performance View Configure system acoustic and Configuration performance information and settings 5 3 2 2 1 Processor Screen The Processor screen allows the user to view the processor core frequency system bus frequency and to enable or disable several processor options This screen also allows the user to view information about a specific processor To access this screen from the Main screen select Advanced Processor Revision 1 0 41 Intel order number E65697 003 Setup Item Processor ID Core Frequency
57. S1064e controller that supports x4 PCI Express link widths and is a single function PCI Express end point device The SAS controller supports the SAS protocol as described in the Serial Attached SCSI Standard version 1 0 and also supports SAS 1 1 features A 32 bit external memory bus off the SAS1064e controller provides an interface for Flash ROM and NVSRAM Non volatile Static Random Access Memory devices The optional Intel SAS Entry RAID Module AXX4SASMOD provides four SAS connectors that support up to four hard drives with a non expander backplane or up to eight hard drives with an expander backplane 3 6 Integrated Baseboard Management Controller The ServerEngines LLC Pilot II Integrated BMC is provided by an embedded ARMS controller and associated peripheral functionality that is required for IPMI based server management Firmware usage of these hardware features is platform dependant The following is a summary of the Integrated BMC management hardware features used by the ServerEngines LLC Pilot II Integrated BMC 250 MHz 32 bit ARM9 Processor Memory Management Unit MMU Two 10 100 Ethernet Controllers with NC SI support 16 bit DDR2 667 MHz interface Dedicated RTC Revision 1 0 23 Intel order number E65697 003 Functional Architecture IntelP amp P Server Board S3420GP TPS 12 10 bit ADCs Eight Fan Tachometers Four PWMs Battery backed Chassis Intrusion I O Register JTAG Master Six 1 C interfaces G
58. TPS Setupitem Options Help Text Set Administrator 123aBcD Administrator password is used to This option is only to control Password control change access in BIOS Setup access to the setup Utility Administrator has full Only alphanumeric characters can be access to all the setup used Maximum length is 7 characters It items Clearing the is case sensitive Administrator password also Note Administrator password must be clears the user password set in order to use the user account Set User Password 123aBcD User password is used to control entry Available only if the access to BIOS Setup Utility administrator password is Only alphanumeric characters can be installed This option only used Maximum length is 7 characters It Protects the setup is case sensitive User password only has Note Removing the administrator limited access to the setup password also automatically removes items the user password Front Panel Lockout Enabled If enabled locks the power button and Disabled reset button on the system s front panel If Enabled is selected power and reset must be controlled via a system management interface 5 3 2 4 Server Management Screen The Server Management screen allows the user to configure several server management features This screen also provides an access point to the screens for configuring console redirection and displaying system information To access this screen from the
59. This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance 10 3 4 VCCI Japan CORE FALERES ERE ERMER VCCI os CEDC IFAB F RRTRETT CORE KERK CTIEFI 4 2 E 2BMELTIETH CORBPAIYAPTLEY ay ERIC LT FRHSNDE BBS FROFCEPHVETF BUER EAR HED TELUBENU RO 4LTFAN English translation of the notice above This is a Class B product based on the standard of the Voluntary Control Council for Interference VCCI from Information Technology Equipment If this is used near a radio or television receiver in a domestic environment it may cause radio interference Install and use the equipment according to the instruction manual 100 Revision 1 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Regulatory and Certification Information 10 3 5 BSMI Taiwan The BSMI Certification Marking and EMC warning is located on the outside rear area of the product ERG e FARE an TER EARP ERR JAER ERATIS Cra E TRU F c ERIS EKA LE EPER 10 3 6 RRL Korea Following is the RRL certification information for Korea English translation of the notice above Type of Equipment Model Name On License and Product Name of Certification Recipient Intel Corporation Date of Manufacturer Refer to date code on product ARON 10 3 7 CNCA CCC China The CCC Certification Mar
60. X O O X X X X Crisis recovery has been initiated because of a user request Ox31h X X O O X X X O Crisis recovery has been initiated by software corrupt flash Ox34h X X O OIX O X X Loading crisis recovery capsule Ox35h X X O O X O X O handing off control to the crisis recovery capsule Ox3Fh X X O OJO O O O Crisis recovery capsule failed integrity check of capsule descriptors Runtime Phase EFI Operating System Boot OXF2h O O O O X X O X Signal that the OS has switched to virtual memory mode OXF4h O O O O X O X X Entering the sleep state OXF5h O O O O X O X O Exitng the sleep state OXF8h O O O olo X X X Ra system has requested EFI to close boot services has been Progress Code OXF9h O X X OX X X X Resetting the keyboard OxFAh O X X O X X X O Disabling the keyboard 112 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Appendix D POST Code Errors Appendix D POST Code Errors Whenever possible the BIOS outputs the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware that is being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes a progress code can be customized to fit the data width The higher the data bit the higher th
61. a set of DDR3 DIMMs on the same memory channel row fails HW Memory BIST but usable memory remains available the BIOS emits a beep code and displays POST Diagnostic LED code OxEB momentarily during the beeping and then continues POST If all of the memory fails HW 16 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Functional Architecture Memory BIST the system acts as if no memory is available beeping and halting with the POST Diagnostic LED code OxE8 No Usable Memory displayed e OxEA Channel Training Error If the memory initialization process is unable to properly perform the DQ DQS training on a memory channel the BIOS emits a beep code and displays POST Diagnostic LED code SEA momentarily during the beeping If there is usable memory in the system on other channels POST memory initialization continues Otherwise the system halts with POST Diagnostic LED code OxEA staying displayed e OxED Population Error If the installed memory contains a mix of RDIMMs and UDIMMs the system halts with POST Diagnostic LED code OxED e OxEE Mismatch Error If more than two quad ranked DIMMs are installed on any channel in the system the system halts with POST Diagnostic LED code OxEE 3 2 3 Publishing System Memory e The BIOS displays the Total Memory of the system during POST if Quiet Boot is disabled in the BIOS setup This is the total size of memory discovered by the BIOS during POST and is the sum
62. al Name P3V3 AUX RMII IBMC RMM3 MDIO 3 P3V3 AUX 4 RMII IBMC RMM3 MDC 5 GND 6 RMII IBMC RMM3 RXD1 GND RMII IBMC RMM3 RXDO 9 GND RMII_IBMC_RMM3_CRS_DV GND CLK_50M_RMM3 GND RMII_IBMC_RMM3_RX_ER GND RMII_IBMC_RMM3_TX_EN GND GND RMII IBMC RMM3 TXDO GND RMII IBMC RMM3 TXD1 P3V3 AUX SPI IBMC BK CS N 25 P3V3 AUX TP RMM3 SPI WE 27 P3V3 AUX SPI IBMC BK DO GND SPI IBMC BK CLK GND SPI IBMC BK DI GND FM RMM3 Present N 6 3 2 LCP IPMB Header Table 35 LPC IPMB Header Pin out J1H2 3 SMB IPMB 5VSB CLK Integrated BMC IMB 5V standby clock line P5V STBY 5 V standby power 6 3 3 HSBP Header Table 36 HSBP Header Pin out J1J1 Pin Signal Name 1 SMB HSBP 5V DAT 2 GND 3 SMB HSBP SV CLK 4 FM HSBP ADD C2 6 3 4 SGPIO Header Revision 1 0 Table 37 SGPIO Header Pin out J1J3 Pin Signal Name Description SGPIO CLOCK SGPIO Clock Signal Intel order number E65697 003 Connector Header Locations and Pin outs 67 Connector Header Locations and Pin outs IntelPEP Server Board S3420GP TPS 2 SGPIO LOAD SGPIO Load Signal 3 SGPIO DATAOUTO SGPIO Data Out 4 SGPIO DATAOUT1 SGPIO Data In 6 4 Front Control Panel Connector The server board provides a 24 pin SSI front panel connector J1C1 for use with Intel and third party chassis The following table provides the pin out for this connector Table 38 Front Panel SSI Standard 24 pin Conne
63. alues shown in the following table If the current limits are exceeded the power supply shuts down and latches off The latch is cleared by toggling the PSON signal or using an AC power interruption The power supply is not damaged from repeated power cycling in this condition 12 V and 5 VSB are protected under over current or shorted conditions so no damage can occur to the power supply Auto recovery feature is a requirement on 5 VSB rail Table 64 Over Current Protection OCP VOLTAGE OVER CURRENT LIMIT PO Mn Max E Zin 20A 27A 5VSB N A 4A 9 4 12 2 Over Voltage Protection OVP The power supply over voltage protection is locally sensed The power supply shuts down and latches off after an over voltage condition occurs You can clear this latch by toggling the PSON signal or using an AC power interruption The following table contains the over voltage limits The values are measured at the output of the power supply s connectors The voltage never exceeds the maximum levels when measured at the power pins of the power supply connector during any single point of fail The voltage never trips any lower than the minimum levels when measured at the power pins of the power supply connector Exception 5 VSB rail should be able to recover after an over voltage condition occurs Table 65 Over voltage Protection OVP Limits Output Voltage Minimum V Maximum V Revision 1 0 93 Intel order number E65697 003 Design and Env
64. and the system will boot to the EFI shell The EFI shell then executes the Startup nsh batch file to start the flash update process The user should then switch off the power and return the recovery jumper to its normal position The user should not interrupt the BIOS POST on the first boot after recovery When the flash update completes Remove the recovery media Turn off the system power Restore the jumper to its original position Turn on the system power Re flash any custom blocks such as user binary or language blocks m Bo ES The system should now boot using the updated system BIOS Revision 1 0 83 Intel order number E65697 003 Intel amp Light Guided Diagnostics IntelP amp P Server Board S3420GP TPS 8 Intel Light Guided Diagnostics The server board has several on board diagnostic LEDs to assist in troubleshooting board level issues This section shows where each LED is located on the server board and describes the function of each LED 8 1 System Status LED The server board provides a system status indicator LED on the front panel This indicator LED has specific states and corresponding interpretation as shown in the following table Table 53 Front Panel Status LED Behavior Summary Criticality Off N A Not ready AC power off If no degraded non critical critical or non recoverable conditions exist Amber Solid on Critical non Fatal alarm system has failed or shutdown recoverable Thermtrip asse
65. are Force Update Mode Enabled 7 1 CMOS Clear and Password Reset Usage Procedure The CMOS Clear J1F5 and Password Reset J1F2 recovery features are designed such that the desired operation can be achieved with minimal system downtime The usage procedure for these two features has changed from previous generation Intel server boards The following procedure outlines the new usage model 7 1 1 Clearing the CMOS To clear the CMOS perform the following steps Power down the server Do not unplug the power cord Open the server chassis For instructions see your server chassis documentation Move jumper J1F5 from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait five seconds Remove AC power Move the jumper back to the default position covering pins 1 and 2 Close the server chassis qeu TNI m 8 Power up the server The CMOS is now cleared and can be reset by going into the BIOS setup Note Removing AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after the procedure is followed and AC power is re applied If this happens remove the AC power cord again wait 30 seconds and re install the AC power cord Power up the system and proceed to the F2 BIOS Setup utility to reset the preferred settings 7 1 2 Clearing the Password To clear the password perform the foll
66. ated BMC provides IPMI management of sensors It polls sensors to monitor and report system health IPMI interfaces o Host interfaces include system management software SMS with receive message queue support and server management mode SMM o Terminal mode serial interface o IPMB interface o LAN interface that supports the IPMI over LAN protocol RMCP RMCP Serial over LAN SOL ACPI state synchronization The Integrated BMC tracks ACPI state changes provided by the BIOS Integrated Baseboard Management Controller Integrated BMC self test The Integrated BMC performs initialization and run time self tests and makes results available to external entities For more information refer to the IPMI 2 0 Specification 4 1 2 Non IPMI Features The Integrated BMC supports the following non IPMI features This list does not preclude support for future enhancements or additions In circuit Integrated BMC firmware update Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality Chassis intrusion detection and chassis intrusion cable presence detection Basic fan control using TControl version 2 SDRs Acoustic management Support for multiple fan profiles Signal testing support The Integrated Baseboard Management Controller Integrated BMC provides test commands for setting and getting platform signal states The Integrated Baseboard Management Controller Integrated BMC generates diagnostic
67. aveur P6 Ard ms 85v 816 ak me vio se anna Abt Lee seno e Grund Ground SE 550 B5 825 aon ws aee 554 33v Ae Ave 824 aeg a Gud sm mama mm B25 3 3V A25 AD 24 B56 AD 03 A56 Ground 78 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Connector Header Locations and Pin outs 6 7 The AD 02 B30 AD 19 A30 Ground B 31 61 5V A61 5V as asv as ap Fan Headers server board provides five SSI compliant 4 pin fan headers to be used as the CPU and chassis The pin configuration for each of the 4 pin fan headers is identical and defined in the following table One 4 pin fan headers are designated as processor cooling fans CPU fan J6D1 SYS1 fan J1J4 SYS2 fan J6J2 SYS3 fan J7J1 SYS4 fan J6B1 Table 51 SSI 4 pin Fan Header Pin out J6E1 J1J4 J6J2 J7J1 J6B1 Pin Signal Name Description 1 Ground Ground is the power supply ground 2 12V Power supply 12 V 3 Fan Tach FAN TACH signal is connected to the Integrated BMC to monitor the fan speed 4 Fan PWM FAN PWM signal to control fan speed Revision 1 0 79 Intel order number E65697 003 Jumper Blocks IntelP amp P Server Board S3420GP TPS 7 Jumper Blocks The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server board Farce Update Update k ir E
68. become available by scrolling off the left or right of the current selections 5 3 2 Server Platform Setup Utility Screens The following sections describe the screens available for the configuration of a server platform In these sections tables are used to describe the contents of each screen These tables follow the following guidelines e The Setup Item Options and Help Text columns in the tables document the text and values displayed on the BIOS Setup screens e Inthe Options column the default values display in bold These values are not displayed in bold on the BIOS Setup screen the bold text in this document serves as a reference point e The Comments column provides additional information where it may be helpful This information does not display on the BIOS Setup screens e Information enclosed in angular brackets lt gt in the screen shots identifies text that can vary depending on the option s installed For example Current Date is replaced by the actual current date e Information enclosed in square brackets in the tables identifies areas where the user must type in text instead of selecting from a provided option e Whenever information is changed except Date and Time the system requires a save and reboot to take place Pressing lt ESC gt discards the changes and boots the system according to the boot order set from the last boot 5 3 2 1 Main Screen The Main screen is the first screen displaye
69. beep codes for fault conditions System GUID storage and retrieval Front panel management The Integrated Baseboard Management Controller Integrated BMC controls the system status LED and chassis ID LED It supports secure lockout of certain front panel functionality and monitors button presses The chassis ID LED is turned on using a front panel button or a command Power state retention Power fault analysis Intel Light Guided Diagnostics Revision 1 0 31 Intel order number E65697 003 Platform Management IntelP amp P Server Board S3420GP TPS Power unit management Support for power unit sensor The Integrated Baseboard Management Controller Integrated BMC handles power good dropout conditions DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Address Resolution Protocol ARP The Integrated BMC sends and responds to ARPs supported on embedded NICs Dynamic Host Configuration Protocol DHCP The Integrated BMC performs DHCP supported on embedded NICs Platform environment control interface PECI thermal management support E mail alerting Embedded web server Integrated KVM Integrated Remote Media Redirection Lightweight Directory Authentication Protocol LDAP support 4 2 Optional Advanced Management Feature Support This section explains the advanced management features supported
70. by more than 2 25 V Each output voltage should reach regulation within 50 ms Tyout on of each other when the power supply is turned on Each output voltage should fall out of regulation within 400 msec Tou off of each other when the power supply is turned off Figure 37 and Figure 38 shows the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied Table 62 Output Voltage Timing Item Description Minimum Maximum Units T vout rise Output voltage rise time from each main output 5 0 70 Msec Tyout_on All main outputs must be within regulation of each 50 Msec other within this time Tout off All main outputs must leave regulation within this 700 Msec time Note 1 The 5 VSB output voltage rise time should be from 1 0 ms to 25 0 ms V out i i A I I i i V2 i i i i l Fd i ME I I I v3 E i I H I I I i V4 IN i E di I I I I I i I i i SZ i i i1 i te Si Tvout_off i lt i vout rise lt j Tyout on AF002709 Figure 37 Output Voltage Timing Revision 1 0 91 Intel order number E65697 003 Design and Environmental Specifications IntelP amp P Server Board S3420GP TPS Table 63 Turn On Off Timing Item Description Minimum Maximum Units L on delay Delay from AC being applied to 5 VSB being N A 1500 Msec within regulation Tac n
71. by the Integrated Baseboard Management Controller Integrated BMC firmware 4 2 1 Enabling Advanced Management Features The Integrated BMC enables the advanced management features only when it detects the presence of the Intel Remote Management Module 3 Intel RMM3 card Without the Intel RMM3 the advanced features are dormant Only the Intel Server Board S3420GPLX has a RMMS module interface 4 2 1 1 Intel RMM3 The Intel RMM3 provides the Integrated BMC with an additional dedicated network interface The dedicated interface consumes its own LAN channel Additionally the Intel RMM3 provides additional flash storage for advanced features like Web Services for Management WS MAN 4 2 2 Keyboard Video Mouse KVM Redirection The Integrated BMC firmware supports keyboard video and mouse redirection over LAN This feature is available remotely from the embedded web server as a Java applet This feature is enabled only when the Intel RMM3 is present The client system must have a Java Runtime Environment JRE version 5 0 or later to run the KVM or media redirection applets 4 2 2 1 Keyboard and Mouse The keyboard and mouse are emulated by the Integrated BMC as USB human interface devices 4 2 2 2 Video Video output from the KVM subsystem is equivalent to the video output on the local console Video redirection is available after video is initialized by the system BIOS The KVM video resolution and refresh rates will alway
72. ct boot device controller OxD4 O O X O X O X X Attempt flash update boot mode 0xD5 O O X O X O X O Transfer control to EFI boot OxD6 O O X O X O O X Trying to boot device selection OxDF O O X OJO O O O Reserved for boot device selection Pre EFI Initialization PEI Core OxEOh O O O X X X X X Entered Pre EFI Initialization phase PEI OxE1h O O O X X X X O Started dispatching early initialization modules PEIM OxE2h O O O X X X O X Initial memory found configured and installed correctly OxE3h O O O X X X O O Transfer control to the DXE Core Driver eXecution Environment DXE Core OxE4h O O O XX O X X lEntered EFI driver execution phase DXE OxE5h OO O X X O X 0O Started dispatching drivers OxE6h O O O X X O O X Started connecting drivers DXE Drivers OxE7h O O O X O O X O Waiting for user input OxE8h O O O X O X X X Checking password OxE9h O O O X O X X O Entering BIOS setup OxEAh O O O X O O Xx X Flash Update OxEEh O O O X1 0 O X X Calling Int 19 One beep unless silent boot is enabled OxEFh O O O xX O O X O Unrecoverable boot failure Revision 1 0 111 Intel order number E65697 003 Appendix C POST Code Diagnostic LED Decoder IntelP amp P Server Board S3420GP TPS Diagnostic LED Decoder O On X Off Checkpoint use Nibble Lower Nibbs B Description 8h 4h 2h 1h 8h 4h 2h 1h LED 7 6 5 4 3 2 131 0 Pre EFI Initialization Module PEIM Recovery 0x30h X
73. ctor Pin out J1C1 Pin Signal Name Pin 1 rava AUX 2 3 Key 4 P5V_STBY 5 FP PWRIEDN 6 p PN 8 s LED HDD ACTIVITY N D 4 FP PWR BINN 2 GND 14 RST FP BIN N 16 GND 18 FP_ID_BTN N 20 PU_FM_SIO_TEMP_SENSOR 22 FP NMLETN N 24 Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel buttons and LEDs The following sections describe the supported functionality of each control panel feature Note Control panel features are also routed through the bridge board connector at location J1C1 as is implemented in Intel Server Systems configured using a bridge board and a hot swap backplane 6 4 1 Power Button The BIOS supports a front control panel power button Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset It is monitored by the Integrated BMC and does not directly control power on the power supply Power Button Off to On The Integrated BMC monitors the power button and the wake up event signals from the chipset A transition from either source results in the Integrated BMC starting the power up sequence Since the processor are not executing the BIOS does not participate in this sequence The hardware receives the power good and reset signals from the Integrated BMC and then transitions to an ON state Power Button On to Off Operating system absent The S
74. d Non recoverable voltage threshold asserted Power fault Power Control Failure Fan redundancy lost insufficient system cooling This does not apply to non redundant systems Off N A Not ready AC power off if no degraded non critical critical or non recoverable conditions exist Notes 1 The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide the contribution to the system status LED 2 Support for upper non critical limit is not provided in the default SDR configuration However if a user does enable this threshold in the SDR then the system status LED should behave as described There is no precedence or lock out mechanism for the control sources When a new request arrives all previous requests are terminated For example if the chassis ID LED is blinking and the chassis ID button is pressed then the chassis ID LED changes to solid on If the button is pressed again with no intervening commands the chassis ID LED turns off 70 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Connector Header Locations and Pin outs 6 5 I O Connectors 6 5 1 VGA Connector The following table details the pin out definition of the VGA connector J7A1 Table 40 VGA Connector Pin out J7A1 Pin Signal Name 3 V IO B CONN Blue analog color signal B e Jeo Gem o e op Gem 9 TP VID CONN BG No connection TP VID CONN B1
75. d when the BIOS Setup is entered unless an error occurred If an error occurred the Error Manager screen displays instead 38 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Advance d Security Server Management Boot Options Boot Manager Logged in as lt Adn Platform ID System BIOS Version Build Date Memory Total Memory Quiet Boot Enabled Disabled POST Error Pause Enabled Disabled System Date lt Current Date gt System Time lt Current Time gt Figure 15 Setup Utility Main Screen Display Table 11 Setup Utility Main Screen Fields Setupltem Options Help Text Logged in as Information only Displays password level that setup is running in Administrator or User With no passwords set Administrator is the default mode Platform ID Information only Displays the Platform ID LX SKU S3420GPLX LC SKU S3420GPLC V SKU S3420GPV System BIOS Version Information only Displays the current BIOS version xx 7 major version yy minor version ZZZz 7 build number Build Date Information only Displays the current BIOS build date Memory Revision 1 0 39 Intel order number E65697 003 BIOS User Interface Options Enabled Disabled Quiet Boot POST Error Pause System Date System Time 5 3 2 2 Enabled Disabled Day of week MM DD YYYY HH MM SS Advanced Screen IntelP amp P Server Board S3420GP TPS Help Text
76. de noise on any output does not exceed 350 mV pk pk over the frequency band of 10 Hz to 20 MHz The measurement is made across a 1000 resistor between each of the DC outputs including ground at the DC power connector and chassis ground power subsystem enclosure The test setup uses a FET probe such as Tektronix model P6046 or equivalent 9 4 9 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the following table This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors A 10 uF tantalum capacitor is placed in parallel with a 0 1 uF ceramic capacitor at the point of measurement Table 61 Ripple and Noise 12 V 50 mVp p 50 mVp p 120 mVp p 120 mVp p 9 4 10 Timing Requirements The timing requirements for the power supply operation are as follows 5 VSB 50 mVp p 90 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Design and Environmental Specifications The output voltages must rise from 10 to within regulation limits Tyout rise within 5 ms to 70 ms except for 5 VSB in which case it is allowed to rise from 1 0 ms to 25 ms The 3 3 V 5 V and 12 V output voltages should start to rise approximately at the same time All outputs must rise monotonically The 5 V output must be greater than the 3 3 V output during any point of the voltage rise The 5 V output must never be greater than the 3 3 V output
77. de on the POST code diagnostic LEDs found on the back edge of the server board To assist in troubleshooting a system hang during the POST process The diagnostic LEDs can be used to identify the last POST process executed Table 54 POST Code Diagnostic LED Location A Status LED F Diagnostic LED 4 B ID LED G Diagnostic LED 3 C Diagnostic LED 7 MSB LED H Diagnostic LED 2 D Diagnostic LED 6 l Diagnostic LED 1 E Diagnostic LED 5 J Diagnostic LED 0 LSB LED Revision 1 0 Intel order number E65697 003 85 Design and Environmental Specifications IntelP amp P Server Board S3420GP TPS 9 Design and Environmental Specifications 9 1 Intel Server Board S3420GP Design Specifications The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 55 Server Board Design Specifications 0 C to 55 C 32 F to 131 F Shock Packaged 20 pounds 36 inches 20 to 40 pounds 30 inches 40 to 80 pounds 24 inches 80 to 100 pounds 18 inches 100 to 120 pounds 12 inches 120 pounds 9 inches Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Chassis design must provide proper airflow to avoid exceeding the Intel Xeon processor maximum case temperature Disclaimer Note Intel Corporation server
78. der Boot Options Floppy Disk 1 lt Available Floppy Disk gt Floppy Disk 2 lt Available Floppy Disk gt Figure 32 Setup Utility Floppy Order Screen Display Table 28 Setup Utility Floppy Order Fields Options Help Text Floppy Disk 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Floppy Disk 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 5 Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices To access this screen from the Main screen select Boot Options gt Network Device Order Boot Options Network Device 1 lt Available Network devices gt Network Device 2 lt Available Network devices gt Figure 33 Setup Utility Network Device Order Screen Display 62 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Table 29 Setup Utility Network Device Order Fields Options Help Text Network Device 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Network Device 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 7 Boot Manager Screen The Boot Manager screen allo
79. ditional power related connector Revision 1 0 Intel order number E65697 003 Connector Type Count Main power CPU power P S aux CPU sockets 1156 on sockets 240 DaUSB 8 Comet JS Heer Jo Header 24 Header 4 Card Edge 9 Comedor 60 65 Connector Header Locations and Pin outs IntelPEP Server Board S3420GP TPS One SSI compliant 2x4 pin power connector J9C1 which provides 12 V power to the CPU VRD The following tables define the connector pin outs Table 32 Baseboard Power Connector Pin out J9A1 Pin Signal Color Pin Signal Color Orange 12Vdc Be 6 sv 8 _ PWRGD_PS Gray 9 svse Table 33 SSI Processor Power Connector Pin out J9C1 Teno Bas 6 L Yelow rbiack avec Yelow black 6 3 System Management Headers 6 3 1 Intel Remote Management Module 3 Intel RMM3 Connector A 34 pin Intel RMM 3 connector J2C1 is included on the server board to support the optional Intel Remote Management Module 3 This server board does not support third party management cards Note This connector is not compatible with the Inte Remote Management Module Inte RMM or the Intel Remote Management Module 2 Intel RMM2 Table 34 Intel RMM3 Connector Pin out J2C1 66 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Signal Name Pin Sign
80. dling esee 113 Table 70 POST Error Beep Codes 2 1 sse eene nennen 117 xii Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS List of Tables This page intentionally left blank Revision 1 0 xiii Intel order number E65697 003 Introduction IntelPEP Server Board S3420GP TPS 1 Introduction This Technical Product Specification TPS provides board specific information detailing the features functionality and high level architecture of the Intel Server Board S3420GP In addition you can obtain design level information for specific subsystems by ordering the External Product Specifications EPS or External Design Specifications EDS for a given subsystem EPS and EDS documents are not publicly available and must be ordered through your local Intel representative 1 4 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Server Board Overview Chapter 3 Functional Architecture Chapter 4 Platform Management Chapter 5 BIOS User Interface Chapter 6 Connector Header Locations and Pin outs Chapter 7 Jumpers Blocks Chapter 8 Intel Light Guided Diagnostics Chapter 9 Design and Environmental Specifications Chapter 10 Regulatory and Certification Information Appendix A Integration and Usage Tips Appendix B Integrated BMC Sensor Tables App
81. e Hard Disks gt Hard Disk 2 lt Available Hard Disks gt Figure 30 Setup Utility Hard Disk Order Screen Display Table 26 Setup Utility Hard Disk Order Fields Setup Wem Options Help Text Hard Disk 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Hard Disk 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 3 CDROM Order Screen The CDROM Order screen allows the user to control the CDROM devices To access this screen from the Main screen select Boot Options CDROM Order Boot Options CDROM 7 Available CDROM devices CDROM 72 Available CDROM devices Figure 31 Setup Utility CDROM Order Screen Display Table 27 Setup Utility CDROM Order Fields Revision 1 0 61 Intel order number E65697 003 BIOS User Interface IntelP amp P Server Board S3420GP TPS Setupltem Options Help Text CDROM 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group CDROM 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 4 Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives To access this screen from the Main screen choose Boot Options gt Floppy Or
82. e granularity of information that can be sent on the progress port The progress codes may be reported by the system BIOS or option ROMs The Response section in the following table is divided into three types No Pause The message displays on the screen during POST or in the Error Manager The system continues booting with a degraded state The user may want to replace the erroneous unit The setup POST error Pause setting does not have any effect with this error Pause The message displays on the Error Manager screen and an error is logged to the SEL The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to continue booting Halt The message displays on the Error Manager screen an error is logged to the SEL and the system cannot boot unless the error is resolved The user must replace the faulty part and restart the system The setup POST error Pause setting does not have any effect with this error Table 69 POST Error Messages and Handling 0113 Fixed Media The SAS RAID firmware cannot run properly The user should attempt to Pause reflash the firmware PCI out of resources error Pause Revision 1 0 113 Intel order number E65697 003 Appendix D POST Code Errors IntelPEP Server Boa Error Code 8111 8120 8121 8130 8131 8140 8141 8160 8161 8170 8171 8180 8181 8190 8198 8300 84F2
83. e ir trac toda eadeni tti o Rr ao eden 28 3 9 Intel UO Acceleration Technolgy 2 Intel I OAT2 a a aaa 29 3 9 1 Direct Cache Access DCA encina ee 29 3 10 Intel Virtualization Technology for Directed UO Intel VT d 29 4 Platform Managemen t U U u o enin na u Y nri 30 4 1 Feature Support pn 30 4 1 1 IPMIE2 0 Feat resz orco etr ertet are aar 30 4 1 2 Non IPMI Features esses enne enne nemen enne nnne nenne rennen nnns 31 4 2 Optional Advanced Management Feature Support 32 4 2 1 Enabling Advanced Management Features 32 4 2 2 Keyboard Video Mouse KVM Redirection 32 4 2 3 Media RedifeeliQls uu cet A Oei Red ded suae Re 33 4 2 4 Web Services for Management WS MAN 34 4 2 5 Local Directory Authentication Protocol DAP 34 4 2 6 Embedded WebDSerVer oe ee e eerte acl quc edes eade Ls 34 4 3 Management Engine ME iio ed t ecd tute at 34 5 BIOS User Interface uuu uu u inr ienke suns is 35 5 1 Logo Diagnostic ocre P P 35 5 2 BIOS Boot Popup MENU u u ua uuu tantaq uki Re SER a De dd eR eara a n 35 5 3 BIOS Setup tili y ree rhet etre wide he nnn asss ER RR mm ERREUR Re danske 35 5 3 1 EIST aT HII LEE 35 5 3 2 Server Platform Setup Utility Screens 38 5
84. e or negative hysteresis Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the Control Panel Status LED Standby Some sensors operate on standby power These sensors may be accessed and or generate events when the main system power is off but AC power is present Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Sensor Name IPMI Watchdog Physical Scrty FP Interrupt NMI System Event Log System Event System Event BB 1 05 PCH Revision 1 0 Platform Applicabilit y Chassis Intrusion is chassis specific Appendix B Integrated BMC Sensor Tables Table 66 Integrated BMC Core Sensors Sensor Type Watchdog 2 23h Physical Security 05h Critical Interrupt 13h Event Logging Disabled 10h System Event 12h Voltage 02h Event Event Offset Contrib Assert Reading Triggers To System De Type Status assert 00 Timer expired status only 01 Hard reset Sensor Specific 02 Power down 6Fh 03 Power cycle 08 Timer interrupt 00 Chassis intrusion Specific 6Fh 04 LAN least Degraded lost 00 Front panel NMI diagnostic interrupt Sensor Specific 6Fh Sensor Specific 02 Log area reset cleared 6Fh Sensor Specific 04 PEF action 6Fh Threshold u I c nc Ze 01h 3 c Non fatal Intel order number E65697 003
85. eir published operating or non operating limits Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright O Intel Corporation 2009 Revision 1 0 iii Intel order number E65697 003 Table of Contents IntelP amp P Server Board S3420GP TPS Table of Contents 1 At MU CEI pee 2 1 1 Chapter Outlines EE 2 1 2 Server Board Use Disclaimer e ut eS Eae e itus DR Habe ARR Lepus 2 De e NEE 1 2 1 Intel Server Board S3420GP Feature Set 1 2 2 Server Board Layout ee ettet reperi ues ign e c CER dean UD Fee ER RYE da 3 2 2 1 Server Board Connector and Component Layout 4 2 2 2 Intel Server Board S3420GP Mechanical Drawings coconococcoccncncnninincnrnrininnnnoso 6 2 2 3 Server Board Rear I O Layout iii cete 12 3 Functional Architecture comoda rin 13 3 1 Processor UDS ys IO Mosca 14 3 1 1 Intel Xeon 3400 Processor mwmsmisrrsresrrervesrereresvresereeresersesereseresereseresesrvesee 14 3 1 2 Intel Turbo Boost Technology 15 3 1 3 Simultaneous Multithreading SMT 15 3 1 4 Enhanced Intel SpeedStep Technologn s e ieseeeiseieiieiesireresresierrerrsrrereereeren 15 3 2 e E EE 15 3 2 1 Memory Sizing and Configuration uude Sit 16 3 2 2 Post Error Codes is 16
86. el amp Server Board S3420GPLX ntel amp Remote Management Module III RMM3 2 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Overview 2 2 Server Board Layout ms eus p Figure 1 Intel Server Board S3420GPLX Picture Revision 1 0 3 Intel order number E65697 003 Overview IntelP amp P Server Board S3420GP TPS 2 2 1 Server Board Connector and Component Layout The following figure shows the board layout of the server board Each connector and major component is identified by a number or letter and 2 provides the description A BCD F G K L M I I m O O DO a Ha rN 5 DO DO o s OD CO DO D BIO D 5 EWB P RE o D O ji IO AF003290 Y Figure 2 Intel Server Board S3420GP Layout 4 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Overview Table 2 Major Board Components
87. elds Disabled Serial Port A Serial Port B None RTS CTS Console redirection allows a serial port to be used for server management tasks Disabled No console redirection Serial Port A Configure serial port A for console redirection Serial Port B Configure serial port B for console redirection Enabling this option disables the display of the Quiet Boot logo screen during POST Flow control is the handshake protocol Setting must match the remote terminal application None Configure for no flow control RTS CTS Configure for hardware flow control Serial port transmission speed Setting must match the remote terminal application Terminal Type PC ANSI Character formatting used for console redirection Setting must VT100 match the remote terminal application VT100 VT UTF8 Legacy OS Disabled This option enables legacy OS redirection i e DOS on serial Redirection Enabled port If it is enabled the associated serial port is hidden from the legacy OS 5 3 2 5 Server Management System Information Screen The Server Management System Information screen allows the user to view part numbers serial numbers and firmware revisions To access this screen from the Main screen select Server Management gt System Information Revision 1 0 57 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS Server Management System Information Board Part Number Board Se
88. endix C POST Code Diagnostic LED Decoder Appendix D POST Code Errors e Appendix E Supported Intel Server Chassis 1 2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system meets the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits 2 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Overview 2 Overview The Intel Server Board S3420GP is a monolithic printed circuit board PCB with features designed to support entry level severs It has three board SKUs S3420GPLX S3420GPLC and S3420GPV 2 4 Intel Server Board S3420GP Feature Set Table 1 Intel Server Board S3420GP Feature Set Description Processor Support for one Xeon 3400 Series Processor in FC LGA 1156 socket package
89. eneral purpose l O Ports 16 direct 64 serial Additionally the ServerEngines Pilot II part integrates a super I O module with the following features KCS BT Interface Two 16C550 Serial Ports Serial IRQ Support 12 GPIO Ports shared with BMC LPC to SPI Bridge SMI and PME Support The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features 24 USB 2 0 for keyboard mouse and storage devices USB 1 1 interface for legacy PS 2 to USB bridging Hardware Video Compression for text and graphics Hardware encryption 2D Graphics Acceleration DDR2 graphics memory interface Up to 1600x1200 pixel resolution PCI Express x1 support Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Functional Architecture USB Code Integrated BMC Block Diagram to Host Memory Interrupt Fan Tach 12 ADC Controller PWM 4 Thermal 1 RTC 8 Ethernet General Purpose MAC with Timers 3 RMII 2 LPC Master JTAG Master amp SPI FLash JTAG Master ARM926EJ S 16KD amp I Cache DDR II 16 bit Memory Controller 667MHz BMC amp KVMS Subsystem KCS System UART 3 BT amp Wakeup Mailboxes Control Video Output LPC Se Interface To Host PCle x1 Interface ES LPC to SPI Watchdog gr qe Flash Bridge mimer external RTC BMC amp KVMS Subsystem EE Graphics Subsystem Figure 13 Integrated BMC
90. es are listed first for example 82460GX followed by alpha entries for example AGP 4x Acronyms are followed by non acronyms Term Definition ACPI Advanced Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Address Resolution Protocal Application Specific Integrated Circuit Advanced Server Management Interface Basic Input Output System Built In Self Test BMC Baseboard Management Controller Circuitry connecting one computer bus to another allowing an agent on one to access the other Bootstrap Processor Byte 8 bit quantity CBC Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS Complementary Metal oxide semiconductor In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board DHCP Dynamic Host Configuration Protocal DPC Direct Platform Control EEPROM Electrically Erasable Programmable Read Only Memory EHCI Enhanced Host Controller Interface EMP Emergency Management Port EPS External Product Specification ESB2 Enterprise South Bridge 2 FBD Fully Buffered DIMM F MB Flexible Mother Board RB Fault Resilient Booting RU Field Replaceable Unit FSB Front Side Bus GB 1024 MB GPA Guest Physical Address G
91. es each functional area Table 9 BIOS Setup Page Layout Functional Area Description Title Bar The title bar is located at the top of the screen and displays the title of the form page the user is currently viewing It may also display navigational information Setup Item List The Setup Item List is a set of controllable and informational items Each item in the list occupies the left column of the screen A Setup Item may also open a new window with more options for that functionality on the board Item Specific Help Area The Item Specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item Help information may include the meaning and usage of the item allowable values effects of the options and so forth Keyboard Command Bar The Keyboard Command Bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys 5 3 1 2 Entering BIOS Setup To enter the BIOS Setup press the F2 function key during boot time when the OEM or Intel logo displays The following message displays on the diagnostics screen and under the Quiet Boot logo screen Press F2 to enter setup When the Setup is entered the Main screen displays However serious errors cause the system to display the Error Manager screen instead of the Main screen 5 3 1 3 Keyboard Commands The bottom right portion of the Setup screen
92. es must be obtained from all suppliers and a Material Declaration Data Sheet MDDS must be produced to illustrate compliance Due verification of random materials is required as a screening audit to verify suppliers declarations The server board complies with the following ecology regulatory requirements 96 All materials parts and subassemblies must not contain restricted materials as defined in Intel s Environmental Product Content Specification of Suppliers and Outsourced Manufacturers http supplier intel com ehs environmental htm Europe European Directive 2002 95 EC Restriction of Hazardous Substances RoHS Threshold limits and banned substances are noted below Quantity limit of 0 1 by mass 1000 PPM for Lead Mercury Hexavalent Chromium Polybrominated Biphenyls Diphenyl Ethers PBB PBDE Quantity limit of 0 01 by mass 100 PPM for Cadmium China RoHS All plastic parts that weigh gt 25gm shall be marked with the IS011469 requirements for recycling Example PC ABS EU Packaging Directive CA Lithium Perchlorate insert Perchlorate Material Special handling may apply Refer to http www dtsc ca gov hazardouswaste perchlorate This notice is required by California Code of Regulations Title 22 Division 4 5 Chapter 33 Best Management Practices for Perchlorate Materials This product part includes a battery which contains Perchlorate material German Green Dot Japan Recycling Revision 1
93. evision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Overview 0 040 31MM MAY COMPONENT HEIGHT on alzs ti3 00MM A PAD LOCATION WO COMPOMENT AND NO PIM THSOWGH ZOME E PLACES OTHE BOARD MOUNTING HOLE KEEFOST AREA WO COMPONENT ZONE 3 PLACES GO 400 C 10 16MM GROUND FADS 9PLACES O COMPONENT ZOWE 2 PLACES FOR CPU we HEATSINK G2 000 C Se u MOTHER BOARD MOUNTING HOLE SESTRICTED AREA LIMITED COMPONENT HEIGHT 0 058 MAX PLACES Dl 108 25 40MM MOTHER 50442 WOUNTINS IOLI NO COMPONENT ZOME FLAC E KEEPOUT ASEA ES PU HEATSINK BACKPLATE MOUNTING AREA WO COMPONENT ZONE O COMPONENT ZONE 4 PLACES FOR ADO OM CARD Figure 8 Intel Server Board S3420GP Secondary Side Keepout Zone Revision 1 0 11 Intel order number E65697 003 Overview IntelP amp P Server Board S3420GP TPS 2 2 3 Server Board Rear UO Layout The following figure shows the layout of the rear I O components for the server board A aa maummmmmmmm 13 4 PB A Ce eee A Serial Port A C NIC Port 1 1 Gb and Dual USB Port Connector B Video D NIC port 2 1 Gb and Dual USB Port Connector Figure 9 Intel Server Board S3420GP Rear I O Layout 12 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Functional Architecture 3 Functional Architecture The architecture and des
94. hlorate Materials This product part includes a battery which contains Perchlorate material 98 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Regulatory and Certification Information 10 3 Electromagnetic Compatibility Notices 10 3 1 FCC Verification Statement USA This device complies with Part 15 of the FCC Rules Operation is subject to two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 6497 Phone 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of these measures Reorie
95. i Tele Debut Password Clear Debut CLEAR CMOS Figure 35 Jumper Blocks J1A2 J1F1 J1F3 J1F2 and J1F5 Table 52 Server Board Jumpers J1F1 J1F2 J1F3 J1F5 J1A2 Jumper Name Pins System Results J1F5 CMOS 1 2 These pins should have a jumper in place for normal system operation Default Clear 2 3 If these pins are jumpered with AC power plugged the CMOS settings are cleared within five seconds These pins should not be jumpered for normal operation J1F1 ME Force 1 2 ME Firmware Force Update Mode Disabled Default Update 2 3 ME Firmware Force Update Mode Enabled J1F2 1 2 These pins should have a jumper in place for normal system operation Default Password Clear 2 3 If these pins are jumpered administrator and user passwords are cleared within 5 10 seconds after the system is powered on These pins should not be jumpered for normal operation J1F3 BIOS 1 2 These pins should have a jumper in place for normal system operation Default Recovery 2 3 Given that the main system BIOS will not boot with these pins jumpered system can only boot from EFI bootable recovery media with the recovery BIOS image J1A2 BMC 1 2 Integrated BMC Firmware Force Update Mode Disabled Default 80 Revision 1 0 Intel order number E65697 003 IntelP P Server Board S3420GP TPS Jumper Blocks Jumper Name Pins System Results Force Update 2 3 Integrated BMC Firmw
96. ides primary system This option is grayed Acoustics cooling before attempting to throttle memory out if CLTT is Acoustic The system will favor using throttling of enabled memory over boosting fans to cool the system if Note This option is thermal thresholds are met not available on some models 5 3 2 3 Security Screen The Security screen allows the user to enable and set the user and administrative password and to lock out the front panel buttons so they cannot be used Trusted Platform Module TPM security is NOT supported on the Intel Server S3420GP board To access this screen from the Main screen select Security Main Advanced Security BREVENE EE M E Te ROT il Boot Manager Administrator Password Status Installed Not Installed User Password Status Installed Not Installed Set Administrator Password 1234aBcD Set User Password 1234aBcD Front Panel Lockout Enabled Disabled Figure 24 Setup Utility Security Configuration Screen Display Table 20 Setup Utility Security Configuration Screen Fields Setupitem Options HelpTet Comments Administrator Password Installed Information only Indicates Status Not Installed the status of the administrator password User Password Status Installed Information only Indicates Not Installed the status of the user password Revision 1 0 53 Intel order number E65697 003 BIOS User Interface IntelP amp P Server Board S3420GP
97. ign of the Intel Server Board S3420GP is based on the Intel 3420 Chipset The chipset is designed for systems based on the Intel Xeon processor in the FC LGA 1156 socket package The chipset contains two main components Intel 3420 Chipset PCI Express switch Intel Server Board S3420GPLX only This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server board x16 connector S3420GPLX Block Diagram ATX 12 x 9 6 Slot 6 G Z DDRS Ch B fa 4 unbuffered Intel Xeon bd PA 6 registered 3400 DDR3 Ch A E DIMMs x8 connector Slot 5 A x8 connector Slot 4 x4 DMI Gen1 x8 connector Slot 3 E s x4 connector Slot 2 gt Intel 3420 82574L PCI Slot 1 gt em AGA BMC Boot SATA II Flash IBMC SERIAL 2 I Sonboard 7 VIDEO SERIAL 1 Notes User Bay FP headers headers 1 Video integrated into BMC USB USE Floppy Header Figure 10 Intel Server Board S3420GP Functional Block Diagram For S3420GPLX Revision 1 0 13 Intel order number E65697 003 Functional Architecture IntelP amp P Server Board S3420GP TPS S3420GPLC Block Diagram l ATX 12 x 9 6 Intel Xeon 3400 Processor x16 connector Slot 6 4unbuffered or 6 registered DI IMMs x8 connector Slot 5 x4 DMI Gen1 x8 connec
98. ing memory to obtain the best performance from the system DDR3 RDIMMs must always be populated using a fill farthest method DDR3 UDIMMs must always be populated on DIMM A1 A2 B1 B2 Intel Xeon 3400 Series Processors support either RDIMMs or UDIMMs RDIMM and UDIMM CANNOT be mixed The minimal memory set is DIMMA1 6 DDR3 DIMMs on adjacent slots on the same channel do not need to be identical Each socket supports a maximum of six slots Standard Intel server boards and systems that use the Intel 3420 chipset support three slots per DDR3 channel two DDR3 channels per socket and only one socket is supported on the Intel Server Board S3420GP akwn s 3 2 5 4 Memory Configuration Table Table 4 Memory Configuration Table This table defines half of the valid memory configurations You can exchange Channel A DIMMs with the DIMMs on Channel B to get another half 20 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Functional Architecture 3 3 Intel 3420 Chipset PCH The Intel 3420 Chipset component is the Platform Controller Hub PCH The PCH is designed for use with Intel processor in a UP server platform The role of the PCH in Intel Server Board 53420GP is to manage the flow of information between its eleven interfaces DMI interface to Processor PCI Express Interface PCI Interface SATA Interface USB Host Interface SMBus Host Interface SPI Interface LPC interface
99. intel Intel Server Board S3420GP Technical Product Specification SERVER BOARD inside Intel order number E65697 003 Revision 1 0 August 2009 Enterprise Platforms and Services Division Revision History IntelP amp P Server Board S3420GP TPS Revision History Revision Modifications Number May 2009 Update July 2009 Ing Update POST error code and diagram Aug 2009 1 0 Update MTBF ii Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future defini
100. ironmental Specifications IntelP amp P Server Board S3420GP TPS 94 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Regulatory and Certification Information 10 Regulatory and Certification Information 10 1 Product Regulatory Compliance Intended Application This product is to be evaluated and certified as Information Technology Equipment ITE which may be installed in offices schools computer rooms and similar commercial type locations The suitability of this product for other product certification categories and or environments such as medical industrial telecommunications NEBS residential alarm systems test equipment etc other than an ITE application will require further evaluation and may require additional regulatory approvals Note The use and or integration of telecommunication devices such as modems and or wireless devices have not been planned for with respect to these systems If there is any change of plan to use such devices then telecommunication type certifications will require additional planning If NEBS compliance is required for system level products additional certification planning and design will be required 10 1 1 Product Safety Compliance CSA 60950 1 Certification Canada or cUL CE Declaration to EU Low Voltage Directive 2006 95 EC Europe EN60950 1 EC60950 1 International CB Certificate amp Report report to include all CB country natio
101. is screen from the Main screen select Advanced gt PCI Advanced PCI Configuration Maximize Memory below 4GB Enabled Disabled Memory Mapped I O above 4GB Enabled Disabled Onboard Video Enabled Disabled Dual Monitor Video Enabled Disabled Onboard NIC1 ROM Enabled Disabled Onboard NIC2 ROM Enabled Disabled Onboard NIC iSCSI ROM Enabled Disabled NIC 1 MAC Address MAC gt NIC 2 MAC Address MAC gt Figure 22 Setup Utility PCI Configuration Screen Display 50 Revision 1 0 Intel order number E65697 003 IntelPOP Server Board S3420GP TPS BIOS User Interface Table 18 Setup Utility PCI Configuration Screen Fields Setup Item Options Maximize Memory Enabled If enabled the BIOS maximizes usage of memory below 4GB Disabled below 4 GB for OS without PAE by limiting PCIE Extended Configuration Space to 64 buses Memory Mapped UC Enabled Enable or disable memory mapped UO of 64 bit above 4GB Disabled PC devices to 4 GB or greater address space Onboard Video Enabled Onboard video controller When disabled the system Disabled Warning System video is completely disabled if requires an add in video this option is disabled and an add in video adapter Card for the video to be is not installed Seen Note This option is not available on some models Dual Monitor Video Enabled If enabled both the onboard video controller and Note This option does not Disabled an add in video adapter are e
102. ity The BIOS setup utility is a text based utility that allows the user to configure the system and view current settings and environment information for the platform devices The Setup utility controls the platform s built in devices boot manager and error manager The BIOS setup interface consists of a number of pages or screens Each page contains information or links to other pages The advanced tab in Setup displays a list of general categories as links These links lead to pages containing a specific category s configuration The following sections describe the look and behavior for platform setup 5 3 1 Operation The BIOS Setup has the following features Revision 1 0 35 Intel order number E65697 003 BIOS User Interface IntelP amp P Server Board S3420GP TPS e Localization The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard The Intel server board BIOS is only available in English e Console Redirection The BIOS Setup is functional through console redirection over various terminal emulation standards This may limit some functionality for compatibility for example color usage or some keys or key sequences or support of pointing devices 5 3 1 1 Setup Page Layout The setup page layout is sectioned into functional areas Each occupies a specific area of the screen and has dedicated functionality The following table lists and describ
103. king and EMC warning is located on the outside rear area of the product Revision 1 0 Intel order number E65697 003 Manufacturer Nation Intel Corporation Refer to country of origin marked on product Certification No On RRL certificate Obtain certificate from local Intel representative 101 Appendix A Integration and Usage Tips IntelPEP Server Board S3420GP TPS Appendix A Integration and Usage Tips When adding or removing components or peripherals from the server board AC power must be removed With AC power plugged into the server board 5 Volt standby is still present even though the server board is powered off Supports only Intel Xeon 3400 Series processor with 95 W and less Thermal Design Power TDP Does not support previous generations of the Intel Xeon processor On the back edge of the server board are diagnostic LEDs that display a sequence of amber POST codes during the boot process If the server board hangs during POST the LEDs displays the last POST event run before the hang Supports only registered DDR3 DIMMs RDIMMs and unbuffered DDR3 DIMMs UDIMMs Does not support the mixing of RDIMMs and UDIMMs For the best performance the number of DDR3 DIMMs installed should be balanced across both processor sockets and memory channels For example a two DIMM configuration performs better than a one DIMM configuration In a two DIMM configuration DIMMs should be installed in DIMM sockets A1 and A
104. l I I Tpwok_low ait I TsvS8_holdup 5 VSB m gt i Tsb_vout EI LE E I _ AC turn on off cycle la PSON turn on off cycle gt AF002710 Figure 38 Turn On Off Timing Power Supply Signals 92 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS Design and Environmental Specifications 9 4 11 Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs typically a leakage voltage through the system from standby output up to 500 mV There is no additional heat generated nor stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously It also does not trip the power supply protection circuits during turn on The residual voltage at the power supply outputs for a no load condition does not exceed 100 mV when AC voltage is applied and the PSONZ signal is de asserted 9 4 12 Protection Circuits Protection circuits inside the power supply should cause only the power supply s main outputs to shut down If the power supply latches off due to a protection circuit tripping an AC cycle OFF for 15 seconds and a PSON cycle HIGH for 1 second should reset the power supply 9 4 12 1 Over current Protection OCP The power supply has current limits to prevent the 3 3 V 5 V and 12 V outputs from exceeding the v
105. l SpeedStep Technology Intel Xeon processors support the Geyserville3 feature of the Enhanced Intel SpeedStep technology This feature changes the processor operating ratio and voltage similar to the Thermal Monitor 1 TM1 feature The BIOS implements the Geyserville3 feature in conjunction with the TM1 feature The BIOS enables a combination of TM1 and TM2 according to the processor BIOS writer s guide 3 2 Memory Subsystem The Intel Xeon 3400 series processor has an Integrated Memory Controller IMC in its package Each Intel Xeon 3400 series processor produces up to two DDR3 channels of memory Each DDR3 channel in the IMC supports up to three DDR3 RDIMM slots or up to two UDIMM slots The DDR3 RDIMM frequency can be 800 1066 1333 MHz DDR3 UDIMM Revision 1 0 15 Intel order number E65697 003 Functional Architecture IntelP amp P Server Board S3420GP TPS frequency can be 1066 1333 MHz All RDIMMs and UDIMMs include ECC Error Correction Code operation Various speeds and memory technologies are supported RAS Reliability Availability and Serviceability is not supported on the Intel Server Board S3420GP 3 2 1 Memory Sizing and Configuration The Intel Server Board S3420GP supports various memory module sizes and configurations These combinations of sizes and configurations are valid only for DDR3 DIMMs approved by Intel Corporation S3420GP BIOS supports e DIMM sizes of 1 GB 2 GB 4 GB and 8 GB e DIMMs comp
106. le 39 System Status LED Indicator States 70 Table 40 VGA Connector Pin out J7A 1 oiooocccconicnonicicncnnnncnc nara 71 Table 41 RJ 45 10 100 1000 NIC Connector Pin out J5A1 71 Table 42 RJ 45 10 100 1000 NIC Connector Pin out J6A1 71 Table 43 SATA Connector Pin out J1H4 J1H1 J1G1 J1H3 J1G3 J1F4 72 Table 44 SAS Connector Pin out J2H1 iii 72 Table 45 External Serial A Port Pin out LI9AT 73 Table 46 Internal 9 pin Serial B Header Pin out J1B2 a 73 Table 47 Internal USB Connector Pin out J1E1 J1D1 74 Table 48 Pin out of Internal USB Connector for Floppy J1J2 74 Table 49 Pin out of Internal USB Connector for low profile Intel Z U130 Value Solid State Drive JIE2 ine E ze edes EMI AD sucre d c dinate A n ener 74 Table 50 Pin out of adaptive riser slot PCI Express slot 6 75 Table 51 SSI 4 pin Fan Header Pin out J6E1 J1J4 J6J2 J7J1 J6B1 79 Table 52 Server Board Jumpers J1F1 J1F2 J1F3 J1F5 J1A2
107. m is in a low power state Sx In SMBus mode the link speed is reduced to 10 Mb s The PCIe interface incorporates two aspects a PCle SerDes electrically and a custom logic protocol 3 8 3 MAC Address Definition Each Intel Server Board S3420GPLX has the following four MAC addresses assigned to it at the Intel factory NIC 1 MAC address 28 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Functional Architecture NIC 2 MAC address Assigned the NIC 1 MAC address 1 Integrated BMC LAN Channel MAC address Assigned the NIC 1 MAC address 2 Intel Remote Management Module 3 Intel RMM3 MAC address Assigned the NIC 1 MAC address 3 Each Intel Server Board S3420GPLC has the following three MAC addresses assigned to it at the Intel factory NIC 1 MAC address NIC 2 MAC address Assigned the NIC 1 MAC address 1 Integrated BMC LAN Channel MAC address Assigned the NIC 1 MAC address 2 Each Intel Server Board S3420GPV has the following two MAC addresses assigned to it at the Intel factory lt TBD gt 3 9 Intel UO Acceleration Technolgy 2 Intel OAT2 The Intel 3420 chipset series platforms do not support Intel UO Acceleration Technology 3 9 1 Direct Cache Access DCA Direct Cache Access DCA is not supported on Intel Xeon 3400 Series processors 3 10 Intel Virtualization Technology for Directed I O Intel VT d The Intel 3420 chipset provides hardware s
108. n Move jumper from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 4 Close the server chassis Reconnect the AC cord and power up the server Perform the Integrated BMC firmware update procedure as documented in the README TXT file that is included in the given Integrated BMC firmware update package After successful completion of the firmware update process the firmware update utility may generate an error stating that the Integrated BMC is still in update mode Power down and remove the AC power cord Open the server chassis Move jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server Note Normal Integrated BMC functionality is disabled with the Force Integrated BMC Update jumper set to the enabled position The server should never be run with the Integrated BMC Force Update jumper set in this position This jumper setting should only be used when the standard firmware update process fails This jumper should remain in the default disabled position when the server is running normally 7 3 ME Force Update Jumper When performing the standard ME force update procedure the update utility places the ME into an update mode allowing the ME to load safely onto the flash device In the unlikely event ME 82 Revision 1 0 Intel order number E65697 0
109. n the server board J1E1 J1D1 provides an option to support an additional USB port each connector supporting two USB ports The following table defines the pin out of the connector Revision 1 0 73 Intel order number E65697 003 Connector Header Locations and Pin outs Table 47 Internal USB Connector Pin out J1E1 J1D1 Pin Sons Name Description 1 USB2 VBUS4 USB power port 4 3 USB ICH PAN CONN USB port 4 negative signal USB ICH P5N CONN USB port 5 negative signal 6 USB ICH PSP CONN USB por positive signal 7 Ground S Gmm o e mm IntelPEP Server Board S3420GP TPS One x connector J1J2 on the server board provides an option to support a USB floppy connector Table 48 Pin out of Internal USB Connector for Floppy J1J2 Pin Signal Name 5V USB N USB P GND K OIN One 2x5 connectors J3F2 on the server board provides an option to support an Intel Z U130 Value Solid State Drive The following table defines the pin out of the connector Table 49 Pin out of Internal USB Connector for low profile Intel Z U130 Value Solid State Drive 74 J3F2 Pin Signal Name Description USB power 5 USB Data USB port positive signal s n fm O O sc mm N LED Activity LED Intel order number E65697 003 Revision 1 0 IntelPEP Server Board S3420GP TPS 6 6 Connector Header Location
110. n window is displayed and the user is asked whether changes can be discarded If No is selected and the Enter key is pressed or if the Esc key is pressed the user is returned to where they were before Esc was pressed without affecting any existing settings If Yes is selected and the Enter key is pressed the setup is exited and the BIOS returns to the main System Options Menu screen T Select Item The up arrow is used to select the previous value in a pick list or the previous option in a menu item s option list The selected item must then be activated by pressing the Enter key y Select Item The down arrow is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the lt Enter gt key o Select Menu The left and right arrow keys are used to move between the major menu pages The keys have no affect if a sub menu or pick list is displayed Tab Select Field The lt Tab gt key is used to move between fields For example Tab can be used to move from hours to minutes in the time item in the main menu Change Value The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list Change Value The plus key on the keypad is used to change the value of the current menu item to the next value This
111. nabled for system appear on some models video The onboard video controller becomes the primary video device Onboard NIC1 ROM Enabled If enabled loads the embedded option ROM for Disabled the onboard network controllers Warning If Disabled is selected NIC1 cannot be used to boot or wake the system Onboard NIC2 ROM Enabled If enabled loads the embedded option ROM for Disabled the onboard network controllers Warning If Disabled is selected NIC2 cannot be used to boot or wake the system Onboard NIC SCSI Enabled If enabled loads the embedded option ROM for This option is grayed out ROM Disabled the onboard network controllers and not accessible if either the NIC1 or NIC2 ROMs are enabled Warning If Disabled is selected NIC1 and NIC2 cannot be used to boot or wake the system Note This option is not available on some models NIC 1 MAC Address No entry Information only 12 hex allowed digits of the MAC address Information only 12 hex digits of the MAC address NIC 2 MAC Address No entry allowed 5 3 2 2 7 System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal characteristics of the system To access this screen from the Main screen select Advanced System Acoustic and Performance Configuration Revision 1 0 51 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS
112. nal deviations BSMI Declaration of Conformity Taiwan UL 60950 1 Recognition USA 10 1 2 Product EMC Compliance Class A Compliance Note This product requires complying with Class A EMC requirements However Intel targets a 10 db margin to support customer enablement AS NZS CISPR 22 Emissions Australia New Zealand CES 003 Canada EN55022 Emissions Europe EN55024 Immunity Europe CE EMC Directive 2004 108 EC Europe CISPR 22 Emissions International KCC MIC Notice No 1997 41 EMC amp 1997 42 EMI Korea BSMI CNS13438 Emissions Taiwan FCC Part 15 Emissions USA Verification 10 1 3 Certifications Registrations Declarations UL Certification US Canada CE Declaration of Conformity CENELEC Europe Revision 1 0 95 Intel order number E65697 003 Regulatory and Certification Information IntelP amp P Server Board S3420GP TPS FCC ICES 003 Class A Attestation USA Canada C Tick Declaration of Conformity Australia MED Declaration of Conformity New Zealand BSMI Declaration Taiwan RRL Certification Korea GOST Listed on one System License Russia Belarus Listed on one System License Belarus Ecology Declaration International 10 1 4 Product Ecology Requirements Intel restricts the use of banned substances in accordance with world wide product ecology regulatory requirements Suppliers Declarations of Conformity to the banned substanc
113. nit within the processor s Note Modifying this setting may affect system performance Adjacent Cache Line Enabled Enabled Cache lines are fetched in pairs Prefetch Disabled even line odd line Disabled Only the current cache line required is fetched Note Modifying this setting may affect system performance 5 3 2 2 2 Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed This screen also allows the user to open the Configure Memory RAS and Performance screen To access this screen from the Main screen select Advanced Memory 44 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Advanced Memory Configuration Total Memory Effective Memory Current Configuration Current Memory Speed DIMM Information DIMM A1 DIMM A2 DIMM A3 DIMM B1 DIMM B2 DIMM B3 Figure 18 Setup Utility Memory Configuration Screen Display Table 14 Setup Utility Memory Configuration Screen Fields Comments Total Memory Information only The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB Effective Memory Information only The amount of memory available to the operating system in MB or GB The Effective Memory is the difference between the Total Physical Memory and the sum of all memory reserved for internal usage RAS redundancy and SMRAM This difference
114. nt or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception Revision 1 0 99 Intel order number E65697 003 Regulatory and Certification Information IntelP amp P Server Board S3420GP TPS 10 3 2 ICES 003 Canada Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe B prescrites dans la norme sur le mat riel brouilleur Appareils Num riques NMB 003 dict e par le Ministre Canadian des Communications English translation of the notice above This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications 10 3 3 Europe CE Declaration of Conformity
115. oard 110 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Appendix C POST Code Diagnostic LED Decoder Diagnostic LED Decoder O On X Off Checkpoint usa BEZ Nibble Lower Nibbs 5 Description 8h 4h 2h 1h 8h 4h 2h th LED HT 6 5 H4 3 2 1 0 0x93h O X X O X X O O Enabling the keyboard 0x94h O X X O X O X X Clearing keyboard input buffer 0x95h O X X O X O X O Reserved for keyboard Mouse only USB 0x98h O X X O X X O X Resetting the mouse Ox99h O X X O X X O O Detecting the mouse Ox9Ah O X X O X O O X Detecting the presence of mouse Ox9Bh O X X O X O O O Enabling the mouse Fixed Media OxBOh O X O O X X X X Resetting fixed media device OxB1h O X O O X X X O Disabling fixed media device OxB2h O X O o X X O X AUS presence of a fixed media device SATA hard drive detection OxB3h O X O O X X O O Enabling configuring a fixed media device Removable Media OxB8h O X O O O X X X Resetting removable media device OxB9h O X O O O X X O Disabling removable media device OXBAh O X o olo X O X Fyr Fa of a removable media device SATA CDROM OxBCh O X O O JO O X X Enabling configuring a removable media device Boot Device Selection BDS OxDO O O X O X X X X Entered the Boot Device Selection phase BDS OxD1 O O X O X X X O Return to last good boot device OxD2 O O X O X X O X Setup boot device selection policy 0xD3 O O X O X X O O Conne
116. of the individual sizes of installed DDR3 DIMMs in the system e The BIOS displays the Effective Memory of the system in the BIOS Setup The term Effective Memory refers to the total size of all active DDR3 DIMMs not disabled and not used as redundant units e The BIOS provides the total memory of the system in the main page of the BIOS setup This total is the same as the amount described by the first bullet in this section e If Quiet Boot is disabled the BIOS displays the total system memory on the diagnostic screen at the end of POST This total is the same as the amount described by the first bullet in this section e The BIOS provides the total amount of memory in the system 3 2 3 1 Memory Reservation for Memory mapped Functions A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset processor and BIOS flash spaces as memory mapped l O regions This region appears as a loss of memory to the operating system In addition to this loss the BIOS creates another reserved region for memory mapped PCIe functions including a standard 64 MB or 256 MB of standard PCI Express MMIO configuration space If PAE is turned on in the operating system the operating system reclaims all these reserved regions In addition to this memory reservation the BIOS creates another reserved region for memory mapped PCI Express functions including a standard 64 MB or 256 MB of standard PCI Express Memory Mapped I O MMIO
117. ome models Unavailable if the SAS Module AXX4SASMOD is disabled or not present Note This option is not available on some models Onboard SATA Enabled Onboard Serial ATA SATA Controller Disabled controller SATA Mode ENHANCED Compatibility AHCI SW RAID SATA Port 0 lt Not Installed Drive information SATA Port 1 lt Not Installed Drive information SATA Port 2 lt Not Installed Drive information SATA Port 3 lt Not Installed Drive information SATA Port 4 lt Not Installed Drive information SATA Port 5 lt Not Installed Drive information 5 3 2 2 4 Serial Ports Screen ENHANCED Supports up to 6 SATA ports with IDE Native Mode COMPATIBILITY Supports up to 4 SATA ports 0 1 2 3 with IDE Legacy mode and 2 SATA ports 4 5 with IDE Native Mode AHCI Supports all SATA ports using the Advanced Host Controller Interface SW RAID Supports configuration of SATA ports for RAID via RAID configuration software Intel Matrix RAID Technology with Software RAID levels 0 1 10 and 5 Disappears when the Onboard SATA Controller is disabled Information only This field is unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled Information only This field is
118. osed of DRAM using 2 Gb technology e DRAMs organized as single rank dual rank or quad rank DIMMS e DIMM speeds of 800 1066 or 1333 MT s e Registered or Unregistered unbuffered DIMMs RDIMMs or UDIMMs Note UDIMMs should be ECC and may or may not have thermal sensors RDIMMs must have ECC and must have thermal sensors S3420GP BIOS has the below limitations 256 Mb technology x4 DRAM on UDIMM and quad rank UDIMM are NOT supported x16 DRAM on UDIMM is not supported on combo routing Memory suppliers not productizing native 800 ECC UDIMMs Intel Xeon 3400 Series support all timings defined by JEDEC 256 Mb 512 Mb technology x4 and x16 DRAMs on RDIMM are NOT supported All channels in a system will run at the fastest common frequency No mixing of registered and unbuffered DIMMs 3 2 2 Post Error Codes The range OxEO OxEF of POST codes is used for memory errors in early POST In late POST this range is used for reporting other system errors e DES No Usable Memory Error If no memory is available the system emits POST Diagnostic LED code OxE8 and halts the system e 0xE8 Configuration Error If a DDR3 DIMM has no SPD information the BIOS treats the DIMM slot as if no DDR3 DIMM is present on it Therefore if this is the only DDR3 DIMM installed in the system the BIOS halts with POST Diagnostic LED code OxE8 no usable memory and halts the system e OxEB Memory Test Error If a DDR3 DIMM or
119. ovides two DDR3 channels and groups DIMMs on the board into an autonomous memory 5 The DIMM identifiers on the silkscreen on the board provide information about the channel and the processor socket to which they belong For example DIMM AT is the first slot on channel A 3 2 5 3 Memory Upgrade Rules Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the following factors Existing DDR3 DIMM population DDR3 DIMM characteristics Optimization techniques used by the Intel Nehalem processor to maximize memory bandwidth In the Independent Channel mode all DDR3 channels operate independently Slot to slot DIMM matching is not required across channels for example A1 and B1 do not have to match each other in terms of size organization and timing DIMMs within a channel do not have to match in terms of size and organization but they operate in the minimal common frequency Also Independent Channel mode can be used to support single DIMM configuration in channel A and in the Single Channel mode Revision 1 0 19 Intel order number E65697 003 Functional Architecture IntelPEP Server Board S3420GP TPS Channel A Channel B A1 A2 A3 B1 B2 B3 RDIMM X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X UDIMM X X X X X X X X X X X X You must observe the following general rules when selecting and configur
120. owing steps Power down the server Do not unplug the power cord 2 Open the chassis For instructions see your server chassis documentation Move jumper J1F2 from the default operating position covering pins 1 and 2 to the password clear position covering pins 2 and 3 Close the server chassis Power up the server and wait 10 seconds or until POST completes 6 Power down the server Revision 1 0 81 Intel order number E65697 003 Jumper Blocks IntelPEP Server Board S3420GP TPS 7 Open the chassis and move the jumper back to the default position covering pins 1 and 2 Close the server chassis Power up the server The password is now cleared and can be reset by going into the BIOS setup 7 2 Integrated BMC Force Update Procedure When performing the standard Integrated BMC firmware update procedure the update utility places the Integrated BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the Integrated BMC firmware update process fails due to the Integrated BMC not being in the proper update state the server board provides an Integrated BMC Force Update jumper J1A2 which forces the Integrated BMC into the proper update state The following procedure should be completed in the event the standard Integrated BMC firmware update process fails Power down and remove the AC power cord Open the server chassis For instructions see your server chassis documentatio
121. provides a list of commands used to navigate through the Setup utility These commands display at all times Each Setup menu page contains a number of features Each feature is associated with a value field except those used for informative purposes Each value field contains configurable parameters Depending on the security option chosen and in effect by the password a menu feature s value may or may not be changed If a value cannot be changed its field is made inaccessible and appears grayed out 36 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Table 10 BIOS Setup Keyboard Command Bar Key Option 03 Desertegen Enter Execute The Enter key is used to activate sub menus when the selected feature is a sub Command menu or to display a pick list if a selected option has a value field or to select a sub field for multi valued features like time and date If a pick list is displayed the Enter key selects the currently highlighted item undoes the pick list and returns the focus to the parent menu The lt Esc gt key provides a mechanism for backing out of any field When the Esc key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the lt Esc gt key is pressed in any sub menu the parent menu is re entered When the lt Esc gt key is pressed in any major menu the exit confirmatio
122. r L2 Cache DNE Cache RAM Information only Size of the Processor L3 Cache Donc Version Information only ID string from the Processor Current QPI Link Speed QPI Link Frequency Enabled Disabled Intel Turbo Boost Technology Enabled Disabled Enhanced Intel SpeedStep Technology Enabled Disabled Intel Hyper Threading Technology Core Multi Processing Enabled Disabled Execute Disable Bit Enabled Disabled Intel Virtualization Technology Enabled Disabled Intel Virtualization Technology for Directed 1 0 Enabled Disabled Interrupt Remapping Revision 1 0 Information only Current speed that the QPI Link is Information only Current frequency that the QPI Link is Intel Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power temperature and current specifications Enhanced Intel SpeedStep Technology allows the system to dynamically adjust processor voltage and core frequency which can result in decreased average power consumption and decreased average heat production Contact your OS vendor regarding OS support of this feature Intel HT Technology allows multithreaded software applications to execute threads in parallel within the processor Contact your OS vendor regarding OS support of this feature Enable 1 2 or All cores of installed processor packages This option is only visible if all processor in the
123. ram 30 Setup Utility Main Screen Display a 39 Setup Utility Advanced Screen Display AAA 41 Setup Utility Processor Configuration Screen Display 42 Setup Utility Memory Configuration Screen Display 45 Setup Utility Mass Storage Controller Configuration Screen Display 46 Setup Utility Serial Port Configuration Screen Display 48 Setup Utility USB Controller Configuration Screen Display 49 Setup Utility PCI Configuration Screen Display 50 Setup Utility System Acoustic and Performance Configuration Screen Display 52 Setup Utility Security Configuration Screen Display 53 Setup Utility Server Management Configuraiton Screen Display 55 Setup Utility Console Redirection Screen Display 56 Setup Utility Server Management System Information Screen Display 58 Setup Utility Boot Options Screen Display 59 Setup Utility Delete Boot Option Screen Display 60 Setup Utility Hard Disk Order Screen Display 61 Setup Utility CDROM Order Sc
124. rated BMC Sensor Tables Appendix B Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose See the Intelligent Plattorm Management Interface Specification Version 2 0 for sensor and event reading type table information Sensor Type The Sensor Type values are the values enumerated in the Sensor Type Codes table in the IPMI specification The Sensor Type provides the context in which to interpret the sensor such as the physical entity or characteristic that is represented by this sensor Event Reading Type The Event Reading Type values are from the Event Reading Type Code Ranges and Generic Event Reading Type Codes tables in the IPMI specification Digital sensors are a specific type of discrete sensor which have only two states Event Offset Triggers Event Thresholds are event generating thresholds for threshold types of sensors ul nr c nc upper non recoverable upper critical upper non critical lower non recoverable lower critical lower non critical uc lc upper critical lower critical Event Triggers are supported event generating offsets for discrete type sensors The offsets can be found in the Generic Event Reading Type Codes or Sensor Type Codes tables in the IPMI specification depending on whether the sensor event reading type is
125. reen Display 61 Setup Utility Floppy Order Screen Display 62 Revision 1 0 Intel order number E65697 003 IntelP amp P Server Board S3420GP TPS List of Figures Figure 33 Setup Utility Network Device Order Screen Display 62 Figure 34 Setup Utility Boot Manager Screen Display 63 Figure 35 Jumper Blocks J1A2 J1F1 J1F3 J1F2 and J1F5 80 Figure 36 Power Distribution Block Diagram cascada land 87 Figure 37 Output Voltage TIMING eoe io eire iere ds 91 Figure 38 Turn On Off Timing Power Supply SGionals 92 Figure 39 Diagnostic LED Placement Diagram 109 Revision10 WWW Intel order number E65697 003 List of Tables IntelPEP Server Board S3420GP TPS List of Tables Table 1 Intel Server Board S3420GP Feature Set 1 Table 2 Major Board Components r 5 Table 3 Standard Platform DIMM Nomenclature 18 Table 4 Memory Configuration Table tiere cid 20 Table 5 Optional RMM3 Advanced Management Board Features 0 cceeeeeeeeeeeeeeeeeeeeeneaaes 26 Table 6 Serial B Header J1B1 Pin out la 26 Table 7 Video Modes Zur LS hua R n l yuana nnne en 27 Table 8 Dual Video Modes
126. remote device to the server It is possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE IMG and CD ROM or DVD ROM ISO files Refer to the Tested supported Operating System List for more information It is possible to mount at least two devices concurrently The mounted device is visible to and useable by the managed system s operating system and BIOS in both pre boot and post boot states The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device It is possible to install an operating system on a bare metal server no operating system present using the remotely mounted device This may also require the use of KVM r to configure the operating system during install If either a virtual IDE or virtual floppy device is remotely attached during system boot both virtual IDE and virtual floppy are presented as bootable devices It is not possible to present only a single mounted device type to the system BIOS 4 2 3 1 Availability The default inactivity timeout is 30 minutes but may be changed through the embedded web server Media redirection sessions persist across system reset but not across an AC power loss Revision 1 0 33 Intel order number E65697 003 Platform Management IntelP amp P Server Board S3420GP TPS 4 2 4 Web Services for Management WS MAN The Integrated BMC firmware suppo
127. rial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 27 Setup Utility Server Management System Information Screen Display Table 23 Setup Utility Server Management System Information Fields e Setupltem Comments 5 3 2 6 Boot Options Screen The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the preferred boot device To access this screen from the Main screen select Boot Options 58 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface Main i STC Ea ENE Boot Options Boot Manager System Boot Timeout lt 0 65535 Boot Option 1 lt Available Boot devices gt Boot Option 2 lt Available Boot devices gt Boot Option x lt Available Boot devices gt Hard Disk Order CDROM Order Network Device Order Delete Boot Option EFI Optimized Boot Enabled Disabled Boot Option Retry Enabled Disabled Figure 28 Setup Utility Boot Options Screen Display Table 24 Setup Utility Boot Options Screen Fields Setupltem Options Help Text Boot Timeout 0 65535 The number of seconds the BIOS After entering the preferred should pause at the end of POST to timeout press the Enter key allow the user to press the F2 key for to register that timeout val
128. rted Non recoverable temperature threshold asserted Non recoverable voltage threshold asserted Power fault Power Control Failure Fan redundancy lost insufficient system cooling This does not apply to non redundant systems Uncorrectable memory error Amber Blink Non critical Non fatal alarm system is likely to fail CATERR asserted Critical temperature threshold asserted Critical voltage threshold asserted Critical fan threshold asserted VRD hot asserted SMI Timeout asserted Correctable error threshold has been reached for a failing DDR3 DIMM System OK System booted and ready Green Blink Degraded System degraded Non critical temperature threshold asserted Non critical voltage threshold asserted Non critical fan threshold asserted Fan redundancy lost sufficient system cooling maintained This does not apply to non redundant systems Power supply predictive failure Unable to use all of the installed memory more than one DDR3 DIMM installed Correctable error threshold has been reached for a failing DDR3 DIMM on a given channel 84 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS 8 2 Post Code Diagnostic LEDs Intel amp Light Guided Diagnostics During the system boot process the BIOS executes several platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST co
129. rts the Web Services for Management WS MAN specification version 1 0 4 2 5 Local Directory Authentication Protocol LDAP The Integrated BMC firmware supports the Local Directory Authentication Protocol LDAP protocol for user authentication Note that IPMI users passwords and sessions are not supported over LDAP 4 2 6 Embedded Webserver The Integrated BMC provides an embedded web server for out of band management User authentication is handled by IPMI user names and passwords Base functionality for the embedded web server includes Power Control Limited control based on IPMI user privilege Sensor Reading Limited access based on IPMI user privilege SEL Reading Limited access based on IPMI user privilege KVM Media Redirection Limited access based on IPMI user privilege Only available when the Intel RMM3 is present PMI User Management Limited access based on IPMI user privilege The web server is available on all enabled LAN channels See Appendix B for Integrated BMC core sensors 4 3 Management Engine ME Intel Management Engine is tied to essential platform functionality This Management Engine firmware includes the following applications Platform Clocks Tune PCH clock silicon to the parameters of a specific board configure clocks at run time power management clocks Thermal Report ME FW reports thermal and power information available only on PECI to host accessible
130. s Reset System powers on Clear System Event Enabled If enabled clears the System Event Log All current Log Disabled entries will be lost Note This option is reset to Disabled after a reboot FRB 2 Enable Enabled Fault Resilient Boot FRB Disabled If enabled the BIOS programs the BMC watchdog timer for approximately 6 minutes If the BIOS does not complete POST before the timer expires the BMC resets the system Revision 1 0 55 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS Setupltem Options Help Text O S Boot Watchdog Enabled If enabled the BIOS programs the watchdog timer Timer Disabled with the timeout value selected If the OS does not complete booting before the timer expires the BMC resets the system and an error is logged Requires OS support or Intel Management Software O S Boot Watchdog Power Off If the OS boot watchdog timer is enabled this is the Grayed out when the O S Timer Policy Reset system action taken if the watchdog timer expires Boot Watchdog Timer is Reset System performs a reset disabled Power Off System powers off O S Boot Watchdog 5 minutes If the OS watchdog timer is enabled this is the Grayed out when the O S Timer Timeout 10 minutes timeout value used by the BIOS to configure the Boot Watchdog Timer is 15 minutes watchdog timer disabled 20 minutes Plug amp Play BMC Enabled If enabled the BMC is detectable by OSs
131. s and Pin outs PCI Express Slot PCI Slot Riser Card Slot A PCI E Riser card will enable a PCI E add on card to be accommodated in the 1U chassis The following table shows the pin out for this riser slot Table 50 Pin out of adaptive riser slot PCI Express slot 6 Pin Signal Description Pin Signal Description B1 12V P12V A1 PRSNT1 N GND B2 12V P12V A2 12V P12V B3 RSVD P12V A3 12V P12V B4 GND GND A4 GND GND B5 SMCLK PU S6 SMBCLK A5 JTAG2 P3V3 RISER A5 B6 SMDATA PU S6 SMBDAT A6 JTAG3 JTAG S6 TDI B7 GND GND A7 JTAG4 NC B8 3 3V P3V3 A8 JTAG5 P3V3 RISER A8 JTAG1 JTAG S6 TRST N 3 3V P3V3 3 3VAUX P3V3 AUX 3 3V P3V3 KEY KEY RSVD NC GND B12 B13 GND GND REFCLKP CLK 100M SLOT6A DP B14 PETPO P2E CPU C S6 TXP 7 A14 REFCLKN CLK 100M SLOT6A DPN B15 PETNO P2E CPU C S6 TXN 7 A15 GND GND B16 GND GND A16 PERPO P2E CPU S6 RXP 7 B17 PRSNT2 N NC A17 PERNO P2E CPU S6 RXN lt 7 gt B18 GND GND A18 GND GND B19 PETP1 P2E CPU C S6 TXP 6 A19 RSVD NC B20 PETN1 P2E CPU C S6 TXN 6 A20 GND GND B21 GND GND A21 PERP1 P2E CPU S6 RXP 6 B22 GND GND A22 PERN1 P2E CPU S6 RXN lt 6 gt B23 PETP2 P2E CPU C S6 TXP 5 A23 GND GND B24 PETN2 P2E CPU C S6 TXN 5 A24 GND GND B25 GND GND A25 PERP2 P2E CPU S6 RXP lt 5 gt GND GND P2E CPU S6 RXN 5 PETP3 P2E CPU C S6 TX
132. s match the values set in the operating system 32 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Platform Management 4 2 2 3 Availability Up to two remote KVM sessions are supported The default inactivity timeout is 30 minutes however this can be changed through the embedded web server Remote KVM activation does not disable the local system keyboard video or mouse Unless the feature is disabled locally remote KVM is not deactivated by local system input KVM sessions persist across system reset but not across an AC power loss 4 2 3 Media Redirection The embedded web server provides a Java applet to enable remote media redirection This may be used in conjunction with the remote KVM feature or as a standalone applet The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears just like a local device to the server allowing system administrators or users to install software including operating systems copy files update the BIOS and so forth or boot the server from this device The following capabilities are supported The operation of remotely mounted devices is independent of the local devices on the server Both remote and local devices are usable in parallel Either IDE CD ROM floppy or USB devices can be mounted as a
133. ser Defaults from the Exit page of the BIOS Setup loads user set defaults instead of the BIOS factory defaults The recommended steps to load the BIOS defaults are 1 2 3 4 64 Power down the system Do not remove AC power Move the Clear CMOS jumper from pins 1 2 to pins 2 3 Move the Clear CMOS jumper from pins 2 3 to pins 1 2 Power up the system Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Connector Header Locations and Pin outs 6 Connector Header Locations and Pin outs 6 1 Board Connector Information The following section provides detailed information regarding all connectors headers and jumpers on the server board It lists all connector types available on the board and the corresponding reference designators printed on the silkscreen Power supply a Main memory EK 1 sms eent FIT wami Front panel F E M Header IPCI EX16 t Poes 9 Sei ATA fe Table 31 Board Connector Matrix Reference Designators J9A1 J9C1 J9J1 J6G1 6 9893 J8J2 J8J1 J9J3 J9J2 J8J4 J2C1 J2H1 J6E1 J1J4 J6J2 J7J1 J6B1 BT5C1 J5A1 J6A1 J7A1 J8A1 J1B2 J4H3 J1C1 J1D1 J1E1 J4B3 J2B2 J3B1 J4B2 J2B1 J1B1 J5J1 J1J1 J1H4 J1H1 J1G1 J1H3 J1G3 J1F4 J1H2 J1J1 J3F2 J1J3 6 2 Power Connectors The main power supply connection uses an SSI compliant 2x12 pin connector J9A1 In addition there is one ad
134. system support Intel Turbo Boost Technology Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks Contact your OS vendor regarding OS support of this feature Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions Note A change to this option requires the system to be powered off and then back on before the setting takes effect Enable Disable Intel Virtualization Technology for Directed I O Report the UO device assignment to VMM through DMAR ACPI Tables Enable Disable Intel VT d Interrupt Remapping support Only visible when Intel Virtualization Technology for Directed UO is enabled 43 Intel order number E65697 003 BIOS User Interface IntelP amp P Server Board S3420GP TPS Setup Item Options Help Text Coherency Support Enabled Enable Disable Intel VT d Coherency Only visible when Intel Disabled support Virtualization Technology for Directed I O is enabled ATS Support Enabled Enable Disable Intel VT d Address Only visible when Intel Disabled Translation Services ATS support Virtualization Technology for Directed I O is enabled Pass through DMA Enabled Enable Disable Intel VT d Pass through Only visible when Intel Support Disabled DMA support Virtualization Technology for Directed I O is enabled Hardware Prefetcher Enabled Hardware Prefetcher is a speculative Disabled prefetch u
135. tage Regulator Down Virtualization Technology Word 16 bit quantity Web Services for Management Zero Insertion Force Revision 1 0 121 Intel order number E65697 003 Reference Documents IntelPEP Server Board S3420GP TPS Reference Documents Refer to the following documents for additional information Intel Server Board S3420GP BIOS External Product Specification Intel Server Board S3420GP Common Core Integrated BMC External Product Specification 122 Revision 1 0 Intel order number E65697 003
136. tal nc Voltage Threshold Degraded Bele 02h 01h ul enc v Kone fatal Temperatur DT P Threshold Degraded Server board Temp e u l c nc 01h c Non 01h fatal nc Temperatur Threshold Degraded Front panel temp e oth u I c nc N 01h c Non fatal l Temperatur Threshold PCH Thermal Margin e 01h 01h Processor MEMTHRM Temperatur MRGN a Threshold 01h 01h Revision 1 0 107 Intel order number E65697 003 Appendix B Integrated BMC Sensor Tables Sensor Name Fan Tach Sensors Processor Therm Margin Processor Therm Ctrl 96 Processor VRD Temp CATERR PCH Thermal Trip 108 Sensor Type Platform Applicabilit Chassis specific Temperatur e 01h Temperatur e 01h Temperatur e 01h Processor 07h Temperatur e 01h IntelPEP Server Board S3420GP TPS Event Reading Type Threshold 01h Threshold 01h Threshold 01h Digital Discrete 05h Digital Discrete 03h Digital Discrete 03h Event Offset Triggers I c nc u c 01 Limit exceeded 01 State Asserted 01 State Asserted Contrib Assert Readabl Event To System De e Data Status assert Value Offsets nc Degraded g As and R T c Non De fatal Non fatal Trig Offset De As and 1 Non fatal Trig Offset De Trig Offset As and li Intel order number E65697 003 Rearm Stand by Revision 1 0 IntelP P Server Board S3420GP TPS Appendi
137. te is tested between 50 Hz and 5 kHz at duty cycles ranging from 10 90 The load transient repetition rate is only a test specification The A step load may occur anywhere within the Min load to the Max load conditions Table 59 Transient Load Requirements A Step Load Size Load Slew Rate Test capacitive Load See note 2 259 v 3v BOA 0A 50A Jo 25 Alusec 250 uF 11 0A 0 25 A usec 500 uF Revision 1 0 89 Intel order number E65697 003 Design and Environmental Specifications IntelPEP Server Board 53420GP TPS 5 VSB 0 5 A 0 25 Alusec Notes 1 Step loads on each 12 V output may happen simultaneously and should be tested that way 9 4 6 Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges Table 60 Capacitve Loading Conditions 9 4 7 Output Minimum Maximum Units 3 3 V 100 2200 uF 5V 400 2200 uF 12 V 500 2200 uF 12 V 1 350 uF 5 VSB 20 350 uF Closed loop Stability The power supply is unconditionally stable under all line load transient load conditions including capacitive load ranges A minimum of 45 phase margin and 10 dB gain margin is required The power supply manufacturer provides proof of the unit s closed loop stability with local sensing through the submission of Bode plots Closed loop stability is ensured at the maximum and minimum loads as applicable 9 4 8 Common Mode Noise The Common Mo
138. telPEP Server Board S3420GP TPS Functional Architecture 3 2 5 1 TableMemory Subsystem Operating Frequency Determination The rules for determining the operating frequency of the memory channels are simple but not necessarily straightforward There are several limiting factors including the number of DIMMs on a channel and organization of the DIMM that is either single rank SR dual rank DR or quad rank QR The speed of the processor s IMC is the maximum speed possible The speed of the slowest component the slowest DIMM or the IMC determines the maximum frequency subject to further limitations A single 1333 MHz DIMM SR or DR on a channel may run at full 1333 MHz speed If two SR DR DIMMs are installed on a channel the speed is limited to 1066 MHZ A single QR RDIMM on a channel is limited to 1066 MHz Two QR RDIMMs or a mix of QR SR DR on a channel is limited to 800 MHz 3 2 5 2 Memory Subsystem Nomenclature 1 DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets The memory channels are identified as channels A B 3 For Intel Xeon 3400 Series each socket can support a maximum of six DIMM sockets three DIMM sockets per channel which can support a maximum of six DIMM sockets 4 The Intel Xeon 3400 Series processor on the Intel Server Board S3420GP is populated on the processor socket It has an Integrated Memory Controller IMC The IMC pr
139. tem 3 7 Video Support The server board includes a video controller in an on board Server Engines Integrated Baseboard Management Controller along with 64 MB of video DDR2 SDRAM The SVGA subsystem supports a variety of modes up to 1600 x 1200 resolution in 8 16 32 bpp modes under 2D It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate The video is accessed using a standard 15 pin VGA connector found on the back edge of the server board The on board video controller can be disabled using the BIOS Setup utility or when an add in video card is detected The system BIOS provides the option for dual video operation when an add in video card is configured in the system 3 7 1 Video Modes The integrated video controller supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 7 Video Modes 2D Mode Refresh Rate Hz 2D Video Mode Support 8 bpp 16 bpp 32 bpp 640x480 60 72 75 85 90 100 120 160 200 Supported Supported Supported 800x600 60 70 72 75 85 90 100 120 160 Supported Supported Supported 1024x768 60 70 72 75 85 90 100 Supported Supported Supported 1152x864 43 47 60 70 75 80 85 Supported Supported Supported 1280x1024 60 70 74 75 Supported Supported Supported 1600x1200 52 Supported Supported Supported 3 7 2 Dual Video The BIOS supports both single video and dual video modes The dual
140. the processor is operating below power temperature and current limits This results in increased performance for both multi threaded and single threaded workloads Intel Turbo Boost Technology operation Turbo Boost operates under Operating System control It is only entered when the operating system requests the highest PO performance state Turbo Boost operation can be enabled or disabled by BIOS Turbo Boost converts any available power and thermal headroom into higher frequency on active cores At nominal marked processor frequency many applications consume less than the rated processor power draw Turbo Boost availability is independent of the number of active cores Maximum Turbo Boost frequency depends on the number of active cores and varies by processor configuration The amount of time the system spends in Turbo Boost operation depends on workload operating environment and platform design If the processor supports the Intel Turbo Boost Technology feature the BIOS Setup provides an option to enable or disable this feature The default state is enabled 3 1 3 Simultaneous Multithreading SMT Most Intel Xeon processors support Simultaneous Multithreading SMT The BIOS detects processors that support this feature and enables the feature during POST If the processor supports this feature the BIOS Setup provides an option to enable or disable this feature The default is enabled 3 1 4 Enhanced Inte
141. tializing memory such as ECC init 0x28h X X O XIO X X X Testing memory PCI Bus 0x50h X O X O X X X X Enumerating PCI buses 0x51h X O X O X X X O Allocating resources to PCI buses 0x52h X O X O X X O X Hot Plug PCI controller initialization 0x53h X O X O X X O O Reserved for PCI bus 0x54h X O X O X O X X Reserved for PCI bus 0x55h X O X O X O X O Reserved for PCI bus 0x56h X O X O X O O X Reserved for PCI bus 0x57h X O X O X O O O Reserved for PCI bus USB 0x58h X O X OJO X X X Resetting USB bus Ox59h X O X olo Xx X O Reserved for USB devices ATA ATAPI SATA Ox5Ah X O X O O X O X Resetting SATA bus and all devices Ox5Bh X O X O OD X O O Detecting the presence of ATA device Ox5Ch X O X O O O X X Enable SMART if supported by ATA device Ox5Dh X O X O O O Xx 0 Reserved for ATA SMBUS Ox5Eh X O X OJO O O X Resetting SMBUS 0x5Fh X O X OJO O O O Reserved for SMBUS Local Console 0x70h X O O O X X X X Resetting the video controller VGA Ox71h X O O O X X X O Disabling the video controller VGA 0x72h X O O O X X O X Enabling the video controller VGA Remote Console Ox78h X O O O O X X X Resetting the console controller 0x79h X O O O O X X O Disablingthe console controller Ox7Ah X O O O O X O X Enabling the console controller Keyboard only USB 0x90h O X X O X X X X Resetting the keyboard 0x91h O X X O X X X O Disabling the keyboard 0x92h O X X O X X O X Detecting the presence of the keyb
142. tion and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information for a product that is still in development Do not finalize a design with this information Information provided in this preliminary document may be incomplete as denoted by TBD or may change Revised information will be published in a later release of this document and when the product is made available Verify with your local sales office that you have the latest datasheet before finalizing a design The Intel Server Board S3420GP may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of th
143. tiple RAID levels to be combined on a single set of hard drives such as RAID 0 and RAID 1 on two disks Other RAID features include hot spare support SMART alerting and RAID 0 autos replace Software components include an Option ROM for pre boot configuration and boot functionality a Microsoft Windows compatible driver and a user interface to configure and manage the RAID capability of the Intel 3420 Chipset 3 4 3 USB 2 0 Support On the Intel 3420 Chipset the USB controller functionality is provided by the dual EHCI controllers with an interface for up to ten USB 2 0 ports All ports are high speed full speed and low speed capable Four external connectors are located on the back edge of the server board Two internal 2x5 header J1E2 and J1D1 are provided each supporting two optional USB 2 0 ports One port on internal vertical connector to support NIC One port on 1x4pin J1J2 on board header to support floppy 3 4 3 1 Native USB Support During the power on self test POST the BIOS initializes and configures the USB subsystem The BIOS is capable of initializing and using the following types of USB devices USB Specification compliant keyboards USB Specification compliant mouse USB Specification compliant storage devices that utilize bulk only transport mechanism USB devices are scanned to determine if they are required for booting 22 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S
144. tor Slot 3 E Pee 3 Intel 3420 Slot1 E Chipset TIT x BMC Boot P Flash SERIAL 2 PORT 80 el a B 9 VIDEO SERIAL 1 Notes 1 Video integrated into BMC User Bay USB headers Floppy Header FP headers Figure 11 Intel Server Board S3420GP Functional Block Diagram From S3420GPLC lt TBD gt Figure 12 Intel Server Board S3420GP Functional Block Diagram From S3420GPV 3 1 Processor Sub System The Intel Server Board S3420GP supports the following processor Intel Xeon 3400 Processor series The Intel Xeon 3400 Series processors processors are made up of multi core processors based on the 45 nm process technology 3 1 1 Intel Xeon 3400 Processor The Intel Xeon 3400 Series processors highly integrated solution variant is composed of four Nehalem based processor cores FC LGA 1156 socket package with 2 5 GT s Up to 95 W Thermal Design Power TDP processors with higher TDP are not supported 14 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Functional Architecture The server board does not support previous generations of the Intel Xeon processors 3 1 2 Intel Turbo Boost Technology Intel Turbo Boost Technology is featured on certain processors in the Intel Xeon Processor 3400 Series Intel Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if
145. uct Regulatory Compliance ird db 10 1 1 Product Safety Compliance starts 10 1 2 Product EMC Compliance Class A Compliance 10 1 3 Certifications Registrations Declarations 00 0 0 eceeeeeeeeeeeeeeeeeeeneneeeeeeeeeees 10 1 4 Product Ecology Requirements dial 10 2 Product Regulatory Compliance Markings eeeeeeeeeeeeeeeeeeeeenntaeeeeeeeeeeeeeea 10 3 Electromagnetic Compatibility Notices 10 3 1 FCC Verification Statement USA mrrrunnnnnnnnvvrvnnnnrnvnnnnnnnnneeverevrvnnnnnnnvnvnverennnn 10 3 2 ICE S 003 Canada viniese 10 3 3 Europe GE Declaration of Conformity idet deeg ege EE 1034 VCC JE uoto Ee nts e o utto 10 35 BEM TalWan a A R e EES ee lade ides 10 36 RR E Korea us EIL EUER NN 10 3 7 CNCA GOG Ghinahuu iie a dati inns Appendix A Integration and Usage Tips u Appendix B Integrated BMC Sensor Tables seen Appendix C POST Code Diagnostic LED Decoder see Appendix D POST Code Errors essen nnne nennen nnne nnn nnne nnne nnns Appendix E Supported Intel Server Chassis I uu Glossary Tcr R f rence Documents u ii gege joe Table of Contents vii Revision 1 0 Intel order number E65697 003 List of Figures IntelP amp P Server Board S34
146. ue entering the BIOS Setup utility to the system These Valid values are 0 65535 Zero is the settings are in seconds default A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot Boot Option x Available boot Set system boot order by selecting the devices boot option for this position Hard Disk Order Set the order of the legacy devices in Visible when one or more this group hard disk drives are in the system CDROM Order Set the order of the legacy devices in Visible when one or more this group CD ROM drives are in the system Floppy Order Set the order of the legacy devices in Visible when one or more this group floppy drives are in the system Revision 1 0 59 Intel order number E65697 003 BIOS User Interface IntelPEP Server Board S3420GP TPS Help Text een Device Order opio j the order of the legacy devices in Visible when one or more of this group these devices are available in the system BEV Device Order Set the order of the legacy devices in Visible when one or more of this group these devices are available in the system Add New Boot Option Add a new EFI boot option to the boot This option is only visible if order an EFI bootable device is available to the system for example a USB drive Delete Boot Option Remove an EFI boot option from the If the EFI shell is deleted boot order you can restore it by setting CMOS defaults
147. unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled The Serial Ports screen allows the user to configure the Serial A COM 1 and Serial B COM2 ports To access this screen from the Main screen select Advanced Serial Port Revision 1 0 Intel order number E65697 003 47 BIOS User Interface Advanced IntelPEP Server Board S3420GP TPS Serial Port Configuration Serial A Enable Address IRQ Serial B Enable Address IRQ Enabled Disabled 3F8h 2F8h 3E8h 2E8h 3or4 Enabled Disabled 3F8h 2F8h 3E8h 2E8h 3or4 Figure 20 Setup Utility Serial Port Configuration Screen Display Table 16 Setup Utility Serial Ports Configuration Screen Fields Help Text Serial A Enabled Enable or Disable Serial port A Enable Disabled Address Select Serial port A base UO address Select Serial port A interrupt request IRQ line Serial B Enabled Enable or Disable Serial port B Enable Disabled Address 3F8h Select Serial port B base I O address 2F8h 3E8h 2E8h De Select Serial port B interrupt request IRQ 4 5 3 2 2 5 USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options To access this screen from the Main screen select Advanced gt USB Configuration 48 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS BIOS User Interface
148. upport for implementation of Intel Virtualization Technology with Directed UO Intel VT d Intel VT d Technology consists of technology components that support the virtualization of platforms based on Intel Architecture Processor Intel VT d Technology enables multiple operating systems and applications to run in dependent partitions A partition behaves like a virtual machine VM and provides isolation and protection across partitions Each partition is allocated its own subset of host physical memory The Intel Virtualization Technology is designed to support multiple software environments sharing the same hardware resources The Intel Virtualization Technology can be enabled or disabled in the BIOS setup The default behavior is disabled Note If the setup options are changed to enable or disable the Virtualization Technology setting in the processor the user must perform an AC power cycle for the changes to take effect Revision 1 0 29 Intel order number E65697 003 Platform Management IntelP P Server Board S3420GP TPS 4 Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines Pilot II The onboard platform management subsystem consists of communication buses sensors system BIOS and server management firmware The following diagram provides an overview of the Server Management Bus SMBUS architecture used on this server board NOT USED P3V3SB PSVSB
149. video mode is disabled by default In the single mode dual monitor video disabled the on board video controller is disabled when an add in video card is detected n single mode the onboard video controller is disabled when an add in video card is detected In dual mode the onboard video controller is enabled and is the primary video device The external video card is allocated resources and is considered the secondary video device When KVM is enabled in iBMC FW dual video is enabled Table 8 Dual Video Modes Revision 1 0 27 Intel order number E65697 003 Functional Architecture IntelP amp P Server Board S3420GP TPS Enabled Onboard video controller Onboard Video Disabled Warning System video is completely disabled if this option is disabled and an add in video adapter is not installed Enabled If enabled both the onboard video controller and Dual Monitor Video Disabled an add in video adapter are enabled for system video The onboard video controller becomes the primary video device 3 8 Network Interface Controller NIC The Intel Server Board S3420GPLX and S3420GPLC support two network interfaces One is provided from the onboard Intel 82574L GbE PCI Express network controller the other is the onboard Intel 82578 Gigabit Network controller The Intel Server Board S3420GPV only supports one network interface which is provided from the onboard Intel 82574L GbE PCI Express network controller
150. ws the user to view a list of devices available for booting and to select a boot device for immediately booting the system To access this screen from the Main screen select Boot Manager Main i Security Server Management Boot Options Boot Manager Internal EFI Shell Boot device 1 gt Boot Option x gt Figure 34 Setup Utility Boot Manager Screen Display Table 30 Setup Utility Boot Manager Screen Fields Setupitem HelpTex Internal EFI Shell Select this option to boot now Note This list is not the system boot option order Use the Boot Options menu to view and configure the system boot option order Boot Device x Select this option to boot now Note This list is not the system boot option order Use the Boot Options menu to view and configure the system boot option order 5 4 Loading BIOS Defaults Different mechanisms exist for resetting the system configuration to the default values When a request to reset the system configuration is detected the BIOS loads the default system configuration values during the next POST You can send the request to reset the system to the defaults in the following ways e Pressing F9 from within the BIOS Setup utility Revision 1 0 63 Intel order number E65697 003 BIOS User Interface IntelP amp P Server Board S3420GP TPS e Moving the clear system configuration jumper e PMI command set System Boot options command e nt15 AX DA209 e Choosing Load U
151. x C POST Code Diagnostic LED Decoder Appendix C POST Code Diagnostic LED Decoder During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process you can use the diagnostic LEDs to identify the last POST process executed Each POST code is represented by the eight amber diagnostic LEDs The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by diagnostic LEDs 4 5 6 and 7 The lower nibble bits are represented by diagnostics LEDs 0 1 2 and 3 If the bit is set in the upper and lower nibbles then the corresponding LED is lit If the bit is clear then the corresponding LED is off The diagnostic LED 7 is labeled as MSB and the diagnostic LED 0 is labeled as LSB Upper Nibble LEDs Lower Nibble LEDs ES AB CDEFGHIJ Figure 39 Diagnostic LED Placement Diagram In the following example the BIOS sends a value of ACh to the diagnostic LED decoder The LEDs are decoded as follows Table 67 POST Progress Code LED Example Upper Nibble LEDs Lower Nibble LEDs LEDs MSB LSB LED 7 LED 6 LED 5 LED 4 LED
152. ystem Control Interrupt SCI is masked The BIOS sets up the power button event to generate an SMI and checks the power button status bit in the ACPI hardware registers when an SMI occurs If the status bit is set the BIOS sets the ACPI power state of the machine in the chipset to the OFF state The Integrated BMC monitors 68 Revision 1 0 Intel order number E65697 003 IntelPEP Server Board S3420GP TPS Connector Header Locations and Pin outs power state signals from the chipset and de asserts PS PWR ON to the power supply As a safety mechanism if the BIOS fails to service the request the Integrated BMC automatically powers off the system in 4 to 5 seconds Power Button On to Off Operating system present If an ACPI operating system is running pressing the power button switch generates a request using SCI to the operating system to shut down the system The operating system retains control of the system and the operating system policy determines the sleep state into which the system transitions if any Otherwise the BIOS turns off the system 6 4 2 Reset Button The platform supports a front control panel reset button Pressing the reset button initiates a request forwarded by the Integrated BMC to the chipset The BIOS does not affect the behavior of the reset button 6 4 3 NMI Button The Intel S3420GP Server Board family BIOS does not support the NMI button 6 4 4 System Status Indicator LED The Intel Server Board S3420

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