Fujitsu CS81 User's Manual
Contents
1. Design Compiler Test Compiler and PrimeTime Chrysalis Design Verifyer and Cadence DP PACKAGE AVAILABILITY No of Pins Balls Pin Ball Pitch TAB BGA Cavity down 304 0 8 mm 352 0 8 mm 480 1 0 mm 560 1 0 mm 660 1 0 mm 720 1 0 mm EBGA Cavity down 576 1 27 mm 672 1 27 mm HQFP Cavity up 208 0 50 mm 240 0 50 mm 256 0 40 mm 304 0 50 mm TQFP Cavity up 100 0 50 mm 120 0 50 mm LQFP Cavity up 144 0 50 mm 176 0 50 mm 208 0 50 mm FBGA Cavity up 112 0 80 mm 144 0 80 mm 168 0 80 mm 176 0 80 mm 192 0 80 mm 224 0 80 mm 240 0 50 mm 272 0 80 mm 288 0 75 mm 304 0 50 mm 320 0 80 mm 368 0 50 mm FC BGA Cavity down 1 089 1 27 mm 1 225 1 27 mm 1 369 1 27 mm 1 681 1 00 mm 1 849 1 00 mm 2 116 1 00 mm 21 mm 23 mm 31 mm 35 mm 40 mm 40 mm 40 mm 45 mm 28 mm 32 mm 28 mm 40 mm 14 mm 20 mm 20 mm 24 mm 28 mm 10 mm 2 mm 2 mm 2 mm 4mm 6mm 0 mm 8 mm 8 mm 2 mm 8 mm 4mm 4 4 4 4 4 4 4 4 4 42 4 mm 45 0 mm 47 5 mm 42 5 mm 45 0 mm 47 5 mm D G GMOS Technology Fujitsu Microelectronics Inc FUJITSU MICROELECTRONICS AMERICA INC Corporate Headquarters ON 1999 Fujitsu Microelectronics Inc 1250 East Arques Avenue Sunnyvale California 94088 3470 All company and product names are trademarks or Tel 800 866 8608 Fax 408 737 5999 registered trademarks of their respective owners E mail inquiry fma fujitsu com Internet http www fma f2. bobi oeries olandard Gel 0 18um CMOS Technology e 0 13 um effective channel length e 3 to 5 layers of metal interconnects e Very high density 110K raw gates mm e Up to 28 million gates e Core power supply voltage 1 8V to 1 1V e 5 nW gate MHz power dissipation at 1 1V e 11 ps gate delay at 1 8V and 1 fan out e Junction temperature range 40 to 125 C e 1 Os 3 3V 2 5V 1 8V 5V tolerant e High density diffused RAMs and ROMs e High speed mixed signal macros e Analog PLLs Wide selection of advanced packaging options e Proven design methodology and tool support Two cell libraries high performance and high density Fujitsu s CS81 a 0 18 um 0 13 4m Leff standard cell product is based on Fujitsu s state of the art CMOS process technology a deep sub micron process designed for today s high density and low power SOC products The cell library which is optimized for synthesis based designs has accurate timing and power characterized data cell areas and statistical wire load models The CS81 standard cell library contains both high perfor mance and high density cells giving designers the option of combining both types of standard cell blocks on the same chip The CS81 library supports popular third party tools and data exchange file standards The CS81 chip cores can operate at 1 8V to 1 1V The I Os operating at 1 8V 2 5V 3 3V or 5V tolerance can conveniently interface with various types of devices In
3. dology is devised for low power and low skew The methodology identifies the best suited clock distribution strategy for a given design and predicts performance in advance Fujitsu supports co sim ulation emulation and high level floor planning to opti mize the power timing and size of the design This enables the designer to make effective architectural level decisions to achieve optimal design solutions Fuyjitsu s design methodology supports cycle based simula tors and formal verification as well as static timing analy sis and the more conventional VHDL and Verilog simula tors Fujitsu s design for test strategy includes boundary scan JTAG and full and partial scan as well as a built in self test for memory Applications CS81 offers high density standard cells for very low power applications Also provided in CS81 are high performance and area optimized memories mixed signal blocks ana log functions a rich set of IP Cores and Mega Macros and various I O interfaces The CS81 ASIC design kit combined with its supported EDA tool sets is poised for chip developments that require ease of tool use proven design flow and a quick time to market Mixed Signal Macros e A D Converters 8 bit 50 MS s high speed 3 3V 8 bit 25 MS s high speed 3 3V 8 bit 1 MS s 3 3V e D A Converters 10 bit 30 MS s 3 3V 8 bit 50 MS s 3 3V 8 bit 1 MS s 3 3V Multiplier Compiler e Multiplicand m 4 lt m lt 32 e Mul
4. terface options include low swing high speed I Os and high speed bus interface I Os Both inline and staggered I O pad configurations are available Inline pads are available in both 70m and 44um pad pitch The 70um pads are wire bonded whereas the 44m pads are used with TAB The 66m wire bond stagger pads can be used for optimizing the die area of pad limited designs mM i svcmos 1 8v PLL Monas paat 1 8V Device gt cmos Clock Input T LVTTL Interface 3 3V Device J Pe CO FUJITSU CS81 1 0 Interface Capabilities P CML lt gt FS LVDS Devices 2 5v Device 2 5V CMOS P cS81 SSTL z si HSTL Analog 1 BV Interface ADC DAC Wy PCI AGP USB Y y y PCI Bus AGP USB Devices In addition to the traditional QFP packages the CS81 family is available in TAB EBGA FBGA and Flip chip BGA packages CS81 offers a rich set of ADCs and DACs PLLs high speed RAMs and ROMs as well as a variety of other embedded functions The following blocks will be avail able in the near future e Special high speed I Os T LVTTL P CML LVDS SSTL and HSTL e Special purpose Interfaces PCI AGP and USB Design Methodology Fujitsu design methodology ensures first time silicon suc cess by integrating proprietary point tools with popular sign off quality industry standard CAD tools such as Logic design rule checker e Delay calculator e Quasi 3 D parasitic extraction tool Fuyjitsu s clock driven design metho
5. tiplier n 4 lt n lt 32 even numbers only Memory Macros e SRAM Compiler single and dual port IRW 1R up to 72K bits per block e High speed SRAMs up to 144K bits e High density SRAMs 1 RW 512K 1 1M bits under development e Register files 2R 2W e ROM Compiler up to 512K bits per block Fujitsu Microelectronics Inc Phase Locked Loops e Analog up to 800 MHz I Os e 1 8V 2 5V and 3 3V CMOS 2 5V is under development e Slew rate controlled e Capable of driving large loads 2 4 8 and 12 mA sinking current e Transceivers under development P CML LVDS PCI SSTL and GTL e AGP 2X and 4X e 2 5 Gbps with clock recovery and Serdes under development To be developed 5V tolerant buffers SOC IP Cores e ARC 32 bit RISC e 10 100 MAC e 64 256 QAM e MPEG2 Decoder Demultiplexer e 8VSBTV Demodulator e AC3 Dolby Voice Decoder e JPEG Encoder and Decoder e PCI 33 66 MHz 32 64 bit cores e USB Host Controller Device IC IDE ATA3 Host Controller e Smart Card I F e IRDA I R Interface e To be developed ARM 7TDMI Hard Macro Oak DSP Hard Macro More IPs are being added ASIC Design Kit and EDA Support Verilog Logic Simulators from Cadence Synopsys and Mentor VHDL VITAL Logic Simulators from Synopsys Cadence and Mentor Synthesis DFT and STA tools from Synopsys Other EDA Tools Verilog XL NC Verilog VCS Model sim Verilog VSS Model sim VHDL V System Leapfrog
6. ujitsu com Printed in the U S A ASIC FS 20820 10 99
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