Dataram DTM68102A memory module
Contents
1. CCELI RUN Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 4 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM PIN DESCRIPTION Name Function 7 0 Data Check Bits DQ 63 0 Data Bits DQS 17 0 t DQS 17 0 c Differential Data Strobes CK t 1 0 CK c 1 0 Differential Clock Inputs CKE 1 0 Clock Enables CAS_n A15 Multiplexed Column Address Strobe or Address 15 RAS n A16 Multiplexed Row Address Strobe or Address 16 CS 3 0 n Chip Selects ACT n Activate Command Input WE n A14 Multiplexed Write Enable or Address 14 Address Inputs BA 1 0 Bank Address select Inputs BG 1 0 Bank Group select Inputs ODTT 1 0 On Die Termination Inputs SA 2 0 SPD Address SCL SPD Clock Input SDA SPD Data Input Output EVENT n Temperature Sensing RESET n Reset for register and DRAMs PARITY Parity bit input for Addr Ctrl ALERT n CRC Error Flag or CMD Addr Parity Flag Output A12 BC n Combination Input Address12 Burst Chop A10 AP Combination Input Addr10 Auto precharge 12V Optional Power Supply Vpp Charge Pump Power Vss Ground VppsPp SPD EEPROM Power VREFCA Reference Voltage for CA Vir Termination Voltage NC No Connection RFU Reserved for Future Use Not used C Document 06330 Revision A 07 May 14 Dataram Corporat2. 3 4 7 10 CL 9 cL Es 5 EM zs 1 6 Reserved ns CWL 9 Optional Optional CL 10 12 tCK ave Reserved 1 5 1 6 ns 1 2 3 7 ave 1 25 lt 1 5 CWL 9 11 CL 11 CL 13 Reserved ns 12 3 4 6 tCKuvo Optional 12 14 1 25 lt 1 5 1 25 lt 1 5 ns 1 2 3 6 tCK ave 1 071 lt 1 25 CWL CL 13 CL 15 58 Reserved ns 1 2 3 4 6 10 12 tCK ave Optional 14 CL 16 1 071 lt 1 25 1 071 lt 1 25 ns 1 2 3 6 CL 14 CL TBD tCK AvG Reserved Reserved ns 1 2 3 4 Pn CL 15 CL TBD tCK ave 0 938 lt 1 071 Reserved ns 1 2 3 4 16 CL TBD tCK ave 0 938 lt 1 071 0 938 lt 1 071 ns 1 2 3 Supported CL Settings Me E 10 12 14 16 nCK 9 10 Supported CL Settings with read DBI TBD TBD nCK Supported CWL Settings 9 10 11 12 14 9 10 11 12 14 nCK Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 2 EM 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM Speed Bin Table Notes Absolute Specification VDDQ VDD 1 20V 0 06 V VPP 2 5V 0 25 0 125 V The values defined with above mentioned table are DLL ON case DDR4 1600 1866 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled 1 9 The CL setting and CWL setting result in tCK avg MIN and tCK avg MAX requirements When making a selection of tCK avg both need to be fulfilled Requirements from CL setting as well as requirements from
3. 600K devices supporting down binning to 1333MT s should program 13 5ns SPD bytes for tAAmin Byte 24 tRCDmin Byte 25 and tRPmin Byte 26 DDR4 1866M devices supporting down binning to 1333MT s or DDR4 1600K should program 13 5ns in SPD bytes for tAAmin Byte 24 tRCDmin Byte 25 and tRPmin Byte 26 DDR4 2133P devices supporting down binning to 1333MT s or DDR4 1600K DDR4 1866M should program 13 5ns in SPD bytes for tAAmin Byte 24 tRCDmin Byte 25 and tRPmin Byte 26 tRCmin Byte 27 29 also should be programmed accordingly For example 48 5ns tRASmin tRPmin 35ns 13 5ns is set to supporting optional down binning CL 9 and CL 11 CL number in parentheses it means that these numbers are optional 10 DDR4 SDRAM supports CL 9 as long as a system meets tAA min Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 3 DTM68102A Eee 288 2Rx4 Registered ECC DDR4 DIMM Pin Configuration Vss Vss 12V NC DQ24 DQS14 t VnercA Vss 00814 c DQS12 t Veg DQS12 c DQ46 RAS n A16 Vpp CS0 n WE 14 DQS45 t CAS 15 00515 SAVE n NC DQS17 t DQS17 c DQS10 t DQS10 c 52 0 Vss DQ36 DQS16 t DQS16 c DQ16 00513 t Vss DQS13 c DQS41 t 00511 c Vss DQ22
4. 77155311777 DTM68102A Mad WA Optimizing Value and Performance 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM Features 288 pin JEDEC compliant DIMM 133 35 mm wide by 31 25 mm high Operating Voltage VDD VDDQ 1 2V 1 14V to 1 26V VPP 2 5V 2 375V to 2 75V VDDSPD 2 25V to 2 75V Type 1 2 V signaling On board temperature sensor with integrated Serial Presence Detect SPD EEPROM Data Transfer Rate 17 0 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 9 10 11 12 13 14 15 and 16 Bi directional Differential Data Strobe signals Per DRAM Addressability is supported Write CRC is supported at all speed grades DBI Data Bus Inversion is supported x8 only CA parity Command Address Parity mode is supported Supports ECC error correction and detection 16 internal banks SDRAM Addressing Row Col BG BA 16 10 2 2 Fully RoHS Compliant Identification DTM68102A 2Gx72 16 2Rx4 PC4 2133P RA0 10 Performance range Clock Module Speed CL trep trp 1067 MHz PC4 2133 16 16 16 1067MHz PC4 2133 15 15 15 933 Hz PC4 1866 14 14 14 933 Hz PC4 1866 13 13 13 800 Hz PC4 1600 12 12 12 800 Hz PC4 1600 11 11 11 667 MHz PC4 1600 10 10 10 667 MHz PC4 1600 9 9 9 Descriptio
5. B gt ODT SDRAMs D 8 5 D 17 14 ODT1 ODT1A gt ODT SDRAMs D 22 19 D 31 27 D36 ODT18 gt ODT SDRAMs D 26 23 D 35 32 50 n CSOA_n gt CS SDRAMs 014 1 0 13 9 018 0 n CS SDRAMs D 8 5 D 17 14 CS1 n CS1A n CS n SDRAMs 0122 19 D 31 27 036 CS1B_n gt CS n SDRAMs D 26 23 D 35 32 YO t CK t SDRAMs 08 5 D 26 23 Y1 t CK t SDRAMs D 4 1 09 D 22 19 D27 Y2_t gt CK t SDRAMs D 17 14 D 35 32 Y3 t CK t SDRAMs D 13 10 D18 D 31 28 036 CK0 c YO c gt CK c SDRAMs D 8 5 D 26 23 1 Y1 c gt CK c SDRAMs D 4 1 09 22 19 027 Y2 gt SDRAMs D 17 14 D 35 32 CK1 c c CK c SDRAMs D 13 10 D18 0131 28 D36 RESET n QRESET gt RESET n All SDRAMs ALERT n ERROR n lt ALERT n All SDRAMs Notes 1 t cterminated with 1200 5 resistor 2 t CK1 cterminated with 1200 5 resistor but not used 3 Unless otherwise noted resistors 220 5 4 Register input CS1 n is tied to VDD Register inputs ODT1 and CKE1 are tied to VSS Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 9 771553117777 DTM68102A MM 288 Pin 2Rx4 Registered DIMM Aud Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram
6. CWL setting tCK avg MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK avg value 1 5 1 25 1 071 0 938 or 0 833 ns when calculating CL nCK tAA ns tCK avg ns rounding up to the next Supported CL where tAA 12 5ns and tCK avg 1 3 ns should only be used for CL 10 calculation tCK avg MAX limits Calculate tCK avg tAA MAX CL SELECTED and round the resulting tCK avg down to the next valid speed bin i e 1 5ns or 1 25ns or 1 071 ns or 0 938 ns or 0 833 ns This result is tCK avg MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value Optional settings allow certain devices in the industry to support this setting however it is not a mandatory feature Refer to supplier s data sheet and or the DIMM SPD information if and how this setting is supported Any DDR4 2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization DDR4 1600 AC timing apply if DRAM operates at lower than 1600 MT s data rate For devices supporting optional down binning to CL 9 CL 11 and CL 13 tAA tRCD tRPmin must be 13 5ns or lower SPD settings must be programmed to match For example DDR4 1
7. com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 10
8. gram 4 TEN pin of SDRAMs is tied to VSS CCP CC S 2 c I2 KP 0H I _ Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 8 DTM68102A 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM BG 1 0 BG 1 0 A gt BG 1 0 SDRAMs 014 1 D 13 9 D 22 18 D 31 27 036 BG 1 0 B gt BG 1 0 SDRAMs 018 5 D 17 14 D 26 23 D 35 32 BA 1 0 BA 1 0 A gt BA 1 0 SDRAMs D 4 1 D 13 9 D 22 18 D 31 27 036 R 1 0 8 gt BA 1 0 SDRAMs 0 8 5 D 17 14 D 26 23 D 35 32 A 17 0 A 17 0 A gt A 17 0 SDRAMs D 4 1 D 13 9 D 22 18 D 31 27 D36 e A 17 0 B gt A 17 0 SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 ACT n gt ACT n SDRAMs D 4 1 D 13 9 D 22 18 D 31 27 036 g gt n SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 C 2 0 C 2 0 A gt C 2 0 SDRAMs D 4 1 D 13 9 D 22 18 D 31 27 036 C 2 0 B gt C 2 0 SDRAMs D 8 5 D 17 14 D 26 23 35 32 PARITY PARA gt PAR SDRAMs D 4 1 D 13 9 D 22 18 D 31 27 036 S PARB gt PAR SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 CKEO gt CKE SDRAMs D 4 1 D 13 9 D18 t CKEOB gt CKE SDRAMs D E 5 0117 14 CKE1 gt SDRAMs D 22 19 D 31 27 036 CKE1B gt CKE SDRAMs D 26 23 D 35 32 ODTO e gt ODT SDRAMs 014 1 D 13 9 018 r ODTO
9. ion 2014 Page 5 EM 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM Comforms to MO 309C 133 35 5 251 16 65 _ 5 66 1 25 1 231 3 d 3 1 7 5 301 i C 15 5 __ a La C 06 C F DDIDIDIDIDIDIDIDUDIDIDUDD c 5 15 Side View gt 3 98mm max 1 4 1mm max Notes 1 Tolerances on all dimensions except where otherwise indicated are 13 Reference JEDEC standard MO 309C 2 All dimensions are expressed millimeters inches Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 6 DTM68102A 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM Functional Diagram VSS 4 55 Document 06330 Revision 07 May 14 Dataram Corporation 2014 Page 7 Gye DTM68102A 16GB 288 Pin 2Rx4 Registered DDR4 DIMM Optimizing Value and Performance VpDsPD Serial PD Vp Y C EVENT_n EVENT n Vpp D1 D36 SAD SA1 SA2 V j SAO SA1 SA2 TT D1 D36 Serial PD with Thermal sensor VREFCA D1 D36 Vss D1 D36 Notes 1 Unless otherwise noted resistor values are 150 5 2 See the Net Structure diagrams for all resistors associated with the command address and control bus 3 ZQ resistors are 2400 1 For all other resistor values refer to the appropriate wiring dia
10. n DTM68102A is a registered 26 72 memory module which conforms to JEDEC s DDR4 2133 PC4 2133 standard assembly is Dual Rank Each rank is comprised of eighteen Samsung 1Gbx4 DDR4 2133 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Document 06330 Revision A 07 May 14 Dataram Corporation 2014 Page 1 DR Optimizing Value and Performance DTM68102A 16GB 288 Pin 2Rx4 Registered ECC DDR4 DIMM Speed Bin Table Speed Bin DDR4 2133P DDR4 2133R CL nRCD nRP 15 15 15 16 16 16 Unit NOTE Parameter Symbol min max min max 14 06 Internal read command to first data tAA 13 50 18 00 15 00 18 00 ns Internal read command to first data with read DBlenabled tAA DBI TBD TBD TBD TBD ns ACT to internal read or write delay 14 06 time tRCD 13 50 15 00 ns 14 06 PRE command period tRP 13 50 15 00 ns ACTto PRE command period tRAS 33 3X 33 ns tREFI tREFI 47 06 ACT to ACT or REF command period tRC 46 50 48 00 ns Normal Read DBI tCK 1 5 1 2
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