Dataram 2GB DDR3-1333
Contents
1. Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 VRerpal31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181A1 211 Vss CB 7 0 Data Check Bits 2 Vss Di Vss 62 Von 92 Vss h po4 1152 DM3 182 Vo 212 DM5 DA 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 oa DQSSM23DQ5 153 TDQS12 183 Vos 213 TDQS14 DQSI8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQS3 64 CK1 oa DQS5 124 Vss 154 Vss 184 CRO 214 Vss DM 8 0 Data Mash 5 Vss I85Vss 65 Von 95 Vss 125DMO 155DQ30 185 CKO 215DQ46 TDQS 17 9 Termination strobes 6 DQS0 36 DQ26 66 Voo 96 DQ42 126 TDQS9 156 DQ31 186 Vo 216DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 7 Dosen 37 DQ27 67 Vrerca 197 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 Parin 198 Vss 128DQ6 158 CB4 188 A0 218DQ52 CAS Column Address Strobe 9 DQ2 39CB0 69 VDD 99 DQ48 j129DQ7 159 CB5 189 Vo 219DQ53 RAS Row Address Strobe 10DQ3 40 CB1 70A10 AP Woo DQ49 130 Vss 160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 11Vss Wi Vss 71 BAO 101Vss 131DQ12 11461 DM8 191 Voo 221 DM6 AVE Write Enable 12DQ8 42 DQS8 72 Voo 102 DQS6I132DQ13 1162 TDQS17 192 RAS 222 TDQS15 A 15 0 Address Inputs 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 223 Vss BA 2 0 Bank Addresses 14Vss 44 Vss 74 CAS 104 Ves H34DM1 164 CB6 194 Vop 224DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Voo 105 DQ52. 0x00 25 eo Refresh Recovery Delay Time tRFCmin Most Significant 160 Ons 0x05 26 Minimum Internal Write to Read Command Delay Time tWTRmin 7 5ns 0x3C 27 Minimum Internal Read to Precharge Command Delay Time 7 5ns 0x3C tRTPmin Upper Nibble for tFAW 28 Bit 3 Bit 0 tFAW Most Significant Nibble 0 0x00 Bit 7 Bit 4 Reserved 0 29 Minimum Four Activate Window Delay Time tFAWmin Least 30 0ns OxFO Significant Byte SDRAM Optional Features Bit 0 RZQ 6 X 30 Bit 1 RZQ 7 X 0x83 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support a gy F Cl lee Ec eres Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 9 Ty DTM64360B 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Oper Wue aed Pesta SDRAM Drivers Supported Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR X 31 On die Thermal Sensor ODTS Readout 0x05 Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor 32 Bit 6 Bit 0 Thermal Sensor Accuracy 0 0x80 Bit 7 Thermal Sensor With TS SDRAM Device Type Bit 6 Bit 0 Non Standard Device Description 0 33 Bit 7 SDRAM Device Type Std Mono 0x00 34 59 Reserved UNUSED 0x00 Module Nominal Height 60 Bit 4 Bit 0 Module Nominal Height max inmm 29 lt h lt
3. No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 13
4. 136 Module Part Number R 0x52 137 Module Part Number A 0x41 138 Module Part Number M Ox4D 139 Module Part Number 0x20 140 Module Part Number 6 0x36 141 Module Part Number 4 0x34 142 Module Part Number 3 0x33 Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 11 DTM64360B UNSER 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 143 Module Part Number 6 0x36 144 Module Part Number 0 0x30 145 Module Part Number 0x20 146 147 Module Revision Code 0x20 148 DRAM Manufacturer ID Code Least Significant Byte UNUSED 0x00 149 DRAM Manufacturer ID Code Most Significant Byte UNUSED 0x00 150 175 Manufacturer s Specific Data UNUSED 0x00 176 255 Open for customer use UNUSED 0x00 Bytes 122 125 change per DIMM A a EE ee S S l l ES S Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 12 DP DATARAM DTM64360B eu 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM DD DATARAM Ween DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram
5. avg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period typ minimum of tens or teL ns Address and Command Hold Time after Clock Dn 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time turD 4 tck DQ to DQS Hold Lou 0 38 tor avg Active to Precharge Time tras 36 9 tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trop 13 125 ns Average Periodic Refresh Interval 0 C lt Tcase lt 85 C REFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C Ion 3 9 us Auto Refresh Row Cycle Time trFc 160 ns Row Precharge Time trp 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay tRRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay tRTP Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twpst 0 3 tck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min The maximum postamble is bound by tHZDQS max Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Pag
6. 0 135 TDQS10 165 CB7 1950DT0 225DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17Vss 47 Vss 77 0pT1 Wo ve 137DQ14 167 NC TEST 197 Ven 227DQ60 SDA SPD Data Input Output 18 DQ10 48 ven 78 Voo 108 DQ56 138DQ15 1168 RESET 198 S3 NC 228DQ61 EVENT Temperature Sensing 19DQ11 49 Vrr 79 82 MG 109 DQ57 139 Vss 169 CKE1 1199 Vss 229 Vss IRESET Reset for register and DRAMs 20Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Voo 200DQ36 230 DM7 PAR_IN Parity bit for Addr Ctri 21 DQ16 51 Vos 81 DQ32 111 DQS7I141DQ21 1171 A15 201 DQ37 231 TDQS16 ERR OUT Error bit for Parity Error 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172A14 202 Vss 232 Vss A12 BC Combination input Addr12 Burst Chop 23Vss 53 ERR_Our B ss 113Vss 143DM2 173 Voo 203 DM4 233DQ62 A10 AP Combination input Addr10 Auto precharge 24 IDQS2I54 Vos 84 DQS4 114 DQ58 144 TDQS11 174 A12 BC 204 TDQS13 234DQ63 Vss Ground 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 AQ 205 Vss 235 Vss Von Power 26Vss 56 A7 86 Vss 116Vss 146DQ22 1176Vop 206 DQ38 236 Vposro Vonsep SPD EEPROM Power 27 DQ18 57 Vos 87 DQ34 117SA0 147DQ23 177 A8 207 DQ39 237 SA1 VRErDa Reference Voltage for DQ s 28 DQ19 58 A5 88 DQ35 118SCL 148 Vss 178 A6 1208 Vss 238 SDA VREFCA Reference Voltage for CA 29Vss 59A4 89 Vss 119SA2 149DQ28 1179Vop 209 DO44 239 Vss Vo Termination Voltage 30 DQ24 60 Vos 90 DQ40 120 ven 150DQ29 1803 2
7. 10DQ45 240 Vrr NC No Connection Not used Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 1 D DATARAM DTM64360B Se 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Front view le 133 35 gt 5 250 9 50 0 374 30 00 1 181 UC 17 30 0 681 0 197 0 008 5 175 EN 47 00 gt La 71 00 gt 0 204 1 850 2 795 123 00 4 843 Back view Side view 3 94 Max 0 155 Max 4 00 Min 0 157 Min 1 27 2 10 gt 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches EECHER Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 2 Z DATARAM DTM64360B 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Value aed Fraftsemanuz Opener RSO DQSRO O J DQSRO DMRO TDQSR9 Oo 7 DOA SNN o o ZG Soo OO Q a OO EE SF DQRI7 0 VO 7 0 RANK 0 DQR 31 24 O DQSR8 DQSR8 O DMR8O _ TDQSR170 J CBRI7 0 DQSR4 O DQSR4 DMR4 TDQSR13 O RANK 0 TDQS ICS IDQS DQS DQR 39 32 O 017 0 TDQSR15O DQR 55 48 TDQSR16O DQR 63 56 TO SDRAMS VDD Von All All 36 OHMS 100 nF All 36 OHMS 100 nF 22 OHMS All 15 OHMS en IL men LCLKO EN RCLKO DQ 63 0 O VVV O DQRI63 0 EM LCLKO R
8. 30 OxOF Bit Bit5 Reserved 0 Module Maximum Thickness 61 Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt th lt 2 0x11 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 Reference Raw Card Used 62 Bit 4 Bit 0 Reference Raw Card RICA 0x00 Bit 6 Bit 5 Reference Raw Card Revision Rev 0 Bit 7 Reserved 0 Registered DIMM Module Attributes 63 Bit 1 Bit 0 of Registers used on RDIMM 1 Register 0x05 Bit 3 Bit 2 of Rows of DRAMs on RDIMM 1 Row Bit 7 Bit 4 Reserved 0 RDIMM Thermal Heat Spreader Solution 64 Bit 6 Bit 0 Heat Spreader Thermal Characteristics 0 0x00 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte Optional UNUSED 0x00 66 Register Manufacturer ID Code Most Significant Byte Optional UNUSED 0x00 67 Register Revision Number Optional y OxFF Register Type 68 Bit 2 0 Support Device SSTE32882 0x00 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 EH Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 10 Ty DTM64360B Opener Wue aed Pesta 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength Command Address 70 Bit 1 Bit 0 RC2 DA3 4 Value RESERVED 0x00 Bit 3
9. Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Light Bit 7 Bit 6 RC3 DBAO0 1 value Command Address B Outputs Light SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and Clock 71 Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light 0x00 Bit 3 Bit 2 RC4 DBA0 1 Control Signals B Outputs Light Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Light Bit 7 Bit 6 RC5 DBA0O 1 value YO YO and Y2 Y2 Clock Outputs Light 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED 0x00 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 0x00 75 SSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED 0x00 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 0x00 77 112 Module Specific Section UNUSED 0x00 113 Module Specific Section UNUSED 0x00 114 116 Module Specific Section UNUSED 0x00 117 Module Manufacturer ID Code Least Significant Byte 0x01 118 Module Manufacturer ID Code Most Significant Byte 0x91 119 Module Manufacturing Location UNUSED 0x00 120 121 Module Manufacturing Date UNUSED 0x00 122 125 Module Serial Number 0x23 126 Cyclical Redundancy Code CRC CRC 0x84 127 Cyclical Redundancy Code CRC CRC OXAD 128 131 Module Part Number 0x20 132 Module Part Number D 0x44 133 Module Part Number A 0x41 134 Module Part Number T 0x54 135 Module Part Number A 0x41
10. CLKO CB 7 0 O VA O CBRI7 0 BA 2 0 BAJ2 0JR A 15 0 t A 15 0 R FONS DASI8 0 O VVv O DQSR 8 0 IRAS L RASR ICAS JCASR cK1 O VVV O ER IDQSI8 0 O VVV O DQSRI8 0 4 WE 4 Il MER DM 8 0 O VVV O DMRI8 0 CKEO D L CKEOR G sn V DECOUPLING 9 OVO eee Be TDQS 17 9 TDQSR 17 9 opp 9 L_ ODTOR DDSPD Serial PD Ka VDD T All Devices PAR_IN ERR OUT VREF DQ All SDRAMs GLOBAL SDRAM CONNECTS CKO L R CLK O Vss All Devices All 47 OHMS OHMS Kg All SDRAMs re a BA 2 0 R ICKO L R CLK O TT All SDRAMs A 15 0 R IRESET IRASR SDRAMS ICASR IWER VTT EVENT All 240 OHMS TEMPERATURE MONITOR All 47 OHMS Za OM SCL SERIAL PD SDA com my ODTOR IRSO VTT Vss SAD SA1 SA2 Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 3 Gester DTM64360B DIN ENT E E TE Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TSTORAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TCASE 0 95 C Voltage on Vpp relative to Vss Vop 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta 0 to 70 C Voltage referenced to
11. DTM64360B 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Identification DTM64360B 256Mx72 2GB 1Rx8 PC3 10600R 9 11 A0 Performance range Clock Module Speed CL trep Je 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm DTM64360B is a registered 256Mx72 memory module high which conforms to JEDEC s DDR3 PC3 10600 Operating Voltage 1 5V 0 075 standard The assembly is a Single Rank The Rank is comprised of nine 256Mx8 DDR3 1333 Hynix SDRAMs VO Typer Son 5 One 2K bit EEPROM is used for Serial Presence On board I2C temperature sensor with integrated serial Detect and a combination register PLL with Address presence detect SPD EEPROM and Command Parity is also used Data Transfer Rate 10 6 Gigabytes sec Both output driver strength and input termination Data Bursts 8 and burst chop 4 mode impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology ZQ Calibration for Output Driver and On Die Termination ODT A thermal sensor accurately monitors the DIMM module Programmable ODT Dynamic ODT during Writes and can prevent exceeding the maximum operating t t f 95C Programmable CAS Latency 6 7 8 and 9 emperat re of 35C Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 15 10 3
12. Down Current Precharge Power lop2P Precharge power down current Fast exit 135 mA Down Current Precharge Quiet Precharge quiet standby current Standby Current lo02Q EH mA Precharge Standby lop2N Precharge standby current 225 mA Current Active Power Down L b Active power down current 135 mA Current Active Standby Active standby current Current Ipp3N 243 mA Operating Burst Burst write operating current Write Current Geh 165 IMA Operating Burst Burst read operating current Read Current oi B10 VE Burst Refresh ku Refresh current 1035 mA Current Self Refresh Luft Self refresh temperature current MAX Tc 85 C 108 mA Current Operating Bank i interleave Read ee All bank interleaved read current 1620 mA Current Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 6 Gye DTM64360B MN 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tecp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width tcL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe toH 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpascK 255 255 ps Write DQS High Level Width tbasH 0 45 0 55 tck
13. Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Vop 1 425 1 5 1 575 V UO Reference Voltage VREFDQ 0 49 Mon 0 50 Mon 0 51 Vop V 1 UO Reference Voltage VREFCA 0 49 Vpp 0 50 Vop 0 51 Vop V 1 Notes For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH Dc VREF 0 1 Vop V Logical Low Logic 0 Vuupe Vss Veer 0 1 V AC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 VIH AC VREF 0 175 V Logical Low Logic 0 Vit ac Vrer 0 175 V Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 4 DY PDATARAM DIN ENT E E TE DTM64360B 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High VIH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low Vu pr DC Vss AC Vss 0 4 0 200 V Differential Inp
14. e 7 Gy DTM64360B MN 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Hex Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0 Bit 3 Bit 0 SPD Bytes Used 176 0x92 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision Rev 1 1 0x11 2 Key Byte DRAM Device Type DDR3 SDRAM 0x0B Key Byte Module Type 3 Bit 3 Bit 0 Module Type RDIMM 0x01 Bit 7 Bit 4 Reserved 0 SDRAM Density and Banks 4 Bit 3 Bit O Total SDRAM capacity in megabits 2Gb 0x03 Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 SDRAM Addressing 5 Bit 2 Bit O Column Address Bits 10 0x19 Bit 5 Bit 3 Row Address Bits 15 Bit 7 6 Reserved 0 6 Reserved 0x00 Module Organization 7 Bit 2 Bit 0 SDRAM Device Width 8 Bits 0x01 Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 Module Memory Bus Width 8 Bit 2 Bit O Primary bus width in bits 64 Bits 0x0B Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 Fine Timebase FTB Dividend Divisor 9 Bit 3 Bit 0 Fine Timebase FTB Divisor 2 0x52 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 1 MTB 10 Medium Timebase MTB Dividend 0 125ns 0x01 8 MTB 11 Medium Timebase MTB Divisor 0 125ns Ge 12 SDRAM Minimum C
15. ut Cross Point Voltage relative to VDD 2 Vix da eee y Capacitance T 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cok 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control SO CKEO ODTO Ci 1 5 2 5 pF DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 1 5 2 5 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current lit 18 18 yA 1 2 Any input 0 V lt VIN lt VDD Output Leakage Current lot 10 10 yA 2 3 OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 5 DIPDATARAM DTM64360B Se 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition Max unit Value Operating One Bank Active kt Operating current One bank ACTIVATE to PRECHARGE 360 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Jon PRECHARGE 450 mA Precharge Current Precharge Power lop2P Precharge power down current Slow exit 108 T
16. ycle Time tCKmin 1 5ns 0x0C 13 Reserved UNUSED 0x00 14 CAS Latencies Supported Least Significant Byte 0x3C Bit 0 CL 4 Bit 1 CL 5 L as ie es Document 06943 Revision A 3 Oct 11 Dataram Corporation 2011 Page 8 Gy DTM64360B 2GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Opry Wate aed Pesta Bit 2 CL 6 X Bit 3 CL 7 X Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 0x00 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 13 125ns 0x69 17 Minimum Write Recovery Time tWRmin 15 0ns 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 19 Minimum Row Active to Row Active Delay Time tRRDmin 6 0ns 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble 1 0x11 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns 0x20 Significant Byte 23 Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns 0x89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Least 160 0ns 24 Significant Byte
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