Dataram DTM65527E memory module
Contents
1. nr Performance NUN Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 5 3 Gigabytes sec Operating Voltage VDD 1 8 V 0 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully RoHS Compliant DTM65527E 2 GB 240 Pin DDR2 Low Power FB DIMM Identification DTM65527E 256Mx72 2GB 1Rx4 PC2 5300F 555 11 C1 Performance range Clock Module Speed CL trcp trp 333MHz DDR2 667 5 5 5 266MHz DDR2 533 4 4 4 200MHz DDR2 400 3 3 3 Aree tie bel Description The DTM65527E is a single rank PC2 5300 Fully Buffered 256MX72 ECC DIMM that conforms to the JEDEC FB DIMM standard The single rank is comprised of eighteen 256Mx4 DDR2 Samsung DRAMs One IDT Rev L4 Low Power Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with thermal interface material TIM is attached to the front and back of the DIMM Pin Configurations Pin Names Front side Back side Pin Names Function 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 SN3 181 SN9 211 SS9 SCK SCK Syst2. M M ERR mc gl Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 17 yee DTM65527E _ ii_ lt lt s 2 GB 240 DDR2 Low Power FB DIMM ai ad 778 Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters Box 7528 Princeton 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 18
3. twr tex ns System Clock Cycle Time 3000 8000 ps Clock High Level Width tc 0 45 0 52 CLK Clock Low Level Width 0 45 0 52 CLK DQ output access time from CK amp CK tac 0 450 0 450 ns DQS Out edge to Clock Edge skew tpascK 0 400 0 400 ns DQS Out edge to Data out edge skew tposo 0 240 ns Data Out hold time from DOS tou tup tous ns 1 Data hold skew factor tous 0 340 ns 1 Clock Half Period tup min tcu ns 1 Input Setup Time fast slew rate tis 0 200 ns 2 3 5 6 Input Hold Time fast slew rate 0 275 ns 2 3 5 6 Input Pulse Width 0 6 6 Write DQS High Level Width tpasH 0 35 CLK Write DOS Low Level Width 0 35 CLK to First Rising edge to DQS In tpass 0 25 0 25 CLK Data In Setup Time to DQS In DQ amp DM tps 0 100 ns Data In Hold Time to DQS In DQ amp DM 0 175 ns NOTES 1 This calculation accounts for tposo max the pulse width distortion of on chip and jitter Data sampled at the rising edges of the clock A0 A13 BAO BA1 50 RAS CAS For command address input slew rate gt 1 0 V ns For command address input slew rate gt 0 5 V ns and 1 0 V ns CK CK slew rates are gt 1 0V ns These Parameters guarantee device timing but they are not necessarily tested on each device and they may be guaranteed by design or tester correlation Data latched at both rising and falling edg
4. _ l 2 GB 240 DDR2 Low Power FB DIMM NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliance test load Common mode measurements to be performed using a 101010 pattern 2 This is the ratio of the VTX DIFFp p of the second and following bits after a transition divided by the VTx DIFFp p of the first bit after a transition 3 De emphasis is disabled in the calibration state 4 Includes all sources of AC common mode noise 5 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition 6 Specified at the package pins into a voltage compliance test load Transmitters must meet both single ended and differential output E1 specifications 7 This specification considered with Vnx ipLE se pc implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered 8 The maximum value is specified to be at least VTX DIFFp p L 4 L VTX CM ACp p 2 9 This number does not include the effects of SSC or reference clock jitter 10 These timing specifications apply to resync mode only 11 Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential
5. RRX D RRX D RRX D Lane to lane PCB skew at RX LRX PCB SKEW 14 6 Ul Lane to Lane PCB skew at the Receiver that must be tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 ps Minimum data tracking 3dB bandwidth FTRK 16 0 2 a MHz Electrical idle entry detect time a 60 ns Electrical idle exit detect time TEI EXIT DETECT 30 ns Bit Error Ratio BER 18 10 Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 7 yee DTM65527E MM 2 GB 240 DDR2 Low Power FB DIMM NOTES FOR RECEIVER INPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin 2 Single ended voltages below that value that are simultaneously detected and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing EI levels with common mode levels during normal operation for the case with transmitter using small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels 3 Multiple lanes need to detect the El condition before the device can act upon the EI detection 4 Specified at the package pins into a timing and voltage compliance test setup 5 This specification considered with VTx IDLE SE Dc implies a maximum 15mV single ended DC offset between TX and RX pins during the elecrical idle condition This in turn a
6. 5 167 VSS 197 552 227 55 vss Ground 18 VSS 48 PN12 78 VSS 108 VDD 138 VSS 168 SN12 198 VSS 228 SCK RFU Reserved For Future Use 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 5 12 199 553 229 5 DNU Do Not Use 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 VSS 200 SS3 230 VSS M TEST Margin Test 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD SA 2 0 Serial Address EEPROM 22 PNO 52 PN6 82 PS4 112 VDD 142 SNO 172 ISN6 202 554 232 VDD 23 PNO 53 55 83 PS4 113 VDD 143 SNO 173 VSS 203 554 233 VDD 24 VSS 54 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7 85 VSS 115 VDD 145 SN1 175 ISN7 205 VSS 235 VDD 26 1 56 VSS 86 RFU1 116 VDD 146 SN1 176 VSS 206 RFU1 236 VDD 27 VSS 57 PN8 87 RFU1 117 VTT 147 VSS 177 SN8 207 RFU1 237 VTT 28 PN2 58 PN8 amp 88 VSS 118 SA2 148 SN2 178 5 8 208 VSS 238 VDDSPD 29 2 59 VSS 89 VSS 119 SDA 149 SN2 179 VSS 209 VSS 239 SAO 30 VSS 60 PN9 90 PS9 120 SCL 150 VSS 180 SN9 210 SS9 240 SA1 NOTE M TEST is not used Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 1 DTM65527E Pd W amp Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM Front view 133 35 i 5 250 9 50 i En 0 374 1 1 91 Dude 17 30 4 0 681 Y 0 197 2 50 Min 5 18 67 00 51 00 0 098 Min 0 204 2 638 2 008 123 00 4
7. 67 READ 3396 WRITE primary channel enabled secondary channel disabled high command 48V 1000 m address lines stable DDR2 SDRAM clock active TDP BW First DIMM LO State TDP Channel 45V 3600 Active IDD TDP 1 BW 2 4GB s 667 DIMM BW 1 6GB s 667 67 READ 33 WRITE primary channel enabled secondary channel enabled mA CKE high command and address lines stable DDR2 SDRAM 1 8 V 750 clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 15V 2700 Training E channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8 V 0 5 Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 10 DTM65527E Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM DRAM AC Characteristics AC operating conditions unless otherwise noted Parameter Symbol Min Unit Note Value Value Row Cycle Time tre 60 ns Auto Refresh Row Cycle Time treo 127 5 ns Row Active Time tras 45 70K ns Row Address to Column Address Delay trop 15 ns Row Active to row Active Delay 7 5 ns Column Address to Column Address Delay tccp 2 CLK Row Precharge time tgp 15 ns Write Recovery Time twR 15 ns Auto Precharge Write Recovery Precharge Time
8. 843 Back view Side view 8 000 Max 0 315 Max w heatsprdr 4 00 Min 0 157 Min 1 27 10 4 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches 2 Document 06028 Revision 29 Sep 09 Dataram Corporation 2010 DATARA d Optimizing Value and Performance 71 DTM65527E 2 GB 240 Pin DDR2 Low Power FB DIMM VSS 150 paso DQS9 10050 0 1 10959 0 1 08 DQS CS DM DQS CS DM 00 3 0 O 1 013 0 DQ 7 4 O V O 3 0 DQS1 DQS10 0 10951 0 1 100510 DQS 005 CS DM 1005 DQS CS DM DQ 11 8 O l O 3 0 DQ 15 12 1 013 0 0052 DQS11 0 4 10952 0 1 pas 0 4 DQS DQS CS DM DQS DQS CS DM 00 19 16 O 1 013 0 00 23 20 1 0 3 0 DQS3 DQS12 DQS3 DQS12 1005 005 CS DM 1005 005 CS DM DQ 27 24 O 1 0 3 0 DQ 31 28 O 1 013 0 DQS4 DQS13 Q DQS4 100513 DQS 08 CS DM DQS CS DM 00 35 32 1 013 0 00139 36 1 013 0 0055 00514 10985 0 1 109514 0 1 1005 005 CS DM 1005 DOS CS D
9. Additive Latencies Supported 0x40 Bit 3 Bit 0 Minimum AL clocks 0 Bit 7 Bit 4 AL Range clocks 4 SDRAM Minimum RAS to CAS Delay tRCD SDRAM Minimum Row Active to Row Active Delay tRRD SDRAM Minimum Row Precharge Time tRP 22 SDRAM Upper Nibbles for tRAS and tRC 0x00 Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 23 SDRAM Minimum Active to Precharge Time tRAS 4 SDRAM Minimum Active to Active Refresh Time tRC SDRAM Minimum Refresh Recovery Time Delay tRFC LSB 127 5ns SDRAM Minimum Refresh Recovery Time Delay tRFC 127 5ns 0x01 MSB SDRAM Minimum Internal Write to Read Command Delay 7 5ns Ox1E tWTR MN SDRAM Minimum Internal Read to Precharge Command Delay 7 5ns Ox1E tRTP Bit 0 BL 4 Bit 1 BL 8 Bit 6 Bit 2 TBD Bit 7 Burst Chop 0x07 Bit 0 150 ohms ODT Bit 1 75 ohms ODT Bit 2 50 ohms ODT Bit 6 Bit 3 TBD 0x01 Bit 0 Weak Driver Bit 7 Bit 1 TBD SDRAM Average Refresh Interval tREFI Double Refresh mode bit High 0xC2 Temperature self refresh rate support indication Bit 0 Bit Average Refresh Interval tREFI uS 7 8 Bit 5 Bit 4 TBD 0 Bit 6 High Temperature Self Refresh 1 Required Bit 7 Double Refresh Requirement 1 5 Tcasemax Delta Bit 3 Bit 0 DTARAW Delta Subfield B 0 4 C Bit 7 Bit 4 Tc
10. PTP Link Draft Spec rev 0 8 12 Pulse width measured at OV differential 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mv for that pin 14 Lane to Lane skew at the Transmitter pins for an end component 15 Lane to Lane skew at the Transmitter pins for an intermediate component assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT 16 This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization 17 Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 18 BER per differential lane For a complete definition of Bit Error Ratio refer to JEDEC s Compliance Methodology section Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 6 ye DTM65527E A Optimizing Value and Performance Differential Receiver Input Specification 2 GB 240 Pin DDR2 Low Power FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak input voltage VRX DIFFp p_L 1 170 1300 mV VRX DIFFp p 2 VRX D VRX D Maximum single ended vo
11. the average of the values measured at 100mV and at 400mvV for that pin 14 This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is significantly below the tracking capability of the receiver 16 This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 8 mmm DTM65527E Optimizing Value and Performance 2 GB 240 DDR2 Low Power FB DIMM Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timing PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs Assertion Duration 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters Parameter Symbol MIN MAX Units Notes CMD2DATA 0x40 Data Rate 667 tC2D AMB 16
12. 2 19 ns CMD2DATA 0x46 Data Rate 667 tC2D AMB 17 7 20 5 ns Resample Delay 6 tRESAMPLE 0 9 1 4 ns 1 Resync Delay 7 8 9 tRESYNC 2 3 2 ns 2 NOTES 1 tRESAMPLE is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resample mode measured from the center of the data eye 2 tRESYNC is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resync mode measured from the center of the data eye p HERR cn i Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 9 mmm DTM65527E Optimizing Value and Performance 2 GB 240 DDR2 Low Power FB DIMM AMB Power Specification 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Test Condition y Value Unit idle Single or last FBDIMM LO state idle 0 BW primary channel 1 5V 2300 Current IDD IDLE 0 secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8 V 550 Idle First FBDIMM LO state idle 0 BW primary and secondary 1 5V 3000 Current IDD IDLE 1 enabled high command and address lines mA stable DDR2 SDRAM clock active 1 8 V 550 TDP BW Single or Last DIMM LO State TDP Channel 45V 2700 Active IDD 0 BW 2 4GB s 667
13. DIMM Voltage Levels of this Assembly Bit 3 Bit 0 Power Supply 1 Bit 7 Bit 4 Power Supply 2 SDRAM Addressing 0x49 Bit 1 0 Number of Banks Bit 5 Bit 3 Column Address Bits Bit 7 Bit 5 Row Address Bits Module Physical Attributes 0x23 Bit 3 Bit 0 Module Thickness mm 7 lt lt 8 0 Bit 4 Bit 2 Module Height mm 30 lt x lt 35 Bit 7 6 Reserved 0 Module Type 0x07 Bit 3 Bit 0 Module Type FB DIMM Bit 7 Bit 4 Reserved Module Organization 0x08 Bit 3 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Fine Timebase Dividend Divisor 0x00 Bit 3 Bit 0 Fine Timebase FTB Dividend Bit 7 Bit 4 Fine Timebase FTB Divisor 0 25ns 0 25ns SDRAM Minimum Cycle Time 0x0 12 SDRAM Maximum Cycle Time tCKmax 13 SDRAM CAS Latencies Supported Bit 3 Bit 0 Minimum CL clocks Bit 7 Bit 4 CL Range clocks 15 SDRAM Write Recovery Times Supported Bit 3 Bit 0 Minimum WR clocks Bit 7 Bit 4 WR Range clocks SDRAM Write Recovery Time tWR 17 SDRAM Write Latencies Supported 0x42 Bit 3 Bit 0 Minimum WL clocks 2 Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 13 mmm DTM65527E Optimizing Value and Performance 2 GB _ 240 DDR2 Low Power FB DIMM Bit 7 Bit 4 WL Range clocks 4 18 SDRAM
14. M DQ 43 40 O 1 013 0 DQI47 44 1 013 0 DQS6 DQS15 DQS6 DQS15 DQS DQS CS DM DQS DQS CS DM DQ 51 48 O 1 0 3 0 DQ 55 52 O I O 3 0 DQS7 DQS16 DQS7 0 1 109516 0 DQS CS DM DQS DQS CS DM 00 59 56 O 4 1 0 3 0 DQ 63 60 1 0 3 0 DQS8 DQS17 DQS8 DQS17 DQS CS DM DQS DQS CS DM 3 0 O 1 0 3 0 7 4 O 1 013 0 PNO PN13 SNO SN13 VTT Terminators PNO PN13 SNO SN13 L PS0 PS9 SS0 SS9 T IPS0 PS9 SS0 SS9 veg 7 AMB DQ0 DQ63 IS0 gt CS CB0 CB7 A CKEO gt VDDSPD SPD AMB DQS0 DQS17 M ODT gt ODTO all SDRAMs DQS0 DQS17 B 0 2 all SDRAMs von SDRAMS ANB SCL 0 15 all SDRAMs SDA RAS all SDRAMs SA1 SA2 ICAS all SDRAMs VREF SDRAMS SAO AAA ME all SDRAMs CK amp CK all SDRAMs Use L l pu SPOLAME SCK amp SCK All address command control clock NNN Vr Notes Ser SERIAL PD 1 DQ to I O wiring may be changed within a nibble 2 There are two physical copies of each address command control 3 There are four physical copies of each clock SDA WP SAO SA1 SA2 Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 3 DTM65527E EygDATARAM 4 2 GB 240 DDR2 Low Power FB DIMM Optimizing Value and Performance Absolute Maximum Ratings Notes 1 Applies to SMB and SPD bus signals 2 Applie
15. Min VTX VTX D 2 Maximum single ended voltage in El condition DC VTX IDLE SE 5 6 2 50 mV Maximum single ended voltage in El condition DC only Mr 20 Maximum peak to peak differential voltage El condition VTX IDLE DIFFp p 6 __ 40 mV Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 Minimum TX eye width 3 2 and 4 Gb s TTX Eye MIN 1 9 10 0 7 en Ul Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 S 0 2 Ul Instantaneous pulse width TTX PULSE 12 0 85 Ul Differential TX output rise fall time TTX RISE TTX 30 90 ps Given by 2096 8096 voltage levels FALL 1 Mismatch between rise and fall times TTX RF MISMATCH 20 Differential return loss RLTX DIFF 8 Measured over 0 1 GHz to 2 4GHz Common mode return loss RLTX CM 6 dB Measured over 0 1 GHz to 2 4GHz Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX Match DC 4 RTX Match DC 24 RTX D RTX D RTX D RTX D Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps TTX DRIFT 240 s Maximum TX Drift resync mode RESYNC 17 p TTX DRIFT 120 s Maximum TX Drift resample mode only RESAMPLE 17 p Bit Error Ratio BER 18 1072 Document 06028 Revision 29 Sep 09 Dataram Corporation 2010 Page 5 yee DTM65527E
16. Pin DDR2 Low Power FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak output voltage for large voltage VTX DIFFp p L 1 900 1300 mV swing VTX DIFFp p 22 VTX D VTX D Differential peak to peak output voltage for regular voltage VTX DIFFp p_R 1 800 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for small voltage VTX DIFFp p_S 1 520 mV swing VTX DIFFp p 2 VTX D VTX D DC common code output voltage for large voltage swing VTX CM_L 1 Ze 375 mV Defined as VTX CM DC avg of VTX D VTX D 2 DC common mode output voltage for small voltage swing VTX CM S 1 135 280 mV Defined as VTX CM DC avg of VTX D VTX D 2 De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 3 4 dB de emphasis Ratio 1 2 3 De emphasized differential output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 7 emphasis AC peak to peak common mode output voltage for large VTX CM ACp p L 1 4 22 90 mV swing VTX CM AC VTX D VTX D 2 Min VTX VTX D 2 AC peak to peak common mode output voltage for regular VTX CM ACp p R 1 4 80 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX VTX D 2 AC peak to peak common mode output voltage for small VTX CM ACp p S 1 4 _ 70 swing VTX CM AC VTX D VTX D 2
17. asemax Subfield A 2 C SDRAM Case Temperature Rise from Ambient due to Activate Precharge minus 2 8 C offset temperature Bit 1 Bit 0 Reserved Bit 7 Bit 2 DTO 36 SDRAM Case Temperature Rise from Ambient due to 5 9 Ox3B Precharge Quiet Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 14 mmm DTM65527E Optimizing Value and Performance 2 GB _ 240 DDR2 Low Power FB DIMM eem TL 37 SDRAM Case Temperature Rise from Ambient due to Precharge Power Down DT2P SDRAM Case Temperature Rise from Ambient due to Active Standby DT3N C 39 SDRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Bit 0 DTARAW Mode Bit Subfield B 0 4 C 0 Bit 7 Bit 1 DT4R Subfield A 0 4 C 23 6 40 SDRAM Case Temperature Rise from Ambient due to 23 5 Ox2F Burst Refresh DT5B C 41 SDRAM Case Temperature Rise from Ambient due to Bank 29 Ox3A Interleave Reads with Auto Precharge DT7 OR Gono GR ODT conve forRankO and rank 1 Reads andwies 0x00 GRODTranODTZcommlrmad FBD ODT Definition for Rank 2 and 3 Bit 1 Bit 0 Rank 2 Data DRAM ODT Disabled Bit 3 Bit 2 Rank 2 Ecc DRAM ODT Disabled Bit 5 Bit 4 Rank 3 Data DRAM ODT Disabled Bit 7 Bit 6 Rank 3 Ecc DRAM ODT Disabled FBD ODT Definition for Rank 0 and 1 Bit 1 Bit 0 Rank 0 Data DRAM ODT 150 Ohms B
18. em Clock Input 2 VDD 32 62 VSS 92 VSS 122 VDD 152 SN3 182 VSS 212 VSS PN PN 13 0 Primary Northbound Data 3 VDD 33 VSS 63 PN10 93 PS5 123 VDD 153 VSS 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 4 VSS 34 PN4 64 PN10 94 PS5 124 VSS 154 SN4 184 SN10 214 555 SN SN 13 0 Secondary Northbound Data 5 VDD 35 4 65 VSS 95 VSS 125 VDD 155 SN4 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 556 SCL Serial Clock EEPROM 7 VDD 37 5 67 11 97 PS6 127 VDD 157 SN5 187 SN11 217 SS6 SDA Serial Data EEPROM 8 VSS 38 5 68 VSS 98 VSS 128 VSS 158 SN5 188 VSS 218 VSS VID 1 0 Voltage ID 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 Reset Signal 10 VCC 40 13 70 PSO 100 PS7 130 VCC 160 SN13 190 550 220 557 vec AMB Core Power and AMB Channel 11 VSS 41 PN13 71 PSO 101 VSS 131 VSS 161 SN13 191 SSO 221 VSS Interface Power 1 5 V 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 558 VDD DRAM Power and AMB DRAM 13 VCC 43 VSS 73 PS1 103 PS8 133 VCC 163 VSS 193 SS1 223 558 Power 1 8 V 14 VSS 44 RFU 74 51 104 VSS 134 VSS 164 RFU1 194 SS1 224 VSS VIT DRAM Address Command Clock 15 VTT 45 RFU 75 VSS 105 RFU2 135 VTT 165 RFU1 195 VSS 225 RFU2 Termination Power VDD 2 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 VSS 196 SS2 226 RFU2 VDDSPD SPD Power 17 RESET 47 VSS 77 52 107 55 137 M
19. es of Data Strobes DQS Document 06028 Revision 29 Sep 09 Dataram Corporation 2010 Page 11 DTM65527E Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max Parameter Symbol Unit Note Value Value DQ Input Pulse Width tpipw 0 35 CLK Read DQS Preamble Time tRPRE 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Setup Time twPRES 0 ns Write DQS Preamble Hold Time twPRE 0 35 CLK Write DQS Postamble Time twest 0 4 0 6 CLK Mode Register Set Delay 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command txsrp 200 CLK 7 8 Hus Average Periodic Refresh Interval 3 9 Hs 2 NOTES 1 For0C lt Tease lt 85 2 For 85 lt Tease 5 95 Document 06028 Revision 29 Sep 09 Dataram Corporation 2010 Page 12 DTM65527E Optimizing Value and Performance 2 GB _ 240 DDR2 Low Power FB DIMM SERIAL PRESENCE DETECT MATRIX Function Value Number of Serial PD Bytes Written SPD Device Size CRC Coverage 0x92 Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 Coverage Bytes 0 116 SPD Revision 0x11 Key Byte DRAM Device Type DDR2 0x09 FB
20. it 3 Bit 2 Rank 0 Ecc DRAM ODT Disabled Bit 5 Bit 4 Rank 1 Data DRAM ODT Disabled Bit 7 Bit 6 Rank 1 Ecc DRAM ODT Disabled UNUSED 81 Channel Protocols Supported Least Significant Byte 0x02 Bit 0 DDR2 Base Non ECC Protocol O0 Not Supported Bit 1 DDR2 Base ECC Protocol 1 Supported Bit 7 Bit 2 TBD 0 Channel Protocols Supported Most Significant Byte UNUSED Back to back Turnaround Cycles Bit 1 Bit 0 Rank Read to Read 0 add l clock Bit Bit 2 Write to Read 0 add l clock Bit 5 Bit 4 Read to Write 1 add l clock Bit 7 Bit 6 TBD 0 AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK AMB Read Access Time for DDR2 667 AMB LINKPARNXT 1 0 10 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK AMB Read Access Time for DDR2 533 AMB LINKPARNXT 1 0 01 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK p c il Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 15 DTM65527E Optimizing Value and Performance 2 GB _ 240 DDR2 Low Power FB DIMM 87 Thermal Resistance of AMB Package from Top Ca
21. llows a ground offset between adjacent FB DIMM of 26mV when worstcase termination resistance matching is considered 6 The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late 7 The relative amplitude ratio limit between adjacent symbols prevents excessive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude 8 This number does not include the effects of SSC or reference clock jitter 9 This number includes setup and hold of the RX sampling flop 10 Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 11 Allows for 15mV DC offset between transmit and receive devices 12 The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRX DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90mV and VRX CM ACp p 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to
22. ltage for El condition DC AC VRX IDLE SE 2 3 4 65 mV Maximum single ended voltage for El condition DC only 4 35 mV Single ended voltage w r t VSS on D D VRX SE 4 300 900 mV Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 Amplitude ratio between adjacent symbols VRX DIFF ADJ e 3 1100mV VRX DIFFp p lt 1300mV RATIO HI 4 7 Amplitude ratio between adjacent symbols VRX DIFF ADJ 4 VRX DIFFp p lt 1100 RATIO 4 7 Maximum inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 UI Maximum RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 m 0 3 Ul Gb s Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 UI Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 a Ul rur RX input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 5 ps evels Common mode of the input voltage VRX CM 1 11 120 400 mV Defined as VRX CM DC avg of VRX D VRX D 2 AC peak to peak common mode of input voltage VRX CM VRX CM ACp p 1 DP 270 mV AC Max VRX D VRX D 2 Min VRX D VRX D 2 Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 45 Differential return loss RLRX DIFF 9 dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLRX CM 6 dB Measured over 0 1 GHz to 2 4GHz RX termination resistance RRX 13 41 55 D D RX resistance difference RRX Match DC 4 RRX Match DC 24 RRX D
23. odule Module Manufacturers JEDEC TD Code 119 Module 1D Module Manufacturing Location 9 7120 21 Module 10 Module Manufacturing Location foo 12225 Module D Module Serial Number f foo 126 OyodicRedundanyCode CRC foa 27 Cyclical Redundancy Code CRO Moe 7128451 Module Par Number 192 ModdePatNumer d fou Document 06028 Revision A 29 Sep 09 Dataram Corporation 2010 Page 16 DTM65527E Optimizing Value and Performance 2 GB 240 Pin DDR2 Low Power FB DIMM 135 WoediePatNumer O O a o 136 Module Part Number R 0x amp 137 ModiePatNumber A o 139 Module Part Number 020 140 ModiePatNumber 6 0x86 ModiePatNumber oo o 5 o 142 ModiePatNumber 5 7196 48 ModiePatNumber O gt oa i44 ModiePatNumber oo 3 145 ModiePatNumber 146147 WodueRevisionCode UNUSED 0900 7148149 _ SDRAM Manufacturer s JEDEC ID Gode UNUSED 0x00 150 Manufacturers Spede Daa O O 151 Manufacturers 152 178 ManufacurersSpedlicData UNUSED 000 0 4 0x5 0 4 4 0 2 0 3 0x3 0x3 0x3 0x3 0 2 0 0 0 0 0 0 0 0 0 1 2 1 D 0 6 5 5 2 7 0 0 0 1 0 0 p
24. s to AMB CMOS signal RESET Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case 0 to 95 C 1 2 Temperature Storage Tstc 55 to 100 1 Operating humidity relative HoPR 10 to 90 1 Storage humidity without condensation Hsrc 5 to 95 1 Voltage on pin relative to Vss Vin Vout 0 3 to 1 75 V 1 Voltage on Vcc relative to Vss Vcc 0 3 to 1 75 V 1 Voltage on Vpp relative to Vss 0 5 to 2 3 V 1 Voltage on relative to Vss Vit 0 5 to 2 3 V 1 Power Dissipation Pp 21 1 NOTES 1 Exposure to absolute maximum rating conditions for extended period may affect reliability 2 For85 lt Tease 95 C tage 3 9 us max DC Operating Conditions 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage Voc 1 425 1 5 1 59 V DDR2 Supply Voltage 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x VDD 0 52 x VDD V EEPROM Supply Voltage SPD VppsPD 3 0 3 3 3 6 V Input High Voltage SPD 2 1 VppsPD V 1 Input Low Voltage SPD 1 0 V 1 Input High Voltage RESET BFUNC 1 0 V 2 Input Low Voltage RESET BFUNC Vito 0 5 V 2 Leakage Curent RESET BFUNC I 90 90 2 Leakage Curent Link IL 5 5 Document 06028 Revision 29 Sep 09 Dataram Corporation 2010 Page 4 mmm DTM65527E Optimizing Value and Performance Differential Transmitter Output Specification 2 GB 240
25. se to 21 2 Ambient Psi AMB C W 88 AMB Case Temperature Rise from Ambient due to AMB in 0x56 Idle 0 State DT AMB Idle 0 C AMB Case Temperature Rise from Ambient due to AMB in 107 0 6 Idle 1 State DT AMB ldle_1 C AMB Case Temperature Rise from Ambient due to AMB in 92 0x5C Idle 2 State DT AMB Idle 2 C 91 AMB Case Temperature Rise from Ambient due to AMB in 145 0x91 Active 1 State DT AMB Active 1 C AMB Case Temperature Rise from Ambient due to AMB in 118 0x76 Active_2 State DT AMB Active_2 C 93 AMB Case Temperature Rise from Ambient due to AMB in LOs UNUSED 0x00 State DT AMB LOs C 99 Rese SSCS 100 101 AMB Personality Bytes Pre initalizaton oo 102 AMBPeronallyByes Prein alzalon oez 108 AWB Personality Bytes Prednitaliza on oez 104 AMBPersonaityByesrPreini alza on foa 105 AMB Personality Bytes Pre ifalization fos 106 AMB Personality Bytes Pre nitaliza on foec 107 108 AME Personality Bytes Post inifalization oo 109 AWB Personality Byles Postinitalizaton for 110 AMB Personality Bytes Postinitializaton fom 111114 Personality Bytes Postinitialization oe 155 AVB Manufacturer s JEDEC ID Cod M6 AMB Manufacturers JEDECID Cod foes 7147 Module Module Manufacturers JEDEC TD Code 118 M
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