Dataram 2GB DDR2
Contents
1. PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CK1 CK1 CK2 CK2 CIN1 6 12 pF Input Capacitance Address 2 0 A 13 0 50 S1 RAS CAS CIN2 46 28 pF and Control WE CKEO CKE1 ODTO ODT1 Input Output Capacitance SOR DOSE 10050 CIO 5 7 pF DC Characteristics 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address IL 160 160 1 Input Leakage Current S 1 0 CKE 1 0 IL 80 80 1 ODT 1 0 Input Leakage Current CK 0 CK 0 IL 4 4 1 Input Leakage Current CK 1 0 CK 1 0 lL 6 6 1 Input Leakage Current DM IL 20 20 1 Output Leakage Current DQS DQ loz 20 20 2 Output Minimum Source DC Current lon 13 4 mA 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested a sample basis only 2 ODT are disabled and 0 V lt Vout lt 3 Von 1 7 V Vout 1420 mV Vpp lou must be less than 21 Ohms for values of Vout between Von and Vpp 280 mV 4 Vpp 1 7 V Vout 280 mV Vourt lo must be less than 21 Ohms for values of between 0 V and 280 mV m P O C YO 42 Document 06926 Revision A 18 DEC 07 Dataram Corporation o 20072. 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 Vrer 0 125 Vpp 0 300 V Logical Low Logic 0 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Logical High Logic 1 ViH AC Vrer 0 250 V Logical Low Logic 0 ViL AC E Vrer 0 250 V Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 4 DTM63367 2GB 256Mx64 240 Pin Unbuffered DDR2DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Svmbol Minimum Maximum Unit Note DC Input Signal Voltage ViN DC 0 300 Vpp 0 300 V 1 DC Differential Input Voltage 0 250 Vpp 0 600 V 2 AC Differential Input Voltage Vip AC 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vix AC 0 50 Vpp 0 175 0 50 Vpp 0 175 V 4 Notes 1 Vm po specifies the allowable DC excursion of each input of a differential pair 2 specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Vinac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 and is expected to track variations in Capacitance T4 25 C f 100 MHz
3. Features DTM63367 DA ARAM 2 GB 256Mx64 240 Pin Unbuffered DDR2 DIMM 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 8 V 0 1 Type SSTL_18 Data Transfer Rate 6 4 Gigabytes sec Data Bursts 4 or 8 bits Sequential or Interleaved ordering Programmable driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 4 or 5 Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration Identification DTM63367 256Mx64 Performance range Clock Module Speed CL tncp tnp 400 MHz PC2 6400 5 5 5 266 MHz PC2 4200 4 4 4 Description DTM63367 is Unbuffered 256 64 memory module which conforms to JEDEC s DDR2 PC2 6400 standard The assembly is comprised of two Ranks Each Rank is comprised of eight 128Mx8 DDR2 SDRAMs One 2K bit EEPROM is used for Serial Presence Detect Both output driver strength input termination impedance are programmable to maintain signal integrity on the signals Pin Description Front Side Back Side Name Function 1 VREF 31 019 6144 91 vss 121VSS 151 vss 181 VDD 211 DM5 CB 7 0 Data Check Bits 2 VSS 32 VSS 62 VDD 92 55 22 004 152 0028 182 212 DQ 63 0 Data Bits DQO 330024 63 Dass 23 095 153 0029 183 A1 213 VSS DQS 8 0 DQS 8
4. 48 Thermal Resistance of DRAM Package from Top Case to 0x74 Ambient Psi T A DRAM C Watt 9 DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree Bit If DRAM does not support high temperature self 1 refresh entry Bit 1 If 0 Do not need double refresh rate for the proper 1 operation DTO Bits 2 7 50 DRAM Case Temperature Rise from Ambient due to 0x32 Precharge Quiet Standby DT2N DT2Q Degree C DRAM Case Temperature Rise from Ambient due to 1 095 0x49 Precharge Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active 0x28 Standby DT3N Degree C 53 DRAM Case temperature Rise from Ambient due to Active INN 0x37 Power Down with Fast PDN Exit DT3Pfast Degree 54 DRAM Case temperature Rise from Ambient due to Active 1 325 0x35 Power Down with Slow PDN Exit DT3Pslow Degree 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Ox5E Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 19 5 0x27 Refresh DT5B Degree C Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 10 DTM63367 972172172111 2GB 256Mx64 240 Pin Unbuffered DDR2DIMM DRAM Case Temperature Rise from Ambient due to Bank 20 5 0x29 Interleave Re
5. 4 843 Back view Side view 4 00Max 7 pim Max 4 00 0 157 Min O NNNnnn Annn nnn nnnm HUHHH O i 1 27 1 10 alle 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches a a gt Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 2 DTM63367 972172117211 2 256 64 240 Pin Unbuffered DDR2DIMM STO S0 O DMRO O 22 pF DQSRO O 5 5 D DQS DOS DQR 7 0 O 1 0 7 0 E VO 7 0 DMR1 O DOSRT O C DQSR1 100 005 5 DM 00 DOS 5 DM DQR 15 8 VO 7 0 VO 7 0 DMR2 O DQSR2 O DQSR2 20 DOS CS DM DQS DOS CS DM DQR 23 16 l O 7 0 V O 7 0 DMR3 O DQSR3 DQSR3 20 DOS CS DM 20 DOS CS DM DQR 31 24 VO 7 0 VO 7 0 All 22 OHMS 00 63 0 O O DQR 63 0 005 7 0 O O DORS 7 0 DQS 7 0 O O DQRSI 0 DM 7 0 O O DMR 7 0 GLOBAL SDRAM CONNECTS 5 1 OHMS 2 0 O WA O BA 2 0 R A 13 0 O AA O 13 0 8 IRAS O AAN O ICAS O AAN O O WA O DQSR4 DQSR4 DQR 39 32 O DMRS DQSR5 DQSR5 20 DOS CS DM 20 DOS CS DM DQRI47 40 I O 7 0 I O 7 0 DMR6 O DQSR6 O DQSR6 DQS DOS CS DM 20 DOS CS DM DQR 55 48 l O 7 0 VO 7 0 DM
6. TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 713 Primary SDRAM Wisi 8 foo 774 Error Checking SDRAM Widi 15 Reserved UNUSED 16 SDRAM Device Attributes Burst Lengths Supported 0x0C TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM 0x08 Device 18 SDRAM Device Attributes CAS Latency 0x30 TBD TBD Latency 2 Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 8 DTM63367 972872117211 2 256 64 240 Pin Unbuffered DDR2DIMM Latency 3 Latency 4 X Latency 5 X Latency 6 TBD DIMM Mechanical Characteristics Max module thickness x lt 4 10 0x01 mm 20 DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD 22 24 25 TBD SDRAM Device Attributes General 0x02 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TBD 25 Clock Cycle TimeatCL X 2 ns SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM 1 Number of PLL on the DIMM N A for UDIMM 0 FET Switch External
7. Page 5 DTM63367 972172172111 2GB 256Mx64 240 in Unbuffered DDR2DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V Max PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address Bank Active 1000 bus inputs are switching Data bus inputs switching 680 mA Precharge Current 4 Operating One lour 0 mA BL 4 CL 5 ns AL 0 CKE is HIGH CS is Bank Active Read Ipp1 HIGH between valid commands Address bus inputs are 760 mA Precharge Current switching Precharge Power lo 2p All banks idle CKE is LOW Other control and address bus inputs 160 Down Current E are stable Data bus inputs are floating Precharge Quiet Ipp2Q All banks idle CKE is HIGH CS is HIGH Other control and 512 M Standby Current address bus inputs are stable Data bus inputs are floating Precharge Standby lop 2N All banks idle CKE is HIGH CS is HIGH Other control and 720 Current Dp address bus inputs are switching Data bus inputs are switching All banks open CKE is LOW Other control and address bus ugs LE Ipp3P inputs are stable Data bus inputs are floating Fast Power down 400 mA exit Mode Register bit 12 0 All banks open tras 70 ms CKE is HIGH CS is HIGH between Ipp3N valid commands Other control and address bus inputs 880 mA switching Data bus inputs are switching Al
8. rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 12
9. vss 109 vss hag vss 169 vss 199 229 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 2032 110 2956 i40 0014 170 VDD 200 0937 230 VREF Reference Voltage 21DQ10 61 VDD 81 0033 111 0057 han 0015 171 CKE1 201 vss 031 vss NC No Connection 220011 52 82 55 112 vss iw2vss 172 VDD 202 1232 DM7 23 VSS 53 VDD 83 0984 113 DQS7 143 0020 173 A15 203 233 24 0016 54 2 84 54 M14 poas i44 0021 174 14 204 vss 234 vss 25 0017 55 85 Vss 115 VSS 145 vss 175 VDD 205 0038 235 0962 26VSS 56 VDD 86 0034 116 0058 hag 176 A12 206 0039 236 0963 27 100952 57 A11 87 2035 117 0959 147 NC 177 9 207 VSS 237 VSS 28 0052 58 7 88 vss 118 vss i48 vss 178 VDD 208 0044 238 VDDSPD 29 VSS 59 VDD 89 0040 119 SDA hag 0022 179 A8 209 2045 239 30 0018 60 5 90 2041 120 scL 50 0023 180 6 210 VSS 240 SA1 Connected but not used Not used Non ECC DIMM Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 1 DTM63367 Front view 133 35 5 250 10 00 30 00 1 181 k 17 80 0 700 0 197 2 54 Min 5 18 gt 63 00 55 00 0 100 Min 0 204 2 480 g 2 165 gt 123 00 Al
10. 0 Differential Data Strobes 4 001 340025 64VDD 94 vss haa vas 154 vss 184 VDD 1214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS 95 0042 i25 155 DM3 185 215 0047 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO 36 53 66 vss 96 0043 26 NC 156 186 CKO 216 VSS CKE 1 0 Clock Enables 50 37 3 67 VDD 97 vss 27 vas 157 vss 187 VDD 217 0952 ICAS Column Address Strobe 8 VSS 38 VSS 68NC DQ48 128 pae 158 0030 188 AO 218 0953 IRAS Row Address Strobe 9 2 390026 69 VDD 0049 29 159 Do31 189 VDD 019 vss 13 0 Chip Selects 10 40 27 70 10 100 vas vas 160 vas 190 220 2 Write Enable 11 88 41 VSS 71 101 131 0012 161 CB4 191 VDD 1221 CK2 A 15 0 Address Inputs 12DQ8 j 42cBO 2 102 32 0013 162 cB5 192 RAS 222 vss BA 2 0 Bank Addresses 13009 43cB1 73 WE 103 vss vas 163 vss 193 50 223 DM6 ODT 1 0 On Die Termination Inputs 14 VSS 44 VSS 74 ICAS 104 56 34 164 DM8 194 VDD 1224 NC SA 2 0 SPD Address 15 0051 45 DQS8 75 VDD 105 base 135 NC 165 NC 195 ODTO 225 vss SCL SPD Clock Input 16 DQS1 46 058 76 51 106 vss i136 vss 166 vss 196 A13 226 DQ54 SDA SPD Data Input Output 17 VSS 47 VSS ODT1 M07 2950 137 167 CB6 197 VDD 1227 DQ55 vss Ground 18 NC 48 CB2 78 VDD 108 0051 CK1 168 CB7 198 vss 028 vss VDD Power 19 NC 49 CB3 79
11. Enable No TBD Analysis probe installed Hain Data Access Time tAC from Clock at CL X 1 Clock Cycle Time at Reduced CAS Latency CL BN EN RE TR Minimum Clock Cycle Time at CL X 2 ns UNUSED Ed i Data Access Time tAC from Clock at CL X 2 UNUSED Ez ium Row Precharge Time 2 29 Minimum RAS to CAS Delay tRCD n S 30 Minimum Active to Precharge Time tRAS ns 34 Data Input Setup Time Before er vee i 5 36 Write Recovery Time tWR ns Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 9 DTM63367 972872172111 2 256 64 240 Pin Unbuffered DDR2DIMM Internal write to read command delay tWTR ns Internal read to precharge command delay tRTP ns 39 Analysis Probe Characteristics UNUSED 40 Extension of Byte 41 tRC and Byte 42 tRFC ns 0x36 Add this value to byte 41 Add this value to byte 42 0 5 EN zii Minimum Active to Active Auto Refresh Time lee 42 SDRAM Minimum Auto Refresh to Active Auto 127 5 Ox7F Refresh Command Period tRFC ns 43 SDRAM Device Maximum Cycle Time CK max 8 0x0 44 M Dev DQS DQ Skew for DOS amp DO asa L DDR SDRAM Device Read Data Hold Skew Factor tQHS 0x1E 6 Sey Relock Time us UNUSED 0x00 47 DRAM maximun Case Temperature Delta Degree 0x50 DT4R4W Delta Bits 0 3 delta Bits 7 4
12. R7 DQSR7 DQSR7 20 DOS CS DM 20 DOS ICS DM DQR 63 56 110 7 0 V O 7 0 3 X 200 OHMS ab SDRAM X4 ICKO 1 5 pF 3 X 200 OHMS G SDRAM X 6 ICK1 3 X 200 OHMS S SDRAM 6 ICK2 DECOUPLING VDDSpD Serial PD VDD All Devices VREF All SDRAMs Vss All Devices SCL SERIAL PD SDA SA0 SA1 SA2 Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 3 DTM63367 2GB 256Mx64 240 Pin Unbuffered DDR2DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 85 C Voltage on Vpp relative to Vss 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V Recommended DC Operating Conditions 0 to 70 C Voltage referenced to 0 V PARAMETER Eu Minimum Tvbical Maximum Unit Note Power Supply Voltage Reference Voltage Bus Termination Voltage Notes Vrer 0 04 VREF Vrer 0 04 1 The value of Veer is expected to equal one half Vpp and to track variations the DC level Peak to peak noise Vrer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to
13. ads with Auto Precharge DT7 Degree C Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi T A PLL C Watt 7 8 59 2 5 5 Thermal Resistance of Register Package from Top to Ambient UNUSED 0x00 Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active UNUSED 0x00 DT PLL Active Degree fore Case Temperature Rise from Ambient due to Register Active Mode Bit 0x00 DT Register Active Mode Bit Bit O If O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default 0 0 Register Active Bits 2 7 0 62 SPD Revision 63 Checksum for Bytes 05 7850 Pat Hanker 000 1 92 796 ModueSeraNumer J os 797 Module SerialNumber 0O 2 98 Module SerialNumber oa 99 Manufacturer s Specific Data UNUSED 127 Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 11 DTM63367 972872172111 2 256 64 240 Pin Unbuffered DDR2DIMM DATARAM DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent
14. erage Periodic Refresh Interval 7 8 US Auto Refresh Row Cycle Time 127 5 nS How tre 12 5 ns Read DQS Preamble Time tRPRE 0 9 1 1 Read DOS Postamble Time test 0 4 0 6 Row Active to Row Active Delay tRRD 7 5 ns Internal Read to Precharge Command Delay trtp 7 5 ns Write DQS Preamble Setup Time twPRE 0 35 ps Write DQS Postamble Time twPsT 0 4 0 6 tck Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr 10 ns Exit Self Refresh to Read Command txsRD 200 tck Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 7 DTM63367 972872172111 2 256 64 240 Pin Unbuffered DDR2DIMM SERIAL PRESENCE DETECT MATRIX Module Attributes Number of Ranks Package and Height of Ranks 2 Card on Card No DRAM Package Planar W dt 5 Hex 0x80 0x08 0x08 OxOE Ox0A 0x61 8 09 S Module Height 30mm 8 Module Data Width UNDSED 8 Voltage Interface Level of this assembly SSTL 1 8V Cycle time Supported CAS Latency CL X 2 5 0x25 tCK ns 10 SDRAM Access from Clock Highest CAS latency ns 11 DIMM configuration type Non parity Parity or ECC 0x00 Data Parity Data ECC Address Command Parity
15. l banks open Continuous burst writes BL 4 CL 5 AL 0 Operating Burst tras 70 ms is HIGH CS is HIGH between valid Write Current Ino4W commands Address bus inputs are switching Data bus inputs 1440 MA are switching All banks open Continuous burst reads lour 0 mA BL 4 Operating Burst CL 5 AL 0 tras 70 ms CKE is HIGH CS is HIGH between 4440 mA Read Current valid commands Address bus inputs are switching Data bus inputs are switching Refresh command at every 75 ns CKE is HIGH CS is HIGH Burst Refresh Ipp5 between valid commands Other control and address bus inputs 2800 mA Current hee are switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V lt 0 2 V Other control and address bus 160 T Current PR inputs are floating Data bus inputs are floating All bank interleaving reads 0 mA BL 4 CL 5 AL 70 Operating Bank 5 Lor i d interleave Read Ipp7 ns tarp 7 5 ns CKE is HIGH CS is HIGH between valid 2960 mA commands Address bus inputs are stable during deselects Data bus inputs are switching One module rank in this operation rest in IDD2P All module ranks in this operation Current Note For all 155 measurements tek 2 5 ns tac 57 5 ns tacp 12 5 ns tras 45 ns trp 15 ns unless otherwise specified All currents are based on DRAM absolute maximum
16. values ea a a ea ge PD aE TTT SS a 7 A T TEE Document 06926 Revision A 18 DEC 07 Dataram Corporation 2007 Page 6 DTM63367 972872172111 2 256 64 240 Pin Unbuffered DDR2DIMM Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 400 400 ps 5 5 Command Delay 2 Clock High Level Width 0 45 0 55 Clock Cycle Time 2 5 8000 DS Clock Low Level Width 0 45 0 55 Data Input Hold Time after DOS Strobe tou 125 ps DQ Input Pulse Width 0 35 DOS Output Access Time from Clock tpasck 400 400 ps Write DQS High Level Width tpasH 0 35 tck Write DQS Low Level Width toast 0 35 DQS Out Edge to Data Out Edge Skew toasa 200 ps Data Input Setup Time Before DQS Strobe tos 50 ps DQS Falling Edge from Clock Hold Time 0 2 DOS Falling Edge to Clock Setup Time toss 0 2 Clock Period minimum of tcy or ns Address and Command Hold Time after Clock 250 DS Address and Command Setup Time before Clock tis 175 ps Load Mode Command Cycle Time 2 DQ to DQS Hold tup Lous Data Hold Skew Factor Lous 300 Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 57 5 ns RAS to CAS Delay trep 12 5 ns Av
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