Kingston Technology ValueRAM 2GB 667MHz DDR2 ECC Fully Buffered CL5 DIMM Dual Rank, x4
Contents
1. vss t S1 t 0 DQSO DOS9 DOSO DOS9 I DM cs DaS Dosi DM cs Das DAS DM cs Das DOS DM TS Das DOS DQO 1 00 1 0 0 DQ4 o0 1 0 0 DQ1 1 01 DO 1 0 1 D18 DQ5 101 D9 1 0 1 D27 DQ2 1 02 1 0 2 DQ6 102 1 0 2 DQ3 1 03 1 03 DQ7 03 1 0 3 DOS1 DOS10 DOS1 DOS10 DM TS Das DOS DM TS Das Das DM tS Das DAS DM TS Das Das DO8 00 oo DO12 100 00 DO9 jo 4 D1 1 0 1 D19 DQ13 101 D10 1 0 1 D28 DQ10 1 02 o2 DO14 02 02 DO1 93 o3 DO15 jo3 o3 DOS2 DQS11 DOS2 a DOS11 DM TS Das DAS Di TS Das DAS DM TS DaS Das D cs Das Das DO16 voo oo DO20 jo0 oo DO17 1 01 D2 O1 D20 DQ2. Compensation Resistor connected to Vss 1 DDRC_C12 DDR Compensation Resistor connected to Vpp 1 VALUERAM0483 001 A00 Page 5 Advanced Memory Buffer Pin Description ie Kingston SPD Bus Interface Signals 5 SCL Serial Presence Detect SPD Clock Input 1 SDA SPD Data Input Output 1 SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB 3 Miscellaneous Signals 163 PLLTSTO PLL Clock Observability Output 1 VCCAPLL Analog VCC for the PLL Tied with low pass filter to VCC 1 VSSAPLL Analog VSS for the PLL Tied to ground on the AMB die Do not tie to ground on the DIMM 1 TEST_pin Leave floating on the DIMM 6 TESTLO_pin Tie to ground on the DIMM2 5 BFUNC Tie to ground to set functionality as buffer on DIMM 1 RESET AMB reset signal 1 NC No connect Many NC are connected to VDD on the DIMM to lower the impedance of the VDD power 129 islands RFU Reserved for Future Use 18 Power Ground Signals 213 Vcc AMB Core Power 1 5 Volt 24 VccFrBD AMB Channel I O Power 1 5 Volt 8 VDD AMB DRAM I O Power 1 8 Volt 24 VppDsPD SPD Power 3 3 Volt 1 Vss Ground 156 Total 655 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK freguency 2 TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs each pin should have a zero ohm resistor pulldown to ground and an unpopulated resistor pullup to VCC T
3. SS4 114 Vss 234 Vss 25 PN1 145 SN1 55 PN7 175 SN7 84 Vss 204 Vss 115 VpD 235 VDD 26 PN1 146 SN1 56 Vss 176 Vss 85 Vss 205 Vss 116 Vop 236 VDD 27 Vss 147 Vss 57 PN8 177 SN8 86 RFU 206 RFU 117 Vit 237 Vrr 28 PN2 148 SN2 58 PN8 178 SN8 87 RFU 207 RFU 118 SA2 238 VDDSPD 29 PN2 149 SN2 59 Vss 179 Vss 88 Vss 208 Vss 119 SDA 239 SA0 30 Vss 150 Vss 60 PN9 180 SN9 89 Vss 209 Vss 120 SCL 240 SA1 90 PS9 210 SS9 RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations These pin positions are reserved for future architecture flexibility MIN _ _ _ 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN13 PS9 PS9 SS9 SS9 VALUERAM0483 001 A00 Page 2 Kingston DIMM Connector Pin Description Pin Name Pin Description Count SCK System Clock Input positive line 1 SCK System Clock Input negative line 1 PN 13 0 Primary Northbound Data positive lines 14 PN 13 0 Primary Northbound Data negative lines 14 PS 9 0 Primary Southbound Data positive lines 10 PS 9 0 Primary Southbound Data negative lines 10 SN 13 0 Secondary Northbound Data positive lines 14 SN 13 0 Secondary Northbound Data negative lines 14 SS 9 0 Secondary Southbound Data positive lines 10 SS 9 0 Secondary Southbound Data ne
4. pg VO1 D26 CB5___ yo4 VO1 D35 CB2 ___ 02 VO2 CB6 ___ 02 MW O2 CB3 1 03 V0 3 CB7 1 03 1 03 PNO PN13 SNO SN13 Vit p Terminators PNO PN13 SNO SN13 All address command control clock A Vit Voc T AMB PS0 PS9 SS0 SS9 PS0 PS9 550 559 Serial PD VpDsPD T7 SPD AMB DO00 D063 L 50 gt CS D0 D17 SCL F CBO CB7 A M CkE0 gt CKE D0 D17 p lt SDA Vpp DO D35 AMB DOS0 DOS17 a 51 gt CS D18 D35 AD A1 AM T DQS0 DQS17 CKE1 gt CKE D18 D35 Ka VREF DO D35 SCL F ODT gt ODTO all SDRAMs SAD SAT SAZ I SDa Lo _ BAO BA2 all SDRAMs Notes Vss l T DO D35 SPD A0 A15 all SDRAMs a Gy AMB SMSE LTR RAS all SDRAMs 1 DQ to I O wiring may be changed within a nibble RESET FE mi 2 There are two physical copies of each address command control SCK SCK CKICK all SDRAMs 3 There are four physical copies of each clock VALUERAM0483 001 A00 Page 4 ie Kingston Architecture Advanced Memory Buffer Pin Description Pin Name Pin Description Count FB DIMM Channel Signals 99 SCK System Clock Input positive line 1 SCK System Clock Input negative line 1 PN 13 0 Primary Northbound Data positive lines 14 PN 13 0 Primary Northbound Data negative lines 14 PS 9 0 Primary Southbound Data positive lines 10 PS 9 0 Primary Southbound Data negative lines 10 SN 13 0 Secondary Northbound Data posit
5. 10 183 SN10 93 PS5 213 SS5 4 Vss 124 Vss 34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 SS5 5 Voo 125 Vpp 35 PN4 155 SN4 65 Vss 185 Vss 95 Vss 215 Vss 6 Voo 126 Vpp 36 Vss 156 Vss 66 PN11 186 SN11 96 Ps6 l216 SS6 7 Vpop 127 Vop 37 PN5 157 SN5 67 PN11 187 SN11 97 PS6 217 SS6 8 Vss 128 Vss 38 PN5 158 SN5 68 Vss 188 Vss 98 Vss 218 Vss 9 Vec 129 Vcc 39 Vss 159 Vss EY 99 PS7 219 SS7 10 Vcc 130 Vcc 40 PN13 160 SN13 69 Vss 189 Vss 100 PS7 220 SS7 11 Vss 131 Vss 41 PN13 161 SN13 70 PSO 190 sso 101 Vss 221 Vss 12 Voc 132 Vcc 42 Vss 162 Vss 71 PS0 191 SS0 102 PS8 222 SS8 13 Vcc 133 Vcc 43 Vss 163 Vss 72 Vss 192 Vss 103 PS8 223 Ss8 144 Vss 134 Vss 44 RFU 164 RFU 73 PS1 193 ss1 104 Vss 224 Vss 15 Vrr l135 Vor 45 RFU 165 RFU 74 PS1 194 Sst 105 RFU 225 RFU 16 VID1 136 VIDO 46 Vss 166 Vss 75 Vss 195 Vss 106 RFU 226 RFU 17 RESET 137 DNU M_Test 47 Vss l 167 Vss 76 PS2 196 SS2 107 Vss 227 Vss 18 Vss 138 Vss 48 PN12 168 SN12 77 PS2 197 SS2 108 Vpp 228 SCK 19 RFU 139 RFU 49 PN12 169 SN12 78 Vss 198 Vss 109 VpD 229 SCK 20 RFU 140 RFU 50 Vss 170 Vss 79 PS3 199 SS3 110 Vss 230 Vss 21 Vss 141 Vss 51 PN6 171 SN6 80 PS3 200 SS3 111 Vop 231 VDD 22 PNO 142 SNO 52 PN6 172 SN6 81 Vss 201 Vss 112 VpD 232 Vpp 23 PNO 143 SNO 53 Vss 173 Vss 82 PS4 202 SS4 113 VDD 233 Vpp 24 Vss 144 Vss 54 PN7 174 SN7 83 Ps4 203
6. 21 1 01 D11 O1 D29 pais jo o2 DQ22 jo2 o2 DO19 793 o3 DQ23 jo3 103 DQS3 DQS12 DOS3 I EE DOS12 i DM TS Das DAS DM cs Das DAS DM TS Das DGS p cs Das Das DO24 00 1 0 0 DQ28 _ oo0 1 0 0 DO25 1 01 1 0 1 D21 DQ29 ___ O 1 1 0 1 DQ26 1 02 D3 1 0 2 DQ30 _ O2 Diz 1 0 2 re DQ27 03 1 0 3 DQ31 10 3 1 0 3 DOS4 DOS13 DOS4 DQS13 DM TS DAS DAS DM cs Das DAS DM cs Das DaS DM TS Das DAS D032 ___lyoo 00 DQ36 voo V0 0 D033 1 01 D4 VO1 D22 DQ37 J101 D13 m I 01 D31 DQ34 0 2 V0 2 DQ38 V02 1 02 D035 03 VO 3 D039 103 03 DOS5 DOS14 DOS5 DOS14 D GS Das Das DM TS Das DAS D T5 Das DGS DM TS Das Das DQ40 00 1 0 0 DQ44 oo 1 0 0 DOM jo1 D5 Vo1 D23 DQ45 01 D14 01 D32 DO42 02 VO 2 DO46 92 VO 2 DQ43 1 93 1 0 3 DQ47 1 93 1 0 3 DQS6 DOS15 DOS6 l DQS15 DM cs DaS DOS DM cs Das DAS DM cs Das DaS DM cs Das Das DQ48 1 00 1 0 0 DQ52 100 1 0 0 DO49 1 01 D6 1 0 1 D24 DO53 1 01 1 I 01 D33 DQ50 ___ jo 2 1 0 2 DO54 __ yo2 D15 1 0 2 DQ51 1 03 1 0 3 DQ55 1 03 1 0 3 DOS7 DOS16 DOS7 i DOS16 DM TS Das DOS DM cs Das Das DM GS Das Das DM cs Das DOAS Dae voo 00 DQ60 O0 1 0 0 1 01 VO1 p25 DO61 O 1 VO1 pass 02 aU o2 DO62 __ 192 DIe o2 a pass 103 o3 DO63 __ 1 93 VO 3 Dass DOS17 Dass I DOS17 DM TS Das DaS DM cs Das Das DM TS Das DOS DM cs Das Das CBO ___ 1 00 1 0 0 CB4___ yoo 1 0 0 CB1 01
7. Kingston OLOGY Memory Module Specifications KVR667D2D4F5 2G 2GB 256M x 72 Bit PC2 5300 CL5 ECC 240 Pin FBDIMM Description This document describes ValueRAM s 2GB 256M x 72 bit PC2 5300 CL5 SDRAM Synchronous DRAM fully buffered ECC dual rank memory module This module is based on thirty six 128M x 4 bit 667MHz DDR2 FBGA components The module also includes an AMB device Advanced Memory Buffer The electrical and mechanical specifications are as follows Feature FBDIMM Module 240 pin JEDEC Standard R C H Memory Organization 2 rank of x4 devices e DDR2 DRAM Interface SSTL_18 e DDR2 Speed Grade 667 Mbps e CAS Latency 5 5 5 Module Bandwidth 5 3 GB s FBDIMM Channel Peak Throughput 8 0 GB s e DRAM VDD VDDQ 1 8V e AMB VCC VCCFBD 1 5V e EEPROM VDDSPD 3 3V typical e Heat Spreader AMB only heat sink PCB Height 30 35mm double side e RoHS Compliant VALUERAM0483 001 A00 04 14 06 Page 1 DDR2 240 pin FBDIMM Pinout Kingston Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Side Side Side Side Side Side Side Side 1 Voo 121 Vpp 31 PN3 151 SN3 61 PN9 181 SN9 91 PS9 211 ss9 2 Vpp 122 Vpp 32 PN3 152 SN3 62 Vss 182 Vss 92 Vss 212 Vss 3 Voo 123 Vpp 33 Vss 153 Vss 63 PN
8. gative lines 10 SCL Serial Presence Detect SPD Clock Input 1 SDA SPD Data Input Output 1 SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB 3 Voltage ID These pins must be unconnected for DDR2 based Fully Buffered DIMMs MID VID 0 is Vpp value OPEN 1 8 V GND 1 5 V VID 1 is Vcc value OPEN 1 5 V GND 1 2 V 2 RESET AMB reset signal 1 RFU Reserved for Future Use 16 Vec AMB Core Power and AMB Channel Interface Power 1 5 Volt 8 Vpp DRAM Power and AMB DRAM I O Power 1 8 Volt 24 Vrr DRAM Address Command Clock Termination Power V pp 2 4 VppsPD SPD Power 1 Vss Ground 80 The DNU M Test pin provides an external connection on R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It DNU M Test is not intended to be used in normal system operation and must not be connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time 4 Total 240 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK freguency 2 Eight pins reserved for forwarded clocks eight pins reserved for future architecture flexibility VALUERAM0483 001 A00 Page 3 Kingston Functional Block Diagram
9. hese resistors can be replaced on production DIMMs with a direct connection to ground VALUERAM0483 001 A00 Page 6 Kingston Package Dimensions Units millimeters en 133 35 R 0 75 8 PLACES o o o o ua a S gt o 1 19 DIA o o Z N Q S 0 10 3 gt 24 40 23 15 19 62 4 G 16 82 a 12 10 A G 3 00 DIAM F a 4 PLACES 4 39 0 21 1 30 t 2 a YR N gwe a Pw ES Lu o o allo DETAIL A Ss 1 50 DIA R 0 75 oom 7 aa 0 10 oun PLACES T a 2 PLACES cC ooo ANAC 0 346 8 8 MAX with heat sink Units inches millimeters 45 x 0 0071 0 18 Agee 0 047 1 19 a 1 06 ld E lt 0 042 1 06 0 054 1 37 Detail A 0 046 1 17 VALUERAM0483 001 A00 Page 7
10. ive lines 14 SN 13 0 Secondary Northbound Data negative lines 14 SS 9 0 Secondary Southbound Data positive lines 10 SS 9 0 Secondary Southbound Data negative lines 10 FBDRES To an external precision calibration resistor connected to Vcc 1 DDR2 Interface Signals 175 DOS 8 0 Data Strobes positive lines 9 DOS 8 0 Data Strobes negative lines 9 DQS 17 9 DM 8 0 Data Strobes x4 DRAM only positive lines These signals are driven low to x8 DRAM on writes 9 DOS 17 9 Data Strobes x4 DRAM only negative lines 9 DQ 63 0 Data 64 CB 7 0 Checkbits 8 A 15 0 A A 15 0 B Addresses A10 is part of the pre charge command 32 BA 2 0 A BA 2 0 B_ Bank Addresses 6 RASA RASB Part of command with CAS WE and CS 1 0 2 CASA CASB Part of command with RAS WE and CS 1 0 2 WEA WEB Part of command with RAS CAS and CS 1 0 2 2 A A ODTA ODTB On die Termination Enable CKE 1 0 A CKE 1 0 B Clock Enable one per rank CS 1 0 A CS 1 0 B Chip Select one per rank CLK 1 0 used on 9 and 18 device DIMMs CLK 3 0 used on 36 device DIMMs CLK 3 2 should be out CLKI3 0 put disabled when not in use 4 CLK 3 0 Negative lines for CLK 3 0 4 DDRC_C14 DDR Compensation Common return pin for DDRC_B18 and DDRC_C18 1 DDRC_B18 DDR Compensation Resistor connected to common return pin DDRC_C14 1 DDRC_C18 DDR Compensation Resistor connected to common return pin DDRC_C14 1 DDRC_B12 DDR
Download Pdf Manuals
Related Search