Transcend 128MB SDRAM PC100 ECC Unbuffer Memory
Contents
1. tcc 10ns 45 mA in power down mode Icc3PS amp CLK lt ViL max tcc lt 45 Active Standby Current Icc3N CKESViH min CS gt VIH min tcc 10ns 270 Input singals are changed one time during 30ns in non power down mode Bank Acti Vene Baus CUN IccaNS CKE ViH min CLK lt ViL max tec Input singals are stable 180 loL 0 mA Operating Current Bust Mode 4 Page Burst 1 125 mA 1 tccp 2CLKs Refresh Current 5 tRC2tRC min 1 890 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 14 mA Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS ViH ViLZVDDQ VSSQ Transcend Information Inc 7 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT AC OPERATING TEST CONDITIONS von 3 3V 0 3V 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 qe oe 1200 Ohm 50 Ohm gt DC 2 4V 2 Output 4 202500119 Vot DC 0 4V lo 2mA 50pF 870 Ohm e 777 7 7 UI Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise not2. 128MB 168Pin PC100 CL3 ECC TS1 6M LS72V8D SDRAM DIMM With 16Mx8 3 3VOLT Description Placement The TS16MLS72V8D is a 16M bit x 64 Synchronous Dynamic RAM high density for PC 133 The TS16MLS72V8D consists of 8 CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS16MLS72V8D is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allows the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 Conformed to JEDEC Standard 4 clocks Burst Mode Operation Auto and Self Refresh Power Down Mode DQM Byte Masking Read Write Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs PCB 09 7143 e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave All inputs are sampled at the positive going edge of the system clock Transcend Information Inc 1 TS16MLS72V8D 128MB 168Pin PC100 CL3 ECC SDRAM DIMM With 16Mx8 3
3. 3VOLT Dimensions Side Millimeters A 133 35 0 40 65 67 23 49 8 89 3 00 F 31 77 0 20 G 19 80 H 15 80 1 27 0 10 Refer Placement Inches 5 250 0 016 2 585 0 925 0 350 0 118 1 250 0 008 0 788 0 622 0 050 0 004 Pin Identification Symbol Function 0 11 0 1 Address input DQ0 DQ63 CLKO CLK2 CKEO CS0 CS2 RAS CAS ANE DQM0 DQM7 SA0 SA2 SCL SDA Vcc Vss NC Data Input Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data DQ Mask Address in EEPROM Serial PD Clock Serial PD Add Data input output 3 3 Voltage Power Supply Ground No Connection Refer Block Diagram AND Pinouts Transcend Information Inc 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT Pinouts Pin Pin i Pin Pin Name No No Name Transcend Information Inc 3 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT TS16MLS72V8D Block Diagram 0 A0 A11 E RAS RAS ICAS WE ICSO CKEO ICS2 0 11 0 1 DQ0 DQ7 SDRAM CLKO CLK2 Serial EEPROM 0 1 2 SA0 SA1SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the
4. ation Command H X X X L H H Transcend Information Inc 10 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT Serial Presence Detect Specification Serial Presence Detect Byte No Function Described eure Vendor Part Specification 0 Number of Bytes Written into Serial Memory 128bytes 80 1 Total Number of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on this Assembly 12 0C 4 Number of Column Addresses on this Assembly 10 0A 5 Number of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 72bits 48 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC ECC 02 15 625us Self 12 Refresh Rate Type Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width X8 08 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec A
5. ed Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time ERASMI 59 ns tRAS max 100 us Row cycle time tRC min 70 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay 1 CLK 3 Number of valid CAS latency 3 2 4 output data Note 1 minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 8 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol value Min Valure Max Unit Note CLK cycle time tcc 10 1000 ns 1 CLK to valid output delay tSAC 6 ns 1 2 Output data hold time tOH 3 ns 2 CLK high pulse width tCH 3 ns 3 CLK low pulse width 3 ns 3 Input setup time 155 2 ns 3 Input hold time tSH 1
6. ll Auto Prec 0E R W Burst 23 SDRAM Cycle Time 2 highest CL 12ns CO 24 SDRAM Access from Clock 2 highest CL 7ns 70 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 20ns 14 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 50ns 32 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 2ns 20 33 Command Address Hold Time ins 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time ins 10 36 61 Information 00 62 SPD Data Revision Code Ver 1 2 12 63 Checksum for Bytes 0 62 58 64 71 Manufacturers ID Dode per JEP 108E Transcend 72 Man Manufacturers ufacturing Location T 54 54 53 31 36 4D 4C 73 90 Number TS16MLS72V8D 53 37 32 56 38 44 20 20 20 20 20 20 91 92 Revision Code 0 Transcend Information Inc 11 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 _ Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 3 F4 128 Unused Storage Locations Open FF Transcend Information Inc 12
7. ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output pea ae in Hi Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the paremeter 3 Assumed input rise fall time tr amp tf ins If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 9 128MB 168Pin PC100 CL3 ECC TS1 6M LS72V8D SDRAM DIMM With 16Mx8 3 3VOLT SIMPLIFIED TRUTH TABLE Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H H L L L H X x 3 Entry L 3 Refresh Self L H H H 3 Refresh i etres Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Adress Auto Precharge Disable L Column 4 Read amp 3 H SEU THE x Adress Column Address Auto Precharge Enable H 4 5 i Auto Precharge Disable L Column 4 hine amp 9 H X L H L L X V Adress Column Address Auto Precharge Enable H Ao As 4 5 Burst Stop H X H H X X 6 Bank Selection V L Precharge Both Banks H X L H X X H X Clock Suspend or Entry H L X 5 x X Active Power L V V V X Down Exit L H X X X X X H X X X Entry H L x Precharge Power L H H Down Mode Exit H X X X L H X L V V V DOM H X V X 7 H X X X No Oper
8. s include Hi Z output leakage for all bi directional buffers with Tri State outputs Transcend Information Inc 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT CAPACITANCE TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA1 28 50 pF Input capacitance RAS CAS WE CIN2 28 50 pF Input capacitance CKEO CIN3 28 50 pF Input capacitance CLKO CLK2 CINA 18 25 pF Input capacitance CS0 CS2 CIN5 18 30 pF Input capacitance DQMO DQM7 CIN6 8 10 pF Data input output capacitance DQ0 DQ63 COUT 9 12 pF Data input output capacitance CBO CB7 COUT 9 12 pF Transcend Information Inc 6 128MB 168Pin PC100 CL3 ECC TS1 6MLS72V8D SDRAM DIMM With 16Mx8 3 3VOLT DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current Burst Length 1 4 1 One Bank Active Inc neun loLZ0mA Precharge Standby Current CKE lt VIL max tcc 10ns 9 mA in power down mode Icc2PS amp CLK lt ViL max tcc 9 CKE ViH min gt tcc 10ns Icc2N Input singals are changed one time during 30ns 180 Precharge Standby Current mA in non power down mode p IccoNS min CLKxViL max 63 nput singals are stable Active Standby Current lt
9. use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 TS16MLS72V8D ABSOLUTE MAXIMUM RATINGS 128MB 168Pin PC100 CL3 ECC SDRAM DIMM With 16Mx8 3 3VOLT Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 C Power dissipation PD 9 W Short circuit current los 50 mA Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Type Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V 2 Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage current
Download Pdf Manuals
Related Search