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Intel S5500WB

1. J1C2 1 Bu T Bi Normal 2 E Clear g 3 Password uH HEE E El El E El EC BIOS Recovery Mode uj fe u fury fur 19 J1C3 9 Normal 2 Recovery 3 e Reset BIOS Configuration nnnm J1B4 Ho a Normal 2 Reset BIOS u lu e UL HU 3 Configuration BG B ENE all B DE ds CLE EO AF003049 Figure 21 Jumper Blocks J1B5 J1C2 J1C3 J1B4 J6A3 J6A2 J7A2 Revision 1 3 45 Intel order number 53971 004 Configuration Jumpers Intel Server Board S5500WB TPS Table 16 Server Board Jumpers J1B5 J1C2 J1C3 J1B4 J6A3 J6A2 Mode of J1B5 BMC Force IBMC GPIO 1 is pulled HIGH Default position Update jumper Update IBMC GPIO 1 is pulled LOW J1C2 Password Clear ICH10R INTRUDER pin is pulled HIGH Default position Clear Password ICH10R INTRUDER amp pin is pulled LOW J1C3 BIOS Recovery 1 2 Normal ICH10R GPIO 55 is pulled HIGH Default Mode position 2 J1B4 CMOS Clear 1 2 Normal ICH10R RTCRST pin is p
2. 003062 Figure 30 Temp Sensor Location Location Description A U4K3 Temp Sensor TMP75 93 Heatsinks The Intel Server Board S5500WB system cooling solutions rely on heatsinks for CPU cooling Chipset and or voltage regulator heatsinks are compatible with the 1U usage Revision 1 3 79 Intel order number 53971 004 Design and Environmental Specifications Intel Server Board S5500WB TPS Note The Intel Thermal Solution STS100P Passive 1U 2U heatsink was tested for processors up to and including 95 W TDP Thermal Design Power Product order code 5 5100 9 3 1 Unified Retention System Support The server board complies with the Intel Unified Retention System URS and the Unified Backplate Assembly The server board ships with a made up assembly of Independent Loading Mechanism ILM and Unified Backplate at each processor socket The URS retention transfers load to the server board via the unified backplate assembly The URS spring captive in the heatsink provides the necessary compressive load for the thermal interface material All components of the URS heatsink soluti
3. G oon od aS jc B loge Ir io Ir io EE ODI LII 1 HD Ed E HOB m E El El E unu nu LU run fun mu AG UU TU TU Be B E to 003115 e o e e e e e Figure 23 Fan Fault LED Locations A FLTMEM2R E FLTCPU1 B FLTMEM2 F FLTCPU1A C FLTCPU2A G FLTMEM1 D FLTCPU2 H FLTMEM1R 8 3 System Status LED The server board provides LED for system status The following figure shows the LED location 68 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Intel Light Guided Diagnostics System Status LED m lt
4. aa me In AF003116 Figure 24 System Status LED Location The bi color System Status LED operates as follows Table 50 System Status LED System ready Revision 1 3 69 Intel order number 53971 004 Intel Light Guided Diagnostics Intel Server Board SSSOOWB TPS System degraded BIOS detected 1 Unable to use all of the installed memory more than one DIMM installed 2 In a mirrored configuration when memory mirroring takes place and system loses memory redundancy This is not covered by 2 3 PCI Express correctable link errors Integrated BMC detected 1 Redundancy loss such as a power supply or fan Applies only if the associated platform subsystem Glen 1 Hz Degraded has rodundangy capabities blink CPU disabled if there are two CPUs and one CPU is disabled Fan alarm Fan failure Number of operational fans should be more than minimum number needed to cool the system Non critical threshold crossed Temperature voltage power nozzle power gauge and 2 Therm Ctrl sensors Battery failure Predictive failure when the system has redund
5. 1 222 00 000000 0 0000000000000000000000022 35 3 13 2 PE WIDTH eaa aea a a a a r rae Aa a ra aaea lara ea kn dae 35 3 13 3 Slot 1 PCI Express x8 Connector esses 36 3 134 Module 36 Intel Expansion Modules cene sn sans 37 Platform Management 240000945 39 5 1 BIOS Feature Overview 39 5 1 1 etr eR e e REOR EP EEA 39 5 1 2 Intel Rapid Boot sonde bed rettet 39 5 1 3 BIOS ce M 39 5 2 BMC Feature 2 0 1 14 2 2 40 0 0000000000000000000000000000 0 0000000050055 39 5 2 1 Server Engines Pilot Gontrollgr toc abate ea oot eco te teeth ttd 40 5 2 2 BMC Firmwares 40 5 2 3 BMC Basic 41 5 2 4 BMC Advanced 4 1 1 222 21200 0 0000000000000000000000000000000000 41 5 3 Management Engine 2222 4 000000 nannte 42 5 3 1 t p rat ben 42 5 3 2 BMC Management Engine
6. 42 5 4 Data Center Manageability 42 5 5 Other PlatformiManagelient os oco cect Peto tare Eae apa 42 Intel order number 53971 004 Table of Contents Intel Server Board SSSOOWB TPS 5 5 1 Wake On LAN MO D nh eee ei ek 42 5 5 2 PCI Express Power marneagelTieril 43 5 5 3 iul ue 43 5 6 SMBUS Architecture 43 5 6 1 SMBUS Device Addresses imet dieto eate ob Ene 43 6 Configuration 5050 arua esi equa FEE pk uad 45 6 1 1 Force IBMC Update J1B5 ao creer 46 6 1 2 Password NT PE 47 6 1 3 BIOS Recovery Mode J103 Gia OU 48 6 1 4 Reset BIOS Configuration 1 4 2 21 49 6 1 5 Video Master JOA I J e Rp 49 6 1 6 ME Firmware Force Update 7 2 2 aeree e e e eerie tcl 50 6 1 7 Serial Interface J6A2 mue diode 50 7 Connector Header Locations and 51 T 1 Power Connectors ee 51 7 2 System Management Headers 2 5 1 1
7. 52 Table 27 Peripheral Power Only for 12 V only SKU J8K2 iPN C22293 003 MOLEX CONNECTOR CORPORATION 43045 0627 nee 52 Table 28 Intel RMM3 Connector Pin out J5B1 cccccccccccsscsssesseesssescsescescecsecseeeeeeeeeeeeeeeeees 53 Table 29 BMC Power Cycle Header J1D2 53 Revision 1 3 xi Intel order number 53971 004 List of Tables Intel Server Board SSSOOWB TPS Table 30 IPMB Header 4 pin J1B2 54 Table 31 SGPIO Header ir 54 Table 32 Front Panel SSI Standard 24 Connector Pin out 1 1 54 Table 33 Power LED Indicator States ice iron 56 Table 34 System Status bED 4 eer ena tr rre eto 57 Table 35 Chassis ID LED Indicator 4422 1 58 Table 36 Slot 6 Riser Connector JAB 1 etie tae tapas 59 Table 37 Slot 1 PCI Express x8 Connector 1 3 22 22 22 60 Table 38 VGA External Video Connector 6 1 2 61 Table 39 VGA Internal Video Connector 101 61 Table 40 RJ 45 10 100 1000 NIC Connector Pin out 8 2 9
8. um 252 5 A 558 Figure 6 Connector Locations Intel order number E5397 1 004 78 681 EIS S S859 S ms dme SES ES 35 85 e je e e e S 21 28 ol gt 25 Ss 25 a ee S o en SB be 75 44 so mt EN gt lee 1100 581 4 855 123 321 5 374 136 501 2X 9 120 231 65 d Ss Ol 32 NET EN 222 29 4 AX 11 820 285 151 4 11 947 1303 451 FT s i 3X 12 130 EL SEES 308 101 ji J 12 262 311 451 Revision 1 3 Intel Server Board SSSOOWB TPS COMPOMENT HEIGHT UNDER 10 MODULE IS 138 3 5mm 110 061 Server Board Overview COMPONENT HEIGHT UNDER SAS MODULE IS 138 3 5mm me ea 5 COMPONENT HEIGHT FOR PCI E E 4 CARD 15 300 7 62mm P COMPOMENT HEIGHT UNDER RMM3 eS g 8 MODULE 15 102 2 60mm EI 89 8 5 ER Sz2 7 ae LONE Sg Ss s Se 58 o c 5 COMONENT ALLOWED 2k 0 100 T 29 UNDER RMM3 CONNECTOR 2 54 Bs 15 138 3 5mm 5x 0 125 THRU HOLE o 13 18
9. 18V Se TYLERSBURG TVLERSBURG XDP CPU PLL m iv CPU Peg 2008 e SSI SKU This version of the server board is designed to work with an off the shelf multi rail power supply that adheres to the SSI power specification Power Supply Design Guideline for 2008 Dual Socket Servers and Workstations You can view SSI specifications at the following website http ssiforum org 12V SKU This version of the server board is designed to work with specially designed single rail power supplies that provide 12V and 5V standby current The server board has integrated high efficiency voltage regulators that produce other voltages required for example 3 3 V 5 V and so forth and can also supply 5 V power required by hard drives 82 Intel order number 53971 004 Revision 1 3 Intel Server Board SSSOOWB TPS Power Subsystem The SSI uses the standard 24 pin and 8 pin power headers along with the 5pin Control connector The 12 V only uses two 8 pin power headers a 7 pin control header and a 6 pin HDD power connector For maximum rack server efficiency a DC 12 V only power supply is recommended Appendix A shows connector pin outs 10 3 Power Sequencing and Reset Distribution The IBMC device is integrated into the power control and reset logic of the system This design reduces the discrete logic requirements of previous generations and at the same time permits FW to manage certa
10. nnn nnn 53 7 2 1 Intel Remote Management Module 3 Intel RMM3 Connector 53 7 2 2 BMC Power Cycle Header 12V 53 7 2 3 Hard Drive Activity Input LED 54 7 2 4 PMB Header ERG e RR RR ER ERA ERE Aa A 54 7 2 5 SGPIOQO Feader cr rec e ro t ken bof pa e baee P p gd 54 7 3 SSI Control Panel COMM COM 54 7 3 1 Power Button iie ii iR ERE RARE M viens dU Ud Th e MAN BE FIRMA 55 7 3 2 Reset BU ttor eT ederet t Habet irati let ovata pe dented 55 7 3 3 NMI Button UR FE ee E ERU DRE ROO CHAR oe RE Rr E n 55 7 3 4 BUON sesto t teque tinc xo 56 7 3 5 56 7 3 6 System Status LED ren ire e EM e e 56 7 3 7 SETA lb WE D EE E AAA 58 7 4 A EEE 59 7 4 1 PCI Express 59 7 4 2 DN 61 7 4 3 ersTe ariete As 62 7 4 4 S rera e e M tee IR dre eter NER RR 63 7 4 5 Intel I O Expansion Modu
11. nnn 10 1 Server Board Power Distribution 10 2 Power Supply Compatibility 10 3 Power Sequencing and Reset Distribution 11 Regulatory and Certification Information 11 1 Product Regulation Requirements 11 1 1 Product Safety Compliance 11 1 2 Product EMC Compliance Class A Compliance 11 1 3 Certifications Registrations Declarations 11 2 Product Regulatory Compliance Markings 11 3 Electromagnetic Compatibility Notices 11 3 1 FCC Verification Statement USA Revision 1 3 Intel order number E53971 004 Table of Contents Table of Contents Intel Server Board SSSOOWB TPS 115527 ICGES 003 Canada tants 86 11 3 3 Europe CE Declaration of Conformity 87 11 34 BSMI I TU E 87 KCC Korea fences 87 Appendix A POST Code LED De Code iiss csccicessscrissicsacsseudeccaderscessscussecvesuvestiverstecnsiueedtaceunsses 88 Appendix B Video POST Code Errors essen nennen nnn nnns 95 GlOSSaEy iieeideo ent iode imer oris pi miba ai in ERE eve ELE Ii Aem Div TRE 99 Reference Documents 5
12. SERVER BOARD inside Intel Server Board SSSOOWB Technical Product Specification Intel order number E53971 004 Revision 1 3 August 2009 Enterprise Platforms and Services Division Revision History Intel Server Board SSSOOWB TPS Revision History Date Revision Modifications Number 03 30 2009 Initial Release 04 29 2009 Formatting corrections 05 20 2009 1 2 Updated heatsink installation steps Corrected processor fault table Added jumper location figure Updated memory support Corrected PCle slot speed Removed S4 support ii Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designe
13. Table 4 Mixed Processor Configurations System Action The BIOS detects the error condition and responds as follows e Logs the error into the system event log SEL e Alerts the Integrated BMC of the configuration error with an IPMI command e Does not disable the processor e Displays 0194 Processor family mismatch detected message in the error manager e Halts the system The BIOS detects the error condition and responds as follows e Logs the error into the SEL e Alerts the Integrated BMC of the configuration error with an IPMI command e Does not disable the processor e Displays 0192 Cache size mismatch detected message in the error manager e Halts the system The BIOS detects the error condition and responds as follows e Adjusts all processor frequencies to the lowest common denominator e Continues to boot the system successfully If the frequencies for all processors cannot be adjusted to be the same then the BIOS e Logs the error into the SEL e Displays 0197 Processor speeds mismatched message in the error manager e Halts the system The BIOS detects the error condition and responds as follows e Logs the error into the SEL e Does not disable the processor e Displays 816x Processor 0x unable to apply microcode update message in the error manager e The system continues to boot in a degraded state regardless of the setting of POST Error Pause in the Se
14. 35 Table 11 PEWIDTH Strapping 35 Table 12 Intel I O Expansion Module Bus PEWIDTH Bits eee 36 Table 13 Intel I O Expansion Module Product Codes 37 Table 14 Advanced eene 41 Table 15 SMBus Device Address 43 Table 16 Server Board Jumpers J1B5 J1C2 J1C3 J1B4 J6A3 2 46 Table 17 Force IBMC Update 46 Table 18 Password Clear 47 Table 19 BIOS Recovery Mode JUmpfer ce adeo 48 Table 20 Reset BIOS 49 Table 21 Video Master 49 Table 22 SSI SKU 24 pin 2x12 Connector 9 1 51 Table 23 CPU 12V Power 2x4 Connector 5 1 51 Table 24 SSI Power Control JOD cits esee to 51 Table 25 12 V only 2x4 Connector replaces EPSD12V 2x12 connector J9D2 51 Table 26 12 V Only Power Control replaces the 1x5 power control J9D1 FOXCONN ELECTRONICS INC HF1107V P1 or TYCO ELECTRONICS CORPORATION 5 104809 i
15. CPU1 CH E1 OxAE CONN VIDEO CONN Platform Management Features Intel Server Board SSSOOWB TPS Power Sub Power Device SMBus Note Rail Bus Rail Address PERENNE CPU M CPUO DIMM 1E CPUO DIMM 1F Baseboard FRU CPU IOH IPMI 3V3SB IBMC SMBus 0 IPMI SVSB_ IPMI Connector IBMC SMBus 5 PWR Sensor 3V3SB NA NA 44 Revision 1 3 Intel order number 53971 004 Intel Server Board S5500WB TPS Configuration Jumpers 6 Configuration Jumpers The following table provides a summary and description of configuration test and debug jumpers on the Intel Server Board S5500WB The server board has several 3 pin jumper blocks that can be used Pin 1 on each jumper block can be identified by the following symbol on the silkscreen V Serial Interface J6A2 ME BMC Update m o Q pare J7A2 Video Master Internal 2 Normal External 4 Update DSR to DTR BMC Force Update e T 5 Normal 2 o L NN r Update 685 3 689 p ff NM e CE d Password Clear
16. 90 Table 57 POST Error Messages and 95 26 GIOSSANY MEM C CH 99 xii Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS List of Tables lt This page intentionally left blank gt Revision 1 3 xiii Intel order number 53971 004 Intel Server Board SSSOOWB TPS Introduction 1 Introduction The Intel Server Board S5500WB is a dual socket server using the Intel Xeon Processor 5500 series processor in combination with the IOH and ICH10R to provide a balanced feature set between technology leadership and cost 1 1 Section Outline This document is divided into the following chapters e Section 1 Introduction e Section 2 Server Board Overview e Section 3 Functional Architecture Section 4 I O Expansion Modules e Section 5 Platform Management Features e Section 6 Configuration Jumpers e Section 7 Connector and Header Location and Pin out e Section 8 Intel Light Guided Diagnostics e Section 9 Design and Environmental Specifications Section 10 Power Subsystem Section 11 Regulatory and Certification Information e Appendix A POST Code LED Decoder Appendix B Video POST Code Errors 1 2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis deve
17. Hot Sensor in VR11 1 9 2 3 Board Temperature Sensor For rack based systems or those systems that do not have a front panel temp sensor the board is enabled to use a board mounted industry standard TMP75 type temp sensor This part is on the IBMC two wire serial SENSOR bus The use of digital parts removes calibration and placement location issues imposed by the alternate analog type sensors 9 2 4 Thermals Sensor Placement The SMBUS based temp sensors are placed such that the ambient air temp can be measured Placement near hot components and or downstream of hot components including chassis based hot spots is avoided The following figure shows the sensor placement on the Intel Server Board S5500WB 78 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Design and Environmental Specifications 105500
18. Crisis recovery initiated by software corrupt flash 0x34h 0 0 1 1 0 1 0 0 Loading crisis recovery capsule 0x35h 0 0 1 1 0 1 0 1 Handing off control to the crisis recovery capsule 0 36 00 1 1 0 1 1 0 Begin crisis recovery Ox3Eh 0 0 1 1 1 1 1 0 No crisis recovery capsule detected Ox3Fh 0 0 4 1 1 1 1 1 Crisis recovery capsule failed integrity check of capsule descriptors 94 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Appendix B Video POST Code Errors Appendix B Video POST Code Errors Whenever possible the BIOS outputs the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes a progress code can be customized to fit the data width The higher the data bit the higher the granularity of information that can be sent on the progress port The progress codes may be reported by the system BIOS or option ROMs The Response section in the following table is divided into three types No Pause The message is displayed on the local Vidoe screen during POSTor in the Error Manager The system continues booting with a degraded state The user may want to replace the erroneous uni
19. Data Center Management Interface Dynamic Host Configuration Protocal DPC Direct Platform Control Electrically Erasable Programmable Read Only Memory Enhanced Host Controller Interface EMP Emergency Management Port External Product Specification Fully Buffered DIMM Flexible Mother Board FRB Fault Resilient Booting Field Replaceable Unit Front Side Bus General Purpose I O Gunning Transceiver Logic GPA Guest Physical Address Revision 1 3 99 Intel order number E53971 004 Glossary Term O S E N I U 12C o gt F IC MB IMC INTR IPMB IPMI T KCS LAN LCD LED LPC LUN m UJ MD2 D5 MTTR o NIC NMI OBF EM PECI PEF PEP PIA PLD PMI POST O O 5 100 Definition Hot Swap Controller Host Physical Address Hertz 1 cycle second Inter Integrated Circuit Bus Intel Architecture Input Buffer Controller Hub Intelligent Chassis Management Bus and Firmware Bridge Independent Loading Mechanism Integrated Memory Controller Interrupt Internet Protocol Intelligent Plattorm Management Bus Intelligent Plattorm Management Interface Infrared In Target Probe 1024 bytes Keyboard Controller Style Local Area Network Liquid Crystal Display Light Emitting Diode Low Pin Count Logical Unit Number Media Access Control 1024KB Management Engine Message Digest 2 Hashing Algorithm Message Digest 5 Hashin
20. 3 448 Memory Reservation for Memory mapped Functions A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset processor and BIOS flash memory mapped I O regions This region displays as a loss of memory to the operating system In addition to this loss the BIOS creates another reserved region for memory mapped PCI Express functions including a standard 64 MB or 256 MB of standard PCI Express Memory Mapped I O MMIO configuration space This is based on the setup selection using the MAX BUS NUMBER feature offered by Intel Tylersburg chipset and a variably sized MMIO region for the PCI Express functions All these reserved regions are reclaimed by the operating system if Physical Address Extension PAE is turned on in the operating system 3 4 5 High Memory Reclaim When 4 GB or more of physical memory is installed physical memory is the memory installed as DDR3 DIMMs the reserved memory is lost However the Intel 5500 Series Chipset provides a feature called high memory reclaim which allows the BIOS and operating system to remap the lost physical memory into system memory above 4 GB the system memory is the memory that can be seen by the processor The BIOS will always enable high memory reclaim if it discovers installed physical memory equal to or greater than 4 GB For the operating system the reclaimed memory is recoverable only when it supports and enables the PAE feature in the processor
21. and C The memory channels from socket 2 are identified as Channels D E and F The DIMM identifiers on the silkscreen on the board provide information about the channel and therefore the processor to which they belong For example DIMM 1 is the first slot on Channel A on processor 1 DIMM D1 is the first DIMM socket on Channel D on processor 2 Table 5 DIMM Nomenclature Processor Socket 1 Processor Socket 2 Channel Channel B Channel C Channel D Channel E Channel F A1 A2 B1 C1 D1 D2 E1 F1 If the socket is not populated the memory slots associated with a processor socket are unavailable You can install a processor without populating the associated memory slots provided a second processor is installed with associated memory In this case the memory is shared by the processors However the platform suffers performance degradation and latency due to the remote memory Sockets are self contained and autonomous However all configurations in the BIOS setup such as RAS Error Management and so forth are applied commonly across sockets 22 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture 3 4 3 ECC Support If at least one non ECC DIMM is present in the system the system reverts to non ECC mode UDIMMs can be ECC or non ECC RDIMMs are always ECC enabled Non ECC DIMMs are not validated and not recommended for server use
22. of Intel Corporation Intel and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names be claimed as the property of others Copyright Intel Corporation 2009 Revision 1 3 iii Intel order number 53971 004 Table of Contents Intel Server Board SSSOOWB TPS Table of Contents 1 Introduction rmn nennen xen ner nnn rrr nnn rr nk era Rea Ex Eran Rr nean 1 1 1 Fea eut m ra 1 1 2 Server Board Use Disclaimer 1 2 Server Board OVGrviGW ic armia eid Eid si asd Ead nc eed LU o Fa FR ESL Peta Fa mda bed E 2 2 1 Intel Server Board S5500WB Server 4 2 2 Server Board Connector and Component 6 2 2 1 Board Rear Connector 8 2 2 2 Server Board Mechanical 8 3 Functional Architecture saves racernssanceeaavivanesuscssanassbiidesencaveanaiedsarvineds 13 3 1 High Level Product F Gallles tub ta 13 3 2 Functional Block et o iet eae Ra 14 3 3 Intel Xeon BhOD Sales oso tbe oe Oben csse tds 15 3 3 1 Processor Suppoltt ER FO E ORE
23. option ROM OxB6A3 DXE boot services driver Unrecognized 98 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Glossary Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed first for example 82460GX with alpha entries following for example AGP 4x Acronyms are then entered in their respective place with non acronyms following Table 58 Glossary Term Definition ACPI Advanced Configuration and Power Interface Application Processor U APIC Advanced Programmable Interrupt Control ARP Address Resolution Protocal ASIC Application Specific Integrated Circuit BIOS Basic Input Output System BIST Built In Self Test BMC Baseboard Management Controller Bridge Circuitry connecting one computer bus to another allowing an agent on one to access the other BS Byte 8 bit quantity U Bootstrap Processor CATERR On a catastrophic hardware event the core signals CATERR to the uncore The core enters a halted state that can only be exited by a reset CBC Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis CEK Common Enabling Kit Challenge Handshake Authentication Protocol In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board
24. pin is pulled LOW Clearing the Password Power down server Do not unplug the power cord Open the chassis For instructions see your server chassis documentation Move jumper J1B6 from the default operating position covering pins 1 and 2 to the password clear position covering pins 2 and 3 Close the server chassis Power up the server wait 10 seconds or POST completes Power down the server Open the chassis and move the jumper back to default position covering pins 1 and 2 Close the server chassis Power up the server Revision 1 3 47 Intel order number 53971 004 Configuration Jumpers Intel Server Board S5500WB TPS The password is now cleared and you can reset it by going into the BIOS setup 6 1 3 BIOS Recovery Mode J1C3 The Intel Server Board S5500WB uses BIOS recovery to repair the system BIOS from flash corruption in the main BIOS and Boot Block This 3 pin jumper is used to reload the BIOS when the image is suspected to be corrupted For directions on how to recover the BIOS refer to the specific BIOS release notes Table 19 BIOS Recovery Mode Jumper Jumper Mode of Position Operation Note 1 2 Normal ICH10R GPIO 55 is pulled HIGH Default position Recovery ICH10R GPIO 55 is pulled LOW You can accomplish a BIOS recovery from the SATA CD and USB Mass Storage device Please note that this platform does not support recovery from a USB floppy The recovery media must c
25. 1 62 zie MES MGrena erect 63 Table 42 50 pin Intel I O Expansion Module Connector Pin out J2B1 3 1 64 Table 43 External RJ 45 Serial Port A COM1 7 1 65 Table 44 Internal 9 pin Serial COM2 2 65 Table 45 External USB Connector 8 1 9 1 65 Table 46 Internal USB Connector 1 1 and 9 2 65 Table 47 Low Profile Internal USB Connector 1 2 66 Table 48 SSI 4 pin Fan Connector J2K2 J2K3 J3K1 J7K1 J8K4 8 5 66 Table 49 8 pin Fan Connector J2K1 amp J8K3 MOLEX CONNECTOR CORPORATION 53398 0890 or 53398 0871 recette 66 Table 50 System Status LED sss E a nennen nennen nnne 69 Table 51 Standard Front Panel 74 Table 52 Fan Connector Location amp 76 Table 53 Fan Connector Location amp Detail br te ie o Re 77 Table 54 Product Regulatory Compliance 66 85 Table 55 POST Progress Code LED Example sess 89 Table 56 Diagnostic LED POST Code Decoder 0 0 0
26. 7 8 9 Close the server chassis Reconnect the AC cord and power up the server Perform the BMC firmware update procedure as documented in the README TXT file included in the given BMC firmware update package After successful completion of the firmware update process the firmware update utility may generate an error stating the BMC is still in update mode Power down and remove the AC power cord Open the server chassis Move the jumper from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC cord and power up the server Note Normal BMC functionality is disabled with the Force BMC Update jumper is set to the enabled position You should never run the server with the BMC Force Update jumper set in this position You should only use this jumper setting when the standard firmware update process fails This jumper should remain in the default disabled position when the server is running normally The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server board 6 1 2 Password Clear J1C2 The user sets this 3 pin jumper to clear the password 6 1 2 1 1 2 3 Table 18 Password Clear Jumper Jumper Position Mode of Operation Note 1 2 Normal ICH10R INTRUDER pin is pulled HIGH Default position Clear Password ICHIOR INTRUDER
27. BMC to the chipset The BIOS does not affect the behavior of the reset button 7 3 3 NMI Button The BIOS supports a front control panel NMI button The NMI button may not be provided on all front panel designs Pressing the NMI button initiates a request that causes the Integrated BMC Revision 1 3 55 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS to generate an NMI non maskable interrupt The NMI is captured by the BIOS during boot services time and by the operating system during runtime During boot services time the BIOS halts the system upon detection of the NMI 7 3 4 Chassis Identify Button The front panel Chassis Identify button toggles the state of the chassis ID LED If the LED is off pushing the ID button lights the LED It remains lit until the button is pushed again or until a Chassis Identify or a Chassis Identify LED command is received to change the state of the LED 7 3 5 Power LED The green power LED is active when the system DC power is on The power LED is controlled by the BIOS The power LED reflects a combination of the state of system DC power and the system ACPI state The following table identifies the different states that the power LED can assume Table 33 Power LED Indicator States ACPI Power LED s5 Of 51 Sleep 1 Hz blink SO 1 Yes 7 36 System Status LED Note The system status LED state shows the
28. Es elk EE aC EM 102 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS List of Figures List of Figures Figure 1 Intel Server Board S5500WB 12V cccccccccssssssscecsesesenscsesesesscecsesesesecseseseecseseseneeees 4 Figure 2 Intel Server Board 55500 WB 591 nei pastore ctetu io tse au beatos b cr bte hut 5 Figure 3 Intel Server Board S5500WB Components both SKUs are 6 Figure 4 Rear Panel Connector Placement eese ente 8 Figure 5 Baseboard and Mounting 2 1 9 Figure 6 Contiector Localioris ee ante Ebr E etude 10 Figure 7 Primary Side Height Restrictions ooi eto 11 Figure 8 Secondary Side Height Restrictions 12 Figure 9 Intel Server Board S5500WB Functional Block 14 Figure 10 Lifting the load lever of ILM 17 Figure 11 Removing the socket cover e Chel Et nee desino nre 18 Figure 12 Installing DIOCeSSOF s oco e 18 Figure 13 Package Installation Remove 19 Figure 14 Installing Removing Heatsink errechnet tret
29. GND 27 69 GND PERxN12 69 28 PETXN3 GND 28 70 PETxP13 GND 70 29 GND PERxP3 29 71 13 GND 71 30 RSVD PERxN3 30 72 GND PERxP13 72 31 PRSNT2 GND 31 73 GND PERxN13 73 32 GND RSVD 32 74 PETxP14 GND 74 33 PETxP4 RSVD 33 75 14 GND 75 Revision 1 3 59 Intel order number E5397 1 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS Pin Pin Pin Pin Side Side Side Side B PCI Express Signal PCI Express Signal A B PCI Express Signal PCI Express Signal A 34 PETxNA4 GND 34 76 GND PERxP14 76 35 GND PERxP4 35 77 GND PERxN14 77 36 GND PERxN4 36 78 PETxP15 GND 78 37 PETxP5 GND 37 79 PETxN15 GND 79 38 5 GND 38 80 GND PERxP15 80 39 GND PERxP5 39 81 PRSNT2 PERXN15 81 40 GND PERxN5 40 82 RSVD GND 82 Table 37 Slot 1 Express x8 Connector J1B3 Pin Side B PCI Express Spec Signal Description Pin Side A PCI Express Spec Description Signal 12V 12V Reserved 12V GND GND SMCLK JTAG TCK SMDATA JTAG TDI GND JTAG TDO 3 3V JTAG TMS JTAG TRST 9 3 3V 3 3VAux 10 3 3V Wake 11 PERST KEY KEY KEY 12 Reserved 12 GND 13 GND 13 REFCLK1 4 PETp 0 4 REFCLK1 PETn 0 GND GND Reserved GND PETp 1 Reserved PETn 1 GND GND PERp 1 GND PERn 1 PETp 2 GND PETn 2 GND GND PERp 2 GND PERn 2 PETp 3 GND PETn 3 GND GND PERp
30. J7A1 J7A2 found on the back edge of the server board and the internal connector J9D3 centered on the right side of the board Table 45 External USB Connector J8A1 J9A1 Signal Name Two 2x5 connectors on the server board provide an option to support an additional four USB ports The pin out is the same for both of the connectors and is detailed in the following table Table 46 Internal USB Connector J1C1 and J9A2 NOS il J 10 NC ND USB U 5V Revision 1 3 65 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS One low profile 2x5 connectors J1D4 on the server board provides an option to support low profile USB based embedded flash devices The pin out of the connector is detailed in the following table Table 47 Low Profile Internal USB Connector J1E2 Pin SignalName__ 7 5 Fan Headers The server board provides six SSI compliant 4 pin fan headers and two 8 fan headers to be used for CPU and IO cooling The pin configuration for each of the 4 pin fan headers is identical and defined in the following tables Table 48 SSI 4 pin Fan Connector J2K2 J2K3 J3K1 J7K1 J8K4 J8K5 Pin SignalName Description 2 12V Power Supply 12V EN TEM AN TACH signal is connected to the BMC to monitor the fan speed 4 PWM OUT PWM signal to control fan speed Table 49 8 pin Fan Connector J2K1 amp J8K3 MOLEX CONNECTOR CO
31. The DCMI specifications are derived from Intelligent Platform Management Interface IPMI 2 0 The DCMI specifications define a uniform set of monitoring control features and interfaces that target the common and fundamental hardware management needs of server systems that are used in large deployments within data centers such as Internet Portal data centers This includes capabilities such as secure power and reset control temperature monitoring event logging and others For more information refer to www intel com go dcmi 5 5 Other Platform Management The platform supports the following sleep states S1 and S5 Within SO the platform supports additional lower power states such as C1e and C6 for the CPU 5 5 1 On LAN WOL e Wake On LAN WOL is supported on both LAN ports and IOM LAN modules for all supported Sleep states e Wake on Ring is supported on the external Serial port only for all supported Sleep states e Wake on USB is supported on the rear and front panel USB ports for S1 only e Wake on RTC is supported for all supported Sleep states 42 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Platform Management Features e Wake IPMI command is supported BMC function no additional hardware requirement for all supported Sleep states 5 5 2 PCI Express Power management LO and L3 power management states are supported on all PCI Express slots and embedded end points 5 5 3 PMB
32. ee ree e pens HI EN REA DERE REA TR 15 3 3 2 Processor Population Rules 15 3 3 3 Installing or Replacing the Processor 22 22 444 20009 17 3 3 4 Intel QuickPath Interconnect Intel QPI cccccscsesesesescseecsescsesesesesesseestsneteceees 20 3 4 Intel QuickPath Memory Controller cccccccscsesesesescsescsescetsescssscesecstscseseecseeceees 21 3 4 1 Supported MEMORY nee rrr Rn e ee a A e a a eee rn 21 3 4 2 Memory Subsystem 22 3 4 3 ECC SUDDOLE utto te ug 23 3 4 4 Memory Reservation for Memory mapped 23 3 4 5 High Memiory Reclaim arreter retine ce thc n 23 3 4 6 Memory Population xcti Eae e Ge dte toti ines 23 3 4 7 Installing and Removing Memory coiere dei des brennt e oa ene Ee en o duet 24 3 4 8 Channel Independent 25 3 4 9 Memory RAS uated atau 25 34 10 Memory Error LED sssrinin 26 3 5 Intel 5500 GhipsellO dae em titt ie eee 26 3 5 1 IOH2A4D PCI EXpr8SsS ce eee tree RE E ET ee PR 27 3 6 Management Be Et P
33. pair consists of 84 signals 20 differential pairs in each direction plus a forwarded differential clock in each direction Each Intel 5500 series processor supports two Intel QPI links one going to the second processor and one going to the Intel 5500 chipset IOH Data signal pairs 2 7 Tx TX Clock signal pair Data signal pairs x Clock signal pair Device 1 Device 2 Figure 15 Intel Link In the current implementation Intel QPI ports are capable of operating at transfer rates of up to 6 4 GT s Intel QPI ports operate at multiple lane widths full 20 lanes half 10 lanes and quarter 5 lanes independently in each direction between a pair of devices communicating via the Intel QPI The server boards support full width communication only For more information see the Intel Overview Rev 1 04 Documenti 380531 34 Intel QuickPath Memory Controller The Intel 5500 series processor has an integrated memory controller on its package Each Intel 5500 Series processor produces up to three channels of DDR3 memory The Intel QPI Memory Controller supports DDR3 800 DDR3 1066 and DDR3 1333 memory technologies The memory controller supports both Registered DIMMs RDIMMs and Unbuffered DIMMs UDIMMs Mixing of RDIMMs and UDIMMs is not supported 3 4 1 Supported Memory The Intel Server Board S5500WB supports six DDR3 memory channels three per processor socket with two
34. variety of payloads a larger Flash component is required to maintain both the platform BIOS and a useful payload An 8 MB Flash should be sufficient to support a payload of approximately 5 MB A significant part of this payload is the 4 5 MB used by the Intel Rapid Boot Toolkit 5 1 3 BIOS Recovery The platform BIOS supports a BIOS Recovery Mode Jumper The BIOS samples this jumper during POST through a GPIO and if set defaults to a recovery mode of operation that allows restoration of the BIOS Flash to a full operational state The platform BIOS supports a Reset BIOS Configuration Jumper The BIOS samples this jumper during POST through a GPIO and if set resets its configuration information stored in Flash memory 5 2 BMC Feature Overview The server management subsystem consists of multiple components including several interconnected microcontrollers The subsystem monitors platform sensors temperatures voltages fans hard drives and so forth implements platform acoustics power and thermal management policies provides an intelligent LCD front panel and provides facilities for remote and local management Revision 1 3 39 Intel order number 53971 004 Platform Management Features Intel Server Board SSSOOWB TPS The server management subsystem is available when the system is connected to wall power but not fully operational 55 state when the system is 51 sleep state or when the system is fully operational SO
35. z WITH 236 C6mm NO COMPONENT 5 z MAX COMPONENT HEIGHT FOR NO COMPONENTS ALLOWED UNDER ed TAB 15 250 6 35mm PCI E CARD TAB 2 PLACES 5 zw P 0 250 0 000 BS 2 16 351 10 001 e 0 600 115 241 1 254 2X 0 871 131 851 5 22 121 2X 1 277 132 441 4 SY r 1 648 lt Pow 41 861 Se 2 Ss 1 900 2 100 40 26 150 801 ep K K e gt Vy WAX COMPONENT HEIGHT IN THIS ZONE IS 295 7 50mm 4 2 0 405 3 482 T 110 291 88 44 2 0 080 o 2 031 pl 4 430 112 521 4 181 4 945 1121 441 125 351 4 981 126 521 5 649 5 950 S 1151 137 y 6 028 J d 153 111 1 249 184 121 MAX COMPONENT HEIGHT ZEPHYR BOARD IS 127 3 22mm 0 4007 L10 16MM NO COMPONENTS FOR ZEPHYR MOUNTING MAX COMPONENT HEIGHT UNDER PCI CARD ZONE IS 0 600 15 2mm 10 891 216 631 21 or O TYLERSBURG HEATSINK KEEPOUTS SHOWN FOR REFERENCE ONLY 0 382 9 70 0 151 3 84 1 326 18 33 681 28 401 1 604 40 741 2 082 52 881 2 643 67 131 3 518 89 36 MAX COMPONENT HEIGHT UNDER CPU HEATSINK 293 7 45 PLACES 133 145 621 Figure 7 Primary Side Height Restrictions Revision 1 3 Intel order number E53971 004 11 Server Board Overview Intel Server Board SSSOOWB TPS Figure 8 Secondary Side Height Restrictions Re
36. 1 1 1 0 0 0 0 1 Started dispatching early initialization modules PEIM OxE2h 1 1 1 0 1 0 Initial memory found configured and installed correctly OxE3h 1 1 1 010 0 1 1 Transfer control to the DXE Core PEI Modules OxFOh 1 1 1 1 0 0 0 O Install PEIM for Platform Status Codes OxF1h 1 1 1 1 0 0 0 1 Detecting Platform Type OxF2h 1 1 1 1 0 0 1 O Early Platform Initialization OxF3h 1 1 1 1 0 0 1 1 PEI Modules initialized Driver eXecution Environment DXE Core OxE4h 1 1 1 0 0 1 0 0 Entered EFI driver execution phase DXE OxE5h 1 1 1 010 1 0 1 Started dispatching drivers OxE6h 1 1 1 0101 1 0 Started connecting drivers DXE Drivers OxE7h 1 1 1 0 1 1 O 1 Waiting for user input OxE8h 1 1 1 0 1 0 0 0 Checking password OxE9h 1 1 1 0 1 O 0 1 Entering BIOS setup OxEAh 1 1 1 0 1 1 0 0 Flash Update OxEBh 1 1 1 0 1 1 O 1 Legacy Option ROM initialization OxECh 1 1 1 0 1 0 0 0 DXE Drivers initialized OxEDh 1 1 1 0 1 0 0 1 Transfer control to Boot Device Selection BDS OxEEh 1 1 1 0 1 1 0 0 Calling Int 19 One beep unless silent boot is enabled OxEFh 1 1 1 01 1 1 O 1 Unrecoverable boot failure Revision 1 3 93 Intel order number 53971 004 Appendix A POST Code LED Decoder Intel Server Board SSSOOWB TPS Pre EFI Initialization Module PEIM Recovery 0x30h 0 0 1 1 0 0 0 0 Crisis recovery initiated because of a user request 0x31h 0 0 1 1 0 0 0 1
37. 2 BMC Power Cycle Header 12V Only A header is provided so you can use an external switch to remove power from the BMC In effect it causes a BMC Power on reset to occur Table 29 BMC Power Cycle Header J1D2 Pin Desciption Note RST BMC PWR CYC When power is removed from the BMC 2 Gu JD Z4 Revision 1 3 53 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS If this switch is used while the system power is still applied then the main power rail regulators is disabled first then the main 3 3V S B regulator is disabled removing power from the BMC The usage of this header is to recover a non responsive board possibly caused by a hung BMC 7 2 3 Hard Drive Activity Input LED Header Table 47 SATA HDD Activity Input LED Header J1E3 Pin Description LED HD ACTIVE L 7 2 4 IPMB Header Table 30 IPMB Header 4 pin J1B2 __ SignlNam f Besripin SMB 5VSB DAT BMC IPMB 5 standby data line GND Ground SMB IPMB 5VSB CLK BMC IPMB 5V standby clock line P5V STBY 5V standby power 7 2 5 SGPIO Header Table 31 SGPIO Header J1B1 Pin SignlName Description SCLOCK SGPIO Clock Signal SLOAD SGPIO Load Signal SDOUTO SGPIO Data Out SDOUTI SGPIO Data In 73 54 Control Panel Connector The server board provides a 24 pin SSI front panel conne
38. 20 Figure 15 Intel OPI Te a se ctetur um uh 21 Figure 16 Memory Channel Population etat cette 23 Figure 17 Installing ree testo dt 24 Figure 18 Mirroring Memory Configuration 26 Figure 19 Integrated BMC Hardware 33 Figure 20 SSSOOWB SMBUS Block Diagram 43 Figure 21 Jumper Blocks J1B5 J1C2 J1C3 J1B4 J6A3 2 2 45 Figure 22 5 V Standby Status LED Locator oett da 67 Figure 23 Fan Fault LED Locatlons rre onere eee toa dete ed Re dees ERE RC RR EMEN nese 68 Figure 24 System Status LED Eo6allgrte ssim be put boda tette 69 Figure 25 DIMM Fault LEDS Locations x iei eil eae E aed 72 Figure 26 Rear Panel Diagnostic 73 Figure 27 Thermal Zones icto oce evene rem etu tende aeger hatten Gates tian LoT E cd 75 Figure 28 Location of Fan Connectors 2 cccccesesseceeecceeeeeeeeeeeeseeeeceneeeeeeeseeeneneedenestenseeenees 76 Figure 29 Fans and Sensors Block 77 Figure 30 Temp Sensor LOCAUON Fee pee aiuti gna eta 79 Figure 31 Un
39. 2h 1 0 1 010 0 1 0 QPlilnitialization OxA3h 1 0 1 010 0 1 1 Initialization OxA4h 1 0 1 0 0 1 0 0 JQPI Initialization 5 1 0 1 0 0 1 0 1 JQPI Initialization OxA6h 1 01 0 0 1 4 0 JQPI Initialization OxA7h 1 0 1 0 0 1 1 1 Initialization OxA8h 1 0 1 0 1 0 0 0 QPI Initialization OxA9h 101 0 1 0 0 1 JQPI Initialization OxAAh 1 141 0 1 0 1 O JQPI Initialization OxABh 1 0 1 0 1 0 1 1 QPllnitialization OxACh 1 0 1 Of 1 1 0 0 JQPI Initialization OxADh 10 1 0 1 1 0 1 JQPI Initialization OxAEh 1 0 1 Of 1 1 1 0 JQPI Initialization OxAFh 1 0 1 0 1 1 1 1 Initialization Integrated Memory Controller IMC OxBOh 1 0 1 1 0 0 0 0 Memory Initialization of Integrated Memory Controller OxB1h 1 0 1 1 0 0 0 1 Memory Initialization of Integrated Memory Controller OxB2h 1 0 1 1 0 oO 1 0 Memory Initialization of Integrated Memory Controller OxB3h 1 0 1 1 0 0 1 1 Memory Initialization of Integrated Memory Controller OxB4h 1 0 1 1 0 1 0 0 Memory Initialization of Integrated Memory Controller OxB5h 1 0 1 1 0 1 0 1 Memory Initialization of Integrated Memory Controller OxB6h 1 0 1 1 0 1 1 0 Memory Initialization of Integrated Memory Controller OxB7h 1 0 1 1 0 1 1 1 Memory Initialization of Integrated Memory Controller OxB8h 1 0 1 1 1 0 0 0 Memory Initialization of Integrated Memory Controller OxB9h 1 0 1 1 1 0 0 1 Memory Initialization of Integrated Memory Controller OxBAh 1 0 1 1 1 0 1 0 Memory Initialization of Integrated Memory Controll
40. 3 Reserved PERn 3 PRSNT2 GND GND Reserved Reserved 34 34 GND 35 GND 35 36 GND 36 37 37 GND 38 38 GND 60 Intel order number E5397 1 004 Revision 1 3 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out Pin Side PCI Express Spec Signal Description Pin Side A PCI Express Spec Description Signal GND GND 7 4 2 Connectors The following table details the pin out definition of the external VGA connector J6A1 Table 38 VGA External Video Connector J6A1 Pin _ SignaName Description VIO R GONN Blue analog colors 5o round s mo 8mm i V_IO_VSYNC_CONN VSYNC vertical sync V IO DDCCLK DDCCLK The following table details the pin out definition of the internal VGA connector J1D1 Table 39 VGA Internal Video Connector J1D1 Pin Signal Name Signal Name Pin 1 2 R_RTN Red Return 3 Green 4 G_RTN Green Return 5 Blue 6 B_RTN Blue Return Revision 1 3 61 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS Pin Signal Name Pin Signal Name Vsync 8 GND Hsync GND KEY VIDEO IN USE signal DDC SDA GND DDC SCL 7 4 3 NIC Connectors The server board provides two stacked RJ 45 2xUSB connectors side by side on the bac
41. 3 Canada Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe Aprescrites dans la norme sur le mat riel brouilleur Appareils Num riques NMB 003 dict e par le Ministre Canadian des Communications English translation of the notice above This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications 86 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Regulatory and Certification Information 11 3 3 Europe CE Declaration of Conformity This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance 11 3 4 BSMI Taiwan The BSMI Certification Marking and EMC warning is located on the outside rear area of the product EEA AE FRES 11 3 5 Following is the KCC certification information for Korea English translation of the notice above I2 9M Hs Bre 4s Halal MHES zx Oo ONA Type of Equipment Model Name On Certif
42. Bus Communications Protocol Specification Version 1 0 1998 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Platform Environmental Control Interface PECI Specification Version 2 0 Intel Corporation Platform Management FRU Information Storage Definition Version 1 0 Revision 1 2 2002 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation http developer intel com design servers ipmi spec htm Revision 1 3 Intel order number 53971 004
43. CPU installed to use follow the clamped algorithm for component thermal sensor The following sample SDR settings could be used e Use Tcontrol byte 8 bit 0 1 Tcontrol value is provided by BIOS via the Set CPU TControl command for the indicated CPU is used Revision 1 3 77 Intel order number 53971 004 Design and Environmental Specifications Intel Server Board SSSOOWB TPS Tcontrol offset Temperature 2 e Pos hyst O C Neg hyst 3 C Those parameters in turn set the following e Upper CPU Tcontrol Tcontrol offset e Lower CPU Tcontrol Tcontrol offset 9 2 2 Memory Temperature Sensor DDR3 cooling requires thermal throttling to protect memory from overheating The Intel Server Board S5500WB supports both DDR3 UDIMM and DDR3 RDIMM SPD temperature sensor DIMM is anticipated to be available on all DDR3 RDIMM but not for non ECC UDIMM so open loop thermal throttling and closed loop thermal throttling are supported e Static open loop thermal throttling The system does not change any of the control registers in the processor during runtime OLTT control registers are configured by BIOS MRC and remain fixed after post e Static closed loop thermal throttling The system does not change the control registers for a closed loop in the processor during runtime CLTT control registers are configured by BIOS MRC For advanced implementation with dynamic OLTT and CLTT refer to the
44. CPU throttling data via PECI The path between the CPU s and IBMC TTL_CPU_PROCHOTS is there as a backup An external source can also toggle PROCHOT to force the CPU to go into throttling mode This usually happens when the system reaches a certain thermal threshold VRHOT is an output of the CPU VR controller which is capable of throttling the CPU via PROCHOT Some simple masking circuitry is required to prevent the VRHOT from asserting the PROCHOT to the CPUs at the time of CPU_RST This keeps the VRHOT from unintentionally causing the CPU to disable FW monitors VRHOT and creates a SEL event if VRHOT is asserted There is no fan action as a result of the BMC seeing VRHOT 9 4 2 THERMTRIP comes from the CPU The THERMTRIP signal is tied to a unique GPI on IBMC for FW to monitor The combined THERMTRIPZ s from both CPUs is also tied to the ICH10R THERMTRIP input to cause an automatic Power Off condition when activated 943 CATERR The CATERR signal from the CPU signals a catastrophic error occurred CATERR may signal two types of issues One type is a warning and is indicated by a pulse on the signal The other is the static critical error which is indicated by a continuously asserted level on the signal The BMC only logs the static Critical Error events and ignores the warnings indicated by the pulse An error on the CPU is immediately communicated to the ICH10R for notification Revision 1 3 81 Intel order n
45. Connector Placement Description Description A ID LED E RJ 45 GbE LAN connector B Status LED F RJ 45 Serial port connector C RJ 45 GbE Dual USB connector G DB15 Video D Dual USB connector H Diagnostic LEDs 2 2 2 X Server Board Mechanical Drawings The following figures are mechanical drawings for the Intel Server Board S5500WB 8 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Server Board Overview Figure 5 Baseboard and Mounting holes Revision 1 3 g Intel order number E53971 004 Server Board Overview 6 182 Intel Server Board SSSOOWB TPS 2x 1 3899 35 281 82 5 ais 4 085 103 761 5 080 129 03 so 47 98 3 190 1 Mii 81 031 5 350 135 891 5 116 131 47 4X 6 780 112 211 10 E 22 of 48 EN 2 Bc mc s amp amp amp S 2 5 E 5 2 0 290 0 245 11 31 16 22 i 9 115 12 92 0 087 2 21 0 180 ias 14 57 19 531 0 398 1 550 8 139 37 lt 8 2x 1 610 40 891 1 311
46. DIMM DDR3 memory 8 DIMMs total across six memory channels three channels per processor in a 2 1 1 configuration VRD optimized to support QR x8 DIMMs No support for QR x4 DIMMs Intel 5500 Chipset IOH Intel 82801Jx I O Controller Hub ICH10R External connections DB 15 Video connectors RJ 45 serial Port A connector RJ 45 connector for 10 100 1000 LAN One 2x USB 2 0 connectors One RJ 45 over USB for 10 100 1000 LAN Internal connections Two USB 2x5 pin header supporting four USB 2 0 ports One low profile USB 2x5 pin One DH 10 Serial Port B header One 2x8 pin VGA header with presence detection to switch from rear I O video connector Six SATA Il connectors Intel 1 0 Expansion Module Dual Connectors One RMM3 connector to support optional Intel Remote Management Module 3 SATA SW RAID 5 Activation Key Connector One SSI EEB compliant front panel header Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Server Board Overview Power Connections SSI SKU One SSI EEB compliant 24 pin main power connector SSI only SKU One SSI compliant 8 pin CPU power connector One SSI compliant 5 pin power control Connector SSI only SKU 12 V Only SKU One 8 pin power connector One 6 pin Aux power connector for 3 3 V and 5 V One 7 pin power control connector supporting two processor zones and two memory zones in a redundant fashion Add in Adapter Support One rise
47. DIMMs on the first channel and one DIMM on the second and third channels of each processor Therefore the server board supports up to 8 DIMMs with dual processor sockets with a maximum memory capacity of 64 GB Revision 1 3 21 Intel order number E5397 1 004 Functional Architecture Intel Server Board SSSOOWB TPS The server board supports DDR3 800 DDR3 1067 and DDR3 1333 memory technologies Memory modules of mixed speed are supported by automatic selection of the highest common frequency of all memory modules The following configurations are not supported validated or recommended e Mixing of RDIMMs and UDIMMs is not supported e Mixing of memory type size speed and or rank has not been validated and is not supported e Mixing memory vendors has not been validated and is not recommended e Non ECC memory has not been validated and is not supported in a server environment NOTE Mixed memory is not tested or supported Non ECC memory is not tested and is not recommended for use in a server environment The Intel Server Board S5500WB uses 2 1 1 memory DIMM layout A 2 1 1 layout was chosen for its lowest power for a particular bandwidth and because it allows the maximum possible bandwidth when a 1 1 1 memory population is used 3 4 2 Memory Subsystem Nomenclature DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets The memory channels from socket 1 are identified as Channels A B
48. ED Color LED State NIC State 10 Mbps Green Amber Right 100 Mbps Green Left Blinking Transmit Receive activity 3 8 1 MAC Address Definition The Intel Server Board S5500WB has the following four MAC addresses assigned to it at the Intel factory e NIC 1 MAC address 30 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture NIC 2 MAC address Assigned the NIC 1 MAC address 1 e Integrated BMC LAN Channel MAC address Assigned the NIC 1 MAC address 2 e Intel Remote Management Module 3 Intel RMM3 MAC address Assigned the NIC 1 MAC address 3 The Intel Server Board S5500WB has a white MAC address sticker included with the board The sticker displays the NIC 1 MAC address in both bar code and alphanumeric formats 3 8 2 LAN Connector Ordering The Intel 82576 NIC is connected to a stacked RJ 45 over USB mag jack for NIC 1 and a RJ 45 mag jack for the second connection NIC 2 3 9 Integrated Baseboard Management Controller The ServerEngines LLC Pilot Il Integrated BMC is provided by an embedded ARMS controller and associated peripheral functionality that is required for IPMI based server management Firmware usage of these hardware features is platform dependant The following is a summary of the Integrated BMC management hardware features used by the ServerEngines LLC Pilot II Integrated BMC e PMI 2 0 Compliant e In
49. I O Controller Hub Super I O 0x63h 0 1 1 0 0 O 1 1 Initializing Super I O Local Console 0x70h 0 1 1 1 O 0 0 0 Resetting the video controller VGA Ox7 1h 0 1 1 1 0 0 0 1 Disabling the video controller VGA 0x72h 0 1 1 1 0 0 1 O Enabling the video controller VGA 0x73h 0 1 1 1 0 0 1 1 Reserved for video controller VGA Remote Console 0x78h 0 1 1 1 1 0 0 0 Resetting the console controller 0x79h 0 1 1 1 1 0 0 1 Disabling the console controller Ox7Ah 0 1 1 1 1 O 1 0 Enabling the console controller Ox7Bh 0 1 1 1 1 0 1 1 Reserved for console controller Keyboard only USB 0x90h 1 0 O 1 0 0 0 0 Resetting the keyboard 0x91h 1 0 O 1 0 0 0 1 Disabling the keyboard 0x92h 1 0 0 1 0 0 1 0 Detecting the presence of the keyboard 0x93h 1 0 O 1 0 0 1 1 Enabling the keyboard 0x94h 1 00 11 0 1 0 0 Clearing keyboard input buffer 0x96h 1 0 0 110 1 1 0 Reserved for keyboard Mouse only USB 0x98h 1 0 O 1 0 0 1 0 Resetting the mouse Ox99h 1 0 0 1 0 0 1 1 Detecting the mouse Ox9Ah 1 00 1 0 1 1 0 Detecting the presence of mouse Ox9Bh 1 00 170 1 1 1 Enabling the mouse Ox9Ch 1 0 0 1 0 0 1 0 Reserved for mouse Serial Port OxA8h 1 0 1 0 1 0 0 0 Resetting the serial port OxA9h 1 0 1 0 1 0 0 1 Disabling the serial port OxAAh 1 0 1 0 1 0 1 0 Detecting the presence of the serial port OxABh 1 0 1 0 1 0 1 1 Clearing serial port buffer OxACh 10 1 0 1 1 0 0 Enabling serial port OxADh 1 0 1 0 1 1 0 1 Reserved f
50. L pd Ted nai tulsa 28 3 7 Intel 82801Jx I O Controller Hub ICH10R cccccccccccsescsesestsesssescssscetscecstsceeseeees 28 iv Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Table of Contents 3 7 1 Setlal ATA SUppOort usar eerte sa t er rte eph 29 3 7 2 USB 2 0 SUppOFt nci eer ete ie irt FU ro YE 29 3 8 Network Interface Controller NIC esee enne 30 3 8 1 MAC Address nnnm 30 3 8 2 LAN Connector Ordering al anaes 31 3 9 Integrated Baseboard Management 31 3 9 1 Integrated BMC Embedded LAN 33 3 9 2 RMM3 Advanced Management 33 3 10 DOMAIN POMS eR EDENDI 33 3 11 2 PREX ERR 34 3 12 Integrated Video 4 20 0000000 0000000000000000000000000000000000 34 3 12 1 Video m Rd Rd e ERR 34 9 12 21 Dual Io m 34 3 12 3 Front Panel 35 3 13 OS ee 35 3 13 1 X16 Riser Slot
51. LT D1 G FLT B D FLT D2 H FLT C 72 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Intel Light Guided Diagnostics 8 5 POST Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server board in the rear I O area of the server board by the VGA connector During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the given POST code to the POST code diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process you can use the Diagnostic LEDs to identify the last POST process executed For a complete description of how these LEDs are read and a list of all supported POST codes refer to Appendix A 003052 Figure 26 Rear Panel Diagnostic LEDs Description Description A ID LED E RJ 45 GbE LAN connector B Status LED F RJ 45 Serial port connector C RJ 45 GbE Dual USB connector G DB15 Video D Dual USB connector H Diagnostic LEDs Revision 1 3 73 Intel order number 53971 004 Intel Light Guided Diagnostics Intel Server Board S5500WB TPS 86 Front Panel Support The Intel Server Board S5500WB supports SSI standard front panel boards The front panel support is provided by a SSI compatible 2x12 pin signal conn
52. Log Dedicated persistent storage for system events Asset Inventory Field replaceable unit FRU information Console Redirection Text based console redirection via serial over LAN SMASH CLP Basic Command line SSH interface for basic server management operations Node Manager Power management by using P state C State cycling method Requires PMBus power supply 5 2 4 BMC Advanced Features The Intel Server Board S5500WB product includes support for an upgrade module to support the advanced server management functionality The Remote Management Module 3 supports an 8 MB SPI Flash which connects to the integrated BMC SPI interface This is in addition to the local integrated BMC 8 MB SPI flash connected to the PILOT II IBMC down on the board The total 16 MB of Flash space is required to support advanced management features as defined in the following table The RMM3 advanced management board has a PHY device that which interfaces with the secondary NC SI port out of the Server Engines PILOT II integrated BMC to offer a dedicated management Ethernet port Table 14 Advanced Features Manageability features Description Remote Power on off sensor status system info Embeddedaveppl System Event log OEM customization KVM Redirection high performance multiple concurrent sessions USB 2 0 Media Redirection boot over remote media Security SSL SSH support WS MAN Dedi
53. M1 FAN MEM1R PWM 1 PWM 1 PWM MEM1 PWM MEM 1 Tach 1 Tach 5 Tach 2 Tach 2 amp 6 J8E1 J8J4 J8J3 J9E1 LED Fan Fault CPU1 LED Fan Fault CPU1A LED Fan Fault MEM1 LED_Fan_Fault_MEM1R 76 Intel order number 53971 004 Revision 1 3 Intel Server Board S5500WB TPS Design and Environmental Specifications Table 53 Fan Connector Location amp Detail CPU 2 Memory 2 FAN_CPU2 FAN_CPU2A FAN_MEM2 FAN_MEM2R PWM_CPUO PWM CPUO PWM MEMO PWM MEMO Tach 3 Tach 7 Tach 4 Tach4 amp 8 J3E1 J2J2 J2J1 J1D5 LED Fan Fault CPUO LED Fan Fault CPUOA LED Fan Fault MEMO LED Fan Fault MEMOR CPUO TEMP FRU POWER SUPPLY GPIO SENSORS SGPO STATUS LEDS LM75 AT24C01 FRU NEHALEM mu XA PSM 0XBO FE NML BTN N 90 LED POSTCODE E 10 IRG IOH ICH SMI TTL 02 LED POSTCODE 2 16 DDR3 CPUo THERMAL2 03 LED POSTCODE 3 E 17 DDR3 CPU1 THERMAL2 04 LED POSTCODE 4 3 18 SMB PWR ALERT 05 LED POSTCODE 5 r FRONT PANEL REPEATER 19 THERMALERT 06 LED POSTCODE 6 3 3VSB 33V eou 20 THERMTRIP N 07 LED POSTCODE 7 amp CONN 5 i 21 CPU PROCHOT N LED STATUS GRE PCA9515 23 CATERR N 5 NEHALEM 09 LED STATUS AMBER g 10 LED FAN FAULT CPUOA 11 LED FAULT CPU1A FAULT 0 14 LED DIMM FAULT 2 16 1 gt 18 6 PEHPSMB s
54. Most operating systems support this feature For details see the relevant operating system manuals 3 46 Memory Population Rules You should populate the memory slots of DDR3 channels furthest from the Intel 5500 series processor first Therefore if A1 is empty you cannot populate use A2 Fill Fill Second First Processor Figure 16 Memory Channel Population Revision 1 3 23 Intel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS 3 4 7 Installing and Removing Memory The silkscreen on the board next to CPU1 displays DIMM A2 DIMM A1 DIMM B1 DIMM C1 and next to CPU2 display DIMM 02 DIMM 01 DIMM 1 DIMM F1 starting from the inside of the board DIMM 1 is the blue socket closest to the CPU 1 socket For memory channel A the server board requires DDR3 DIMMs within a channel to be populated starting with the DIMM farthest from the processor The DIMM farthest from the processor per channel is blue on the board 3 4 7 1 Installing DIMMs To install DIMMs follow these steps 1 Turn off the server 2 Disconnect the AC power cord from the server 3 Remove the server s cover and locate the DIMM sockets see Installing Memory Figure 17 Installing Memory 4 Make sure the clips at either end of the DIMM socket s are pushed outward to the open position see letter A in the figure above 5 Holding the DIMM by the edges remove it from its anti static package 6 Positi
55. OOWB TPS Functional Architecture 3 3 Intel Xeon 5500 Series The Intel 5500 series processors are the first generation server workstation processor to implement the following key new technologies Intel QuickPath Memory Controller e Point to point link interface based on the Intel QuickPath Interconnect Intel QPI which was formerly known as the Common System Interface CSI The Intel 5500 series processor is a series of multi core processors based on the 45 nm process technology Processor features vary by SKU and include up to two Intel QPI point to point links capable of up to 6 4 GT s up to 8 MB of shared cache and an integrated memory controller The processor family supports Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions SSE3 and Streaming SIMD Extensions 4 55 4 It also supports the following advanced technologies Execute Disable Bit Intel 64 Technology Enhanced Intel SpeedStep Technology Intel Virtualization Technology Intel VT and Intel Hyper threading 3 3 1 Processor Support The server board supports the following processors or two Intel 5500 series processor s in FC LGA 1366 socket B package with 4 8 GT s 5 86 GT s or 6 4 GT s Intel e Up to 95 W Thermal Design Power TDP e 80 W Processor only supports Intel up to 5 86 GT s and DDR3 at 1067 MHz or lower e Supports Low Voltage LV processors The server board does not support previ
56. RPORATION 53398 0890 or 53398 0871 Signal Name GND 12V Pin 1 2 3 4 5 6 7 8 66 Revision 1 3 Intel order number 53971 004 Intel Server Board S5500WB TPS Intel Light Guided Diagnostics 8 Intel Light Guided Diagnostics The server boards have several onboard diagnostic LEDs to assist in troubleshooting board level issues This section provides a description the location and function of each LED on the server board 81 5 V Standby LED Several server management features of this server board require a 5 V stand by voltage is supplied from the power supply Some of the features and components that require this voltage must be present when the system is Off include the Integrated BMC onboard NICs and optional RMM3 connector with Intel RMM3 installed The LED is located in the lower left corner of the server board and is labeled 5VSB_LED is illuminated when AC power is applied to the platform and 5 V standby voltage is supplied to the server board by the power supply D IU amp 8 6 f E EL _ i 5 Standby i Status LED
57. User Datagram Protocol Universal Host Controller Interface URS Unified Retention System UTC Universal time coordinare Universally Unique Identifier Voltage Identification VRD Voltage Regulator Down Virtualization Technology 16 bit quantity ZIF Zero Insertion Force Revision 1 3 Intel order number 53971 004 Glossary 101 Reference Documents Intel Server Board S5500WB TPS 102 Reference Documents ACPI 3 0 http www acpi info spec htm IPMI 2 0 Data Center Management Interface Specification v1 0 May 1 2008 www intel com go dcmi PCI Bus Power Management Interface Specification 1 1 http Awww pcisig com PCI Express Base Specification Rev 2 0 06 http www pcisig com PCI Express Card Electromechanical Specification Rev 2 0 http www pcisig com PMBus http pmbus org SATA 2 6 http www sata io org SMBIOS 2 4 SSI EEB 3 0 http www ssiforum org USB 1 1 http www usb org USB 2 0 http www usb org Windows Logo SDG 3 0 Inte Dynamic PowerTechnology Node Manager 1 5 External Interface Specification using IPMI 2007 Intel Corporation Node Power and Thermal Management Architecture Specification v1 5 rev 0 79 2007 Intel Corporation Intef Server System Integrated Baseboard Management Controller Core External Product Specification 2007 Intel Corporation Intef Thurley Server Platform Services IPMI Commands Specification 2007 Intel Corporation Intelligent Platform Management
58. WB TPS Server Board Overview Figure 2 Intel Server Board S5500WB SSI Revision 1 3 5 Intel order number E53971 004 Server Board Overview Intel Server Board SSSOOWB TPS 2 2 Server Board Connector and Component Layout A B a a ae o Hr pe 5 9 9 oo i n i bo NN FI ilo J o A 9 MM EB 1 ba LL s 010 EL BB o pm J KK 6 Ba EHK ll s HH jer CC Tikes EB e 9 2 O M FF DD AA Y X N AF003051 Figure 3 Intel Server Board S5500WB Components both SKUs are shown 6 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Se
59. Yoo EGE o A 2 N BE e 2 FB E ru i Till i T mor fmt maor Essen 9 eme AF003114 Figure 22 5 V Standby Status LED Location Revision 1 3 67 Intel order number 53971 004 Intel Light Guided Diagnostics Intel Server Board S5500WB TPS 8 2 Fan Fault LEDs Fan fault LEDs are present for the six fans and are located near each CPU fan header
60. a chipset component 0x22h 0 0 1 0 0 0 1 0 Reading configuration data from memory SPD on FBDIMM 0 23 0 0 1 0 0 0 1 1 Detecting presence of memory 24 1 070 14 0 O Programming timing parameters the memory controller Ox25h 0 0 14 0 0 1 0 1 Configuring memory parameters the memory controller 0 26 00 1 0 0 1 1 O Optimizing memory controller settings 0 27 00 1 0 0 1 1 1 Initializing memory such as ECC init 0x28h 0 0 1 0 1 0 0 O Testing memory OxE4h 4 4 4 olola olo BIOS cannot communicate with DIMM serial channel hardware failure OxE6h 1 1 1 olo 1 1 0 DIMM s failed Memory iBIST Memory Link Training failure OxE8h 1 1 1 0 1 0 0 0 Nomemory available system halted OxE9h 1 1 1 0 1 O 0 1 Unsupported or invalid DIMM configuration system halted OxEAh 1 1 1 0 1 0 1 0 DIMM training sequence failed system halted OxEBh 1 1 1 01 0 1 1 Memory test failed system halted OxECh 1 1 1 0 1 1 O0 0 Unsupported or invalid DIMM configuration system halted OxEDh 1 1 1 0 1 1 O0 1 Unsupported or invalid DIMM configuration system halted OxEBh 1 1 1 0 1 0 1 1 DIMM with corrupted SPD data detected system halted 90 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Appendix A POST Code LED Decoder QuickPath Interconnect OxAOh 101 00 0 JQPI Initialization OxA1h 1 0 1 010 0 0 1 QPlilnitialization OxA
61. ace Controller NIC Network interface support is provided from the onboard Intel 82576 NIC which is a single compact component with two fully integrated GbE Media Access Control MAC and Physical Layer PHY ports The Intel 82576 NIC provides the server board with support for dual LAN ports designed for 10 100 1000 Mbps operation Refer to the Intel 82576 Gigabit Ethernet Controller Datasheet Document 82576 for full details of the NIC feature set The NIC device provides a standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab and is capable of transmitting and receiving data at rates of 1000 Mbps 100 Mbps or 10 Mbps The Intel 82576 NIC is powered off the main standby voltage rail via DC to DC Voltage regulators for efficiency purposes It is on standby power so the BMC can send out of band management traffic over the RMII bus to the network during sleep state S5 The NIC supports the normal RJ 45 LINK Activity speed LEDs as well as the Proset ID function These LEDs are powered from a Standby voltage rail The link activity LED at the right of the connector indicates network connection when on and transmit receive activity when blinking The speed LED at the left of the connector indicates 1000 Mbps operation when amber 100 Mbps operation when green and 10 Mbps when off The following table provides an overview of the LEDs Table 7 NIC Status LED L
62. age and the Revision 1 3 25 Intel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS other channels hold the secondary image of the system memory The integrated memory controller in the Intel 5500 series alternates between both channels for read transactions Under normal circumstances write transactions are issued to both channels Mirroring is only supported between Channels A amp B and Channels D amp E The presence of a DIMM on Channel C or F causes the BIOS to disable Mirroring and revert to the Independent Channel mode Figure 18 Mirroring Memory Configuration 3 4 10 Memory Error LED Each DIMM is allocated an LED that when lit indicates a memory DIMM failure It is the function of the BIOS to identify bad DIMMs during the boot process The BIOS sends a message to the BMC to indicate which DIMM LED needs turn on 3 5 Intel 5500 Chipset IOH The Intel 5500 Chipset component is an I O Hub IOH The Intel 5500 Chipset provides a connection point between various I O components and Intel processors using the Intel QPI interface The Intel 5500 Chipset IOH is capable of interfacing with up to 24 PCI Express lanes which can be configured in various combinations of x4 x8 x16 and limited x2 and x1 devices The Intel 5500 Chipset IOH is responsible for providing a path to the legacy bridge In addition the Intel 5500 Chipset supports a x4 DMI Direct Media Interface link int
63. al I O Module es single and double wide es single and double wide SW RAID LSI SW RAID 0 1 5 10 LSI SW RAID 0 1 5 10 Processor Support 95 W optimized for 80 W 95 W optimized for 80 W Integrated in BMC Integrated in BMC ISM BMC w IPMI 2 0 support w IPMI 2 0 support Power Supply 12 V and 5 VS B PMBus 12 V 5 V 3 3 V 5 VSB PMBus Referenced Chassis Chenbro RM13204 Chassis and Intel Server System SR1690WB Revision 1 3 13 Intel order number E53971 004 Functional Architecture Intel Server Board S5500WB TPS 3 2 Functional Block Diagram p DDR3 22 DDR3 intel DDR3 QuickPath intel Xeon DDR3 inside QuickPath QuickPath 24D SKU Slot 6 is Single x8 ITP Conn h PCIe Gen2 x8 PE 7 8 Slot 6 x16 slot PCle Gen2 4 PE 9 10 Intel 5500 Intel GbE Intel 1 0 E Pole Gent TZ Gen2x4 9 10 Expansion Module GbE gt over A PCleGen2x4 USB Slot 1 SATA x6 USB x1 x1 USB USB x2 Video x2 USB ICH10R 99 OS Front Panel Rear x2 USB _ USB Serial l Rear Panel Port SPI x2 Optical USB x2 Internal Drive Serial FLASH Header AF003058 Figure 9 Intel Server Board S5500WB Functional Block Diagram 14 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSS
64. ant power supplies Non fatal alarm system is likely to fail BIOS Detected 1 In non mirroring mode if the threshold of ten correctable errors is crossed within the window 2 PCI Express uncorrectable link errors Amber Non Fatal Integrated BMC Detected n Critical threshold crossed Voltage temperature power nozzle power gauge and PROCHOT therm Ctrl sensors VRD Hot asserted The minimum number of fans required to cool the system are not present or have failed 70 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Intel Light Guided Diagnostics Fatal alarm system has failed or shut down BIOS Detected DIMM failure when there is one DIMM present and no good memory is present Run time memory uncorrectable error in non redundant mode CPU configuration error for instance processor stepping mismatch Ambet sold on Fatal Integrated BMC Detected 1 CPU IERR signal asserted CPU 1 is missing CPU THERMTRIP No power good power fault Power Unit Redundancy sensor Insufficient resources offset indicates not enough power supplies are present Not ready AC power off 1 The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide the contribution to the system status LED 2 Support for an upper non critical threshold limit is not provided in default SDR configuration However if a user does
65. as LSB Least Significant Bit Figure 33 Diagnostic LED Placement Diagram 88 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Appendix A POST Code LED Decoder In the following example the BIOS sends a value of ACh to the diagnostic LED decoder The LEDs are decoded as follows Table 55 POST Progress Code LED Example Upper Nibble LEDs Lower Nibble LEDs Status Results Upper nibble bits 1010b Ah Lower nibble bits 1100b Ch the two are concatenated as ACh Revision 1 3 89 Intel order number E5397 1 004 Appendix A POST Code LED Decoder Intel Server Board SSSOOWB TPS Table 56 Diagnostic LED POST Code Decoder Diagnostic LED Decoder 1 On 0 Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1 8h 4h 2h 1h LED 7 6 5 H4j 2 1 0 Host Processor Description Power on initialization of the host processor bootstrap 0x10h 0 0 0 1 0 0 0 0 processor Ox11h 0 1 0 0 0 4 Host processor cache initialization including AP 0 12 0 170 0 1 0 Starting application processor initialization Ox13h 0 1 0 0 1 1 SMM initialization Ox14h 0 0 1 0 4 olo Selection of Processor with least features to be used as Boot Strap Processor 0x15h 0 0 0 1 0 1 0 1 Switch AP processor to become the new Boot Strap Processor Chipset 0 21 0 0 1 0 0 0 0 1 Initializing
66. cated NIC Shared NIC Onboard NICs LDAP support Revision 1 3 41 Intel order number 53971 004 Platform Management Features Intel Server Board SSSOOWB TPS 5 3 Management Engine ME 5 3 1 Overview The Intel Server Platform Services SPS is a set of manageability services provided by the firmware executing an embedded ARC controller within the This management controller is also commonly referred to as the Management Engine ME The functionality provided by the SPS firmware is different from Intel Active Management Technology Intel AMT or AT provided by the ME on client platforms Server Platform Services SPS are value added platform management options that enhance the value of Intel platforms and their component ingredients CPUs chipsets and I O components Each service is designed to function independently wherever possible or grouped together with one or more features in flexible combinations to allow OEMs to differentiate platforms 5 3 2 BMC Management Engine Interaction Management Engine Integrated BMC interactions include the following Integrated BMC stores sensor data records for ME owned sensors Integrated BMC participates in ME firmware update Integrated BMC initializes ME owned sensors based on SDRs Integrated BMC receives platform event messages sent by the Integrated BMC notifies ME of POST completion 5 4 Data Center Manageability Interface
67. ce e Provide Access to ICH10R Devices The ME has control of ICH10R platform instrumentation SPS provides a mechanism for the BMC to access this instrumentation through IPMI OEM commands Use of this capability on Intel servers is platform SKU specific e CH10 temperature monitoring 2 0 Proxy SPS offers a means for a BMC without 2 0 interface to use the as a PECI proxy The BMC on Intel servers already has a PECI 2 0 interface so this SPS capability is not used 3 7 Intel 82801 x I O Controller Hub ICH10R The Intel 82801 Jx I O Controller Hub ICH10R provides extensive I O support and supports the following features and specifications PCI Express Base Specification Revision 1 1 support e ACPI Power Management Logic Support Revision 3 0a e Enhanced DMA controller interrupt controller and timer functions e Integrated Serial ATA host controllers with independent DMA operation on up to six ports and AHCI support e USB host interface with support for up to 12 USB ports six UHCI host controllers and two EHCI high speed USB 2 0 host controllers 28 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture e System Management Bus SMBus Specification Version 2 0 with additional support for devices e Low Pin Count LPC interface support Serial Peripheral Interface SPI support 3 7 1 Serial ATA Support The ICH10R has an integra
68. ck panel changes 3 13 4 O Module Connector Mezanine connectors are provided to support the various I O modules both the older Gen 1 I O modules supported by Intel Server Board S5000PAL and newer double wide Gen 2 I O modules supported by the Intel Server Board 5520UR are supported on the Intel Server Board S5500WB The Intel I O Expansion Module is also required to inform the of the Intel I O Expansion Module Bus usage PEWIDTH bit 1 is to be used for this Table 12 Intel I O Expansion Module Bus PEWIDTH Bits Intel 1 0 mu device 36 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Intel 1 0 Expansion Modules 4 Intel I O Expansion Modules The Intel Server Board S5500WB supports a variety of I O Module options using 2x4 PCI Express Gen2 Intel I O Expansion Module connectors on the rear of the server board Each Intel I O Expansion Module connector is 50 pin surface mount 0 8mm pitch header The Intel Server Board S5500WB accommodates both the double wide I O expansion modules and the PCI Express Gen 1 I O modules used the S5000PAL rack server The Legacy modules are e Dual Port GbE I O Module External 4 Port SAS I O Module The new modules consist of e nternal 4 port Intel 82576 GbE Dual Port Intel 10GbE I O Module e Internal 4 port LSI 1064e SAS I O Module e Internal 4 port LSI 1078e SAS I O Module e Infiniband I O E
69. ctor J1D3 for use with SSI compliant third party chassis The following table provides the pin out for this connector Table 32 Front Panel SSI Standard 24 pin Connector Pin out J1E1 Signal Name i Signal Name P3V3 STBY Power LED Anode P3V3 STBY Front Panel Power P5V STBY ID LED Anode FP PWR LED N FP ID LED BUF N P3V3 HDD Activity LED Anode FP LED STATUS GREEN N LED HDD ACTIVITY N FP LED STATUS A MBER N 54 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out Pin Signal Name i Signal Name FP_PWR_BTN_N NIC1_ACT_LED_N GND Power Button GND NIC1_LINK_LED_N BMC RST BTN N SMB SENSOR 3V3STB DATA GND Reset GND SMB SENSOR 3V3STB CLK FP ID BTN N FP CHASSIS INTRU NIC2 ACT LED N FP NMI BTN N NIC2 LINK LED N Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel buttons and LEDs The following sections describe the supported functionality of each control panel feature 7 3 1 Power Button The BIOS supports a front control panel power button Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset It is monitored by the Integrated BMC and does not directly control power on the power supply Power Button Off to On The Integrated BMC monitors the power button and the wake up event signals from the c
70. cy energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product Only peripherals computer input output devices terminals printers etc that comply with FCC Class A or B limits may be attached to this computer product Operation with noncompliant peripherals is likely to result in interference to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception 11 3 2 ICES 00
71. e e Up to 1600x1200 pixel resolution USB interface Code to Host Memory TAG Interrupt Fan Tach 8 aa USB d LPC Master Mese ermal an TAG Master Controller USB 2 0 Td SPI Flash ARM926E S 16K D Cache RTC and Ethernet MAC Crypto and Senora UART 3 12C 6 with RMII Video Tim 2 3 Interface 2 Accelarator DDR II up to DDR II 16 bit 667 MHz Memory gt Controller BMC and KVMS Subsystem GPIO System KCS BT and LUE uere mes interface to Host c Interface Real Time Graphics LPC to SPI Watchdog clock interface Controller Flash Bridge Timer requires external RTC Graphics Super I O Subsystem Subsystem SPI Memory 1x PCI Express 32 Intel order number E53971 004 interface to Host AF002700 Revision 1 3 Intel Server Board SSSOOWB TPS Functional Architecture Figure 19 Integrated BMC Hardware 3 9 1 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10 100 network interfaces These interfaces are not shared with the host system At any time you can enable only one dedicated interface for management traffic The default active interface is the NIC 1 port For these channels you can enable support for IPMl over LAN and DHCP For security reasons embedded LAN channels have the following default settings Address Static All users disabled 3 9 2 RMM3 Advanced Management Board The RMM3 advanced manage
72. e ECC error encountered Major 85A5 DIMM C2 Uncorrectable ECC error encountered Major 85A6 DIMM D1 Uncorrectable ECC error encountered Major 85A7 DIMM_D2 Uncorrectable ECC error encountered Major 85A8 DIMM E1 Uncorrectable ECC error encountered Major 85A9 DIMM E2 Uncorrectable ECC error encountered Major 85AA DIMM F1 Uncorrectable ECC error encountered Major 85AB DIMM F2 Uncorrectable ECC error encountered Major 8604 Chipset Reclaim of non critical variables complete Minor 9000 Unspecified processor component has encountered a non specific error Major 9223 Keyboard component was not detected Minor 9226 Keyboard component encountered a controller error Minor 9243 Mouse component was not detected Minor 9246 Mouse component encountered a controller error Minor 9266 Local Console component encountered a controller error Minor 9268 Local Console component encountered an output error Minor 9269 Local Console component encountered a resource conflict error Minor Mar 92C8 Serial Port component encountered an output error Minor 94C6 LPC component encountered a controller error Minor Revision 1 3 97 Intel order number 53971 004 Appendix B Video POST Code Errors Intel Server Board SSSOOWB TPS Error Code Processor component encountered a high voltage error 501 ATA SMART is disabled DXE boot services driver Not enough memory available to shadow a legacy Minor OxA6A0
73. e can also be forced setting the MGPIOx jumper on the board Boot image verification and boot failure 6 1 7 Serial Interface J6A2 Pins Mode Description 1 2 DCD to DTR Data Carrier Detect 3 4 DSR to DTR Data Set Ready 50 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out 7 Connector Header Locations and Pin out 7 1 Power Connectors Table 22 SSI SKU 24 pin 2x12 Connector J9B1 Pin SignalName__ Pin Signal Name 1 33v 13 3 3V 14 GND 15 5V 16 GND 17 T5V 18 GND 19 20 ODA Table 23 CPU 12V Power 2x4 Connector J5K1 Signal Name GND GND GND Table 24 SSI Power Control J9D1 Pin SignalName_ SMB PWR CLK SMB PWR DAT SMB PWR ALRT GND 3 3V Remote Sense 1 2 3 4 5 Table 25 12 V only 2x4 Connector replaces EPSD12V 2x12 connector J9D2 Revision 1 3 51 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS Pin Signal Name GND GND GND GND 12V 12V 12V 12V Or RAJUIN Table 26 12 V Only Power Control replaces the 1x5 power control J9D1 FOXCONN ELECTRONICS INC HF1107V P1 or TYCO ELECTRONICS CORPORATION 5 104809 6 Si
74. e enabled and used in the Independent Channel mode Adjacent slots on channels A and D do not need matching size and organization However the speed of the channel is configured to the maximum common speed of the DIMMs The single channel mode is established using the independent channel mode by populating DIMM slots from channel A only 3 4 9 Memory RAS The memory RAS offered by the Intel 5500 series processor is performed at channel level for example during mirroring channel B mirrors channel A All DIMM matching requirements are on a slot to slot basis on adjacent channels For example to enable mirroring corresponding slots on channels A and B must have DIMMS of identical parameters If one socket fails the population requirements for RAS the BIOS sets all six channels to the Independent Channel mode One exception to this rule is when all DIMM slots from a socket are empty for example when only DIMM slots A1 B1 and C1 are populated mirroring is possible on the platform 3 4 9 1 Memory Population for Channel Mirroring Mode The mirrored configuration is a redundant image of the memory and can continue to operate despite the presence of sporadic uncorrectable errors Channel mirroring is a RAS feature in which two identical images of memory data are maintained thus providing maximum redundancy On the Intel 5500 series based Intel server boards mirroring is achieved across channels Active channels hold the primary im
75. e following two conditions 1 This device may not cause harmful interference and 2 This device must accept any interference received including interference that may cause undesired operation Manufactured by Intel Corporation EMC Marking Class A Canada CANADA ICES 003 CLASS A CANADA NMB 003 CLASSE A CE Mark Europe BSMI Marking Class A Taiwan LE dE EARE aii EE SI SAR 11 3 Electromagnetic Compatibility Notices 11 3 1 FCC Verification Statement USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Revision 1 3 85 Intel order number E5397 1 004 Regulatory and Certification Information Intel Server Board SSSOOWB TPS For questions related to the EMC performance of this product contact Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 6497 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequen
76. ector The front panel connector supports the following diagnostic LEDs Table 51 Standard Front Panel Functionality LED Color Condition What It Means Power on or SO sleep Power Sleep i 51 sleep Off also sleep S5 modes System ready No alarm System ready but degraded redundancy lost such as power supply or fan failure non critical temp voltage threshold battery failure or predictive PS failure Critical alarm Voltage thermal or power fault CPU1 missing insufficient power unit redundancy resource offset asserted Non Critical failure Critical temp voltage threshold VDR hot asserted min number fans not present or failed AC power off System unplugged AC power on System powered off and in standby no prior degraded non critical critical state HDD access HDD fault Not Supported Not Supported Off No access LAN link no access LAN TIS LAN access Idle LAN link no access LAN access Idle Front panel chassis ID button pressed Identification Unit selected for identification via software No identification Predictive failure rebuild identify Activity LAN 2 Activity 74 Revision 1 3 Intel order number 53971 004 Intel Server Board S5500WB TPS Design and Environmental Specifications 9 Design and Environmental Specifications 9 1 Fan Speed Control Thermal Management Fan speed control supports the following thermal sensors e Discr
77. ed Self Test BIST 8525 DIMM C2 failed Self Test BIST 8526 DIMM D1 failed Self Test BIST 8527 DIMM D2 failed Self Test BIST 8528 DIMM 1 failed Self Test BIST 8529 DIMM E2 failed Self Test BIST 852A DIMM F1 failed Self Test BIST Major 8542 DIMM B1 Disabled Major 8543 DIMM B2 Disabled Major 8544 DIMM C1 Disabled Major 8545 DIMM C2 Disabled Major 8546 DIMM D1 Disabled Major 8547 DIMM D2 Disabled Major 8548 DIMM E1 Disabled Major 8549 DIMM E2 Disabled Major Major Major Major Major Major Major Major YK S 96 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Appendix B Video POST Code Errors Error Code Error Message 8566 DIMM_D1 Component encountered a Serial Presence Detection SPD Response fail error Major 8567 DIMM D2 Component encountered a Serial Presence Detection SPD fail error Major 8568 DIMM E1 Component encountered a Serial Presence Detection SPD fail error Major 8569 DIMM E2 Component encountered a Serial Presence Detection SPD fail error Major 856A DIMM F1 Component encountered a Serial Presence Detection SPD fail error Major 856B DIMM F2 Component encountered a Serial Presence Detection SPD fail error Major Major 85A4 DIMM C1 Uncorrectabl
78. em to automatically power up and immediately power down after the procedure is followed and AC power is re applied If this happens remove the AC power cord again wait 30 seconds and re install the AC power cord Power up the system and proceed to the lt F2 gt BIOS Setup Utility to reset the desired settings 6 1 5 Video Master Table 21 Video Master Jumper Jumper Position Operation Notes Internal connector will override if both connectors are used External connector will override if both connectors are used This jumper determines which video is the primary J6A3 1 2 jumpered Internal video connector is primary but video can come out of external video connector if you connect to it Revision 1 3 49 Intel order number 53971 004 Configuration Jumpers Intel Server Board S5500WB TPS J6A3 2 3 jumpered External video connector is primary but video can come out of internal video connector if you connect to it 6 16 ME Firmware Force Update 7 2 Pins ME Firmware Update Mode 1 2 Disabled Default 2 3 Enabled The ME firmware consists of two operational images and a recovery image During boot the recovery loader is started first and it tries to load the active firmware image by running the loader of this image If it fails to boot it tries to boot the other operational image If both fail the recovery loader starts in recovery mode The recovery mod
79. emory mirroring takes place and system loses memory redundancy This is not covered by 2 PCI Express correctable link errors Integrated BMC detected 1 Redundancy loss such as a power supply or fan Applies only if the associated platform subsystem has redundancy capabilities CPU disabled if there are two CPUs and CPU is disabled Fan alarm Fan failure Number of operational fans should be more than minimum number needed to cool the system Non critical threshold crossed Temperature voltage power nozzle power gauge and PROCHOT2 Therm Ctrl sensors Battery failure Predictive failure when the system has redundant power supplies Non fatal alarm system is likely to fail BIOS Detected 1 2 In non mirroring mode if the threshold of ten correctable errors is crossed within the window PCI Express uncorrectable link errors Integrated BMC Detected Critical threshold crossed Voltage temperature power nozzle power gauge and PROCHOT therm Ctrl sensors VRD Hot asserted Minimum number of fans to cool the system is not present or have failed 57 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS System Status Amber Solid on Fatal Fatal alarm system has failed or shut down BIOS Detected DIMM failure when there is one DIMM present and no good memory is present Run time memory uncor
80. enable this threshold in the SDR then the system status LED should behave as described Revision 1 3 71 Intel order number 53971 004 Intel Light Guided Diagnostics Intel Server Board S5500WB TPS 8 4 DIMM Fault LEDs Each DIMM slot has a DIMM Fault LED near the DIMM slot en E J 5 BIB H _ re am 30 HOR o e e e e ACS E E e e e kaa Ble o Ed Bo AF003117 Figure 25 DIMM Fault LEDs Locations A FLT F E FLT A2 B FLT E F FLT A1 C F
81. er OxBBh 1 0 1 1 1 0 1 1 Memory Initialization of Integrated Memory Controller OxBCh 1 0 1 1 1 1 0 0 Memory Initialization of Integrated Memory Controller OxBDh 1 0 1 1 1 1 0 1 Memory Initialization of Integrated Memory Controller OxBEh 1 0 1 1 1 1 1 0 Memory Initialization of Integrated Memory Controller OxBFh 1 0 1 1 1 1 1 1 Memory Initialization of Integrated Memory Controller PCI Bus 0x50h 0 1 0 1 0 0 O 0 Enumerating PCI buses 0x51h 0 1 0 1 0 0 0 1 Allocating resources to PCI buses 0x52h 0 1 0 1 0 0 1 0 J Hot Plug PCI controller initialization 0x53h 0 1 0 1 0 0 1 1 Reserved for PCI bus 0x54h 0 1 0 1 0 1 0 0 for PCI bus 0 55 0 1 0 110 1 0 1 Reserved for PCI bus Revision 1 3 91 Intel order number 53971 004 Appendix A POST Code LED Decoder Intel Server Board SSSOOWB TPS USB 0x56h 0 1 0 1 0 1 1 0 Initializing USB host controllers 0 57 0 1 0 1 0 1 1 1 Detecting USB devices 0x58h 0 1 0 1 1 0 0 O Resetting USB bus 0x59h 0 1 0 1 1 0 0 1 Reserved for USB devices ATA ATAPI SATA O0x5Ah 0 1 0 1 1 O 1 0 Resetting SATA bus and all devices Ox5Bh 0 1 0 1 1 0 1 1 Detecting the presence of ATA device Ox5Ch 0 1 0 1 1 1 0 0 Enable SMART if supported by ATA device Ox5Dh 0 1 0 1 1 1 0 1 Reserved for ATA SMBUS Ox5Eh 0 1 0 1 1 1 1 0 Resetting SMBUS Ox5Fh 0 1 0 1 1 1 1 1 Reserved for SMBUS Controller Hub 0x61h 0 1 1 0 0 0 0 1 Initializing
82. erface for the legacy bridge and interfaces with other devices through SMBus Controller Link and RMII Reduced Media Independent Interface manageability interfaces The Intel 5500 Chipset supports the following features and technologies e Intel QuickPath Interconnect Intel e PCI Express Gen2 e Intel Virtualization Technology Intel VT for Directed I O 2 Intel VT D2 26 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture e Manageability Engine ME subsystem 3 5 1 IOH24D PCI Express PCI Express Gen1 and Gen2 are dual simplex point to point serial differential low voltage interconnects The signaling bit rate is 2 5 Gb s one direction per lane for Gen1 and 5 0 Gb s one direction per lane for Gen2 Each port consists of a transmitter and receiver pair A link between the ports of two devices is a collection of lanes x1 x2 x4 x8 x16 and so forth All lanes within a port must transmit data using the same frequency The following table lists the usage of the OH24D PCI Express bus segments Table 6 IOH24D PCI Express Bus Segments PCI Bus Segment Width PCI 1 0 Card Slots Bem uU 0 E om Gb s PCI Edd x4 PCI Express Gen1 ouhbidge to the ICH10R PE1 PE2 Gb s PCI Express x4 PCI Express Gen1 throughput to an onboard NIC Intel 5500 Chipset Gen1 IOH PCI Express PE3 20 Gb S PCI Express X4 PCI Express Gen2 thro
83. erform an AC power cycle for the changes to take effect Revision 1 3 27 Intel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS The Intel 5500 Chipset IOH supports DMA remapping from inbound PCI Express memory Guest Physical Address GPA to Host Physical Address HPA PCI Express devices are directly assigned to a virtual machine leading to a robust and efficient virtualization 3 6 Management Engine The Management Engine ME is an embedded ARC controller within the The performs manageability functions called Intel Server Platform Services SPS for the discrete Baseboard Management Controller BMC The functionality provided by the SPS firmware is different from Intel Active Management Technology Intel AMT or AT provided by the ME on client platforms Server Platform Services are value added platform management options that enhance the value of Intel platforms and their component ingredients CPUs chipsets and I O components Each service is designed to function independently wherever possible or grouped together with one or more features in flexible combinations to allow OEMs Original Equipment Manufacturers to differentiate platforms The following is a high level view of the Intel Server Board S5500WB SPS functions e Node Management Features e NPTM Policy Manager e Power Supply Monitoring Service e Inlet Temperature Monitoring Service e CPU Power Limiting Servi
84. ete board level digital thermal sensor TMP75 e Front panel Temp Sensor if present e CPU PECI DTS DDR3 RDIMM TSOD Eight front system fan headers for four individual thermal zones Zone 4 2 fans responds to memory2 and CPU2 temperatures Zone 3 CPU2 and 2 fans responds to CPU2 and IOH temperatures Zone 2 CPU1 and fans responds to CPU1 and temperatures Zone 1 1 fans responds to memory1 and CPU1 temperatures Memory2 ie ZONE 4 ZONE 3 ZONE 2 7 ZONE 1 Memory1 Figure 27 Thermal Zones Revision 1 3 75 Intel order number E5397 1 004 Design and Environmental Specifications Intel Server Board SSSOOWB TPS The following tables show a basic location of the fan connectors on the board The first line is the silk screen name of the connector the second is the PWM signal name the third is the Tach and the forth is the reference description The last is the signal name associated with the fault LED signal 1 Located near front Combo header Redundant Fan CPU 1a Fan CPU 1 Fan Active H S Located near front Combo header Mem 2 Redundant Fan DOOOOOOUDI Double Rotor 3 4 Wire Fan headers CPU_2a Fan CPU_2 Fan Active H S Figure 28 Location of Fan Connectors Table 52 Fan Connector Location amp Detail Double Rotor 1 CPU 1 Memory 1 FAN CPU1 FAN CPU1A FAN ME
85. g Algorithm Higher Security Milliseconds Memory Type Range Register Multiplexor Network Interface Controller Nonmaskable Interrupt Output Buffer Original Equipment Manufacturer Unit of electrical resistance Platform Environment Control Interface Platform Event Filtering Platform Event Paging Intel Server Board SSSOOWB TPS Platform Information Area This feature configures the firmware for the platform hardware Programmable Logic Device Platform Management Interrupt Power On Self Test Intel order number E5397 1 004 Revision 1 3 Intel Server Board SSSOOWB TPS Definition Power Supply Management Interface PWM Pulse Width Modulation QP QuickPath Interconnect RAM Random Access Memory Reliability Availability Serviceability Usability and Manageability Reduced Instruction Set Computing ROM Read Only Memory RTC Real Time Clock Component of ICH peripheral chip on the server board RMM3 Remote Management Module 3 D Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read Only Memory 2 2 SEL System Event Log SIO Server Input Output System Management BUS SMI Server Management Interrupt SMI is the highest priority nonmaskable interrupt Server Management Mode SMS Server Management Software Simple Network Management Protocol TBD To Be Determined Thermal Design Power TIM Thermal Interface Material Universal Asynchronous Receiver Transmitter UDP
86. gnal Name SMB PWR CLK SMB PWR DAT SMB PWR ALRT Remote Sense Return 12V Remote Sense PS ON 5V S B G2 NO Table 27 Peripheral Power Only for 12 V only SKU J8K2 IPN C22293 003 MOLEX CONNECTOR CORPORATION 43045 0627 Note This connector is for output power only The 5V is limited to 6 5A and the 3 3V is limited to 2A Pin 4 is a 3 3V output Power Good signal if needed for a backplane Pin SignalName 1 5V 2 5V 3 GND 4 Powergood 5 3 3V 6 GND 52 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out 7 2 System Management Headers 7 2 1 Intel Remote Management Module Intel RMM3 Connector A 34 pin Intel RMM 3 connector J5B1 is included on the server board to support the optional Intel Remote Management Module 3 There is no support for third party management cards on this server board Note This connector is not compatible with the Intel Remote Management Module Intel or the Intel Remote Management Module 2 Intel RMM2 Table 28 Intel RMM3 Connector Pin out J5B1 SignalName Pin 3V3 AUX RMII MDIO Signal Name RXDO RX DV RMII REF CLK GND KEY pin removed GND 20 RMII TXDO GND 22 TXD1 3V3 AUX SPI CS N 3V3 AUX NC spare 3V3 AUX SPI DO SPI CLK 7 2
87. hipset A transition from either source results in the Integrated BMC starting the power up sequence Since the processors are not executing the BIOS does not participate in this sequence The hardware receives the power good and reset signals from the Integrated BMC and then transitions to an ON state Power Button On to Off operating system absent The System Control Interrupt SCI is masked The BIOS sets up the power button event to generate an SMI and checks the power button status bit in the ACPI hardware registers when an SMI occurs If the status bit is set the BIOS sets the ACPI power state of the machine in the chipset to the OFF state The Integrated BMC monitors power state signals from the chipset and de asserts PS PWR ON to the power supply As a safety mechanism if the BIOS fails to service the request the Integrated BMC automatically powers off the system in four to five seconds Power Button On to Off operating system present If an ACPI operating system is running pressing the power button switch generates a request via SCI to the operating system to shut down the system The operating system retains control of the system and the operating system policy determines the sleep state into which the system transitions if any Otherwise the BIOS turns off the system 7 3 2 Reset Button The platform supports a front control panel reset button Pressing the reset button initiates a request forwarded by the Integrated
88. ication and Product Certification No On KCC certificate Obtain certificate from local Intel representative Name of Certification Recipient Intel Corporation Date of Manufacturer Refer to date code on product Manufacturer Nation Intel Corporation Refer to country of origin marked on product LM Bo Revision 1 3 87 Intel order number 53971 004 Appendix A POST Code LED Decoder Intel Server Board SSSOOWB TPS Appendix A POST Code LED Decoder During the system boot process the BIOS executes several platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board To assist in troubleshooting a system hang during the POST process the diagnostic LEDs can be used to identify the last POST process to be executed Each POST code is represented by the eight amber diagnostic LEDs The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by diagnostic LEDs 4 5 6 and 7 The lower nibble bits are represented by diagnostics LEDs 0 1 2 and 3 If the bit is set in the upper and lower nibbles then the corresponding LED is lit If the bit is clear then the corresponding LED is off The diagnostic LED 7 is labeled as Most Significant Bit and the diagnostic LED 0 is labeled
89. ified Retention System and Unified Backplate Assembly 80 Revision 1 3 ix Intel order number 53971 004 List of Figures Intel Server Board SSSOOWB TPS Figure 32 Power Distribution Diagram eeeeeeeeseseeeeeeseeeee 82 Figure 33 Diagnostic LED Placement Diagram n 88 X Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS List of Tables List of Tables Table 1 Intel Server Board S5500WB Feature Set cccccecceescesesccesescescscesstseessstessssenseeeneaee 2 Table 2 Intel Server Board S5500WB System 7 Table 3 Intel Server Board S5500WB Features sse 13 Table 4 Mixed Processor Configurations 2 20000 16 Table 5 DIMM Nomenclature 22 Table 6 IOH24D PCI Express Bus Segment c c eeeecceeeedeeeneeneeeeeeesneseeueneeneeseeseneseeneeee 27 Table 7 NIC Status rr e nie sets aeass sends ERU SER XR ERR ERR Re e denies 30 82 RED Cu IR 33 Table 9 Supported Video Modes 0022 220 000 000000 rennes 34 Table 10 Dual Video
90. in features related to the power on off control and the reset logic Revision 1 3 83 Intel order number 53971 004 Regulatory and Certification Information Intel Server Board SSSOOWB TPS 11 Regulatory and Certification Information 11 1 Product Regulation Requirements Intended Application This product was evaluated as Information Technology Equipment ITE which may be installed in offices schools computer rooms and similar commercial type locations The suitability of this product for other product categories and environments Such as medical industrial telecommunications NEBS residential alarm systems test equipment other than an ITE application may require further evaluation This is an FCC Class A device Integration of it into a Class B chassis does not result in a Class B device 11 1 1 Product Safety Compliance The Intel Server Board S5520UR complies with the following safety requirements UL60950 CSA 60950 USA Canada EN60950 Europe EC60950 International CB Certificate amp Report IEC60950 report to include all country national deviations GOST R 50377 92 Listed on one System Certification Russia Belarus Certification Listed on System Certification Belarus Low Voltage Directive 73 23 EEE Europe Certification Argentina 11 1 2 Product EMC Compliance Class A Compliance FCC ICES 003 Emissions USA Canada Verification CISPR 22 Emis
91. it is implemented in the LIBIPMI library on both host and BMC sides to transfer large blocks of data up to 32 K much faster than KCS can IPMI commands are embedded in data written read to a virtual CD ROM device The embedded server management firmware stack is based on a core stack from American Megatrends Incorporated AMI The stack runs on an embedded version of the Linux operating system and provides support for current industry standard management interfaces IPMI 2 0 and emerging industry standard advanced management interfaces SMASH CLP and WS MAN The stack also includes support for keyboard video mouse KVM and USB media redirection The server management subsystem provides remote connectivity through a single GbE NIC with NC SI support RMII NPTM support is required you must use the ME function in the to accomplish this 40 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS 5 2 3 BMC Basic Features Platform Management Features Feature Description IPMI 2 0 Compliance to IPMI 2 0 specification Remote Management Out of band access via either LAN or serial port for numerous features Hardware Monitor Monitor of fans voltages temperatures chassis intrusions memory errors power supplies hard drives and so forth Event Management System event filtering Event Alerting System events delivered via SNMP traps or email System Event
92. k edge of the board J8A2 J9A1 The pin out for NIC connectors are identical and are defined in the following table Table 40 RJ 45 10 100 1000 NIC Connector Pin out J8A2 J9A1 7 5 12 02 05 10 14 i 62 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out 7 4 4 SATA Connectors The server board provides up to six SATA SAS connectors SATA 0 J9B2 SATA 1 J9B3 SATA 2 J9C1 e SATA 3 J9C2 SATA 4 J9B5 e SATA 5 J9B4 The pin configuration for each connector is identical and defined in the following table Table 41 SATA Connectors Pin SignaName escription GND Ground SATA TX P Positive side of transmit differential pair SATA TX N Negative side of transmit differential pair Ground GND SATA RX N Negative side of receive differential pair SATA RX P Positive side of receive differential pair GND Ground 7 4 5 Intel 1 0 Expansion Module Connector The server board provides 2x internal 50 pin Intel I O Expansion Module style connector J2B1 J3B1 to accommodate proprietary form factor Intel I O Expansion Modules which expand the I O capabilities of the server board without sacrificing an add in slot from the riser cards There are multiple Intel I O Expansion Modules for use on this server board For more information on the supported Intel I O Expansion Mod
93. le Connector 0 63 vi Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS 7 4 6 Serial Port 7 4 7 USB Connectors 7 5 Fan Headers 8 Intel Light Guided Diagnostics 8 1 5v otandby LED oot 8 2 Fan Fault LEDS 8 3 System Status eee eh ee 8 4 DIMM Fault LEDS ineei oes nets 8 5 POST Code Diagnostic LEDs 8 6 Front Panel 9 Design and Environmental Specifications 9 1 Fan Speed Control Thermal Management 9 2 Thermal Sensors 9 2 1 Processor Temperature Sensor 9 2 2 Memory Temperature 9 2 3 Board Temperature 9 2 4 Thermals Sensor Placement 9 3 9 3 1 Unified Retention System 9 4 EITOIS idiot eet nr 9 4 1 PROCHOTH acht qute hin hes 942 JHEBRMTRIPS aote 943 MCATERRE 10 Power Subsystem
94. lected on BIOS menu for SATA controller e Intel Embedded Server RAID Technology Il Option ROM e Intel Embedded Server RAID Technology II drivers most recent revision e Atleast two SATA hard disk drives 3 7 1 2 Intel Embedded Server RAID Technology Option ROM The Intel Embedded Server RAID Technology II for SATA Option ROM provides a pre operating system user interface for the Intel Embedded Server RAID Technology II implementation and provides the ability to use an Intel Embedded Server RAID Technology 1 volume as a boot disk as well as to detect any faults in the Intel Embedded Server RAID Technology II volume s 3 7 2 USB 2 0 Support The USB controller functionality integrated into ICH10R provides the server board with an interface for up to 12 USB 2 0 ports All ports are high speed full speed and low speed capable e Four external connectors are located on the back edge of the server board Revision 1 3 29 Intel order number E5397 1 004 Functional Architecture Intel Server Board SSSOOWB TPS e Two internal 2x5 headers are provided capable of supporting two optional USB 2 0 ports each typically one header supports Front panel USB and one supports an internal third party management card e One internal low profile 2x5 header is provided e One Internal Type A USB vertical connector is provided for attaching standard peripherals e The BMC consumes 2 ports for a total of 12 Ports 3 8 Network Interf
95. lopment and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Revision 1 3 1 Intel order number E53971 004 Server Board Overview Intel Server Board SSSOOWB TPS 2 Server Board Overview The Intel Server Board S5500WB is a monolithic printed circuit board PCB with features designed to support the Internet Portal Data Center markets The following table provides a high level product feature list Table 1 Intel Server Board S5500WB Feature Set Feature Processors Memory Chipset Control Support for one or two Intel Xeon Processor 5500 series processors FC LGA 1366 Socket B package with up to 95 W Thermal Design Power TDP Supports future processor compatibility guidelines 4 8 GT s 5 86 GT s and 6 4 GT s Intel QuickPath Interconnect Intel Meets EVRD11 1 Support for 800 1066 1333 MT s ECC registered RDIMM or unbuffered U
96. ment board serves two purposes The first is to give the customer the option to add a dedicated management 100 Mbit LAN interface to the product The second is to give additional flash space enabling the Advanced Management functions to support WS MAN and CIMOM The RMM3 comes with a third 10 100GbE NIC that connects to the board RMM3 management traffic can use the third NIC or NIC 1 Table 8 RMM3 Features Manageability features Description Remote Power on off sensor status system info System Event log and OEM customization Embedded Web U KVM Redirection High performance and multiple concurrent sessions USB 2 0 Media Redirection Boot over remote media Security SSL SSH support WS MAN Dedicated NIC Shared NIC Onboard NICs LDAP Support 3 10 Serial Ports The server board provides two serial ports an external RJ 45 serial port and an internal serial header The rear RJ 45 serial A port is a fully functional serial port that can support any standard serial device The serial B port is an optional port that is accessed through a 9 pin internal DH 10 header You can use a standard DH 10 to DB9 cable to direct serial A port to the rear of a chassis Appendix A defines the serial B interface Revision 1 3 33 Intel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS 3 11 Wake up Control Wake from 51 is supported on LAN USB Serial port and PCI Expre
97. message displays at the end of the process once the flash update succeeds 7 Power OFF the system and revert the recovery jumper position to normal operation 8 Power ON the system 9 Do NOT interrupt the BIOS POST during the first boot 48 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Configuration Jumpers 6 1 4 Reset BIOS Configuration 1 4 This jumper used to be the CMOS Clear jumper Since the previous generation the BIOS has moved CMOS data to the NVRAM region of the BIOS flash The BIOS checks during boot to determine if the data in the NVRAM needs to be set to default Table 20 Reset BIOS Jumper Jumper Position Mode of Operation Normal ICHIOR RTCRST is pulled HIGH Default position 2 3 Reset BIOS ICH10R RTCRST pin is pulled LOW Configuration 6 1 4 1 Clearing the CMOS 1 Power down server Do not unplug the power cord 2 Open the server chassis For instructions see your server chassis documentation 3 Move jumper J1B4 from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait five seconds Remove AC power Move the jumper back to default position covering pins 1 and 2 Close the server chassis Power up the server The CMOS is now cleared and you can reset it by going into the BIOS setup Note Removing AC Power before performing the CMOS Clear operation causes the syst
98. nk has Thermal Interface Material TIM located on the bottom of it Use caution when you unpack the heatsink so you do not damage the TIM To install the heatsink follow these steps 1 Remove the protective film on the TIM if present 2 Orient the heatsink over the processor as shown in Figure 15 The heatsink fins must be positioned as shown to provide correct airflow through the system 3 Set the heatsink over the processor lining up the four captive screws with the four posts surrounding the processor 4 Loosely screw in the captive screws on the heatsink corners in a diagonal manner according to the numbers shown in as follows a Starting with the screw at location 1 engage the screw threads by giving it two rotations in the clockwise direction and stop IMPORTANT Do not fully tighten b Proceed to the screw at location 2 and engage the screw threads by giving it two rotations and stop c Engage screws at locations 3 and 4 by giving each screw two rotations and then stop d Repeat steps 4a through 4c by giving each screw two rotations each time until all screws are lightly tightened up to a maximum of 8 inch Ibs torque Revision 1 3 19 Intel order number E5397 1 004 Functional Architecture Intel Server Board SSSOOWB TPS Removing the Heatsink Installing the Heatsink Figure 14 Installing Removing Heatsink 3 3 3 3 Removing the Processor Heatsink To remove the heatsink follow these steps 1 Loosen the fo
99. oller is disabled when an add in video card is detected In the dual mode onboard video enabled dual monitor video enabled the onboard video controller is enabled and is the primary video device The external video card is allocated resources and is considered the secondary video device The BIOS Setup utility provides options to configure the feature as follows 34 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture Table 10 Dual Video Options Onboard Video Enabled Disabled Dual Monitor Video Enabled Shaded if onboard video is set to Disabled Disabled 3 12 3 Front Panel Video The Intel Server Board 55500 provides a mechanism to support video to the front panel via the use of an internal header When a monitor is plugged into the front panel video connector the rear panel video stream is disconnected There is a jumper option to change this default action When the internal header is used by a third party Management card to do KVM over LAN and then when a monitor is plugged into the rear panel video connector the video stream to the internal header is cut off 3 13 1 0 Slots 3 13 1 X16 Riser Slot Definition Slot 6 was defined to support riser cards Slot 6 has a x16 physical connector with a PCI Express Gen II x8 electrical interface Two clocks are provided so the bus can be bifurcated into two x4 connectors Because of CPU placement a 1U system support
100. on refer to the I O modules in the Intel I O Expansion Modules Hardware Specification 38 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Platform Management Features 5 Platform Management Features This section explains BIOS and firmware FW requirements that drive specific hardware implementations of the platform To a large extent this is background information 5 1 BIOS Feature Overview The Intel Server Board S5500WB product uses the AMI Aptio v3 x code base 5 1 1 EFI Support The platform BIOS is compiled to support the 64 bit EFI environment natively This allows operating systems that EFl aware to take advantage of the EFI boot process in a native 64 bit environment It is expected this will reduce the time required to boot the platform to those operating systems Additionally any utilities that make use of the EFI environment provided by the platform BIOS need to support either the native 64 bit environment or make use of the EFI byte code EBC Of course to maintain compatibility with legacy operating environments a legacy boot option is provided 5 1 2 Intel Rapid Boot Toolkit The BIOS supports the Intel Rapid Boot Toolkit on this platform The toolkit allows users to develop payloads that may co exist with the platform BIOS in the Flash component attached to the south bridge The BIOS supports boots to the user defined payload when this mechanism is enabled To enable a
101. on are captive to the heatsink and only require a Philips screwdriver to attach to the unified backplate assembly See the following figure for the stacking order of the URS components The ILM and unified backplate are removable allowing for the use of non Intel heatsink retention solutions Screw y W DUI E Compression Spring TUM 4 IM lt Retention Cup I lt dd _ HA QI NN UC Heat Sink i IU V Retaining Ring Motherboard Thermal Interface Material TIM ILM and Socket ILM Attach Studs Unified Backplate Heat Sink 3 Attach Studs N 8 i lt gt o Figure 31 Unified Retention System and Unified Backplate Assembly AF003063 80 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Design and Environmental Specifications 9 4 Errors This section outlines how errors are routed in the hardware to ensure appropriate FW action logging fan control system management and so forth is taken when an event occurs 9 4 1 PROCHOT PROCHOT is a bi directional signal The CPU toggles PROCHOT when it goes into throttling mode The duty cycle of PROCHOT toggling indicates the amount of throttling initiated by the CPU FW does not monitor PROCHOT to determine CPU throttling percentage Instead it obtains outbound
102. on the DIMM above the socket Align the two small notches in the bottom edge of the DIMM with the keys in the socket letter B in Figure 16 7 Insert the bottom edge of the DIMM into the socket letter C in Figure 16 8 When the DIMM is inserted push down on the top edge of the DIMM until the retaining clips snap into place letter D in Figure 16 Make sure the clips are firmly in place letter E in Figure 16 9 Replace the server s cover and reconnect the AC power cord 24 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture 3 4 7 2 Removing DIMMs To remove a DIMM follow these steps 1 Turn off all peripheral devices connected to the server 2 Turn off the server 3 Remove the AC power cord from the server 4 Remove the server s cover 5 Gently spread the retaining clips at each end of the socket The DIMM lifts from the socket 6 Holding the DIMM by the edges lift it from the socket and store it in an anti static package 7 Reinstall and reconnect any parts you removed or disconnected to reach the DIMM sockets 8 Replace the server s cover and reconnect the AC power cord 348 Channel Independent Mode In the Independent Channel mode you can populate multiple channels in any order for example you can populate channels B and C while channel A is empty Also DIMMs on adjacent channels do not need to have identical parameters Therefore all DIMMs ar
103. ontain the following files under the root directory 1 FVMAIN FV 2 UEFI iFlash32 2 6 Build 9 3 4 Startup nsh update accordingly to use proper Rec CAP file The BIOS starts the recovery process by first loading and booting to the recovery image file FVMAIN FV on the root directory of the recovery media SATA CD or USB disk This process takes place before any video or console is available Once the system boots to this recovery image file FVMAIN FV it boots automatically into the EFI Shell to invoke the Startup nsh script and start the flash update application IFlash32 efi IFlash32 efi requires the supporting BIOS Capsule image file Rec CAP After the update is complete a message displays stating the BIOS has been updated successfully This indicates the recovery process is finished The user should then switch the recovery jumper back to normal operation and restart the system by performing a power cycle The following steps demonstrate this recovery process 1 Power OFF the system 2 Insert recovery media 3 Switch the recovery jumper Details regarding the jumper ID and location can be obtained from the Board EPS for that Platform 4 Power ON the system 5 The BIOS POST screen will appear displaying the progress and the system automatically boots to the EFI SHELL 6 The Startup nsh file executes and initiates the flash update IFlash32 efi with a new capsule file Rec CAP The regular IFlash
104. or serial port 92 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Appendix A POST Code LED Decoder Fixed Media OxBOh 1 0 1 1 0 0 0 0 Resetting fixed media device OxB1h 1 0 1 1 0 0 0 1 Disabling fixed media device OxB2h 1 0 4 1 olol4 0 Detecting presence of a fixed media device SATA hard drive detection and so forth OxB3h 1 0 1 1 0 0 1 1 Enabling configuring a fixed media device OxB4h 1 0 1 1 0 1 0 0 Reserved for fixed media Removable Media OxB8h 1 0 1 1 1 0 0 0 Resetting removable media device OxB9h 1 0 1 1 1 0 0 1 Disabling removable media device Detecting presence of a removable media device SAT OBAh 1 0 1 1 4 0 0 CDROM detection and so forth OxBCh 1 0 1 1 1 1 0 0 Enabling configuring a removable media device OxBDh 1 0 1 1 1 1 O 1 Reserved for removable media device Boot Device Selection BDS OxDO 1 1 0 1 0 0 0 O Entered the Boot Device Selection phase BDS OxD1 1 1 0 1 O 0 0 1 Return to last good boot device OxD2 1 1 0 1 0 0 1 0 Setup boot device selection policy OxD3 1 1 0 1 0 0 1 1 Connect boot device controller OxD4 1 1 0 1 0 1 0 0 Attempt flash update boot mode OxD5 1 1 0 1 0 1 0 1 Transfer control to EFI boot OxD6 1 1 0 1 0 1 1 O Trying to boot device selection OxDF 1 1 0 1 1 1 1 1 Reserved for boot device selection Pre EFI Initialization PEI Core OxEOh 1 1 1 0 0 0 0 0 Entered Pre EFI Initialization phase PEI OxE1h
105. ors The Intel Server Board S5500WB has two PCI Express slots The pin outs for the slots are shown in the following tables Connector Header Locations and Pin out Table 36 Slot 6 Riser Connector J4B1 Pin Pin Pin Pin Side Side Side Side B PCI Express Signal PCI Express Signal A B PCI Express Signal PCI Express Signal A 1 12V PRSNT1 1 41 6 GND 41 2 12V 12V 2 42 PETxN6 GND 42 3 RSVD 12V 3 43 GND PERxP6 43 4 GND GND 4 44 GND PERxN6 44 5 SMCLK JTAG2 5 45 PETxP7 GND 45 6 SMDATA JTAG3 6 46 PETxN7 GND 46 7 GND JTAG4 7 47 GND PERxP7 47 8 3 3V JTAG5 8 48 PRSNT2 PERxN7 48 9 JTAG1 3 3V 9 49 GND GND 49 10 3 3VAUX 3 3V 10 50 PETxP8 RSVD 50 11 WAKE PERST 11 51 PETxN8 GND 51 KEY KEY KEY KEY 52 GND PERxP8 52 KEY KEY KEY KEY 53 GND PERxN8 53 12 RSVD GND 12 5A PETxP9 GND 54 13 GND REFCLK 13 55 9 GND 55 14 PETxPO REFCLK 14 56 GND PERxP9 56 15 PETxNO GND 15 57 GND 9 57 16 GND PERxPO 16 58 PETxP10 GND 58 17 PRSNT2 PERxNO 17 59 10 GND 59 18 GND GND 18 60 GND PERxP10 60 19 1 RSVD 19 61 GND PERXN10 61 20 1 GND 20 62 PETxP11 GND 62 21 GND PERxP1 21 63 PETxN11 GND 63 22 GND PERxN1 22 64 GND PERxP11 64 23 PETxP2 GND 23 65 GND PERxN11 65 24 PETxN2 GND 24 66 PETxP12 GND 66 25 GND PERxP2 25 67 PETxN12 GND 67 26 GND PERxN2 26 68 GND PERxP12 68 27 PETxP3
106. ous generations of the Intel Xeon Processors 3 3 2 Processor Population Rules For optimum performance when two processors are installed both must be the identical revision and have the same core voltage and Intel QPI core speed When only one processor is installed it must be in the socket labeled CPU1 The other socket must be empty You must populate processors in sequential order Therefore you must populate processor socket 1 CPU1 before processor socket 2 CPU2 When a single processor is installed no terminator is required in the second processor socket 3 3 2 1 Mixed Processor Configurations The following table describes mixed processor conditions and recommended actions for all Intel server boards and systems that use the Intel 5500 Chipset The errors fall into one of the following two categories e Fatal If the system can boot it goes directly to the error manager regardless of whether the Post Error Pause setup option is enabled or disabled Revision 1 3 15 Intel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS Major If the Post Error Pause setup option is enabled the system goes directly to the error manager Otherwise the system continues to boot and no prompt is given for the error The error is logged to the error manager Processor family not identical Processor cache not identical Processor frequency speed not identical Processor microcode missing
107. r slot supporting both full height and low profile 1U and 2U MD2 PCI Express x16 riser cards PCI gen2 Express x8 w x16 connector One riser slot supporting PCI Express x8 riser cards PCI gen2 Express x4 w x8 connector Two Intel Expansion Module card connectors supporting double and single wide I O modules Onboard ServerEngines LLC Pilot Il Controller Matrox G200 2D Video Graphics controller Uses 8 MB of the BMC 32 MB DDR2 Memory Hard Drive Support for six ICH10R SATA II ports pee loners swe Sem eae OOOO Server Management Onboard ServerEngines LLC Pilot II Controller Integrated Baseboard Management Controller Integrated BMC IPMI 2 0 compliant Basic e BMC Controller ARC 926E S microcontroller e Super IO Serial Port logic legacy interfaces LPC interface Port80 e Hardware Monitoring Fan speed control and voltage monitoring Advanced e Video and USB compression and redirection NC SI port a high speed sideband management interface e Integrated Super I O on LPC interface Revision 1 3 3 Intel order number E5397 1 004 Server Board Overview Intel Server Board SSSOOWB TPS 2 1 Intel Server Board SSSOOWB Server Board The Intel Server Board S5500WB has two board SKUs SSI compliant and 12 V only SKU The board layouts of the SKUs are shown E ULECECE 330230333 Figure 1 Intel Server Board S5500WB 12V 4 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOO
108. rectable error in non redundant mode CPU configuration error for instance processor stepping mismatch Integrated BMC Detected 1 CPU CATERR signal asserted CPU 1 is missing CPU THERMTRIP No power good power fault Power Unit Redundancy sensor Insufficient resources offset indicates not enough power supplies are present Not read Notes 1 The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide the contribution to the system status LED 7 3 7 Chassis ID LED The chassis ID LED provides a visual indication of a system being serviced The state of the chassis ID LED is affected by the following Toggled by the chassis ID button Controlled by the Chassis Identify command IPMI Controlled by the Chassis Identify LED command OEM Table 35 Chassis ID LED Indicator States LED State Identify active via button Solid on Identify active via command 1 Hz blink There is no precedence or lock out mechanism for the control sources When a new request arrives all previous requests are terminated For example if the chassis ID LED is blinking and the chassis ID button is pressed then the chassis ID LED changes to solid on If the button is pressed again with no intervening commands the chassis ID LED turns off 58 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS 7 4 1 0 Connectors 7 4 1 PCI Express Connect
109. rs must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design This document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent
110. rver Board Overview Table 2 Intel Server Board S5500WB System Interconnects Description Description A Dual Intel Expansion Module V Processor Socket 1 Connectors B PCI Express x16 Gen2 8 Pin CPU Connector C Remote Management Module 3 X Processor Socket 2 D POST Code LEDs Y 4 pin Fan Connector CPU2 E External I O Z 4 pin Fan Connector CPU2A F USB Connector 4 pin Fan Connector MEM2 G Battery 8 pin Fan Connector MEM2R H SATA Connectors DIMM Slot D2 24 Pin Connector SSI only DD DIMM Slot D1 J 8 Pin Connector 12V only EE DIMM Slot E1 K Aux Power 5 pin or 7 pin FF DIMM Slot F1 L RAID Key GG Front Panel Connector M DIMM Slot C1 HH HDD LED Header N DIMM Slot B1 1 Low Profile USB Connector DIMM Slot 1 JJ Internal VGA Connector P DIMM Slot A2 KK BMC Power Cycle Header 12V Only Q 8 pin Fan Connector MEM1R LL USB Connector R 4 pin Fan Connector 1 MM Slot 1 Express x8 Gen2 5 4 Fan Connector SGPIO Connector 4 Fan Connector CPU1 OO IMPB Connector U HDD Power Connector 12V only PP Serial Port B Revision 1 3 Intel order number E5397 1 004 Server Board Overview Intel Server Board SSSOOWB TPS 2 2 1 Board Rear Connector Placement The Intel Server Board S5500WB has the following board rear connector placement AF003052 Figure 4 Rear Panel
111. s only PCI Express adapters that meet the PCI SIG half card definition Full length boards are supported in a 2U system by using a taller riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated Appendix A documents the pin assignments for this connector 3 13 2 PE WIDTH Strapping On the Intel Server Board S5500WB the IOH needs to be informed of the PCI Express bus width during power on This is accomplished using the PEWIDTH input straps The mechanism used is the PEWIDTH bits one bit is used to signify the width and number of PCI Express buses used by the riser For slot 6 the PEWIDTH bit used is O Table 11 PEWIDTH Strapping Bits PEWIDTHO Description pin A50 1U one x8 1 x8 PCI Express Slot 2U two x4 2 X4 PCI Express Slots By using this mechanism for selecting PCI Express port width you can avoid a BIOS rediscover and reboot Revision 1 3 35 Intel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS The PEWIDTH is pulled up to 3 3 V Aux on the baseboard and grounded if necessary by the riser The baseboard provides an inverter and voltage level translator before passing this signal to the 3 13 3 Slot 1 PCI Express x8 Connector Slot 1 provides a PCI Express x4 bus on an x8 connector if provided for use in a 2U chassis that uses LP boards without risers Although it is feasible to use the at the same time it would require 2U chassis ba
112. sions International EN55022 Emissions Europe EN55024 Immunity Europe Directive 89 336 EEC Europe AS NZS 3548 Emissions Australia New Zealand VCCI Emissions Japan BSMI CNS13438 Emissions Taiwan GOST R 29216 91 Emissions Listed on one System Certification Russia GOST R 50628 95 Immunity Listed on one System Certification Russia Belarus Certification Listed one System Certification Belarus EMI Korea 11 1 3 Certifications Registrations Declarations NRTL Certification US Canada CE Declaration of Conformity CENELEC Europe FCC ICES 003 Class A Attestation USA Canada Declaration of Conformity Australia MED Declaration of Conformity New Zealand BSMI Certification Taiwan 84 Revision 1 3 Intel order number 53971 004 Intel Server Board S5500WB TPS Regulatory and Certification Information GOST Listed on one System Certification Russia Belarus Listed on one System Certification Belarus KCC Certification Korea Ecology Declaration International 11 2 Product Regulatory Compliance Markings This Intel Server Board bears the following regulatory marks Table 54 Product Regulatory Compliance Markings Regulatory Compliance Country Marking UL Mark USA Canada TERTE p CE FCC Marking Class A USA This device complies with Part 15 of the FCC Rules Operation of this device is subject to th
113. ss slots 3 12 Integrated Video Support The SVGA subsystem supports a variety of modes up to 1600 x 1200 resolution in 8 16 32 bpp modes under 2D It also supports both CRT and LCD monitors up to a 200 Hz vertical refresh rate The video is accessed using a standard 15 pin VGA connector found in the I O panel area of the server board You can disable the onboard video controller using the BIOS Setup utility or when an add in video card is detected The system BIOS provides the option for dual video operation when an add in video card is configured in the system 3 12 1 Video Modes The integrated video controller supports all standard VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 9 Supported Video Modes 2D Mode Refresh Rate Hz 2D Video Mode Support 8 bpp 16 bpp 32 bpp 640x480 60 72 75 85 90 Supported Supported Supported 100 120 160 200 800x600 60 70 72 75 85 Supported Supported Supported 90 100 120 160 1024x768 60 70 72 Supported Supported Supported 75 85 90 100 1152x864 43 47 60 70 75 80 85 Supported Supported Supported 1280x1024 60 70 74 75 Supported Supported Supported 1600x1200 52 Supported Supported Supported 3 12 2 Dual Video The BIOS supports both single video and dual video modes The dual video mode is enabled by default in the BIOS In the single mode dual monitor video disabled the onboard video contr
114. state 5 2 1 Server Engines Pilot Il Controller The center of the server management subsystem is the Server Engines Pilot Il integrated Baseboard Management Controller This device provides support for many platform functions including system video capabilities legacy Super I O functions and also provides an ARM 926 EJ microcontroller to host the embedded server management firmware stack The Server Engines Pilot Il baseboard management controller across Intel s server product line with two different management feature set configurations Basic and Advanced The Intel Server Board S5500WB supports both Basic features include IPMI 2 0 support remote management hardware monitoring event management event alerting system event log asset inventory console redirection web interface and SMASH CLP basic feature set Advanced features include the Basic features plus KVM redirection USB Media redirection SMASH CLP Advanced feature set and WS MAN To enable the Advanced features you must install the Remote Management Module 3 NOTE The BMC consumes two USB ports one runs at USB1 1 for keyboard mouse redirection and one runs at USB2 0 for media redirection 5 2 2 BMC Firmware The BMC supports a Fast Firmware Update mode in addition to the standard KCS Keyboard Controller Style SMS interface This is a special AMI proprietary protocol that goes over the USB connection between the host and the BMC Called IPMI over USB
115. state for the current most severe fault For example if there was a critical fault due to one source and a non critical fault due to another source the system status LED state would be solid on the critical fault state The system status LED is a bicolor LED Green status shows a normal operation state or a degraded operation Amber fault shows the system hardware state and overrides the green status The Integrated BMC detected state and the state from the other controllers such as the SCSI SATA hot swap controller state are included in the LED state For fault states monitored by the Integrated BMC sensors the contribution to the LED state follows the associated sensor state with the priority going to the most critical state currently asserted When the server is powered down transitions to the DC off state or 55 the Integrated BMC is still on standby power and retains the sensor and front panel status LED state established prior to the power down event The following table maps the system state to the LED state 56 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out Table 34 System Status LED Green Solidon System ready EL EILM Hz Degraded blink Amber 1 Hz Non Fatal blink Revision 1 3 BIOS detected 1 2 Unable to use all of the installed memory more than one DIMM installed In a mirrored configuration when m
116. t The setup POST error Pause setting does not have any effect with this error Pause The message is displayed on the Error Manager screen and an error is logged to the SEL The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to continue booting Halt The message is displayed on the Error Manager screen an error is logged to the SEL and the system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system The setup POST error Pause setting does not have any effect with this error Table 57 POST Error Messages and Handling Fixed Media The SAS RAID firmware can not run properly The user should Major 0113 attempt to reflash the firmware 0140 PCI component encountered a PERR error 0141 PCI resource conflict 0146 PCI out of resources error 0192 Processor 0x cache size mismatch detected Fatal 0193 Processor Ox stepping mismatch Minor 0194 Processor Ox family mismatch detected Fatal Revision 1 3 95 Intel order number E53971 004 Appendix B Video POST Code Errors Intel Server Board SSSOOWB TPS Error Code Response Maior Maior Mar Mar 8502 CLTT Configuration Failure Error Major 8520 1 failed Self Test BIST 8521 DIMM 2 failed Self Test BIST 8522 DIMM B1 failed Self Test BIST 8523 DIMM B2 failed Self Test BIST 8524 DIMM_C1 fail
117. ted Serial ATA SATA controller that supports independent DMA operation on six ports and data transfer rates of up to 3 0 Gb s The six SATA ports on the server board are numbered SATA 1 through SATA 6 You can enable or disable the SATA ports and or configure them by accessing the BIOS setup utility during POST 3 7 1 1 Intel Embedded Server RAID Technology II The onboard storage capability of these server boards includes support for Intel Embedded Server RAID Technology II Intel ESRTII which provides three standard software RAID levels data stripping RAID Level 0 data mirroring RAID Level 1 and data stripping with mirroring RAID Level 10 For higher performance you can use data stripping to alleviate disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers Data mirroring is used for data security If a disk fails a mirrored copy of the failed disk is brought online There is no loss of either PCI resources request grant pair or add in card slots With the addition of an optional Intel RAID Activation Key Intel ESRTII is also capable of providing fault tolerant data stripping software RAID Level 5 such that if a SATA hard drive fails you can restore the lost data on a replacement drive from the other drives that make up the RAID 5 pack Intel Embedded Server RAID Technology functionality requires the following items ICH10R IO Controller Hub e Software RAID option is se
118. tegrated 250 MHz 32 bit ARM9 processor Six lC SMBus modules with Master Slave support e Two independent 10 100 Ethernet Controllers with RMII support e Six interface e Memory Management Unit MMU DDR2 16 bit up to 667 MHz memory interface e Up to 16 direct and 64 Serial GPIO ports e 12 10 bit Analog to Digital Converters e Eight Fan Tachometers Inputs e Four Pulse Width Modulators PWM Chassis Intrusion Logic with battery backed general purpose register e JTAG Master interface e Watchdog timer Additionally the ServerEngines Pilot II part integrates a super I O module with the following features e Keyboard Style BT Interface e Two 16C550 compatible serial ports Serial IRQ support e 16 GPIO ports shared with Integrated BMC Revision 1 3 31 Intel order number E53971 004 Functional A rchitecture Intel Server Board SSSOOWB TPS e LPC to SPI Bridge for system BIOS support SMI and PME support e ACPI compliant e Wake up control The Pilot contains an integrated KVMS subsystem and graphics controller with the following features e USB 2 0 for keyboard mouse and storage devices e Hardware Video Compression for text and graphics e Hardware encryption e 2D Graphics Acceleration DDR2 graphics memory interface e Matrox 2000 Graphics core with PCI Express x1 host interfac
119. tel order number E53971 004 Functional Architecture Intel Server Board SSSOOWB TPS AF003060 Figure 11 Removing the socket cover 7 Remove the protective socket cover See letter D in Figure 11 8 Align the pins of the processor with the socket and insert the processor into the socket Orientation Notch AF003061 Figure 12 Installing processor 9 Lower the load plate and load lever of the ILM cover completely NOTE Make sure the alignment triangle mark and the alignment triangle cutout align correctly To assist in package orientation and alignment with the socket A The package Pin1 triangle and the socket Pin1 chamfer provide a visual reference for proper orientation B The package substrate has orientation notches along two opposing edges of the package offset from the centerline The socket has two corresponding orientation 18 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture posts to physically prevent mis orientation of the package These orientation features also provide an initial rough alignment of the package to the socket C The socket has alignment walls at the four corners to provide final alignment of the package orientation notch Pini triangle alignment walls access orientation post Pini chamfer Figure 13 Package Installation Remove Feature 3 3 3 2 Installing the Processor Heatsink s CAUTION The heatsi
120. tup Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Functional Architecture System Action Processor Intel QuickPath Halt The BIOS detects the error condition and responds as Interconnect speeds not follows identical e Adjusts all processor interconnect frequencies to lowest common denominator Logs the error into the SEL Alerts the Integrated BMC about the configuration error Does not disable the processor Displays 0195 Processor Ox Intel R QPI speed mismatch message in the Error Manager e f POST Error Pause is disabled in the Setup continues to boot in a degraded state e If POST Error Pause is enabled in the Setup pauses the system but can continue to boot if operator directs 3 3 3 Installing or Replacing the Processor 3 3 3 1 Installing the Processor To install a processor follow these instructions Turn off all peripheral devices connected to the server Turn off the server Disconnect the AC power cord from the server Remove the server s cover See the document that came with your server chassis for instructions on removing the server s cover 5 Locate the processor socket and raise the raise the load lever of the ILM cover completely see letter A in the figure below eS 003059 Figure 10 Lifting the load lever of ILM cover 6 Open the load plate see letter B in Figure 10 and letter C in Figure 11 Revision 1 3 17 In
121. ughput to slot 1 Intel 5500 Chipset Gen2 IOH PCI Express PE7 PE8 40 Gb S PCI Express x8 PCI Express Gen2 throughput to the slot 6 riser Intel 5500 Chipset Gen2 IOH PCI Express 9 10 40 Gb S PCI Express x4 PCI Express Gen2 throughput to each of the two Intel Intel 5500 Chipset Gen2 I O Expansion Module connectors IOH PCI Express 3 5 1 1 Direct Cache Access DCA The DCA mechanism is a system level protocol a multi processor system to improve I O network performance by providing higher system performance It is designed to minimize cache misses when a demand read is executed This is accomplished by placing the data from the I O devices directly into the CPU cache through hints to the processor to perform a data pre fetch and install it in its local caches The Intel 5500 series processor supports Direct Cache Access DCA You enable or disable DCA in the BIOS processor setup menu 3 5 1 2 Intel Virtualization Technology for Directed 1 0 Intel VT d The Intel Virtualization Technology is designed to support multiple software environments sharing the same hardware resources Each software environment may consist of an operating system and applications You can enable or disable the Intel Virtualization Technology in the BIOS setup The default behavior is disabled Note If the setup options are changed to enable or disable the Virtualization Technology setting in the processor the user must p
122. ules refer to the Intel Server Board IO Module Hardware Specification The following table details the pin out of the Intel 1 0 Expansion Module connectors Revision 1 3 63 Intel order number 53971 004 Connector Header Locations and Pin out Intel Server Board SSSOOWB TPS Table 42 50 pin Intel Expansion Module Connector Pin out J2B1 J3B1 Pin SignalNam _ Pin SignalName_ 1 3 PERSTIO MODULEN 4 6ND 5 GND 6 PE2ESBRXPC O 7 GND 8 PED lt 0 gt 9 11 13 15 GND 17 19 21 22 25 27 29 GND 31 33 35 37 39 GND 41 43 45 47 49 64 Revision 1 3 Intel order number E5397 1 004 Intel Server Board SSSOOWB TPS Connector Header Locations and Pin out 7 4 6 Serial Port Connectors The server board provides one external RJ 45 Serial A port J7A1 and one internal 9 pin serial B header J1A2 The following tables define the pin outs Table 43 External RJ 45 Serial Port A COM1 J7A1 Pin SignalName Pin Signa 1 SPA RTS 5 SPA RI 2 SPA 6 SPA SIN 3 SPA SOUT N 7 SPA DSR 4 GND 8 SPA CTS Table 44 Internal 9 pin Serial B COM2 J1A2 Pin SignalName Pin SignalName SPB DCD SPB DSR SPB SIN N SPB RTS SPB SOUT N SPB CTS SPB DTR SPB RI GND 7 4 7 USB Connectors The following table details the pin out of the external USB connectors
123. ulled HIGH Default position 2 3 Clear CMOS ICH10R RTCRST pin is pulled LOW Settings J6A3 Video Master 1 2 Internal Internal connector will override if both connectors are used 2 3 External External connector will override if both connectors are used J7A2 ME Firmware 1 2 Disabled Default Force Update 2 3 Enabled J6A2 Serial Interface DCD to DTR Data Carrier Detect DSR to DTR Data Set Ready 6 1 1 Force IBMC Update 1 5 When performing a standard BMC firmware update procedure the update utility places the BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the BMC firmware update process fails due to the BMC not being in the proper update state the server board provides a BMC Force Update jumper J1B5 which will force the BMC into the proper update state The following procedure should be followed in the event the standard BMC firmware update process fails Table 17 Force IBMC Update Jumper Jumper Position Operation Note IBMC GPIO 1 is pulled HIGH Default position IBMC GPIO 1 is pulled LOW 1 Power down and remove the AC power cord 2 Open the server chassis See your server chassis documentation for instructions 3 Move jumper from the default operating position covering pins1 and 2 to the enabled position covering pins 2 and 3 46 Revision 1 3 Intel order number 53971 004 Intel Server Board SSSOOWB TPS Configuration Jumpers
124. umber 53971 004 Power Subsystem 10 Power Subsystem Intel Server Board SSSOOWB TPS 10 1 Server Board Power Distribution ON BOARD PERIPHERAL IC SWITCHER 7 lt LINEAR DDR3 4 DIMMS LEN CPUo VDD HAGA 275 DDR3 VTT e CPUo DDAS VIT XE 14 AVERAGE QUA PEAK 075 DDR VTT CPU DDR3 VIT t 4m AVERAGE an sasa CPU VDD PK 2A TOC ICH10 E TYLERSBURG 10H 1 om STB BN VAUX SWITCH mam mcam 2 KAWELA OMA TYLERSBURG ICH10 t OMA 7 SOMA P3V3 AUX USB 20 TBD USAGE MODI PCIE GEN2 9 8 EEPROM ZEPHYR RMMS ICH10 IOH ICH10 1 5V ZA PK f ICH10 cw SATA 2 PCIE RISER CARD POWER RESISTORS 551 MOO PCIE SLOT P 2V SW SWITCH n 12V ONLY SYSTEMCPU MEM FANS 4 TED 551 MODE 1 1V D mm m me Pi2v ONLY e TYLERSBUAG 10H L 127 PU e CPUo PLL im TA Figure 32 Power Distribution Diagram 10 2 Power Supply Compatibility The Intel Server Board S5500WB is offered in two models Mon Dec 08 14 33 43 CKs09B DB1200 TEMA DRIVE HEADER rua RISER CARD
125. ur captive screws on the heatsink corners in a diagonal manner according to the numbers shown in Figure 1 as follows a Starting with the screw at location 1 loosen it by giving it two rotations in the anticlockwise direction and stop IMPORTANT Do not fully loosen b Proceed to the screw at location 2 and loosen it by giving it two rotations and stop c Loosen screws at locations 3 and 4 by giving each screw two rotations and then stop d Repeat steps 1a through 1c by giving each screw two rotations each time until all screws are loosened 2 Lift the heatsink from the board 3 3 4 Intel QuickPath Interconnect Intel QPI Intel QPI is a cache coherent link based interconnect specification for processor chipset and I O bridge components You can use it in a wide variety of desktop mobile and server platforms spanning 32 and Intel Itanium architectures Intel QPI also provides support for high performance I O transfer between I O nodes It allows connection to standard I O buses such as 20 Revision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture PCI Express PCI X PCI including peer to peer communication support AGP Accelerated Graphics Port and so forth through the appropriate bridges Each Intel QPI link consists of 20 pairs of uni directional differential lanes for the transmitter and receiver plus a differential forwarded clock A full width Intel QPI link
126. us Power supplies that have PMBus 1 1 are supported and required to support Intel Dynamic Power Node Manager Intel Server Board S5500WB supports the features of Intel Dynamic Power Node Manager version 1 5 except the inlet temperature sensor 5 6 SMBUS Architecture Block REPEATER CKSO9B 33v DC HOST BUS T Pcasers DOR3 DIMMS X 2 CPUO CH A1 p 2 XDPO CPU 5 CPUO CH A2 eg 2 2 DB CPUO CH B1 y 4 SBURG 1 YLERSBUR zs PE CPUD CH C1 us 1 AG ME n FRU AT24CG4 y TEMP SENSOR a a lt Y y FRONT PANEL ICHA10R T 2 STB Lin E 2 REPEATER POWER SUPPLY e avsa 2 T x amp PCASSIS Pet KAWELA gt gt 3 3V STS LAN BUS 2 150 3 5v STBY IPM BUS we a a 8 poem 5v STBY IPM BUS 3 1 e M Bus POR 150 Tey D IBMC Figure 20 55500WB SMBUS Block Diagram 5 6 1 SMBUS Device Addresses Table 21 lists the SMBus addresses of various devices by bus Table 15 SMBus Device Address Assignment Power Sub Power Device SMBus Note Rail Bus Rail Address Host 3V3SB NA NA IBMCSMBs3 NoConnect ICHIOR SMBus 509 Pd pB43 opc Dmm H Revision 1 3 43 Intel order number 53971 004 DIMMS CPU1 CH D1 1 Ox 8 CPUM CH D2 OxAA
127. usus ___ VOLTAGE SENSORS 2 CEU RDMM EVENT N 19 LED DIMM FAULT 7 5 4 CPUD N 20 LED FAN FAULT Pi2V 6 PV VCCP CPUO 5 1 THERMTRIP N 21 LED FAN FAULT o P5V 7 PV CPUI amp CPU0 VRHOT 22 LED FAN FAULT CPUO P3Vs PiV5 DDR3 CPUO T MEM 23 LED FAN FAULT CPU1 PsV STBY 9 P1V5 DDR3 CPU1 24 LED FAN FAULT MEMOR P3V3 STBY 10 P1Vi_IOH 25 LED FAN FAULT MEMIR P1VS ICH 11 P1V8 AUX NIC 26 NA 27 NA 28 N A 29 NA 30 NA 31 NA J a FA 5 CONN INTRUDER 5 6 1X4 CONI SWITCH 5021 BEER BEE 6 6 9 2 THERMAL SENSORS gt gt MOSFET HSBP e ISOLATION 0 NOT USED i 1 NOT USED CONN A NOT USED z E 2 BASEBOARD 0XCO ISO HSBP L i 361 CONN B 3 orense ADC BATT GPIO SGPIO CHASS THERM axc2 SM BUS 1 33V STBY f 225555 5555 B Bis Bus 100 5V STBY IPMI IBMC lt lt lt lt s lt PUR BUS CONN Figure 29 Fans and Sensors Block Diagram 9 2 Thermal Sensors 9 2 1 Processor PECI Temperature Sensor The processor thermal control uses a CPU PECI thermal sensor which is a relative temperature off PROCHOT trip point a 20C reading means 20C below trip point temperature The BMC can get the Intel 5500 series processor PECI Tcontrol values for each
128. vision 1 3 Intel order number E53971 004 Intel Server Board SSSOOWB TPS Functional Architecture 3 Functional Architecture The Intel Server Board S5500WB is a purpose build power optimized server used in 11 rack Memory and processor socket placement is made to minimize the amount of fan power required to cool these components Voltage Regulators VRDs are optimized for a particular range of memory and CPU power that suits the target Internet Portal Datacenter IPDC segment of the market The VRDs are also designed to be highly power efficient balancing the needs of being small in size and also cost effective There are two SKUs a 12 V only SKU and an SSl compliant SKU 3 1 High Level Product Features Table 3 Intel Server Board S5500WB Features S5500WB 12V S5500WB SSI Form Factor EATX 12 x 13 EATX 12 x 13 UMP Intel 5500 Chipset Intel 5500 Chipset IOH i Intel 82801Jx I O Controller Hub ICH10R ntel 82801 1 Controller Hub ICH10R Memory RDIMMs or 8 UDIMMs DDR3 8 RDIMMs or 8 UDIMMs DDR3 Slots 1 PCI Express x8 w x16 connector 1 PCI Express x8 w x16 connector 1 PCI Express x4 w x8 connector 1 PCI Express x4 w x8 connector Ethernet Dual GbE Intel 82576 Gigabit Ethernet Dual GbE Intel 82576 Gigabit Ethernet Storage Six SATA II ports 3Gb s Six SATA II ports 3Gb s SAS One 1 4 port SAS module on IOM connector One 1 4 port SAS module on IOM optional onnector option
129. xpansion Module Single Port QDR The second x4 Intel I O Expansion Module controller does not support a single wide module it is only used to support a double wide module You must mount single wide modules on connector J3B1 closest to Slot 6 marked Legacy Intel I O Expansion Module on the silkscreen When double wide Intel I O Expansion Modules are installed there might be interference with some adapters installed in Slot 1 The following table shows the product codes for each module Table 13 Intel I O Expansion Module Product Codes Intel SAS Entry RAID I O Expansion Module Provides 4 AXX4SASMOD port pass through SAS entry level RAID 0 1 1E and optional host RAID 4 internal ports AXXGBIOMOD Dual Gigabit Ethernet I O Expansion Module Intel Integrated RAID Expansion Module Provides four internal ports full featured SAS SATA RAID 0 1 5 6 and AXXROMBSASMR striping capability for spans 10 50 60 You must order the optional backup battery AXXRSBBU3 separately AXXSASIOMOD External 4 port SAS I O Expansion Module AXX10GBIOMOD Dual port 10 Gigabit Ethernet I O Expansion Module with connectors Revision 1 3 37 Intel order number E5397 1 004 Intel 1 0 Expansion Modules Intel Server Board S5500WB TPS Quad port Gigabit Ethernet I O Expansion Module based on AXXAGBIOMODZ the Intel 82576EB Gigabit Ethernet Controller AXXIBQDRMOD InfiniBand 1 Expansion Module Single Port QDR For more informati

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