Home

Fujitsu MB86617A Network Card User Manual

image

Contents

1. instruction Read A code gg Specify each instruction code 7 0 d Read Specify required operand for each instruction code gt operan Write Write 0 into all hts for instructions without operand Note Before writing in instruction for this register read out IPC busy Bit bit15 of 7 2 flag amp status Register and confirm that the IPC busy value is 0 7 0 31 Fujitsu VLSI LST Specification MBS66IZA 7 4 interrupt factor Indicate Register interrupt mask Setting Register interrupt factor indicate register is the register that indicates interrupt reported by this LSI Refer to Chapter 10 Interrupt for measure against and details of each Bit and interrupt factor interrupt mask setting register is the register that controls mask of each interrupt factor generated by this LSI Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit s interrupt mask Interrupt factor interrupt mask Indicate that interrupt factors are not generated Read 1 Indicate that interrupt factors are generated After reading out this register clear to 0 automatically 15 0 Do not mask interrupt factors interrupt mask Write Mask interrupt factors 1 Interrupt factors masked by setting of this register are neither stored in interrupt indicate register nor assert INT signal interrupt facto Rev 1 O 32 Fujitsu VLSI LST Specification MBS66
2. netten ina dein A aW a s aa QA d P d 70 7 33 PHY LINK REGISTER ADDRESS SETTING REGISTER I trente nitet tenete tetti intei teinte U 71 7 34 PHY LINK REGISTER ACCESS PORT 72 7 35 REVISION INDICATE REGISTER suu aaa tet ade dea tie dot rd ote ptc ttt ade ep reto 73 7 36 TRANSMIT CGMS TSCH INDICATE REGISTER L tnter inns 74 7 37 TRANSMIT CGMS TSCH ENDICATE REGISTER a 75 7 38 TRANSMIT CGMS TSCH INDICATE STATUS REGISTER 76 7 39 TRANSMIT SETTING ict crt ic bete en id dtes 78 CHAPTER 8 PHY INK REGISTER FUNCTION DESCRIPTION U U Ra E uuu Q u 80 8 1 PHY LINK REGISTER T ABLE erede n EX ERE EAE RE RR THERE WE TR ERE ER RR ER Fe RR e 81 8 2 PHYSICAL REGISTER 00 READ cnet etit ethnic are rec 83 8 3 PHYSICAL REGISTER 01 READ WRITE 84 8 4 PHYSICAL REGISTER 02 READ ian itera dina Walesa aaa a dated e 85 8 5 PHYSICAL REGISTER 03 READ inigi aia ea a a a re et n ER E iyaiwa n EC rr e e n aen 86 8 6 PHYSICAL REGISTER 04
3. 100 CHAPTER 1 Q 101 91 1 5 cde RU P det e LR dice E Dee 102 Rev 1 O iv Fujitsu VLSI LST Specification MBS66IZA 9 2 DESCRIPTION OF EACH INSTRUCTION ne dra dp ink Fn dd d n er i 103 CHAPTER IO INTERRUPT RE nne ar noe 106 10 1 INTERRUPT FACTOR INDICATOR REGISTER amp INTERRUPT MASK SETTING REGISTER 107 10 2 INTERRUPT 108 10 3 DESCRIPTION OF eic eth t p t dede er pta cei e db o 109 CHAPTER 11 OPERATION 112 raten e n tet ret dece teta Et bacis 113 112 SELE ID PACKET RECEIVING qaqa grec cele et ti e N enel TO ed 114 11 2 1 Sdf ID Packet Receive at Bus Reset Process nn n nnnnnnnnnnnnnnnnnnnnnnnnnnnnasnsnnnn 115 11 2 2 Sdf ID Packet Receive after Transmitting Ping Packet Ping 118 11 3 ASYNCHRONOUS PACKET 5 a tte sette tto 120 11 4 ASYNCHRONOUS PACKET RECEIVING eene tnnt 122 11 5 ISOCHRONOUSPACKET TRANSMITTING ct ege sni ep nn e Rc n a ed o tpe etn 125 1L6 ISOCHRONOUS PACKET REGEIVING tet ctii de n dr d to ded vir A Ha d Dp 128 CHAPTER 12 SYSTEM CONFIGURATION IIIII III III III Q 130 12
4. TPBIASO 1 1 1 1 1 gt XTPA2 TPB2 XTPB2 TPBIAS2 Fujitsu VLSI LST Specification MBS66IZA m Asynchronous Transmit FIFO Extended M ode Asynch Transmit Exdusive FIFO TPAO 256 byte to XTPA0 D 2 D 9 XTPB0 o gt TPBIASO Asynch Transmit Exdusive FIFO 256 byte 1 to PHY XTPA1 LINK 4 Layer Control 1 Circuit 9 1 51 d a 3 TPA2 g m 5 8 XTPA2 TPB2 i XTPB2 M gt TPBIAS2 FIFO 2 Interface Fig 3 1 2 Block Diagram Asynchronous Transmit FIFO Extended M ode 7 0 5 Fujitsu VLSI LST Specification Asynchronous Receive FIFO Extended ode Asynch Transmit Exdusive FIFO 256 byte 2 I 2 2 zd 8 3 a a b 9 Asynch Transmit Exdusve FIFO 256 byte D PHY LINK 2 FIFO Layer a Control e Byte Circuit _ T a g g 5 5 lli 3 5 2 Interface Fig 3 1 3 Block Diagram Asynchronous Receive Extended Mode 86677 gt TPBIASO 1 1 1 1 1 2 2 2 XTPB2 gt TPBIAS2 Rev 1 O 6 F
5. eme eu a iwa hs ente ert s Meu 7 E DATA BRIDGE s 7 CHAPTER 4 PIN ASSIGNMENT U U U U U U U 8 4T PIN ASSIGNMENT e c c rea e c te aH OR d 9 4 2 CORRESPONDING TABLE OF MB86617 A PIN tenente tte tentent tnnt ntt tto tna tette tentant tte 10 4 3 OUTLINE DRAWING PACKAGE etre d drum ipee en 11 CHAPTER 5 PIN FUNCTION U U U U U U U U u uu ul uu 12 5 1 TEEEI3 94 INTERFACE u aaa aaa aaa Hbc c Fe Pr e eu a cH n HX LEX Kk Waya 13 5 2 IS OGHRONOUS eren ere tei ere petu triennium pore Erb n dete D n PAR EM IK As 14 5 4 MPU TNTEREAGE MEME 16 5 5 OTHER PINS 17 5 0 POWER GND BIN 18 CHAPTER 6 INTERNAL REGISTER rere eee s U U u A EA EN E NE NEN NEN E NE NE A RA E E uuu 19 CHAPTER 7 INTERNAL REGISTER FUNCTION DESCRIPTION U e U aas u Q Qu 25 TA MODE CONTROL REGISTER a ner ana Ud cert ied d i EH wau 27 7 2 FLAG 62 STATUS REGISTER iir rr RH RE unis NER ra va 29 Rev 1 O ii Fujitsu VLSI LST Specification MBS66IZA 7 3 INSTRUCTION FETCH REGISTER edia ii nk d d d d
6. 1 5 Rev 1 O 19 Fujitsu VLSI LST Specification A BSO6OITA READ Register Name Register Name transmit DSS packet header setting A upper receive DSS packet header setting A upper transmit DSS packet header setting A medium receive DSS packet header setting A medium N N N N transmit DSS packet header setting A lower receive DSS packet header setting A lower transmit DSS packet header setting receive DSS packet header setting least significant least significant N transmit 055 packet header setting B most significant receive DSS packet header setting B most significant N oo gt gt transmit DSS packet header setting B upper receive DSS packet header setting B upper N transmit DSS packet header setting B medium receive DSS packet header setting B medium transmit DSS packet header setting B lower receive DSS packet header setting B lower transmit DSS packet header setting B least significant receive DSS packet header setting B least significant o N reserved TSP status data bridge transmit information setting 1 A data bridge transmit information setting 1 A data bridge transmit information setting 2 A data bridge transmit information setting 2 A data bridge transmit information setting 3 B data bridge transmit information setting 3 B o2 data bridge transmit info
7. an aa ada aaaea aana 31 7 4 INTERRUPT FACTOR INDICATE REGISTER INTERRUPT MASK SETTING 5 32 7 5 RECEIVE CKNOWLEDGE INDICATE REGISTER 33 7 6 A BUEFER DATA PORT RECEIVE TRANSMIT ukna aha recite x ca rct vir Rc one Ron e be P E c ri P 34 7 7 5 T RANSMIT INFORMATION SETTING REGISTER A tnter 35 7 8 TSP T RANSMIT INFORMATION SETTING REGISTER B ener nente tnnt tereti tentent toten totes 37 7 9 TRANSMIT OFFSET SETTING REGISTER 1 12 1 I U 39 7 10 TRANSMIT OFFSET SETTING REGISTER iu u nan nnne tente te 40 7 11 TSP RECEIVE INFORMATION SETTING REGISTER 41 7 12 RECEIVE DSS PACKET HEADER INDICATE REGISTER A TRANSMIT DSS PACKET HEADER SETTING REGISTER A 44 7 13 RECEIVE DSS PACKET HEADER INDICATE REGISTER B T RANSMIT DSS PACKET HEADER SETTING REGISTER B 45 REGISTER EAR ase cR LO ANNA AE ARE et 46 7 15 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 1 A eren a 48 7 16 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 2 a 49 7 17 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 3 B 50 7 18 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 4 B I 51 7 19 DATA BRIDGE RE
8. b DSS at transmit 10 b Rev 1 O 4 Fujitsu VLSI LST Specification MBS66IZA 7 16 Data Bridge Transmit Information Setting Register 2 A Data bridge transmit information setting register 2 A is the register that sets CIP header range transmit channel and speed added to transmit packet processed by bridge Ach Het Tx channel A Tx speed d d w m Writein FMT range of transmit header _ Read MSB bit1 5 LSB bit 10 Sod DIA Write MPEG2 TS at transmit 100000 b DSS at transmit 100001 b Tx TSF A wae Writein TSF range of transmits CIP header 8 3 Tx ch LA Read Write in channel range of transmit Isochronous packet header Write MSB bit LSB bit3 Write in transmit packet speed Read MSB bit2 LSB bitl 2 1 Tx speed A Write 100 at transmit 00 b s200 at transmit 01 b s400 at transmit 10 b WE Always indicates 0 reserved Rev 1 O 46 Fujitsu VLSI LST Specification MBS66IZA 7 17 Data Bridge Transmit Information Setting Register 3 B Data bridge transmit information setting register 3 B is the register that sets CIP header range added to transmit packet processed by bridge Bch Tx SID B Tx DBS B TFNB FN B Read Write in SID range of transmit CIP header i Tee L MSB bit1 5 LSB bit 10 Write m DBS range of transmit header Read MSB bit9 LSB bit2 222 TX DBSB Writ
9. Indicates that received packet is normal Rx late B Read Indicates that received packet was Late packet Deletes packet and does not output to TSP IC Clears to 0 by lead of this register Indicates that 50 60 range of CIP header of received Isochronous packet is 07 Indicates that 50 60 range of CIP header of received Isochronous packet is 1 Clears to 0 by lead of this register Indicates that STYPE range of CIP header of received Isochronous packet is 00000 or 00001 Indicates that STYPE range of CIP header of received Isochronous packet is other than 00000 or 00001 Clears to 0 by lead of this regist er Indicates that DBC range of CIP header of received Isochronous packet is normal BRG HFO u Indicates that DBC range of CIP header of received Isochronous packet is not consecutive Clears to 0 by lead of this register Rx 56 err B Read Rx stype err B Read Rev 1 O 6 Fujitsu VLSI LST Specificatior MBS66IZA Indicates that CIP header of received Isochronous packet is normal Rx CIP err B Read 1 Indicates that CIP header of received Isochronous packet has an error Cleared to 0 by lead of this register Indicates that FMT range of CIP header of received Isochronous packet is the value 0 allowed to be received at DV EN DSS EN or TSEN ICh bitlO to 8 DV 00000 MPEG2 10000 or 055 100001 Rx FMT err B Read Ind
10. reserved gt reserved oo reserved reserved reserved reserved reserved reserved N reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved EN EN EN 8 Rev 1 O 22 Fujitsu VLSI LST Specification MBS66IZA READ Register Name Register Name reserved reserved N reserved reserved reserved reserved reserved reserved reserved gt reserved reserved reserved reserved m reserved reserved reserved reserved reserved reserved Q reserved reserved reserved reserved reserved reserved a reserved reserved Q Q reserved reserved Q les reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Z reserved reserved 5 gt reserved reserved n m reserved reserved reserved reserved Rev 1 O 23 Fujitsu VLSI LST Specification MBS66IZA gt reserved reserved reserved reser
11. LSB bit7 Processes transmit data as MPEG2 TS packet Tx form B Processes transmit data as DSS packet Processes transmit DSS packet as 140 byte input DSS size B 1 Processes transmit DSS packet as 130 byte set TSID B Rev 1 O 37 Fujitsu VLSI LST Specificatior MBS66IZA Selects CGMS information input from TSP IC as EMI information to be output to CP IC Read 4 EMI select B Write Selects setting value of set EMI A bit3 to 2 as EMI information to be output to CP IC Read Set EMI information to be output to CP IC 3 2 set EMI B un it Valid only when EMI select A bit4 18417 me MSB bit3 LSB bit2 Does not insert internal 27 MHz counter to System clock count range of DSS packet header Read 1 27 t B e Write Inserts internal 27 MHz counter to System clock count range of DSS packet header Does not mask port B input of TSP IC interface Reads in input data from port A at transmit 0 ort mask B P Write Masks port B input of TSP IC interface Does not read in input data from port A at transmit Rev 1 O 38 Fujitsu VLSI LST Specification MBS66IZA 7 9 Transmit Offset Setting Register A Transmit offset setting register A is the register that sets offset value added to cycle time monitor value Its aim is to generate source packet header Time stamp added to transmit packet processed by bridge Ach Max 32 ms Time stamp value is generated on the basis of cycle time monitor value at
12. MODEO gt gt 2 2 2 TPBIAS2 mowi s p avo v0 p J aep com ______ 7 tTa _____ r a vw mo TSVALB 957 w vo L 2 vo 98 we mess 13 57 1 101 145 XTPAI 102 146 1 103 TSDB3 TPBIASI 104 Ls uo TSDBO IERRB SELIOB SELTSPB g 5 m gt N AVSS 106 AVSS 107 108 109 110 o2 t 5 N 112 113 114 115 116 117 T O 118 T O 119 T O 120 LINKON 121 T O PMODE 122 VO 23 124 T O 125 126 PBIASO N N VSS N oo N gt w N o w ON 18 o EM EM 26 EM 34 35 36 _ oo N Ne oo gt oo pA 7 0 1C Fujitsu VLSI LST Specification MBS66IZA 4 3 Outline Drawing of Packag
13. 000000 MPEG2 TS 100000 DSS 100001 The following errors occurred at bridge Bch during packet receiving gt Data length value differs f rom that specified in the format gt The value of 50 60 range at CIP header is 1 at DV receiving gt The value of STYPE range at CIP header is other than 00000 00001 at DV receiving gt value of DBC range at header is discontinuous gt Header error in CIP header gt The value of FMT range at CIP header is other than that allowed to be received at DV EN DSS EN TSEN 1Ch bit10 to 8 DV 000000 MPEG2 TS 100000 DSS 100001 109 Fujitsu VLSI LST Speci cation MBS66IZA s Z bad Bs 1 n 7 0 Isochronous cycle too long Bus occupancy violation Asynchronous packet received CPIF output header is no 47h Transmit Data length short error Data length long error Packet format error Header CRC error Data CRC error Asynchronous receive FIFO full Asynchronous packet send Input CGMS or TSCH changed Acknowledge missing Acknowledge send Receive EMI or ODD EVEN changed First packet received Isochronous cycle exceeded specified time gt Informs only if this node is Cycle master Node occupied longer time than MAX DATA TIME gt Need to issue Bus reset Received Asynchronous packet addressed to self node normally and stored data at ASYNC r
14. 1 RECOMMENDED CONNECTION FOR 1934 PORT FOR ONE 13 12 2 RECOMMENDED CONNECTION FOR CABLE POWER SUPPLY tnit 12 12 3 RECOMMENDED CONNECTION FOR BUILD IN PLL LOOP FILTER n nn 133 12 4 CONFIGURATION OF FEEDBACK CIRCUIT AT CRYSTAL OSCILLATOR I nte tret tenete ttn tita 134 Rev 7 Fujitsu VLSI LST Specification MBS66IZA Chapter 1 Overview This chapter explains the overview of 86617 MB86617A is Fujitsus IEEE1394 serial bus controller based on both IEEE1394 Standard IEEE Std 1394 1995 1394 Standard Draft rev 2 0 This MB86617A has three ports for network under the 1394 cable environment differential transceiver and comparator and the transfer data rate supports S400 MB86617A integrates PHY and LINK layers into single chip and plans for degression of component side product and saving power consumption 8661 has two exclusive ports one is the combined use for receiving a message of interface for DV for MPEG2 and DSS data transfer and performs isolating and packeting of Header and Data department with these two ports automatically This function is suited for maintaining continuum of transfer 7 0 1 Fujitsu VLSI LST Specification MBS66IZA Chapter 2 Features This chapter explains the features of MB86617A Compliant with IEEE1394 high performance serial bus standard and P1394 a standard draft Integrates PHY and L
15. 8 7 6 5 4 3 2 1 0 CUT CUT Pi a va Value pmo h ww h sn O Pinme Jom e Pm EX Automatically clears when receive process is executed by bridge Bch after setting Read at 15 Rx start B Write Executes receive process by bridge Bch Automatically clears when receive process is stopped by bridge Bch after setting at q Write 1 Stops receive process by bridge Bch Rx channel B Read Write in Isochronous packet channel to be received by bridge Bch Write MSB bit8 LSB bit3 Write Starts receive process by bridge Ach Automatically clears when receive process is stopped by bridge Ach after setting at q Write 1 Stops receive process by bridge Ach Rxch LA Read Write in Isochronous packet channel to be received by bridge Ach Write MSB bit5 LSB clears when receive process is executed by bridge Ach after setting at 1 7 Rx start A 5 Rev 1 O 52 Fujitsu VLSI LST Specification MBS66IZA 7 20 Transmit Packet Link Split Setting Register Transmit packet link split setting register is the register that sets number of link and split of source packets to be transmitted AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ial Value Value 000 ww b b Selects odd even value to be input from CP IC as odd even range of Isochronous packet header to be transmitted by br
16. DV EN Write Allows receiving DV data Read 7 0 41 Fujitsu VLSI LST Specification MBS66IZA Deletes received data and reports FMT error when MPEG2 TS data is received ISO packet header and CIP header are indicated in register TSEN Allows receiving MPEG2 TS data Does not output the packet received by bridge Ach to port B of TSP IC IF 7 TV2A Outputs the packet received by bridge Ach to port B of TSP IC I F Does not output the packet received by bridge Ach to port A of TSP IC IF 6 TVIA Outputs the packet received by bridge Ach to port A of TSP IC I F 1 Always indicates 0 reserved Always write in 0 Outputs DSS packet with DSS packet header received by bridge Bch to TSP IC in unit of 140 byte Outputs DSS packet without DSS packet header received by bridge Ach to TSP IC in unit of 130 byte Removed DSS packet header is stored at receive DSS packet header indicate register A output DSS size Outputs received data to TSP IC in synchronization with 6 144 MHz TSCLK 2 TCLKSL Write Outputs received data to TSP IC in synchronization with 3 072 MHz TSCLK Outputs to port A when TSCMP bitO is 1 Read 1 CMPSEL Write Outputs to port B when TSCMP bitO is 1 0 Does not merge packet received by Ach and Bch TSCMP Read Write 1 Outputs to one TSP IC after merging packets received by Ach and Bch Note 1 Do not set TV2B bit15 bit14 a
17. LST Specificatior M BSO6OITA Indicates that port event and resume processing have notoccurred Read Port_event Indicates that Connected Bia Disabled Fault bit has changed when Int_enable bit 1 is set 4417 Indicates that resume processing was performed when Resume Int bit is set at 1 ECAH Clears the bit value to 0 by writing in 1 Disables arbitration acceleration function Read Enab_accel Write Enables arbitration acceleration function 0 Disables multi speed packet concatenation function Enab_multi z Write 1 Enables multi speed packet concatenation function Rev 1 O 89 Fujitsu VLSI LST Specification MBS66IZA 8 8 Physical register 07 08 09 read Physical Register 07 08 09 are the registers that indicate signal condition of IEEE1394 port and cable connection condition R W Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Astat 0 Bstate 0 sta state 0 pes Astat 1 Bstate 1 peu Description of Each Bit Indicate line state of 1394 port n MSB 7 LSB 6 o i 7 6 Astat n Read 01 10 Indicate TPB line state of 1394 port n MSB 5 LSB 4 00 invalid 5 4 Bstat n Read 01 TP 10 11 Z Indicates that 1394 port n is parent port Child n Indicates that 1394 port n is children port Indicates that cable is connected to 1394 port n Always indicate 0 Ex Indic
18. Specification 7 25 7 26 7 27 7 28 7 29 7 30 7 31 7 32 7 33 PHY LINK Register Access Port Revision Indicate Register Transmit CGMS TSCH Indicate Register A Transmit CGMS TSCH Indicate Register B Transmit CGMS TSCH Indicate Status Register Transmit EMI OE Setting Register 7 0 Receive Isochronous Packet Header Indicate Register 3 B Receive Isochronous Packet Header Indicate Register 4 B FIFO Reset Setting Register Data Bridge Transmit Receive Status Register A Data Bridge Transmit Receive Status Register B Isochronous channel monitor Register cycle timer monitor Indicate Register Ping time monitor Register PHY LINK Register Address Setting Register 2 MBS66IZA Fujitsu VLSI LST Specification MBS66IZA 7 1 M ode control Register Mode control register is the register that performs the relative setting of various operation mode of this LSI AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sID Cp Iso H AE oe pn Ll i i Red Always indicate 0 15 12 reserved CPS soft reset Read li s ID store Read Note 1 Write Enable CP IC interface Needs external CP IC Read Cp_through Write Disable IC interface CP IC interface i s internally by passed PHY LINK is reset by writing 0 after writing 1 not automatic clear Note 1 Perform read modify write so as not to re wr
19. count value MSB 5 LSB 0 Does not perform bus reset 1 Performs bus reset Automatically clears to 0 at the completion of bus reset Note 1 This bit is automatically set by receiving the PHY configuration packet too Note 2 This bit is automatically set by receiving the PHY configuration packet too Also this bit value returns to initial value at the second next bus reset Rev 1 O 84 Fujitsu VLSI LST Specificatior MBS66IZA 8 4 Physical register 02 read Physical Register 02 is the register that indicates if the extended PHY register map is in existence or not and the number of ports 3 port Extended Total_ports m Description of each Bit 1 5 Extended Read Indicate that this node has PHY register map MSB 7 LSB 5 Always indicate fixed value 7 h Indicate the number of ports held by this node MSB 4 LSB 0 Rev 1 O 85 Fujitsu VLSI LST Specificatior MBS66IZA 8 5 Physical register 03 read Physical Register 03 is the register that indicates max transfer speed S400 of this node 5 Bi Bi Bt Bi Bit Bi 1 15 14 13 12 11 10 m Description of Each Bit em Indicate max transfer speed supporting PHY of this node MSB 7 LSB 5 iid Indicate Delay value at the receive signal repeat MSB 3 LSB 0 Rev 1 O 8 Fujitsu VLSI LST Specification MBS66IZA
20. register 03 lt Rev 1 O 82 Fujitsu VLSI LST Specification MBS66IZA 8 2 Physical register 00 read Physical Register 00 is the register that indicates Physical ID root status and cable power st atus of this node Bit 0 i E Bit Bit Bit Bit Bit Bit s ES pi z E P A 1 15 14 13 12 11 10 Su Description of Each Bit Indicate node No of this node determined by identify during processing bus Physical ID Read reset MSB 7 LSB 2 Effective after completion of bus reset Indicates that this node is not root Read Indicates that this node is root B Indicates that the supplied cable power is below specification Read Indicates that the supplied cable power is over specification Rev 1 O 83 Fujitsu VLSI LST Specification MBS66IZA 8 3 Physical register 01 read write Physical Register 01 is the register that set s indicates force root and gap count Do not write into this register except for the case that the node is Bus manager or Isochronous resource manager in the environment with no Bus manager i Bit Bit Bit Bit dE x e 1 15 14 12 11 10 Gap count Initial Value h Description of Each Bit F Always indicate 0 15 8 reserved This node does not try to be root during next bus reset This node tries to be root during next bus reset Indicate current gap count value MSB 5 LSB 0 Gap_count Note 2 Set gap
21. reset completed IN T3 interrupt assert XIN T interrupt busy bit 1 ENT Figure 11211 Flow example for Sef ID packet receiving before bus reset completion 7 0 16 Fujitsu VLSI LST Specificatior MBS66IZA Flow chart after bus reset completion Host Device Issue Asynchronous receive 03h instrudion Read one word from receive Asynchronous data port T data req bit 0 Issue Remove busy 04h instruction Prepare for reading received data Read one word of the received data and increment the read pointer of buffer Receive Remove busy 04h instruction busy bit 0 Clear the receive Asynchronous buffer and set FIFO according to FIFO mode Note 2 Figure 112 12 Flow example for Self ID packet receiving after bus reset completed When Asyn FIFO sel modecontrol register 3 is 1 and send rec modecontrol register 2 is 1 Asynchronous receive FIFO 256 byte and Bridge FIFO 2048 byte are used with combined as A synchronous receive buffer In other case Asynchronous receive FIFO 256 byte and Asynchronous transmit FIFO 256 byte are used with combined Note2 When Asyn FIFO sel is 1 and transmit rec is 1 Asynchronous transmitting FIFO 256 byte and Bridge FIFO 2048 byt are deared When Asyn FIFO SEL is 1 and transmit rec is 0 Asynchronous receiving FIFO 256 byte and Asynchronous transmitting FIFO 256 byte are cleared Asynchro
22. sync clock input pin for input data of TS packet TSCLKB I O On receiving sync clock output pin for output data of TS packet switchable either 6 144MHz or 3 072MHz Output pin of time stamp trigger signal L active signal LST Specification A BSO6OITA WI NU Lm Output pin for noticing error of receive data on port A H active signal Output pin for noticing error of receive data on port B H active signal LKA Clock input pin for DSS data 27MHz wax Clock input pin for DSS data 27MHz 7 0 15 Fujitsu VLSI LST Specification MBS66IZA 5 4 MPU Interface This section explains the pin function of MPU interface Address input pin for selecting internal register Available only when selecting non multi mode When selecting multiplex mode set this signal in fixed L Data I O pin Corresponding to address input signal when selecting multiplex mode 80 system mode read out strobe input pin for this device 68 system mode input pin for controlling read out write for this device 80 system mode strobe input pin for writing into ths device 68 system mode input pin of XDS signal to be output with data bus in available Input pin of ALE signal to be output with its address in available when selecting multiplex mode When selecting non multiplex mode set this signal in fixed L Output pin of DMA transfer requiring signal for DMAC Input pin of DMA allowance signal from DMAC
23. than 3 SP executes according to setting Executes 5 SP combined transmission at FIFO FULL Read Write SPQA Write in number of links for source packet processed by bridge Ach DBQA Write in number of links for source packet processed by bridge Ach SPQ 2 0 Please specify link number of source packet Note Valid setting values are 0 5 Processes assuming there are no settings from microcomputer during 0 setting When 6 7 are set it is regarded to be 5 source packet link gt DBQ 1 0 Please specify split number of source packet 00 No setting from microcomputer OL 2 splits 10 4 splits 11 8 splits 4 splits at DSS gt When the setting values of both SPQ 2 0 and DBQ 1 0 are not 0 follow the setting of SPQ 2 0 When the setting values of both SPQ 2 0 and DBQ 1 0 are 0 no setting from microcomputer LSI automatically executes link process in source packet unit Rev 1 O 54 Fujitsu VLSI LST Specificatior MBS66IZA 7 21 Late Packet Decision Range Setting Register A Late packet decision range setting register A is the register that sets Late decision range of source packet to be transmitted by bridge Ach AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 late range A Initial Value 0000 h 15 8 Write in Late packetdecision range Setting range is Oh to FFh unit 125
24. the transmit data at ASYNC transmit specific buffer beforehand Logical inverse part is added automatically by this device Rev 1 O 103 Fujitsu VLSI LST Specification MBS66IZA m Asynchronous Send 31h This instruction transmits the data stored at the ASYNC transmit specific buffer This instruction performs the following serial actions from access to arbitration by detecting arb reset gap generation and transfer of packet to receipt of Acknowledge packet When the performances from packet transmit to Acknowledge receive are normally completed this instruction reports interrupt of Asynchronous packet send INT17 In case of occurring an error it reports interrupt of error and completes performance Store the transmit data at ASYNC transmit specific buffer beforehand In case that the transmit data length does not satisfy with the quadlet unit write in 0 until quadlet unit The CRC code is to be added automatically Received Acknowledge is indicated at receive Acknowledge indicate register address O8h Note When destination ID is set at Broadcast it is completed without waiting for receipt of Acknowledge Operand Name Meaning Specify transmit Speed code MSB 1 LSB 0 00 lt 5100 1 0 Speed code 01 5200 10 S400 11 reserved Data FIFO init 63h This instruction clears the contents of buffer specified by Operand Specify buffer to be cleared MSB 7 LSB 0 11 h ASYNC rec
25. 00 h 15 8 Write in Late packetdecision range Setting range is Oh to FFh unit 125145 Read Xd Write 7 0 Write in Late packetdecision range Setting range is Oh to COh unit 16 24 576 2 Note Late packet decision is performed by comparing the time difference between SPH Source Packet Header and CTR Cycle Time Monitor Transmit Packet is transmitted normally when calculation result of SPH minus CTR for source packet transmitted from Bridhe is within the late range B 0000 h Tf it is out of range Late packet process is performed The packet concerned is deleted and transmit late is reported Set the upper 16 bit of the setting value for transmit offset setting register B 14h to 16h Receive Received packet is output at the point of SPH CTR when calculation result of SPH minus CTR for source packet received at Bridhe Bch is within the late range B 000071 the value this register is shifted 4 bits to the left If it is out of range Late packet process is performed The packet concerned is deleted and receive late is reported Rev 1 O 5 Fujitsu VLSI LST Specification MBS66IZA 7 23 Receiv e Isochronous Packet Header Indicate Register 1 A Receive Isochronous packet header indicate register 1 A is the register that indicates Isochronous packet header information received by bridge Ach AD RW Bit Bit Bit Bit Bit Bit Bit Bit B
26. 000 h Pm acion Rx SIF B Indicates SIF range of receive DSS packet header 15 28h Tx SIF B Write SIF range of transmit 055 packet header Rx System Read Indicate System clock count range of receive DSS packet header 14 0 28h clock countB MSB 28h bitl 4 LSB 2Ah bit8 15 82Ah Writ Write in System clock count range of transmit DSS packet header count B rite MSB 28h bitl 4 LSB 2Ah bit8 wee non Indicates EF range of received DSS packet header 7 2Ah Ill Write in EF range of transmit DSS packet header 6 0 QAh Indicates reserved range of receive DSS packet header 100200 reserved 15 0 Eh 15 0 30h Write Write in reserved range of transmit 055 packet header 7 0 45 Fujitsu VLSI 2Ah LST 5 pecificatior MBS66IZA 7 14 TSP Status Register TSP status register indicates status of TSP IC I F mw Bt Bit Bi Bit Bi Bi Bit Bi Bit Bi Bi Bt Bi Bi Bit 1x 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tx len TxJen dii B Por A ei ie A Indicates that CGMS information input from port B of TSP IC I F is not changed TS chg B Indicates that CGMS information corresponding to TSCH classification ID of same type input from port B of TSP IC is changed Clears to 0 by lead of this register Indicates that TS classification ID input from port B of TSP IC
27. 10 2 Interrupt 103 Description of Interrupt 7 0 106 MBS66IZA Fujitsu VLSI LST Specification MBS66IZA 10 1 Interrupt factor Indicator Register amp interrupt mask Setting Register Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 06h interrupt mask Interrupt mask interrupt factor Indicate Register This register indicate the interrupt content reported by this device Do not indicate the interrupt code specified MASK Do not reflect INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT 08h 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 W its code to XINT terminal either gt interrupt mask setting register This register masks the interrupt reported by this device Do not report the interrupt if 1 is set for Bit corresponding to interrupt factor 7 0 10 Fujitsu VLSI LST Speci 10 2 Interrupt cation 07 86677 Interrupt Interrupt Item INTI Loop detected Self ID packet error 4 Bus reset detected INTI5 Data CRC error INTs INT20 Acknowledge send INT29 INTO INTSI INT32 7 0 Self ID packet received 108 Fujitsu VLSI LST Specification 10 3 Description of Interrupt MBS66IZA Each interrupt items are described below Loop dete
28. 15 Read Write 7 0 Write in Late packetdecision range Setting range is Oh to COh unit 16 24 576MHz Note Late packet decision is performed by comparing the time difference between SPH Source Packet Header and CTR Cycle Time Monitor Transmit Packet is transmitted normally when calculation result of SPH minus for source packet transmitted from Bridhe Ach is within the late range A 0000 h If it is out of range Late packet process is performed The packet concerned is deleted and transmit late is reported Set the upper 16 bit of the setting value for transmit offset setting register A 14h to 16h Receive Received packet is output at the point of SPH CTR when calculation result of minus for source packet received at Bridhe Ach is within the late range A 0000 h the value this register is shifted 4 bits to the left If it is out of range Late packet process is performed The packet concerned is deleted and receive late is reported 7 0 55 Fujitsu VLSI LST Specification MBS66IZA 7 22 Late Packet Decision Range Setting Register B Late packet decision range setting register B is the register that sets Late decision range of source packet to be transmitted by bridge Bch AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 late range B Initial Value 00
29. 8 5 Physical Register 03 8 6 Physical Register 04 8 7 Physical Register 05 8 8 Physical Register 07 08 09 89 Physical Register 0A 8 10 Physical Register 0D OE OF 8 11 Physical Register 10 8 12 Physical Register 11 12 13 8 13 Physical Register 14 15 16 8 14 Physical Register 17 18 19 IB ID 1E 8 15 Link Register 00 8 16 Link Register 01 817 Link Register 02 8 18 Link Register 03 Rev 1 O 8C Fujitsu VLSI LST Specification MBS66IZA 8 1 PHYLINK Register Table Table of Physical Register and Link Register is shown below PHY LINK addr reserved Physical register 00 Physical register 01 lt reserved Physical register 02 reserved Physical register 03 Physical register 04 Physical register 05 reserved Physical r egister 407 EN E BN RN RN NN CNN oe see e BINNEN NR RN CN xe cm reserved Physical register 10 Eh reserved Physical register 11 reserved Physical register 12 www NEN reserved Physical register 15 reserved Physic al register 16 00h 02h 04h 06h 08h Ah OEh 10h 12h 14h 16h 18h 1 1Ch 1Dh 1 20h 24h 26h 28h 2Ah Rev 1 O 81 Fujitsu VLSI LST Specification MBS66IZA Physical register 1C lt Physical register 10 lt w Physical register 1 Link register 00 Link register 01 g Link register 02 Link
30. 8 6 Physical register 04 read write Physical Register 04 is the register that sets the parameter of Self ID packet to be transmitted by this node i i RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 zr imm m Description of Each Bit Always indicate 0 15 8 reserved Link active Read Set L bit Link active value of Sel ID packet automatically transmitted by this Note 1 Write node with the system power ON Contender Read Set c bit CONTENDER value of Self ID packet automatically transmitted by this Note 2 Write node with the system power ON Indicate Jitter value at receive signal repeat Read MSB 5 LSB 3 5 3 Jitter Always indicates fixed value 000 b 2 0 Pwr class Read Set pwr field POWER CLASS value of Self ID packet automatically transmitted Note 3 Write by this node with the system power ON Note 1 L bit value of Self ID packet that is automatically transmitted by this node with the cable supply power ON is always set at 0 regardless of the setting of this bit Note 2 c bit value of Self ID packet that is automatically transmitted by this node with the cable supply power ON is always set at 0 regardless of the setting of this bit Note 3 pwr field value of Self ID packet which is automatically transmitted by this node with the cable supply power ON is always set at the value of PWR3 1 terminal regar
31. A7 0 SELIOA SELTSPA TSVALIDB TSSYNCB On transmitting sync clock input pin for input data of TS packet On receiving sync clock output pin for output data of TS packet switchable either 6 144MHz or 3 072MHz pin for TS packet data on Port A Serial input pin for CGMS and TSCH information on port A Effective for 8 clocks since TSSYNCA input signal rising Output pin for switching I O on port A Outputs L at transmitting and F at receiving Output pin for switching output device from port A LO pin for indicating effective data period of TS packet on port B H active signal Input Output pin for indicating leading data of TS packet on port B H active signal TSDB7 0 SELIOB SELTSPB ICLK 7 0 14 Fujitsu VLSI I O pin for TS packet data on port B Serial input pin for CGMS and TSCH information on port B Effective for 8 clocks since TSSYNCA input signal rising Output pin for switching I O on port B Outputs L at transmitting and H at receiving Output pin for switching output device from port B Clock input pin from DV IC Output pin for signal to be allowed accessing to Isochronous FIFO Asserted by completing reception of data for one source packet L active signal Input signal for enable signal of Isochronous data Output Isochronous FIFO data to data output pin while this signal in active Switch data synchronizing with rise edge of ICLK On transmitting
32. C by bridge Bch is 47h Indicates that synchronization byte of received MPEG2 TS input from CP IC by bridge Bch is not 47h Clears to 0 by lead of this register Indicates that FIFO on TSP IC I F side of bridge Ach is not empty TSP FIFO Read emp A 4 1 Indicates that FIFO on TSP IC I F side of bridge Ach is empty 0 Indicates transmit data length input from TSP IC I F is normal Indicates transmit data length input from TSP IC I F is not consistent with specified format data length Deletes transmit data without writing into FIFO Clears to 0 by lead of this register T x length err A Read Indicates that FIFO on TSP IC I F side of bridge Ach is not full 4 TSP FIFO Read full A 1 Indicates that FIFO on TSP IC I F side of bridge Ach is full 7 0 47 Fujitsu VLSI LST Specification MBS66IZA 7 15 Data Bridge Transmit Information Setting Register 1 A Data bridge transmit information setting register 1 A is the register that sets CIP header range added to transmit packet processed by bridge Ach Tx SID A Tx DBS A FN A Read Write in SID range of transmit header i TESIDSA L MSB 515 LSB bit 10 Write m DBS range of transmit CIP header Read MSB bit9 LSB bit2 222 TxDBS A write MPEG2 TS at transmit 000001 10 b DSS at transmit 00001001 b Write in EN range of transmit CIP header Read MSB bit1 LSB 120 TEES Write MPEG2 TS at transmit 11
33. CEIVE INFORMATION SETTING REGISTER tente treten tette tette tette tette te esto 52 7 20 TRANSMIT PACKET LINK SPLIT SETTING REGISTER iesseeeee eene nnne ann nanan 53 7 21 LATE PACKET DECISION RANGE SETTING REGISTER A ten tette tin 55 7 22 LATE PACKET DECISION RANGE SETTING REGISTER B nter tnter tenter tette 56 7 23 RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 1 A JII I 57 7 24 RECEIVE HRONOUS PACKET HEADER INDICATE REGISTER 2 JII nnne nn 58 7 25 RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 3 nennen nn 59 7 26 RECEIVE ISOCHRONOUS PACKET HEADER INDICATE REGISTER 4 B nter tentent tnr tentes 60 72T FIFO SETTING REGISTER t notam dac ct e ofer c ed qua 61 7 28 DATA BRIDGE TRANSMIT RECEIVE STATUS REGISTER A eere rennen tnter 62 7 29 DATA BRIDGE TRANSMIT RECEIVE STATUS REGISTER B nter tentent nnne tinta tinto te 65 7 30 ISOCHRONOUS CHANNEL ONITOR REGISTER serere rente an 68 7 31 CYCLE TIMER MONITOR INDICATE 58 11111 69 Rev 1 O iii Fujitsu VLSI LST Specification MBS66IZA 1 32 PING MONITOR REGISTER
34. I F is not changed Indicates that TSCH classification ID input from port B of TSP IC I F is not consistent with TSCH classification ID 10h bit12 to 7 set TS ID A or 12h bit12 to 7 set TSID B to be stored to FIFO Clears to 0 by lead of this register Indicates that transmit data length input from TSP IC I F is not consistent with specified format data length Deletes transmit data without writing into FIFO Clears to 0 by lead of this register TSP FIFO b emp B T x length err Rev 1 O 4 Fujitsu VLSI E 1 Indicates that synchronization byte of received MPEG2 TS input from CP IC by 0 bridge Bch is 47h 13 no 47h B Read Indicates that synchronization byte of received MPEG2 TS input from CP IC by 1 bridge Bch is not 47h Clears to 0 by lead of this register 11 LST Specificatior MBS66IZA Indicates that CGMS information input from port A of TSP IC I F is not changed i Indicates that CGMS information input from port A of TSP I F is changed Clears to 0 by lead of this register Indicates that TS classification ID input from port A of TSP IC I F is not changed Indicates that TSCH classification ID input from port B of TSP IC I F is not consistent with TSCH classification ID 10h bit12 to 7 set TS ID A or 12h bit12 to 7 set TSID B to be stored to FIFO Clears to 0 by lead of this register Indicates that synchronization byte of received MPEG2 TS input from CP I
35. INK layers into single chip gt 1394 port number 3 ports gt Transfer Data Rate 5100 5200 5400 On chip PLL corresponding to Crystal Osci llator generate internal clock gt 4K Byte X 2 channels Isochronous transmit and receive data buffer 256Byte Asynchronous exclusive buffer for transmit receive gt Auto isolating and packeting for received header and data of packet gt Two exclusive ports for Isochronous transfer 8 bit bus gt Loading interface with copy protection LSI 8 bits I O gt Generating and Checking Function for 32bit CRC gt 6 pin cable supported gt Power supply system 3 3V size D battery gt Package LQFP 176 176 03 Rev 1 O 2 Fujitsu VLSI LST Specification MBS66IZA Chapter 3 Chip Block This chapter explains the MB86617A block diagram and the function of each block 3 1 Block Diagram 3 2 Function of Each Block Rev 1 O 3 Fujitsu VLSI LST Specification 3 1 Block Diagram MB86617A block diagram is shown below Normal Operation Mode Asynch Transmit Exclusive FIFO 256 byte 2 zb x 3 D 3 D 5 9 Asynch Transmit Exdusive FIFO 256 byte PHY LINK FIFO FIFO Layer a Control 5 2KByte KByte Circuit S s 5 S 5 5 8 g 9 D 5 5 2 M FIFO 2KByte CP IC Interface Fig 3 1 1 Block Diagram Normal Operation Mode 7 0 4 MBS66IZA TPAO XTPAO TPBO
36. IZA 7 5 Receive Acknowledge Indicate Register Receive Acknowledge indicate register is the register that indicates received Acknowledge packet addressed to itself Read out this register after interrupt report of Asynchronous packet send AD R W Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Receive Indicate code of received Acknowledge packet addressed to it Receive Indicate parity of received Acknowledge packet addressed to it par mE MSB LSB Note In case of not receiving Acknowledge within specified time this register indicates and reports interrupt of Acknowledge missing Rev 1 O 33 Fujitsu VLSI LST Specificatior MBS66IZA 7 6 A buffer Data Port Receive Transmit This integrated register is the buffer access port for both ASYNC receive specific buffer and ASYNC transmit specific one Read data is able to be read out IEEE1394 packet data in the order received MSB 15T read Write data is transmitted as IEEE1394 packet data in the order written in MSB 157 write Bit Bit Bit Bit Bit Bit T E 5 p E 15 14 13 12 11 10 ASYNC Receive Specific Buffer Data ASYNC Transmit Specific Buffer Data Initial Value Undefined Read Read out port of Asynchronous receive specific buffer 5 i MSB bit15 LSB Write Write in port of Asynchronous transmit specific buff
37. LST Specification MBS66IZA IEEE1394 Serial Bus Controller for DTV 86617 LSI Specification Rev LO August 16 2001 Rev 1 O i Fujitsu VLSI LST Specification MBS66IZA Contents CHAPTER 1 OVERVIEW 1 CHAPTER 2 FEATURES rrr U U U RN EN RN NEN NEN NEN AERA AR A UL RN E RN EN RN NEN EN E EN uuu uu ul QQ 2 CHAPTER 3 CHIP BLOCK rrr U U EN EN NEN NEN EN NE A U RN uuu QQ ul uu 3 Ses 4 BNORMAL OPERATION M ODE wat ai s qhaaaqq dre e eeu d t o a i u t Ve D 4 ASYNCHRONOUS TRANSMIT FIFO EXTENDED MODE nter tte tte 5 ASYNCHRONOUS RECEIVE FIFO EXTENDED n ttt 6 3 2 FUNCTION OF EACH BLOCK e e re Ve be ec 7 a PHY LAYER CONTROL tea odere te ic a attt pros ca erre pce det boten ott 7 mI LAYER CONTROL C IRCU IT a an aaa aaah a ecc E 7 B INTERFACE zi emer ayaq o ta p ode n o E RR ae cento de red RIT 7 E CP GIN TERRACE Ss
38. OOh unit 1 24 576MHz 7 0 4C Fujitsu VLSI LST Specification MBS66IZA 7 11 TSP Receive Information Setting Register TSP receive information setting register performs the setting for outputting received packet to TSP IC AD gw Bt Bit Bt Bi Bi Bit Bt Bit Bi Bt Bit Bt Bit Bi Bt Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ouput 1 RW TV DS EN TV2A TVIA m 3t MP sze B ae Does not output packet received by bridge Bch to port B of TSP IC IF Outputs packet received by bridge Bch to port B of TSP IC I F 0 Does not output packet received by bridge Bch to port A of TSP IC I F i Outputs packet received by bridge Bch to port A of TSP IC Always indicates 0 reserved Always write in 0 output DSS Read size B Write Outputs DSS packet received by bridge Bch with DSS packet header attached to TSP IC in unit of 140 byte Outputs DSS packet received by bridge Bch without attachment of DSS packet header to TSP IC in unit of 130 byte Removed DSS packet header is stored at receive DSS packet header indicate register B Deletes received data and reports FMT error when DSS data is received ISO packet header and CIP header are indicated in register Allows receiving DSS data 0 Deletes received data and reports FMT error when DV data is received ISO packet header and CIP header are indicated in register Read
39. Output pin for interruption request 7 0 1 Fujitsu VLSI LST Specification 5 5 Other Pins MBS66IZA This section explains the pin function like internal PLL LINKON TESTI 7 7 0 Input signal for resetting signal When operating with cable supply power set this pin to This pin is used for setting operating mode of MPU This device is operated as follows depending on the setting of and MODEO pins 00 input TX1940 mode 01 input MB90F574 mode 10 input 80 system non multiplex mode input 68 system non multiplex mode Exterior type crystal connecting pin for oscillator circuit 24 576MHz Connect to GND through 5 1kQ register Exterior type filter circuit connecting pin for internal PLL Connect to GND through 5 1kQ register Power supply input pin from IEEE1394 cable Detect cable supply power 0 to 33V requiring of lowering dividing voltage Criterion pin for inputting power L input operate with power supplying through IEEE1394 cable H input operate with system power Setting pin got POWER CLASS of Self ID packet to be transmitted when operating with supply power through cable Note The POWER CLASS of the Self ID packet to be sent when operating under the system power does not use this pin but follows the setting of Pwr bit Bit2 to 0 of Physical Register 4 Output pin for detecting Link on packet receive Output when recei
40. READ WRITE a te tenista 87 8 7 PHYSICAL REGISTER 05 READ WRTIE saa erc e eic ert n d e dc ved ee a xs e c 88 8 8 PHYSICAL REGISTER 07 08 09 READ wu cccsssssssssssssssesssssssssssesssesssesecssecsuecsvecseeususesusesssesssesesesanesesesasesacsvasseeueusesusesustensesesesanesanesaseres 90 8 9 PHYSICAL REGISTER 0A OB READ WRITE 91 8 10 PHYSICAL REGISTER 0D OE OF READ WRITE eren 92 SAX T PHYSICAL REGISTER 10 READ trente noir cin ec m cta e rte tits i e c e n a onc oca ona ec rl n RE SE Eva d 93 8 12 PHYSICAL REGISTER 12 13 READ iiic ttbi e e Hat ced ce p dnb dp d dee ded pos 94 8 13 PHYSIGAL REGISTER 15 16 READ e aq d e e ed ia a e E DUE 95 8 14 PHYSICAL REGISTER 17 18 19 IC ID 1E I nnne enne nnn nn 96 8 15 LINK REGISTER 00 READ WRITE iicet dato nera c ea gl ara e ien aed er bcc c ean cca toca ccce bc se 97 8 16 LINK REGISTER 01 READ WRITE ro Ee d d 98 8 17 LINK REGISTER 02 READ WRITE tiet eere i a A ae aA 99 8 18 LINK REGISTER 03 READ WRITE eerte nnne
41. Read Sdf ID packet received interrupt INT29 Figure 112 221 Flow example of operation from Pin packet transmitting to Self ID packet receivin Rev 1 O 118 Fujitsu VLSI LST Specification MBS66IZA m Flow chart after receiving Self1D packet Host Device Issue Asynchronous receive 03h instruction Preparefor reading received data Read the data of one word from Read one word of received data and receive Asynchronous data port increment the read pointer Read flag amp status register 0 Issue Remove busy 04h instruction 4 Receive Remove busy 04h instrudion FIFO remote modefor receiving completed recv busy bit 0 Figure 1 2 2 2 Flow example after receiving Sef ID packet Rev 1 O 119 Fujitsu VLSI LST Specification MBS66IZA 11 3 Asynchronous Packet Transmitting The example of control flow for transmitting of Asynchronous packet is shown below m Flow chart before storing transmitting data into Asynchronous transmit FIFO Host Device Write data for 1 word Asynchronous transmit buffer and inarement the write pointer Write one word the data to be transmitted in Asynchronous transmit data port Number of residual transfer byte Number of residual transfer byte minus 2 Number of residual transfer byte gt 0 Figure 1131 Flow chart before storing transmitting data in Asynchronous transmit Notel Store the data to b
42. Rev 1 O 2 Fujitsu VLSI LST Specification MBS66IZA 7 2 flag amp status Register flag amp status register indicates the status of this LSI and data access inquiries Bit Bit Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bit 15 14 13 12 u 0 9 8 7 6 5 4 3 2 1 0 PC tan tan pue ine 2 busy ready busy empty empty ES Indicates that receipt of instruction is available busy Read Indicates that receipt of instruction is not available Indicates that bus reset or forced sleep is being executed and transmit receive of packet is unavailable tran ready Read Indicates that bus reset is completed and forced sleep is not being executed and transmit receive of packet is available Indicates that packet transmit is not being executed or in the process of packet receive addressed to this node tran busy Read Indicates that packet transmit is being executed or in the process of packet receive addressed to this node Indicates that Isochronous cycle is not being executed ISO cycle Read Indicates that Isochronous cycle is being executed by transmit or receive of cycle start packet Indicates that Asynchronous transmit specific buffer is not empty A T x buff Read Empty Indicates that Asynchronous transmit specific buffer is empty Indicates that Asynchronous receive specific buffer is not empty A Rx buff Empty Indicates that Asynchronous receive specif
43. able Write reserved LINK layer is disabled LINK layer is enabled Always indicates 0 Always write in 0 Always indicates 0 reserved LST Specification MBS66IZA 8 18 Link register 03 read write Link Register 03 is the register that performs Link layer reset and initializes setting of the node phy ww Be Bi Bi Bi Bi Bi Bi Bt Bi Bi Bi Br Bi Bi Bie Bi s 15 I Litas 12 8 7 6 5 4 3 2 1 0 m Description of Each Bit Always indicate 0 15 2 reserved Always write 0 REN Read Link init Releases initialize of LINK layer Initializes LINK layer Resets LINK layer 0 Releases reset of LINK layer Link reset Read ink rese Write E 1 7 0 100 Fujitsu VLSI LST Specification MBS66IZA Chapter 9 Instruction This chapter explains the instruction codes and details for respective instructions 9 1 Instruction Code Table 9 2 Description of Each Instruction 7 0 101 Fujitsu VLSI LST Specification A BSO6OITA 9 1 Instruction Code Table emm Asynchronous receive 03 Remove busy mode 04 Send PHY packet 21 Asynchronous Send 31 Speed code rra pere gt REC Rev 1 O 102 Fujitsu VLSI LST Specificatior MBS66IZA 9 2 Description of Each Instruction m Start sleep 01h This instruction changes this device into forced slee
44. alue added to IPH of empty packet until valid data is transmitted after starting transmission Selects the setting value of IPH EMI A bit6 to 5 and IPH OE A bit 4 as EMI information and Odd Even value added to IPH of empty packet until valid data is transmitted after starting transmission 11 reserved 1 Read 7 IPH select A NE Rev 1 O 78 Fujitsu VLSI LST Specificatior MBS66IZA Set EMI information which are set in IPH of empty packet transmitted from bridge Ach Read Valid only when select A bit7 is set to 6 5 IPH Write MSB bit6 LSB bit5 EMI information after transmitting valid data depends on the setting of EMI select A 10h bit4 Set Odd Even value which is set in IPH of empty packet transmitted from Read bridge Ach 4 IPH OE A Write Valid only when select A bit7 is set to EMI information after transmitting valid data depends on the setting of o e select A 3Eh bit8 Read Always indicate 0 3 0 reserved Write Always write in 0 Rev 1 O 73 Fujitsu VLSI LST Specification MBS66IZA Chapter S PHY INK Register Function Description This chapter explains the Physical Register and Link register that enables to access from PHY LINK register access port address 62h by setting PHYT LINK register address setting register address 60h in detail 8 1 PHY LINK Register Table 8 2 Physical Register 00 8 3 Physical Register 01 84 Physical Register 02
45. ates that cable is not connected to 1394 port n 2 Connected n Rev 1 O 9C Fujitsu VLSI LST Specification A BSO6OITA 8 9 Physical register 0A 0B 0C read write Physical Register 0A OB OC are the registers that indicate bias detect condition of IEEE1394 installed in this node and performs setting of enable disable of IEEE1394 port phy 2 Dsabl ed1 Bis2 5 m Description of Each Bit DES Always indicates 0 15 2 reserved Indicates that bias voltage is not detected at 1394 port n Read Bias n Indicates that bias voltage is detected at 1394 port n write Always indicates 0 Read Enables 1394 port n Write ER 1 Disable 1394 port n Rev 1 O 91 Fujitsu VLSI LST Specification MBS66IZA 8 10 Physical register 0D 0E read write Physical Register 0D are the registers that indicate maximum transfer speed of the node connected to IEEE1394 port installed in this node R Negotiated_speed 0 18 Int en abe 0 W Negotiated speed 1 lAh Int en 1 Negotiated speed otiated speed 2 Negotiated speed P Int en Ie r m Description of Each Bit J Red Always indicates 0 reserved Write Always write in 0 Indicate max transfer speed between nodes connected to 1394 port n MSB 7 LSB 5 Rei 000 S100 Negotiated_ i 001 S200 speed n 010 S400 011 111 invalid Does not indicate 1 at Port_event bit w
46. channel No TXFMTB 21h TXCHB Iso channel No 4001 Set criteria for Late packet Ach Set criteria for Late packet Bch Set at Ach transmitting TXSTA Z1 TFA TXFMTA 1 IDSIZEA 1 DSS130 Set at Bch transmitting TXSTB 1 TFB TXFMTB 1 IDSIZEB 1 DSS130 Set at Ach transmitting 1 TFA Set at Bch transmitting TXSTB 1 TFB Rev 1 O 127 Fujitsu VLSI LST Specification MBS66IZA 11 6 Isochronous Packet Receiving The example of control flow for receiving Isochronous packet is shown below Host Device Set necessary datato registers such as Bridg and TSPIF Se value to registers such as Bridge and TSPIF N ote CP LSI and storeit in FIFO at TSPIF Report Receivelate occurred IN T 30 interrupt assert XINT Discard source packet Read Receive late occurred INT30 interrupt Output source packet from the TSPIF port when the value of source packet header equals to the value of cydetimer Figure 11 6 Flow example for transmitting Isochronous packet Rev 1 O 128 Fujitsu VLSI LST Specification MBS66IZA N ote Register and bit necessary for receiving are as follows Data MPEGTS TSPSB 0 5 0 TSEN 1 DSSEN 1 Set TVIA TV1B TV2A TV2B Set TV1A TV1B TV2A TV2B Set TV1A TV1B TV 2 TV2B according to Ch received according to Ch received according to Ch received and port port Set criteria for Late pac
47. commended connection for build in PLL loop filter is shown below RF FIL 3900 5 5 1KQ 5 3300pF 5 Figure 123 Recommended connection for build in PLL loop filter Rev 1 O 133 MBS66IZA Fujitsu VLSI LST Specification MBS66IZA 12 4 Configuration of Feedback Circuit at Crystal Oscillator The example of configuration of feedback circuit at crystal oscillator is shown below No outside resistance is needed because the feedback resistance is built in 20 20 Figure 124 Configuration of feedback circuit at crystal oscillator Rev 1 O 134 Fujitsu VLSI
48. cted Self ID packet error Bus reset complete Bus reset detected Isochronous packet receive error A ch Isochronous packet receive error B ch 7 Topology is in Loop gt Need to issue reset Occurred convention failure like Physical ID did not count up each Self ID packet received during Self Identify process gt Continues to receive Self ID packet after reporting interrupt but reports Bus reset complete 05h interrupt Detected logical inverse error while receiving Self ID packet after sending Ping packet in normal transfer mode gt Delete receive packet This device has completed Bus reset process and able to perform packet transfer gt All the follows Bus reset Tree Identify and Self Identify are completed by this interrupt information Reset Bus reset in any of the following conditions gt Detected BUSRESET signal from other node gt Received Bus reset The following errors occurred at bridge Ach during packet receiving gt Data length value differs from that specified in the format gt The value of 50 60 range at CIP header is 1 at DV receiving gt The value of STYPE range at CIP header is other than 00000 00001 at DV receiving gt The value of DBC range at CIP header is discontinuous gt Header error in CIP header gt The value of FMT range at CIP header is other than that all owed to be received at DV EN DSS EN or TSEN 1Ch bit10 to 8 DV
49. dicate Product ID of this chip MSB 7 LSB 0 Rev 1 O 95 Fujitsu VLSI LST Specification MBS66IZA 8 14 Physical register 17 18 19 1A 1B 1C 1D 1E read write Physical Register 17 18 19 1A 1B 1C ID 1E are in the range of 8 bit X 8 Free RAM SEIS DIM pepe C m Description of Each Bit Always indicates 0 15 8 reserved Write Rev 1 O 9 Fujitsu VLSI LST Specification MBS66IZA 8 15 Link register 00 read write Link Register 00 is the register that sets this node to operate as cycle master phy ww Be Bt Bi Bi Bt Bi Bi Bi Bt Bi Bi Bi Bi Bi Bi 2 15 a3 12 o 9 8 7 6 5 4 5 2 1 0 m Description of Each Bit Always indicate 0 15 6 reserved Does not cycle master Read cycle master as cycle master if it is root m Sets the value of this bit at 1 by writing in Always indicate 0 4 0 reserved Always write in 0 Rev 1 O 97 Fujitsu VLSI LST Specification MBS66IZA 8 16 Link register 01 read write Link Register 00 is the register that sets this node to perform as cycle master phy ww Be Bi Bit Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi Bi 2 15 a3 12 9 8 7 6 5 4 5 2 1 0 m Description of Each Bit 34 Always indicate 0 15 6 reserved Does not cycle master 7 Ed cycle master Per
50. dless of the setting of this bit Rev 1 O 87 Fujitsu VLSI LST Specification MBS66IZA 8 7 Physical register 05 read write Physical Register 05 is the register indicating availability of cable supply power standard and timeout detect of arbitration state machine Bit B 2 0 ww Bt Bi Bit Bi Bi Bi Bi Bi Bi Be Bi Bi it Bit link Il lil 8 7 6 5 4 3 1 0 Rane Pwr Time Port Hb m Description of Each Bit Red Always indicate 0 15 8 reserved Read Does not indicate 1 at Port event bit during resume processing 7 Resume Int Write 1 Indicates 1 at Port event bit during resume processing Read B Read Loop Does not perform short bus reset Performs short bus reset Automatically clears to 40 at the completion of bus reset Indicates that port connection is in a loop Indicates that port connection is in a loop Clears the bit value to 0 by writing in 1 Read Timeout Rev 1 O 88 Fujitsu VLSI Clears the bit value to 0 by writing in 1 Indicates that timeout is not detected by arbitration state machine Indicates that timeout is det ected by arbitration state machine Indicates that the cable supply power satisfies the standard Read 4 Indicates that the cable supply power does notsatisfy the standard 1 Clears the bit value to 0 by writing in 1
51. e This section shows the outline drawing of MB86617A package LQFP 176 FPT 176P M03 75 7 LOFP 1762 7 2 x 595 2 amp amp FPT 176P M03 FSAF vO LOFP 1762 FPT 176P M03 22 00 0 3X B6 012150 1721467 27 NOM NOM eon cl A part 1 1 Ki 4 1 poro 1905 FUJITSJ UMITED FT7R07S YC 1 Wh mm liches 7 0 11 Fujitsu VLSI LST Specificatior MBS66IZA Chapter 5 Pin Function This chapter explains the MB86617A pin function 5 1 IEEE1394 Interface 52 Isochronous TSP IC DV IC Interface 5 4 MPU Interface 5 5 Other Pins 5 6 Power GND Pin Rev 1 O 12 Fujitsu VLSI LST Specification MBS66IZA 5 1 IEEE1394 Interface This section explains the pin function of IEEE1394 interface T O T O pin of TPA minus signal on cable port 0 T O T O pin of TPB plus signal on cable port 0 Output pin of reference voltage for common voltage on cable port 1 EI Output pin of reference voltage for common voltage on cable port 2 Rev 1 O 13 Fujitsu VLSI LST Specification MBS66IZA 5 2 Isochronous Interface This section explains the pin function of Isochronous interface TSVALIDA VO LO pin for indicating effective data period of TS packet on port A F active signal TSSYNCA pin for indicating leading data of TS packet on port A H active signal TSCLKA TSD
52. e Check Header CRC OK NG Report Header CRC Error IN T14 Read Header CRC Error IN T14 interrupt a interrupt and duscard received packet Packet receiving process completed rev busy bit 0 1 Transmit Ack busy X and discard received packet Packet receiving process completed Store Asynchronous into Asynchronous receive buffer Transmit cknowledge packet Receive buffer full Read Asynchronous Receive FIFO Report A synchronous Receive FIFO full full IN T16 INT16 interrupt assert XIN T Read Asynchronous packet m Report Asynchronous packet receive received IN T9 INT9 interrupt assert XINT rew busy bit 1 Packet receiving process completed Figure 114 1 Flow example for received data before storing in Asynchronous receive FIFO Rev 1 O 123 Fujitsu VLSI LST Specification MBSCOITA m Flow chart for received data after storing in Asynchronous receive FIFO lt Host gt lt Device gt Issue Asynchronous receive 03h instruction Read 1 word of the data from receive Asynchronous data port Read flag amp status register 0 Issue Remove busy 04h instruction 4 Prepare for reading received data Read 1 word of received data and increment read pointer of receive buffer Receive Remove busy 04h instruction Receive FIFO read mode completed rew busybit 0 Figure 1142 Flow chart for received data after storing in Asynchronous receiv
53. e FIFO Notel If the length of received data 15 quadret digid it is stored by quadret unit Note2 CRC codeis not induded in the data Rev 1 O 124 Fujitsu VLSI LST Specification MBS66IZA 11 5 Isochronous Packet Transmitting The example of control flow for transmitting Isochronous packe is shown below Rev 1 O 125 Fujitsu VLSI LST Specification MBS66IZA lt amp gt Device Set necessary data to registers such as Set valueto registers such as Bridge and TSPIF Input the poko sans and deck m Storesource packet in FIFO at TSPIF Transmit source packet to CP LSI Bridg and TSPIF N ote Receive processed source packet from CP LSI and storeit in FIFO at Bridge Yes Arbitration procedure Arbitration result Lost Won Transmit Late evaluation Transmit Late Read Transmit late occurred IN T32 __ l __ Report Transmit late occurred IN T32 interrupt interrupt assert XIN T Discard source packet and transmit empty packet Connect source packet according to register setting and transmit Figure 11 5 Flow example for transmitting Isochronous packet Rev 1 O 126 Fujitsu VLSI LST Specification MBS66IZA Note Register and bit necessary for transmitting are as follows aues MPEGTS 08 TSPSB 0 CPSB 0 CPSB 0 16h x value of 1 O 38h DBSB 06h FN B 3h DBSB 09h FN B 2h TXFMTB 20h TXCHB Iso
54. e MPEG2 TS at transmit 000001 10 b DSS at transmit 00001001 b Write in FN range of transmit CIP header Read MSB bitl LSB Write MPEG2 TS at transmit 11 b DSS at transmit 10 b Rev 1 O 5C Fujitsu VLSI LST Specification MBS66IZA 7 18 Data Bridge Transmit Information Setting Register 4 B Data bridge transmit information setting register 4 B is the register that sets CIP header range transmit channel and speed added to transmit packet processed by bridge Bch ETE Tx FMT B SE Tx channel B Tx speed B d d B NEN Writein FMT range of transmit header Read MSB 5 LSB bit 10 Sod US Write MPEG2 TS at transmit 100000 b DSS at transmit 100001 b _ gt Tx TSF B ESSEN Writein TSF range of transmit CIP header 8 3 Tx ch LB Read Writein channel range of transmit Isochronous packet header ARSE Write MSB bit8 LSB bit3 Write in transmit packet speed Read MSB bit2 LSB bitl 2 1 Tx speed B Write 100 at transmit 00 b 200 at transmit 01 b 5400 at transmit 10 b mao Always indicates 0 reserved Always writes in 0 7 0 51 Fujitsu VLSI LST Specification MBS66IZA 7 19 Data Bridge Receive Information Setting Register Data bridge receive information register performs the setting of receive packet AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9
55. e transmit previously in Asynchronous transmit FIFO Note2 If the transmitting length is below the digit of quadret write 0 there up to quadret unit Note3 The device can automatically attaches CRC code Rev 1 O 120 Fujitsu VLSI LST Specification MBS66IZA m Flow chart after storing transmitting data into A synchronous transmit FIFO Host Device RexiveAsynd roncustrensrrit 31h insrudion IssueAsyrd ronoustransmit 3Ih instruction Read Asynchronous transmit buffer Arbitration procedure Arbitration result Lost i Won Transmit Asynchronous packet After the transfer of DATA_END release bus and wait Asynchronous Acknowledge received No YS Store receive Acknowledge packet in receive Acknowledge indication register Read Asynchronous packet transmit Report Asynchronous packet send INT17 interrupt m IN T17 interrupt assert XIN T Read Ad nowledge missing IN T20 Report Acknowledge missing IN T20 interrupt interrupt assert XINT Figure 11 3 2 Flow chart after storing transmitting data in Asynchronous transmit FIFO Rev 1 O 121 Fujitsu VLSI LST Specification MBS66IZA 11 4 Asynchronous Packet Receiving The example of control flow for receiving Asynchronous packet is shown below Rev 1 O 122 Fujitsu VLSI LST Specification MBS66IZA m Flow chart for received data before storing Asynchronous receive FIFO Host Device Receive packet to self nod
56. eader range of DSS packet received by bridge Ach E 5 Rx System clock count A high s omm TED om NEN ERE CK NN ERE NN reserved Initial Value 0000 h Rx SIF A Indicates SIF range of received DSS packet header 15 1Eh Tx SIF A EJGEN Write in SIF range of transmits DSS packet header Rx System Indicate System clock count range of received DSS packet header 14 0 1Eh clock count A MSB 1Eh bit14 LSB 206 68 15 820h T x System Write in System clock count range of transmit DSS packet header clock count A MSB 1Eh bit14 LSB 206 68 Indicates EF range of received DSS packet header 7 20h Write in EF range of transmits DSS packet header 6 0 20h Indicates reserved range of received DSS packet header 15 0 22h 15 0 24h 15 0 26h reserved Write in reserved range of transmit DSS packet header 7 0 44 Fujitsu VLSI LST Specification MBS66IZA 7 13 Receive DSS Packet Header Indicate Register B Transmit DSS Packet Header Setting Register B DSS packet header indicate register B indicates DSS packet header range of DSS packet received by bridge Bch Transmit DSS packet header setting register B sets DSS packet header range of DSS packet received by bridge Bch Rx System clock count B high T x System clock count B high Rx maximum bit rate B low reserved j S S S o e S SOS EA reserved Initial Value 0
57. eceive specific buffer Header byte of source packet output from CPIF at transmitting MPSG2 TS is not 47h Valid only when transmitting MPSG2 TS Receive packet data length is shorter than data length of packet header Receive packet data length is longer than data length of packet header gt Store only data indicated by data length value to buffer Detected format error in packet received Occurred convention failure of packet format like Reserved range is not 0 gt Delete packet received Detected CRC error in the header of packet received gt Delete packet received Detected CRC error in the data range of packet received gt Do not delete packet received ASYNC receive specific buffer is full gt Delete following packet received Completed sending Asynchronous packet by issueing instruction CGMS or TSCH information input from TSP IC I F was not consistent with the souce packet input just before Not returned Acknowledge packet in correspondance with Asynchronous packet of non broadcast sent from self node within specified limit Completed sending Acknowledge packet Changede EMI data or ODD EVEN value of received Isochronous packet Received the first packet after setting receive ISO channel 110 Fujitsu VLSI LST Specification A Boool17A Received cycle start packet normally when self node is not root gt Isochronous cycle starts Set ISO cycle Bit Bit12 of flag amp status registe
58. eive specific buffer 12 ASYNC transmit specific buffer Other than above reserved FIFO select code 7 0 104 Fujitsu VLSI LST Specification MBS66IZA DMA Transmit Asynchronous 71h This instruction writes in the transmit Asynchronous packet to ASYNC transmit specific buffer using DMA transmit Assert DREQ signal after issuing this instruction Determine the transmit bite value by transmit data length within packet header write in up to quadlet unit then negate DREQ signal After completion of writing in issue the Asynchronous send instruction 31h DMA Transmit PHY packet 72h This instruction writes in the transmit PHY packet to ASYNC transmit specific buffer using DMA transfer Assert the DREQ signal after issuing this instruction Negate the DREQ signal after writing in 2 bites After completion of writing in issue the Send PHY packet instruction 21h Receive 73h This instruction reads out the data stored in ASYNC receive specific FIFO using DMA transfer Issue Asynchronous receive instruction 03h before issuing this instruction Assert DREQ signal after issuing this instruction Negate DREQ signal when ASYNC receive specific FIFO is empty Rev 1 O 105 Fujitsu VLSI LST Specificatior Chapter 10 Interrupt This chapter explains the inturrput factors and method for interrupt mask 10 1 Interrupt factor Indicator Register amp interrupt mask Setting Register
59. en Rx start B 3Ch bit15 is set at 1 and receive process is started Indicates that received Isochronous packet after starting receive process is not the first receive packet Indicates that EMI information of receive Isochronous packet header is not changed Indicates that EMI information of receive Isochronous packet header has changed from just former EMI information of packet received by Isochronous cycle Clears to 0 by lead of this register Indicates that odd even information of receive Isochronous packet header is not changed Indicates that odd even information of receive Isochronous packet header has changed from just former odd even information of packet received Isochronous cycle Clears to 0 by lead of this register Rx 15 Read Indicates that the first Isochronous packet is received after starting receive process 1 Clears to 0 by lead of this register 0 1 Rx EMI a Rev 1 O 65 Fujitsu VLSI LST Specificatior MBS66IZA Indicates that data length of receive packet is same as specified data length in 0 format 10 Rx dlen err B Read Indicates that data length of receive packet differs to the specified data length in the 1 format Clears to 0 by lead of this register Indicates that transmit packet is transmitted normally Tx late B Indicates that transmit packet became Late packet Delete packet and not transmit Clears to 0 by lead of this register
60. er 2 MSB 515 LSB Rev 1 O 34 Fujitsu VLSI LST Specification MBS66IZA 7 7 TSP Transmit Information Setting Register A TSP transmit information setting register A is the register that makes settings for transmit packet processed by bridge Ach AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set TSID A im select set EMI A count mk 0 Automatically clears when transmit process is started with bridge Ach after setting Read at Write 1 Starts transmit processing with bridge Ach Automatically clears when transmit process is stopped by bridge Ach after setting Read at Write Stops transmit process by bridge Ach 15 Tx start A Tx end A Processes transmit data as MPEG2 TS Tx form A Processes transmit data as DSS packet Processes transmit 055 packet as 140 byte input DSS size A 1 Processes transmit DSS packet as 130 byte Outputs to SELTSPA output terminal 13 Tx select A Outputs H to SELTSPA output terminal Set TSCH classification ID to be stored at HFO of bridge Ach ist DD i MSB bit12 LSB bit7 Rev 1 O 35 Fujitsu VLSI LST Specificatior MBS66IZA Selects CGMS information input from TSP IC as EMI information to be output to CP IC Read 4 EMI select A Write Selects setting value of set EMI A bit3 to 2 as EMI information to be output to CP IC Read Set EMI
61. er Ping Packet Transmitting 7 0 14 Fujitsu VLSI LST Specification MBS66IZA 11 2 1 Self ID Packet Receive at Bus Reset Process This section explains the receiving process of Self ID packet The MB86617A device is capable of receiving self ID packets that each mode transmit in the self identity stage of bus reset process When is written to the 510 store bit of mode control register refer to 7 1 the self ID packet in the bus reset process can be received and the data removing the logical inverse section is stored in the Asynchronous receive FIFO and Asynchronous transmit FIFO 512 bytes maxixum When the number of total data exceeds 512 bytes the overflown data are discarded Bus reset force dears FIFO for Asynchronous receiving and FIFO for Asynchronous transmitting to store Sdf ID packet Rev 1 O 15 Fujitsu VLSI LST Specification MBS66IZA m Flow chart before bus reset completion Host Device Start bus reset Read Bus reset detected IN T4 interrupt EX Report Bus reset detected IN T4 interrupt assert XINT ZU store 0 Bus reset leted 65 Y Read Bus reset completed INT3 d Report Bus reset completed INT3 interrupt interrupt Set FIFO according to FIFO mode Clear Asynchronous receive buffer Note 1 recv busy bit 0 Store received Self ID packet to Asynchronous receive buffer Bus reset completed No Yes Read Bus reset completed IN T3 2 Report Bus
62. et indicated in TSCHA 1 bit5 to 0 Indicates ID of TS type for source packet input first from port A at TSP IC I F T8 mH MSB bit5 LSB 7 0 74 Fujitsu VLSI LST Specification A BSO6OITA 7 37 Transmit CGMS TSCH Indicate Register B Transmit CGMS TSCH indicate register B indicates CGMS information and identification of TS type for source packet input from port B at TSP IC I F CGMSB 2 TSCHB 2 TSCHB 1 Initial Value 00 b 00 h 00 h CCMB Indicates CGMS information for source packet indicated in TSCHB 2 bit13 to 8 Indicates if ID of TS type for source packet inpu from port B at TSP IC I F is TSCHB 2 Read different from that in low bit TSCHB 1 MSB bit13 LSB bit8 Indicates CGMS information for source packet indicated in TSCHB 1 bit5 to 0 Indicates ID of TS type for source packet input first from port B at TSP IC I F 7 0 75 Fujitsu VLSI LST Specification MBS66IZA 7 38 Transmit CGMS TSCH Indicate Status Register Transmit CGMS TSCH indicate status register indicates validity of source packet input from TSP IC I F Bit Bit Bit Bit Bit Bit Bit i Bit Bit 9 8 7 6 5 4 3 1 0 ud T po T iv d Ee SEN 2 BE 1 Always indicate 0 15 11 reserved Indicates that the packet indicated in CGMSB 1 and TSCHB 1 82h bit7 to 0 was EAE input from port B at TSP IC I F Indicates that the packet indicated in CGMSB 2 and 2 82h bit15 to 8 was
63. ets MPEG2 TS DSS and DVC and re builds the receiving data At data transmission this section adds Isochronous packet header and CIP header and connects separates source packet When transmitting 2ch it connects Isochronous packet At data receipt it dd ees Isochronous packet header and CIP header restores by unit of source packet When receiving 2ch it separates Isochronous packet and divide them to each FIFO gt Integrated transmit receive dual purpose FIFO for transferring Isochronous by 2K byte X 2 channels 7 0 7 Fujitsu VLSI LST Specification MBS66IZA Chapter 4 Pin Assignment This chapter explains the pin assignment and table of pin function of MB86617A 4 Pin Assignment 4 2 Corresponding Table of MB86617A Pin 43 Outline Drawing of Package Rev 1 O 8 Fujitsu VLSI LST Specification 4 1 Pin Assignment The following diagram shows the MB86617A pin assignment XRESET MODE1 MODEO XCS XWR XDS XRD F XW AL XINT DREQ XDACK VDD VSS D15 D14 D13 D12 D11 M B86617 AD FPT 176P M03 Rev O 9 MBS66IZA VdS LT3S SELIOA IERRA TSDAO TSDA1 TSDA2 TSDA3 VSS VDD TSDA4 TSDA5 TSDA6 TSDA7 TSVALA TSCGMSA TSSYNCA TSCLKA VSS VDD VSS VDD VSS VDD SSA Fujitsu VLSI LST Specification MBS66IZA 4 2 Corresponding Table of MB86617A Pin The following table shows the corresponding items of MB86617A pin
64. finally input from port B at TSP IC I F EB Clears to 0 by writing 1 Clears to 0 by writing 1 Indicates that the value indicated in CGMSB 1 and TSCHB 1 82h bit7 to 0 is invalid Indicates that the value indicated in CGMSB 1 and TSCHB 1 82h bit7 to 0 is Clears to 0 by writing 1 Always indicate 0 reserved Always write in Indicates that the value indicated in CGMSB 2 and TSCHB 2 82h bit15 to 8 is invalid Read Indicates that the value indicated in CGMSB 2 and TSCHB 2 82h bit15 to 8 is valid 7 0 76 Fujitsu VLSI LST Specificatior MBS66IZA 0 Indicates that the packet indicated in CGMSA 1 and TSCHA 1 80h bit7 to 0 was finally input from port A at TSP IC I F 2 act TSCHA 1 Indicates that the packet indicated in CGMSA 2 and TSCHA 2 80h bit15 to 8 was finally input from port A at TSP IC I F wie Clears to 0 by writing 1 Indicates that the value indicated in CGMSA 2 and TSCHA 2 80h bit15 to 8 is invalid Read 1 vld TSCHA 2 1 Indicates that the value indicated in CGMSA 2 and TSCHA 2 80h bit15 to 8 is valid Write Clears to 0 by writing 1 0 Indicates that the value indicated in CGMSA 1 and TSCHA 1 80h bit7 to 0 is invalid Read 0 vid TSCHA 1 Indicates that the value indicated in CGMSA 1 TSCHA 1 80h bit7 to 0 is valid ESSEN Clears to 0 by writing 1 7 0 7 Fujitsu VLSI LST Spec
65. forms as cycle master if it is root Sets the value of this bit at 0 by writing in 1 Always indicate 0 4 0 reserved wie f Always write in 0 Rev 1 O 9 Fujitsu VLSI LST Specification MBS66IZA 8 17 Link register 02 read write Link Register 02 is the register that sets transfer mode of acknowledge packet transmitted by this node and disable setting of Link layer RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit oon 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 m Description of Each Bit rea Always indicate 0 15 4 reserved Always write 0 At receipt of normal packet Automatically transmits Acknowledge packet pending to all request packet Automatically transmits Acknowledge packet of complete to all response packet Automatically transmits packet Code value of Acknowledge packet automatically transmitted when Read error is detected depends on the kind of error ack mode Write At receipt of normal packet Automatically transmits Acknowledge packet of pending to Read request and Lock request Automatically transmits Acknowledge packet of ack_complete to Write request packet and all response packet Code value of Acknowledge packet automatically transmitted when error is detected depends on the kind of error Rev 1 O 95 Fujitsu VLSI Always write in 0 Read Link En
66. hen Connected Bias Disabled Fault bit changed 4 Int_enable n Indicates at event bit when Connected Bias Disabled Fault bit changed Clears the bit value to 0 by writing in 1 Always indicates 0 reserved Rev 1 O 92 Fujitsu VLSI LST Specification MBS66IZA 8 11 Physical register 10 read Physical Register 10 is the register that indicates Compliance level of this node Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 13 12 9 8 7 6 5 4 3 2 1 0 Compliance level 01 h Description of Each Bit Compliance 1 Indicate that this node supports P1394a standard Read MSB 7 LSB 0 Always indicate fixe value 01 h Rev 1 O 93 Fujitsu VLSI LST Specificatior MBS66IZA 8 12 Physical register 11 12 13 read Physical Register 11 12 13 are the registers that indicate Vendor_ID of this node Vendor_ID hi Fixed Value 00 h L wep peee e e e Description of Each Bit _ Indicate Vendor ID of Fujitsu MSB 7 LSB 0 Rev 1 O 94 Fujitsu VLSI LST Specification MBS66IZA 8 13 Physical register 14 15 16 read Physical Register 14 15 16 are the registers that indicate Product_ID of this node Product_ID hi Fixed Value 08 h e e C m Description of Each mem S In
67. ic buffer is empty Rev 1 O 23 Fujitsu VLSI LST Specification MBS66IZA Indicates that the device is not in forced sleep Read 1 Indicates that the device is in forced sleep by accepting Start sleep 01h instruction Indicates that no data is stored in ASYNC receive specific buffer Read data req Indicates that data is stored in ASYNC receive specific buffer 0 Indicates that packet receive is not in busy mode recv busy Read Note2 1 Indicates that packet receive is in busy mode due to receipt of Asynchronous packet and ID packet ES Indicates that node is not the cycle master now cmstr Read B 1 Node is cycle master now Interrupt indicate register does not have interrupt INT Read Interrupt indicate register has interrupt Note 1 IEEE1394 block is in internal reset status until integrated PLL is locked after turning the power ON PHY layer and Link layer do not operate during this period Note 2 In case that Asynchronous packet addressed to this node is received with this Bit indicate 1 it transmits ack busy X Rev 1 O 3C Fujitsu VLSI LST Specification MBS66IZA 73 instruction fetch Register instruction fetch register is the register that writes in instructions for this LSI and consists of the instruction code and operand Refer to Chapter 9 Instruction for each instruction code and operand code Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
68. icates that FMT range of CIP header of received Isochronous packet is other 1 than the value allowed to be received at DV EN DSS EN or TS EN 1Ch bit10 to 8 000007 2 10000 or DSS 100001 Clears to 0 by reading of this register Rev 1 O 67 Fujitsu VLSI LST Specification MBS66IZA 7 30 Isochronous Channel Monitor Register Isochronous channel monitor register is the register that indicates Isochronous packet channel flowing through 1394 bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NE E 200 NK NN Initial Value 0000 h Indicate that 1 at Bit corresponding to channel number of Isochronous packet flowing through 1394 bus 52h bit15 0 channelO 115 1350 e Read 54h bit15 0 6 channel31 56h bit15 0 channel32 channel47 58h bit15 0 channel48 channel63 Rev 1 O 6 Fujitsu VLSI LST Specification MBS66IZA 7 31 Cycle timer monitor Indicate Register Cycle timer monitor indicate register indicates value of integrated cycle timer register Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit HES cycle timer monitor hi aR cycle timer monitor 10 Initial Value 0000 h cycle timer m Read Indicate value of built in cycle timer register onitor MSB bit15 LSB bit0 Note This register latches the lower word 5 h by reading out lower word 5Ch and releases
69. idge Bch o e select B Selects Tx o e B bit14 setting value as odd even range of Isochronous packet header to be transmitted by bridge Bch Write in odd even range of transmit Isochronous packet header Valid with o e select B bit15 setting value 1 and reads in this setting value to transmit Isochronous packet header Tx o e B Executes 25 combined transmission as FIFO NFULL operation when setting of 2SP separated transmission or combined transmission for less than 2SP With more than 3 SP executes according to setting Executes 5 SP combined transmission at FIFO FULL Write in number of link of source packet processed by bridge Bch Selects odd even value to be input from CP IC as odd even range of Isochronous packet header to be transmitted by bridge Bch Selects Tx o e B b bit6 setting value as odd even range of Isochronous packet header to be transmitted by bridge Bch Read Read Tx o e A Write in odd even range of transmit Isochronous packet header Valid with o e select B bit7 setting value 1 and reads in this setting value to transmit Isochronous packet header Ju Read DBQB Write Write in number of split of source packet processed by bridge Bch Rev 1 O 53 Fujitsu VLSI LST Specificatior MBS66IZA Executes 2SP combined transmission as FIFO NFULL operation when setting of 2SP separated transmission or combined transmission for less than 2SP With more
70. ification MBS66IZA 7 39 Transmit EMI OE Setting Register Transmit EMI OE setting register sets EMI information and Odd Even value added to empty packet until valid data is transmitted AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPH IPH IPH IPH 86h RW select IPH EMEB OE select IPH B A A Mus Sets the default value EMI 00 OE 0 as EMI information and Odd Even 0 value added to IPH of empty packet until valid data is transmitted after starting transmission Read IPH select B Write Selects the setting value of IPH EMI B bit14 to 13 and IPH OE B bit 12 as EMI information and Odd Even value added to IPH of empty packet until valid data is transmitted after starting transmission Set EMI information which are set in IPH of empty packet transmitted from bridge Bch Read Valid only when select B bit15 is set to 1 Write MSB 6114 LSB bit13 EMI information after transmitting valid data depends on the setting of EMI select B 12h bit4 12 8 Set Odd Even value which is set in IPH of empty packet transmitted from bridge Bch Valid only when select B bit15 is set to 1 EMI information after transmitting valid data depends on the setting of o e select B 3Eh bit15 Read Sets the default value EMI 00 OE 0 as EMI information and Odd Even v
71. information to be output to CP IC 3 2 set EMI A od Valid only when EMI select A bit4 is 17 MSB bit3 LSB bit2 Does not insert internal 27 MHz counter value to System clock count ran ge of DSS packet header 1 27Mcoun A Read Write Inserts internal 27 MHz counter value to System clock count range of DSS packet header Does not mask port A input of TSP IC interface Read in input data from port A at transmit 0 ort mask A Read P Write Masks port A input of TSP IC interface Does not read in input data from port A at transmit Rev 1 O 3 Fujitsu VLSI LST Specification MBS66IZA 7 8 TSP Transmit Information Setting Register B TSP transmit information setting register B is the register that makes settings for transmit packet processed by bridge Bch AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i EMI ZM m set TSID B im select set EMI B count lt 9 B pos m clears when transmit process is started with bridge Bch after setting at 1 ie Starts transmit process with bridge Bch Automatically clears when transmit process is stopped by bridge Bch after setting at 1 Stops transmit process bridge Bch Outputs L to SELTSPB output terminal 15 Tx start B Tx end B Tx select B Outputs H to SELTSPB output terminal Set TSCH classification ID to be stored at FIFO of bridge Bch MSB bit12
72. input of first byte of source packet from TSP IC Bit Bit Bit Bit Bit Bit ps D e E pt y m E 15 14 13 12 11 10 reserved transmit offset A high transmit offset A low 0000 h CAKA Always indicate 0 15 4 high reserved 3 0 high Set value to be added to cycle count range of cycle time monitor 15 12 low Setting range is Oh to FFh lt 1251 transmit offset Read A Write Set value to be added to cycle offset range of cycle time monitor Setting range is Oh to COOh unit 1 24 576 MHz Rev 1 O 39 Fujitsu VLSI LST Specification MBS66IZA 7 10 Transmit Offset Setting Register B Transmit offset setting register B is the register that sets offset value added to cycle time monitor value Its aim is to generate source packet header Time stamp added to transmit packet processed by bridge Bch Max 32 ms Time stamp value is generated on the basis of cycle time monitor value at input of first byte of source packet from TSP IC Bit Bit Bit Bit Bit Bit p P E E b 15 14 13 12 11 10 reserved transmit offset B high transmit offset B low 0000 h Always indicate 07 15 4 high reserved 3 0 high Set value to be added to cycle count range of cycle time monitor 15 12 low Setting range is Oh to FFh lt 1251 transmit offset Read B Write Set value to be added to cycle offset range of cycle time monitor Setting range is Oh to C
73. it Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 44h Rx EMI A Rx SID A P Indicate EMI range of receive Isochronous packet header 6 mesa ma Indicates odd even range of receive Isochronous packet header Indicate SI range of CIP header of receive Isochronous packet 7 0 57 Fujitsu VLSI LST Specification MBS66IZA 7 24 Receive Isochronous Packet Header Indicate Register 2 A Receive Isochronous packet header indicate register 2 A is the register that indicates Isochronous packet CIP header information received by bridge Ach Beit 11 6 I SEEN see a E gee T Isochronous packet CIP header Indicates 50 60 range of receive Isochronous packet CIP header when receiving EMEN eee TSF range of receive Isochronous packet CIP header when receiving MPEG2 TS or DSS M Indicate STYPE range of CIP header of receive Isochronous packet MSB bit4 LSB Rev 1 O 58 Fujitsu VLSI LST Specification MBS66IZA 7 25 Receive Isochronous Packet Header Indicate Register 3 B Receive Isochronous packet header indicate register 3 B is the register that indicates Isochronous packet header information received by bridge Bch AD RW Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 48h Rx EMI B R Rx SID B eR C gt Indicate EMI range of receive Isochronous packe
74. ite other bit 2 Write 0 after 500 ns minimum passed after writing 417 Not stop clock for providing to TSP I F CP I F and data bridge Stop clock for providing to TSP I F CP I F and data bridge when PMODE input terminal is in Deletes Sel ID packet in spite of receiving it during bus reset In case of receiving Sel ID packet during bus reset process this bit stores 512 byte at maximum accompanying with both Asynchronous receive FIFO and Asynchronous transmit FIFO TSSYNCA and TSSYNCB signals are neccesary to detect the first byte of the input data to TSP interface TSSYNCA and TSSYNCB signals are not neccesary to detect the first byte of the input data to TSP interface TSSYNCA and TSSYNCB signals are not asserted when the data is outputted from TSP interface TSSYNCA and TSSYNCB signals are asserted when the data is outputted from TSP interface 5 i Read ync ou Write reserved Iso FIFO Read no clr Write Rev 1 O 2 Fujitsu VLSI Always indicate 0 Always write in 0 Clears receive Isochronous FIFO when bus reset occurred Does not clear Isochronous FIFO when bus reset occurred Read 7 S LE LST Specification M BS6OITA Uses 2K byte FIFO on LINK I F side of bridge for Isochronous transmit receive Asyn FIFO 3 sel E Note 1 Refer to Self ID Packet Receive Operation for the internal operation flow and read out flow of with this bit set at 1
75. ket Ach 42h Set criteria for Late packet Bch Ach received RXSTA RXCHA Iso channd No Bch received RXSTB lh RXCHB Iso channel Rev 1 O 129 Fujitsu VLSI LST Specification Chapter 12 System Configuration This chapter explains the system configuration of this chip 121 Recommended Connection for 1934 Port for one port 12 2 Recommended Connection for Cable Power Supply 12 3 Recommended Connection for Build in PLL Loop Filter 12 4 Configuration of Feedback Circuit at Crystal Oscillator Rev O 130 MBS66IZA Fujitsu VLSI LST Specification A BSO6OITA 12 1 Recommended C onnection for 1934 Port for one port Theexample of recommended connection of 1934 port terminal for one port is shown below 999999 gt 999 9 000 969 999 999 999 999 5 1k 1 Figure 121 Recommended connection for 1934 port for one port For unused 1394 port TPBIAS should be open and TPA XTPA TPB and XTPB should be be connected to GND Rev 1 O 131 Fujitsu VLSI LST Specification MBS66IZA 122 Recommended Connection for Cable Power Supply The exampleof recommended connection of cable power supply for 1394 cable is shown below Power max 33V 510 5 CPS lt 2 2uF 91 5 Figure 122 Recommended connection for cable power supply Rev 1 O 12 Fujitsu VLSI LST Specification 12 3 Recommended Connection for Build in PLL Loop Filter The example of re
76. latch by reading out upper word To read out this register make sure to read out in the order of 5Ch 54A h two as a set Rev 1 O 68 Fujitsu VLSI LST Specification MBS66IZA 7 32 Ping Time Monitor Register Ping time monitor register is the register that indicates time period of transmitting request packet to receiving response packet to the request R W Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Initial Value 0000 h NOT Indicate time period from transmitting request packet to receiving response packet Ping time monitor Read to the request Counts by 20ns unit MSB bit15 LSB 7 0 7 Fujitsu VLSI LST Specification MBS66IZA 7 33 PHY LINK Register Address Setting Register PHY LINK register address setting register is the register that sets address in order to access PHY LINK register indirectly PHY LINK register indicated with address set by this register can be accessed from PHY LINK register access port Bit Bit Bit Bit Bit Bit T Es 2s a p P m 15 14 13 12 11 10 Always indicate 0 reserved Read Set address of PHY LINK register to be accessed dpi Ee ee I 1 0 71 Fujitsu VLSI LST Specification MBS66IZA 7 34 PHYLINK Register Access Port PHY LINK register access port is the port to access PHY LINK register indirectly PHY LINK register indicated with addre
77. n of this device and displays the examples of control flow 111 Initialization 112 D Packet Receiving 113 Asynchronous Packet Transmitting 11 4 Asynchronous Packet Receiving 115 Isochronous Packet Transmitting 116 Isochronous Packet Receiving Rev 1 O 12 Fujitsu VLSI LST Specification M BSO6OITA 11 1 Initialization The example of control flow from the system power on to the packet transmitting receiving possible state is shown below In this examle the device is not operated with cable power supply before turning on the power of system lt Host gt lt Device gt START System power ON Inner reset and release reset Start internal PLL Receive BUS RESET i No Yes Start bus reset process Report Bus reset ddecte IN T interrupt Complete bus rese process Report Bus reset complete IN interrupt eat XINT Power CPSterminal L up 50015 Power XRESET terminal to L up to 400ns Read Bus rese detected IN T4 interrupt Read Bus reset complete IN T3 interrupt Packet transmitting receiving possible Figure 11 1 Example of flow for Initialization Rev 1 O 113 Fujitsu VLSI LST Specification MBS66IZA 11 2 Self ID Packet Receiving The example of control flow for receiving Saf ID packet is shown beow 1121 Self ID Packet Receive during Bus Reset Process 122 5 Packet Receive aft
78. nd DV1B bit12 to 1 simultaneously Note 2 Do not set TV2A bit7 bit6 bit4 to 1 simultaneously Note 3 Do not set TV2B bit15 and TV2A bit7 to 1 simultaneously Note 4 Do not set TV1B bit14 and bit6 to 1 simultaneously Note 5 Do not 1 to 2 bit15 TV1B bit14 TV2A bit7 and TV1A bit6 when TSCMP bitO is set to 1 Note 6 FMT error is reported when receiving data format other than DV EN bit10 DSS EN bit9 and TSEN bit8 regardless of their settings Rev 1 O 42 Fujitsu VLSI LST Specification MBS66IZA Register setting value and selection of output port are shown in the table below Receive TSP IC I F TSP IC I F Status CMP TS Port A Port B TV2B TV1B TV2A 1 Processing Ach Receive data Receive data Ich receive Processing Bch Receive data Processing Bch Receive data 0 Processing Ach Processing Bch Receive data Receive data 0 Processing Bch Processing Ach Receive data Receive data Ich receive Processing 1 h Receive data E Ach Bc M data Rev 1 O 43 Fujitsu VLSI LST Specification MBSO6OITA 7 12 Receive DSS Packet Header Indicate Register A Transmit DSS Packet Header Setting Register A Receive DSS packet header indicate register A indicates DSS packet header range of DSS packet received by bridge Ach Transmit DSS packet header setting register A sets DSS packet h
79. nous transmit FIFO and Bridge FIFO are combined to be set in Asynchronous transmit buffer Set Asynchronous receive FIFO to Asynchronous receive buffer When Asyn FIFO sel is 0 Asynchronous receive FIFO 256 byte and Asynchronous transmit FIFO 256 byte are cleared and reset Asynchronous receive FIFO to Asynchronous receive buffer Asynchronous transmit FIFO to Asynchronous transmit buffer Rev 1 O 1 Fujitsu VLSI LST Specification MBS66IZA 1122 Self ID Packet Receive after Transmitting Ping Packet Ping Regardless of 540 store bit setting in the mode control register refer to 7 1 the device receives self ID packet after a ping packet transmitted and stores the data removing logical inverse section the Asynchronous receive FIFO m Flow chart from transmitting of Pig packet to receiving Self ID packet Ping ost gt Device H Store ping packet to betransmitted in Asynchronous receive buffer Issue Send PHY packet 21h Issue instruction Store pin packet two word to be transmitted in Asynchronous transmit buffer Read Asynchronous transmit buffer Arbitration procedure Arbitration result Won Lost Transmit Ping packet Report Physical packet send interrupt INTS XINT Store received Self ID packet in Asynchronous receive buffer Read Physical packet send interrupt EE INT25 Report Self ID packet received interrupt IN T29 XINT
80. on LINK I F side of bridge Bch reset BRG Read FIFO B Write 1 Resets FIFO on LINK I F side of bridge Bch Always indicate 0 reserved Releases FIFO reset on TSP IC side of bridge Ach reset TSP Read FIFO A Write Resets FIFO on TSP IC I F of bridge Ach Releases FIFO reset on LINK I F side of bridge Ach reset BRG Read FIFO A Write Resets on LINK I F side of bridge Ach Always indicate 0 Reserved Always write in 0 Note 1 This register is not cleared automatically 0 Releases forced reset of bridge Ach 7 reset A Read Write Execute forced reset of bridge Ach After writing 1 check the state and then write 0 Note 2 Do not set 1 to this register during transmit receive execution Rev 1 O 61 Fujitsu VLSI LST Specification MBS66IZA 7 28 Data Bridge Transmit Receive Status Register A Data bridge transmit receive status register indicates status of packet to be transmitted received by bridge Ach Bit Bit Bit Bit Bit i Bit Bit Bit Bit Bit Bit i Bit Bit Bit d Rxoe Fx Rx R6 s chg A a atea ema 8 6 a EVE de A d err As em A etA Indicates that bridge Ach is not in the process of transmit Indicates 0 when Tx end A 10h bit14 is set at 1 and transmit process is stopped 15 Tx busy A Indicates that bridge Ach is in the process of transmit Indicates 1 when Tx start A 10h bit15 is
81. p stops the driver receiver function of 1394 port and then changed into the status with this device s cable cut Also it stops the clock to be input from integrated PLL to IEEE1394 block Access to each register is available No interrupt this instruction is reported Confirm the sleep condition using sleep Bit Bit4 of flag amp status register address 02h m Removesleep 02h This instruction releases this device from forced sleep condition No interrupt to this instruction is reported Confirm the sleep condition release using sleep Bit Bit4 of flag amp status register address 02h m Asynchronous Receive 03 h This instruction reads the out data stored at ASYNC receive specific buffer Even though the receive data length does not satisfy with the quadlet unit this instruction stores up to quadlet unit The receive data does not have CRC code and Logical inverse part m Removebusy mode 04 h This instruction releases the busy mode set due to receiving normal Asynchronous packet or Self ID packet addressed to this node m Send PHY packet 21 h This instruction transmits the data stored at ASYNC receive specific buffer Do not issue this instruction in case that this instruction is not Bus manager node or not Isochronous resource manager no de without existence of Bus manager When packet transmit operation is completed normally this instruction report s the interrupt of Physical packet send INT25 Store
82. r Clears to 0 by lead of this register Indicates that FMT range of CIP header of received Isochronous packet is the value 0 allowed to be received at DV EN DSS EN or TSEN ICh bitlO to 8 DV 00000 MPEG2 10000 055 100001 Rx FMT err A Read Indicates that FMT range of CIP header of received Isochronous packet is other than the value allowed to be received at DV EN DSS EN or TS EN 1 bit10 to 8 000007 MPEG2 10000 or DSS 100001 Clears to 0 by reading of this register Rev 1 O 64 Fujitsu VLSI LST Specification MBS66IZA 7 29 Data Bridge Transmit Receive Status Register B Data bridge transmit receive status register B indicates status of packet transmitted received by bridge Bch mw Bt Bit Bit Bit Bi Bi Bi Bi Bi Bi Bi Bi it Bi Bi Bit a Rx a Rx een DBC de B pis B er B B ut Indicates that bridge Bch is not in the process of transmit Indicates 0 when Tx end B 12h bit14 is set at 1 and transmit process is stopped 15 Tx Indicates that bridge Bch is in the process of transmit Indicates 1 when Tx start B 12h bit15 is set at and transmit process is started Indicates that bridge Bch is not in the process of receive Indicates 0 when Rx end 3Ch bitl4 is set at 1 and receive process is stopped Indicates that bridge Bch is in the process of receive Indicates 1 wh
83. r address 02h at 1 simaltaneously with this interrupt report INT24 Cycle start packet send Completed to send Cycle start packet when self node is root INT25 Physical packet send Completed to send Physical packet INT26 Extended PHY packet received Received Extended PHY packet normally Received Physical configuration packet normally gt Reflect to Physical register 01 address Phy Link reg 02h and switch to specified performance automatically Cycle start packet received Physical configuration packet received INT28 Lisbon packet received Received Link on packet addressed to self node normally gt Assert LINKON terminal output simultaneously Received Self ID packet normally Store data at ASYNC receive specific buffer Receive late was occured INT30 Receive late occurred 4 Delete packet received Though Instruction was issued it was not accepted because the content was not appropriate for this device e g gt Issued Remove sleep 02h instruction in spite of not in sleep condition Instruction abort State gt Issued Instruction suspend 62h instruction without instruction to be stopped gt Used undefine operand against issued instruction gt Issued instruction was undefined etc Transmit late was occured Transmit late occured gt Delete packet transmitted 7 0 11 Fujitsu VLSI LST Specification MBS66IZA Chapter 11 Operation This chapter explains the operatio
84. r Name reserved data bridge transmit receive status B N reserved Isochronous channel monitor 1 Isochronous channel monitor 2 reserved Isochronous channel monitor 3 oo reserved Isochronous channel monitor 4 gt reserved cycle time monitor upper a reserved cycle time monitor lower t reserved Ping time monitor PHY LINK register address setting PHY LINK register address setting N PHY LINK register access port PHY LINK register access port Revision indicate register upper reserved Revision indicate register lower reserved reserved gt reserved reserved m reserved reserved reserved reserved N reserved reserved reserved reserved reserved oo reserved reserved a gt reserved reserved a reserved reserved m reserved reserved B 7 0 21 Fujitsu VLSI LST Specification MBS66IZA READ Register Name Register Name reserved transmit CGMS TSCH indicate A reserved transmit CGMS TSCH indicate B oo oo N R transmit CGMS TSCH indicate status transmit CGMS TSCH indicate status oo transmit EMI OE setting transmit EMI OE setting oo oo reserved
85. rmation setting 4 B data bridge transmit information setting 4 B 95 data bridge receive information setting data bridge receive information setting t transmit packet concatenate split setting transmit packet concatenate split setting Late packet criterion range setting A Late packet criterion range setting A Late packet criterion range setting B Late packet criterion range setting B T reserved receive Isochronous packet header indicate 1 A oae packet hender DSS packet header seting e estDs packet header oting 8 header setine BJ dower gy e os i duta bridae vanst infomation sing 318 sme vanomit infomation sening 41B wansmit vansmit packet coneatenatcfsplit sening tammityaletconeenatpitseting _ taepacketerteionransesenins ta Cate packet orteion range setine 0 receive I ochronous packet header indicate 2 A reserved receive Isochronous packet header indicate 3 B gt receive Isochronous packet header indicate 4 B FIFO reset FIFO reset m reserved data bridge transmit receive status Rev 1 O 2C Fujitsu VLSI LST Specification MBS66IZA READ Register Name Registe
86. rs to the specified data length 1 in the format Clears to 0 by lead of this register 0 Indicates that transmit packet is transmitted normally Tx late A B Indicates that transmit packet became Late packet Delete packet and not transmit Clears to 0 by lead of this register Indicates that the received packet is normal Indicates that received packet was Late packet Delete packet and not output to TSP IC Clears to 0 by lead of this register Indicates that 50 60 range of header for received Isochronous packet is 0 Indicates that 50 60 range of CIP header of received Isochronous packet is Clears to 0 by lead of this register Indicates that DBC range of CIP header of received Isochronous packet is normal Indicates that DBC range of CIP header of received Isochronous packet received is not consecutive Clears to 0 by lead of this register Rev 1 O 63 Fujitsu VLSI 1 H 0 Indicates that STYPE range of CIP header of received Isochronous packet is 00000 or 000077 5 Rx stype Read Indicates that STYPE range of CIP header of received Isochronous packet is other 1 than 00000 00007 Clears to 0 by lead of this register 1 3 2 1 LST Specificatior MBS66IZA Indicates that CIP header of received Isochronous packet is normal Rx CIP err A Read 1 Indicates that CIP header of received Isochronous packet has an erro
87. set at and transmit process is started Indicates that bridge Ach is not in the process of receive Indicates 0 when Rx end A 3Ch bit6 is set at 1 and receive process is stopped Indicates that bridge Ach is in the process of receive Indicates 1 when Rx start A 3Ch bit7 is set at 1 and receive process is started Indicates that Isochronous packet received after starting receive process is not the first packet received Indicates that EMI information of received Isochronous packet header is not changed Indicates that EMI informatio n of received Isochronous packet header has changed from just former EMI information of packet received by Isochronous cycle Clears to 0 by lead of this register Indicates that odd even information of received Isochronous packet header is not changed Indicates that odd even information of received Isochronous packet header has changed from just former odd even information of packet received Isochronous cycle Clears to 0 by lead of this register Rx ISTP A Read Indicates that the first Isochronous packet is received after receive process is 1 started Clears to 0 by lead of this register 0 1 Rx EMI Rev 1 O 62 Fujitsu VLSI LST Specificatior MBS66IZA Indicates that the data length of received packet is same as specified data length in format 10 Rx dlen err A Read Indicates that the data length of received packet diffe
88. ss set by PHY LINK register address setting register can be accessed from this port Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit LIEN NNI phy link data Initial Value 0000 h Read Indicates PHY LINK register contents defined by address set by PHY LINK register address setting register MSB 15 LSB 0 15 0 phy link data Writ Executes write in the process of register defined by this address set by PHY LINK register address setting register MSB 15 LSB 0 Rev 1 O 72 Fujitsu VLSI LST Specification MBS66IZA 7 35 Revision Indicate Register Revision indicate register is the regster that indicates chip revision of this LSI Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Revision code hi Revision code 10 Initial Value Fixed m Indicate Revision code Rev 1 O 73 Fujitsu VLSI LST Specification MBS66IZA 7 36 Transmit CGMS TSCH Indicate Register A Transmit CGMS TSCH indicate register A indicates CGMS information and identification of TS type for source packet input from port A at TSP IC CGMSA 2 TSCHA 2 TSCHA 1 Initial Value 00 b 00 h 00 h CGMSA Indicates CGMS information for source packet indicated in TSCHA 2 bit13 to 8 Indicates if ID of TS type for source packet input from port A at TSP IC is TSCHA 2 Read different from that in low bit TSCHA 1 MSB bit13 LSB bit8 Indicates CGMS information for source pack
89. t header 6 omes Raa fo Indicates odd even range of receive Isochronous packet header Indicate SI range of CIP header of receive Isochronous packet Rev 1 O 59 Fujitsu VLSI LST Specification MBS66IZA 7 26 Receive Isochronous Packet Header Indicate Register 4 B Receive Isochronous packet header indicate register 4 B is the register that indicates Isochronous packet CIP header information received by bridge Bch d D di 16 11 6 8 as E EU T Isochronous packet CIP header Indicates 50 60 range of receive Isochronous packet CIP header when receiving ENSE ice TSF range of receive Isochronous packet CIP header when receiving MPEG2 TS or DSS Indicate STYPE range of header of receive Isochronous packet MSB bit4 LSB 7 0 ec Fujitsu VLSI LST Specification MBS66IZA 7 27 FIFO Reset Setting Register FIFO reset setting register sets force reset of bridge and each FIFO gw Bit Bt Bi Bi Bi Bi Bi Bi Bt Bt Bi Bi Bit Bt 15 i META EUM 9 8 7 6 5 4 3 2 1 0 resetT reset reset reset SP BRG wet TSP 4h RW Lo Hro HFO HFO B B A Read Releases forced reset of bridge Bch Write Executes forced reset of bridge Bch 0 Releases FIFO reset TSP IC I F side of bridge Bch reset TSP Read FIFO B Write 1 Resets FIFO on TSP IC I F side of bridge Bch 0 Releases FIFO reset
90. ujitsu VLSI LST Specification MBS66IZA 3 2 Function of Each Block This section explains the function of each block for 86617 m PHY Layer Contrd Circuit This circuit is for the Physical layer of IEEE 1394 with the following functions gt Asynchronous transfer is supported under cable environment gt Maximum transfer data rate 393 216Mbit sec gt with three ports for transceiver receiver transfer IEEE1394 packet gt with bus monitor initial performance for occurring bus reset speed signaling arbitration encode decode transfer receive data m LINK Layer Control Circuit This circuit generates standard packet for IEEE1394 controls transfer and performs the following functions Generates and checks 32 bit CRC for header and data of packet gt Activates cycle master function with integrated 32 bit cycle timer register m TSP IC Interface This TSP IC Interface has two exclusive ports with the following functions for transmitting receiving TSP IC MPEG2 TS and DSS data and receiving DV data gt Adds time stamp to both MPEG2 TS and DSS data gt Outputs received data just when the value of time stamp SPH and cycle timer is matched with each other gt Integrated transmit receive dual purpose FIFO for transferring Isochronous by 2K byte X 2 channels m CP IC Interface This interface adds the copy information to CP IC so as to correspond to copy protect m Data Bridge This Data Bridge pack
91. ved reserved reserved reserved reserved Rev 1 O 24 Fujitsu VLSI LST Specification Chapter 7 Internal Register Function Description This chapter explains the details of the internal register of MB86617A Rev 1 O mode control Register flag amp status Register instruction fetch Register interrupt factor Indicate Register interrupt mask Setting Register Receive Acknowledge Indicate Register A buffer Data Port Receive Transmit TSP Transmit Information Setting Register A TSP Transmit Information Setting Register B Transmit Offset Setting Register A Transmit Offset Setting Register B TSP Receive Information Setting Register Transmit DSS Packet Header Setting Register A 7 13 7 14 7 15 7 16 7 17 7 18 7 19 7 20 721 7 22 7 23 7 24 Transmit DSS Packet Header Setting Register B TSP Status Register Data Bridge Transmit Information Setting Register 1 A Data Bridge Transmit Information Setting Register 2 A Data Bridge Transmit Information Setting Register 3 B Data Bridge Transmit Information Setting Register 4 B Data Bridge Receive Information Setting Register Transmit Packet Link Split Setting Register Late Packet Decision Range Setting Register A Late Packet Decision Range Setting Register B Receive Isochronous Packet Header Indicate Register 1 A Receive Isochronous Packet Header Indicate Register 2 A 25 MBS66IZA Fujitsu VLSI LST
92. ving Link on packet under operating with supply power through IEEE1394 cable When PMODE becomes H DL is output With the PMODE in H the output of this pin is not changed If not using this pin set this pin as open one This pin is for test Use this pin as open one 17 Fujitsu VLSI LST Specification MBS66IZA 5 6 Power GND Pin This section explains the power GND pin 3 3V digital power pin Digital ground pin 3 3V analog power pin Analog ground pin Rev 1 O 18 Fujitsu VLSI LST Specification MBS66IZA Chapter 6 Internal Register This chapter explains the MB86617A internal register Note that the access of internal register is applied only 16 bits access WRITE READ Address HEX Register Name Register Name om gt EN Interrupt mask setting A Interrupt indicate A EM Interrupt mask setting B Interrupt indicate B EN A buffer data port transmit A buffer data port receive 0 2 4 6 8 12 14 16 18 A 1 1 transmit offset setting A lower transmit offset setting A lower transmit offset setting B upper transmit offset setting B upper transmit offset setting B lower transmit offset setting B lower TSP receive information setting TSP receive information setting transmit DSS packet header setting A receive DSS packet header setting A most significant most significant 0 0 0 0 0 smi 0

Download Pdf Manuals

image

Related Search

Related Contents

Wolf DCX-1500I Home Theater System User Manual  スマートベンチレータ Vivo 40  Informations Scanner    sistema di fissazione esterna orthofix  89.53 kb - CNREurope    iso-tech idm 103/105/105rms multimetre numerique manuel de l    海外在住者向け設定サポートガイド  

Copyright © All rights reserved.
Failed to retrieve file