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Cypress Semiconductor Perform CY8C24x94 Specifications

1. TOP VIEW SIDE VIEW BOTTOM VIEW 3 500 REF 5 000 0 100 ER 7 0900 0 0 500 pitch 39 25 140 200 REF 0 250 9 050 VE PN ft LD UUUWUUUUU 5 BAN P eU ee sieges E PIN 1 DOT 8 LASER MARK 5 EE C 3 500 0 100 8 D gg I p cece T LO R ee Cc D Cj EO 8 7 I 0 400 0 100 16 0 0 05 1 9 075 as 3 500 0 100 o5 ce ojo NOTES Sz 1 BEE HATCH AREA IS SOLDERABLE EXPOSED PAD gi 2 BASED ON REF JEDEC MO 220 3 DIMENSIONS ARE IN MILLIMETERS 001 30999 D 4 PACKAGE WEIGHT SEE CYPRESS PACKAGE MATERIAL DECLARATION DATASHEET PMDD POSTED ON THE CYPRESS WEB Important Note For information on the preferred dimensions for mounting QFN packages see the application note Application Notes for Surface Mount Assembly of Amkor s MicroLeadFrame MLF Packages available at http www amkor com Figure 26 56 Pin 300 Mil SSOP maa NOTE REFER TO PMDD SPEC 1 ME TUT 2 DIMENSIONS IN INCHES MIN 29 56 0 720 E 0 730 SEATING PLANE 0 005 0 088 l 0 092 2035 T 7 0 010 j HH LHHHHHHHHHHHHHHHHHH GAUGE PLANE nl en HE ajaa po eH i TL gaze F BSC 0 008 0 8 EN 0 0
2. Type Pin E Pin No Digital Analog Name Description 1 NC No connection Pin must be left floating 2 yo I PO 7 Analog column mux input 3 yo PO 5 Analog column mux input and column output 4 I O PO 3 Analog column mux input and column output 5 yo PO 1 Analog column mux input 6 1 0 P2 7 7 VO P2 5 8 yo P2 3 Direct switched capacitor block input 9 yo P2 1 Direct switched capacitor block input 10 NC No connection Pin must be left floating 11 NC No connection Pin must be left floating 12 NC No connection Pin must be left floating 13 NC No connection Pin must be left floating 14 OCD OCDE OCD even data I O 15 OCD OCDO OCD odd data output 16 Power SMP SMr connection to required external compo nents 17 NC No connection Pin must be left floating 18 NC No connection Pin must be left floating 19 NC No connection Pin must be left floating 20 NC No connection Pin must be left floating 21 NC No connection Pin must be left floating 22 NC No connection Pin must be left floating 23 VO P1 7 IC SCL 24 VO pr FGM 4 25 NC No connection Pin must be left floating 26 1 0 P1 3 27 70 P1 1 XTALin PC SCL ISSP SCLKMI 28 Power VDD Supply voltage 29 NC No connection Pin must be left floating 30 NC No connection Pin must be left floating 31 70 P1 0 XTALout PC SDA ISSP SDATA 32 1 0 P1 2 33 lo P1 4 Optional EXTCLK 34 1 0 P1 6 35 NC No connection Pin must be left fl
3. Z CY8C24223A SP CYPRESS CY8C24423A PERFORM Table 22 5 V DC Analog Reference Specifications continued Reference Reference Power n Pei Settings Symbol Reference Description Min Typ Max Units 0b010 RefPower high Vrerw Ref High Vpp Vpp 0 121 Vpp 0 003 Vn V Opamp bias high yc AGND Vpp 2 Vpp 2 0 040 Vpp 2 Vpp 2 0 034 V Vrero Reflow Vss Vss Vss 0 006 Vss 0 019 V RefPower high Vrerw Ref High Vpp Vpp 0 083 Vpp 0 002 Yoo V Opamp bias low youn AGND Vpp 2 Vpp 2 0 040 Vpp 2 0 001 Vpp 2 0 033 V Vrerio Reflow Vss Vss Vss 0 004 Vss 0 016 V RefPower medium VREFHI Ref High Vpp Vpp 0 075 Vpp 0 002 Vpp V Opamp bias high Viseno AGND Vpp 2 Vpp 2 0 040 Vpp 2 0 001 Vpp 2 0 032 V Vrero RefLow Vss Vas Vss 0 003 Vss 0 015 V RefPower medium Vgggu RefHigh Vpp Vpp 0 074 Vpp 0 002 VDD V Opamp bias low yop AGND Vpp 2 Vpp 2 0 040 Vpp 2 0 001 Vpp 2 0 032 V Vrerto Reflow Vss Ves Vss 0 002 Vss 0 014 V 0b011 RefPower high Vrerw RefHigh 3 x Bandgap 3 753 3 874 3 979 V Opamp bias high Vicenp AGND 2 x Bandgap 2 511 2 590 2 657 V VrerLo Reflow Bandgap 1 243 1 297 1 333 V RefPower high VREFHI Ref High 3 x Bandgap 3 767 3 881 3 974 V Opamp bias low Vienp AGND 2xBandgap 2 518 2 592 2 652 V VREFLO Ref Low Bandgap 1 241 1 295 1 330 V RefPower m
4. i Type i ds Figure 6 CY8C24423A 28 Pin PSoC Device No DITE PARIS Name Description i 1 I O PO 7 Analog column mux input A I PO 7 1 28 Bl Voo 2 yo I O IPOISJ Analog column mux input and column output A IO PO S 2 27 jm PO 6 A I 3 I O I O PO 3 Analog column mux input and column output a n 3 L oe 4 I O PO 1 Analog column mux input P2I7 5 24 I POLO A 5 I O P2 7 P2 5 6 PDIP X 23m P2 6 External VRef 6 lO P2 5 A I P2 3 7 ssop 22 P214 External AGND 7 10 I P2 3 Direct switched capacitor block input Eh o 0 e 8 I O P2 1 Direct switched capacitor block input I2CSCL P1 7 amp 10 19 XRES 9 Power SMP SMP connection to external components I2C SDA P1 5 ai deje P1 6 required P1 3 42 47 P1 4 EXTCLK 10 O P1 7 12C SCL 12C SCL XTALin P4 1 amp 43 46 P1 2 11 I O P1 5 IC SDA mn a Vss E 14 15 P1 0 XTALout I2GDA 12 yo P1 3 13 yo P1 1 XTALin RC SCL ISSP SCLKSI 14 Power Vss Ground connection 15 I O P1 0 XTALout PC SDA ISSP SDATASI 16 yo P1 2 17 yo P1 4 Optional EXTCLK 18 yo P1 6 19 Input XRES Active high external reset with internal pull down 20 WO P2 0 Direct switched capacitor block input Not for Production 21 I O P2 2 Direct switched capacitor block input 22 I O P2 4 External analog ground AGND 23 I O P2 6 External voltage reference Vper 24 I O PO 0 Analog column mux input 25 I
5. Symbol Description Min Typ Max Units troa Rising settling time from 80 of AV to 0 1 of AV 10 pF load unity gain Power low Opamp bias low 3 92 us Power medium Opamp bias high 0 72 us tsoa Falling settling time from 20 of AV to 0 1 of AV 10 pF load unity gain Power low Opamp bias low 5 41 us Power medium Opamp bias high 0 72 us SRroa Rising slew rate 20 to 80 10 pF load unity gain Power low Opamp bias low 0 31 V us Power medium Opamp bias high 2 7 V us SRroa Falling slew rate 20 to 80 10 pF load unity gain Power low Opamp bias low 0 24 V us Power medium Opamp bias high 1 8 V us BWoa Gain bandwidth product Power low Opamp bias low 0 67 MHz Power medium Opamp bias high 2 8 MHz Enoa Noise at 1 kHz Power medium Opamp bias high 100 nV rt Hz When bypassed by a capacitor on P2 4 the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 14 dB This is at frequencies above the corner frequency defined by the on chip 8 1 K resistance and the external capacitor Figure 14 Typical AGND Noise with P2 4 Bypass 1000 100 r r 0 001 0 01 0 1 Freq kHz 1 10 100 At low frequencies the opamp noise is proportional to 1 f power independent and determined by device geometry At high freque
6. Symbol Description Min Typ Max Units Notes Fimo12 IMO freguency for 12 MHz 11 5 12 12 7127 281 MHz Trimmed for 2 7 V operation using factory trim values See Figure 8 on page 18 SLIMO mode 1 Fimos IMO freguency for 6 MHz 5 5 6 6 5127 28 MHz Trimmed for 2 7 V operation using factory trim values See Figure 8 on page 18 SLIMO mode 1 Fopu1 CPU frequency 2 7 V nominal 0 937 3 3 1521 MHz SLIMO mode 0 FBLK27 Digital PSoC block frequency 0 12 12 7147 28 MHz Refer to the AC Digital Block 2 7 V nominal Specifications F32k1 ILO frequency 8 32 96 kHz Faok U ILO untrimmed frequency 5 100 kHz After a reset and before the M8C si starts to run the ILO is not trimmed See the System Resets section of the PSoC Technical Reference Manual for details on timing this txgsT External reset pulse width 10 Hs DC12M 12 MHz duty cycle 40 50 60 96 DCiLo ILO duty cycle 20 50 80 Fmax Maximum freguency of signal on row input 12 7 MHz or row output SRpower up Power supply slew rate 250 V ms Vpp slew rate during power up tPOWERUP Time from end of POR to CPU executing 16 100 ms Power up from 0 V See the System code Resets section of the PSoC Technical Reference Manual tit mom 12 MHz IMO cycle to cycle jitter RMS 400 1000 ps N 32 12 MHz IMO long term N cycle to cycle 600 1300 ps jitter RMS 12 MHz IMO period jitter RMS 100 500 ps tit pu 3 12 MHz IMO cycle to cycl
7. sses 18 Document Number 38 12028 Rev V CY8C24123A CY8C24223A CY8C24423A AC Electrical Characteristics sss 36 Packaging Information mn 50 Packaging Dimensions WoooooWoWooo 50 Thermal Impedances sese 56 Capacitance on Crystal Pins oo ooWoo 56 Solder Reflow Specifications 56 Development Tool Selection 57 SoftWare qe dette 57 Development Kits i oooooocoWoWoooWoWo Wo 57 Evaluation Tools oooooWooWoWo WoWoWoWW 57 Device Programmers i ooooWo oWooo 58 Accessories Emulation and Programming 58 Ordering Information eene 59 Ordering Code Definitions esses 59 ACTONYMS e 60 Acronyms Sed anna nata anal mnta 60 Reference Documents oom 60 Document Conventions oom 61 Units Of Measure e eerte tete 61 Numeric Conventions oooooWoWooWooooW 61 Glossary 61 Eee 66 Part Numbers Affected oooooooWoWoo 66 CY8C24123A Qualification Status 66 CY8C24123A Errata Summary sess 66 Document History Page eene 67
8. Full duplex universal asynchronous receiver transmitter UART Multiple serial peripheral interface SPI masters or slaves Can connect to all general purpose I O GPIO pins o Complex peripherals by combining blocks sequence PRS modules Global Digital Interconnect Global Analog Interconnect SRAM 256 Bytes SROM Flash 4KB m Precision programmable clocking a Internal 5 24 48 MHz main oscillator o High accuracy 24 MHz with optional 32 kHz crystal and phase locked loop PLL da Optional external oscillator up to 24 MHz a Internal oscillator for watchdog and sleep CPU Core M8C Sleep and Watchdog Interrupt gt ret Controller Multiple Clock Sources Includes IMO ILO PLL and ECO i IGITAL SYSTEM ANALOG SYSTEM m Flexible on chip memory S ra 9 4 KB flash program storage 50 000 erase write cycles Ref n 256 bytes SRAM data storage pata a In system serial programming ISSP Array a Partial flash updates n Flexible protection modes a Electronically erasable programmable read only memory EEPROM emulation in flash m Programmable pin configurations Internal Switch x Digital Multiply Decimator POR and LVD Voltage Mode o 25 mA sink 10 mA source on all GPIOs Clocks Accum
9. writes Ippp Supply current during programming or verify 5 25 mA ViLp Input low voltage during programming or verify 0 8 V ViHP Input high voltage during programming or verify 2 1 V li p Input current when applying Vi p to P1 0 or P1 1 0 2 mA Driving internal pull down during programming or verify resistor lp Input current when applying Vip to P1 0 or P1 1 1 5 mA Driving internal pull down during programming or verify resistor Votwv Output low voltage during programming or verify Vss 0 75 V VoHv Output high voltage during programming or verify Vpp 1 0 Vpp V Flashenpg Flash endurance per block 50 0001161 B Erase write cycles per block Flashent Flash endurance total 7 1 800 000 Erase write cycles Flashpr Flash data retention 10 Years DC PC Specifications Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Tp lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 28 DC I2C Specifications Symbol Description Min Typ Max Units Notes ViLi2C Input low level 0 3 x Vpp V 24V lt Vpp lt 3 6V 025xVpp V 1475V lt Vpp lt 5 25V Viui2c Input hig
10. Note For Die sales information contact a local Cypress sales office or Field Applications Engineer FAE Ordering Code Definitions CY 8 C 24 xxx SPxx Ne Package Type PX PDIP Pb free SX SOIC Pb free PVX SSOP Pb free LFX LKX QFN Pb free AX TQFP Pb Free Speed 24 MHz Part Number Family Code Technology Code C CMOS Marketing Code 8 Cypress PSoC Company ID CY Cypress Thermal Rating C Commercial Industrial E Extended Note 43 This part may be used for in circuit debugging It is NOT available for production Document Number 38 12028 Rev V Page 60 of 71 CY8C24123A Eng CY8C24223A CYPRESS CY8C24423A PERFORM Acronyms Acronyms Used Table 53 lists the acronyms that are used in this document Table 53 Acronyms Used in this Datasheet Acronym Description Acronym Description AC alternating current MIPS million instructions per second ADC analog to digital converter OCD on chip debug API application programming interface PCB printed circuit board CMOS complementary metal oxide semiconductor PDIP plastic dual in line package CPU central processing unit PGA programmable gain amplifier CRC cyclic redundancy check PLL phase locked loop CT continuous time POR power on reset DAC digital to analog converter PPOR precision power on reset DC direct current PRS pseudo random se
11. dB Opamp bias minimum is 60 dB VouicuoA High output voltage swing internal signals Power high Opamp bias high Power low Opamp bias low Vpp 0 2 V setting is not allowed for 3 3 V Vpp Power medium Opamp bias low Vpp 0 2 V operation Power high Opamp bias low Vpp 0 2 V Votowoa Low output voltage swing internal signals Power high Opamp bias high Power low ppamp Opamp bias low 0 2 setting is not allowed for 3 3 V Vpp Power medium Opamp bias low 0 2 V operation Power high Opamp bias low 0 2 Ison Supply current including associated AGND Power high Opamp bias high buffer setting is not allowed for 3 3 V Vpp Power low Opamp bias low 150 200 uA operation Power low Opamp bias high 300 400 uA Power medium Opamp bias low 600 800 uA Power medium Opamp bias high 1200 1600 uA Power high Opamp bias low 2400 3200 uA Power high Opamp bias high pA PSRRoA Supply voltage rejection ratio 64 80 dB Vgs lt Vin X Vpp 2 25 or Von 125 V Vin Vpn Document Number 38 12028 Rev V Page 22 of 71 m CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM Table 16 2 7 V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes Vosoa Input offset voltage absolute value Power high Opamp bias high Power low Opamp bias
12. Peci System Resets era Bump a Pull up pull down high Z strong or open drain drive modes i on all GPIOs SYSTEM RESOURCES 9 Eight standard analog inputs on all GPIOs and four additional analog inputs with restricted routing a Two 30 mA analog outputs on all GPIOs a Configurable interrupt on all GPIOs Errata For information on silicon errata see Errata on page 67 Details include trigger conditions devices affected and proposed workaround Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document Number 38 12028 Rev V Revised January 13 2015 PERFORM More Information CY8C24123A CY8C24223A CY8C24423A Cypress provides a wealth of data at www cypress com to help you to select the right PSoC device for your design and to help you to quickly and effectively integrate the device into your design Following is an abbreviated list for PSOC 1 m Overview PSoC Portfolio PSoC Roadmap m Product Selectors PSoC 1 PSoC 3 PSoC 4 or PSoC 5LP In addition PSoC Designer offers a device selection tool within PSoC 1 at the time of creating a new project m Datasheets Describe and provide electrical specifications for all the PSoC 1 family of devices Visit the PSoC 1 datasheets web page for a complete list m Application notes and code examples a Visit the PSoC 1 Code Examples web page for a comprehen sive list of code examples a Cypress offers a large number
13. 1 300 P2 4 1 283 V P2 4 Vpp 2 0b110 RefPower high VREFHI Ref High 2 x Bandgap 2 512 2 594 2 654 V Opamp bias high Viseno AGND Bandgap 1 250 1 303 1 346 V VREFLO Ref Low Vss Vss Vss 0 011 Vss 0 027 V RefPower high VREFHI Ref High 2 x Bandgap 2 515 2 592 2 654 V Opamp bias low Viseno AGND Bandgap 1 253 1 301 1 340 V VREFLO Ref Low Vss Vss Vss 0 006 Vss 0 02 V RefPower medium VkerHi Ref High 2 x Bandgap 2 518 2 593 2 651 V Opamp bias high Viseno AGND Bandgap 1 254 1 301 1 338 V VREFLO Ref Low Vss Vss Vss 0 004 Vss 0 017 V RefPower medium VREFHI Ref High 2 x Bandgap 2 517 2 594 2 650 V Opamp bias low Viseno AGND Bandgap 1 255 1 300 1 337 V VnEFLO Ref Low Vss Vss Vss 0 003 Vss 0 015 V 0b111 RefPower high VREFHI Ref High 3 2 x Bandgap 4 011 4 143 4 203 V Opamp bias high Viseno AGND 1 6 x Bandgap 2 020 2 075 2 118 V VREFLO Ref Low Vss Vss Vss 0 011 Vss 0 026 V RefPower high VREFHI Ref High 3 2 x Bandgap 4 022 4 138 4 203 V Opamp bias low Viseno AGND 1 6 x Bandgap 2 023 2 075 2 114 V VREFLO Ref Low Vss Vss Vss 0 006 Vss 0 017 V RefPower medium VkerHi Ref High 3 2 x Bandgap 4 026 4141 4 207 V Opamp bias high Viseno AGND 1 6 x Bandgap 2 024 2 075 2 114 V VnEFLO Ref Low Vss Vss Vss 0 004 Vss 0 015 V RefPower medium VkerHi Ref High 3 2 x Bandgap 4 030 4 143 4 206 V Opamp bias low Viseno AGND 1 6 x Bandgap 2 024 2 076 2 112 V VREFLO Ref
14. 2D Ww ACC DRO ED RW DCBO3DR2 2E RW ACC_DR3 EE RW DCBO3CRO 2F ACC_DR2 EF RW 30 ACBOOCR3 RDIORI FO 31 ACBOOCRO RDIOSYN F1 32 ACBOOCR1 RDIOIS F2 33 ACBOOCR2 RDIOLTO F3 34 ACBO1CR3 RDIOLT1 F4 35 ACBO1CRO RDIOROO F5 36 ACBO1CR1 RDIORO1 F6 37 ACBO1CR2 CPU F F7 RL 38 F8 39 F9 3 FB 3 FC 2 f 1 18 I FD SE erst re 7 SF rf YPC F Blank fields are Reserved and must not be accessed Access is bit specific Document Number 38 12028 Rev V Page 16 of 71 CY8C24123A We s CY8C24223A CYPRESS CY8C24423A PERFORM Table 0 1 Register Map Bank 1 Table Configuration Space Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access PRTODMO 00 RW 40 ASC10CRO 80 RW CO PRTODM1 01 RW 41 ASC10CR1 81 RW C1 PRTOICO 02 RW 42 ASC10CR2 82 RW C2 PRTOIC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DMO 04 RW 44 ASD11CRO 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1ICO 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DMO 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2ICO 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB OC 4C 8C CC OD 4D 8D CD OE 4E 8E CE OF 4F 8F CF 10 50 ASD20CRO 90 RW GDI O IN DO RW 11 51 ASD20CR1 91 RW GDI E IN D1 RW 12 52 ASD20CR2
15. low 2400 3200 yA Power high Opamp bias high 4600 6400 yA PSRRoa Supply voltage rejection ratio 64 80 dB Vss lt Vin lt Vpp 2 25 or Vpp 1 25 V lt Vin lt Vpp Document Number 38 12028 Rev V Page 21 of 71 ON CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM Table 15 3 3 V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes VosoA Input offset voltage absolute value Power high Opamp bias high Power low Opamp bias high 1 65 10 mV setting is not allowed for 3 3 V Vpp Power medium Opamp bias high 1 32 8 mV operation Power high Opamp bias high mV TCVosoa Average input offset voltage drift 7 0 35 0 uV C IEBOA Input leakage current port 0 analog pins 20 pA Gross tested to 1 uA Cinoa Input capacitance port 0 analog pins 4 5 9 5 pF Package and pin dependent Temp 25 C Vcmoa Common mode voltage range 0 2 Vpp 02 V The common mode input voltage range is measured through an analog output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer GoLoA Open loop gain Specification is applicable at low Power low ppamp Opamp bias low 60 dB Opamp bias For high Opamp bias Power medium Opamp bias low 60 dB mode except high power high Power high Opamp bias low 80
16. Bandgap 1 160 1 300 1 337 V VREFLO Ref Low Vss Vss Vss 0 002 Vss 0 011 V RefPower low VREFHI Ref High 2 x Bandgap Not allowed Not allowed Not allowed V Opamp bias high VAGND AGND Bandgap 1 252 1 300 1 339 V VREFLO Ref Low Vss Vss Vss 0 002 Vss 0 011 V RefPower low VREFHI Ref High 2 x Bandgap Not allowed Not allowed Not allowed V Opamp bias low VAGND AGND Bandgap 1 252 1 300 1 339 V VREFLO Ref Low Vss Vss Vss 0 001 Vss 0 01 V 0b111 All power settings Not allowed at 2 7 V DC Analog PSoC Block Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C x Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 25 DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units Notes Ret Resistor unit value continuous time 12 2 kQ Csc Capacitor unit value switched capacitor 80 fF Document Number 38 12028 Rev V Page 34 of 71 CY8C24123A fe CY8C24223A CYPRESS CY8C24423A PERFORM DC POR SMP and LVD Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran
17. DC24M 24 MHz duty cycle 40 50 60 96 DC o ILO duty cycle 20 50 80 96 Step24M 24 MHz trim step size 50 kHz Fout48M 48 MHz output freguency 46 8 48 0 49 204 251 MHz Trimmed Using factory trim values FMAX Maximum frequency of signal on row input 12 3 MHz or row output SRpowER UP Power supply slew rate 250 V ms Vpp slew rate during power up tpowERUP Time from end of POR to CPU executing 16 100 ms Power up from 0 V See the System code Resets section of the PSoC Technical Reference Manual tjit IMO 28 24 MHz IMO cycle to cycle jitter RMS 200 700 ps IN 32 24 MHz IMO long term N cycle to cycle 300 900 ps jitter RMS 24 MHz IMO period jitter RMS 100 400 ps tit p Pl 24 MHz IMO cycle to cycle jitter RMS 200 800 ps N 32 24 MHz IMO long term N cycle to cycle 300 1200 jitter RMS 24 MHz IMO period jitter RMS 100 700 Notes 24 4 75 V lt Vpp lt 5 25 V 25 3 0 V lt Vpp lt 3 6 V See application note Adjusting PSoC Trims for 3 3 V and 2 7 V Operation AN2012 for information on trimming for operation at 3 3 V 26 Refer to Cypress Jitter Specifications application note Understanding Datasheet Jitter Specifications for Cypress Timing Products AN5054 for more information Document Number 38 12028 Rev V Page 38 of 71 P CYPRESS PERFORM Table 30 2 7 V AC Chip Level Specifications CY8C24123A CY8C24223A CY8C24423A
18. Description Mi Typ Max Units Foscext Frequency with CPU clock divide by 182 0 093 12 3 MHz Foscext Freguency with CPU clock divide by 2 or greater 0 186 24 6 MHz High period with CPU clock divide by 1 41 7 5300 ns fLowperiodwith CPU clock divideby1 1 447 m Power up IMO to switch 150 us Notes 32 Maximum CPU frequency is 12 MHz at 3 3 V With the CPU clock divider set to 1 the external clock must adhere to the maximum frequency and duty cycle requirements 33 If the frequency of the external clock is greater than 12 MHz the CPU clock divider must be set to 2 or greater In this case the CPU clock divider ensures that the fifty percent duty cycle requirement is met Document Number 38 12028 Rev V Page 48 of 71 CY8C24123A Ze Z CY8C24223A CYPRESS CY8C24423A PERFORM Table 44 2 7 V AC External Clock Specifications Symbol Description Min Typ Max Units Notes Foscext Frequency with CPU clock divide by 114 0 093 12 3 MHz Foscext Frequency with CPU clock divide by 2 or greater 0 186 12 3 MHz High period with CPU clock divide by 1 41 7 5300 ns Low period with CPU clock divide by 1 41 7 ns Power up IMO to switch 150 us AC Programming Specifications Table 45 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40
19. MHz divided by 8 Vpp 2 4 75 V 1 stop bit 25 2 MHz Vpp lt 4 75 V 25 2 MHz Receiver Input clock frequency 1 The baud rate is equal to the input clock frequency divided by 8 Vpp 4 75 V 2 stop bits 50 4 MHz Vpp 2 4 75 V 1 stop bit 25 2 MHz Vpp lt 4 75 V 25 2 MHz Note 30 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nominal period Document Number 38 12028 Rev V Page 45 of 71 PERFORM Table 38 2 7 V AC Digital Block Specifications CY8C24123A CY8C24223A CY8C24423A Function Description Min Typ Max Units Notes All Block input clock frequency 12 7 MHz 2 4V lt Vpp lt 3 0 V Functions Timer Capture pulse width 1001811 ns Input clock frequency with or without capture 12 7 MHz Counter Enable Input Pulse Width 1001811 ns Input clock frequency no enable input 12 7 MHz Input clock freguency enable input 12 7 MHz Dead Band Kill pulse width Asynchronous restart mode 20 ns Synchronous restart mode 1001811 ns Disable mode 1001811 ns Input clock frequency 12 7 MHz CRCPRS Input clock freguency 12 7 MHz PRS Mode CRCPRS Input clock freguency 12 7 MHz CRC Mode SPIM Input clock frequency 6 35 MHz The SPI serial clock SCLK freguency is egual to the input cl
20. P2 4 1 197 V P2 4 Vpp 2 RefPower high VREFHI Ref High P2 4 Bandgap P2 4 1 209 P2 4 1 289 P2 4 1 353 V Opamp bias low P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 Bandgap P2 4 1 352 P2 4 1 294 P2 4 1 222 V P2 4 Vpp 2 RefPower medium Vggrui Ref High P2 4 Bandgap P2 4 1 218 P2 4 1 291 P2 4 1 351 V Opamp bias high P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 Bandgap P2 4 1 351 P2 4 1 296 P2 4 1 224 V P2 4 Vpp 2 RefPower medium VREFHI Ref High P2 4 Bandgap P2 4 1 215 P2 4 1 292 P2 4 1 354 V Opamp bias low P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 Bandgap P2 4 1 352 P2 4 1 297 P2 4 1 227 V P2 4 Vpp 2 0b110 RefPower high VREFHI Ref High 2 x Bandgap 2 460 2 594 2 695 V Opamp bias high eun AGND Bandgap 1 257 1 302 1 335 V VREFLO Ref Low Vss Vss Vss 0 01 Vss 0 029 V RefPower high VREFHI Ref High 2 x Bandgap 2 462 2 592 2 692 V Opamp bias low_ V un AGND Bandgap 1 256 1 301 1 332 V VREFLO Ref Low Vss Vss Vss 0 005 Vss 0 017 V RefPower medium Vggreui Ref High 2 x Bandgap 2 473 2 593 2 682 V Opampbias high y p AGND Bandgap 1 257 1 301 1 330 V VREFLO Ref Low Vss Vss Vss 0 003 Vss 0 014 V RefPower medium Vrefi Ref High 2 x Bandgap 2 470 2 594 2 685 V Opamp bias low Ty aun
21. for digital signaling when using an analog resource that depends on the analog reference Some coupling of the digital signal may appear on the AGND Table 22 5 V DC Analog Reference Specifications Reference ARF CR ADI DON Symbol Reference Description Min Typ Max Units 5 3 Settings 0b000 RefPower high Vrerui Ref High Vpp 2 Bandgap Vpp 2 1 136 Vpp 2 1 288 Vpp 2 1 409 V Opamp bias high Viseno AGND Vppi2 Vpp 2 0 138 Vpp 2 0 003 Vpp 2 0 132 V Vrerio Ref Low Vpp 2 Bandgap Vpp 2 1 417 Vpp 2 1 289 Vpp 2 1 154 V RefPower high Vrerui RefHigh Vpp 2 Bandgap Vpp 2 1 202 Vpp 2 1 290 Vpp 2 1 358 V Opamp bias low Viseno AGND Vpp 2 Vpp 2 0 055 Vpp 2 0 001 Vpp 2 0 055 V VREFLO Ref Low Vpp 2 Bandgap Vpp 2 1 369 Vpp 2 1 295 Vpp 2 1 218 V RefPower medium VkerHi Ref High Vpp 2 Bandgap Vpp 2 1 211 Vpp 2 1 292 Vpp 2 1 357 V Opamp bias high Viseno AGND Vpp 2 Vpp 2 0 055 Vpo 2 Vpp 2 0 052 V VREFLO Ref Low Vpp 2 Bandgap Vpp 2 1 368 Vpp 2 1 298 Vpp 2 1 224 V RefPower medium Vggrui Ref High Vpp 2 Bandgap Vpp 2 1 215 Vpp 2 1 292 Vpp 2 1 353 V Opamp bias low y 5 AGND Vppi2 Vpp 2 0 040 Vpp 2 0 001 Vpp 2 0 033 V VREFLO Ref Low Vpp 2 Bandgap Vpp 2 1 368 Vpp 2 1 299 Vpp 2 1 2
22. high 1 65 10 mV setting is not allowed for 2 7 V Vpp Power medium Opamp bias high 1 32 8 mV operation Power high Opamp bias high mV TCVosoa Average input offset voltage drift 7 0 35 0 uV C lepoa Input leakage current port 0 analog pins 20 pA Gross tested to 1 pA Cinoa Input capacitance port 0 analog pins 4 5 9 5 pF Package and pin dependent Temp 25 C Vcmoa Common mode voltage range 0 2 Vpp 0 2 V The common mode input voltage range is measured through an analog output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer GoLoA Open loop gain Specification is applicable at low Power low Opamp bias low 60 dB Opamp bias For high Opamp bias Power medium Opamp bias low 60 dB mode except high power high Power high Opamp bias low 80 dB Opamp bias minimum is 60 dB VouicuoA High output voltage swing internal signals Power high Opamp bias high Power low Opamp bias low Vpp 0 2 V setting is not allowed for 2 7 V Vpp Power medium Opamp bias low Vpp 0 2 V operation Power high Opamp bias low Vpp 0 2 V Votowoa Low output voltage swing internal signals Power high Opamp bias high Power low Opamp bias low 0 2 setting is not allowed for 2 7 V Vpp Power medium Opamp bias low 0 2 V
23. 013 0 330 0 004 0 101 0 015 0 3811 0 0125 0 317 0 050 1 270 IF 0019t0 4821 0 0118 0 2991 0 050 1 2701 YP 51 85024 F Document Number 38 12028 Rev V Page 53 of 71 PERFORM CY8C24123A CY8C24223A Figure 22 28 Pin 300 Mil Molded DIP SEE LEAD END a 14 AN MIN pl pl A gs fh pl ain gui DIMENSIONS IN INCHESEMM WAX i 4 REFERENCE JEDEC MO 095 q 0 295 7 491 PACKAGE WEIGHT 2 15gms hr hg Sr hd hr hg hg hg FT PART 15 28 7 P28 3 STANDARD PKG TI I 0 08012 03 PZ28 3 LEAD FREE PKG SEATING PLANE 1345134161 1 385 35 181 10 29017 361 p 0 358 251 0 120 3 051 0140L3 551 019014 821 Hi 1014013553 T T 01601406 x A ER 0 01210 301 S MIN SET TUE Eom SEES ue 0 06011 521 321 _ 1 03107 871 0 09012 281 0 065 1 65 0 38519 783 0 11012 793 001510381 0 020 0 501 SEE LEAD END OPTION LEAD END OPTION LEAD 1 14 15 amp 28 ah Tn 51 85014 G sebut L14l 1 Figure 23 28 Pin 210 Mil SSOP 114 DIA PIN 1 ID A 114 0 u o Pr P el DIMENSIONS IN MILLIMETERS MIN 1 SEATING PLANE E 0 65 BSC 2 00 1 65 MAX 185
24. 20 Pin 210 Mil SSOP 1 14 114 DIA 10 PIN 1 ID FEET 7 50 8 10 DIMENSIONS IN MILLIMETERS MIN MAX i LU UU UU UU LU 11 20 7 00 235 MIN DE 40 0 MIN GAUGE PLANE 0 25 SEATING PLANE 0 65 BSC 5 00 j 2 00 165 0 55 un UE MAX 185 095 125 REF com 1 pos 0 21 0 22 1P 0 38 51 85077 F Figure 21 20 Pin 300 Mil Molded SOIC PIN 1 ID NITE 1 JEDEC STD REF MO 119 10 1 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT T DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE 3 DIMENSIONS IN INCHES MIN MAX 0 29117 3911 4 PACKAGE WEIGHT 0 559ms 0 30017 6201 0 394 10 0071 0 419110 6421 11 20 002610660 0 03210 8121 PART 20 3 STANDARD PKG L 257112653 E SEATING PLANE SZ20 3 LEAD FREE PKG 0 513113 0301 0 09212 336 0 10512 6671 i JON I 0 00410 1013 E 0 0091 0 2311 0
25. 6 1 3 V Document Number 38 12028 Rev V Page 29 of 71 CY8C24123A CYPRESS CY8C24423A PERFORM Table 22 5 V DC Analog Reference Specifications continued Reference Reference Power ARF_CR Symbol Reference Description Min Typ Max Units 5 3 Settings 0b101 RefPower high Vrerui RefHigh P2 4 Bandgap P2 4 1 228 P2 4 1 284 P2 4 1 332 V Opamp bias high P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 VrefLo RefLow P2 4 Bandgap P2 4 1 358 P2 4 1 293 P2 4 1 226 V P2 4 Vpp 2 RefPower high Vrerui RefHigh P2 4 Bandgap P2 4 1 236 P2 4 1 289 P2 4 1 332 V Opamp bias low P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 Vrerio RefLow P2 4 Bandgap P2 4 1 357 P2 4 1 297 P2 4 1 229 V P2 4 Vpp 2 RefPower medium Veer RefHigh P2 4 Bandgap P2 4 1 237 P2 4 1 291 P2 4 1 337 V Opamp bias high P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 Vrerio Ref Low P2 4 Bandgap P2 4 1 356 P2 4 1 299 P2 4 1 232 V P2 4 Vpp 2 RefPower medium Veer Ref High P2 4 Bandgap P2 4 1 237 P2 4 1 292 P2 4 1 337 V Opamp bias low P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 E VrefLo Reflow P2 4 Bandgap P2 4 1 357 P2 4
26. 92 RW GDI O OU D2 RW 13 53 ASD20CR3 93 RW GDI E OU D3 RW 14 54 ASC21CRO 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC GO EN DD RW 1E 5E 9E OSC CR4 DE RW 1F 5F 9F OSC CR3 DF RW DBBOOFN 20 RW CLK CRO 60 RW A0 OSC CRO EO RW DBBOOIN 21 RW CLK CR1 61 RW A1 OSC CR1 E1 RW DBBO0OU 22 RW ABF_CRO 62 RW A2 OSC_CR2 E2 RW 23 AMD_CRO 63 RW A3 VLT_CR E3 RW DBBO1FN 24 RW 64 A4 VLT_CMP E4 R DBBO1IN 25 RW 65 A5 E5 DBB010U 26 RW AMD CR1 66 RW A6 E6 27 ALT_CRO 67 RW AT E7 DCBO2FN 28 RW 68 A8 IMO TR E8 W DCBO2IN 29 RW 69 A9 ILO TR E9 Ww DCBO2OU 2A RW 6A AA BDG TR EA RW 2B 6B AB ECO TR EB W DCBO3FN 2C RW 6C AC EC DCBO3IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE 2F 6F AF EF 30 ACBOOCR3 70 RW RDIORI BO RW FO 31 ACBOOCRO 71 RW RDIOSYN B1 RW F1 32 ACBOOCR1 72 RW RDIOIS B2 RW F2 33 ACBOOCR2 73 RW RDIOLTO B3 RW F3 34 ACBO1CR3 74 RW RDIOLT1 B4 RW F4 35 ACBO1CRO 75 RW RDIOROO B5 RW F5 36 ACBO1CR1 76 RW RDIORO1 B6 RW F6 37 ACBO1CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 19 B9 F9 3A TA BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU SCR1 FE 3F 7F BF CPU_SCRO FF Blank fields are Reserved and must not be accessed Access is bit specific Document Number 38 12028 Rev V Page 17 of 71 CY8C24123A I CY8C24223A CYPRESS CY8C24423A PERFORM Electrical Specifications This section presents the DC and AC electrical spec
27. AGND Bandgap 1 256 1 300 1 332 V VREFLO Ref Low Vss Vss Vss 0 002 Vss 0 012 V 0b111 All power settings Not allowed at 3 3 V Document Number 38 12028 Rev V Page 320f 71 CY8C24123A s CYPRESS CY8C24423A PERFORM Table 24 2 7 V DC Analog Reference Specifications Keteange Reference Power ARF CR Symbol Reference Description Min Typ Max Units 5 3 Settings 0b000 All power settings Not allowed at 2 7 V 0b001 RefPower medium VREFHI Ref High P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias high Vpp 2 P2 6 0 5 V 0 739 0 016 0 759 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 1 675 0 013 1 825 RefPower medium VREFHI Ref High P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias low Vpp 2 P2 6 0 5 V 0 098 0 011 0 067 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 308 0 004 0 362 RefPower low VREFHI Ref High P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias high Vpp 2 P2 6 0 5 V 0 042 0 005 0 035 VAGND AGND P2 4 P2 4 P2 4
28. ICE Flex Pod for CY8C29x66 family m Cat 5 adapter m Mini Eval programming board m 110 240 V power supply Euro Plug adapter m iMAGEcraft C compiler registration required m ISSP cable m USB 2 0 cable and Blue Cat 5 cable m 2 CY8C29466 24PXI 28 PDIP chip samples Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store Document Number 38 12028 Rev V CY8C24123A CY8C24223A CY8C24423A CY3210 MiniProg1 The CY3210 MiniProg1 kit lets you to program PSoC devices through the MiniProg1 programming unit The MiniProg is a small compact prototyping programmer that connects to the PC through a provided USB 2 0 cable The kit includes m MiniProg programming unit m MiniEval socket programming and evaluation board m 28 pin CY8C29466 24PXI PDIP PSoC device sample m 28 pin CY8C27443 24PXI PDIP PSoC device sample m PSoC Designer software CD m Getting Started guide m USB 2 0 cable CY3210 PSoCEval1 The CY3210 PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit The evaluation board includes an LCD module potentiometer LEDs and plenty of bread boarding space to meet all of your evaluation needs The kit includes m Evaluation board with LCD module m MiniProg programming unit m 28 pin CY8C29466 24PXI PDIP PSoC device sample 2 m PSoC Designer software CD m Getting Started guide m USB 2 0 cable CY3214 PSoCEvalUSB The CY3214 PSoCEvalUSB evaluation kit fe
29. INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 38 12028 Rev V Revised January 13 2015 Page 71 of 71 PSoC Designer is a trademark and PSoC6 is a registered trademark of Cypress Semiconductor Corporation All other trademarks or registered trademarks referenced herein are property of the respective corporations Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an Cc system provided that the system conforms to the I C Standard Specification as defined by Philips As from October 1st 2006 Philips Semiconductors has a new trade name NXP Semiconductors
30. P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 030 0 030 RefPower low VREFHI Ref High P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias low Vpp 2 P2 6 0 5 V 0 367 0 005 0 308 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 345 0 301 0b010 RefPower high VREFHI Ref High Vpp Vpp 0 100 Vpp 0 003 Vpp V Opamp bias high VAGND AGND Vpp 2 Vpp 2 0 038 Vpp 2 Vpp 2 0 036 V VREFLO Ref Low Vss Vss Vss 0 005 Vss 0 016 V RefPower high VREFHI Ref High Vpp Vpp 0 065 Vpp 0 002 Vbp V Opamp bias low VAGND AGND Vpp 2 Vpp 2 0 025 Vpp 2 Vpp 2 0 023 V VREFLO Ref Low Vss Vss Vss 0 003 Vss 0 012 V RefPower medium VREFHI Ref High Vpp Vpp 0 054 Vbpp 0 002 Vbp V Opamp bias high VAGND AGND Vpp 2 Vpp 2 0 024 Vpp 2 0 001 Vpp 2 0 020 V VREFLO Ref Low Vss Vss Vss 0 002 Vss 0 012 V RefPower medium VREFHI Ref High Vpp VDD 0 042 Vpp 0 002 Vbp V Opamp Tow eren AGND pola Vpp 2 0 027 Vpg 2 0 001 Vpp 2 0 022 V VREFLO Ref Low Vss Vss Vss 0 001 Vss 0 010 V RefPower low VREFHI Ref High Vpp Vpp 0 042 Vpp 0 002 Vpp V Opamp bias aa aug AGND pola Vpp 2 0 028 Vpp 2 0 001 Vpp 2 0 023 V VREFLO Ref Low Vss Vss Vss 0 001 Vss 0 010 V RefPower lo
31. QI o10 f oos 0 21 IL 022 0 38 Document Number 38 12028 Rev V 235 MIN GAUGE PLANE 0 25 EF elc MAX 95 51 85079 F Page 54 of 71 CY8C24123A EE CY8C24223A CYPRESS CY8C24423A Figure 24 28 Pin 300 Mil Molded SOIC NOTE 1 JEDEC STD REF MO 119 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED PIN 1 ID AT THE MOLD PARTING LINE MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE 3 DIMENSIONS IN INCHES MIN LAMANYA AAN 0 2917 39 0 300 7 62 0 394 10 01 0 419 10 64 ITTTTTTTTTTTT _ PL 0 026 0 66 8283 STANDARD PKG 0 032 0 81 228 3 LEAD FREE PKG SX28 3 LEAD FREE PKG s 0 697 17 70 7 SEATING PLANE 0 713 18 11 0 092 2 33 J4 0 105 2 67 18 H m Hd H H m D m D mi O T 1 I 0 00410 101 Lt 0 0091 0 23 H LL 001300331 0 004 0 10 00180038 901251847 0 05011 27 0 019 0 48 0 011810 301 0 050 1 27 TYP 51 85026 H Document Number 38 12028 Rev V Page 55 of 71 EM CY8C24123A Ar CY8C24223A CY8C24423A PERFORM Figure 25 32 Pin Sawn QFN Package
32. The workaround mentioned above should be used Document Number 38 12028 Rev V Page 67 of 71 Document History Page PERFORM CY8C24123A CY8C24223A CY8C24423A Document Title CY8C24123A CY8C24223A CY8C24423A PSoC Programmable System on Chip Document Number 38 12028 Revision ECN Choise Sup Sn Description of Change m 236409 SFV See ECN New silicon and new document Preliminary datasheet A 247589 SFV See ECN Changed the title to read Final datasheet Updated Electrical Specifications chapter B 261711 HMT See ECN Input all SFV memo changes Updated Electrical Specifications chapter C 279731 HMT See ECN Update Electrical Specifications chapter including 2 7 VIL DC GPIO spec Add Solder Reflow Peak Temperature table Clean up pinouts and fine tune wording and format throughout D 352614 HMT See ECN Add new color and CY logo Add URL to preferred dimensions for mounting MLF packages Update Transmitter and Receiver AC Digital Block Electrical Specifi cations Re add ISSP pinout identifier Delete Electrical Specification sentence re devices running at greater than 12 MHz Update Solder Reflow Peak Temper ature table Fix CY com URLs Update CY copyright E 424036 HMT See ECN Fix SMP 8 pin SOIC error in Feature and Order table Update 32 pin QFN E Pad dimensions and rev A Add ISSP note to pinout tables Update typical and recommended Storage Temperatur
33. be met This is automatically the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line trmax tsupat 1000 250 1250 ns according to the Standard Mode I C bus specification before the SCL line is released Document Number 38 12028 Rev V Page 50 of 71 CYPRESS PERFORM Packaging Information CY8C24123A CY8C24223A CY8C24423A This section illustrates the packaging specifications for the CY8C24x23A PSoC device along with the thermal impedances for each package and the typical package capacitance on crystal pins Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tools dimensions see the emulator pod drawings at http www cypress com design MR10161 Packaging Dimensions 0 380 Figure 17 8 Pin 300 Mil PDIP B 0 390 PIN 1 ID 4 1 DIMENSI o 0 240 0 260 5 8 I 0 100 BSC SEATING ni PLANE 0 180 MAX 0 145 0 125 0 015 MIN 0 140 JILL 0055 0 070 0014 0 022 Document Number 38 12028 Rev V NS IN INCHES MIN MAX 0 300 0385 0 008 0 015 CEN 0 0 430 MAX 51 85075 D Page 51 of 71 Figure 18 8 Pin 150 Mil
34. by which the average of a set of values departs from a reference value 3 The electrical mechanical magnetic or other force field applied to a device to establish a reference level to operate the device block 1 A functional unit that performs a single function such as an oscillator 2 A functional unit that may be configured to perform one of several functions such as a digital PSoC block or an analog PSoC block buffer 1 A storage area for data that is used to compensate for a speed difference when transferring data from one device to another Usually refers to an area reserved for IO operations into which data is read or from which data is written 2 A portion of memory set aside to store data often before it is sent to an external device or as it is received from an external device 3 An amplifier used to lower the output impedance of a system bus 1 Anamed connection of nets Bundling nets together in a bus makes it easier to route nets with similar routing patterns 2 A set of signals performing a common function and carrying similar data Typically represented using vector notation for example address 7 0 3 One or more conductors that serve as a common connection for a group of related devices clock The device that generates a periodic signal with a fixed frequency and duty cycle A clock is sometimes used to synchronize different logic blocks comparator An electronic circuit that produces an output voltage
35. cation tips from experts on the devices kits For example Flash read write access from firmware explains how we can read and write to flash in PSoC 1 devices PSoC Designer is a free Windows based Integrated Design Environment IDE It enables concurrent hardware and firmware design of systems based on CapSense see Figure 1 With PSoC Designer you can 1 Drag and drop user modules to build your hardware system design in the main design workspace 2 Codesign your application firmware with the PSoC hardware using the PSoC Designer IDE C compiler 3 Configure user module 4 Explore the library of user modules 5 Review user module datasheets Figure 1 PSoC Designer Features File Edit View Project Interconnect Build Debug Program Tools Window Help Hd SEL ET Aree Global Resources pdproje AX startpage pdprojects Chip 2 Jam QA 4 gt x WorkspaceEplorer eA CPU Clock 3 MHz SysCIk 8 7 600 97 GOE aoak a 32K Select Intemal 5 Aa E GT Workspace POPea 1 F Sleep Timer 512 Hz E 2 PDProjectS CY8C24423 VC1 SysCk 16 S E PDProect5 Chip VC2 VC1 16 iy Loadable Corta VC3 Source VC2 sag VC3 Divider 256 Si SysCik Sour Intemal 24 MHz SysCIk 2 Dis No Analog Powe SC On Ref Bot Mane AI Row CPU Clock Selects the CPU clock speed fes 33 75 KHz to 24 MHz Derved from th g
36. condition 4 7 0 6 us tHDDATI2C Data hold time 0 0 Hus tsupAroc Data setup time 250 1001871 i ns tsustoizc Setup time for stop condition 4 0 0 6 HS tBuFI2C Bus free time between a stop and start condition 4 7 1 3 us tsp2c Pulse width of spikes are suppressed by the input filter 0 50 ns Table 47 AC Characteristics of the IC SDA and SCL Pins for Vpp 3 0 V Fast Mode Not Supported PN Standard Mode Fast Mode 1 Symbol Description Units Min Max Min Max Fscui2c SCL clock frequency 0 100 kHz tupsTai2c Hold time repeated start condition After this period the first clock 4 0 Hs pulse is generated tiowi2c Low period of the SCL clock 4 7 us tuicuizc High period of the SCL clock 4 0 HS tSUSTAI2C Setup time for a repeated start condition 4 7 HS tHDDATI2C Data hold time 0 Hs tsupaTi2c Data setup time 250 ns tsustoizc Setup time for stop condition 4 0 HS tBuFI2C Bus free time between a stop and start condition 4 7 Hs tsPi2c Pulse width of spikes are suppressed by the input filter ns Figure 16 Definition for Timing for Fast Standard Mode on the Pc Bus 1 I2C SDA Tsupati2zc I la Tupstai2c S f STOP Condition 4 Repeated START Condition START Condition Note 37 A fast mode 12C bus device can be used in a Standard Mode I C bus system but the requirement tsupar 2 250 ns must then
37. example PO 2 P1 4 maximum 100 mA on odd port pins for example PO 3 P1 5 150 mA maximum combined lo budget loH High level source current 10 mA Vok Vpp 1 0 V see the limitations of the total current in the note for Voy lot Low level sink current 25 mA Vo 0 75V see the limitations of the total current in the note for VoL ViL Input low level 0 8 V IVpp 3 0to 5 25 Vin Input high level 2 1 V Vpp 3 0 to 5 25 Vu Input hysterisis 60 mV In Input leakage absolute value 1 nA Gross tested to 1 yA Cin Capacitive load on pins as input 3 5 10 pF Package and pin dependent Temp 25 C Cout Capacitive load on pins as output 3 5 10 pF Package and pin dependent Temp 25 C Table 13 2 7 V DC GPIO Specifications Symbol Description Min Typ Max Units Notes Rpy Pull up resistor 4 5 6 8 KQ Rpp Pull down resistor 4 5 6 8 KQ VoH High output level Vpp 0 4 V lon 2 mA 6 25 Typ Vpp 2 4 to 3 0 V 16 mA maximum 50 mA Typ combined lop budget VoL Low output level 0 75 V lo 11 25 mA Vpp 2 4 to 3 0 V 90 mA maximum combined lo budget loH High level source current 2 m mA Vox Vpp 0 4 see the limitations of total current in note for Voy Vi Input low level 0 75 V Vbpp 2 4 to 3 0 Vin Input high level 2 0 V Vbpp 2 4 to 3 0 Vu Input hysteresis 90 mV lo Low level sink current 11 25 mA Vor 75 see the limitations of total cu
38. of PSoC application notes covering a broad range of topics from basic to advanced level Recommended application notes for getting started with PSoC 1 are AN75320 Getting Started with PSoC 1 AN2094 PSoC 1 Getting Started with GPIO AN2015 PSoC 1 Getting Started with Flash amp E2PROM AN2014 Basics of PSoC 1 Programming AN32200 PSoC 1 Clocks and Global Resources AN2010 PSoC 1 Best Practices and Recommendations m Technical Reference Manual TRM PSoC Designer a Visit the PSoC 1 TRM page for the complete list of TRMs Following documents provide detailed descriptions of the Ar chitecture Programming specification and Register map de tails of CY8C2XXXX PSoC 1 device family PSoC1 CY8C2XXXX TRM PSoC1 ISSP Programming Specifications m Development Kits o CY3210 CY8C24x23 PSoC R Evaluation Pods EvalPod are 28 pin PDIP adapters that seamlessly connect any PSoC device to the 28 pin PDIP connector on any Cypress PSoC development kit CY3210 24x23 provides evaluation of the CY8C24x23A PSoC device family on any PSoC developer kit PSoC developer kits are sold separately a Visit the PSoC 1 Kits page and refer the Kit Selector Guide document to find out the suitable development kits and debuggers for all PSoC 1 families m The CY3217 MiniProg1 and CY8CKIT 002 PSoC MiniProg3 device provide an interface for flash programming m Knowledge Base Articles KBA Provide design and appli
39. operation Power high Opamp bias low 0 2 Ison Supply current including associated AGND Power high Opamp bias high buffer setting is not allowed for 2 7 V Vpp Power low Opamp bias low 150 200 uA operation Power low Opamp bias high 300 400 uA Power medium Opamp bias low 600 800 uA Power medium Opamp bias high 1200 1600 uA Power high Opamp bias low 2400 3200 uA Power high Opamp bias high uA PSRRoA Supply voltage rejection ratio 64 80 dB Vss lt ME pp 2 or DC Low Power Comparator Specifications Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ty lt 85 C 3 0 V to 3 6 V and 40 C x Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V at 25 C and are for design guidance only Table 17 DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes Vperipc Low power comparator LPC reference voltage 0 2 Vpp 1 V range IsLpc LPC supply current 10 40 HA Vos pc LPC voltage offset 2 5 30 mV Document Number 38 12028 Rev V Page 23 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM DC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage
40. setan buatan laa 3 Analog System senam bana yak aka 4 Additional System Resources sese 5 PSoC Device Characteristics sssessse 5 Getting Started oooooooomoommmnn 6 Application Notes sess 6 Development Kits i iii ooooooooWoWo Woo oom 6 Tralning ERE 6 CYPros Consultants oooo WoWoWooo oo 6 Solutions Library ai rte 6 Technical Support ooooocooWoWo WoWoWoWoWom oo 6 Development Tools oooooo ooo oo momen 7 PSoC Designer Software Subsystems 7 Designing with PSoC Designer oooo om 8 Select User Modules Woo 8 Configure User Modules ooWoWooWooo 8 Organize and Connect 8 Generate Verify and Debug oooooooWooo 8 PINOUutS ea aa an akan 9 8 Pin Part Pinout WoooooooWoo Woman 9 20 Pin Part Pinout oooooooWooWoW Wana 10 28 Pin Part Pinout oooooooooooWoWo Waah 11 32 Pin Part Pinout ooooooooWooWo Woman 12 56 Pin Part Pinout ooooocoooWoWoWo Wook 13 Register Reference sese 14 Register Conventions sse 14 Register Mapping Tables sees 14 Electrical Specifications eee 17 Absolute Maximum Ratings ooooo 17 Operating Temperature i o oooWoWooo 18 DC Electrical Characteristics
41. the constraints of a fixed peripheral controller Digital blocks are provided in rows of four where the number of blocks varies by PSoC device family This gives a choice of system resources for your application Family resources are shown in Table 1 on page 6 1 Errata When the device is operated within 0 C to 70 C the frequency tolerance is reduced to 2 5 but if operated at extreme temperature below 0 C or above 70 C frequency tolerance deviates from 2 5 to 5 For more information see Errata on page 67 Document Number 38 12028 Rev V Page 4 of 71 CY8C24123A E CY8C24223A CYPRESS CY8C24423A PERFORM Analog System Figure 3 Analog System Block Diagram The analog system consists of six configurable blocks each PO 7 4 PO S consisting of an opamp circuit that allows the creation of complex analog signal flows Analog peripherals are very flexible and can POS a Pola be customized to support specific application requirements Some of the more common PSoC analog functions most Pog e Pol available as user modules are Po 1 r Popo m ADCs up to two with 6 to 14 bit resolution selectable as 5 d pole incremental delta sigma and SAR i 5 m Filters two and four pole band pass low pass and notch m Amplifiers up to two with selectable gain to 48x m Instrumentation amplifiers one with selectable gain to 93x m Comparators up to two
42. trop Rising settling time to 0 1 1 V Step 100 pF load Power low 4 us Power high 4 us tsop Falling settling time to 0 196 1 V Step 100 pF load Power 7 low 3 us Power high 3 us SRrop Rising slew rate 20 to 80 1 V Step 100 pF load Power low 0 4 V us Power high 0 4 V us SRrog Falling slew rate 80 to 20 1 V Step 100 pF load Power low 0 4 V us Power high 0 4 V us BWog Small signal bandwidth 20 MV pp 3dB BW 100 pF load Power low 0 6 MHz Power high 0 6 MHz BWog Large signal bandwidth 1 Vpp 3dB BW 100 pF load Power low 180 kHz Power high 180 kHz AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 42 5 V AC External Clock Specifications Symbol Description Min Typ Max Units Foscext Freguency 0 093 24 6 MHz High period 20 6 5300 ns flopissa T 206 PPT m Power up IMO to switch 150 us Table 43 3 3 V AC External Clock Specifications Symbol
43. 08 0008 0 0135 i 51 85062 F Document Number 38 12028 Rev V Page 56 of 71 CY8C24123A E ies CY8C24223A CYPRESS CY8C24423A PERFORM Thermal Impedances Capacitance on Crystal Pins Table 48 Thermal Impedances per Package Table 49 Typical Package Capacitance on Crystal Pins Package Typical 0 mies Package Package Capacitance 8 pin PDIP 123 C W 8 pin PDIP 2 8 pF 8 pin SOIC 185 C W 8 pin SOIC 2 0 pF 20 pin PDIP 109 C W 20 pin PDIP 3 0 pF 20 pin SSOP 117 C W 20 pin SSOP 2 6 pF 20 pin SOIC 81 C W 20 pin SOIC 2 5 pF 28 pin PDIP 69 C W 28 pin PDIP 3 5 pF 28 pin SSOP 101 C W 28 pin SSOP 2 8 pF 28 pin SOIC 74 C W 28 pin SOIC 2 7 pF 32 pin QFNIS9I 22 C W 32 pin QFN 2 0 pF Solder Reflow Specifications Table 50 shows the solder reflow temperature limits that must not be exceeded Table 50 Solder Reflow Specifications Maximum Peak Maximum Time package Temperature Tc above Tc 5 C 8 pin PDIP 260 C 30 seconds 8 pin SOIC 260 C 30 seconds 20 pin PDIP 260 C 30 seconds 20 pin SSOP 260 C 30 seconds 20 pin SOIC 260 C 30 seconds 28 pin PDIP 260 C 30 seconds 28 pin SSOP 260 C 30 seconds 28 pin SOIC 260 C 30 seconds 32 pin QFN 260 C 30 seconds Notes 38 T TA Power x Oj 39 To achieve the thermal impedance specified for the QFN package refer to Application Note
44. 2 0 040 Vpp 2 0 001 Vpp 2 0 039 V VREFLO Ref Low Vss Vss Vss 0 005 Vss 0 020 V RefPower high VREFHI Ref High Vpp Vpp 0 082 Vpp 0 002 Vbp V Opamp bias low VAGND AGND Vpp 2 Vpp 2 0 031 Vpp 2 Vpp 2 0 028 V VREFLO Ref Low Vss Vss Vss 0 003 Vss 0 015 V RefPower medium VREFHI Ref High Vpp Vpp 0 083 Vpp 0 002 Vbp V Opamp bias high xr AGND Vag Vpp 2 0 032 Vpp 2 0 001 Vpp 2 0 029 V VREFLO Ref Low Vss Vss Vss 0 002 Vss 0 014 V RefPower medium VREFHI Ref High Vpp Vpp 0 081 Vpp 0 002 Vpp V Opamp bias low VAGND AGND Vpp 2 Vpp 2 0 033 Vpp 2 0 001 Vpp 2 0 029 V VREFLO Ref Low Vss Vss Vss 0 002 Vss 0 013 V 0b011 All power settings Not allowed at 3 3 V Document Number 38 12028 Rev V Page 31 of 71 CY8C24123A 7 CYPRESS CY8C24423A PERFORM Table 23 3 3 V DC Analog Reference Specifications continued Reference Reference Power ARF_CR 7 Symbol Reference Description Min Typ Max Units Settings 5 3 0b100 All power settings Not allowed at 3 3 V 0b101 RefPower high VREFHI Ref High P2 4 Bandgap P2 4 1 211 P2 4 1 285 P2 4 1 348 V Opamp bias high P2 4 Vpp 2 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 Bandgap P2 4 1 354 P2 4 1 290
45. 2 7 5 mV TCVosoA Average input offset voltage drift 7 0 35 0 uV C IEBOA Input leakage current port 0 analog pins 20 pA Gross tested to 1 yA Cinoa Input capacitance port 0 analog pins 4 5 9 5 pF Package and pin dependent Temp 25 C Vcmoa Common mode voltage range 0 0 DD V The common mode input voltage Common mode voltage range high power or high 0 5 Vpp 0 5 range is measured through an Opamp bias analog output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer GoLoA Open loop gain Specification is applicable at high Power low Opamp bias high 60 dB Opamp bias For low Opamp bias Power medium Opamp bias high 60 dB mode minimum is 60 dB Power high Opamp bias high 80 dB VouicuoA High output voltage swing internal signals Power low Opamp bias high Vpp 0 2 V Power medium Opamp bias high Vpp 0 2 V Power high Opamp bias high Vpp 0 5 V Votowoa Low output voltage swing internal signals Power low Opamp bias high 0 2 Power medium Opamp bias high 0 2 V Power high Opamp bias high 0 5 Ison Supply current including associated AGND buffer Power low Opamp bias low 150 200 yA Power low Opamp bias high 300 400 yA Power medium Opamp bias low 600 800 yA Power medium Opamp bias high 1200 1600 yA Power high Opamp bias
46. 22 V 0b001 RefPower high Vreen RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias high Vpp 2 P2 6 0 5 V 0 072 0 017 0 041 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 029 0 010 0 048 RefPower high Vrerui RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias low Vpp 2 P2 6 0 5 V 0 066 0 010 0 043 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 024 0 004 0 034 RefPower medium Veer RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias high Vpp 2 P2 6 0 5 V 0 073 0 007 0 053 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 028 0 002 0 033 RefPower medium Verry RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias low Vpp 2 P2 6 0 5 V 0 073 0 006 0 056 VAGND AGND P2 4 P2 4 P2 4 P2 4 VREFLO Ref Low P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 0 5 V 0 030 0 032 0b010 RefPower high VREFHI Ref High Vpp Vpp 0 102 Vpp 0 003 Vbp V Opamp bias high VAGND AGND Vpp 2 Vpp
47. 25 V 0b001 RefPower high Vrerw RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias high Vpp 2 P2 6 1 3 V 0 076 0 021 0 041 Vacnn AGND P2 4 P214J P2 4 P2 4 VrerLo Reflow P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 1 3 V 0 025 0 011 0 085 RefPower high Vrerw RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias 7 low Vpp 2 P2 6 1 3 V 0 069 0 014 0 043 Vacnn AGND P2 4 P214J P2 4 P2 4 VrerLo Reflow P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 1 3 V 0 029 0 005 0 052 RefPower medium Vgggu RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias high Vpp 2 P2 6 1 3 V 0 072 0 011 0 048 Vacnn AGND P2 4 P214J P2 4 P2 4 VrerLo RefLow P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 1 3 V 0 031 0 002 0 057 RefPower medium Vgggu RefHigh P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Opamp bias 7 low Vpp 2 P2 6 1 3 V 0 070 0 009 0 047 Vacnn AGND P2 4 P2 4 P2 4 P2 4 VrerLo Reflow P2 4 P2 6 P2 4 P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V Vpp 2 P2 6 1 3 V 0 033 0 001 0 039 Document Number 38 12028 Rev V Page 28 of 71 CY8C24123A
48. 3 V AC GPIO Specifications Symbol Description Min Typ Max Units Notes Fcpio GPIO operating freguency 0 12 MHz Normal Strong Mode tRiseF Rise time normal strong mode Cload 50 pF 3 18 ns Vpp 4 5 to 5 25 V 10 to 90 tFallF Fall time normal strong mode Cload 50 pF 2 18 ns Vpp 4 5 to 5 25 V 10 to 90 tRiseS Rise time slow strong mode Cload 50 pF 10 27 ns Vpp 3 to 5 25 V 10 to 90 tFallS Fall time slow strong mode Cload 50 pF 10 22 ns Vpp 3 to 5 25 V 10 to 90 Table 32 2 7 V AC GPIO Specifications Symbol Description Min Typ Max Units Notes Fepio GPIO operating frequency 0 3 MHz Normal strong mode tRiseF Rise time normal strong mode Cload 50 pF 6 50 ns Vpp 2 4 to 3 0 V 10 to 90 tFallF Fall time normal strong mode Cload 50 pF 6 50 ns Vpp 2 4 to 3 0 V 10 to 90 tRiseS Rise time slow strong mode Cload 50 pF 18 40 120 ns Vpp 2 4 to 3 0 V 10 to 90 tFallS Fall time slow strong mode Cload 50 pF 18 40 120 ns Vpp 2 4 to 3 0 V 10 to 90 Figure 0 1 GPIO Timing Diagram 9096 I GPIO Pin Output Voltage 10 MEN re ene nb aan ea 1 i TRiseF TFallF TRiseS TFallS Document Number 38 12028 Rev V Page 41 of 71 CY8C24123A fe CY8C24223A CYPRESS CY8C24423A PERFORM AC Operational Amplifier Specifications The following tables list th
49. 397 spec 001 14503 spec related information Added Errata Document Number 38 12028 Rev V Page 69 of 71 CYPRESS PERFO RM Document History Page continued CY8C24123A CY8C24223A CY8C24423A Document Title CY8C24123A CY8C24223A CY8C24423A PSoC Programmable System on Chip Document Number 38 12028 Revision ECN Orig of Change Submission Date Description of Change T 4066332 PMAD 07 17 2013 Added Errata Footnotes Note 1 19 Updated PSoC Functional Overview Updated PSoC Core Added Note 1 and referred the same note in 4th paragraph in PSoC Core Added Note 19 and referred the same note in Fiyo24 parameter Updated Electrical Specifications Updated AC Electrical Characteristics Updated AC Chip Level Specifications Updated minimum and maximum values of F yjo24 parameter Updated AC Digital Block Specifications Replaced all instances of maximum value 49 2 with 50 4 and 24 6 with 25 2 in Table 37 Updated in new template U 4479672 RJVB 08 20 2014 Updated Packaging Information Updated Packaging Dimensions spec 51 85011 Changed revision from C to D spec 51 85024 Changed revision from E to F spec 51 85026 Changed revision from G to H Updated Errata Updated CY8C24123A Errata Summary Updated details in Fix Status column in the table Updated details in Fix Status bulleted point below the
50. 4K 256 No 40 C to 85 C 4 6 6 4 2 No 8 pin 150 mil SOIC E 4K 256 No 40 C to 85 C 4 6 6 4 2 No Tape and Reel CY8C24123A 24SXIT 20 pin 300 mil DIP CY8C24223A 24PXI 4K 256 Yes 40 C to 85 C 4 6 16 8 2 Yes 20 pin 210 mil SSOP CY8C24223A 24PVXI 4K 256 Yes 40 C to 85 C 4 6 16 8 2 Yes 20 pin 210 mil SSOP 4K 256 Yes 40 C to 85 C 4 6 16 8 2 Yes Tape and Reel CY8C24223A 24PVXIT 20 pin 300 mil SOIC CY8C24223A 24SXI 4K 256 Yes 40 C to 85 C 4 6 16 8 2 Yes 20 pin 300 mil SOIC 4K 256 Yes 40 C to 85 C 4 6 16 8 2 Yes Tape and Reel CY8C24223A 24SXIT 28 pin 300 mil DIP CY8C24423A 24PXI 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes 28 pin 210 mil SSO CY8C24423A 24PVXI 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes 28 pin 210 mil g 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes Tape and Reel CY8C24423A 24PVXIT 28 pin 300 mil SOIC CY8C24423A 24SXI 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes 28 pin 300 mil SOIC 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes Tape and Reel CY8C24423A 24SXIT 32 pin 5 x 5 mm 1 00 max z 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes Sawn QFN CY8C24423A 24LTXI 32 pin 5 x 5 mm 1 00 max 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes Sawn GEN Tape and Reel CY8C24423A 24LTXIT 56 pin OCD SSOP CY8C24000A 24PVXI 3 4K 256 Yes 40 C to 85 C 4 6 24 10 2 Yes
51. 5 CY8C24223A 20 Pin PSoC Device No Digital T Name meer noes i 1 lO I PO 7 Analog column mux input A 1 PO 4 20 P Voo 2 I O VO PO B5 Analog column mux input and column output iis i k L i 3 I O I O PO 3 Analog column mux input and column output A I PO a PDIP 47 E Pore A 4 I O PO 1 Analog column mux input SMP B m 16 PO 0 A I 5 Power SMP SMP connection to external components 20 SCL PIT me 5 XRES required I2C SDA P4 5 7 44 m P1 6 6 O P1 TC SCL I2C SCL XTALin B i C B 2 ded 7 I O P1 5 1 C SDA Ves mi 11 e Pl XTALout 8 I O P1 3 9 I O P1 1 XTALin IC SCL ISSP SCLKBI 10 Power Vss Ground connection 11 I O P1 0 XTALout I2C SDA ISSP SDATABI 12 I O P1 2 13 I O P1 4 Optional external clock input EXTCLK 14 I O P1 6 15 Input XRES Active high external reset with internal pull down 16 I O PO 0 Analog column mux input 17 I O PO 2 Analog column mux input 18 I O PO 4 Analog column mux input 19 I O PO 6 Analog column mux input 20 Power Vpp Supply voltage LEGEND A Analog Input and O Output Note 5 These are the ISSP pins which are not high Z at POR See the PSoC Technical Reference Manual for details Document Number 38 12028 Rev V Page 11 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM 28 Pin Part Pinout Table 4 28 Pin PDIP SSOP and SOIC
52. 5 Vpp 02 V Power high 05 Vpp 02 V Votowog Low output voltage swing Load 1 K ohms to Vpp 2 Power low 0 5 x Vpp 0 7 V Power high 0 5xVpp 0 7 V IsoB Supply current including Opamp bias cell No Load 0 8 2 0 mA Power low 2 0 43 mA Power high PSRRog Supply voltage rejection ratio 52 64 dB Vout gt Vpp 1 25 Document Number 38 12028 Rev V Page 25 of 71 PERFORM DC Switch Mode Pump Specifications Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ty lt 85 C 3 0 V to 3 6 V and 40 C x Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 21 DC Switch Mode Pump SMP Specifications CY8C24123A CY8C24223A CY8C24423A Symbol Description Min Typ Max Units Notes Vpump5 V 5 V output voltage from pump 4 75 5 0 5 25 V Configuration listed in footnote Average neglecting ripple SMP trip voltage is set to 5 0 V Vpump3V 3 3 V output voltage from pump 3 00 3 25 3 60 V Configuration listed in footnote 11 Average neglecting ripple SMP trip voltage is set to 3 25 V Vpump2V 2 6 V output voltage from pump 2 45 2 55 2 80 V Configuration listed in footnote 1 Average neglecting ri
53. 8 Rev V Page 68 of 71 PERFORM Document History Page continued CY8C24123A CY8C24223A CY8C24423A Document Title CY8C24123A CY8C24223A CY8C24423A PSoC Programmable System on Chip Document Number 38 12028 Revision ECN Orig of Change Submission Date Description of Change L 2897881 MAXK NJF 03 23 2010 Add More Information on page 2 Update unit in Table 10 28 and Table 38 of SPIS Maximum Input Clock Frequency from ns to MHz Update revision of package diagrams for 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 QFN Updated Cypress website links Removed reference to PSoC Designer 4 4 Updated 56 Pin SSOP definitions and diagram Added TBAKETEMP and TgAkeriME Parameters in Absolute Maximum Ratings Updated 5 V DC Analog Reference Specifications table Updated Note in Packaging Information Added Note 29 Updated Solder Reflow Specifications table Removed Third Party Tools and Build a PSoC Emulator into your Board Removed inactive parts from Ordering Information Update trademark info and Sales Solutions and Legal Information M 2942375 VMAD 06 02 2010 Updated content to match current style guide and datasheet template No technical updates O 3032514 3098766 NJF YJI 09 17 10 12 01 2010 Added PSoC Device Characteristics table Added DC I C Specifications table Added Faok y max limit Added Tjit IMO specif
54. A 24PVXI CY8C24423A 24PVXIT CY8C24423A 24SXI CY8C24423A 24SXIT CY8C24423A 24LFXI CY8C24423A 24LTXI CY8C24423A 24LTXIT CY8C24000A 24PVXI CY8C24123A Qualification Status Product Status Production CY8C24123A Errata Summary The following table defines the errata applicability to available CY8C24123A family devices Items Part Number Silicon Revision Fix Status 1 Internal Main Oscillator IMO Tolerance Deviation at CY8C24123A A No silicon fix planned Temperature Extremes Workaround is reguired 1 Internal Main Oscillator IMO Tolerance Deviation at Temperature Extremes m Problem Definition Asynchronous Digital Communications Interfaces may fail framing beyond 0 to 70 C This problem does not affect end product usage between 0 and 70 C m Parameters Affected The IMO frequency tolerance The worst case deviation when operated below 0 C and above 70 C and within the upper and lower datasheet temperature range is 5 m Trigger Condition S The asynchronous Rx Tx clock source IMO frequency tolerance may deviate beyond the data sheet limit of 2 5 when operated beyond the temperature range of Oto 70 C m Scope of Impact This problem may affect UART IrDA and FSK implementations m Workaround Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface m Fix Status Silicon fix is not planned
55. C lt T4 lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 45 AC Programming Specifications Symbol Description Min Typ Max Units Notes tRscLK Rise time of SCLK 1 20 ns trscik Fall time of SCLK 1 20 ns tsscLk Data setup time to falling edge of SCLK 40 ns tuscLk Data hold time from falling edge of SCLK 40 ns Fscuk Frequency of SCLK 0 8 MHz tERASEB Flash erase time block 20 ms twRITE Flash block write time 80 ms tbscLK Data out delay from falling edge of SCLK 45 ns Vpp 3 6 tbscLk3 Data out delay from falling edge of SCLK 50 ns 3 0 lt Vpp lt 3 6 tbscLk2 Data out delay from falling edge of SCLK 70 ns 2 4 lt Vpp lt 3 0 tERASEALL Flash erase time Bulk 20 ms Erase all blocks and protection fields at once tPRocRAM Hor Flash block erase flash block write time 2008 ms o C lt Tj lt 100 C tpRocRam COLD Flash block erase flash block write time 4008 ms 40 C lt Tj lt 0 Notes 34 Maximum CPU frequency is 12 MHz at 3 3 V With the CPU clock divider set to 1 the external clock must adhere to the maximum frequency and duty cycle requirements 35 If the frequency of the external clock is greater than 12 MHz the CPU clock divider must b
56. CY8C24123A CY8C24223A A M 07 CYPRESS CY8C24423A EET WONSS PSoC Programmable System on Chip Features m New CY8C24x23A PSoC device a Derived from the CY8C24x23 device m Powerful Harvard architecture processor a Low power and low voltage 2 4 V an M8C processor speeds up to 24 MHz a8 x 8 multiply 32 bit accumulate a Low power at high speed m Additional system resources a I2C slave master and multi master to 400 kHz da Operating voltage 2 4 V to 5 25 V d Watchdog and sleep timers 5 Operating voltages down to 1 0 V using on chip switch mode z User c ntigurable low voltage detection tty pump SMP 9 Integrated supervisory circuit a Industrial temperature range 40 C to 85 C a On chip precision voltage reference m Advanced peripherals PSoC blocks e 3 Six rail to rail analog PSoC blocks provide Up to 14 bit analog to digital converters ADCs Up to 9 bit digital to analog converters DACs Programmable gain amplifiers PGAs Programmable filters and comparators a Four digital PSoC blocks provide 8 to 32 bit timers and counters 8 and 16 bit pulse width Logic Block Diagram modulators PWMs Port 2HPort 1 PSoC CORE i Cyclical redundancy check CRC and pseudo random PSTN Complete development tools a Free development software PSoC Designer a Full featured in circuit emulator ICE and programmer a Full speed emulation a Complex breakpoint structure a 128 KB trace memory
57. Document Number 38 12028 Rev V Page 61 of 71 CY8C24123A CY8C24223A CY8C24423A PERFORM Document Conventions Units of Measure Table 54 lists the unit sof measures Table 54 Units of Measure Symbol Unit of Measure Symbol Unit of Measure kB 1024 bytes us microsecond dB decibels ms millisecond C degree Celsius ns nanosecond fF femto farad ps picosecond pF picofarad uV microvolts kHz kilohertz mV millivolts MHz megahertz mVpp millivolts peak to peak rt Hz root hertz nV nanovolts kQ kilohm V volts Q ohm uW microwatts yA microampere W watt mA milliampere mm millimeter nA nanoampere ppm parts per million pA pikoampere percent mH millihenry Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h for example 14h or 3Ah Hexadecimal numbers may also be represented by a Ox prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not indicated by an h or b are decimals Glossary active high analog blocks analog to digital ADC API Application Programming Interface asynchronous Bandgap reference bandwidth Document Number 38 12028 Rev V 10 A logic signal having its asserted state as the logic 1 state 11 A logic signal having the logic 1 state as the higher voltage of
58. Hz VC3 93 75 kHz analog power off SLIMO mode 0 IMO 24 MHz Ipp3 Supply current 3 3 6 0 mA Conditions are Vpp 3 3 V Ta 25 C CPU 3 MHz SYSCLK doubler disabled VC1 1 5 MHz VC2 93 75 kHz VC3 93 75 kHz analog power off SLIMO mode 0 IMO 24 MHz Ipp27 Supply current 2 4 mA Conditions are Vpp 2 7 V Tp 25 C CPU 0 75 MHz SYSCLK doubler disabled VC1 0 375 MHz VC2 23 44 kHz VC3 0 09 kHz analog power off SLIMO mode 1 IMO 6 MHz Isp Sleep mode current with POR LVD sleep timer 3 6 5 pA Conditions are with internal slow speed and WDT 10 oscillator Vpp 3 3 V 40 C lt Ta lt 55 C analog power off IsBH Sleep mode current with POR LVD sleep timer 4 25 HA Conditions are with internal slow speed and WDT at high temperature 9 oscillator Vpp 3 3 V 55 C lt Ty lt 85 C analog power off ISBxTL Sleep mode current with FSR LVD sleep timer 4 7 5 HA Conditions are with properly loaded WDT and external crystal 1 uW max 32 768 kHz crystal Vpp 3 3 V 40 C lt TA lt 55 C analog power off lsgxr H Sleep Mode current with POR LVD sleep timer 5 26 pA Conditions are with properly loaded WDT and external crystal at high temperature 1 1uW max 32 768 kHz crystal Vpp 3 3 V 55 C lt Ty 85 C analog power off VREF Reference voltage Bandgap 1 28 1 30 1 32 V Trimmed for ap
59. Low Vss Vss Vss 0 003 Vss 0 013 V Document Number 38 12028 Rev V Page 30 of 71 CY8C24123A SP CYPRESS CY8C24423A PERFORM Table 23 3 3 V DC Analog Reference Specifications kereronce Reference Power ARF_CR Symbol Reference Description Min Typ Max Units 5 3 Settings 0b000 RefPower high Vrerui RefHigh Vpp 2 Bandgap Vpp 2 1 170 Vpp 2 1 288 Vpp 2 1 376 V Opamp bias high x an AGND Vpp 2 Vpp 2 0 098 Vpp 2 0 003 Vpp 2 0 097 V VREFLO Ref Low Vpp 2 m Bandgap Vpp 2 1 386 Vpp 2 1 287 Vpp 2 1 169 V RefPower high Vngrui RefHigh Vpp 2 Bandgap Vpp 2 1 210 Vpp 2 1 290 Vpp 2 1 355 V Opampiblas low Fyen AGND Vpp 2 Vpp 2 0 055 Vpp 2 0 001 Vpp 2 0 054 V VREFLO Ref Low Vpp 2 Bandgap Vpp 2 1 359 Vpp 2 1 292 Vpp 2 1 214 V RefPower medium Vggrui Ref High Vpp 2 Bandgap Vpp 2 1 198 Vpp 2 1 292 Vpp 2 1 368 V Opamp bias high VAGND AGND Vpp 2 Vpp 2 0 041 Vpp 2 Vpp 2 0 04 V VREFLO Ref Low Vpp 2 Bandgap Vpp 2 1 362 Vpp 2 1 295 Vpp 2 1 220 V RefPower medium Vreft Ref High Vpp 2 Bandgap Vpp 2 1 202 Vpp 2 1 292 Vpp 2 1 364 V Opamp bias ow ros CD AGND VE Vpp 2 0 033 Vpp 2 Vpp 2 0 080 V VREFLO Ref Low Vpp 2 Bandgap Vpp 2 1 364 Vpp 2 1 297 Vpp 2 1 2
60. O PO 2 Analog column mux input 26 I O PO 4 Analog column mux input 27 I O PO 6 Analog column mux input 28 Power Vpp Supply voltage LEGEND A Analog Input and O Output Note 6 These are the ISSP pins which are not high Z at POR See the PSoC Technical Reference Manual for details Document Number 38 12028 Rev V Page 12 of 71 CY8C24123A a CY8C24223A CYPRESS CY8C24423A PERFORM 32 Pin Part Pinout Table 5 32 Pin QFN Pin No Type Pin Description Figure 7 CY8C24423A 32 Pin PSoC Device Digital Analog Name 65 1 I O P2 7 4x44 lt lt z 10 P2 PERE oF Fy 3 I O P2 3 Direct switched capacitor block input 4 I O P2 1 Direct switched capacitor block input P2 7 lea 1 PO 2 A I 5 Power Vss Ground connection P2ISI fm 2 PO O A I 6 Power SMP SMP connection to external components A P2IS E Pale External VRef reguired A l ien e GEN be E AGND 7 UO Pi PC SCL BE aS 8 I O P1 5 1 C SDA 12C SCL P4 7 f r 7 XRES 9 NC No connection Pin must be left floating 2C SDA P1 5 fa 8 P1I 6 10 VO P1 3 11 I O P1 1 XTALin I2C SCL ISSP SCLKBI QREESENEY 12 Power Vss Ground Connection 5 P 5 2 13 I O P1 0 XTALout I2C SDA ISSP SDATAl 2 2 14 I O P1 2 3 i 15 I O P1 4 Optional EXTCLK g 2 16 NC No connection Pin must be left floating i 17 I O P1 6 18 Inp
61. PO O Al P P2 6 External VRef E P2 4 External AGND ka P2 2 Al fa P2 0 Al NC NC NC FNC la CCLK BHCLK P XRES NC NC PNC NC NC NC ka P1 6 m P1 4 EXTCLK P P1 2 P P1 0 XTALOut I2C SDA SDATA NC a NC Page 14 of 71 CYPRESS PERFORM Register Reference This section lists the registers of the CY8C24x23A PSoC device For detailed register information see the PSoC Programmable Sytem on Chip Reference Manual Register Conventions Abbreviations Used The register conventions specific to this section are listed in the following table Table 7 Abbreviations Convention Description Read register or bit s Write register or bit s Logical register or bit s Clearable register or bit s oO e s a Access is bit specific Document Number 38 12028 Rev V CY8C24123A CY8C24223A CY8C24423A Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is referred to as I O space and is divided into two banks Bank 0 and Bank 1 The XOI bit in the Flag register CPU_F determines which bank the user is currently in When the XOI bit is set the user is in Bank 1 Note In the following register mapping tables blank fields are reserved and must not be accessed Page 15 of 71 EM CY8C24123A FP CY8C24223A 7 CYPRESS CY8C24423A PERFORM Table 8 Register Map Ban
62. SOIC CY8C24123A CY8C24223A CY8C24423A 1 DIMENSIONS IN INCHES MM MIN MAX 2 PIN 1 IDIS OPTIONAL ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME PIN 1 ID 5 3 REFERENCE JEDEC MS 012 4 PACKAGE WEIGHT 0 07gms Jt PART 808 15 STANDARD PKG SZ08 15 LEAD FREE PKG 0 150 3 810 SW8 15 LEAD FREE PKG 0 157 3 987 025015842 0 244 6 197 Y 5 Tn SEATING PLANE 7 PA soia 14 0 061 1 549 0 068 1 727 f NG XI 0 004 0 102 erem oe Aa l ge uns 1 TER 0 0075 0 190 PE TE 0 0098 0 249 0 035 0 889 0 0098 0 249 er 51 8506 G Figure 19 20 Pin 300 Mil Molded DIP 10 1 ph dh dh dh dh Jh fh dh dh gh DIMENSIONS IN INCHES MIN MAX C 0 250 0 270 T T T T Er J I U C T hy J I U I ir hy I J 11 20 0 030 TP 0070 0 970 1 040 SEATING PLANE L 0280 0 325 0 140 0 120 Y 0190 0140 L 0 115 0 009 k 0 160 0 015 0 012 Al U JU UU 0 060 0 090 J L 0 055 _ 0 015 0 310 0 110 0 065 0 020 0 385 51 85011 D Document Number 38 12028 Rev V Page 52 of 71 mE CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM Figure 20
63. Sales Solutions and Legal Information 70 Worldwide Sales and Design Support 70 PROGQUCUS E ana 70 PSOC Solutions hunt kan aka alan 70 Cypress Developer Community ooooWoo 70 Technical Support oooooooooWo oom 70 Page 3 of 71 PERFORM PSoC Functional Overview The PSoC family consists of many programmable system on chips with on chip controller devices These devices are designed to replace multiple traditional MCU based system components with a low cost single chip programmable device PSoC devices include configurable blocks of analog and digital logic and programmable interconnects This architecture makes it possible for you to create customized peripheral configurations that match the requirements of each individual application Additionally a fast CPU flash program memory SRAM data memory and configurable I O are included in a range of convenient pinouts and packages The PSoC architecture shown in Figure 2 consists of four main areas PSoC core digital system analog system and system resources Configurable global busing allows combining all the device resources into a complete custom system The PSoC CY8C24x23A family can have up to three I O ports that connect to the global digital and analog interconnects providing access to four digital blocks and six analog blocks PSoC Core The PSoC core is a powerful engine that supports a rich f
64. a streams 2 The abrupt and unwanted variations of one or more signal characteristics such as the interval between successive pulses the amplitude of successive cycles or the frequency or phase of successive cycles low voltage detect A circuit that senses Vpp and provides an interrupt to the system when Vpp falls lower than a selected threshold LVD M8C An 8 bit Harvard architecture microprocessor The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash SRAM and register space master device A device that controls the timing for data exchanges between two devices Or when devices are cascaded in width the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface The controlled device is called the slave device Document Number 38 12028 Rev V Page 64 of 71 PERFORM CY8C24123A CY8C24223A CY8C24423A Glossary continued microcontroller mixed signal modulator noise oscillator parity phase locked loop PLL pinouts port power on reset POR PSoC9 PSoC Designer pulse width modulator PWM RAM register reset ROM serial settling time Document Number 38 12028 Rev V An integrated circuit chip that is designed primarily for control systems and products In addition to a CPU a microcontroller typically includes memory timing circuits and IO circuitry The reason for this is t
65. ad Power low 0 65 V us Power high 0 65 V us SRrog Falling slew rate 80 to 20 1 V Step 100 pF load Power low 0 65 V us Power high 0 65 V us BWog Small signal bandwidth 20mVpp 3dB BW 100 pF load Power low 0 8 MHz Power high 0 8 MHz BWop Large signal bandwidth 1Vpps 3dB BW 100 pF load Power low 300 kHz Power high 300 kHz Table 40 3 3 V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units trop Rising settling time to 0 1 1 V Step 100 pF load Power low 3 8 us Power high 3 8 us tsop Falling settling time to 0 196 1 V Step 100 pF load Power low 2 6 us Power high 2 6 us SRrop Rising slew rate 20 to 80 1 V Step 100 pF load Power low 0 5 V us Power high 0 5 V us SRrog Falling slew rate 80 to 20 1 V Step 100 pF load Power low 0 5 V us Power high 0 5 V us BWog Small signal bandwidth 20mVpp 3dB BW 100 pF load Power low 0 7 MHz Power high 0 7 MHz BWog Large signal bandwidth 1V p 3dB BW 100 pF load Power low 200 kHz Power high 200 kHz Document Number 38 12028 Rev V Page 47 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM Table 41 2 7 V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units
66. and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 18 5 V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes C Load Capacitance 200 pF This specification applies to the external circuit that is being driven by the analog output buffer VosoB Input offset voltage absolute value 3 12 mV TCVosog Average input offset voltage drift 6 uV c VcMoB Common mode input voltage range 0 5 Vpp 1 0 V Rouros Output resistance Power low 1 W Power high 1 W VouicHop High output voltage swing Load 32 ohms to Vpp 2 Power low 0 5 x Vpp 1 1 V Power high 0 5 x Vpp 1 1 V VoLowog Low output voltage swing Load 32 ohms to Vpp 2 Power low 5 x Vpp 1 3 V Power high 10 5 x Vpp 1 3 V IsoB Supply current including Opamp bias cell No Load 1 1 5 1 mA Power low 2 6 8 8 mA Power high PSRRog Supply voltage rejection ratio 52 64 dB Vout gt Vpp 1 25 Table 19 3 3 V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes C Load Capacitance 200 pF This specification applies to the ext
67. atures a development board for the CY8C24794 24LFXI PSoC device Special features of the board include both USB and capacitive sensing development and debugging support This evaluation board also includes an LCD module potentiometer LEDs an enunciator and plenty of bread boarding space to meet all of your evaluation needs The kit includes m PSoCEvalUSB board m LCD module m MiniProg programming unit m Mini USB cable m PSoC Designer and Example Projects CD m Getting Started guide m Wire pack Page 58 of 71 PERFORM Device Programmers All device programmers can be purchased from the Cypress Online Store CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit The modular programmer includes three programming module cards and supports multiple Cypress products The kit includes m Modular programmer base m Three programming module cards m MiniProg programming unit m PSoC Designer software CD m Getting Started guide m USB 2 0 cable Accessories Emulation and Programming Table 51 Emulation and Programming Accessories CY8C24123A CY8C24223A CY8C24423A CY3207ISSP In System Serial Programmer ISSP The CY3207ISSP is a production programmer It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment Note CY3207ISSP needs special software and is not compatible w
68. e Each pin s drive mode may be selected from eight options allowing great flexibility in external interfacing Every pin can generate a system interrupt on high level low level and change from last read Note CY8C24123A CY8C24223A CY8C24423A Digital System The digital system consists of four digital PSoC blocks Each block is an 8 bit resource that may be used alone or combined with other blocks to form 8 16 24 and 32 bit peripherals which are called user module references Figure 2 Digital System Block Diagram To System Bus To Analog System Digital Clocks From Core DIGITAL SYSTEM Digital PSoC Block Array Row 0 4 Y y Y Y DBB00 DBB01 DCBO2 DCBOS uoneJnByuo2 jndino Moy GIE 7 0 E coo GIO 7 0 Interconnect foes GOO 7 0 Digital peripheral configurations are m PWMs 8 and 16 bit m PWMs with dead band 8 and 16 bit m Counters 8 to 32 bit m Timers 8 to 32 bit m UART 8 bit with selectable parity m SPI master and slave m C slave and multi master one is available as a system resource m CRC generator 8 to 32 bit m IrDA m PRS generators 8 to 32 bit The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin The buses also allow for signal multiplexing and performing logic operations This configurability frees your designs from
69. e guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Settling times slew rates and gain bandwidth are based on the analog continuous time PSoC block Power high and Opamp bias high is not supported at 3 3 V and 2 7 V Table 33 5 V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units troa Rising settling time from 80 of AV to 0 1 of AV 10 pF load unity gain Power low Opamp bias low 3 9 us Power medium Opamp bias high 0 72 us Power high Opamp bias high 0 62 us tsoa Falling settling time from 20 of AV to 0 1 of AV 10 pF load unity gain Power low Opamp bias low 5 9 us Power medium Opamp bias high 0 92 us Power high Opamp bias high 0 72 us SRroa Rising slew rate 20 to 80 10 pF load unity gain Power low Opamp bias low 0 15 V us Power medium Opamp bias high 1 7 V us Power high Opamp bias high 6 5 V us SRroa Falling slew rate 20 to 80 10 pF load unity gain Power low Opamp bias low 0 01 V us Power medium Opamp bias hig
70. e jitter RMS 400 1000 ps N 32 12 MHz IMO long term N cycle to cycle 700 1300 jitter RMS 12 MHz IMO period jitter RMS 300 500 Notes 27 2 4 V pp lt 3 0 V 28 Refer to application note Adjusting PSoC Trims for 3 3 V and 2 7 V Operation AN2012 for information on trimming for operation at 3 3 V 29 Refer to Cypress Jitter Specifications application note Understanding Datasheet Jitter Specifications for Cypress Timing Products AN5054 for more information Document Number 38 12028 Rev V Page 39 of 71 CY8C24123A CY8C24223A F CYPRESS CY8C24423A PERFORM Figure 11 PLL Lock Timing Diagram PLL Enable F4 Teisen gt 24 MHz PLL Gain Figure 12 PLL Lock for Low Gain Setting Timing Diagram PLL Enable Thusewow gt 24 MHz 1 PLL Gain Figure 13 External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz lt Tos Document Number 38 12028 Rev V Page 40 of 71 mE CY8C24123A EE CY8C24223A CYPRESS CY8C24423A PERFORM AC GPIO Specifications These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ty lt 85 C 3 0 V to 3 6 V and 40 C lt Ta 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 31 5 V and 3
71. e per industrial specs Add OCD non production pinout and package diagram Update CY branding and QFN convention Update package diagram revisions F 521439 HMT See ECN Add Low Power Comparator LPC AC DC electrical spec tables Add new Dev Tool section Add CY8C20x34 to PSoC Device Characteristics table G 2256806 UVS See ECN Added Sawn pin information PYRS H 2425586 DSO See ECN Corrected Ordering Information to include CY8C24423A 24LTXI and AESA CY8C24423A 24LTXIT 2619935 OGNE 12 11 2008 Changed title to CY8C24123A CY8C24223A CY8C24423A PSoc AESA Programmable System on Chip Updated package diagram 001 30999 to A Added note on digital signaling in DC Analog Reference Specifications on page 28 Added Die Sales information note to Ordering Information on page 60 J 2692871 DPT 04 16 2009 Updated Max package thickness for 32 pin QFN package PYRS Formatted Notes Updated Getting Started on page 7 Updated Development Tools on page 8 and Designing with PSoC Designer on page 9 K 2762168 JVY 06 25 2009 Updated DC GPIO AC Chip Level and AC Programming Specifications as AESA follows Modified FIMO6 and TWRITE specifications Replaced Tramp time specification with SRpower up slew rate specification Added note 9 to Flash Endurance specification Added IOH IOL DCj_o F32K us Tpowerup TERASEALL TPROGRAM HOT and TPROGRAM COLD specifications Document Number 38 1202
72. e set level This is one type of hardware reset Cypress Semiconductor s PSoC isa registered trademark and Programmable System on Chip is a trademark of Cypress The software for Cypress Programmable System on Chip technology An output in the form of duty cycle which varies as a function of the applied measurand An acronym for random access memory A data storage device from which data can be read out and new data can be written in A storage device with a specific capacity such as a bit or byte A means of bringing a system back to a know state See hardware reset and software reset An acronym for read only memory A data storage device from which data can be read out but new data cannot be written in 1 Pertaining to a process in which all events occur one after the other 2 Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel The time it takes for an output signal or value to stabilize after the input has changed from one value to another Page 65 of 71 PERFORM CY8C24123A CY8C24223A CY8C24423A Glossary continued shift register slave device stop bit synchronous tri state UART user modules user space Vpp Vss watchdog timer Document Number 38 12028 Rev V A memory storage device that sequentially shifts a word either left or right to output a stream of serial data A device that allows another device to co
73. e set to 2 or greater In this case the CPU clock divider ensures that the fifty percent duty cycle requirement is met 36 For the full industrial range you must employ a temperature sensor user module FlashTemp and feed the result to the temperature argument before writing Refer to the Flash APIs application note Design Aids Reading and Writing PSoC Flash AN2015 for more information Document Number 38 12028 Rev V Page 49 of 71 CY8C24123A CY8C24223A CY8C24423A PERFORM ACC Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 46 AC Characteristics of the IC SDA and SCL Pins for Vpp gt 3 0 V Symbol Description Sando Mode wanted Units Min Max Min Max Fscui2c SCL clock frequency 0 100 0 400 kHz tupsra2c Hold time repeated start condition After this period the first clock 4 0 0 6 us pulse is generated ti owi2c Low period of the SCL clock 4 7 1 3 us tuiGHi2c High period of the SCL clock 4 0 0 6 us SUSTAI2C Setup time for a repeated start
74. e used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL
75. eature set The core includes a CPU memory clocks and configurable GPIOs The M8C CPU core is a powerful processor with speeds up to 24Hz providing a four MIPS 8 bit Harvard architecture microprocessor The CPU uses an interrupt controller with 11 vectors to simplify programming of real time embedded events Program execution is timed and protected using the included sleep and watchdog timers WDT Memory encompasses 4 KB of flash for program storage 256 bytes of SRAM for data storage and up to 2 KB of EEPROM emulated using the flash Program flash uses four protection levels on blocks of 64 bytes allowing customized software IP protection The PSoC device incorporates flexible internal clock generators including a 24 MHz internal main oscillator IMO accurate to 2 5 to 5 over temperature and voltagel The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system A low power 32 kHz internal low speed oscillator ILO is provided for the sleep timer and WDT If crystal accuracy is required the ECO 32 768 kHz external crystal oscillator is available for use as a real time clock RTC and can optionally generate a crystal accurate 24 MHz system clock using a PLL The clocks together with programmable clock dividers as a System Resource provide the flexibility to integrate almost any timing requirement into the PSoC device PSoC GPIOSs provide connection to the CPU digital and analog resources of the devic
76. edium VREFHI Ref High 3 x Bandgap 2 771 3 885 3 979 V Opamp bias high Viseno AGND 2 x Bandgap 2 521 2 593 2 649 V Vrero Reflow Bandgap 1 240 1 295 1 331 V RefPower medium Vggrui Ref High 3 x Bandgap 3 771 3 887 3 977 V Opamp bias low Viseno AGND 2xBandgap 2 522 2 594 2 648 V VrerLo Reflow Bandgap 1 239 1 295 1 332 V 0b100 RefPower high Vrerw RefHigh 2xBandgap P2 6 2 481 P2 6 2 569 P2 6 2 639 P2 6 V Opamp bias high P2 6 1 3 V Vacnn AGND 2x Bandgap 2 511 2 590 2 658 VrerLo Reflow 2xBandgap P2 6 2 515 P2 6 2 602 P2 6 2 654 P2 6 V P2 6 1 3 V RefPower high Vrerw RefHigh 2xBandgap P2 6 2 498 P2 6 2 579 P2 6 2 642 P2 6 V Opamp bias low P2 6 1 3 V Vacnn AGND 2x Bandgap 2 518 2 592 2 652 V Vrerlo Reflow 2xBandgap P2 6 2 513 P2 6 2 598 P2 6 2 650 P2 6 V P2 6 1 3 V RefPower medium Vgggu RefHigh 2xBandgap P2 6 2 504 P2 6 2 583 P2 6 2 646 P2 6 V Opamp bias high P2 6 1 3 V Vacnn AGND 2x Bandgap 2 521 2 592 2 650 V VrerLo Reflow 2xBandgap P2 6 2 513 P2 6 2 596 P2 6 2 649 P2 6 V P2 6 1 3 V RefPower medium Very RefHigh 2xBandgap P2 6 2 505 P2 6 2 586 P2 6 2 648 P2 6 V Opamp bias low P2 6 1 3 V Vacnn AGND 2x Bandgap 2 521 2 594 2 648 V VrerLo Reflow 2xBandgap P2 6 2 513 P2 6 2 595 P2 6 2 648 P2 6 V P2
77. ernal circuit that is being driven by the analog output buffer VosoB Input offset voltage absolute value 3 12 mV TCVosog Average input offset voltage drift 6 uV C VcMoB Common mode input voltage range 0 5 Vpp 1 0 V RouroB Output resistance Power low 1 Q Power high 1 Q VomHieHos High output voltage swing Load 1 K ohms to Vpp 2 Power low 0 5 x Vpp 1 0 V Power high 05xVpp 1 0 V VorLowos Low output voltage swing Load 1 K ohms to Vpp 2 Power low 0 5xVpp 1 0 V Power high 0 5 x Vpp 1 0 V IsoB Supply current including Opamp bias cell no load 0 8 2 0 mA Power low 2 0 4 3 mA Power high PSRRog Supply voltage rejection ratio 52 64 dB Vout gt Vpp 1 25 Document Number 38 12028 Rev V Page 24 of 71 CY8C24123A f PERFORM Table 20 2 7 V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes C Load Capacitance 200 pF This specification applies to the external circuit that is being driven by the analog output buffer VosoB Input offset voltage absolute value 3 12 mV TCVosog Average input offset voltage drift 6 uVIC VcMoB Common mode input voltage range 0 5 Vpp 1 0 V RouroB Output resistance Power low 1 Q Power high 1 Q Vouicuop High output voltage swing Load 1 K ohms to Vpp 2 Power low 0
78. essfully implement your design Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I O pins Perform the selection configuration and routing so that you have complete control over all on chip resources Generate Verify and Debug When you are ready to test the hardware configuration or move on to developing code for the project perform the Generate Configuration Files step This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system The generated code provides APIs with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed A complete code development environment lets you to develop and customize your applications in C assembly language or both The last step in the development process takes place inside PSoC Designer s Debugger accessed by clicking the Connect icon PSoC Designer downloads the HEX image to the ICE where it runs at full speed PSoC Designer debugging capabilities rival those of systems costing many times more In addition to traditional single step run to breakpoint and watch variable features the debug interface provides a large trace buffer It lets you to define complex breakpoint events that include monitoring address and data bus values memory locations and exter
79. eudo random number generator or SPI digital to analog A device that changes a digital signal to an analog signal of corresponding magnitude The analog to digital ADC DAC converter performs the reverse operation Document Number 38 12028 Rev V Page 63 of 71 CY8C24123A Fes CY8C24223A CYPRESS CY8C24423A PERFORM Glossary continued duty cycle The relationship of a clock period high time to its low time expressed as a percent emulator Duplicates provides an emulation of the functions of one system with a different system so that the second System appears to behave like the first system external reset An active high signal that is driven into the PSoC device It causes all operation of the CPU and blocks to stop XRES and return to a pre defined state flash An electrically programmable and erasable non volatile technology that provides users with the programmability and data storage of EPROMs plus in system erasability Non volatile means that the data is retained when power is off Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected A Flash block holds 64 bytes frequency The number of cycles or events per unit of time for a periodic function gain The ratio of output current voltage or power to input current voltage or power respectively Gain is usually expressed in dB Ic A two wire serial computer bus by Ph
80. f data and serial bits Pre build pre tested hardware firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks User Modules also provide high level API Application Programming Interface for the peripheral function The bank 0 space of the register map The registers in this bank are more likely to be modified during normal program execution and not just during initialization Registers in bank 1 are most likely to be modified only during the initialization phase of the program A name for a power net meaning voltage drain The most positive power supply signal Usually 5 V or 3 3 V A name for a power net meaning voltage source The most negative power supply signal A timer that must be serviced periodically If it is not serviced the CPU resets after a specified period of time Page 66 of 71 CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM Errata This section describes the errata for the CY8C24xxxA device family Details include errata trigger conditions scope of impact available workaround and silicon revision applicability Contact your local Cypress Sales Representative if you have questions Part Numbers Affected Part Number Ordering Information CY8C24123A CY8C24123A 24PXI CY8C24123A 24SXI CY8C24123A 24SXIT CY8C24223A 24PXI CY8C24223A 24PVXI CY8C24223A 24PVXIT CY8C24223A 24SXI CY8C24223A 24SXIT CY8C24423A 24PXI CY8C24423
81. ges 4 75 V to 5 25 V and 40 C lt TA 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Note The bits PORLEV and VM in the following table refer to bits in the VLT CR register See the PSoC Programmable Sytem on Chip Technical Reference Manual for more information on the VLT CR register Table 26 DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes Vpp value for PPOR trip Vpp must be greater than or VppoRo PORLEV 1 0 00b 2 36 2 40 V Jegualto2 5V during startup VPPOR1 PORLEV 1 0 01b 2 82 2 95 V reset from the XRES pin or Vppor2 PORLEV 1 0 10b 4 55 4 70 V reset from watchdog Vpp value for LVD trip Vivpo VM 2 0 000b 2 40 245 2 5172 V Vivp1 VM 2 0 001b 2 85 2 92 2 9913 V Vivp2 VM 2 0 010b 2 95 3 02 3 09 V Vivp3 VM 2 0 011b 3 06 3 13 3 20 V Vivb4 VM 2 0 100b 4 37 4 48 4 55 V VLVb5 VM 2 0 101b 4 50 4 64 4 75 V Vivpe VM 2 0 110b 4 62 4 73 4 83 V Vivp7 VM 2 0 111b 4 71 4 81 4 95 V Vpp value for SMP trip Vpumpo VM 2 0 000b 2 50 2 55 26214 V Vpump1 VM 2 0 001b 2 96 3 02 3 09 V Vpump2 _ VM 2 0 010b 3 03 3 10 3 16 V Vpump3 VM 2 0 011b 3 18 325 3 3205 V Vpump4 VM 2 0 100b 4 54 4 64 4 74 V Vpump3 VM 2 0 101b 4 62 4 73 4 83 V Vpumps VM 2 0 110b 471 4 82 4 92 V Vp
82. h Number I O Rows Blocks Inputs Outputs Columns Blocks Size Size CY8C29x66 up to 64 4 16 up to 12 4 4 12 2K 32K CY8C28xxx up to 44 upto3 upto 12 upto 44 up to 4 up to 6 re 1K 16K CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16K CY8C24x94 up to 56 1 4 up to 48 2 2 6 1K 16K CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4K CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8K CY8C22x45 up to 38 2 8 up to 38 0 4 6 1K 16K CY8C21x45 up to 24 1 4 up to 24 0 4 6 512 8K CY8C21x34 up to 28 1 4 up to 28 0 2 42 512 8K CY8C21x23 up to 16 1 4 upto 8 0 2 4l2 256 4K CY8C20x34 up to 28 0 0 up to 28 0 0 312 31 512 8K CY8C20xx6 up to 36 0 0 up to 36 0 0 32 3 up to up to 2K 32 K Notes 2 Limited analog functionality a 3 Two analog blocks and one CapSense Document Number 38 12028 Rev V Page 6 of 71 PERFORM Getting Started For in depth information along with detailed programming details see the PSoC Technical Reference Manual For up to date ordering packaging and electrical specification information see the latest PSOC device datasheets on the web Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors which include Arrow Avnet Digi Key Farnell Future Electronics and Newark Training Free PSoC technical training on demand web
83. h 0 5 V us Power high Opamp bias high 4 0 V us BWoa Gain bandwidth product Power low Opamp bias low 0 75 MHz Power medium Opamp bias high 3 1 MHz Power high Opamp bias high 5 4 MHz Enoa Noise at 1 kHz Power medium Opamp bias high 100 nV rt Hz Table 34 3 3 V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units tkoa Rising settling time from 80 of AV to 0 1 of AV 10 pF load unity gain Power low Opamp bias low 3 92 us Power medium Opamp bias high 0 72 us tsoa Falling settling time from 20 of AV to 0 1 of AV 10 pF load unity gain Power low Opamp bias low 5 41 us Power medium Opamp bias high 0 72 us SRroa Rising slew rate 20 to 80 10 pF load unity gain Power low Opamp bias low 0 31 V us Power medium Opamp bias high 2 7 V us SRroa Falling slew rate 20 to 80 10 pF load unity gain Power low Opamp bias low 0 24 V us Power medium Opamp bias high 1 8 V us BWoa Gain bandwidth product Power low Opamp bias low 0 67 MHz Power medium Opamp bias high 2 8 MHz ENoa Noise at 1 kHz Power medium Opamp bias high 100 nV rt Hz Document Number 38 12028 Rev V Page 42 of 71 CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM Table 35 2 7 V AC Operational Amplifier Specifications
84. h level 0 7 x Vpp V 2 4 V lt Vpp lt 5 25 V Notes 16 The 50 000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range Voltage ranges are 2 4 V to 3 0 V 3 0 V to 3 6 V and 4 75 V to 5 25 V 17 A maximum of 36 x 50 000 block endurance cycles is allowed This may be balanced between operations on 36 x 1 blocks of 50 000 maximum cycles each 36 x 2 blocks of 25 000 maximum cycles each or 36 x 4 blocks of 12 500 maximum cycles each to limit the total number of cycles to 36 x 50 000 and that no single block ever sees more than 50 000 cycles For the full industrial range the user must employ a temperature sensor user module FlashTemp and feed the result to the temperature argument before writing Refer to the Flash APIs application note Design Aids Reading and Writing PSoC Flash AN2015 for more information 18 All GPIOs meet the DC GPIO Vj and Viu specifications found in the DC GPIO Specifications sections The PC GPIO pins also meet the above specs Document Number 38 12028 Rev V Page 36 of 71 CY8C24123A CY8C24223A CY8C24423A PERFORM AC Electrical Characteristics AC Chip Level Specifications These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Tp lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typica
85. ication removed existing jitter specifications Updated Analog reference tables Updated Units of Measure Acronyms Glossary and References sections Updated solder reflow specifications No specific changes were made to AC Digital Block Specifications table and Ic Timing Diagram They were updated for clearer understanding Updated Figure 13 since the labelling for y axis was incorrect Template and styles update Sunset review no content update P 3351721 YJI 08 31 2011 Full annual review of document No changes are required Q R S 3367463 3598291 3991993 BTK GIR LURE XZNG PMAD 09 22 2011 04 24 2012 05 08 2013 Updated text under DC Analog Reference Specifications on page 28 Removed package diagram spec 51 85188 as there is no active MPN using this outline drawing The text Pin must be left floating is included under Description of NC pin in Table 5 on page 13 and Table 6 on page 14 Updated Table 50 on page 57 to give more clarity Removed Footnote 35 Changed the PWM description string from 8 to 32 bit to 8 and 16 bit Updated Packaging Information spec 51 85066 Changed revision from E to F spec 51 85014 Changed revision from F to G spec 51 85026 Changed revision from F to G spec 001 30999 Changed revision from C to D spec 51 85062 Changed revision from E to F Updated Reference Documents Removed 001 17
86. ifications of the CY8C24x23A PSoC device For the latest electrical specifications check if you have the most recent datasheet by visiting the website at http www cypress com Specifications are valid for 40 C x Ta x 85 C and Ty x 100 C except where noted Refer to Table 29 on page 37 for the electrical specifications for the IMO using SLIMO mode Figure 9 Voltage versus CPU Frequency Figure 8 IMO Frequency Trim Options A A 5 25 5 25 4 75 L 4 75 2 5 5 o 3 60 o 3 00 3 00 240 240 gt T T T T gt 93 kHz 3 MHz 12 MHz 24 MHz 93 kHz 6 MHz 12MHz 24 MHz CPUFrequency IMOFrequency Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device User guidelines are not tested Table 9 Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes Tste Storage temperature 55 25 100 C_ Higher storage temperatures reduce data retention time Recommended storage temperature is 25 C 25 C Extended duration storage temperatures above 65 C degrades reliability Tpaketemp Bake temperature 125 See C package label tsakerime Bake time See 72 Hours package label TA Ambient temperature with power applied 40 85 C Vpp Supply voltage on Vpp relative to Vss 0 5 6 0 V Vio DC input voltage Vss 0 5 Vpp 0 5 V Vioz DC voltage applied to tri sta
87. ilips Semiconductors now NXP Semiconductors I2C is an Inter Integrated Circuit It is used to connect low speed peripherals in an embedded system The original system was created in the early 1980s as a battery control interface but it was later used as a simple internal bus system for building control electronics I2C uses only two bi directional pins clock and data both running at 5 V and pulled high with resistors The bus operates at 100 kbits second in standard mode and 400 kbits second in fast mode ICE The in circuit emulator that allows users to test the project in a hardware environment while viewing the debugging device activity in a software environment PSoC Designer input output I O A device that introduces data into or extracts data from a system interrupt A suspension of a process such as the execution of a computer program caused by an event external to that process and performed in such a way that the process can be resumed interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt Many routine ISR interrupt sources may each exist with its own priority and individual ISR code block Each ISR code block ends with the RETI instruction returning the device to the point in the program where it left normal program execution jitter 1 A misplacement of the timing of a transition from its ideal position A typical form of corruption that occurs on serial dat
88. inars and workshops which is available online via www cypress com Document Number 38 12028 Rev V CY8C24123A CY8C24223A CY8C24423A covers a wide variety of topics and skill levels to assist you in your designs CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs To contact or become a PSoC Consultant go to the CYPros Consultants web site Solutions Library Visit our growing library of solution focused designs Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly Technical Support Technical support including a searchable knowledge base articles and technical forums is also available online If you cannot find an answer to your question call our Technical Support hotline at 1 800 541 4736 Page 7 of 71 PERFORM Development Tools PSoC Designer is the revolutionary integrated design environment IDE that you can use to customize PSoC to meet your specific application requirements PSoC Designer software accelerates system design and time to market Develop your applications using a library of precharacterized analog and digital peripherals called user modules in a drag and drop design environment Then customize your design by leveraging the dynamically generated application programming interface API libraries of code Finally debug and test yo
89. ions and dynamic reconfiguration Dynamic reconfiguration makes it possible to change configurations at run time In essence this lets you to use more than 100 percent of PSoC s resources for an application Document Number 38 12028 Rev V CY8C24123A CY8C24223A CY8C24423A Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools You can develop your design in C assembly or a combination of the two Assemblers The assemblers allow you to merge assembly code seamlessly with C code Link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing C Language Compilers C language compilers are available that support the PSoC family of devices The products allow you to create complete C programs for the PSoC family devices The optimizing C compilers provide all of the features of C tailored to the PSoC architecture They come complete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality Debugger PSoC Designer has a debug environment that provides hardware in circuit emulation allowing you to test the program in a physical system while providing an internal view of the PSoC device Debugger commands allow you to read and program and read and write data memory and
90. ith PSoC Programmer The kit includes m CY3207 programmer unit m PSoC ISSP software CD m 110 240 V power supply Euro Plug adapter m USB 2 0 cable Part Number Pin Package Flex Pod Kit Foot Kit Adapter 21 All non QFN All non QFN CY3250 24X23A Adapters can be found at CY3250 8DIP FK http www emulation com CY3250 8SOIC FK CY3250 20DIP FK CY3250 20SOIC FK CY3250 20SSOP FK CY3250 28DIP FK CY3250 28SOIC FK CY3250 28SSOP FK Notes 40 Flex Pod kit includes a practice flex pod and a practice PCB in addition to two flex pods 41 Foot kit includes surface mount feet that can be soldered to the target PCB 42 Programming adapter converts non DIP package to DIP footprint Specific details and ordering information for each of the adapters can be found at http www emulation com Document Number 38 12028 Rev V Page 59 of 71 CY8C24123A SSS CYPRESS CY8C24423A PERFORM Ordering Information The following table lists the CY8C24x23A PSoC device s key package features and ordering codes Table 52 CY8C24x23A PSoC Device Key Features and Ordering Information o o o 9 2 2 2 2 9 a aera rS 3 Sue Morales ea e 3 F e e e o E Po Lo 6g a oe miela ee S o as la 5 9 sS 5 B8 glx c fe id E aAia a lt 4 8 pin 300 mil DIP CY8C24123A 24PXI 4K 256 No 40 C to 85 C 4 6 6 4 2 No 8 pin 150 mil SOIC CY8C24123A 24SXI
91. k 0 Table User Space Name Addr 0 Hex Access Name Addr 0 Hex Access Name Addr 0 Hex Access Name Addr 0 Hex Access PRTODR 00 RW 40 ASC10CRO 80 RW CO PRTOIE 01 RW 41 ASC10CR1 81 RW C1 PRTOGS 02 RW 42 ASC10CR2 82 RW C2 PRTODM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CRO 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 4T ASD11CR3 C7 PRT2DR 08 RW 48 C8 PRT2IE 09 RW 49 C9 PRT2GS OA RW 4A CA PRT2DM2 0B RW 4B CB 0c 4C CC OD 4D CD 0E 4E CE OF 4F CF 70 DO 11 51 ASD20CR1 D1 73 D3 74 D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 2C_CFG D6 RW 17 57 ASC21CR3 2C SCR D7 18 58 2C DR D8 RW 19 59 2C MSCR D9 1A 5A 9A NT CLRO DA RW 1B 5B 9B NT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D NT_CLR3 DD RW 1E 5E 9E NT_MSK3 DE RW 1F 5F 9F DF DBBOODRO 20 AMX IN 60 RW A0 NT MSKO EO RW DBBOODR1 21 Ww 61 A1 NT MSK1 E1 RW DBBOODR2 22 RW A2 NT VC E2 RC DBBOOCRO 23 ARF CR A3 RES WDT E3 Ww DBBO1DRO 24 CMP_CRO A4 DEC_DH E4 RC DBBO1DR1 25 Ww ASY CR A5 DEC DL E5 RC DBBO1DR2 26 RW CMP CR1 A6 DEC CRO E6 RW DBBO1CRO 27 AT DEC CR1 E7 RW DCBO2DRO 28 A8 MUL X E8 Ww DCBO2DR1 29 WwW AQ MUL_Y E9 Ww DCBO2DR2 2A RW AA MUL DH EA R DCBO2CRO 2B MUL DL EB R DCBO3DRO 2C ACC DR1 EC RW DCBO3DR1
92. l parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 29 5 V and 3 3 V AC Chip Level Specifications Symbol Description Min Typ Max Units Notes Fimoz4 7 Internal main oscillator IMO frequency 22 8 24 25 270 771 MHz Trimmed for 5 V or 3 3 V operation for 24 MHz using factory trim values See Figure 8 on page 18 SLIMO mode 0 Fi Moe IMO frequency for 6 MHz 5 5 6 6 5 2021 MHz Trimmed for 5 V or 3 3 V operation using factory trim values See Figure 8 on page 18 SLIMO mode 1 Fopu1 CPU frequency 5 V nominal 0 937 24 24 611 MHz SLIMO mode 0 Fepu2 CPU frequency 3 3 V nominal 0 937 12 12 341 MHz SLIMO mode 0 F48M Digital PSoC block frequency 0 48 49 220 227 MHz Refer to the AC Digital Block Specifications Foam Digital PSoC block frequency 0 24 24 61221 MHz F32k1 ILO frequency 15 32 64 kHz Faok2 External crystal oscillator 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle Faok U ILO untrimmed frequency 5 100 kHz After a reset and before the M8C starts to run the ILO is not trimmed See the System Resets section of the PSoC Technical Reference Manual for details on timing this Fei PLL frequency 23 986 MHz Is a multiple x732 of crystal frequency TPLLSLEW PLL lock time 0 5 10 ms TpLLSLEwsLow PLL lock time for low gain setting 0 5 50 ms Tos Exte
93. lement a wide variety of user selectable functions The PSoC development process is 6 Select user modules 7 Configure user modules 8 Organize and connect 9 Generate verify and debug Select User Modules PSoC Designer provides a library of prebuilt pretested hardware peripheral components called user modules User modules make selecting and implementing peripheral devices both analog and digital simple Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function They also provide parameters and properties that allow you to tailor their precise configuration to your particular application For example a PWM User Module configures one or more digital PSoC blocks one for each eight bits of resolution Using these parameters you can establish the pulse width and duty cycle Configure the parameters and properties to correspond to your chosen application Enter values directly or by selecting values from drop down menus All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website These user module datasheets explain the internal operation of the user module and provide performance specifications Each datasheet describes the use of each user Document Number 38 12028 Rev V CY8C24123A CY8C24223A CY8C24423A module parameter and other information that you may need to succ
94. nal signals Page 9 of 71 CY8C24123A CY8C24223A CYPRESS CY8C24423A This section describes lists and illustrates the CY8C24x23A PSoC device pins and pinout configurations Every port pin labeled with a P is capable of digital I O However Vss Vpp SMP and XRES are not capable of digital I O 8 Pin Part Pinout Table 2 8 Pin PDIP and SOIC Pin Type Pin Sn Figure 4 CY8C24123A 8 Pin PSoC Device Description No Digital Analog Name eae 1 y o I O PO 5 Analog column mux input and column A IO PO S Vop output A 10 PO 3 PO A 2 I O VO PO 3 Analog column mux input and column 126 SOL KTALIN PIM POL A output Vss P1 0 XTALout I2C SDA 3 I O P1 1 Crystal input XTALin IC serial clock SCL ISSP SCLK 4 Power Vss Ground connection 5 y o P1 0 Crystal output XTALout I C serial data SDA ISSP SDATAW 6 I O PO 2 Analog column mux input 7 I O PO 4 Analog column mux input Power Vpp Supply voltage LEGEND A Analog Input and O Output Note 4 These are the ISSP pins which are not high Z at POR See the PSoC Technical Reference Manual for details Document Number 38 12028 Rev V Page 10 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM 20 Pin Part Pinout Table 3 20 Pin PDIP SSOP and SOIC i Type i OM Figure
95. ncies increased power level reduces the noise spectrum level Document Number 38 12028 Rev V Page 43 of 71 ZZ CYPRESS PERFORM Figure 15 Typical Opamp Noise 1000 100 CY8C24123A CY8C24223A CY8C24423A 10 0 001 0 01 AC Low Power Comparator Specifications Table 36 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V at 25 C and are for design guidance only Table 36 AC Low Power Comparator Specifications Freq kHz Symbol Description Min Typ Max Units Notes tRLPC LPC response time 50 us gt 50 mV overdrive comparator reference set within VREFLPC Document Number 38 12028 Rev V Page 44 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 37 5 V and 3 3 V AC Digi
96. ntrol the timing for data exchanges between two devices Or when devices are cascaded in width the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface The controlling device is called the master device An acronym for static random access memory A memory device allowing users to store and retrieve data at a high rate of speed The term static is used because after a value has been loaded into an SRAM cell it remains unchanged until it is explicitly altered or until power is removed from the device An acronym for supervisory read only memory The SROM holds code that is used to boot the device calibrate circuitry and perform Flash operations The functions of the SROM may be accessed in normal user code operating from Flash A signal following a character or block that prepares the receiving device to receive the next character or block 1 A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal 2 A system whose operation is synchronized by a clock signal A function whose output can adopt three states 0 1 and Z high impedance The function does not drive any value in the Z state and in many respects may be considered to be disconnected from the rest of the circuit allowing another output to drive the same net A UART or universal asynchronous receiver transmitter translates between parallel bits o
97. o permit the realization of a controller with a minimal quantity of chips thus achieving maximal possible miniaturization This in turn reduces the volume and the cost of the controller The microcontroller is normally not used for general purpose computation as is a microprocessor The reference to a circuit containing both analog and digital techniques and components A device that imposes a signal on a carrier 1 A disturbance that affects a signal and that may distort the information carried by the signal 2 The random variations of one or more characteristics of any entity such as voltage current or data A circuit that may be crystal controlled and is used to generate a clock frequency A technique for testing transmitting data Typically a binary digit is added to the data to make the sum of all the digits of the binary data either always even even parity or always odd odd parity An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal The pin number assignment the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board PCB package Pinouts involve pin numbers as a link between schematic and PCB design both being computer generated files and may also involve pin names A group of pins usually eight A circuit that forces the PSoC device to reset when the voltage is lower than a pr
98. oating 36 NC No connection Pin must be left floating 37 NC No connection Pin must be left floating 38 NC No connection Pin must be left floating 39 NC No connection Pin must be left floating 40 NC No connection Pin must be left floating 41 Input XRES Active high external reset with internal puli down 42 OCD HCLK OCD high speed clock output 43 OCD CCLK OCD CPU clock output 44 NC No connection Pin must be left floating 45 NC No connection Pin must be left floating 46 NC No connection Pin must be left floating 47 NC No connection Pin must be left floating 48 yo P2 0 Direct switched capacitor block input 49 yo P2 2 Direct switched capacitor block input 50 VO P2 4 External AGND 51 1 0 P2 6 External VREF 52 yo PO 0 Analog column mux input 53 yo PO 2 Analog column mux input and column output 54 yo PO 4 Analog column mux input and column output 55 yo PO 6 Analog column mux input 56 Power VDD Supply voltage LEGEND A Analog I Input O Output and OCD On Chip Debug Note CY8C24123A CY8C24223A CY8C24423A Figure 8 CY8C24000A 56 Pin PSoC Device 12C SCL P17 I2C SDA P1 5 NC P1 3 SCLK I2C SCL XTALIn P1 1 Vss 9 These are the ISSP pins which are not high Z at POR See the PSoC Technical Reference Manual for details Document Number 38 12028 Rev V O OONOAARWNA SSOP 56 55 54 53 52 51 50 48 P Voo F Po 6 Al fa PO 4 AIO P PO 2 AIO Ia
99. ock freguency divided by 2 SPIS Input clock freguency 4 23 MHz Width of SS Negated between transmissions 1001811 ns Transmitter Input clock frequency 12 7 MHz The baud rate is equal to the input clock freguency divided by 8 Receiver Input clock frequency 12 7 MHz The baud rate is equal to the input clock freguency divided by 8 Note 31 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz 84 ns nominal period Document Number 38 12028 Rev V Page 46 of 71 CY8C24123A fe CY8C24223A CYPRESS CY8C24423A PERFORM AC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta 85 C 3 0 V to 3 6 V and 40 C lt Ta 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 39 5 V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units trop Rising settling time to 0 1 1 V Step 100 pF load Power low 2 5 us Power high 2 5 us tsop Falling settling time to 0 196 1 V Step 100 pF load Power 7 low 2 2 us Power high 2 2 us SRrop Rising slew rate 20 to 80 1 V Step 100 pF lo
100. or current whenever two input levels simultaneously satisfy predetermined amplitude requirements compiler A program that translates a high level language such as C into machine language configuration In PSoC devices the register space accessed when the XIO bit in the CPU F register is set to 1 space crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components cyclicredundancy A calculation used to detect errors in data communications typically performed using a linear feedback shift check CRC register Similar calculations may be used for a variety of other purposes such as data compression data bus A bi directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa More generally a set of signals used to convey data between digital functions debugger A hardware and software system that allows the user to analyze the operation of the system under development A debugger usually allows the developer to step through the firmware one step at a time set break points and analyze memory dead band A period of time when neither of two or more signals are in their active state or in transition digital blocks The 8 bit logic blocks that can act as a counter timer serial receiver serial transmitter CRC generator ps
101. outed to both the digital and analog systems Additional clocks may be generated using digital PSoC blocks as clock dividers m The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs m The I2C module provides 100 and 400 kHz communication over two wires slave master and multi master are supported m Low voltage detection LVD interrupts can signal the appli cation of falling voltage levels while the advanced POR circuit eliminates the need for a system supervisor m An internal 1 3 V reference provides an absolute reference for m A multiply accumulate MAC provides a fast 8 bit multiplier the analog system me VON ADCS and DACS with 32 bit accumulate to assist in both general math and digital filters m An integrated switch mode pump generates normal operating voltages from a single 1 2 V battery cell providing a low cost boost converter PSoC Device Characteristics Depending on your PSoC device characteristics the digital and analog systems can have 16 8 or 4 digital blocks and 12 6 or 4 analog blocks Table 1 on page 6 lists the resources available for specific PSoC device groups The PSoC device covered by this datasheet is highlighted in this table Table 1 PSoC Device Characteristics PSoC Part Digital Digital Digital Analog Analog Analog Analog SRAM Flas
102. pple SMP trip voltage is set to 2 55 V Ipump Available output current Configuration listed in footnote 11 Vegar 1 8 V Vpymp 5 0 V 5 mA SMP trip voltage is set to 5 0 V Vear 1 5 V Vpump 3 25 V 8 mA SMP trip voltage is set to 3 25 V Vear 1 3 V Vpump 2 55 V 8 mA SMP trip voltage is set to 2 55 V Vgarb V Input voltage range from 1 8 5 0 V Configuration listed in footnote battery SMP trip voltage is set to 5 0 V Vgar3 V Input voltage range from 1 0 3 3 V Configuration listed in footnote 1 battery SMP trip voltage is set to 3 25 V Vpat2V Input voltage range from 1 0 3 0 V Configuration listed in footnote battery SMP trip voltage is set to 2 55 V VBATSTART Minimum input voltage from 1 2 V Configuration listed in footnote battery to start pump 0 C lt Ta x 100 1 25 Vat Ta 40 C AVpump Line Line regulation over Vgar 5 Vo Configuration listed in footnote Vo E range is the Vpp Value for PUMP Trip specified by the VM 2 0 setting in the DC POR and LVD Specification Table 26 on page 35 AVpump Load Load regulation 5 Vo Configuration listed in footnote Vo d is the Vpp value for PUMP Trip specified by the VM 2 0 setting in the DC POR and LVD Specification Table 26 on page 35 AVpUMP Ripple Output voltage ripple depends i 100 i mVpp Configuration listed in footnote T on capacitor load Load is 5 mA E3 Efficiency 35 50 Configuration lis
103. propriate Vpp Vpp gt 3 0 V Vggr2 Reference voltage Bandgap 1 16 1 30 1 32 V Trimmed for appropriate Vpp Vpp 24 V to 3 0 V Note 10 Standby current includes all functions POR LVD WDT sleep time needed for reliable system operation This must be compared with devices that have similar functions enabled Document Number 38 12028 Rev V Page 19 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM DC GPIO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 12 5 V and 3 3 V DC GPIO Specifications Symbol Description Min Typ Max Units Notes Rpy Pull up resistor 4 5 6 8 KQ Rpp Pull down resistor 4 5 6 8 kQ Vou High output level Vpp 1 0 V lon 10 MA Vpp 4 75 to 5 25 V maximum 40 mA on even port pins for example PO 2 P1 4 maximum 40 mA on odd port pins for example PO 3 P1 5 80 mA maximum combined lop budget VoL Low output level 0 75 V lo 25 mA Vpp 4 75 to 5 25 V maximum 100 mA on even port pins for
104. quence DTMF dual tone multi frequency PSoC Programmable System on Chip ECO external crystal oscillator PWM pulse width modulator EEPROM electrically erasable programmable read only QFN quad flat no leads memory GPIO general purpose I O RTC real time clock ICE in circuit emulator SAR successive approximation IDE integrated development environment SC switched capacitor ILO internal low speed oscillator SLIMO slow IMO IMO internal main oscillator SMP switch mode pump I O input output SOIC small outline integrated circuit IrDA infrared data association SPITM serial peripheral interface ISSP in system serial programming SRAM static random access memory LCD liquid crystal display SROM supervisory read only memory LED light emitting diode SSOP shrink small outline package LPC low power comparator UART universal asynchronous receiver transmitter LVD low voltage detect USB universal serial bus MAC multiply accumulate WDT watchdog timer MCU microcontroller unit XRES external reset Reference Documents CY8CPLC20 CY8CLED16P01 CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23 CY8C24x23A CY8C22x13 CY8C21x34 CY8C21x23 CY7C64215 CY7C603xx CY8CNP1xx and CYWUSB6953 PSoC Programmable System on Chip Technical Reference Manual TRM 001 14463 Design Aids Reading and Writing PSoC Flash AN2015 001 40459 Application Notes for Surface Mount Assembly of Amkor s MicroLeadFrame MLF Packages available at http www amkor com
105. read and write I O registers You can read and write CPU registers set and clear breakpoints and provide program run halt and step control The debugger also lets you to create a trace buffer of registers and memory locations of interest Online Help System The online help system displays online context sensitive help Designed for procedural and quick reference each functional subsystem has its own context sensitive help This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer In Circuit Emulator A low cost high functionality in circuit emulator ICE is available for development support This hardware can program single devices The emulator consists of a base unit that connects to the PC using a USB port The base unit is universal and operates with all PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the target board and performs full speed 24 MHz operation Page 8 of 71 PERFORM Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs These configurable resources called PSoC blocks have the ability to imp
106. rnal crystal oscillator startup to 1 B 1700 2620 ms TosAcc External crystal oscillator startup to 2800 3800 ms The crystal oscillator freguency is 100 ppm within 100 ppm of its final value by the end of the Tosacc period Correct operation assumes a properly loaded 1 uW maximum drive level 32 768 kHz crystal 3 0 V lt Vpp lt 5 5 V 40 C lt Ta lt 85 C txrsT External reset pulse width 10 US Notes 19 Errata When the device is operated within 0 C to 70 C the frequency tolerance is reduced to 2 5 but if operated at extreme temperature below 0 C or above 70 C frequency tolerance deviates from 2 5 to 5 For more information see Errata on page 67 20 4 75 V lt Vpp lt 5 25 V 21 3 0 V Vpp 3 6 V See application note Adjusting PSoC Trims for 3 3 V and 2 7 V Operation AN2012 for information on trimming for operation at 3 3 V 22 See the individual user module datasheets for information on maximum frequencies for user modules 23 Refer to Cypress Jitter Specifications application note Understanding Datasheet Jitter Specifications for Cypress Timing Products AN5054 for more information Document Number 38 12028 Rev V Page 37 of 71 CY8C24123A Fes CY8C24223A CYPRESS CY8C24423A PERFORM Table 29 5 V and 3 3 V AC Chip Level Specifications continued Symbol Description Min Typ Max Units Notes
107. rrent in note for VoL In Input leakage absolute value 1 nA Gross tested to 1 uA Cin Capacitive load on pins as input 3 5 10 pF Package and pin dependent Temp 25 C Cout Capacitive load on pins as output 3 5 10 pF Package and pin dependent Temp 25 C Document Number 38 12028 Rev V Page 20 of 71 mE CY8C24123A F ge s CY8C24223A CYPRESS CY8C24423A PERFORM DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta 85 C 3 0 V to 3 6 V and 40 C lt Ta 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only The operational amplifier is a component of both the analog continuous time PSoC blocks and the Analog Switched Cap PSoC blocks The guaranteed specifications are measured in the analog continuous time PSoC block Typical parameters are measured at 5 V at 25 C and are for design guidance only Table 14 5 V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes Vosoa Input offset voltage absolute value Power low Opamp bias high 1 6 10 mV Power medium Opamp bias high _ 1 3 8 mV Power high Opamp bias high 1
108. s for Surface Mount Assembly of Amkor s MicroLeadFrame MLF Packages available at www amkor com Document Number 38 12028 Rev V Page 57 of 71 PERFORM Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C24x23A family Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer used to generate PSoC firmware applications PSoC Designer is available free of charge at http www cypress com and includes a free C compiler PSoC Programmer Flexible enough to be used on the bench in development yet suitable for factory programming PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer PSoC Programmer software is compatible with both PSoC ICE Cube In Circuit Emulator and PSoC MiniProg PSoC programmer is available free ofcharge at http www cypress com Development Kits All development kits can be purchased from the Cypress Online Store CY3215 DK Basic Development Kit The CY3215 DK is for prototyping and development with PSoC Designer This kit supports in circuit emulation and the software interface lets you to run halt and single step the processor and view the content of specific memory locations Advance emulation features also supported through PSoC Designer The kit includes m PSoC Designer software CD m ICE Cube in circuit emulator m
109. t gt Extemal Headers Parameters UART 1 vax t d passer n con Fee SU UNTI 1 In ahh ee d L 4 m z Y Datasheet Workspace Explorer Code Outlining User Modules ax JJ VE Da 8 Bit UART Datasheet d User Modules uart V53 seem 5 0 Ampifiers SoC Blocks API MEMORY Finn 5 Analog Comm i Bytes ms s Counters Indicates the name used to identf this Resources A bom DAC Me Digital Flash RAM User Module instance igi ox kg Emp mal D M ticked Cus T z F a CRC16 Pinout pdproject5 3x CY8C29 27 24 22 21xxx CY8C23x33 CY7C64215 CYWUSB6953 a EzI2Cs E PO 0 Port 0 0 StdCPU Hi Y8CLED02 04 08 16 CY8CLEDOxD CY8CLEDOxG CY8CTST110 CY8CTMG110 rj I2CHW E pom Port 0 1 SJCPU Hi CYBCTST120 CY8CTMG120 CYSCTMA120 140 CYBC21X45 pori P 02 StdCPU Hi CY8C22x45 CY8CTMA30xx CVBC28x 16PO1 og E SU cysczex43 CYBC28x52 amp PO Port 0 3 StdCPU Hi amp PO 4 Port 0 4 StdCPU Hi CY8C29 27xxx Low 2 0 2 I pos Port 0 5 StdCPU Hi CY8CLEDOSA6 Level POf 6 Port 0 6 StdCPU Hi CYSCPLC20 API CY8C28x43 PO Pot 0 7 StCPU Hi ee E Ed ES ar 2 PO Pot 1 0 StdCPU Hi l chow Level Buffer z Patt Port_1_1 StdCPU Hi API size a UART Pil Pot12 SdCUH defaut 1 mame PI Pot 1 3 St4CPUL Hi 7 a Genetic ii Output Document Number 38 12028 Rev V Page 20f71 Contents PSoC Functional Overview o mo 3 PSOG COE E aan hb sa aa 3 Digital System
110. table Completing Sunset Review v 4622083 01 13 2015 Added More Information section RKRM Document Number 38 12028 Rev V Page 70 of 71 a 1 di CY8C24223A SS CYPRESS CY8C24423A E CY8C24123A PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Automotive cypress com go automotive psoc cypress com solutions Clocks amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Developer Community Lighting amp Power Control cypress com go powerpsoc Community Forums Blogs Video Training Memory cypress com go memory PSoC cypress com go psoc Technical Support Touch Sensing cypress com go touch cypress com go support USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2004 2015 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to b
111. tal Block Specifications Function Description Min Typ Max Unit Notes All functions Block input clock frequency Vpp 2 4 75 V 50 4 MHz Vpp lt 4 75 V 25 2 MHz Timer Input clock frequency No capture Vpp 2 4 75 V 50 4 MHz No capture Vpp 4 75 V 25 2 MHz With capture 25 2 MHz Capture pulse width 501801 ns Counter Input clock frequency No enable input Vpp 2 4 75 V 50 4 MHz No enable input Vpp lt 4 75 V 25 2 MHz With enable input 25 2 MHz Enable input pulse width 5ol300 ns Dead Band Kill pulse width Asynchronous restart mode 20 ns Synchronous restart mode 501801 ns Disable mode 501801 ns Input clock frequency Vpp 2 4 75 V 50 4 MHz Vpp lt 4 75 V 25 2 MHz CRCPRS Input clock freguency ed Vpp2475V z 504 MHz Vpp lt 4 75 V 25 2 MHz CRCPRS Input clock freguency 25 2 MHz CRC Mode SPIM Input clock frequency 8 2 MHz The SPI serial clock SCLK freguency is egual to the input clock freguency divided by 2 SPIS Input clock SCLK freguency 4 1 MHz The input clock is the SPI SCLK in SPIS mode Width of SS negated between 501301 ns transmissions Transmitter Input clock frequency The baud rate is equal to the input clock frequency Vpp gt 4 75 V 2 stop bits 1 504
112. te Vgs 0 5 Vpp 0 5 V Imo Maximum current into any port pin 25 50 mA ESD Electrostatic discharge voltage 2000 V Human body model ESD LU Latch up current 200 mA Document Number 38 12028 Rev V Page 18 of 71 CY8C24123A Z CY8C24223A CYPRESS CY8C24423A PERFORM Operating Temperature Table 10 Operating Temperature Symbol Description Min Typ Max Units Notes TA Ambient temperature 40 85 C Tj Junction temperature 40 100 C The temperature rise from ambient to junction is package specific See Table 48 on page 57 You must limit the power consumption to comply with this requirement DC Electrical Characteristics DC Chip Level Specifications Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 11 DC Chip Level Specifications Symbol Description Min Typ Max Units Notes Vpp Supply voltage 24 5 25 V See DC POR and LVD specifications Table 26 on page 35 Ipp Supply current 5 8 mA Conditions are Vpp 5 0 V Ta 25 C CPU 3 MHz SYSCLK doubler disabled VC1 1 5 MHz VC2 93 75 k
113. ted in footnote 1 Load is 5 mA SMP trip voltage is set to 3 25 V E gt Efficiency S Fpump Switching freguency 1 3 MHz DCpump Switching duty cycle 50 Note 11 L4 2 mH inductor C4 10 mF capacitor D4 Schottky diode See Figure 10 Document Number 38 12028 Rev V Page 26 of 71 CY8C24123A CY8C24223A CY8C24423A 4 YPRESS PERFORM Figure 10 Basic Switch Mode Pump Circuit V Document Number 38 12028 Rev V Page 27 of 71 CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM DC Analog Reference Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ta lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 24 V to 3 0 V and 40 C lt Ta x 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only The guaranteed specifications for RefHI and RefLo are measured through the Analog Continuous Time PSoC blocks The power levels for RefHi and RefLo refer to the Analog Reference Control register AGND is measured at P2 4 in AGND bypass mode Each Analog Continuous Time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local AGND buffer Reference control power can be set to medium or high unless otherwise noted Note Avoid using P2 4
114. the two states The basic programmable opamp circuits These are SC switched capacitor and CT continuous time blocks These blocks can be interconnected to provide ADCs DACs multi pole filters gain stages and much more A device that changes an analog signal to a digital signal of corresponding magnitude Typically an ADC converts a voltage to a digital number The digital to analog DAC converter performs the reverse operation A series of software routines that comprise an interface between a computer application and lower level services and functions for example user modules and libraries APIs serve as building blocks for programmers that create software applications A signal whose data is acknowledged or acted upon immediately irrespective of any clock signal A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE to produce a zero temperature coefficient ideally reference 1 The frequency range of a message or information processing system measured in hertz 2 The width of the spectral region over which an amplifier or absorber has substantial gain or loss it is sometimes represented more specifically as for example full width at half maximum Page 62 of 71 ma CY8C24123A at CY8C24223A CYPRESS CY8C24423A PERFORM Glossary continued bias 1 Asystematic deviation of a value from a reference value 2 The amount
115. ump7 _ VM 2 0 111b 4 89 5 00 5 12 V Notes 12 Always greater than 50 mV above Vppor PORLEV 00 for falling supply 13 Always greater than 50 mV above Vppor PORLEV 01 for falling supply 14 Always greater than 50 mV above V ypo 15 Always greater than 50 mV above V vp3 Document Number 38 12028 Rev V Page 35 of 71 CY8C24123A E CY8C24223A CYPRESS CY8C24423A PERFORM DC Programming Specifications Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75 V to 5 25 V and 40 C lt Ty lt 85 C 3 0 V to 3 6 V and 40 C lt Ta lt 85 C or 2 4 V to 3 0 V and 40 C lt Ta lt 85 C respectively Typical parameters are measured at 5 V 3 3 V and 2 7 V at 25 C and are for design guidance only Table 27 DC Programming Specifications Symbol Description Min Typ Max Units Notes Vppp Vpp for programming and erase 4 5 5 5 5 V MN uncti Uire ments of external programmer tools Vppiv Low Vpp for verify 24 2 5 2 6 V This specification applies to the functional require ments of external programmer tools Vppuv High Vpp for verify 5 1 5 2 5 3 V This specification applies to the functional require ments of external programmer tools VppwrITe Supply voltage for flash write operation 2 7 5 25 V This specification applies to this device when it is executing internal flash
116. ur designs with the integrated debug environment including in circuit emulation and standard software debug features PSoC Designer includes m Application editor graphical user interface GUI for device and user module configuration and dynamic reconfiguration m Extensive user module catalog m Integrated source code editor C and assembly m Free C compiler with no size restrictions or time limits m Built in debugger m In circuit emulation m Built in support for communication interfaces n Hardware and software I2C slaves and masters a Full speed USB 2 0 aUp to four full duplex universal asynchronous receiver transmitters UARTs SPI master and slave and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP Windows Vista and Windows 7 PSoC Designer Software Subsystems Design Entry In the chip level view choose a base device to work with Then select different onboard analog and digital components that use the PSoC blocks which are called user modules Examples of user modules are analog to digital converters ADCs digital to analog converters DACs amplifiers and filters Configure the user modules for your chosen application and connect them to each other and to the proper pins Then generate your project This prepopulates your project with APIs and libraries that you can use to program your application The tool also supports easy development of multiple configurat
117. ut XRES Active high external reset with internal pull down 19 I O P2 0 Direct switched capacitor block input 20 I O P2 2 Direct switched capacitor block input 21 I O P2 4 External AGND 22 I O P2 6 External VREF 23 I O l PO 0 Analog column mux input 24 I O PO 2 Analog column mux input 25 NC No connection Pin must be left floating 26 I O PO 4 Analog column mux input 27 I O PO 6 Analog column mux input 28 Power Vpp Supply voltage 29 I O PO 7 Analog column mux input 30 I O I O PO 5 Analog column mux input and column output 31 I O I O PO 3 Analog column mux input and column output 32 I O PO 1 Analog column mux input LEGEND A Analog Input and O Output Notes 7 The center pad on the QFN package must be connected to ground Vss for best mechanical thermal and electrical performance If not connected to ground it must be electrically floated and not connected to any other signal 8 These are the ISSP pins which are not high Z at POR See the PSoC Technical Reference Manual for details Document Number 38 12028 Rev V Page 13 of 71 PERFORM 56 Pin Part Pinout The 56 pin SSOP part is for the CY8C24000A On Chip Debug OCD PSoC device Note This part is only used for in circuit debugging It is NOT available for production Table 6 56 Pin SSOP OCD
118. w VREFHI Ref High Vpp Vpp 0 036 Vpp 0 002 Vbp V Opamp bias low VAGND AGND Vpp 2 Vpp 2 0 184 Vpp 2 0 001 Vpp 2 0 159 V VREFLO Ref Low Vss Vss Vss 0 001 Vss 0 009 V Document Number 38 12028 Rev V Page 33 of 71 CY8C24123A f PERFORM Table 24 2 7 V DC Analog Reference Specifications continued continued Reference Reference Power ARF_CR SICUL ON Symbol Reference Description Min Typ Max Units 5 3 Settings 0b011 All power settings Not allowed at 2 7 V 0b100 All power settings Not allowed at 2 7 V 0b101 All power settings Not allowed at 2 7 V 0b110 RefPower high VREFHI Ref High 2 x Bandgap Not allowed Not allowed Not allowed V Opamp bias high VAGND AGND Bandgap 1 160 1 302 1 340 V VREFLO Ref Low Vss Vss Vss 0 007 Vss 0 025 V RefPower high VREFHI Ref High 2 x Bandgap Not allowed Not allowed Not allowed V Opamp bias low VAGND AGND Bandgap 1 160 1 301 1 338 V VREFLO Ref Low Vss Vss Vss 0 004 Vss 0 017 V RefPower medium VREFHI Ref High 2 x Bandgap Not allowed Not allowed Not allowed V Opamp bias high VAGND AGND Bandgap 1 160 1 301 1 338 V VREFLO Ref Low Vss Vss Vss 0 003 Vss 0 013 V RefPower medium Vrefi Ref High 2 x Bandgap Not allowed Not allowed Not allowed V Opamp bias low F Vono AGND
119. with 16 selectable thresholds m DACs up to two with 6 to 9 bit resolution m Multiplying DACs up to two with 6 to 9 bit resolution m High current output drivers two with 30 mA drive as a PSoC Core resource m 1 3 V reference as a system resource m DTMF dialer m Modulators m Peak detectors m Many other topologies possible Analog blocks are arranged in a column of three which includes one continuous time CT and two switched capacitor SC blocks as shown in Figure 3 Lmnnannas Dee L pi Interfaceto RefHi gt Reference 4 AGNDIN gt Digital System RefLo Generators 4 Refin AGND 4 0 0 4 Bandgap m Correlators M8C Interface Address Bus Data Bus Etc Document Number 38 12028 Rev V Page 50f 71 CY8C24123A CY8C24223A CYPRESS CY8C24423A PERFORM Additional System Resources System resources some of which are listed in the previous sections provide additional capability useful to complete systems Additional resources include a multiplier decimator switch mode pump low voltage detection and power on reset POR Statements describing the merits of each system resource follow m Digital clock dividers provide three customizable clock frequencies for use in applications The clocks can be r

Cypress Semiconductor Perform CY8C24x94 Specifications

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