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TC1793 Data Sheet

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1. Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AF13 P4 14 V0 A1 Port 4 General Purpose I O Line 14 IN38 l FH IN38 Line of GPTAO IN38 l IN38 Line of GPTA1 T12HRC l CCU60 T13HRC l CCU60 CCPOS2A l CCU61 T4EUDA l GPT120 T4EUDB l GPT121 OUT38 01 OUT38 Line of GPTAO OUT38 02 OUT38 Line of GPTA1 OUT6 O3 OUT6 Line of LTCA2 AD14 P4 15 0 A1 Port 4 General Purpose I O Line 15 IN39 l Qu IN39 Line of GPTAO IN39 l IN39 Line of GPTA1 OUT39 01 OUT39 Line of GPTAO OUT39 02 OUT39 Line of GPTA1 OUT7 O3 OUT7 Line of LTCA2 Port 5 B13 P5 0 0 A1 Port 5 General Purpose I O Line 0 RXDOA l e ASCO Receiver Input Output A T6EUDA l GPT120 T6EUDB l GPT121 RXDOA O1 ASCO Receiver Input Output A OUT72 O2 OUT72 Line of GPTAO OUT72 O3 OUT72 Line of GPTA1 Data Sheet 41 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function A13 P5 1 0 A1 Port 5 General Purpose I O Line 1 TXDO O1 FH ASCO Transmitter Output A OUT73 O2 OUT73 Line of GPTAO OUT73 O3 OUT73 Line of GPTA1 A14 P5 2 0 A2 Port 5 General Purpose I O Line 2 RXD1A l d ASC1 Receiver Input Output A RXD1A O1 ASC1 Receiver Input Output A OUT74 O2
2. Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function A10 P3 14 V0 A1 Port 3 General Purpose I O Line 14 IN22 l FH IN22 Line of GPTAO IN22 l IN22 Line of GPTA1 IN22 l IN22 Line of LTCA2 T13HRE l CCU63 OUT22 O1 OUT22 Line of GPTAO OUT22 O2 OUT22 Line of GPTA1 OUT22 O3 OUT22 Line of LTCA2 B9 P3 15 l O A1 Port 3 General Purpose I O Line 15 IN23 l A IN23 Line of GPTAO IN23 l IN23 Line of GPTA1 IN23 l IN23 Line of LTCA2 OUT23 O1 OUT23 Line of GPTAO OUT23 O2 OUT23 Line of GPTA1 OUT23 O3 OUT23 Line of LTCA2 Port 4 AD10 P4 0 0 A1 Port 4 General Purpose I O Line 0 IN24 l PU IN24 Line of GPTAO IN24 l IN24 Line of GPTA1 IN24 l IN24 Line of LTCA2 MRST2A l SSC2 Master Receive Input A Master Mode OUT24 O1 OUT24 Line of GPTAO OUT24 O2 OUT24 Line of GPTA1 MRST2 O3 SSC2 Slave Transmit Output Slave Mode Data Sheet 35 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AE10 P4 1 I O A1 Port 4 General Purpose I O Line 1 IN25 l FH IN25 Line of GPTAO IN25 l IN25 Line of GPTA1 IN25 l IN25 Line of LTCA2 MTSR2A l SSC2 Slave Receive Input A Slave Mode
3. Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B10 P3 6 V0 A1 Port 3 General Purpose I O Line 6 IN14 l FH IN14 Line of GPTAO IN14 l IN14 Line of GPTA1 IN14 l IN14 Line of LTCA2 T13HRE l CCU62 T6EUDB l GPT120 T6EUDA l GPT121 OUT14 01 OUT14 Line of GPTAO OUT14 O2 OUT14 Line of GPTA1 OUT 14 O3 OUT14 Line of LTCA2 C9 P3 7 VO A1 Port 3 General Purpose I O Line 7 IN15 l PE IN15 Line of GPTAO IN15 l IN15 Line of GPTA1 IN15 l IN15 Line of LTCA2 OUT15 01 OUT15 Line of GPTAO OUT15 02 OUT15 Line of GPTA1 OUT15 O3 OUT15 Line of LTCA2 D10 P3 8 l O A1 Port 3 General Purpose I O Line 8 IN16 l ia IN16 Line of GPTAO IN16 l IN16 Line of GPTA1 IN16 l IN16 Line of LTCA2 T13HRE l CCU61 OUT16 O1 OUT16 Line of GPTAO OUT16 O2 OUT16 Line of GPTA1 OUT16 O3 OUT16 Line of LTCA2 Data Sheet 32 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C11 P3 9 V0 A1 Port 3 General Purpose I O Line 9 IN17 l FH IN17 Line of GPTAO IN17 l IN17 Line of GPTA1 IN17 l IN17 Line of LTCA2 OUT17 O1 OUT17 Line of GPTAO OUT17 O2 OUT17 Line of GPTA1 OUT 17 O3 OUT17 Line of LTCA2 C10 P3 10 I O A1 Port 3 General Purpos
4. Address Command Burst Burst Recovery Next Addr Phase s Phase s Phase s Phase s Phase s Phase s BFCLKI 4 lio lio T ea OS A 23 0 Burst Start Address X Next oh ir S w j ADV mP CS 3 0 CSCOMB j RD RD WR m Iw gt ba I bs gt D 31 0 jj 32 Bit Data Addr 0 K Data Addr 4 D 15 0 Se oe 16 Bit f f Data Addr 0 X Data Addr 2 f zm f 9 Oxi WAIT 1 Output delays are always referenced to BCLKO The reference clock for input characteristics depends on bit EBU BFCON FDBKEN EBU BFCON FDBKEN 0 BFCLKO is the input reference clock EBU BFCON FDBKEN 1 BFCLKI is the input reference clock EBU clock feedback enabled BurstRDWR 4 vsd Figure 29 EBU Burst Mode Read Write Access Timing Data Sheet 1 70 V 1 2 2014 05 Cinfineon Tels Electrical ParametersAC Parameters 5 3 12 4 EBU Arbitration Signal Timing Vss 0 Vi Vpp 1 5 V x 596 Vppggu 2 5 V 5 and 3 3 V x 5 Class B pins T 40 C to 125 C C 35 pF Table 45 EBU EBU Arbitration Timings Parameter Symbol Values Unit Note Min Typ Max Test Condition Output delay from ta CC 3 ns BFCLKO rising edge Data setup to BFCLKO tog SR 8 ns falling edge Data hold from BFCLKO t SR 2 B ns falling edge 1 Not subject to production test verified by design chara
5. Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function V25 P13 8 0 B Port 13 General Purpose I O Line 8 AD8 l FB EBU Address Data Bus Line 8 OUT96 O1 OUT96 Line of GPTAO OUT96 O2 OUT96 Line of GPTA1 OUT88 O3 OUTS88 Line of LTCA2 AD8 O EBU Address Data Bus Line 8 U24 P13 9 0 B Port 13 General Purpose I O Line 9 AD9 l Ja EBU Address Data Bus Line 9 OUT97 01 OUT97 Line of GPTAO OUT97 O2 OUT97 Line of GPTA1 OUT89 O3 OUT89 Line of LTCA2 AD9 O EBU Address Data Bus Line 9 Y26 P13 10 I O B Port 13 General Purpose I O Line 10 AD10 l EM EBU Address Data Bus Line 10 OUT98 O1 OUT98 Line of GPTAO OUT98 O2 OUT98 Line of GPTA1 OUT90 O3 OUT90 Line of LTCA2 AD10 O EBU Address Data Bus Line 10 AA26 P13 11 0 B Port 13 General Purpose I O Line 11 AD11 l PU EBU Address Data Bus Line 11 OUT99 O1 OUT99 Line of GPTAO OUT99 O2 OUT99 Line of GPTA1 OUT91 O3 OUT91 Line of LTCA2 AD11 O EBU Address Data Bus Line 11 Data Sheet 67 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function W25 P13 12 0 B Port 13 General Purpose I O Line 12 AD12 l FH EBU Address Data Bus Line 12 OUT 100 O1 OUT100 Line of GPTAO OUT100 O2 OUT100 Line of GPTA1 OUT92 O3 OUT92
6. Device Package ROJCT ROJCB ROJA Unit Note 1 1 TC1793 PG BGA 416 3 3 4 5 12 1 KIW 1 The top and bottom thermal resistances between the case and the ambient R ar Rrcap are to be combined with the thermal resistances between the junction and the case given above A c Rz cg in order to calculate the total thermal resistance between the junction and the ambient R The thermal resistances between the case and the ambient Ric Rtcag depend on the external system PCB case characteristics and are under user responsibility The junction temperature can be calculated using the following equation T T4 Ryy x Pp where the Rija is the total thermal resistance between the junction and the ambient This total junction ambient resistance Ry can be obtained from the upper four partial thermal resistances Thermal resistances as measured by the cold plate method MIL SPEC 883 Method 1012 1 Data Sheet 174 V 1 2 2014 05 Cinfineon Hs Electrical ParametersPackage and Reliability 5 5 2 Package Outline i ra 2E WreTg c 6000 LASEREDI Figure 31 Package Outlines PG BGA 416 You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products 5 5 3 Quality Declarations Table 48 Quality Parameters Parameter Symbol Values Unit Note Te
7. tears CC 150 ns C 20 pF pin out driver weak 28 ns C 50 pF edge slow pin out driver strong 16 ns C 7 50 pF edge soft pin out driver strong 50 ns C 50 pF pin out driver medium 140 ns C 150 pF pin out driver medium 550 ns Cj 7 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet 107 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 17 Standard Pads Class A1 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Rise time pad type A1 fg4 CC 150 ns C 7 20 pF pin out driver weak 28 ns C 50 pF edge slow pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 7 50 pF pin out driver medium 140 ns C 7 150 pF pin out driver medium 550 ns C 7 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Input high voltage Class Vina 0 6x min V V A1 pads SR Vppp DDP 0 3 3 6 Input low voltage Class Vra 0 3 0 36 x V A1 pads SR Vope Ratio Vil Vih A1 pads V La 0 6 Vinat CC Data Sheet 108 V 1 2 2014 05 Cinfineon
8. 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 200 MHz operation at full temperature range Multiple on chip memories 4 Mbyte Program Flash Memory PFLASH with ECC 192 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 2x8 Kbyte Key Flash 128 Kbyte Data Scratch Pad RAM DSPR 16 Kbyte Instruction Cache ICACHE 32 Kbyte Instruction Scratch Pad RAM PSPR 16 Kbyte Data Cache DACHE 128 Kbyte Memory SRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller 8 Channel Safe DMA SDMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure Data Sheet 6 V 1 2 2014 05 Cinfineon Tene Summary of Features 64 bit Cross Bar Interconnect between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge SFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction Four SSC Guardian SSCG modules one for each SSC Two serial Micro Second Bus interfaces MSC for serial port expansion to external power devices Two High Speed Micro Link interfaces MLI for serial i
9. Figure 10 Testing Waveform Output Delay VLoadt 0 1 V fosse Ma Timing pe Qj Vou 0 1V Reference Vioag 0 1 V a Prs e Vo 0 1 V MCT04880_new Figure 11 Testing Waveform Output High Impedance Data Sheet 137 V 1 2 2014 05 Cinfineon Tel Electrical ParametersAC Parameters 5 3 2 Power Sequencing 5 25V 4 5V n i 4 75V E 3 47V N VAREF 3 3V uu N 3 0V 12 N 1 365V aN 1 3V ay 1 235V TN t Vppe PORST Y 4 gt power power t down fail Power Up 10 vsd Figure 12 5 V 3 3 V 1 3 V Power Up Down Sequence The following list of rules applies to the power up down sequence All ground pins Vss must be externally connected to one single star point in the system Regarding the DC current component all ground pins are internally directly connected At any moment in time to avoid increased latch up risk each power supply must be higher then any lower power supply 0 5 V or VDD5 gt VDD3 3 0 5 V VDD5 gt VDD1 3 0 5 V VDD3 3 gt VDD1 3 0 5 V see Figure 12 The latch up risk is minimized if the I O currents are limited to 20 mA for one pin group AND 100 mA for the completed device I Os AND additionally before power up after power down 1 mA for one pin in inactive mode 0 V on all power supplies During power up and power down the voltage difference between the power supply pins of the same voltage 3
10. reset_beh2 As programmed Figure 13 Power Pad and Reset Timing Data Sheet 141 V 1 2 2014 05 Cinfineon Tels Electrical ParametersAC Parameters 5 3 4 Phase Locked Loop PLL Table 31 PLL SysCIk Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Accumulated Jitter De CC 7 7 ns Modulation frequency Junon SR 50 200 kHz PLL base frequency Jpttpase 50 200 320 MHz CC VCO input frequency frer CC 8 16 MHz VCO frequency range Juco CC 400 720 MHz with inactive modulation 400 600 MHz with active modulation Modulation jitter Jmop CC 2 5 ns Total long term jitter Jor CC 9 5 ns Sum of Dp and Jon Modulation Amplitude MASR 0 2 5 of fuco PLL lock in time t CC 14 200 us N gt 32 14 400 us N lt 32 System frequency Ssysp 0 01 with active deviation CC modulation Phase Locked Loop Operation When PLL operation is enabled and configured the PLL clock fico and with it the SRI Bus clock fag is constantly adjusted to the selected frequency The PLL is constantly adjusting its output frequency to correspond to the input frequency from crystal or clock source resulting in an accumulated jitter that is limited This means that the relative deviation for periods of more than one clock cycle is lower than for a single clock cycle This is especially important for bus cycle
11. Summary of Features Two General Purpose Timer Array Modules GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare 6 modules Two General Purpose 12 Timer Units GPT120 and GPT121 44analog input lines for ADC 4 independent kernels ADCO ADC1 and ADC2 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of feapc clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 8 digital input lines for SENT communication according to the SENT specification J2716 FEB2008 221 digital general purpose I O lines GPIO Digital I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Buses Dedicated Emulation Device chip available TC1793ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL and PLL ERAY Flexible CRC Engine FCE IEEE 802 3 CRC32 ethernet polynomial 0xX82608EDB CRC kernel 0 CRC32C Castagnoli 0xD419CC15 CRC k
12. 5 6 Electrical ParametersGeneral Parameters Voltage overshoot to 6 5V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h Voltage overshoot to 4 0V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h This parameter is valid under the assumption the PORST signal is constantly at low level during the power up power down of Vppp 5 1 5 1 Extended Range Operating Conditions The following extended operating conditions are defined 1 3V 596 lt Vop Vpposc Vpppr Vppar lt 1 3V 7 5 overvoltage condition limited to 10000 hours duration cumulative in lifetime due to the reliability reduction of the chip caused by the overvoltage stress 1 3V 7 596 lt Vpp Vpposc Vpper Vppar lt 1 3V 1096 overvoltage condition limited to 1000 hours duration cumulative in lifetime due to the reliability reduction of the chip caused by the overvoltage stress 3 3V 5 lt Vopp Voposca Vpppra Voorts Voome Vopegu 3 3V 10 overvoltage condition limited to 1000 hours duration cumulative in lifetime due to the reliability reduction of the chip caused by the overvoltage stress Table 14 Pin Groups for Overload Short Circuit Current Sum Parameter Group Pins
13. AC20 AB23 V23 P23 E23 D24 C25 B26 D16 D9 H4 R4 Data Sheet 83 V 1 2 2014 05 Cinfineon Table 2 TC1793 PinningTC1793 Pin Configuration Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AC16 AD16 AE16 AF16 D22 C23 B24 A25 D14 D7 K4 Vopp Port Power Supply 3 3V H23 H24 H25 H26 M23 T23 Y23 AC18 AC22 VDDEBU EBU Port Power Supply 1 8V 2 5V 3 3V R1 VopsB Emulation Stand by SRAM Power Supply 1 3V Emulation device only Note This pin is N C in a productive device AC10 AC17 AC19 AC23 W23 R23 L23 D23 C24 B25 A26 D15 D8 J4 T4 Digital Ground outer balls Data Sheet 84 V 1 2 2014 05 Cinfineon Table 2 TC1793 PinningTC1793 Pin Configuration Pin Definitions and Functions cont d Pin Symbol Cirl Type Function K10 K11 K12 K13 K14 K15 K16 K17 Vs S Digital Ground center balls L10 L11 L12 L13 L14 L15 L16 L17 Digital Ground center balls cont d M10 M11 M12 M13 M14 M15 M16 M17 Digital Ground center balls cont d N10 N11 N12 N13 N14 N15 N16 N17 Digital Ground center balls cont d Data Sheet 85 V 1 2 2014 05 Cinfineon Table 2 TC1793 PinningTC1793 Pin Configuration Pin Definitions and Funct
14. FM PLL PLL ERAY System Peripheral Bus SPB TC1793 Abbreviations ICACHE Instruction Cache DCACHE Data Cache PSPR Program ScratchPad RAM DSPR Data ScratchPad Data RAM BROM Boot ROM PFlash Program Flash DFlash Data Flash PRAM Parameter RAM in PCP CMEM Code RAM in PCP SRI Cross Bar XBar_SRI On Chip Bus Slave Interface On Chip Bus Master Interface Ext FADC Supply Figure 3 Data Sheet Block Diagram V 1 2 2014 05 e Infineon ERE Pinning 3 Pinning Figure 4 is showing the TC1793 Logic Symbol Alternate Functions PORST T 1 TESTNODE 97 port 0 GPTA HWCFG E RAY General Control ae 16 GPT12 ESRO al n paki GPTA MLIO ERU SSC1 9 SSC3 CCU6 GPT12 ESR1 14 Z Port 2 GPTA SSC0 SSC1 TRST 46 TCK DAPO K Z Port 3 GPTA CCU6 GPT12 a 16 ocps TDUBRKIN 4 K 7Pot4 gt GPTA SSC2 CCU6 GPT12 JTAG Control BRKOUT ees BUE ASCO ASC1 MSCO MSC1 TDO BRKOUT 2 LVDS MLIO CCU6 GPT12 DAP2 BRKIN 12 ASCO ASC SSC1 CANI KZ Port 6 4 Sie KE j E RAY CCU6 GPT12 K Z gt Port 7 ERU ADC Mux SSC3 XTAL1 8 gt Pot 8 MLI1 GPTA SENT XTAL2 CCU6 GPT12 V 15 MSCO MSC1 GPTA panes K Pot9 f SENT CCUG GPTI2 Voposcs 6 Oscillator Vesose K Port 10 SSO 16 Vss Z gt Port 11 gt EBU Voopr 8 VopPraca gt Z gt Port 12 EBU 16 Vovesu 2 Z Port 13 GPTA EBU 11 16 Vooe 13 7 Port 14 GPTA E
15. Multiple on chip memories 4 Mbyte Program Flash Memory PFLASH with ECC 192 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 2 x 8 Kbyte Key Flash 128 Kbyte Data Scratch Pad RAM DSPR 16 Kbyte Instruction Cache ICACHE 32 Kbyte Instruction Scratch Pad RAM PSPR 16 Kbyte Data Cache DACHE 128 Kbyte Memory SRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller 8 Channel Safe DMA SDMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Cross Bar Interconnect between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge SFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction Four SSC Guardian SSCG modules one for each SSC Two serial Micro Second Bus interfaces MSC for serial port expansion to external power devices Two High Speed Micro Link interfaces MLI for serial inter processor communication Data Sheet 1 V 1 2 2014 05 Cinfineon TES Summary of Features One External Bus Interface EBU supporting different memories asynchronous memories e g SRAM peripheral d
16. 4 S erase program cycles per UCB Data Sheet 172 V 1 2 2014 05 Infineon TC1793 Electrical ParametersFlash Memory Parameters Table 46 FLASH32 Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Wake Up time twy CC i 270 us DFlash wait state WSpe 50nsx configuration CC fesi PFlash wait state WS pF 26 ns x configuration CC fesi 1 Incase of wordline oriented defects see robust EEPROM emulation in the User s Manual this erase time can increase by up to 100 2 reprogramming takes additiona 2 reprogramming takes additiona 23088 5 ms 5 ms Storage and inactive time included In case the Program Verify feature detects weak bits these bits will be programmed up to twice more Each In case the Program Verify feature detects weak bits these bits will be programmed once more The Only valid when a robust EEPROM emulation algorithm is used For more details see the User s Manual At average weighted junction temperature 7 100 C or the retention time at average weighted temperature of T 110 C is minimum 10 years or the retention time at average weighted temperature of 7 150 C is minimum 0 7 years Data Sheet 173 V 1 2 2014 05 Infineon Hs Electrical ParametersPackage and Reliability 5 5 Package and Reliability 5 5 1 Package Parameters Table 47 Thermal Characteristics of the Package
17. ERE ee ayav x r cda ex 5 103 5 2 2 Analog to Digital Converters ADCX SK kk KK RR KK KK SR 5 121 5 2 3 Fast Analog to Digital Converter FADC 00 5 126 5 2 4 Oscillator PIRS g ise erre uum Eya A Lb dae Pe eee IERTE 5 130 5 2 5 Temperature Sensor kk kk kk KK KK KK KK KIRR KK K KK KK KK KK 5 131 5 2 6 Power Supply Current kk kk kk KK KK KK KK KK KK KK KK KK KK 5 132 5 2 6 1 Calculating the 1 3 V Current Consumption 5 135 5 3 AC Parameters 4 4 saya a l ya a a a l ya eens 5 137 5 3 1 Testing Waveforms ss ak kla a kala deka al klan a tte 5 137 5 3 2 Power Sequencing k kk kk kk kk KK KK KK tee 5 138 5 3 3 Power Pad and Reset Timing 220000 ee ee eee 5 140 5 3 4 Phase Locked Loop PLL ck kaka a a ak kul ak kak ka eee 5 142 5 3 5 ERAY Phase Locked Loop ERAY_PLL W K KK 5 145 5 3 6 JTAG Interface TIMIN eri a kk al salna a e 5 146 5 3 7 DAP Interface Timing ik kak kc a kk a kl kn k kk a a a a ka A ka 5 148 5 3 8 Micro Link Interface MLI Timing sese 5 149 5 3 9 Micro Second Channel MSC Interface Timing 5 152 5 3 10 SSC Master Slave Mode Timing KK RR RR KK KS 5 154 5 3 11 ERAY Interface Timing kk kk kk KK KK KK tees 5 157 5 3 12 EBU TIMINGS ce A uk alaya an lk yal E PR Qe l wats 5 159 5 3 12 1 BFCLKO Output Clock Timing 0 00 eee eee 5 159 5 3
18. IN51 l FU IN51 Line of GPTAO IN51 l IN51 Line of GPTA1 CC62INB l CCU62 CC62INA l CCU63 CC62 O1 CCU63 OUT51 O2 OUT51 Line of GPTA1 FCLP1B O3 MSC1 Clock Output D18 P9 4 0 A2 Port 9 General Purpose I O Line 4 IN52 l PU IN52 Line of GPTAO IN52 l IN52 Line of GPTA1 COUT60 O1 CCU63 OUT52 O2 OUT52 Line of GPTA1 EN03 O3 MSCO Device Select Output 3 Data Sheet 55 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function D19 P9 5 I O A2 Port 9 General Purpose I O Line 5 IN53 l FH IN53 Line of GPTAO IN53 l IN53 Line of GPTA1 SENT1 l SENT Digital Input COUT61 01 CCU63 OUT53 O2 OUT53 Line of GPTA1 ENO2 O3 MSCO Device Select Output 2 C19 P9 6 I O A2 Port 9 General Purpose I O Line 6 IN54 l EH IN54 Line of GPTAO IN54 l IN54 Line of GPTA1 SENT3 l SENT Digital Input OUT54 01 OUT54 Line of GPTAO SENT3 02 SENT Digital Output ENO1 O3 MSCO Device Select Output 1 D20 P9 7 0 A2 Port 9 General Purpose I O Line 7 IN55 l PU IN55 Line of GPTAO IN55 l IN55 Line of GPTA1 SENT4 l SENT Digital Input OUT55 01 OUT55 Line of GPTAO SENT4 02 SENT Digital Output SOPOB O3 MSCO serial Data Output C20 P9 8 0 A2 Port 9 General Purpose I O Line 8 SENT6 l ER SENT Digital Input COUT62 O1 CCU63 SENT6 02 SENT Di
19. MRSTG2A l SSC Guardian 2 Master Receive Input A Master Mode OUT25 01 OUT25 Line of GPTAO OUT25 O2 OUT25 Line of GPTA1 MTSR2 O3 SSC2 Master Transmit Output Master Mode AD11 P42 V0 A1 Port 4 General Purpose I O Line 2 IN26 l PU IN26 Line of GPTAO IN26 l IN26 Line of GPTA1 IN26 l IN26 Line of LTCA2 SCLK2 l SSC2 Input OUT26 01 OUT26 Line of GPTAO OUT26 02 OUT26 Line of GPTA1 SCLK2 O3 SSC2 Output AE11 P4 3 I O A1 Port 4 General Purpose I O Line 3 IN27 l EM IN27 Line of GPTAO IN27 l IN27 Line of GPTA1 IN27 l IN27 Line of LTCA2 OUT27 01 OUT27 Line of GPTAO OUT27 O2 OUT27 Line of GPTA1 SLSO20 O3 SSC2 Output Data Sheet 36 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AC12 P4 4 I O A1 Port 4 General Purpose I O Line 4 IN28 l FH IN28 Line of GPTAO IN28 l IN28 Line of GPTA1 IN28 l IN28 Line of LTCA2 OUT28 01 OUT28 Line of GPTAO OUT28 O2 OUT28 Line of GPTA1 SLSO21 03 SSC2 Output AD12 P4 5 I O A1 Port 4 General Purpose I O Line 5 IN29 l EH IN29 Line of GPTAO IN29 l IN29 Line of GPTA1 IN29 l IN29 Line of LTCA2 OUT29 O1 OUT29 Line of GPTAO OUT29 O2 OUT29 Line of GPTA1 SLSO22 O3 SSC2 Output AF10 P4 6 0 A1 Port 4 General Purpose I O Line 6 IN30 l PU IN30 Line of GPTAO IN30 l IN30 Line of GPTA1
20. PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function D17 P5 8 V0 F Port 5 General Purpose I O Line 8 CC62INA l FH CCU62 CC62INB l CCU63 SONO O1 MSCO Differential Driver Serial Data Output Negative OUT80 O2 OUTS80 Line of GPTAO CC62 O3 CCU62 C16 P5 9 I O F Port 5 General Purpose I O Line 9 SOPOA O1 o MSCO Differential Driver Serial Data Output Positive A OUT81 O2 OUTS81 Line of GPTAO COUT60 O3 CCU62 C17 P5 10 I O F Port 5 General Purpose I O Line 10 FCLNO O1 FH MSCO Differential Driver Clock Output Negative OUT82 O2 OUT82 Line of GPTAO COUT61 O3 CCU62 C18 P5 11 0 F Port 5 General Purpose I O Line 11 FCLPOA O1 PU MSCO Differential Driver Clock Output Positive A OUT83 O2 OUTS 3 Line of GPTAO COUT62 O3 CCU62 A16 P5 12 l O F Port 5 General Purpose I O Line 12 SON1 O1 i MSC1 Differential Driver Serial Data Output Negative OUT84 O2 OUT84 Line of GPTAO OUT84 O3 OUT84 Line of GPTA1 Data Sheet 44 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B16 P5 13 V0 F Port 5 General Purpose I O Line 13 SOP1A O1 FB MSC1 D
21. add identification registers for new product option rework first sentence for chapter 5 3 reduce min value for f for both PLLs Split fico for system PLL into two conditions add for MLI and SSC parameter valid strong driver medium edge only add footnote 5 for SSC parameters add parameters t45 tg t47 and t49 to the EBU The following changes where done between Version 1 1 and 1 1 1 of this document update the incoorect CHIPID values for copper and non copper bond options product SAK TC 1793N 512F270EB not longer supported and replaced by SAK TC1793N 512F270EF The following changes where done between Version 1 1 1 and 1 2 of this document remove the following product options SAK TC1793F 512F270EB e change Vs from 2 1V to 1 9V in table 23 e change fg from 100ns to 200ns in table 42 change t4 from 100ns to 200ns in table 42 e extend Kovan conditon from Joys 0 mA Joy2 1 mA to Joys 0 mA Joy2 2 mA change fg from 4ns to 2ns in table 43 change fg from 4ns to 2ns in table 43 Data Sheet 4 V 1 2 2014 05 Cinfineon Ios History change tz parameter description from Data output delay to WR rising edge deviation from the ideal programmed value to Data output delay to WR falling edge deviation from the ideal programmed value in table 43 Data Sheet 5 V 1 2 2014 05
22. medium 2 4 Top 2 mA pin out driver medium Vope 0 4 Igy2 400 uA pin out driver weak 2 4 Toy 500 uA pin out driver weak Output voltage low class A1 pads Voas CC 0 4 Ig 2 mA pin out driver medium 0 4 lo lt 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 17 Standard Pads Class A1 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for A1 HYSA O 1x V pads 1 CC Vppp Input Leakage Current loza 1000 1000 nA Class A1 CC On Resistance of the Rosonw 450 600 Ohm gj 0 5 mA class A1 pad weak CC P MOS driver 210 340 Ohm g 0 5 mA N MOS Data Sheet 106 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 17 Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition On Resistance of the class A1 pad medium driver Rosonm CC 155 Ohm Top 2 mA P_MOS 110 Ohm lo lt 2 MA N_MOS On Resistance of the class A1 pad strong driver Rpson1 CC 100 Ohm Ig 2 mA P MOS 80 Ohm Ig 2 mA N MOS Fall time pad type A1
23. pads CC Vbpesu 0 1x V Vppepu 3 3 V VopeBu Input Leakage Current lozg CC 6000 6000 nA else class B pads 3000 3000 nA Vppegu 2 0 6 V lt Vi V DDEBU 2 0 6 V Ratio between low and Vig 0 6 high input threshold Ving CC On Resistance of the Rpsoww 450 600 Ohm Joy gt 0 5 mA class B pad weak driver CC P MOS 210 340 Ohm 7g 0 5 mA N MOS On Resistance of the RpsowM 155 Ohm Top 2 mA class B pad medium CC P MOS driver S z 110 Ohm g 2 mA N MOS Data Sheet 115 V 1 2 2014 05 Cinfineon Table 19 TC1793 Electrical ParametersDC Parameters Standard Pads Class B cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition On Resistance of the class B pad strong driver Rosone CC 28 Ohm Top 2 mA P_MOS 22 Ohm lo lt 2 MA N_MOS Fall time class B pads edge sharp pin out driver strong 2 trg CC 3 7 ns C 35 pF Vopegu 2 375 Vbpegu lt 2 625 3 0 ns C 35 pF Vopeggu 3 13 Vbpegu lt 3 47 4 6 ns C 50 pF Vopegus 2 375 Vbpegu lt 2 625 3 7 ns C 50 pF Vppgsgu gt 3 13 Vbpegu lt 3 47 9 0 ns C 100 pF Vosesus 2 375 Vppegu lt 2 625 7 5 ns C 100 pF Vopegu 3 13 Vbpegu lt 3 47 Data Sheet 116 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC
24. wc Qnfineon Never stop thinking 32 Bit Microcontroller TC1793 32 Bit Single Chip Microcontroller Data Sheet V 1 2 2014 05 Microcontrollers Edition 2014 05 Published by Infineon Technologies AG 81726 Munich Germany 2014 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device
25. 0 0001 Toys 0 mA for analog inputs negative CC Iov 2 mA analog pad 5 0 V Overload coupling factor Kovap 5 0 0000 Toys 3 mA for analog inputs positive CC 1 lov gt 0 mA analog pad 5 0 V CPU Frequency fceu SR 270 MHz SAK TC1793F 512F 270EB SAK TC1793F 512F 270EF SAK TC1793N 512F 270EF SAK TC1793S 512F 270EF 200 MHz SAK TC1793F 512F 200EF SAK TC1793F 512F 200EB Data Sheet 96 V 1 2 2014 05 Cinfineon Table 13 TC1793 Electrical ParametersGeneral Parameters Operating Conditions Parameters cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Modulated fopu J CPU_mod SR ulated 270 MHz SAK TC1793F 512F 270EB SAK TC1793F 512F 270EF SAK TC1793N 512F 270EF SAK TC1793S 512F 270EF 200 MHz SAK TC1793F 512F 200EF SAK TC1793F 512F 200EB FPI bus frequency frp SR 100 MHz Modulated f p EPI modul ated SR 100 2 MA MHz MA modulatio n amplitude FSI frequency Jes SR 150 MHz Modulated f s Fs modu T ated SR 150 2 MA MHz MA modulatio n amplitude PCP Frequency fece SR 200 MHz Modulated fpcp J PCP_mod ulated SR 200 2 MA1 MHz MA modulatio n amplitude SRI Frequency Jsn SR 270 MHz SAK TC1793F 512F 270EB SAK TC1793F 512F
26. 11 l O A1 Port 2 General Purpose I O Line 11 IN3 l a IN3 Line of GPTAO IN3 l IN3 Line of GPTA1 IN3 l IN3 Line of LTCA2 OUT3 01 OUT3 Line of GPTAO OUT3 02 OUT3 Line of GPTA1 OUT3 03 OUT3 Line of LTCA2 Data Sheet 26 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C4 P2 12 I O A1 Port 2 General Purpose I O Line 12 IN4 l FH IN4 Line of GPTAO INA l IN4 Line of GPTA1 IN4 l IN4 Line of LTCA2 T12HRB l CCU62 CCPOSOA l CCU63 T2INB l GPT120 T2INA l GPT121 OUT4 01 OUT4 Line of GPTAO OUT4 02 OUT4 Line of GPTA1 OUT4 O3 OUT4 Line of LTCA2 A3 P2 13 0 A1 Port 2 General Purpose I O Line 13 IN5 l d IN5 Line of GPTAO IN5 l IN5 Line of GPTA1 IN5 l IN5 Line of LTCA2 OUT5 O1 OUT5 Line of GPTAO OUT5 O2 OUT5 Line of GPTA1 OUT5 O3 OUT5 Line of LTCA2 Data Sheet 27 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B4 P2 14 V0 A1 Port 2 General Purpose I O Line 14 ING l PU IN6 Line of GPTAO IN6 l IN6 Line of GPTA1 ING l IN6 Line of LTCA2 CCPOSOA l CCU60 T12HRB l CCU61
27. 270EF SAK TC1793N 512F 270EF SAK TC1793S 512F 270EF 200 MHz SAK TC1793F 512F 200EF SAK TC1793F 512F 200EB Data Sheet 97 V 1 2 2014 05 Cinfineon Tel Electrical ParametersGeneral Parameters Table 13 Operating Conditions Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Modulated fen sRI modu 270 MHz SAK TC1793F ated OR 512F 270EB SAK TC1793F 512F 270EF SAK TC1793N 512F 270EF SAK TC1793S 512F 270EF 200 MHz SAK TC1793F 512F 200EF SAK TC1793F 512F 200EB Inactive device pin current 7p SR 1 1 mA All power supply voltages Vppx 9 Short circuit current of Igg SR 5 5 mA digital outputs Absolute sum of short Xlcp 100 mA circuit currents of the CC device Absolute sum of short Lsc pe 20 mA circuit currents per pin CC group Ambient Temperature T SR 40 125 C Junction temperature T SR 40 150 C Core Supply Voltage Vbo SR 1 17 1 3 1 439 V for duration limitation see Section 5 1 5 1 EBU supply voltage Vppepu 3 135 3 3 3479 IV BR 2 375 25 2625 V Flash supply voltage 3 3V Vppr a 2 97 33 3 639 V for duration SR limitation see Section 5 1 5 1 Data Sheet 98 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersGeneral Parameters Table 13 Operating Conditions
28. 6 l O B Port 11 General Purpose I O Line 6 Reserved O1 PB Reserved O2 Reserved O3 A6 O EBU Address Bus Line 6 K23 P11 7 0 B Port 11 General Purpose I O Line 7 Reserved O1 is Reserved O2 Reserved O3 AT O EBU Address Bus Line 7 M26 P11 8 I O B Port 11 General Purpose I O Line 8 Reserved O1 u Reserved O2 Reserved O3 A8 O EBU Address Bus Line 8 M25 P11 9 l O B Port 11 General Purpose I O Line 9 Reserved O1 FE Reserved O2 Reserved O3 A9 O EBU Address Bus Line 9 Data Sheet 61 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function M24 P11 10 0 B Port 11 General Purpose I O Line 10 Reserved O1 FB Reserved O2 Reserved O3 A10 O EBU Address Bus Line 10 L24 P11 11 l O B Port 11 General Purpose I O Line 11 Reserved O1 PB Reserved O2 Reserved O3 A11 O EBU Address Bus Line 11 N26 P11 12 0 B Port 11 General Purpose I O Line 12 Reserved O1 is Reserved O2 Reserved O3 A12 O EBU Address Bus Line 12 N23 P11 13 VO B Port 11 General Purpose I O Line 13 Reserved O1 u Reserved O2 Reserved O3 A13 O EBU Address Bus Line 13 N24 P11 14 I O B Port 11 General Purpose I O Line 14 Reserved O1 FE Reserved O2 Reserved O3 A14 O EBU Addres
29. CC Converter clock Franc 1 100 MHZ feapc frp SR Conversion time to CC 21 1 For 10 bit Jeane conversion Input resistance of the Rean 100 200 kOh analog voltage path Rn CC m Rp Settling time of a channel tse CC 5 us amplifier after changing ENN or ENP Analog input voltage V ANF VeAGND Vopwr V range SR Data Sheet 127 V 1 2 2014 05 Infineon TC1793 Table 26 FADC Parameters cont d Electrical ParametersDC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Analog reference ground VrAGwp Vssar Vssar V SR 0 05 0 05 Analog reference voltage Vearer 3 0 3 63 V SR 9 This value applies in power down mode M No missing codes 2 minimium once per week as of the pulses does not exceed 1 h 2 overshoots The offser error voltage drifts over the whole temperature range maximum 3LSB Calibration should be preformed at each power up In case of a continous operation it should be performed Voltage overshoot to 4V is permissible provided the pulse duration is less than 100 us and the cumulated sum A running conversion may become inexact in case of violating the nomal operating conditions voltage The calibration procedure should run after each power up when all power supply voltages and the reference voltage have stabilized Data Sheet 128 V 1 2 2014 05 Cinfineon Har Electrical
30. Control Bitfield ADDRC AHOLDC RDWAIT DATAC RDRECOVC ADDRC 1 31 0 15 V V Next DV loo New Addr Phase Recovery Phase opt 0 15 1 15 7 ea PY tls d DV bp CSCOMB pv t pv b bs bs J PV b7 DV bs Temen MRIW X DV bo pv programmed value Tesu c x sum correponding bitfield values new_DemuxWR_Async_10 vsd Figure 28 Demultiplexed Write Access 5 3 12 3 EBU Burst Mode Access Timing Vss 0 ViVpp 1 3 V 596 Vopepy 2 5 V 5 and 3 3 V 5 Class B pins C 2 35 pF Data Sheet 168 V 1 2 2014 05 Infineon TC1793 Table 44 EBU Burst Read Timings Electrical ParametersAC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Output delay from tig CC 2 2 ns BFCLKO rising edge RD and RD WR lobo l 2 2 ns active inactive after BFCLKO active edge CSx output delay from to CC 2 5 1 5 ns BFCLKO active edge ADV active inactive after t CC 2 x 2 ns BFCLKO active edge BAA active inactive after t CC 2 5 1 5 ns BFCLKO active edge Data setup to BFCLKI t3 SR 3 ns rising edge Data hold from BFCLKI tog SR J0 ns rising edge WAIT setup low or high t SR 3 ns to BFCLKI rising edge WAIT hold low
31. Control Output 1 SLSO34 O2 SSC3 Output Reserved O3 Port 8 H2 P8 0 1 0 A2 Port 8 General Purpose I O Line 0 IN40 l PU IN40 Line of GPTAO IN40 l IN40 Line of GPTA1 SENTO l SENT Digital Input OUT40 01 OUT40 Line of GPTAO COUT62 O2 CCU61 TCLK1 O3 MLH transmit Channel Clock Output Data Sheet 50 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function H1 P8 1 V0 A1 Port 8 General Purpose I O Line 1 IN41 l FH IN41 Line of GPTAO IN41 l IN41 Line of GPTA1 TREADY1A MLI1 transmit Channel ready Input A SENT1 l SENT Digital Input CC61INA l CCU60 CC61INB l CCU61 OUT41 O1 OUT41 Line of GPTAO CC61 O2 CCU60 SENT1 O3 SENT Digital Output J3 P8 2 0 A2 Port 8 General Purpose I O Line 2 IN42 l P IN42 Line of GPTAO IN42 l IN42 Line of GPTA1 SENT2 l SENT Digital Input CAPINA l GPT120 CAPINB l GPT121 COUT63 O1 CCU61 OUT42 O2 OUT42 Line of GPTA1 TVALID1A O3 MLH transmit Channel valid Output A Data Sheet 51 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function J2 P
32. DemuxRD Async 10 vsd Figure 26 Data Sheet Demultiplexed Read Access 164 V 1 2 2014 05 Cinfineon Tene Electrical ParametersAC Parameters Table 43 EBU Asynchnronous Write Timings Parameter Symbol Values Unit Note Min Typ Max Test Condition A 23 0 output delay to tx CC 2 5 2 5 ns WR rising edge deviation from the ideal programmed value A 23 0 output delay to ta CC 2 5 2 5 ns WR rising edge deviation from the ideal programmed value CS rising edge to WR ta CC 2 2 ns rising edge deviation from the ideal programmed value ADV rising edge to WR ta CC 2 5 S 2 ns rising edge deviation from the ideal programmed value BC rising edge to WR ta CC 2 5 2 ns rising edge deviation from the ideal programmed value WAIT input setup to WR t SR 12 ns rising edge deviation from the ideal programmed value WAIT input hold to WR fa SR JO ns rising edge deviation from the ideal programmed value Data output delay to WR t CC 5 5 2 ns falling edge deviation from the ideal programmed value Data Sheet 165 V 1 2 2014 05 Cinfineon TC1793 Table 43 EBU Asynchnronous Write Timings cont d Electrical ParametersAC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Data output delay to WR t CC 5 5 2 ns rising edge deviation from t
33. IN30 l IN30 Line of LTCA2 OUT30 O1 OUT30 Line of GPTAO OUT30 O2 OUT30 Line of GPTA1 SLSO23 O3 SSC2 Output Data Sheet 37 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AE12 P4 7 I O A1 Port 4 General Purpose I O Line 7 IN31 l FH IN31 Line of GPTAO IN31 l IN31 Line of GPTA1 IN31 l IN31Line of LTCA2 T6INB l GPT120 T6INA l GPT121 OUT31 01 OUT31 Line of GPTAO OUT31 O2 OUT31 Line of GPTA1 SLSO24 O3 SSC2 Output AC13 P4 8 0 A1 Port 4 General Purpose I O Line 8 IN32 l PU IN32 Line of GPTAO IN32 l IN32 Line of GPTA1 CCPOS1A l CCU60 T13HRB l CCU61 T3EUDA l GPT120 T3EUDB l GPT121 OUT32 01 OUT32 Line of GPTAO OUT32 O2 OUT32 Line of GPTA1 OUTO O3 OUTO Line of LTCA2 Data Sheet 38 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AB19 P4 9 V0 A1 Port 4 General Purpose I O Line 9 IN33 l FH IN33 Line of GPTAO IN33 l IN33 Line of GPTA1 CCPOS2A l CCU60 T12HRC l CCU61 T13HRC l CCU61 T4INA l GPT120 T4INB l GPT121 SLSI2 l SSC2 OUT33 O1 OUT33 Li
34. Line of LTCA2 AD12 O EBU Address Data Bus Line 12 V24 P13 13 0 B Port 13 General Purpose I O Line 13 AD13 l Ja EBU Address Data Bus Line 13 OUT101 O1 OUT101 Line of GPTAO OUT 101 O2 OUT101 Line of GPTA1 OUT93 O3 OUT93 Line of LTCA2 AD13 O EBU Address Data Bus Line 13 Y25 P13 14 I O B Port 13 General Purpose I O Line 14 AD14 l Ky EBU Address Data Bus Line 14 OUT102 01 OUT102 Line of GPTAO OUT102 02 OUT102 Line of GPTA1 OUT94 O3 OUT94 Line of LTCA2 AD14 O EBU Address Data Bus Line 14 AB26 P13 15 0 B Port 13 General Purpose I O Line 15 AD15 l EBU Address Data Bus Line 15 OUT103 O1 OUT103 Line of GPTAO OUT103 O2 OUT103 Line of GPTA1 OUT95 O3 OUT95 Line of LTCA2 AD15 O EBU Address Data Bus Line 15 Port 14 Data Sheet 68 V 1 2 2014 05 Cinfineon Hus PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function W24 P14 0 0 B Port 14 General Purpose I O Line 0 AD16 l FB EBU Address Data Bus Line 16 CC60 O1 CCU60 OUT96 O2 OUT96 Line of GPTA1 OUT96 O3 OUT96 Line of LTCA2 AD16 O EBU Address Data Bus Line 16 AA25 P14 1 0 B Port 14 General Purpose I O Line 1 AD17 l PU EBU Address Data Bus Line 17 CC61 O1 CCU60 OUT97 O2 OUT97 Line of GPTA1 OUT97 O3 OUT97 Line of LTCA2 AD17 O EBU Address Data Bus Line 17 Y24 P14 2 l O B Port 14 General
35. Parameters Table 19 Standard Pads Class B cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Rise time class B pads trp CC _ 3 7 ns C 35 pF edge sharp pin out Vbpegu 2 375 driver strong Vopesus lt 2 625 3 0 ns C 35 pF Vobpggu 3 13 Vbpegu lt 3 47 _ 4 6 ns C 50 pF Voppggu 2 375 Vbpegu lt 2 625 E 3 7 ns C 50 pF Vopgsu 3 13 Vbpegu lt 3 47 9 0 ns C 100 pF Vopggu 2 375 Vbpegu lt 2 625 7 5 ns C 100 pF Vppegu gt 3 13 Vbpegu lt 3 47 Input high voltage class B Viyz CC 0 6x max V V pads VppEBU DDEBU 0 3 3 6 Input low voltage Class B Vjg CC 0 3 0 36 x V pads VppEBU Output voltage high class Vous Vppesu _ V Tou 2 mA B pads CC 0 4 Vbpegu 2 375 Vbpegu lt 3 47 V Output voltage low class Vore CC z 0 4 V Igj 2mA B pads 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise 2 For non strong driver and sharp edge settings see the class A2 definitions Data Sheet 117 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 20 Standard Pads Class F Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis F HYSF 0 0
36. ParametersDC Parameters FADC Analog Input Stage VcAGND B Vearer 2 FADC Reference Voltage Input Circuitry e o Veangr FADC InpRefDiag Figure 8 FADC Input Circuits Data Sheet 129 V 1 2 2014 05 Cinfineon TC1793 5 2 4 Oscillator Pins Table 27 OSC XTAL Parameters Electrical ParametersDC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Input current at XTAL1 Tix CC 25 25 HA Vin lt Voposcs Vin gt 0 V Input frequency fosc SR 4 40 MHz Direct Input Mode selected 8 25 MHz External Crystal Mode selected Oscillator start up time toscs 10 ms CC Input high voltage at Vinx SR 10 7x Vppos V XTAL1 Vppos ca C3 0 5 Input low voltage at Vix SR 0 5 03x IV XTAL1 Vppos C3 Input Hysteresis for HYSAX 200 mV XTAL1 pad cc 1 toscs is defined from the moment when Vpposc3 3 13V until the oscillations reach an amplitude at XTAL1 of 0 3 Vpposcs The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystral suppliers 2 If the XTAL1 pin is driven by a crystal reaching a minimum amplitude peak to peak of 0 4 Vpposca is necessary 3 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses s
37. Purpose I O Line 2 AD18 l EM EBU Address Data Bus Line 18 CC62 O1 CCU60 OUT98 O2 OUT98 Line of GPTA1 OUT98 O3 OUT98 Line of LTCA2 AD18 O EBU Address Data Bus Line 18 AA23 P14 3 0 B Port 14 General Purpose I O Line 3 AD19 l EBU Address Data Bus Line 19 COUT60 O1 CCU60 OUT99 O2 OUT99 Line of GPTA1 OUT99 O3 OUT99 Line of LTCA2 AD19 O EBU Address Data Bus Line 19 Data Sheet 69 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AB25 P14 4 0 B Port 14 General Purpose I O Line 4 AD20 l FB EBU Address Data Bus Line 20 COUT61 O1 CCU60 OUT100 O2 OUT100 Line of GPTA1 OUT 100 O3 OUT100 Line of LTCA2 AD20 O EBU Address Data Bus Line 20 AB24 P14 5 0 B Port 14 General Purpose I O Line 5 AD21 l PU EBU Address Data Bus Line 21 COUT62 O1 CCU60 OUT101 O2 OUT101 Line of GPTA1 OUT 101 O3 OUT101 Line of LTCA2 AD21 O EBU Address Data Bus Line 21 AA24 P14 6 I O B Port 14 General Purpose I O Line 6 AD22 l Ky EBU Address Data Bus Line 22 COUT63 01 CCU60 OUT102 O2 OUT102 Line of GPTA1 OUT102 O3 OUT102 Line of LTCA2 AD22 O EBU Address Data Bus Line 22 AC26 P14 7 0 B Port 14 General Purpose I O Line 7 AD23 l EBU Address Data Bus Line 23 CC60 O1 CCU61 OUT103 O2 OUT103 Line of GPTA1 OUT103 O3
38. T3INA l GPT120 T3INB l GPT121 OUT6 O1 OUT6 Line of GPTAO OUT6 O2 OUT6 Line of GPTA1 OUT6 O3 OUT6 Line of LTCA2 A4 P2 15 0 A1 Port 2 General Purpose I O Line 15 IN7 l FU IN7 Line of GPTAO IN7 l IN7 Line of GPTA1 IN7 l IN7 Line of LTCA2 OUT7 01 OUT7 Line of GPTAO OUT7 02 OUT7 Line of GPTA1 OUT7 O3 OUT7 Line of LTCA2 Port 3 Data Sheet 28 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B12 P3 0 V0 A1 Port 3 General Purpose I O Line 0 IN8 l PU IN8 Line of GPTAO IN8 l IN8 Line of GPTA1 IN8 l IN8 Line of LTCA2 CTRAPA l CCU62 CTRAPB l CCU61 CC60INC l CCU62 T12HRE l CCU63 CC61INC l CCU63 T5INA l GPT120 T5INB l GPT121 OUT8 O1 OUTS8 Line of GPTAO OUT8 O2 OUTS Line of GPTA1 OUT8 O3 OUTS Line of LTCA2 A12 P3 1 0 A1 Port 3 General Purpose I O Line 1 IN9 l PU IN9 Line of GPTAO IN9 l IN9 Line of GPTA1 IN9 l IN9 Line of LTCA2 OUT9 O1 OUTO9 Line of GPTAO OUT9 O2 OUTO9 Line of GPTA1 OUT9 O3 OUTS Line of LTCA2 Data Sheet 29 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C13 P3 2 I
39. TC1793 Electrical ParametersDC Parameters Table 17 Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Output voltage high class A1 pads Vonat CC Vopr 0 4 lou gt 1 4 mA pin out driver medium Vopr 0 4 lou gt 1 4 mA pin out driver strong 2 4 Ton 2 mA pin out driver medium 2 4 Ton 2 mA pin out driver strong Vopr 0 4 lon 400 uA pin out driver weak 2 4 lon 500 uA pin out driver weak Output voltage low class A1 pads Votat CC 0 4 Ig 2 mA pin out driver medium 0 4 Ig 2 mA pin out driver strong 0 4 Ig lt 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Data Sheet 109 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 18 Standard Pads Class A2 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for A2 HYSA2 0 1x V pads CC Vopp Input Leakage current loza2 6000 6000 nA V lt Vopp 2 Class A2 CC 1 V V gt Vppp 2 1V V20V Vis Vopp V 3000 3000 nA Vi gt Vppp 2 1 V V lt Vppp 2 1
40. Vppar Vpppr 1 365 V VDDP Vpposc Vppwr Vppria Voppr 3 47 V Vbpm 5 25 V fSRI CPU 270 200 MHz fPCP 180 200 MHz fSRI 90 100 MHz TJ 150 oC The realisic power pattern defines the following conditions e TJ 150 oC fsm fceu 270 200 MHz fece 180 200 MHz frp 90 100MHz Vop Voposc Vppar Voper 1 326 V Vopr Vpposca Vopris Vpppra Vppwr 3 366 V Voom 5 1 V The max power pattern defines the following conditions e TJ 150 oC fsm fopy 270 200 MHz fece 180 200 MHz e fep 90 100MHz Voo Vpposc Vppar Vpppr 1 43 V Vopp Voposcs Vopris Voppr3 Vopr 3 63 V Vopm 55 V Data Sheet 132 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 29 Power Supply Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Core active mode supply pp CC 840 mA power current pattern max fCPU 270 MHz 621 mA power pattern realisti C fCPU 270 MHz 735 mA_ power pattern max fCPU 200 MHz 555 mA power pattern realisti C fCPU 200 MHz lbp current at PORST Low pp pons 298 mA TJ 150 oC CC 249 mA TJ 1400C E Ray PLL core supply Ipppr 4 mA current CC Oscillator core supply Ipposc 3 mA current CC Analog core supply Ippar E 26 mA current CC Sum of all 1 3 V supply Tppsum 6
41. Vppy 0 07V then the accuracy of the ADC decrease by 4LSB12 Table 25 Conversion Time Operating Conditions apply Parameter Symbol Values Unit Note Conversion te CC 2x Tape 44 STC n x Tang us n 7 8 10 12 for time with n bit conversion post calibration Tapco 1 fep Conversion 2 x Tape 2 STC n x Tape Tapc 1 fapci time without post calibration The power up calibration of the ADC requires a maximum number of 4352 fpc cycles Analog Input Circuitry AIN On o T Cansw C AINTOT AINSW Reference Voltage Input Circuitry H AREF On e o Analog InpRefDiag Figure 6 ADCx Input Circuits Data Sheet 124 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters loz1 500nA 4 200nA 100nA Single ADC Input Vin Vppm gt 100nA1 500nA loz1 600nA4 300nA L 100nA 100nA1 600nA 396 97 100 Overlayed ADC FADC Input VI N VDDM gt 396 97 100 Figure 7 Data Sheet ADCx Analog Inputs Leakage 125 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters 5 2 3 Fast Analog to Digital Converter FADC FADC parameter are vaild for Vbo ppar 1 235 V to 1 365 V Vbowr 2 97 V to 3 6 V Table 26 FADC Parameters Parameter Symbol Values Min Typ Max Unit Note Test Cond
42. are additional decrease in the ADC speed and accuracy If the analog reference voltage range is below Vp but still in the defined range of Vppw 2 and Vppy is used then the ADC converter errors increase If the reference voltage is reduced by the factor k k 1 TUE DNL INL Gain and Offset errors increase also by the factor 1 k If the analog reference voltage is gt V5py then the ADC converter errors increase For 10 bit conversions the error value must be multiplied with a factor 0 25 For 8 bit conversions the error value must be multiplied with a factor 0 0625 For fapc between 18MHz and 20MHz the TUE and Gain Error can increase beyond the given limits For STC 2 INL DNL and Offset errors can also increase Data Sheet 123 V 1 2 2014 05 Infineon His Electrical ParametersDC Parameters 11 For a conversion time of 1 us a rms value of 85pA result for Ippero 12 The leakage current definition is a continuos function as shown in figure ADCx Analoge Input Leakage The numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function 13 Measured without noise 14 For 10 bit conversion the TUE is 2LSB for 8 bit conversion the TUE is 1LSB 15 A running conversion may become inexact in case of violating the normal conditions voltage overshoot 16 If the reference voltage Varer increase or the Vppy decrease so that Varer Vppy 0 05V to
43. available TC1793ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL and PLL ERAY Flexible CRC Engine FCE IEEE 802 3 CRC32 ethernet polynomial 0xX82608EDB CRC kernel 0 CRC32C Castagnoli 0xD419CC15 CRC kernel 1 The SAK TC1793F 512F200EB SAK TC1793F 512F200EF has the following features High performance 32 bit super scalar TriCore V1 6 CPU with 6 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Multiply accumulate unit able to sustain 2 MAC operations per cycle Fully pipelined Floating point unit FPU Data Sheet 2 V 1 2 2014 05 Cinfineon Tene Summary of Features 200 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 200 MHz operation at full temperature range Multiple on chip memories 4 Mbyte Program Flash Memory PFLASH with ECC 192 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 2x 8 Kbyte Key Flash 128 Kbyte Data Scratch Pad RAM DSPR 16 Kbyte Instruction Cache ICACHE 32 Kbyte Instruction Scratch Pad RAM PSPR 16 Kbyte Data Cache DACHE 128 Kbyte Memory SRAM 16 Kbyte BootROM BROM 16 Chan
44. noise on the pad supply voltage measured between Vpposc and V ssosc iS limited to a peak to peak voltage of Vpp 100 mV for noise frequencies below 300 KHz and Vpp 40 mV for noise frequencies above 300 KHz These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes Oscillator Watchdog OSC WDT The expected input frequency is selected via the bit field SCU_OSCCON OSCVAL The OSC WDT checks for too low frequencies and for too high frequencies The frequency that is monitored is fogcree which is derived for fosc 9 f OSC f SS E TAR oscrEF OSCVAL 1 The divider value SCU_OSCCON OSCVAL has to be selected in a way that foscrer is 2 5 MHz Data Sheet 143 V 1 2 2014 05 Cinfineon ree Electrical ParametersAC Parameters Note foscrer has to be within the range of 2 MHz to 3 MHz and should be as close as possible to 2 5 MHz The monitored frequency is too low if it is below 1 25 MHz and too high if it is above 7 5 MHz This leads to the following two conditions Too low fose lt 1 25 MHz x SCU_OSCCON OSCVAL 1 Too high fosc gt 7 5 MHz x SCU_OSCCON OSCVAL 1 Note The accuracy is 30 for these boundaries Frequency Modulation Frequency modulation defines a slow and predictable variation of the clock speed The modulation configuration itself is controlled via register SCU_PLLCON2 where the two bit fields
45. 0 pF DE 5V ADC l 3 3 V LVTTL input only 1 These values show typical application configurations for the pad Complete and detailed pad parameters are available in the individual pad parameter table on the following pages 2 Supplied via Vppggu 3 In applications where the LVDS pins are not used disabled these pins must be either left unconnected or properly terminated with the differential parallel termination of 100 O 10 Data Sheet 91 V 1 2 2014 05 Cinfineon TC1793 5 1 3 Electrical ParametersGeneral Parameters Absolute Maximum Ratings Stresses above the values listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions may affect device reliability Table 9 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Note Min Typ Max Test Con dition Storage temperature Ter SR 65 150 C Voltage at 1 3 V power supply Vg SR 2 0 V pins with respect to Vss Voltage at 3 3 V power supply Vopp 4 33 V pins with respect to Veg SR Voltage at 5 V power supply Vbom SR 7 0 V pins with respect to Vss
46. 05 Cinfineon Ls Electrical ParametersAC Parameters MLI Transmitter Timing ls t4 TCLKx TDATAx TVALIDx TREADYx MLI Receiver Timing bs ba RCLKx RDATAx RVALIDx RREADYx MLI Tmg 2 vsd Figure 19 MLI Interface Timing Note The generation of RREADY x is in the input clock domain of the receiver The reception of TREADYx is asynchronous to TCLKx The MLI parameters are vaild for C 50 pF and strong driver medium edge Data Sheet 150 V 1 2 2014 05 Cinfineon TC1793 Table 35 MLI Receiver Electrical ParametersAC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition RCLK clock period too SR 1 fee ns RCLK high time ta SR l 0 5x ns t20 RCLK low time too SR l 05x ns 120 RCLK rise time ta SR l 4 ns RCLK fall time ta SR l 4 ns RDATA RVALID setup tos SR 42 ns time before RCLK falling edge RDATA RVALID hold time t2 SR 2 2 ns after RCLK falling edge RREADY output delay ta SR 0 16 ns time 1 The following formula is valid t21 t22 t20 2 Min and Max values for this parameter can be derived from the typ value by considering the other receiver timing parameters 3 The RCLK max input rise fall times are best case parameters for fSYS 90 MHz For reduction of EMI slower input signal rise fall times can be used for longer RCLK cloc
47. 1 P2 4 2 P6 6 9 2 P6 5 4 P6 11 10 3 P6 15 12 4 P8 5 0 5 P8 7 6 P1 15 13 6 P1 5 P1 11 8 7 P1 4 2 P1 6 P1 12 8 P1 1 0 P7 2 0 9 P7 7 3 10 P4 6 0 11 P4 10 7 12 P4 15 11 13 P10 5 0 14 P15 7 4 P16 1 0 15 P15 3 P15 12 11 P16 5 3 Data Sheet 100 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersGeneral Parameters Table 14 Pin Groups for Overload Short Circuit Current Sum Parameter Group Pins 16 P15 2 0 P15 9 8 P16 2 P16 8 17 P15 10 P15 15 13 P16 7 6 18 P14 15 12 19 P14 11 8 P16 12 20 P14 7 3 P16 11 21 P13 15 P14 2 0 22 P13 14 11 23 P13 10 8 P16 10 24 P13 7 4 P16 9 25 P12 5 P13 3 0 26 P12 4 0 27 P11 15 11 28 P11 10 6 29 P11 5 2 30 P11 1 0 P12 7 6 31 P9 10 P9 14 32 P9 7 P9 13 33 P9 4 2 P9 6 34 P9 1 P9 5 P9 9 8 35 P9 0 P9 12 11 36 P5 11 8 37 P5 6 P5 15 12 38 P5 0 P5 5 2 P5 7 39 P3 5 0 P5 1 40 P3 12 6 41 PO 3 0 P3 15 13 42 PO 11 4 43 P0 14 12 44 P0 15 Data Sheet 101 V 1 2 2014 05 Cinfineon ee Electrical ParametersGeneral Parameters Table 14 Pin Groups for Overload Short Circuit Current Sum Parameter Group Pins 45 P2 15 11 46 P2 10 5 Data Sheet 102 V 1 2 2014 05 Cinfineon TC1793 Electrical Parameters
48. 12 2 EBU Asynchronous Timings 0000 e eee eee ee 5 159 5 3 12 3 EBU Burst Mode Access Timing 0 ee eee eee 5 168 Data Sheet l 1 V 1 2 2014 05 Cinfineon Tots 5 3 12 4 EBU Arbitration Signal Timing 2000s eee eee 5 171 5 4 Flash Memory Parameters kk kK KK KK eee eee KK KIRI KI 5 172 5 5 Package and Reliability lel 5 174 5 5 1 Package Parameters was kla k kk a la kak kak kk kik anek ka a 5 174 5 5 2 Package Outline kk kk kk kK KK eee 5 175 5 5 3 Quality Declarations kk kk kk kK KK KK KK ees 5 175 6 HISIOTV coco k ala Anna aoe ya 400 k ran Red QE A dx BUR teen nee a cee 6 1 Data Sheet l 2 V 1 2 2014 05 Cinfineon a Data Sheet 3 V 1 2 2014 05 Cinfineon a Data Sheet 4 V 1 2 2014 05 Cinfineon Tene 1 Summary of Features Summary of Features The SAK TC1793F 512F270EF has the following features High performance 32 bit super scalar TriCore V1 6 CPU with 6 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Multiply accumulate unit able to sustain 2 MAC operations per cycle Fully pipelined Floating point unit FPU 270 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 200 MHz operation at full temperature range
49. 12F270EF TA 40 C to 125 C SAK TC1793F 512F200EF TA 40 C to 125 C SAK TC1793F 512F200EB TA 40 C to 125 C SAK TC1793N 512F270EF TA 40 C to 125 C SAK TC1793S 512F270EF TA 40 C to 125 C Data Sheet 9 V 1 2 2014 05 Cinfineon TONS System Overview of the TC1793 2 System Overview of the TC1793 The TC1793 combines three powerful technologies within one silicon die achieving new levels of power speed and economy for embedded applications Reduced Instruction Set Computing RISC processor architecture Digital Signal Processing DSP operations and addressing modes On chip memories and peripherals DSP operations and addressing modes provide the computational power necessary to efficiently analyze complex real world signals The RISC load store architecture provides high computational bandwidth with low system cost On chip memory and peripherals are designed to support even the most demanding high bandwidth real time embedded control systems tasks Additional high level features of the TC1793 include Efficient memory organization instruction and data scratch memories caches Serial communication interfaces flexible synchronous and asynchronous modes Peripheral Control Processor standalone data operations and interrupt servicing DMA Controller DMA operations and interrupt servicing General purpose timers High performance on chip buses On chip debugging and emulation fac
50. 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters Ba bea 1 First shift First latching SCLK SCLK edge SCLK edge m bs bs sa a Last latching SCLK edge 1 This timing is based on the following setup CON PH CON PO 0 SSC_TmgSM Figure 22 Data Sheet SSC Slave Mode Timing 156 V 1 2 2014 05 Cinfineon Tels Electrical ParametersAC Parameters 5 3 11 ERAY Interface Timing The timings of this section are valid for the strong driver and either sharp edge or medium edge settings of the output drivers with C 25 pF The ERAY interface is only available for the SAK TC1793F 512F270EF SAK TC1793F 512F270EB SAK TC1793F 512F200EF SAK TC1793F 512F200EB SAK TC1793S 512F270EF Table 39 ERAY Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Time span from last BSS fg CC 997 75 1002 2 ns to FES without the 5 influence of quartz tolerancies d10Bit TX TxD data valid from te1 teo i 1 5 ns Asymmetrical fsample flip flop txd reg CC delay of rising TxDA TxDB andfalling edge dTxAsym 9 TxDA TxDB Time span between last fe SR 966 1046 1 ns BSS and FES without influence of quartz tolerancies d10Bit RX 99 RxD capture by fsample fea fes i x 3 0 ns Asymmetrical RxDA RxDB sampling CC delay of rising flip flop dRxAsym 9 andfalling edge RxDA RxDB TxD data d
51. 2 0 B Port 14 General Purpose I O Line 12 AD28 l FB EBU Address Data Bus Line 28 COUT62 O1 CCU61 OUT108 O2 OUT108 Line of GPTA1 OUT108 O3 OUT108 Line of LTCA2 AD28 O EBU Address Data Bus Line 28 AE25 P14 13 0 B Port 14 General Purpose I O Line 13 AD29 l Ja EBU Address Data Bus Line 29 COUT63 O1 CCU61 OUT109 O2 OUT109 Line of GPTA1 OUT109 O3 OUT109 Line of LTCA2 AD29 O EBU Address Data Bus Line 29 AE24 P14 14 I O B Port 14 General Purpose I O Line 14 AD30 l i EBU Address Data Bus Line 30 T3INC l GPT120 T3IND l GPT121 OUT110 01 OUT110 Line of GPTAO OUT110 02 OUT110 Line of GPTA1 OUT110 O3 OUT110 Line of LTCA2 AD30 O EBU Address Data Bus Line 30 Data Sheet 72 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AD24 P14 15 I O B Port 14 General Purpose I O Line 15 AD31 l FB EBU Address Data Bus Line 31 T3EUDC l GPT120 T3EUDD l GPT121 OUT111 01 OUT111 Line of GPTAO OUT111 02 OUT111 Line of GPTA1 OUT111 O3 OUT111 Line of LTCA2 AD31 O EBU Address Data Bus Line 31 Port 15 AE21 P15 0 0 B Port 15 General Purpose I O Line 0 T4INC l PU GPT120 T4IND l GPT121 CCPOS2B l CCU60 Reserved O1 Reserved O2 Reserved O3 CS0 O Chip Select Output Line 0 AD21 P15 1 I O B Port 1
52. 3 Electrical ParametersAC Parameters EBU STATE Control Bitfield Duration Limits in EBU CLK Cycles A 23 0 CS 3 0 ADV BC 3 0 WAIT AD 31 0 MR W pv fy Address Phase ADDRC 1 15 Address Hold Phase opt AHOLDC 0 15 Command Delay Phase CMDDELAY 0 7 Command Phase RDWAIT 1 31 Recovery Phase opt RDRECOVC 0 15 XX Valid Address AN A Addr pv b py t md DV f pv s Pth rb CSCOMB N pv t pyv ts a COED pv programmed value Tesu c k sum correponding bitfield values new_MuxRD_Async_10 vsd New Addr Phase ADDRC 1 15 Figure 25 Data Sheet Multiplexed Read Access 163 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters EBU Address Address Hold Command Recovery New Addr STATE Phase Phase opt Phase Phase opt Phase Duration Limits in 1 15 0 15 1 531 0 15 1 15 EBU_CLK Cycles A 23 0 Valid Address A _ Adar DV fo pv li CHE 2 pv h b CS 3 0 CSCOMB I pV t DV t ADV pv h RD m pv t pv lT ITZ l BC 3 0 Hk _ pv ls Lb WAIT t m AD 31 0 Data In MR W m Dv ls pv programmed value Tggu cix sum correponding bitfield values new
53. 3 mW power dissipation pattern max fCPU 270 MHz 1488 mW power pattern realisti C fCPU 270 MHz 1523 mW power pattern max fCPU 200 MHz 1403 mW power pattern realisti C fCPU 200 MHz 1 Infineon Power Loop CPU and PCP running all peripherals active The power consumption of each customer application will most probably be lower than this value but must be evaluated seperately This current includes the E Ray module power consumption including the PCP operation component The pp decreases typically by 97 mA if the fcp decreases by 50MHz at constant T 4 The pp decreases typically by 105 mA if the fopy decreases by 50MHz at constant T D Flash read write or erase opoeration in parallel to P Flash operations name in Test Condition is covered already in the give current limits 6 Relevant for the power supply dimensioning not for thermal considerations 7 In case of erase of Program Flash PFx internal flash array loading effects may generate transient current Spikes of up to 15 mA for maximum 5 ms per flash module 8 For power supply dimensioning of Vppp 30 mA have to added for flash programming case Note In general current consumption for operations with data flash are always lower than the defined values for program flash read operation 5 2 6 1 Calculating the 1 3 V Current Consumption The current consumption of the 1 3 V rail compose out
54. 3 V 1 3 V and 5 V with different names for example VDDP VDDFL3 that are internally connected via diodes must be lower than Data Sheet 138 V 1 2 2014 05 Cinfineon Tete Electrical ParametersAC Parameters 100 mV On the other hand all power supply pins with the same name for example all VDDP are internally directly connected It is recommended that the power pins of the same voltage are driven by a single power supply The PORST signal may be deactivated after all VDD5 VDD3 3 VDD1 3 and VAREF power supplies and the oscillator have reached stable operation within the normal operating conditions At normal power down the PORST signal should be activated within the normal operating range and then the power supplies may be switched off Care must be taken that all Flash write or delete sequences have been completed At power fail the PORST signal must be activated at latest when any 3 3 V or 1 3 V power supply voltage falls 1296 below the nominal level If under these conditions the PORST is activated during a Flash write only the memory row that was the target of the write at the moment of the power loss will contain unreliable content In order to ensure clean power down behavior the PORST signal should be activated as close as possible to the normal operating voltage range n case of a power loss at any power supply all power supplies must be powered down conforming at the same time to the rules number 2 an
55. 5 General Purpose I O Line 1 T4EUDC l ika GPT120 T4EUDD l GPT121 CCPOS2B l CCU61 Reserved O1 Reserved O2 Reserved O3 CS1 O Chip Select Output Line 1 Data Sheet 73 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AD20 P15 2 y o B Port 15 General Purpose I O Line 2 Reserved O1 FB Reserved O2 Reserved O3 CS2 O Chip Select Output Line 2 AD19 P15 3 I O B Port 15 General Purpose I O Line 3 Reserved 01 PB Reserved O2 Reserved O3 CS3 O Chip Select Output Line 3 AE17 P15 4 yo B Port 15 General Purpose I O Line 4 Reserved O1 is Reserved O2 Reserved O3 BCO O Byte Control Line 0 AD17 P15 5 I O B Port 15 General Purpose I O Line 5 Reserved O1 u Reserved O2 Reserved O3 BC1 O Byte Control Line 1 AF18 P15 6 l O B Port 15 General Purpose I O Line 6 Reserved O1 FE Reserved O2 Reserved O3 BC2 O Byte Control Line 2 Data Sheet 74 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type
56. 5 JTAG Timing Data Sheet 147 V 1 2 2014 05 Cinfineon rus Electrical ParametersAC Parameters 5 3 7 DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface Note These parameters are not subject to production test but verified by design and or characterization Table 34 DAP Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition DAPO clock period trek SR 12 5 ns DAPO high time ty SR 14 ns DAPO low time t SR 4 ns DAPO clock rise time t4 SR 2 ns DAPO clock fall time t SR 2 ns DAP1 setup to DAPO tig SR 6 0 _ ns rising edge DAP1 hold after DAPO t SR 6 0 ns rising edge DAP1 valid per DAPO t CC 8 e ns C 7 20 pF clock period f 80 MHz 10 ns C 50 pF f 40 MHz 1 See the DAP chapter for clock rate restrictions in the Active IDLE protocol state 2 The Host has to find a suitable sampling point by analyzing the sync telegram response 0 1 V f DDP MC DAPO Figure 16 Test Clock Timing DAPO Data Sheet 148 V 1 2 2014 05 Cinfineon TOGS Electrical ParametersAC Parameters AJANA DAPO he t r DAP1 MC_DAP1_RX Figure 17 DAP Timing Host to Device MC_DAP1_TX Figure 18 DAP Timing Device to Host 5 3 8 Micro Link Interface MLI Timing Data Sheet 149 V 1 2 2014
57. 5000 ns C 20000 pF pin out driver weak Input high voltage class A2 pads Viaa2 SR 0 6 x Vppp min V DDP 0 3 3 6 Input low voltage Class A2 pads V La2 SR 0 3 0 36 x Vopp Output voltage high class A2 pads Voua2 CC Voor 0 4 Igy2 1 4 mA pin out driver medium Vope 0 4 Tone 1 4 mA pin out driver strong 2 4 Io 2 mA pin out driver medium 2 4 Io 2 mA pin out driver strong Vopr 0 4 Toyz 400 pA pin out driver weak 2 4 Toz 500 pA pin out driver weak Data Sheet 114 V 1 2 2014 05 Cinfineon TC1793 Table 18 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Output voltage low class A2 pads Vora2 CC 0 4 Ig 2 mA pin out driver medium 0 4 Ig 2 mA pin out driver strong 0 4 lo lt 500 pA pin out driver weak 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Table 19 Standard Pads Class B Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis B class HYSB 0 08x V Vppepu 2 5 V
58. 54 mA power currents CC pattern realisti C fCPU 270 MHz 588 mA power pattern realisti C fCPU 200 MHz E Ray PLL 3 3V supply lppeg 4 mA CC Oscillator power supply Ipposca 11 mA current 3 3V CC Data Sheet 133 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 29 Power Supply Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition FADC analog supply Ippwr 15 mA current 3 3V CC Ippe current at PORST lope por 5 7 mA Low st CC Tppp current no pad Ippp CC lppe mA including flash activity LVDS off PORST read current 25 _ lppg mA including flash PORST programming 55 current 9 x lppe mA including flash PORST erase verify 40 current 9 Flash memory current Ibor 98 mA flash read CC current 29 mA flash programming current 9 98 mA flash erase current 9 Current Consumption of Ji ps 24 mA in total for all LVDS Pad Pairs CC LVDS pairs Sum of all 3 3 V supply Ipp3sum_ 1609 mA including flash currents no pad activity CC read current LVDS off ADC 5V power supply Ibom CC 6 mA current Data Sheet 134 V 1 2 2014 05 Infineon His Electrical ParametersDC Parameters Table 29 Power Supply Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Maximum power PDCC 163
59. 5x V cc Vppp Input Leakage Current Iozr CC 6000 6000 nA V lt Vopp 2 Class F 1 V V gt Vppp 2 1V V20V Vis Vopp V 3000 3000 nA V gt Vppp 2 1 V V lt Vppp 2 1V Ratio Vil Vih F pads Vite 0 6 Vine CC On Resistance of the RpsowM i 170 Ohm Top 2 mA class F pad medium CC P MOS driver 145 Ohm Jg 2 mA N_MOS Fall time pad type F ter CC 60 ns C 50 pF CMOS mode Rise time pad type F tar CC 60 ns C 50 pF CMOS mode Input high voltage pad Ving SR 10 6x min V V class F CMOS mode Vope DDP 0 3 3 6 Input low voltage Class F V c SR 0 3 0 36x V pads CMOS mode Vopp Output high voltage class Voc Vopp V Top 1 4 mA F pads CMOS mode CC 0 4 2 4 V Io 2 mA Output low voltage class Vopr CC 0 4 V Ig 2 mA F pads CMOS mode 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Data Sheet 118 V 1 2 2014 05 Cinfineon Hine Electrical ParametersDC Parameters Table 21 Standard Pads Class Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis Class I HYSI 01x V cc Vppp Input Leakage Current loz CC 1000 1000 nA Ratio between low and Vii Vy 0 6 high input threshold CC Input high voltage class
60. 7 1 l D S Port 17 General Purpose I Line 1 SENT1 l SENT Digital Input 1 AN9 Analog Input ADCO CH9 Y3 P17 2 l D S Port 17 General Purpose I Line 2 SENT2 l SENT Digital Input 2 AN10 Analog Input ADCO CH10 9 AA2 P17 3 l D S Port 17 General Purpose I Line 3 SENT3 l SENT Digital Input 3 AN11 l Analog Input ADCO CH11 AB1 P17 4 l D S Port 17 General Purpose I Line 4 SENT4 l SENT Digital Input 4 AN12 l Analog Input ADCO CH12 W3 P17 5 l D S Port 17 General Purpose I Line 5 SENT5 l SENT Digital Input 5 AN13 l Analog Input ADCO CH13 Y2 P17 6 l D S Port 17 General Purpose Line 6 SENT6 l SENT Digital Input 6 AN14 l Analog Input ADCO CH14 AA1 P17 7 l D S Port 17 General Purpose I Line 7 SENT7 l SENT Digital Input 7 AN15 Analog Input ADCO CH15 9 AE3 P17 8 l D S Port 17 General Purpose I Line 8 SENTO l SENT Digital Input 0 AN36 l Analog Input ADC2 CH4 Data Sheet 78 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AF2 P17 9 l D S Port 17 General Purpose I Line 9 SENT1 l SENT Digital Input 1 AN37 l Analog Input ADC2 CH5 AC4 P17 10 l D S Port 17 General Purpose I Line 10 SENT2 l SENT Digital Input 2 AN38 l Analog Inpu
61. 8 3 I O A2 Port 8 General Purpose I O Line 3 IN43 l FH IN43 Line of GPTAO IN43 l IN43 Line of GPTA1 SENT3 l SENT Digital Input CC62INA l CCU60 CC62INB l CCU61 OUT43 O1 OUT43 Line of GPTAO CC62 O2 CCU60 TDATA1 O3 MLH transmit Channel Data Output A J1 P8 4 0 A1 Port 8 General Purpose I O Line 4 IN44 l PU IN44 Line of GPTAO IN44 l IN44 Line of GPTA1 RCLK1A l MLI1 Receive Channel Clock Input A SENT4 l SENT Digital Input CC62INB l CCU60 CC62INA l CCU61 OUT44 O1 OUT44 Line of GPTAO CC62 O2 CCU61 T3OUT O3 GPT121 Data Sheet 52 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function K2 P8 5 I O A2 Port 8 General Purpose I O Line 5 IN45 l FH IN45 Line of GPTAO IN45 l IN45 Line of GPTA1 SENT5 l SENT Digital Input CTRAPA l CCU60 CTRAPB l CCU62 CC60INC l CCU60 T12HRE l CCU61 CC61INC l CCU61 OUT45 O1 OUT45 Line of GPTAO OUT45 O2 OUT45 Line of GPTA1 RREADY1A O3 MLI1 Receive Channel ready Output A K3 P8 6 I O A1 Port 8 General Purpose I O Line 6 IN46 l a IN46 Line of GPTAO IN46 l IN46 Line of GPTA1 RVALID1A l MLI1 Receive Channel valid Input A SENT6 l SENT Digital Input OUT46 O1 OUT46 Line of GPTAO COUT60 O2 CCU61 T6OUT O3 GPT120 Data Sheet 53 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 P
62. Age 4 4 LSB ADC CC resolution 12 bit 9 9 Converter clock fanc SR 4 100 MHZ fapc frei Internal ADC clock faoc CC 1 E 18 MHz ADCO 1 18 MHz ADC1 1 20 0 MHz ADC2 Charge consumption per Qcony 70 8510 100 pC charge needs to conversion CC be provided via VAREF0 Data Sheet 121 V 1 2 2014 05 Cinfineon TC1793 Table 24 ADC Parameters cont d Electrical ParametersDC Parameters Parameter Symbol Values Min Typ Max Unit Note Test Condition Input leakage at analog inputs Igz CC 100 500 nA Vis Voom V V 0 97 x Voom V overlayed No 100 600 nA V2 0 97 x Voom V Vis Voom V overlayed Yes 500 100 nA V 0 03 x Voom V V20V overlayed No 600 100 nA V 0 03 x Voom V V20V overlayed Yes 100 200 nA Vi 0 03 x Voom V Vi 0 97 x Voom V overlayed No 100 300 nA Vi 0 97 x Voom V V gt 0 03 x Voom V overlayed Yes Input leakage current at Varero VAREF2 Input leakage current at VAREF1 loz CC HA Varen V Varerx lt Voom V HA Varer V VarerxS Voom V Input leakage current at VAGNDx HA Vacnpxz V VacnoxS Voom V ON resistance of the transmission gates in the analog voltage path 900 1500 Ohm Data Sheet 122 V 1 2 2014 05 Infineon His Electrical ParametersDC Param
63. BU CCU6 GPT12 Digital Circuitry Voo 5 16 Power Supply Vinee KZ Port 15 EBU Vss 4 7 Port 16 EBU even NC in PD 16 SENT Vissie Port 17 Overlay with Analog Inputs V vi ANAS0 Analog Inputs FADC Analog FAGND 3 ds Power Supply VeaREF Vongrx Voowr Vaenox ADCO ADC1 ADC2 Vopar Voom Analog Power Supply N C 3 Vssm 1 Only available for SAKTC 1793F 512F 270EF SAK TC1793F 512F270EB SAK TC1793F 512F200EF and SAK TC 1793F 512F200EB TC1793 LogSym 416 Figure 4 TC1793 Logic Symbol Data Sheet 14 V 1 2 2014 05 Infineon TES PinningTC1793 Pin Configuration 3 1 TC1793 Pin Configuration This chapter shows the pin configuration of the TC1793 package PG BGA 416 10 11 12 13 14 15 16 17 18 19 13 14 15 16 17 mca05584 97 vsd Figure 5 TC1793 Pinning for PG BGA 416 Package Data Sheet 15 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions Pin Symbol Ctrl Type Function Port 0 A9 P0 0 I O A1 Port 0 General Purpose I O Line 0 HWCFGO l PU Hardware Configuration Input 0 OUT56 O1 OUT56 Line of GPTAO OUT56 O2 OUT56 Line of GPTA1 OUT80 O3 OUTS80 Line of LTCA2 A8 PO 1 I O A1 Port 0 General Purpose I O Line 1 HWCFG1 l i Hardware Configuration Input 1 OUT57 O1 OUT57 Line of GPTAO OUT57 O2 OUT57 Line of GPTA1 OUT81 O3 OUTS81
64. Bus Master Interface arn OCDS 11 Debug Interface JTAG Ex 16 channels 2MB PFlash MemCheck 192 KB DFlash MLI 16 KB BROM KeyFlash PMI DMI 32 KB PSPR 16 KB ICACHE 128 KB DSPR 16 KB DCACHE Cross Bar Interconnect SRI SDMA 8 channels 5V 3 3V supported as well Ext ADC Supply Y 32 KB CMEM MultiCAN External EZ c ses Request U 7 2xCCU6 SENT kak E GPT120 FCE GPTAO MSC FMPLL PLL ERAY al E F LTCA2 System Peripheral Bus SPB 33V max ADC L8 3 3V Ext FADC Supply 5V max C TC1793 Figure 2 Block Diagram Data Sheet 12 V 1 2 2014 05 Infineon TC1793 System Overview of the TC1793Block Diagram Figure 3 shows the block diagram of the SAK TC1793S 512F270EF PMI 32 KB PSPR 16 KB ICACHE TriCore CPU 128 KB DSPR 16 KB DCACHE 2MB PFlash 192 KB DFlash 16 KB BROM KeyFlash 2 asce KA 4 ssc EA 4 SSCG SSC Guardian a E Ra 2 puis n MultiCAN 4 Nodes 128 MO SENT 8 channels GPTAO GPTA1 LTCA2 2 MB PFlash DMA 16 channels MemCheck XBAR Ls Ca OCDS11 Debug Interface JTAG MLI 16 KB PRAM M s Interrupts 32 KB CMEM 2 CCU6 ZEN 2 2 A GPT120 MSC LVDS Interrupt System STM SBCU Ports External Request Unit FCE SCU
65. CBS_JDPID 0000 6350 F000 0408 AB CBS_JTAGID 1018 E083 F000 0464 AB SCU_CHIPID 9700 9702 F000 0640 AB SCU_MANID 0000 1820 F000 0644 AB SCU_RTID 0000 0000 F000 0648 AB Table 5 SAK TC1793F 512F200EB Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 AB CBS_JTAGID 1018 E083 F000 0464 AB SCU_CHIPID 1700 9702 F000 0640 AB SCU_MANID 0000 1820 F000 0644 AB SCU_RTID 0000 0000 F000 0648 AB Table 6 SAK TC1793N 512F270EF Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 AB CBS_JTAGID 1018 E083 F000 0464 AB SCU_CHIPID 8700 B102 F000 0640 AB Data Sheet 88 V 1 2 2014 05 Cinfineon TC1793 Identification Registers Table 6 SAK TC1793N 512F270EF Identification Registers cont d Short Name Value Address Stepping SCU MANID 0000 1820 F000 0644 AB SCU RTID 0000 0000 F000 0648 AB Table 7 SAK TC1793S 512F270EF Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 63504 F000 0408 AB CBS_JTAGID 1018 E083 F000 0464 AB SCU CHIPID C700 9702 F000 0640 AB SCU_MANID 0000 18204 F000 0644 AB SCU_RTID 0000 0000 F000 06484 AB Data Sheet 89 V 1 2 2014 05 Cinfineon Tel Electrical ParametersGeneral Parameters 5 Electrical Parameters This specification provides all electrical parameters of the TC1793 5 1 General Parameters 5 1 1 Par
66. Channel valid Input A OUT66 O1 OUT66 Line of GPTAO OUT66 O2 OUT66 Line of GPTA1 OUT90 O3 OUT90 Line of LTCA2 L4 P1 11 l O A1 Port 1 General Purpose I O Line 11 RDATAOA l PU MLIO Receive Channel Data Input A SLSI3 l SSC3 Input OUT67 01 OUT67 Line of GPTAO OUT67 02 OUT67 Line of GPTA1 OUT91 O3 OUT91 Line of LTCA2 P4 P1 12 I O A2 Port 1 General Purpose I O Line 12 EXTCLKO 01 2 External Clock Output 0 OUT68 O2 OUT68 Line of GPTAO OUT68 O3 OUT68 Line of GPTA1 L3 P1 13 I O A1 Port 1 General Purpose I O Line 13 RCLKOB l m MLIO Receive Channel Clock Input B OUT69 O1 OUT69 Line of GPTAO OUT69 O2 OUT69 Line of GPTA1 OUT93 O3 OUT93 Line of LTCA2 L2 P1 14 I O A1 Port 1 General Purpose I O Line 14 RVALIDOB l FB MLIO Receive Channel valid Input B OUT70 O1 OUT70 Line of GPTAO OUT70 O2 OUT70 Line of GPTA1 OUT94 O3 OUT94 Line of LTCA2 Data Sheet 22 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function L1 P1 15 0 A1 Port 1 General Purpose I O Line 15 RDATAOB l FH MLIO Receive Channel Data Input B OUT71 O1 OUT71 Line of GPTAO OUT71 O2 OUT71 Line of GPTA1 OUT95 O3 OUT95 Line of LTCA2 Port 2 D3 P2 2 0 A1 Port 2 General Purpose I O Line 2 SLSO02 O1 PU SSCO Slave Select Output Line 2 SLSO12 O2 SSC1 Slave Select Output Li
67. DC Parameters 5 2 DC Parameters 5 2 1 Input Output Pins Table 15 Standard Pads Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Pin capacitance digital Cio CC 10 pF T 25 C inputs outputs f gt 1 MHz Pull down current ppl 150 HA Vi gt 0 6 x Vopp V CC 10 2 E uA V gt 0 36 x Vopp V Pull Up current pun 10 uA V lt 0 6 x Vopp V CC 100 uA V lt 0 36 x Vopp V Spike filter always blocked tgp CC 10 ns only PORST pin pulse duration Spike filter pass through tsr CC 100 ns only PORST pin pulse duration Table 16 Standard Pads Class A1 Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for A1 HYSAI 0 1x V pads CC Vopp Input Leakage Current Toza1 500 500 nA Vi gt 0 V Class A1 CC V lt Vbpp V Ratio Vil Vih A1 pads Via 0 6 Vinar CC Data Sheet 103 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 16 Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition On Resistance of the class A1 pad weak driver Rosonw CC 450 600 Ohm Top 0 5 mA P_MOS 210 340 Ohm Ig 0 5 mA N MOS On Resistance of the class A1 pad medium driver Rosonm CC 155 Ohm Iou gt 2 mA P MOS 110
68. DSON parameters to class B pads supply range of 1 8 V for Vopegywas removed update all current values of table 28 Power Supply Parameters rework the 3 3 V current part of the Power Supply Parameters for better description and usage Parameters ppp rp Jppri3e and Jppg an are removed and replaced in the following way Ippp rp is replaced by Jppp with the condition including flash programming current lporiac is replaced by Jppp with the condition including flash erase verify current lpprian is replaced by Jppp with the condition including flash read current parameter ppg 45 Was renamed to ppg 4 The rework of the 3 3 V current part of the Power Supply Parameters was done for simplification and clarification Former given values could still be used if liked the new definition results in the same resulting values or slightly better values The flash module is supplied via ppr a and ppp For the different flash operating modes in worst case different allocations for the two domains resulting The application typical case flash read has max Jppp of 25 mA and max ppr 4 of 98 mA resulting is a sum of 123 mA The case flash programming has max ppp of 55 mA and max ppg 4 of 29 mA resulting is a sum of 84 mA The case flash erase verify has max Ippp of 40 mA and max ppg 4 of 98 mA resulting is a sum of 138 mA So for the old parameter Jppp with 35 mA the new version reads as lppe 25 Ippp po
69. Function AE18 P15 7 y o B Port 15 General Purpose I O Line 7 Reserved O1 FB Reserved O2 Reserved O3 BC3 O Byte Control Line 3 AF20 P15 8 I O B Port 15 General Purpose I O Line 8 Reserved O1 PB Reserved O2 Reserved O3 RD O Read Control Line AF21 P15 9 0 B Port 15 General Purpose I O Line 9 Reserved O1 is Reserved O2 Reserved O3 RD WR O Write Control Line AF22 P15 10 l O B Port 15 General Purpose I O Line 10 Reserved O1 u Reserved O2 Reserved O3 ADV O Address Valid Output AE20 P15 11 0 B Port 15 General Purpose I O Line 11 WAIT l PU Wait Input for inserting Wait States Reserved O1 Reserved O2 Reserved O3 Data Sheet 75 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AF19 P15 12 0 B Port 15 General Purpose I O Line 12 Reserved O1 FB Reserved O2 Reserved O3 MR W O Motorola style Read Write Control Signal AF23 P15 13 1 0 B Port 15 General Purpose I O Line 13 Reserved O1 PB Reserved O2 Reserved O3 BAA O Burst Address Advance Output AF24 P15 14 0 B Port 15 General Purpose I O Line 14 BFCLKI l dis Burst FLASH Clock Input Clock Feedback Reserved O1 Reserved O2 Reserved O3 AF25 P15 15 I O B Port 15 General P
70. Input 35 ADC2 CH3 AE3 AN36 D S Analog Input 36 ADC2 CH4 SENTO AF2 AN37 D S Analog Input 37 ADC2 CH5 SENT1 ACA AN38 D S Analog Input 38 ADC2 CH6 SENT2 AF3 AN39 D S Analog Input 39 ADC2 CH7 SENT3 AD4 AN40 D S Analog Input 40 ADC2 CH8 SENT4 AE4 AN41 l D S Analog Input 41 ADC2 CH9 SENT5 AC5 AN42 l D S Analog Input 42 ADC2 CH10 SENT6 AF4 AN43 D S Analog Input 43 ADC2 CH11 SENT7 9 System I O B22 PORST l PD Power on Reset Input A23 ESRO VO A2 External System Request Reset Input 0 Default configuration during and after reset is open drain driver The driver drives low during power on reset Data Sheet 81 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function A22 ESR1 lO A2 External System Request Reset Input 1 PD E24 TCK l PD JTAG Module Clock Input DAPO l Device Access Port Line 0 E25 TDI l A2 JTAG Module Serial Data Input BRKIN l Fy OCDS Break Input Alternate Output BRKOUT O OCDS Break Output Alternate Input B23 TESTMODE PU Test Mode Select Input F24 TMS l A2 JTAG Module State Machine Control Input DAP1 l O FB Device Access Port Line 1 F23 TRST l PD JTAG Module Reset Enable Input G26 XTAL1 l Main Oscillat
71. L jitter of the programed duration in number of clock periods must be added separately Operating conditions apply and C 35 pF Data Sheet 159 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters Table 41 EBU Common Asynchronous Timings Parameter Symbol Values Unit Note Min Typ Max Test Condition Pulse wdih deviation from t CC 0 8 0 8 ns edge medium the ideal programmed 0 8 _ 0 8 ns edge sharp width due to B pad asymmetry rise delay fall delay AD 31 0 output delay to t CC 5 5 2 ns ADV rising edge multiplexed read write AD 31 0 output delay to t CC 5 5 2 ns ADV rising edge multiplexed read write Address valid to CS falling t CC 2 2 ns edge deviation from programmed value Address valid to ADV tig CC J 2 2 ns falling edge deviation from programmed value ADV falling edge ty7CC 2 2 ns gt CSfalling edge deviation from programmed value 1 Not subject to production test verified by design characterization Data Sheet 160 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters Table 42 EBU Asynchronous Read Timings Parameter Symbol Values Min Typ Max Unit Note Test Condition A 23 0 output delay to RD rising edge deviation from the ideal programmed value to CC 2 5 2 5 A 23 0 output delay to RD rising edg
72. Line of LTCA2 AT P0 2 I O A2 Port 0 General Purpose I O Line 2 HWCFG2 l Em Hardware Configuration Input 2 OUT58 O1 OUT58 Line of GPTAO OUT58 O2 OUT58 Line of GPTA1 OUT82 O3 OUTS82 Line of LTCA2 B8 P0 3 I O A1 Port 0 General Purpose I O Line 3 HWCFG3 l FB Hardware Configuration Input 3 OUT59 O1 OUT59 Line of GPTAO OUT59 O2 OUT59 Line of GPTA1 OUT83 O3 OUTS 3 Line of LTCA2 Data Sheet 16 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B7 P0 4 0 A1 Port 0 General Purpose I O Line 4 HWCFG4 l FH Hardware Configuration Input 4 OUT60 O1 OUT60 Line of GPTAO OUT60 O2 OUT60 Line of GPTA1 EVTOO O3 MCDS Output Event 0 A6 P0 5 I O A1 Port 0 General Purpose I O Line 5 HWCFG5 l i Hardware Configuration Input 5 OUT61 O1 OUT61 Line of GPTAO OUT61 O2 OUT61 Line of GPTA1 EVTO1 O3 MCDS Output Event 1 B6 P0 6 0 A2 Port 0 General Purpose I O Line 6 HWCFG6 l P Hardware Configuration Input 6 OUT62 O1 OUT62 Line of GPTAO OUT62 O2 OUT62 Line of GPTA1 EVTO2 03 MCDS Output Event 2 C8 P0 7 VO A1 Port 0 General Purpose I O Line 7 HWCFG7 l i Hardware Configuration Input 7 OUT63 O1 OUT63 Line of GPTAO OUT63 O2 OUT63 Line of GPTA1 EVTO3 03 MCDS Output Event 3 C7 P0 8 I O A1 Port 0 General Pur
73. O A1 Port 3 General Purpose I O Line 2 IN10 l FH IN10 Line of GPTAO IN10 l IN10 Line of GPTA1 IN10 l IN10 Line of LTCA2 T13HRE l CCU63 OUT10 O1 OUT10 Line of GPTAO OUT10 O2 OUT10 Line of GPTA1 OUT10 O3 OUT10 Line of LTCA2 B11 P3 3 l O A1 Port 3 General Purpose I O Line 3 IN11 l FB IN11 Line of GPTAO IN11 l IN11 Line of GPTA1 IN11 l IN11 Line of LTCA2 OUT11 O1 OUT11 Line of GPTAO OUT 11 O2 OUT11 Line of GPTA1 OUT 11 O3 OUT11 Line of LTCA2 Data Sheet 30 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C12 P3 4 V0 A1 Port 3 General Purpose I O Line 4 IN12 l FH IN12 Line of GPTAO IN12 l IN12 Line of GPTA1 IN12 l IN12 Line of LTCA2 T12HRE l CCU62 CC61INC l CCU62 CTRAPA l CCU63 CTRAPB l CCU60 CC60INC l CCU63 OUT12 O1 OUT12 Line of GPTAO OUT 12 O2 OUT12 Line of GPTA1 OUT12 O3 OUT12 Line of LTCA2 A11 P3 5 I O A1 Port 3 General Purpose I O Line 5 IN13 l a IN13 Line of GPTAO IN13 l IN13 Line of GPTA1 IN13 l IN13 Line of LTCA2 OUT13 O1 OUT13 Line of GPTAO OUT13 O2 OUT13 Line of GPTA1 OUT 13 O3 OUT13 Line of LTCA2 Data Sheet 31 V 1 2 2014 05 Cinfineon TES PinningTC1793 Pin Configuration
74. OUT103 Line of LTCA2 AD23 O EBU Address Data Bus Line 23 Data Sheet 70 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AD26 P14 8 0 B Port 14 General Purpose I O Line 8 AD24 l FH EBU Address Data Bus Line 24 CC61 O1 CCU61 T3OUT O2 GPT120 OUT 104 O3 OUT104 Line of LTCA2 AD24 O EBU Address Data Bus Line 24 AC25 P14 9 0 B Port 14 General Purpose I O Line 9 AD25 l Ja EBU Address Data Bus Line 25 CC62 O1 CCU61 T3OUT O2 GPT121 OUT105 O3 OUT105 Line of LTCA2 AD25 O EBU Address Data Bus Line 25 AE26 P14 10 I O B Port 14 General Purpose I O Line 10 AD26 l EM EBU Address Data Bus Line 26 COUT60 O1 CCU61 T6OUT O1 GPT120 OUT 106 O3 OUT106 Line of LTCA2 AD26 O EBU Address Data Bus Line 26 AD25 P14 11 0 B Port 14 General Purpose I O Line 11 AD27 l PU EBU Address Data Bus Line 27 COUT61 O1 CCU61 T6OUT O1 GPT121 OUT107 O3 OUT107 Line of LTCA2 AD27 O EBU Address Data Bus Line 27 Data Sheet 71 V 1 2 2014 05 Cinfineon Nav PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AC24 P14 1
75. OUT74 Line of GPTAO OUT74 O3 OUT74 Line of GPTA1 B14 P5 3 V0 A1 Port 5 General Purpose I O Line 3 TXD1 O1 PU ASC1 Transmitter Output A OUT75 O2 OUT75 Line of GPTAO OUT75 O3 OUT75 Line of GPTA1 C15 P5 4 0 A2 Port 5 General Purpose I O Line 4 T13HRB l FH CCU62 CCPOS1A l CCU63 T2EUDB l GPT120 T2EUDA l GPT121 ENOO O1 MSCO Device Select Output 0 RREADYOB 02 MLIO Receive Channel ready Output B OUT76 O3 OUT76 Line of GPTAO Data Sheet 42 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C14 P5 5 V0 A1 Port 5 General Purpose I O Line 5 SDIO l FH MSCO Serial Data Input T12HRC l CCU62 T13HRC l CCU62 CCPOS2A l CCU63 T4EUDB l GPT120 T4EUDA l GPT121 OUT77 01 OUT77 Line of GPTAO OUT77 O2 OUT77 Line of GPTA1 OUT 101 O3 OUT101 Line of LTCA2 B15 P5 6 0 A2 Port 5 General Purpose I O Line 6 CC60INA l PA CCU62 CC60INB l CCU63 EN10 O1 MSC1 Device Select Output 0 TVALIDOB O2 MLIO transmit Channel valid Output B CC60 O3 CCU62 A15 P5 7 0 A1 Port 5 General Purpose I O Line 7 SDI1 l PU MSC1 Serial Data Input CC61INA l CCU62 CC61INB l CCU63 OUT79 O1 OUT79 Line of GPTAO OUT79 O2 OUT79 Line of GPTA1 CC61 O3 CCU62 Data Sheet 43 V 1 2 2014 05 Cinfineon TC1793
76. Ohm Ig 2 mA N MOS Fall time pad type A1 tear CC 150 ns C 20 pF pin out driver weak 50 ns C7 50 pF pin out driver medium 140 ns C 7 150 pF pin out driver medium 550 ns C 7 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet 104 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 16 Standard Pads Class A1 cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Rise time pad type A1 tra CC 150 ns C 7 20 pF pin out driver weak 50 ns C 50 pF pin out driver medium 140 ns C 7 150 pF pin out driver medium 550 ns C 7 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Input high voltage class Vint 06x min V V A1 pads SR Vppp DDP 0 3 3 6 Input low voltage class A1 Vi 44 SR 0 3 0 36x V pads Voppp Data Sheet 105 V 1 2 2014 05 Cinfineon TC1793 Table 16 Electrical ParametersDC Parameters Standard Pads Class A1 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Output voltage high class A1 pads Vonat CC Vope 0 4 Io 1 4 mA pin out driver
77. On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction Four SSC Guardian SSCG modules one for each SSC Two serial Micro Second Bus interfaces MSC for serial port expansion to external power devices Two High Speed Micro Link interfaces MLI for serial inter processor communication One External Bus Interface EBU supporting different memories asynchronous memories e g SRAM peripheral devices synchronous devices e g burst NOR flash PSRAM and DDR NOR flash e g LPDDR NVM Jedec 42 2 ONFI 2 0 limited frequency at 1 8 V I O supply One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality Two General Purpose Timer Array Modules GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare 6 modules Two General Purpose 12 Timer Units GPT120 and GPT121 44 analog input lines for ADC 4 independent kernels ADCO ADC1 and ADC2 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC in
78. PT121 Reserved 01 Reserved 02 Reserved O3 A5 P0 14 I O A2 Port 0 General Purpose I O Line 14 T6INA l x GPT120 T6INB l GPT121 TXDA 01 E Ray Channel A transmit Data Output Reserved 02 Reserved O3 D4 P0 15 0 A1 Port 0 General Purpose I O Line 15 Reserved O1 FB Reserved O2 Reserved O3 Port 1 P3 P1 0 0 A2 Port 1 General Purpose I O Line 0 REQO l d External trigger Input 0 EXTCLK1 O1 External Clock Output 1 Reserved O2 Reserved O3 Data Sheet 19 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function P2 P1 1 V0 A1 Port 1 General Purpose I O Line 1 REQ1 l FH External trigger Input 1 CC60INA CCU60 CC60INB CCU61 CC60 O1 CCU60 Reserved O2 Reserved O3 P1 P1 2 I O A1 Port 1 General Purpose I O Line 2 REQ2 l External trigger Input 2 Reserved O1 Reserved O2 Reserved O3 N1 P1 3 I O A1 Port 1 General Purpose I O Line 3 REQ3 l a External trigger Input 3 TREADYOB MLIO transmit Channel ready Input B Reserved O1 Reserved O2 Reserved O3 N4 P1 4 I O A2 Port 1 General Purpose I O Line 4 TCLKO O1 PU MLIO transmit Channel Clock Output Reserved 02 Reserved O3 Data Sheet 20 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Conf
79. Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition ADC analog supply Voom 2 97 5 5 59 v voltage SR Oscillator core supply Voposc 1 17 1 3 1 439 V for duration voltage SR limitation see Section 5 1 5 1 Oscillator 3 3V supply Voposc3 2 97 3 3 3 639 V for duration voltage SR limitation see Section 5 1 5 1 Digital supply voltage for Vppp SR 2 97 3 3 3 63 5 V for duration IO pads limitation see Section 5 1 5 1 E Ray PLL core voltage Vpppr 1 17 1 3 1439 V for duration supply SR limitation see Section 5 1 5 1 E Ray PLL 3 3V supply Voppr3 2 97 J3 3 3 639 V for duration SR limitation see Section 5 1 5 1 VDDP voltage to ensure Vppppa 0 65 V defined pad states CC Digital ground voltage Vss SR O V Analog ground voltage for Vssm SR 0 1 0 0 1 V Voom Analog core supply VbpaF 1 17 1 3 1439 V for duration SR limitation see Section 5 1 5 1 FADC ADC analog Vopwr 2 97 3 3 3 635 V for duration supply voltage SR limitation see Section 5 1 5 1 Analog ground voltage for VssafF 0 1 0 0 1 V Vopmr SR 1 MA equals the modulation amp 2 Applicable for digital outputs itude in percentage times the configured PLL clock out frequency 3 Voltage overshoot to 1 7V is permissible at Power Up and PORST low provided the pulse duration is less than 100 us and the cumulated sum of the pulses does not exceed 1 h Data Sheet V 1 2 2014 05 Cinfineon rus 4
80. Purpose I O Line 14 BRKIN l PU OCDS Break Input ECTT2 l TTCAN Input REQ15 l External trigger Input 15 Reserved 01 Reserved 02 Reserved O3 BRKOUT O OCDS Break Output Port 10 AE15 P10 0 0 A2 Port 10 General Purpose I O Line 0 MRSTO l PU SSCO Master Receive Input Master Mode MRSTO O1 SSCO Slave Transmit Output Slave Mode Reserved O2 Reserved O3 Data Sheet 58 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AF15 P10 1 l O A2 Port 10 General Purpose I O Line 1 MTSRO l Pu SSCO Slave Receive Input Slave Mode MRSTGO l SSC Guardian 0 Master Receive Input Master Mode MTSRO O1 SSCO Master Transmit Output Master Mode Reserved 02 Reserved O3 AD15 P10 2 I O A1 Port 10 General Purpose I O Line 2 SLSIO l ik SSCO Slave Select Input Reserved O1 Reserved O2 Reserved O3 AF14 P10 3 0 A2 Port 10 General Purpose I O Line 3 SCLKO l j SSCO Clock Input Output SCLKO O1 SSCO Clock Input Output Reserved O2 Reserved O3 AE14 P10 4 V0 A1 Port 10 General Purpose I O Line 4 SLSOO O1 PU SSCO Slave Select Output Line 0 Reserved O2 Reserved O3 AC15 P10 5 0 A1 Port 10 General Purpose I O Line 5 SLSO1 O1 P SSCO Slave Select Output Line 1 R
81. SCO amp SSC1 Slave Select Output Line AND 7AND Slave Select Output Line 17 SLSO17 Data Sheet 24 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C2 P2 8 V0 A1 Port 2 General Purpose I O Line 8 INO l PU INO Line of GPTAO INO l INO Line of GPTA1 INO l INO Line of LTCA2 CCPOSOA l CCU62 T12HRB l CCU63 T3INB l GPT120 T3INA l GPT121 OUTO 01 OUTO Line of GPTAO OUTO 02 OUTO Line of GPTA1 OUTO 03 OUTO Line of LTCA2 A2 P2 9 0 A1 Port 2 General Purpose I O Line 9 IN1 l d IN1 Line of GPTAO IN1 l IN1 Line of GPTA1 IN1 l IN1 Line of LTCA2 OUT1 O1 OUT1 Line of GPTAO OUT1 O2 OUT1 Line of GPTA1 OUT1 O3 OUT1 Line of LTCA2 Data Sheet 25 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B3 P2 10 V0 A1 Port 2 General Purpose I O Line 10 IN2 l FH IN2 Line of GPTAO IN2 l IN2 Line of GPTA1 IN2 l IN2 Line of LTCA2 T12HRE l CCU60 CC61INC l CCU60 CTRAPA l CCU61 CTRAPB l CCU63 CC60INC l CCU61 OUT2 O1 OUT2 Line of GPTAO OUT2 O2 OUT2 Line of GPTA1 OUT2 O3 OUT2 Line of LTCA2 C3 P2
82. V SR 10 6x min V V pins Vopp DDP 0 3 3 6 Input low voltage Class V SR 0 3 0 36x V pads Vope 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Class S pad parameters are only valid for Vopy 4 75 V to 5 25 V Table 22 Standard Pads Class S Parameter Symbol Values Unit Note Min Typ Max Test Condition Input Hysteresis for class HYSS 0 3 V S pads CC Input leakage current lozs CC 300 300 nA Input voltage high Ving CC 3 6 V Input voltage low Vig CC 1 9 V Vj s Delta Viso 50 50 mV Maximum input CC low state threshold variation over 1ms Vbpp consta nt 1 Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It can t be guaranteed that it suppresses switching due to external system noise Data Sheet 119 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters 2 Vi gp is implemented to ensure J2716 specification It can t be guaranteed that it suppresses switching due to external noise Table 23 LVDS_Pads Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Output impedance pad Ro CC 40 140 Ohm class F LVDS mode Fall time
83. V Ratio Vil Vih A2 pads Vino 0 6 Vina CC On Resistance of the Rpsoww 450 600 Ohm o4 0 5 mA class A2 pad weak driver CC P MOS 210 340 Ohm ZoL lt 0 5 mA N MOS On Resistance of the RpsowM 155 Ohm Top 2 mA class A2 pad medium CC P_MOS driver j 110 Ohm g 2 mA N MOS On Resistance of the Rpsow2 28 Ohm Top 2 mA class A2 pad strong driver CC P_MOS 22 Ohm c lt 2 mA N MOS Data Sheet 110 V 1 2 2014 05 Cinfineon TC1793 Table 18 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Fall time pad type A2 ins CC 150 ns C 7 20 pF pin out driver weak ns C 50 pF edge medium pin out driver strong 10 ns C 50 pF edge medium minus pin out driver strong 3 7 ns C 50 pF edge sharp pin out driver strong ns C 50 pF edge sharp minus pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 50 pF pin out driver medium 7 5 ns C 7 100 pF edge sharp pin out driver strong 140 ns C 150 pF pin out driver medium Data Sheet 111 V 1 2 2014 05 Cinfineon Table 18 TC1793 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parameter Symbol V
84. Voltage on any Class A input Vn SR 0 7 Vppp 0 7 V Whatever pin and dedicated input pins or max 4 33 is lower with respect to Vss Voltage on any Class D VAN 0 6 7 0 V analog input pin with respect Varery to Vacnp SR Voltage on any shared Class Vaine 0 6 7 0 V D analog input pin with VEAREF respect to Vssar if the FADC SR is switched through to the pin Input current on any pin Tin 10 10 mA during overload condition Absolute maximum sum of all in 25 25 mA input circuit currents for one port group during overload condition Absolute maximum sum ofall ZI 200 200 mA input circuit currents during overload condition Data Sheet 92 V 1 2 2014 05 Cinfineon Ion Electrical ParametersGeneral Parameters 1 The port groups are defined in Table 14 Data Sheet 93 V 1 2 2014 05 Cinfineon rus Electrical ParametersGeneral Parameters 5 1 4 Pin Reliability in Overload When receiving signals from higher voltage devices low voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification Table 10 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met full operation life time 24000 h is not exceeded Operating Conditions are met for pad supply levels Vppe Voom Or Vopesu temperature If a pin current is out of the Operating Condition
85. alues Min Typ Max Unit Note Test Condition 550 ns C 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 65000 ns C 20000 pF pin out driver weak Data Sheet V 1 2 2014 05 Cinfineon TC1793 Table 18 Electrical ParametersDC Parameters Standard Pads Class A2 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Rise time pad type A2 trag CC 150 ns C 7 20 pF pin out driver weak 7 0 ns C 50 pF edge medium pin out driver strong 10 ns C 50 pF edge medium minus pin out driver strong 3 7 ns C 50 pF edge sharp pin out driver strong ns C 50 pF edge sharp minus pin out driver strong 16 ns C 50 pF edge soft pin out driver strong 50 ns C 50 pF pin out driver medium 7 5 ns C 7 100 pF edge sharp pin out driver strong 140 ns C 150 pF pin out driver medium Data Sheet 113 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 18 Standard Pads Class A2 cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition 550 ns C 150 pF pin out driver weak 18000 ns C 20000 pF pin out driver medium 6
86. am Flash SRAM DFlash Data Flash PRAM Parameter RAM in PCP ws WS cs CMEM Code RAM in PCP XBAR SRI Cross Bar XBar SRI C Bar Intt ct SRI S On Chip Bus Slave Interface ross Bar Interconnect SRI gt XBAR M On Chip Bus Master Interface OCDS L1 Debug Bridge DMA Interface JTAG 16 channels 2MB PFlash 2 MB PFlash SFI MemCheck 192 KB DFlash 16 KB BROM KeyFlash 2 7 MLI Interrupt SDMA ASC System 8 channels gt a4 2 E SSC CE 2 d STM 4 E SSCG SSC Guardian SBCU BMU Ee 2 Channels r li SENT 8 channels wT GPT120 GPTAO 2 T SCU FM PLL EN GPTA1 PLL ERAY LTCA2 System Peripheral Bus SPB 7 MultiCAN External 4Nodes 128 MO 2 CCUS Request Unit 2xCCU6 FCE 33V max Ext FADC Supply TC1793 Figure 1 Block Diagram Data Sheet 11 V 1 2 2014 05 Infineon Tev System Overview of the TC1793Block Diagram Figure 2 shows the block diagram of the SAK TC1793N 512F270EF TriCore CPU Abbreviations ICACHE Instruction Cache DCACHE Data Cache PSPR Program ScratchPad RAM DSPR Data ScratchPadl Data RAM BROM Boot ROM PFlash Program Flash DFlash Data Flash PRAM Parameter RAM in PCP CMEM Code RAM in PCP XBAR SRI Cross Bar XBar SRI Em On Chip Bus Slave Interface LN On Chip
87. ameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1793 and partly its requirements on the system To aid interpreting the parameters easily when evaluating them for a design they are marked with an two letter abbreviation in column Symbol e CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1793 and must be regarded for a system design SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1793 designed in Data Sheet 90 V 1 2 2014 05 Cinfineon 5 1 2 TC1793 Electrical ParametersGeneral Parameters Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics More details mainly DC parameters are defined in the Section 5 2 1 Table 8 Pad Driver and Pad Classes Overview Class Power Type Sub Class Speed Load Leakage Termination Supply Grade 1500C 1 A 3 3 V LVTTL A1 6 MHz 100 pF 500 nA No I O e g GPIO LVTTL Au 25 50 pF 1 pA Series outputs e g serial MHz termination I Os recommended A2 40 50 pF 3 pA Series e g serial MHz termination I Os recommended B 3 3 V LVTTL 75 35 pF 6 uA Series I O MHz termination 2 5 V 75 35 pF recommended MHz F 3 3 V LVDS 50 Parallel MHz termination 100 Q 10 CMOS 6 MHz 5
88. cterization BFCLKO oM tN by by HLDA Output ty t NT BREQ Output BFCLKO HOLD Input HLDA Input EBUArb 1 Figure 30 EBU Arbitration Signal Timing Data Sheet 171 V 1 2 2014 05 Cinfineon TC1793 5 4 Electrical ParametersFlash Memory Parameters Flash Memory Parameters The data retention time of the TC1793 s Flash memory depends on the number of times the Flash memory has been erased and programmed Table 46 FLASH32 Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Data Flash Erase Time fgg5 CC 4 2D js per Sector Program Flash Erase terr CC 5 S Time per 256 KByte Sector Program time data flash tpgp CC z 5 3 ms without per page reprogramming 15 9 ms with two reprogramming cycles Program time program tprp CC 5 3 ms without flash per page reprogramming 10 6 ms with one reprogramming cycle Data Flash Endurance NgCC 160000 cycle Min data 4 S retention time 5 years Erase suspend delay FL_ErSusp 15 ms CC Wait time after margin fe Margin 10 _ us change Del CC Program Flash Retention tpe CC 20 year Max 1000 Time Physical Sector S erase program cycles Program Flash Retention tge7 CC 20 year Max 100 Time Logical Sector 9 S erase program cycles UCB Retention Time 9 tary CC 20 year Max
89. d 4 Although not necessary it is additionally recommended that all power supplies are powered up down together in a controlled way as tight to each other as possible Additionally regarding the ADC reference voltage VAREF VAREF must power up at the same time or later then VDDM and VAREF must power down either earlier or at latest to satisfy the condition VAREF VDDM 0 5 V This is required in order to prevent discharge of VAREF filter capacitance through the ESD diodes through the VDDM power supply In case of discharging the reference capacitance through the ESD diodes the current must be lower than 5 mA Data Sheet 139 V 1 2 2014 05 Cinfineon Tels Electrical ParametersAC Parameters 5 3 3 Power Pad and Reset Timing Table 30 Reset Timings Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Application Reset Boot tg CC 960 uS fopy 270 MHz Time 1140 lus fopy 200 MHz Power on Reset Boot tgp CC 2 5 ms Time HWCFG pins hold time tupou SR 16 _ ns from ESRO rising edge femi HWCFG pins setup time to ps SR 0 s x ns ESRO rising edge Ports inactive after ESRO tp CC 8 fep ns reset active Ports inactive after fpp CC 150 ns PORST reset active Minimum PORST active fpo SR 10 B ms time after power supplies are stable at operating levels TESTMODE TRST hold tpo4 SR 100 ns time from PORST ris
90. define the modulation properties 10 _ fosc MODFREQ x 31 32 MOD Pp MODAMP 11 MODAMP MA ee N x 161 Data Sheet 144 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters 5 3 5 ERAY Phase Locked Loop ERAY_PLL Table 32 PLL_ERAY Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Accumulated jitter at Dpp CC 0 8 0 8 ns SYSCLK pin Accumulated Jitter Dp CC 0 5 a 0 5 ns PLL Base Frequency of fpitsase_ 50 250 360 MHz the ERAY PLL eray CC VCO input frequency of frer CC 20 x 40 MHz the ERAY PLL VCO frequency range of fico era 450 500 MHz the ERAY PLL y CC PLL lock in time t CC 5 6 200 us Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF with the maximum driver and sharp edge Note The maximum peak to peak noise on the pad supply voltage measured between Vpppra and Vespr is limited to a peak to peak voltage of Vpp 100 mV for noise frequencies below 300 KHz and Vpp 40 mV for noise frequencies above 300 KHz These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes Data Sheet 145 V 1 2 2014 05 Cinfineon rus Electrical ParametersAC Parameters 5 3 6 JTAG Interface Timing The following parameters are applicable for comm
91. e deviation from the ideal programmed value t4 CC 2 5 ns CS rising edge to RD rising edge deviation from the ideal programmed value t CC 2 5 ns ADV rising edge to RD rising edge deviation from the ideal programmed value tz CC 1 5 4 5 ns BC rising edge to RD rising edge deviation from the ideal programmed value t CC 2 5 ns WAIT input setup to RD rising edge deviation from the ideal programmed value fs SR 12 ns WAIT input hold to RD rising edge deviation from the ideal programmed value te SR ns Data input setup to RD rising edge deviation from the ideal programmed value t SR 12 ns Data Sheet 161 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters Table 42 EBU Asynchronous Read Timings cont d Parameter Symbol Values Min Typ Max Unit Note Test Condition Data input hold to RD rising edge deviation from the ideal programmed value tz SR ns MR W output delay to RD rising edge deviation from the ideal programmed value to CC 1 5 ns Data input hold from CS rising edge tig CC ns Data input setup to CS rising edge tig CC 12 ns 1 Not subject to production test verified by design characterization Data Sheet 162 V 1 2 2014 05 Infineon TC179
92. e I O Line 10 IN18 l EH IN18 Line of GPTAO IN18 l IN18 Line of GPTA1 IN18 l IN18 Line of LTCA2 CCPOS1A l CCU62 T13HRB l CCU63 T3EUDB l GPT120 T3EUDA l GPT121 OUT18 O1 OUT18 Line of GPTAO OUT18 O2 OUT18 Line of GPTA1 OUT18 O3 OUT18 Line of LTCA2 D13 P3 11 0 A1 Port 3 General Purpose I O Line 11 IN19 l PU IN19 Line of GPTAO IN19 l IN19 Line of GPTA1 IN19 l IN19 Line of LTCA2 OUT19 01 OUT19 Line of GPTAO OUT19 02 OUT19 Line of GPTA1 OUT19 O3 OUT19 Line of LTCA2 Data Sheet 33 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function D11 P3 12 V0 A1 Port 3 General Purpose I O Line 12 IN20 l PU IN20 Line of GPTAO IN20 l IN20 Line of GPTA1 IN20 l IN20 Line of LTCA2 CCPOS2A l CCU62 T12HRC l CCU63 T13HRC l CCU63 T4INB l GPT120 T4INA l GPT121 OUT20 01 OUT20 Line of GPTAO OUT20 02 OUT20 Line of GPTA1 OUT20 O3 OUT20 Line of LTCA2 D12 P3 13 I O A1 Port 3 General Purpose I O Line 13 IN21 l a IN21 Line of GPTAO IN21 l IN21 Line of GPTA1 IN21 l IN21 Line of LTCA2 OUT21 01 OUT21 Line of GPTAO OUT21 02 OUT21 Line of GPTA1 OUT21 03 OUT21 Line of LTCA2 Data Sheet 34 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration
93. e conditions for LVDS pad parameters as loads are defined by interface MSC timings add parameter Vj sp for class S pads add Vbpm supply limitation for class S parameters add footnote 10 to table 23 ADC parameters remove old footnote 2 from table 24 FADC parameters remove term typical from load of Peripheral Timings add definition of driver strength settings for ERAY Interface Timing update formulas for frequency modulation change SSC parameter from tg CC to SR add figures for EBU Multiplexer and Demultiplexed Write Access change footnote 4 wording for ERAY timing back to TC1797 wording increase flash parameters tprp and tppp values increase flash parameter terp add section 5 2 6 1 change in legende of table 2 definition of class S pad remove condition for Vopegy correct section Extended Range Operating Conditions for the 3 3 V area increase limit in Extended Range Operating Conditions from 1 hour to 1000 hours Data Sheet 2 V 1 2 2014 05 Cinfineon ru History specify wording for limitation of pad performance in section Extended Range Operating Conditions remove incorrect test conditions for RDSONx parameters remove ADC 3 from ADC parameters adjust typo in temperature profile removed RDSON parameters for class F pads weak driver as only medium is available e add parameter fsysp for the SYSPLL changed RDSON values for class F pads updated class B pads rise and fall times definitions e add R
94. elay from dTxdly 10 0 ns Px PDR PDy sampling flip flop CC 000 15 0 ns Px_PDR PDy 001 RxD capture delay by dRxdly 10 0 ns sampling flip flop CC 1 This includes the PLL_ERAY accumulated jitter 2 Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers Quarz tolerance and PLL_ERAY accumulated jitter are not included 3 E Ray TxD output drivers have an asymmetry of rising and falling edges of teno tral lt 1 ns 4 Limits of 966ns and 1046 1ns correspond to 30 70 Vppp FlexRay standard input thresholds For input thresholds of this product a correction of 0 5 ns and 0 1 ns has to be applied Data Sheet 157 V 1 2 2014 05 Infineon Tels Electrical ParametersAC Parameters 5 Valid for output slopes of the bus driver of dRxSlope x 5ns 20 Vppp to 80 Vppp according to the FlexRay Electrical Physical Layer Specification V2 1B For A2 pads the rise and fall times of the incoming signal have to satisfy the following inequality 1 6ns lt frag fraz lt 1 3ns 6 Valid for output slopes of the bus driver of dRxSlope x 5ns 20 Vppp to 80 Vppp according to the FlexRay Electrical Physical Layer Specification V2 1B For A2 pads the rise and fall times of the incoming signal have to satisfy the following inequality 1 6ns lt teas traz lt 1 3ns BSS Last CRC Byte FES Byte Start Sequence Frame End Seque
95. ernel 1 The SAK TC1793N 512F270EF has the following features High performance 32 bit super scalar TriCore V1 6 CPU with 6 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Multiply accumulate unit able to sustain 2 MAC operations per cycle Fully pipelined Floating point unit FPU 270 MHz operation at full temperature range e 32 bit Peripheral Control Processor with single cycle instruction PCP2 16 Kbyte Parameter Memory PRAM 32 Kbyte Code Memory CMEM 200 MHz operation at full temperature range Multiple on chip memories 4 Mbyte Program Flash Memory PFLASH with ECC 192 Kbyte Data Flash Memory DFLASH usable for EEPROM emulation 2x8 Kbyte Key Flash Data Sheet 4 V 1 2 2014 05 Cinfineon Tene Summary of Features 128 Kbyte Data Scratch Pad RAM DSPR 16 Kbyte Instruction Cache ICACHE 32 Kbyte Instruction Scratch Pad RAM PSPR 16 Kbyte Data Cache DACHE 128 Kbyte Memory SRAM 16 Kbyte BootROM BROM 16 Channel DMA Controller e 8 Channel Safe DMA SDMA Controller e Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Cross Bar Interconnect between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge SFI Bridge Versatile
96. eserved O2 Reserved O3 Data Sheet 59 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function Port 11 J26 P11 0 0 B Port 11 General Purpose I O Line 0 Reserved O1 Nu Reserved O2 Reserved O3 AO O EBU Address Bus Line 0 K25 P11 1 0 B Port 11 General Purpose I O Line 1 Reserved O1 ve Reserved O2 Reserved O3 A1 O EBU Address Bus Line 1 K26 P11 2 V0 B Port 11 General Purpose I O Line 2 Reserved O1 ce Reserved O2 Reserved O3 A2 O EBU Address Bus Line 2 J23 P11 3 0 B Port 11 General Purpose I O Line 3 Reserved O1 PH Reserved O2 Reserved O3 A3 O EBU Address Bus Line 3 K24 P11 4 0 B Port 11 General Purpose I O Line 4 Reserved O1 EE Reserved O2 Reserved O3 A4 O EBU Address Bus Line 4 Data Sheet 60 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function L25 P11 5 0 B Port 11 General Purpose I O Line 5 Reserved O1 FB Reserved O2 Reserved O3 A5 O EBU Address Bus Line 5 L26 P11
97. eters Table 24 ADC Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition ON resistance forthe ADC RAy 180 550 900 Ohm test pull down for AIN7 CC Resistance of the Rarer E 500 1000 Ohm reference voltage input CC path Sample time tg CC 2 257 Tapci Calibration time after bit tea CC E 4352 cycle ADC_GLOBCFG SUCAL S is set Total Unadjusted TUE CC 4 419 LSB ADC Error9915 resolution 12 bit Analog reference ground Vaguno Vssm Varerx V SR 0 05 1 Analog input voltage Vain SR Vacnpx Varerx V Analog reference voltage Varerx Vacnpx Vppm V SR 1 0 05 9 16 Analog reference voltage Varerx Vpp2 Voom V range99 VAGNDx 0 05 SR 1 7 oOo 10 The sampling capacity of the conversion C network is pre charged to V4gge 2 before the sampling moment Because of the parasitic elements the voltage measured at AINx can deviate from Vaper 2 Applies to AINx when used as auxiliary reference input This represents an equivalent switched capacitance This capacitance is not switched to the reference voltage at once Instead smaller capacitances are successively switched to the reference voltage The sum of DNL INL GAIN OFF errors does not exceed the related TUE total unadjusted error If a reduced analog reference voltage between 1V and Vppy 2 is used then there
98. evices synchronous devices e g burst NOR flash PSRAM and DDR NOR flash e g LPDDR NVM Jedec 42 2 ONFI 2 0 limited frequency at 1 8 V I O supply One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality One FlexRay module with 2 channels E Ray Two General Purpose Timer Array Modules GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare 6 modules Two General Purpose 12 Timer Units GPT120 and GPT121 44 analog input lines for ADC 4 independent kernels ADCO ADC1 and ADC2 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fgapnc clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 8 digital input lines for SENT communication according to the SENT specification J2716 FEB2008 221 digital general purpose I O lines GPIO Digital I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Buses Dedicated Emulation Device chip
99. from FCLP rising edge driver and sharp minus edge 2 10 ns ENx with strong driver and medium minus edge 0 21 ns ENx with strong driver and soft edge SDI bit time fag CC 8x 2 ns Tusc Data Sheet 152 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters Table 37 MSC Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition SDI rise time tag SR 200 ns SDI fall time fag SR 200 ns 1 FCLP signal rise fall times are only defined by the pad rise fall times 2 FCLP signal high and low can be minimum 1xTysc 3 TMSC TSYS 1 fSYS 4 SOP FCLP either propagated by LVDS or by CMOS strong driver and non soft edge 0 9 FCLP Voor 0 1 Vipp SOP EN SDI MSC_Tmg_1 vsd Figure 20 MSC Interface Timing Note The data at SOP should be sampled with the falling edge of FCLP in the target device Data Sheet 153 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters 5 3 10 SSC Master Slave Mode Timing The SSC parameters are vaild for C 50 pF and strong driver medium edge Table 38 SSC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition SCLK clock period 79 fg CC 2x1 ns frei MTSR SLSOx delay form fs CC O 8 ns SCLK rising edge MRST setup to SCLK fg SR 16 5 ns latchin
100. g edge MRST hold from SCLK ts SR JO i ns latching edge SCLK input clock t4 SR 4x1 x ns period eri SCLK input clock duty fos fg 45 55 cycle SR MTSR setup to SCLK ts SR 1 fee ns latching edge MTSR hold from SCLK te SR M fep ns latching edge 5 SLSI setup to first SCLK ts SR 1 fep ns latching edge 5 SLSI hold from last SCLK ts SR 7 ns latching edge MRST delay from SCLK fe CC O 16 5 ns shift edge SLSI to valid data on tg CC 16 5 ns MRST 1 SCLK signal rise fall times are the same as the rise fall times of the pad 2 SCLK signal high and low times can be minimum 1xTSSC 3 TSSCmin TSYS 1 fSYS 4 Fractional divider switched off SSC internal baud rate generation used Data Sheet 154 V 1 2 2014 05 Infineon Tels Electrical ParametersAC Parameters 5 For CON PH 1 slave select must not be removed before the following shifting edge This mean that what ever is configured shifting latching first SLSI must not be de actived before the last trailing edge from the pair of shifting latching edges SCLK MTSR 1 This timing is based on the following setup CON PH CON PO 0 2 The transition at SLSOn is based on the following setup SSOTC TRAIL 0 and the first SCLK high pulse is in the first one of a transmission SSC_TmgMM Figure 21 SSC Master Mode Timing Data Sheet 155 V 1
101. gital Output FCLPOB O3 MSCO Clock Output Data Sheet 56 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function A21 P9 9 I O A1 Port 9 General Purpose I O Line 9 SENTO FE SENT Digital Input Reserved O1 SENTO O2 SENT Digital Output Reserved O3 B21 P9 10 I O A1 Port 9 General Purpose I O Line 10 EMGSTOP is Emergency Stop SENT7 SENT Digital Input COUT63 O1 CCU63 SENT7 O2 SENT Digital Output Reserved O3 C21 P9 11 0 A1 Port 9 General Purpose I O Line 11 SENT2 ce SENT Digital Input Reserved O1 SENT2 O2 SENT Digital Output Reserved O3 D21 P9 12 lO A1 Port 9 General Purpose I O Line 12 SENT5 BH SENT Digital Input Reserved O1 SENT5 O2 SENT Digital Output Reserved O3 Data Sheet 57 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C26 P9 13 I O A2 Port 9 General Purpose I O Line 13 BRKIN l FH OCDS Break Input ECTT1 l TTCAN Input Reserved 01 Reserved 02 Reserved O3 BRKOUT O OCDS Break Output D26 P9 14 I O A2 Port 9 General
102. he ideal programmed value MR W output delay to tag CC 2 5 E 1 5 ns WR rising edge deviation from the ideal programmed value 1 Not subject to production test verified by design characterization Data Sheet 166 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters EBU STATE Control Bitfield Duration Limits in EBU_CLK Cycles 23 0 CS 3 0 ADV BC 3 0 WAIT AD 31 0 Address Phase ADDRC 1 15 VN Address Hold Phase opt AHOLDC 0 15 Command Phase RDWAIT 1 31 Data Hold Phase DATAC 0 15 pv bo Recovery New Addr Phase opt Phase ADDRC RDRECOVC 0 15 7 V V Next XK Valid Address KX Adar 1 15 Dv t DV ls t 4 wap D bs PV b7 be Ce jT Tesu cix sum correponding bitfield values DV t Id th i pv bo CSCOMB MRIW X pv be pv programmed value new_MuxWR_Async_10 vsd Figure 27 Data Sheet Multiplexed Write Access 167 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters EBU STATE Duration Limits in EBU_CLK Cycles A 23 0 CS 3 0 ADV WAIT AD 31 0 Address Phase 3 15 V Y Address Hold Phase opt 0 15 Data Hold Phase Command Phase
103. ifferential Driver Serial Data Output Positive A OUT85 O2 OUTS 5 Line of GPTAO OUT85 O3 OUTS85 Line of GPTA1 B17 P5 14 V0 F Port 5 General Purpose I O Line 14 FCLN1 O1 PU MSC1 Differential Driver Clock Output Negative OUT86 O2 OUTS86 Line of GPTAO OUT86 O3 OUTS86 Line of GPTA1 A17 P5 15 l O F Port 5 General Purpose I O Line 15 FCLNP1A O1 FB MSC1 Differential Driver Clock Output Positive A OUT87 O2 OUTS 7 Line of GPTAO OUT87 O3 OUT87 Line of GPTA1 Port 6 F3 P6 4 I O A1 Port 6 General Purpose I O Line 4 MTSR1 l Bn SSC1 Slave Receive Input Slave Mode MRSTG1 l SSC Guardian 1 Master Receive Input Master Mode MTSR1 01 SSC1 Master Transmit Output Master Mode Reserved O2 Reserved O3 Data Sheet 45 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function G4 P6 5 0 A1 Port 6 General Purpose I O Line 5 MRST1 l FH SSC1 Master Receive Input Master Mode MRST1 O1 SSC1 Slave Transmit Output Slave Mode Reserved O2 Reserved O3 E3 P6 6 I O A1 Port 6 General Purpose I O Line 6 SCLK1 l FB SSC1 Clock Input Output SCLK1 O1 SSC1 Clock Input Output Reserved O2 Reserved O3 G3 P6 7 0 A1 Port 6 General Purpose I O Line 7 SLSI1 l dis SSC1 slave Select Input T6OFL O1 GPT120 Reserved O2 Rese
104. iguration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function M4 P1 5 0 A1 Port 1 General Purpose I O Line 35 TREADYOA FH MLIO transmit Channel ready Input A Reserved O1 Reserved O2 Reserved O3 N3 P1 6 I O A2 Port 1 General Purpose I O Line 6 TVALIDOA O1 PR MLIO transmit Channel valid Output A SLSO10 O2 SSC1 Slave Select Output Line 10 COUT60 O3 CCU60 N2 P1 7 0 A2 Port 1 General Purpose I O Line 7 CC61INB l EN CCU60 CC61INA l CCU61 TDataO O1 MLIO transmit Channel Data Output CC61 O2 CCU61 T3OUT O3 GPT120 M3 P1 8 I O A1 Port 1 General Purpose I O Line 8 RCLKOA l m MLIO Receive Channel Clock Input A OUT64 O1 OUT64 Line of GPTAO OUT64 O2 OUT64 Line of GPTA1 OUT88 O3 OUTS6 Line of LTCA2 M2 P1 9 I O A2 Port 1 General Purpose I O Line 9 RREADYOA O1 FH MLIO Receive Channel ready Output A SLSO11 O2 SSC1 Slave Select Output Line 11 OUT65 O3 OUT65 Line of GPTAO Data Sheet 21 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function M1 P1 10 0 A1 Port 1 General Purpose I O Line 10 RVALIDOA l FH MLIO Receive
105. ilities Flexible interconnections to external components Flexible power management The TC1793 is a high performance microcontroller with TriCore CPU program and data memories buses bus arbitration an interrupt controller a peripheral control processor and a DMA controller and several on chip peripherals The TC1793 is designed to meet the needs of the most demanding embedded control systems applications where the competing issues of price performance real time responsiveness computational power data bandwidth and power consumption are key design elements The TC1793 offers several versatile on chip peripheral units such as serial controllers timer units and Analog to Digital converters Within the TC1793 all these peripheral units are connected to the TriCore CPU system via the Flexible Peripheral Interconnect FPI Bus and the Cross Bar Interconnect SRI Several I O lines on the TC1793 ports are reserved for these peripheral units to communicate with the external world Data Sheet 10 V 1 2 2014 05 Infineon neues System Overview of the TC1793Block Diagram 2 1 Block Diagram Figure 1 shows the block diagram of the SAK TC1793F 512F270EF SAK TC1793F 512F200EF SAK TC1793F 512F200EB Abbreviations ICACHE Instruction Cache PMI DMI DCACHE Data Cache Imu PSPR Program ScratchPad RAM DIEPSPR TriCore 428 KB DSPR DSPR Data ScratchPadl Data RAM CPU BROM Boot ROM 16 KB ICACHE 16 KB DCACHE sale PFlash Progr
106. in Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function K1 P8 7 V0 A1 Port 8 General Purpose I O Line 7 IN47 l FH IN47 Line of GPTAO IN47 l IN47 Line of GPTA1 RDATA1A l MLI1 Receive Channel Data Input A SENT7 l SENT Digital Input OUT47 O1 OUT47 Line of GPTAO COUT61 O2 CCU61 T6OUT 03 GPT121 Port 9 A19 P9 0 0 A2 Port 9 General Purpose I O Line 0 IN48 l PU IN48 Line of GPTAO IN48 l IN48 Line of GPTA1 COUT63 O1 CCU62 OUT48 O2 OUt48 Line of GPTA1 EN12 O3 MSC1 Device Select Output 2 B19 P9 1 I O A2 Port 9 General Purpose I O Line 1 IN49 l PU IN49 Line of GPTAO IN49 l IN49 Line of GPTA1 CC60INB l CCU62 CC60INA l CCU63 CC60 O1 CCU63 OUT49 O2 OUT49 Line of GPTA1 EN11 O3 MSC1 Device Select Output 1 Data Sheet 54 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B20 P9 2 I O A2 Port 9 General Purpose I O Line 2 IN50 l FH IN50 Line of GPTAO IN50 l IN50 Line of GPTA1 CC61INB l CCU62 CC61INA l CCU63 CC61 O1 CCU63 OUT50 O2 OUT50 Line of GPTA1 SOP1B O3 MSC1 serial Data Output A20 P9 3 0 A2 Port 9 General Purpose I O Line 3
107. ing edge PORST rise time tpor SR 50 ms TESTMODE TRST tpos SR 0 ns setup time to PORST rising edge Application Reset inactive tpo app 409 us after PORST deassertion SR 1 The duration of the boot time is defined between the rising edge of the internal application reset and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts 2 The given time includes the time of the internal reset extension for a configured value of SCU RSTCNTCON RELSA 0x05BE 3 The duration of the boot time is defined between the rising edge of the PORST and the clock cycle when the first user instruction has entered the CPU pipeline and its processing starts Data Sheet 140 V 1 2 2014 05 Infineon Tels Electrical ParametersAC Parameters 4 The given time includes the internal reset extension time for the System and Application Reset which is visible through ESRO 5 This parameter includes the delay of the analog spike filter in the PORST pad 6 Application Reset is assumed not to be extended from external otherwise the time extends by the time the Application Reset is extended ia 4 1490 VENE Voor 12 VDDP VobPPA VDD toon Vo 12 PORST f 2 f 7 a tPoH tPoH TRST TESTMODE ESRO HWCFG Pads Pad state undefined Tri state or pull device active
108. ingTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function G2 P6 13 I O A2 Port 6 General Purpose I O Line 13 TXDCAN2 O1 FH CAN Node 2 Transmitter Output TXDA 02 E Ray Channel A transmit Data Output 2 COUT62 O3 CCU60 F1 P6 14 0 A1 Port 6 General Purpose I O Line 14 RXDCANS3 l ce CAN Node 3 Receiver Input 0 CAN Node 2 Receiver Input 1 RXDB1 E Ray Channel B Receive Data Input 1 2 Reserved O1 Reserved O2 COUT63 O3 CCU60 G1 P6 15 I O A2 Port 6 General Purpose I O Line 15 CC60INB l PH CCU60 CC60INA l CCU61 TXDCAN3 O1 CAN Node 3 Transmitter Output TXDB 02 E Ray Channel B transmit Data Output 2 CC60 O3 CCU61 Port 7 R3 P7 0 l O A1 Port 7 General Purpose I O Line 0 MRST3 l BR SSC3 Master Receive Input Slave Mode REQ4 l External trigger Input 4 AD2EMUX2 01 ADC2 external multiplexer Control Output 2 MRST3 O2 SSC3 Slave Transmit Output Maste Mode Reserved O3 Data Sheet 48 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function R2 P7 1 I O A1 Port 7 General Purpose I O Line 1 REQ5 l FH Ex
109. ions cont d Pin Symbol Cirl Type Function P10 P11 P12 P13 P14 P15 P16 P17 Vs S Digital Ground center balls cont d R10 R11 R12 R13 R14 R15 R16 R17 Digital Ground center balls cont d T10 T11 T12 T13 T14 T15 T16 T17 Digital Ground center balls cont d U10 U11 U12 U13 U14 U15 U16 U17 Digital Ground center balls cont d Data Sheet 86 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function A1 N C Not connected These pins are reserved for AF1 future extension and shall not be connected AF26 externally A24 C22 AC21 AD23 AE22 AE23 Only applicable in TC1793ED Reserved in TC1793PD won The MTSR output of SSCx is overlayed with the MRSTG input of the related SSCGx 4 Only available for SAK TC1793F 512F270EF SAK TC1793F 512F200EF and SAK TC1793F 512F200EB Analog Input overlayed with a SENT Digitial Input The related port logic is used configure the input as either analog input default after reset or digital input The related port logic supports only the port input features as the connected pads are input pads only 5 10Z1 valid for this pin is the parameter with overlayed No in the ADC parameter table 6 IOZ1 valid for this pi
110. ition Input current at VFAREF I FAREF CC 120 HA Input leakage current at VFAREF I FOZ2 CC 500 500 nA VearerS VDDMF V Vearer 0 V Input leakage current at VFAGND Trozs CC 500 500 nA DNL error EF on CC LSB Vin mode differential Gain 1 or 2 LSB Vin mode differential Gain 4 or 82 LSB Vin mode single ended Gain 1 or 2 2 LSB Vin mode single ended Gain 4 or 8 GRADient error EF rap CC Vin mode differential Gain lt 4 Vin mode single ended Gains 4 Vin mode differential Gain 8 Vin mode single ended Gain 8 Data Sheet 126 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersDC Parameters Table 26 FADC Parameters cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition INL error EF we 4 i 4 LSB Vn mode CC differential 4 4 LSB Vn mode single ended Offset error EF ore 90 90 mV Vi mode CC differential Calibration No 90 90 mV Vix mode single ended Calibration No 20 20 mV Vix mode differential Calibration Ye s 3 4 20 20 mV Viy mode single ended Calibration Ye s 3 4 Error of commen mode EF per 60 60 mV voltage Vearer 2 CC Channel amplifier cutoff fcorr 2 MHz frequency
111. k periods Table 36 MLI Transmitter Parameter Symbol Values Unit Note Min Typ Max Test Condition TCLK clock period tip CC 2x1 ns S TCLK high time t CC 045x 0 5x 0 55x ns Ko tio tio TCLK low time ti CC 045x 0 5x 0 55x ns tio tio tio TCLK rise time ta CC 0 3x jns tio TCLK fall time n CC 0 3x ns hg Data Sheet 151 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters Table 36 MLI Transmitter cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition TDATA TVALID output ta CC 3 4 4 ns delay time TREADY setup time tig SR 18 ns before TCLK rising edge TREADY hold time after t 4 SR 2 ns TCLK rising edge 1 The following formula is valid t11 t12 t10 2 The min max TCLK low high times t11 t12 include the PLL jitter of fSYS Fractional divider settings must be regarded additionally to t11 t12 3 For high speed MLI interface strong driver sharp or medium edge selection class A2 pad is recommended for TCLK 5 3 9 Micro Second Channel MSC Interface Timing The MSC parameters are vaild for C 50 pF Table 37 MSC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition FCLP clock period ta CC 2x ns Tusc SOP ENx outputs delay j CC 2 5 ns ENx with strong
112. n is the parameter with overlayed Yes in the ADC parameter table Legend for Table 2 Column Cirl Input for GPIO port lines with IOCR bit field selection PCx OXXXg O Output O0 Output with IOCR bit field selection PCx 1X00 O1 Output with IOCR bit field selection PCx 1X01 ALT1 O2 Output with IOCR bit field selection PCx 1X10 ALT2 OS Output with IOCR bit field selection PCx 1X11 ALT3 Column Type A1 Pad class A1 LVTTL A1 Pad class A1 LVTTL A2 Pad class A2 LVTTL B Pad class B LVTTL F Pad class F LVDS CMOS D Pad class D ADC S Pad class S SENT PU with pull up device connected during reset PORST 0 PD with pull down device connected during reset PORST 0 TR tri state during reset PORST 0 Data Sheet 87 V 1 2 2014 05 TC1793 Cinfineon 4 Identification Registers Identification Registers The Identification Registers uniquely identify the whole device Table 3 SAK TC1793F 512F270EF Identification Registers Short Name Value Address Stepping CBS_JDPID 0000 6350 F000 0408 AB CBS_JTAGID 1018 E083 F000 0464 AB SCU_CHIPID 8700 9702 F000 0640 AB SCU_MANID 0000 1820 F000 0644 AB SCU_RTID 0000 0000 F000 0648 AB Table 4 SAK TC1793F 512F200EF Identification Registers Short Name Value Address Stepping
113. nce sample TXD BSS Last CRC Byte FES Byte Start Sequence Frame End Sequence RXD ERAY TIMING Figure 23 ERAY Timing Data Sheet 158 V 1 2 2014 05 Cinfineon Tels Electrical ParametersAC Parameters 5 3 12 EBU Timings 5 3 12 1 BFCLKO Output Clock Timing Vss 0 V Vop 1 3 V 596 Vopepy 2 5 V 5 and 3 3 V 596 C 35 pF Table 40 BFCLKO Output Clock Timing Parameters Parameter Symbol Values Unit Note Min Typ Max Test Con dition BFCLKO clock period terc ko CC 13 33 ns BFCLKO high time te CC 3 ns BFCLKO low time te CC 3 ns BFCLKO rise time ty CC 3 ns BFCLKO fall time fe cc 3 ns BFCLKO duty cycle tj r t DC 35 50 55 1 Not subject to production test verified by design characterization 2 The PLL jitter characteristics add to this value according to the application settings See the PLL jitter parameters 3 The PLL jitter is not included in this parameter If the BFCLKO frequency is equal to fcpy the K divider has to be regarded BFCLKO BFCLKO 0 5 Voppos MCT04883_mod Figure 24 BFCLKO Output Clock Timing 5 3 12 2 EBU Asynchronous Timings Vss 0 V Vbo 1 3 V 596 Vppggu 2 5 V 5 and 3 3 V 5 Class B pins C 35 pF for address data C 40pF for the control lines For each timing the accumulated PL
114. ne 12 SLSO02 O3 SSCO amp SSC1 Slave Select Output Line 2 AND AND Slave Select Output Line 12 SLSO12 D2 P2 3 0 A1 Port 2 General Purpose I O Line 3 SLSO03 O1 EH SSCO Slave Select Output Line 3 SLSO13 O2 SSC1 Slave Select Output Line 13 SLSO03 O3 SSCO amp SSC1 Slave Select Output Line 3 AND AND Slave Select Output Line 13 SLSO13 D1 P2 4 0 A1 Port 2 General Purpose I O Line 4 SLSO04 O1 x SSCO Slave Select Output Line 4 SLSO14 O2 SSC1 Slave Select Output Line 14 SLSO04 O3 SSCO amp SSC1 Slave Select Output Line 4 AND AND Slave Select Output Line 14 SLSO14 Data Sheet 23 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function C1 P2 5 0 A1 Port 2 General Purpose I O Line 5 SLSO05 O1 FH SSCO Slave Select Output Line 5 SLSO15 O2 SSC1 Slave Select Output Line 15 SLSO05 O3 SSCO amp SSC1 Slave Select Output Line 5 AND AND Slave Select Output Line 15 SLSO15 B1 P2 6 0 A1 Port 2 General Purpose I O Line 6 SLSO06 O1 rH SSCO Slave Select Output Line 6 SLSO16 O2 SSC1 Slave Select Output Line 16 SLSO06 O3 SSCO amp SSC1 Slave Select Output Line 6 AND AND Slave Select Output Line 16 SLSO16 B2 P2 7 I O A1 Port 2 General Purpose I O Line 7 SLSO07 O1 a SSCO Slave Select Output Line 7 SLSO17 O2 SSC1 Slave Select Output Line 17 SLSOO07 O3 S
115. ne of GPTAO OUT33 O2 OUT33 Line of GPTA1 OUT1 O3 OUT1 Line of LTCA2 AF12 P4 10 I O A1 Port 4 General Purpose I O Line 10 IN34 l a IN34 Line of GPTAO IN34 l IN34 Line of GPTA1 T12HRB l CCU60 CCPOSOA l CCU61 T2INA l GPT120 T2INB l GPT121 OUT34 01 OUT34 Line of GPTAO OUT34 O2 OUT34 Line of GPTA1 OUT2 O3 OUT2 Line of LTCA2 Data Sheet 39 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AD13 P4 11 V0 A1 Port 4 General Purpose I O Line 11 IN35 l FH IN35 Line of GPTAO IN35 l IN35 Line of GPTA1 OUT35 01 OUT35 Line of GPTAO OUT35 02 OUT35 Line of GPTA1 OUT3 O3 OUT3 Line of LTCA2 AC14 P4 12 0 A1 Port 4 General Purpose I O Line 12 IN36 l PU IN36 Line of GPTAO IN36 l IN36 Line of GPTA1 T13HRB l CCU60 CCPOS1A l CCU61 T2EUDA l GPT120 T2EUDB l GPT121 OUT36 01 OUT36 Line of GPTAO OUT36 02 OUT36 Line of GPTA1 OUT4 O3 OUT4 Line of LTCA2 AE13 P4 13 0 A1 Port 4 General Purpose I O Line 13 IN37 l PU IN37 Line of GPTAO IN37 l IN37 Line of GPTA1 OUT37 01 OUT37 Line of GPTAO OUT37 02 OUT37 Line of GPTA1 OUT5 O3 OUT5 Line of LTCA2 Data Sheet 40 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration
116. nel DMA Controller 8 Channel Safe DMA SDMA Controller Sophisticated interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High performing on chip bus structure 64 bit Cross Bar Interconnect between CPU Flash and Data Memory 32 bit System Peripheral Bus SPB for on chip peripheral and functional units One bus bridge SFI Bridge Versatile On chip Peripheral Units Two Asynchronous Synchronous Serial Channels ASC with baud rate generator parity framing and overrun error detection Four High Speed Synchronous Serial Channels SSC with programmable data length and shift direction Four SSC Guardian SSCG modules one for each SSC Two serial Micro Second Bus interfaces MSC for serial port expansion to external power devices Two High Speed Micro Link interfaces MLI for serial inter processor communication One External Bus Interface EBU supporting different memories asynchronous memories e g SRAM peripheral devices synchronous devices e g burst NOR flash PSRAM and DDR NOR flash e g LPDDR NVM Jedec 42 2 ONFI 2 0 limited frequency at 1 8 V I O supply One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality One FlexRay module with 2 channels E Ray Data Sheet 3 V 1 2 2014 05 Cinfineon TES
117. ns 32 mA for the same application relevant case The following changes where done between Version 0 7 and 1 0 of this document improve parameters pppg 3 change for parameter Ng note from Max data retention to Min e change description of parameter toa for the ADC correct typo for class D pads in tables 14 and 15 adapt Absolute Maximun Rating add footnote to Flash parameter fern Data Sheet 3 V 1 2 2014 05 Cinfineon ru History add note at the end of Pin Reliability in Overload section clearify pad supply levels in Pin Reliability in Overload section add footnote for D Flash currents in power section clearify wording for valid operating conditions add negative limit for class S pad leakage increase max values for parameter fg change formula 10 change MLI parameter 4 min value change footnote 3 for EBU parameter t3 change package naming add products SAK TC1793N 512F270EF and SAK TC1793N 512F270EB split FADC DNL parameter into two conditions and change value for gain 4 and 8 update footnote 10 for the ADC update package outline update parmeter description for SSC parameters t and t53 change SSC parameters from CC to SR Symbol for toe 157 ts and tsg increase value range for BFCLKO duty cycle The following changes where done between Version 1 0 and 1 1 of this document add product option SAK TC1793S 512F270EF update block diagrams to cover new option
118. nter processor communication One External Bus Interface EBU supporting different memories asynchronous memories e g SRAM peripheral devices synchronous devices e g burst NOR flash PSRAM and DDR NOR flash e g LPDDR NVM Jedec 42 2 ONFI 2 0 limited frequency at 1 8 V I O supply One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer one CAN node supports TTCAN functionality One FlexRay module with 2 channels E Ray Two General Purpose Timer Array Modules GPTA with additional Local Timer Cell Array LTCA2 providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input Output management Two Capture Compare 6 modules Two General Purpose 12 Timer Units GPT120 and GPT121 44analog input lines for ADC 4 independent kernels ADCO ADC1 and ADC2 Analog supply voltage range from 3 3 V to 5 V single supply 4 different FADC input channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fgapnc clock 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 8 digital input lines for SENT communication according to the SENT specification J2716 FEB2008 e 221 digital general purpose I O lines GPIO Digi
119. of GPTA1 OUT83 O3 OUTS 3 Line of LTCA2 AD3 O EBU Address Data Bus Line 3 Data Sheet 65 V 1 2 2014 05 Cinfineon Hus PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function V26 P13 4 0 B Port 13 General Purpose I O Line 4 AD4 l FB EBU Address Data Bus Line 4 OUT92 O1 OUT92 Line of GPTAO OUT92 O2 OUT92 Line of GPTA1 OUT84 O3 OUT84 Line of LTCA2 AD4 O EBU Address Data Bus Line 4 U25 P13 5 0 B Port 13 General Purpose I O Line 5 AD5 l Ja EBU Address Data Bus Line 5 OUT93 01 OUT93 Line of GPTAO OUT93 O2 OUT93 Line of GPTA1 OUT85 O3 OUTS 5 Line of LTCA2 AD5 O EBU Address Data Bus Line 5 U23 P13 6 l O B Port 13 General Purpose I O Line 6 AD6 l EM EBU Address Data Bus Line 6 OUT94 O1 OUT94 Line of GPTAO OUT94 O2 OUT94 Line of GPTA1 OUT86 O3 OUTS86 Line of LTCA2 AD6 O EBU Address Data Bus Line 6 W26 P13 7 0 B Port 13 General Purpose I O Line 7 AD7 l EBU Address Data Bus Line 7 OUT95 O1 OUT95 Line of GPTAO OUT95 O2 OUT95 Line of GPTA1 OUT87 O3 OUTS 7 Line of LTCA2 AD7 O EBU Address Data Bus Line 7 Data Sheet 66 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration
120. of two parts Static current consumption Dynamic current consumption The static current consumption is related to the device temperature T and the dynamic current consumption depends of the configured clocking frequencies and the software Data Sheet 135 V 1 2 2014 05 Cinfineon His Electrical ParametersDC Parameters application executed These two parts needs to be added in order to get the rail current consumption 2 z mA 0 02041 x T W 3 75 xe J C mA 0 01825x T 15 58 71 c IE JEC Function 2 defines the typical static current consumption and Function 3 defines the maximum static current consumption Both functions are valid for Vpp 1 326 V For the dynamic current consumption using the real pattern and fau 2 3 2 focp 3 ftp the function 4 applies 4 mA 1 22 ETE IDym x fopylMHz For the dynamic current consumption using the real pattern and faa fpcp 2 fep the function 5 applies 5 mA Ipym L 308 ar x fopy MHz and this finally results in Ipp lo IpyM Data Sheet 136 V 1 2 2014 05 Cinfineon Tels Electrical ParametersAC Parameters 5 3 AC Parameters All AC parameters are defined with maximum driver strength unless otherwise noted 5 3 1 Testing Waveforms Vopp 90 rise_fall Figure 9 Rise Fall Time Parameters VppP Vopge 2 lt Test Points Vppe 2 Vss mc104881 a vsd
121. oom 0 6 V Table 12 PN Junction Characteristics for negative Overload Pad Type In 3 mA In 5 MA A1 A1 F_ J Un Vss 0 6 V Un Vss 0 7 V A2 Un Vss 0 5 V Un Vss 0 6 V LVDS Un Vss 0 7 V D Un Vssm 0 6 V S Un Vssm 0 6 V Note A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery without having any negative reliability impact on the operational life time Data Sheet 95 V 1 2 2014 05 Cinfineon rus Electrical ParametersGeneral Parameters 5 1 5 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the TC1793 All parameters specified in the following tables refer to these operating conditions unless otherwise noticed Digital supply voltages applied to the TC1793 must be static regulated voltages which allow a typical voltage swing of 5 96 All parameters specified in the following tables Table 15 and following refer to these operating conditions Table 13 unless otherwise noticed in the Note Test Condition column The Extended Range Operating Conditions did not increase area of validity of the parameters defined in table 10 and later Table 13 Operating Conditions Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Overload coupling factor Kovan
122. or PLL Clock Generator Input G25 XTAL2 O Main Oscillator PLL Clock Generator Output D25 TDO O A2 JTAG Module Serial Data Output BRKIN l PU OCDS Break Input Alternate Input BRKOUT O OCDS Break Output Alternate Output DAP2 O Device Access Port Line 2 Power Supply WA Vopm ADC Analog Part Power Supply 3 3V 5V YA Vssm ADC Analog Part Ground AE5 VAREFO ADCO Reference Voltage AF5 VAGNDO ADCO Reference Ground VAGND2 ADC2 Reference Ground AD6 VAREF1 ADC1 Reference Voltage AC6 VAGND1 ADC1 Reference Ground AD9 VAREF2 ADC2 Reference Voltage Data Sheet 82 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AF8 VEAREF FADC Reference Voltage AE8 VEAGND FADC Reference Ground AE9 Vopme FADC Analog Part Power Supply 3 3V ACY VppArF FADC Analog Part Logic Power Supply 1 3V AF9 Vsswur FADC Analog Part Ground VssaF FADC Analog Part Logic Ground A18 Vopria Flash Power Supply 3 3V B18 H3 F25 Vssosc Main Oscillator Ground Vas Digital Ground F26 Vpposc Main Oscillator Power Supply 1 3V E26 Vpposc3 Main Oscillator Power Supply 3 3V G23 Voppr E Ray PLL Power Supply 1 3V G24 Vopprs E Ray PLL Power Supply 3 3V AC11 Vpp Digital Core Power Supply 1 3V
123. or high tog SR 0 ns from BFCLKI rising edge 1 Not subject to production test verified by design characterization 2 An active edge can be rising or falling edge depending on the settings of bits BFCON EBSE ECSE and clock divider ratio Negative minimum values for these parameters mean that the last data read during a burst may be corrupted However with clock feedback enabled this value is oversampling not required for the LMB transaction and will be discarded If the clock feedback is not enabled the input signals are latched using the internal clock in the same way as at asynchronous access So t14 t15 t16 t17 t18 and t19 from the asynchronous timings apply 3 For BUSCONx EBSE 1B and BUSAPx EXLCLK 00B ADV will change normally on the clock edge so this parameter is used directly For BUSCONx EBSE 1B and other values of BUSAPx EXTCLK ADV and BAA add the high pulse width of EBUCLK to this parameter For BUSCONx EBSE 0B and BUSAPx EXTCLK 00B add the high pulse width of EBUCLK to this parameter For BUSCONx EBSE 0B and BUSAPx EXTCLK 11B add two EBUCLK periodsto this parameter to get the hold time from BFCLKO rising edge to the ADV For BUSCONx EBSE 0B and BUSAPx EXTCLK 01B or 10B add 1 EBUCLK period Please note that the high pulse width of EBUCLK is defined by the high pulse width of fVCO of the used PLL Data Sheet 169 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersAC Parameters
124. or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Cinfineon Never stop thinking 32 Bit Microcontroller TC1793 32 Bit Single Chip Microcontroller Data Sheet V 1 2 2014 05 Microcontrollers Cinfineon Tel Table of Contents 1 Summary of Features kk KK KK KK KK KK KK KK KK KK 1 1 2 System Overview of the TC1793 00 KEK KK 2 10 2 1 Block Diagram ulllssllssselll KK KK KK KK KK KK K 2 11 3 PINNING rm 3 14 3 1 TC1793 Pin Configuration 0 0 0 eee 3 15 4 Identification Registers 0 0 eee RR RR KK 4 88 5 Electrical Parameters KK KK KK KK RR RR KK KR KK 5 90 5 1 General Parameters kk kk kk kK KK KK KK KK KK KK KI KI KIR KK KK KI KK IK 5 90 5 1 1 Parameter Interpretation 000000 KK eee KR KK KIIR 5 90 5 1 2 Pad Driver and Pad Classes Summary 2000 00 5 91 5 1 3 Absolute Maximum Ratings lees 5 92 5 1 4 Pin Reliability in Overload llle 5 94 5 1 5 Operating Conditions kk KK KK KK KK ee 5 96 5 1 5 1 Extended Range Operating Conditions 5 100 5 2 DC Parameters ess set gu a l0 d al RU rc Rosa ee banan BREE EES 5 103 5 2 1 Input Outp t PIDs sers preia a k
125. ort 12 General Purpose I O Line 5 Reserved O1 PB Reserved O2 Reserved O3 A21 O EBU Address Bus Line 21 J24 P12 6 0 B Port 12 General Purpose I O Line 6 Reserved O1 is Reserved O2 Reserved O3 A22 O EBU Address Bus Line 22 J25 P12 7 I O B Port 12 General Purpose I O Line 7 Reserved O1 u Reserved O2 Reserved O3 A23 O EBU Address Bus Line 23 Port 13 Data Sheet 64 V 1 2 2014 05 Cinfineon Hus PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function T26 P13 0 0 B Port 13 General Purpose I O Line 0 ADO l FB EBU Address Data Bus Line 0 OUT88 O1 OUTS6 Line of GPTAO OUT88 O2 OUTS88 Line of GPTA1 OUT80 O3 OUTS80 Line of LTCA2 ADO O EBU Address Data Bus Line 0 T24 P13 1 0 B Port 13 General Purpose I O Line 1 AD1 l Ja EBU Address Data Bus Line 1 OUT89 01 OUT89 Line of GPTAO OUT89 O2 OUTS89 Line of GPTA1 OUT81 O3 OUTS81 Line of LTCA2 AD1 O EBU Address Data Bus Line 1 U26 P13 2 l O B Port 13 General Purpose I O Line 2 AD2 l EM EBU Address Data Bus Line 2 OUT90 O1 OUT90 Line of GPTAO OUT90 O2 OUT90 Line of GPTA1 OUT82 O3 OUTS82 Line of LTCA2 AD2 O EBU Address Data Bus Line 2 T25 P13 3 0 B Port 13 General Purpose I O Line 3 AD3 l EBU Address Data Bus Line 3 OUT91 O1 OUT91 Line of GPTAO OUT91 O2 OUT91 Line
126. pad type LVDS t CC 2 ns termination 100 O 1 96 Rise time pad type LVDS t CC 2 ns termination 100 O x 1 96 Pad set up time tset tvo 13 us termination s CC 100 O 1 96 Output Differential Voltage Vo CC 150 400 mV termination 100 O x 1 96 Output voltage high pad Vo CC 1525 mV termination class F LVDS mode 100 0Q 1 Output voltage low pad Vg CC 875 mV termination class F LVDS mode 100 Q 1 96 Output Offset Voltage Vos CC 1075 1325 mV termination 100 OQ x 1 96 Data Sheet 120 V 1 2 2014 05 Cinfineon TC1793 5 2 2 Electrical ParametersDC Parameters Analog to Digital Converters ADCx ADC parameter are valid for Vbo ppar 1 235 V to 1 365 V Vppy 4 5 V to 5 5 V Table 24 ADC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Switched capacitance at Cainsw 9 20 pF the analog voltage inputs CC Total capacitance of an Caintot 20 30 pF analog input CC Switched capacitance at Carersw 15 30 pF the positive reference CC voltage input Total capacitance of the Caperto 20 40 pF voltage reference inputs CC Differential Non Linearity EApy 3 3 LSB ADC Error 9 97 CC resolution 12 bit 9 9 Gain Error 99 EAgan 95 l 3 5 LSB ADC CC resolution 12 bit 9 9 Integral Non BANL 3 3 LSB ADC Linearity 9 CC resolution 12 bit 9 9 Offset Error 997 E
127. pose I O Line 8 Reserved O1 FB Reserved O2 Reserved O3 Data Sheet 17 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function B5 P0 9 0 A1 Port 0 General Purpose I O Line 9 RXDAO FH E Ray Channel A Receive Data Input 0 Reserved O1 Reserved O2 Reserved O3 C6 P0 10 I O A2 Port 0 General Purpose I O Line 10 TXENA O1 FH E Ray Channel A transmit Data Output enable Reserved O2 Reserved O3 D6 PO 11 0 A2 Port 0 General Purpose I O Line 11 T5INB l po GPT120 T5INA l GPT121 TXENB O1 E Ray Channel B transmit Data Output enable Reserved O2 Reserved O3 C5 P0 12 l O A2 Port 0 General Purpose I O Line 12 T5EUDA l n GPT120 T5EUDB l GPT121 TXDB 01 E Ray Channel B transmit Data Output Reserved 02 Reserved 03 Data Sheet 18 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function D5 P0 13 V0 A1 Port 0 General Purpose I O Line 13 RXDBO FH E Ray Channel B Receive Data Input 0 T5EUDB l GPT120 T5EUDA l G
128. put channels channels with impedance control and overlaid with ADC1 inputs Extreme fast conversion 21 cycles of fanc clock Data Sheet 5 V 1 2 2014 05 Cinfineon Tel Summary of Features 10 bit A D conversion higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter 8 digital input lines for SENT communication according to the SENT specification J2716 FEB2008 221 digital general purpose I O lines GPIO Digital I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Buses Dedicated Emulation Device chip available TC1793ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Clock Generation Unit with PLL and PLL ERAY Flexible CRC Engine FCE IEEE 802 3 CRC32 ethernet polynomial 0xX82608EDB CRC kernel 0 CRC32C Castagnoli 0xD419CC15 CRC kernel 1 The SAK TC1793S 512F270EF has the following features High performance 32 bit super scalar TriCore V1 6 CPU with 6 stage pipeline Superior real time performance Strong bit handling Fully integrated DSP capabilities Multiply accumulate unit able to sustain 2 MAC operations per cycle Fully pipelined Floating point unit FPU 270 MHz operation at full temperature range 32 bit Peripheral Control Processor with single cycle instruction PCP2
129. rved O3 F4 P6 8 I O A2 Port 6 General Purpose I O Line 8 RXDCANO l PU CAN Node 0 Receiver Input 0 CAN Node 3 Receiver Input 1 RXDOB l ASCO Receiver Input Output B CAPINB l GPT120 CAPINA l GPT121 Reserved 01 RXDOB O2 ASCO Receiver Input Output B Reserved O3 Data Sheet 46 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function E4 P6 9 I O A2 Port 6 General Purpose I O Line 9 TXDCANO O1 FH CAN Node 0 Transmitter Output TXDO O2 ASCO Transmitter Output B T60FL O3 GPT120 F2 P6 10 0 A2 Port 6 General Purpose I O Line 10 RXDCAN1 l PU CAN Node 1 Receiver Input 0 CAN Node 0 Receiver Input 1 RXD1B l ASC1 Receiver Input Output B Reserved 01 RXD1B O2 ASC1 Receiver Input Output B TXENA O3 E Ray Channel A transmit Data Output enable E2 P6 11 I O A2 Port 6 General Purpose I O Line 11 TXDCAN1 O1 FE CAN Node 1 Transmitter Output TXD1 O2 ASC1 Transmitter Output B TXENB O3 E Ray Channel B transmit Data Output enable 2 E1 P6 12 0 A1 Port 6 General Purpose I O Line 12 RXDCAN2 l PN CAN Node 2 Receiver Input 0 CAN Node 1 Receiver Input 1 RXDA1 E Ray Channel A Receive Data Input 1 Reserved O1 Reserved O2 COUT61 O3 CCU60 Data Sheet 47 V 1 2 2014 05 Cinfineon TC1793 Pinn
130. s Bus Line 14 Data Sheet 62 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function N25 P11 15 0 B Port 11 General Purpose I O Line 15 Reserved O1 FB Reserved O2 Reserved O3 A15 O EBU Address Bus Line 15 Port 12 P26 P12 0 1 0 B Port 12 General Purpose I O Line 0 Reserved O1 ve Reserved O2 Reserved O3 A16 O EBU Address Bus Line 16 P24 P12 1 V0 B Port 12 General Purpose I O Line 1 Reserved O1 ce Reserved O2 Reserved O3 A17 O EBU Address Bus Line 17 P25 P12 2 0 B Port 12 General Purpose I O Line 2 Reserved O1 PH Reserved O2 Reserved O3 A18 O EBU Address Bus Line 18 R24 P12 3 0 B Port 12 General Purpose I O Line 3 Reserved O1 EE Reserved O2 Reserved O3 A19 O EBU Address Bus Line 19 Data Sheet 63 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function R26 P12 4 0 B Port 12 General Purpose I O Line 4 Reserved O1 FB Reserved O2 Reserved O3 A20 O EBU Address Bus Line 20 R25 P12 5 l O B P
131. s but within the overload parameters then the parameters functionality of this pin as stated in the Operating Conditions can no longer be guaranteed Operation is still possible in most cases but with relaxed parameters Note An overload condition on one or more pins does not require a reset Table 10 Overload Parameters Parameter Symbol Values Unit Note Min Typ Max Test Con dition Input current on any digital pin Zi 5 5 mA during overload condition except LVDS pins Input current on LVDS pins Jini vps 3 3 mA Absolute sum of all input Inc 20 20 mA circuit currents for one port group during overload condition Input current on analog pins Jnana 3 3 mA Absolute sum of all analog Insa 45 45 mA input currents for analog inputs during overload condition Absolute sum of all input Lins 100 100 mA circuit currents during overload condition 1 The port groups are defined in Table 14 Note FADC input pins count as analog pin as they are overlayed with an ADC pins Data Sheet 94 V 1 2 2014 05 Cinfineon TC1793 Electrical ParametersGeneral Parameters Table 11 PN Junction Characteristics for positive Overload Pad Type Ty 3 mA Ty 5 mA A1 A1 F Uy Vopp 0 6 V Un Vopr 0 7 V A2 Un Vopr 0 5 V Un Vopr 0 6 V LVDS Un Vopr 0 7 V D Unn Voom 0 6 V S Un V
132. s using wait states and for the operation of timers serial interfaces etc For all slower operations and longer periods e g pulse train generation or measurement lower baudrates etc the deviation caused by the PLL jitter is negligible Data Sheet 142 V 1 2 2014 05 Cinfineon Tete Electrical ParametersAC Parameters Two formulas are defined for the absolute approximate maximum value of jitter Dm in ns dependent on the K2 factor the SRI clock frequency fag in MHz and the number m of consecutive fau clock periods for K2 lt 100 and m lt fsgsj MHz 2 Dm ns s x Q 9 0 KD x D o o x K2 7 K2 x fag MHz 0 5 x fag MHz 1 740 8 else Dm ns 5 m K2 x for MHz With rising number m of clock cycles the maximun jitter increases linearly up to a value of m that is defined by the K2 factor of the PLL Beyond this value of m the maximum accumulated jitter remains at a constant value Further a lower SRI Bus clock frequency Jor results in a higher absolute maximum jitter value Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF with the maximum driver and sharp edge Note The maximum peak to peak noise on the pad supply voltage measured between Vbposc3 and Vssosc iS limited to a peak to peak voltage of Vpp 100 mV for noise frequencies below 300 KHz and Vpp 40 mV for noise frequencies above 300 KHz The maximum peak to peak
133. st Condition Min Typ Max Operation fop 24000 hours Lifetime ESD susceptibility Vi E 2000 V Conforming to according to JESD22 A114 B Human Body Model HBM Data Sheet 175 V 1 2 2014 05 Cinfineon TELS Electrical ParametersPackage and Reliability Table 48 Quality Parameters Parameter Symbol Values Unit Note Test Condition Min Typ Max ESD susceptibility Vagm zx 500 V x of the LVDS pins ESD susceptibility Vopy 500 V Conforming to according to JESD22 C101 C Charged Device Model CDM Moisture MSL _ 3 _ Conforming to Jedec Sensitivity Level J STD 020C for 240 C 1 This lifetime refers only to the time when the device is powered on 2 For worst case temperature profile equivalent to 1200 hours at T 125 150 C 3600 hours at T 110 125 C 7200 hours at T 100 110 C 11000 hours at T 25 100 C 1000 hours at T 40 25 C Data Sheet 176 V 1 2 2014 05 Cinfineon ru 6 History History The following changes where done between Version 0 6 and 0 62 of this document Change for port 1 7 the symbol from CC60INB to CC61INB for the CCU60 input Add footnote to port 4 1 alternate output 3 MTSR2 change function description for port 4 1 alternate output 3 MTSR2 from Slave to Master Transmit Add footnote to port 6 4 alternate output 1 MTSR1 Add footnote to port 7 1 alternate ou
134. t ADC2 CH6 AF3 P17 11 l D S Port 17 General Purpose I Line 11 SENT3 l SENT Digital Input 3 AN39 l Analog Input ADC2 CH7 AD4 P17 12 l D S Port 17 General Purpose I Line 12 SENT4 l SENT Digital Input 4 AN40 l Analog Input ADC2 CH8 AE4 P17 13 l D S Port 17 General Purpose I Line 13 SENT5 l SENT Digital Input 5 AN41 l Analog Input ADC2 CH9 AC5 P17 14 l D S Port 17 General Purpose I Line 14 SENT6 l SENT Digital Input 6 AN42 l Analog Input ADC2 CH10 AF4 P17 15 l D S Port 17 General Purpose I Line 15 SENT7 l SENT Digital Input 7 AN43 l Analog Input ADC2 CH11 9 Analog Input Port AE1 ANO l D Analog Input 0 ADCO CHO AD2 AN1 l D Analog Input 1 ADCO CH1 9 AA4 AN2 l D Analog Input 2 ADCO CH2 AB3 AN3 l D Analog Input 3 ADCO CH3 Data Sheet 79 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AC2 AN4 l D Analog Input 4 ADCO CH4 ADC2 CH12 AA3 AN5 l D Analog Input 5 ADCO CH5 ADC2 CH13 AD1 ANG l D Analog Input 6 ADCO CH6 ADC2 CH14 AB4 AN7 l D Analog Input 7 ADCO CH7 ADC2 CH15 AC1 AN8 l D S Analog Input 8 ADCO CH8 SENTO AB2 AN9 l D S Analog Input 9 ADCO CH9 SENT1 Y3 AN10 l D S Analog Input 10 ADCO CH10 SENT2 AA2 AN11 l D S Analog Inp
135. tal I O ports with 3 3 V capability On chip debug support for OCDS Level 1 CPU PCP DMA On Chip Buses Dedicated Emulation Device chip available TC1793ED multi core debugging real time tracing and calibration four five wire JTAG IEEE 1149 1 or two wire DAP Device Access Port interface Power Management System Data Sheet 7 V 1 2 2014 05 Cinfineon Hus Summary of Features Clock Generation Unit with PLL and PLL ERAY Flexible CRC Engine FCE IEEE 802 3 CRC32 ethernet polynomial 0xX82608EDB CRC kernel 0 CRC32C Castagnoli 0xD419CC15 CRC kernel 1 e Secure Hardware Extension SHE For further information please contact your Infineon representative Data Sheet 8 V 1 2 2014 05 Cinfineon Tene Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product This ordering code identifies The derivative itself i e its function set the temperature range and the supply voltage The package and the type of delivery For the available ordering codes for the TC1793 please refer to the Product Catalog Microcontrollers which summarizes all available microcontroller variants This document describes the derivatives of the device The Table 1 enumerates these derivatives and summarizes the differences Table 1 TC1793 Derivative Synopsis Derivative Ambient Temperature Range SAK TC1793F 5
136. ternal trigger Input 5 MTSR3 l SSC3 Slave Receive Input Slave Mode MRSTG3B l SSC Guardian 3 Master Receive Input B Master Mode ADOEMUX2 01 ADCO external multiplexer Control Output 2 MTSR3 O2 SSC3 Master Transmit Output Master Mode Reserved O3 U4 P7 2 0 A1 Port 7 General Purpose I O Line 2 SCLK3 l PU sca Input ADOEMUXO O1 ADCO external multiplexer Control Output 0 SCLK3 O2 SSC3 Output Reserved O3 U3 P7 3 0 A1 Port 7 General Purpose I O Line 3 ADOEMUX1 01 PU ADCO external multiplexer Control Output 1 SLSO30 O2 SSC3 Output Reserved O3 T3 P7 4 I O A1 Port 7 General Purpose I O Line 4 REQ6 l PU External trigger Input 6 AD2EMUXO 01 ADC2 external multiplexer Control Output 0 SLSO31 O2 SSC3 Output Reserved O3 Data Sheet 49 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function T2 P7 5 0 A1 Port 7 General Purpose I O Line 5 REQ7 l FB External trigger Input 7 AD2EMUX1 O1 ADC2 external multiplexer Control Output 1 SLSO32 O2 SSC3 Output Reserved O3 T1 P7 6 VO A1 Port 7 General Purpose I O Line 6 AD1EMUXO 01 B ADC1 external multiplexer Control Output 0 SLSO33 O2 SSC3 Output Reserved O3 U2 P7 7 V0 A1 Port 7 General Purpose I O Line 7 AD1EMUX1 O1 PU ADC1 external multiplexer
137. tput 2 MTSR3 Change for port 8 2 the symbol from CC61 CCU60 to COUT63 CCU61 Change for port 8 3 the symbol from OUT43 GPTA1 to CC62 CCU60 correct typo for port 9 4 from COUT amp to COUT60 correct typo for port 9 5 from COUT amp to COUT61 Change for port 15 4 and 15 5 the type from B1 to B Change for port 15 the type from S to D S add clarification that table 11 defines the conditions for all other parameters add conditions for MLI MSC SSC parameters add parameters dTxdly and dRxdly to ERAY parameters correct footnotes for ERAY parameters split flash parameters tPRD and tPRP in two conditions add conditions to LVDS pad parameters remove Pin Reliability in Overload section add parameters IIN and Sum IIN to absolute ratings add parameter HYSX to PSC_XTAL added RDSON values for all driver settings weak medium and strong removed footnote 2 of table 10 change load for timing of SSC MSC and MLI from C 25 pF to C 50 pF typical add to parameters ta and tpp condition C 50 pF add new footnote 7 to ADC parameter table add min and max value for Qcony and adapt typ value add load conditions for tee and tar add conditions to PLL parameter t change DAP parameter t from SR to CC classification remove footnote 2 for the FADC adapt IDs for AB step removed footnote 2 in table 9 change max value for ADC parameter ts from 255 to 257 The following changes where done between Version 0 62 and 0 63 of this doc
138. ument shift Output function CC62 of CCU60 for P8 3 from O3 to O2 remove output function OUT43 for GPTA1 for P8 3 Data Sheet 1 V 1 2 2014 05 Cinfineon ru History add output function TData1 for MLI1 as O3 for P8 3 remove O2 OUT105 for GPTA1 of P14 9 add O2 T3OUt for GPT121 of P14 9 changed the name for O3 from EVTO2 to EVTO1 for P0 5 changed the name for O3 from EVTO3 to EVTO2 for P0 6 changed the name for O3 from EVTO4 to EVTO3 for PO 7 changed the name for O1 and O2 from OUT70 to OUT71 for P1 15 add input function SLSI2 for SSC2 to P4 9 change input function T13HRE from CCU60 to CCU63 for P3 14 change for port 8 2 the symbol from CC61 CCU60 to COUT63 CCU61 change for port 14 10 the symbol from T3OUT GPT120 to TEOUT GPT121 add to all SSC signal the associated SSC module where is was missing in the pinning add section Pin Reliability in Overload increase values for absolute maximum parameters J and Sum y correct P14 8 O2 as this was uncorrected label as O1 The following changes where done between Version 0 63 and 0 7 of this document update value of RTID registers in section Identification Registers for AB step remove sentence Exposure to conditions within the maximum ratings will not affect device reliability To replace this sentence section Pin Reliability in Overload was added add footnote 1 to table 12 Operating Conditions increase values for absolute maximum parameters J and Sum y remove capacitanc
139. unication through the JTAG debug interface The JTAG module is fully compliant with IEEE1149 1 2000 Note These parameters are not subject to production test but verified by design and or characterization Table 33 JTAG Interface Timing Parameters Operating Conditions apply Parameter Symbol Values Unit Note Min Typ Max Test Condition TCK clock period t1 SR 25 ns TCK high time t2 SR 10 ns TCK low time tz SR 10 ns TCK clock rise time t SR 4 ns TCK clock fall time ts SR 4 ns TDI TMS setup t6 SR 6 ns to TCK rising edge TDI TMS hold t SR 6 ns after TCK rising edge TDO valid after TCK falling tg CC 13 ns C 50 pF 1 edge propagation delay tg CC 3 5 ns C 20pF TDO hold after TCK falling ti CC 2 ns edge TDO high imped to valid t9 CC _ 14 ns C 50 pF from TCK falling edge TDO valid to high imped ti CC 13 5 ns C 50 pF from TCK falling edge 1 The falling edge on TCK is used to generate the TDO timing 2 The setup time for TDO is given implicitly by the TCK cycle time Data Sheet 146 V 1 2 2014 05 Cinfineon rus Electrical ParametersAC Parameters 0 9 Vpop 0 1 V f DDP MC JTAG TCK Figure 14 Test Clock Timing TCK ts L TMS Galat ui o TDO MC JTAG Figure 1
140. urpose I O Line 15 Reserved 01 u Reserved O2 Reserved O3 BFCLKO O Burst Mode Flash Clock Output Non Differential Port 16 Data Sheet 76 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AF17 P16 0 0 B Port 16 General Purpose I O Line 0 HOLD l FH Hold Request Input Reserved O1 Reserved O2 Reserved O3 AD18 P16 1 I O B Port 16 General Purpose I O Line 1 HLDA l FH Hold Acknowledge Output Reserved O1 Reserved O2 Reserved O3 HLDA O Hold Acknowledge Output AD22 P16 2 V0 B Port 16 General Purpose I O Line 2 Reserved O1 d Reserved O2 Reserved O3 BREQ O Bus Request Output AE19 P16 3 0 B Port 16 General Purpose I O Line 3 Reserved O1 PU Reserved O2 Reserved O3 CSCOMB O Combined Chip Select Output Port 17 AC1 P17 0 l D S Port 17 General Purpose I Line 0 SENTO l SENT Digital Input 0 AN8 Analog Input ADCO CH8 Data Sheet 77 V 1 2 2014 05 Cinfineon TC1793 PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AB2 P1
141. ut 11 ADCO CH11 SENT3 AB1 AN12 l D S Analog Input 12 ADCO CH12 SENT4 W3 AN13 l D S Analog Input 13 ADCO CH13 SENT5 Y2 AN14 l D S Analog Input 14 ADCO CH14 SENT6 AA1 AN15 l D S Analog Input 15 ADCO CH15 SENT7 V4 AN16 l Analog Input 16 ADC1 CHO W2 AN17 D Analog Input 17 ADC1 CH1 9 Y1 AN18 D Analog Input 18 ADC1 CH2 V3 AN19 l D Analog Input 19 ADC1 CH3 w1 AN20 l D Analog Input 20 ADC1 CH4 V2 AN21 D Analog Input 21 ADC1 CH5 V1 AN22 D Analog Input 22 ADC1 CH6 U1 AN23 D Analog Input 23 ADC1 CH7 AC8 AN24 l D Analog Input 24 ADC1 CH8 FADC_FADINOP 9 AD8 AN25 l D Analog Input 25 ADC1 CH9 FADC_FADINON AC7 AN26 l D Analog Input 26 ADC1 CH10 FADC_FADIN1P Data Sheet 80 V 1 2 2014 05 Cinfineon TES PinningTC1793 Pin Configuration Table 2 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function AD7 AN27 D Analog Input 27 ADC1 CH11 FADC FADIN1N 9 AE6 AN28 D Analog Input 28 ADC1 CH12 FADC FADIN2P 9 AF6 AN29 D Analog Input 29 ADC1 CH13 FADC FADIN2N 9 AE7 AN30 D Analog Input 30 ADC1 CH14 FADC FADINS3P 9 AF7 AN31 D Analog Input 31 ADC1 CH15 FADC_FADIN3N 9 AC3 AN32 D Analog Input 32 ADC2 CHO AE2 AN33 l D Analog Input 33 ADC2 CH1 AD3 AN34 D Analog Input 34 ADC2 CH2 AD5 AN35 D Analog
142. witching due to external system noise Note It is strongly recommended to measure the oscillation allowance negative resistance in the final target system layout to determine the optimal parameters for the oscillator operation Please refer to the limits specified by the crystal or ceramic resonator supplier Data Sheet 130 V 1 2 2014 05 Cinfineon TC1793 5 2 5 Temperature Sensor Table 28 DTS Parameters Electrical ParametersDC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Measurement time tu CC l 100 us Temperature sensor Tsp SR 40 150 C range Sensor Accuracy Trsa CC 6 6 C calibrated Start up time after resets trgg7 SR 20 us inactive The following formula calculates the temperature measured by the DTS in C from the RESULT bit field of the DTSSTAT register Data Sheet Tj 131 03 DTSSTATRESULT 596 2 1 V 1 2 2014 05 Cinfineon His Electrical ParametersDC Parameters 5 2 6 Power Supply Current The total power supply current defined below consists of leakage and switching component Application relevant values are typically lower than those given in the following two tables and depend on the customer s system operating conditions e g thermal connection or used application configurations The operating conditions for the parameters in the following table are VDD Vpposc

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