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ST10 Family programming manual

1. 3 5 5 Mnemonic Description O ft 2 c css 522 SUBCB reg Subtract immediate byte data from direct register 21841618112 4 with Carry SUBCB reg mem Subtract direct byte memory from direct register with 2 8 4 6 8 12 4 Carry SUBCB mem reg Subtract direct byte register from direct memory 2 8 4 6 8 12 4 Carry Table 9 Arithmetic instructions Continued lt Mnemonic Description 9 c 5 5 3 d4 AND Rw Rw Bitwise AND direct word GPR with direct GPR 2161213141612 Rw Rw Bitwise AND indirect word memory with direct GPR 2 6 2 3 4 6 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 6 2 3 416 2 and post increment source pointer by 2 AND Rw data3 Bitwise AND immediate word data with direct GPR 2 6 2 3 4 16 2 AND reg data g Bitwise AND immediate word data with direct regis 2 8 4 6 8 121 4 ter AND reg mem Bitwise AND direct word memory with direct register 2 8 4 6 8 12 4 AND mem reg Bitwise AND direct word register with direct memory 2 8 4 6 8 121 4 ANDB Rb Rb Bitwise AND direct byte GPR with direct GPR 216234612 Rb Rw Bitwise AND indirect byte memory with direct GPR 2 6 2 3 4 6 2 ANDB Rw Bitwise AND indirect byte memory with direct GPR 2 6 2 3 4 6 2 and
2. Addressing Mode Overwritten Address IDX no change IDX IDX 2 IDX IDX 2 IDX QX IDX 10 MAC Flags N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes IDX 8 Rw 8 Yes 93 Xm 98 rrrr rqqq 4 CoMACMus IDX Rwm8 Yes 93 Xm 8 rrrrirqqq 4 CoMACMus IDX Rw rnd Yes 93 Xm 99 rrrr rqqq 4 CoMACMRus IDX amp Rwm8 Yes 93 Xm B8 rrrrirqqq 4 CoMACMRus IDX amp Rw 8 rnd Yes 93 Xm B9 rrrr rqqq 4 Examples CoMACMus IDX1 QX0 R10 QR1 rnd ACC lt ACC IDX1 R10 R10 lt R10 QR1 IDX1 QX0 lt IDX1 IDX1 lt IDX1 Repeat 3 times CoMACMus IDXO R8 QRO ACC lt ACC IDXO R8 R8 lt R8 IDXO QX0 lt IDXO IDXO IDXO Repeat MRW times CoMACMRus IDX1 QX1 R7 rnd ACC IDX1 R7 ACC rnd R7 lt R7 IDX1 QX1 l
3. PROGRAMMING MANUAL CoCMP CoCMP Group Syntax Operation Data Types Description MAC Flags Addressing Modes Examples Compare Compare Instructions CoCMP op1 op2 tmp lt 2 1 ACC lt gt tmp DOUBLE WORD Subtracts a 40 bit signed operand from the 40 bit Accumulator content and update the N Z and C flags contained in the MSW register leaving the accumulator unchanged The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended The MS bit of the MCW register does not affect the result This instruction is not repeat able and allows up to two parallel memory reads N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Not affected E Not affected SL Not affected Mnemonic Rep Format Bytes CoCMP RWm No A3 nm C2 00 4 CoCMP IDX amp Rwm 93 Xm C2 0 0qqq 4 CoCMP Rw No 83 nm C2 0 0qqq 4 CoCMP IDX1 QX0 R11 QR1 MSW N Z C lt ACC R11 IDX1 CoCMP 1 R2 CoCMP R2 R5 R11 lt R11 QR1 IDX1 lt IDX1 MSW N Z C lt ACC R2 NR1 R2 lt R2 2 MSW N Z C ACC R5 R2 153 197 CoLOAD 2 PROGRAMMING
4. N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise iy PROGRAMMING MANUAL CoMACM R Addressing Modes Examples CoMACM IDX1 QXO R10 QR1 rnd Repeat times CoMACM IDXO R8 QRO Repeat MRW times CoMACM IDX1 QX1 R7 C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Mnemonic Rep CoMACM IDX amp Yes CoMACM IDX amp Rw 8 Yes CoMACM IDX amp rnd Yes CoMACMR IDX amp Yes CoMACMR IDX amp rnd Yes Format Bytes 93 Xm D8 rrrr rqqq 4 93 Xm E8 rrrr rqqq 4 93 Xm 09 rrrr rqqq 4 93 Xm F8 rrrr rqqq 4 93 Xm F9 rrrr rqqq 4 ACC IDX1 R10 rnd R10 R10 QR1 IDX1 QX0 lt IDX1 IDX1 lt IDX1 ACC IDX0 R8 R8 lt R8 QRO IDXO QX0 lt IDXO IDXO IDX1 R7 IDX1 QX1 lt IDX1 IDX1 lt IDX1 QX1 R7 lt R7 167 197 CoMACM R u PROGRAMMING MANUAL CoMACM R u
5. Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most signifi cant bit of the specified data type Cleared other wise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ADD RWm 00 nm 2 ADD Rw Rwi 08 n 10ii 2 ADD Rw 08 n 11ii 2 ADD Rw 08 n 0 2 reg dataig 06 4 ADD reg mem 02 MM 4 ADD mem reg 04RRMMMM 4 55 197 PROGRAMMING MANUAL AD D B Integer Addition Syntax ADDB op1 op2 Operation op1 lt op1 op2 Data Types BYTE Description Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 Flags Addressing Modes 56 197 E 2 V Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared oth
6. E 2 V 0 0 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes XORB Rb Rbm 51 nm 2 XORB 59 n 10ii 2 XORB Rb Rw 59 n 1lii 2 XORB Rb data 59 n 0 2 XORB reg dataig 57 RR 4 XORB reg mem 53 4 XORB mem reg 55RRMMMM 4 PROGRAMMING MANUAL MAC Instruction set 2 Instruction set This section describes the instruction set for the MAC Refer to device datasheets for information about which ST10 devices include the MAC 2 1 Addressing modes MAC instructions use some standard ST10 addressing modes such as GPR direct or for immediate shift value To supply the MAC with up to 2 new operands per instruction cycle new MAC instruction addressing modes have been added These allow indirect addressing with address pointer post modification Double indirect addressing requires 2 pointers one of which can be supplied by any GPR the other is provided by one of two new specific SFRs and IDX Two pairs of offset registers QRO QR1 and QX0 QX1 are associated with each pointer GPR or IDX The GPR pointer gives access to the entire memory space whereas IDX are limited to
7. Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Mnemonic Format Bytes MOVBS Rb Rbm DO mn 2 MOVBS reg D2RRMMMM 4 MOVBS reg 05 4 107 197 MOVBZ PROGRAMMING MANUAL MOVBZ Move Byte Zero Extend Syntax MOVBZ 1 2 Operation low byte op1 lt op2 high byte op1 lt 00 Data Types WORD BYTE Description Moves and zero extends the contents of the source byte specified by op2 to the word location specified by the destina tion operand op1 The contents of the moved data is examined and the flags are updated accordingly Flags E 2 V 0 m 0 E Always cleared 2 Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Always cleared Addressing Modes Mnemonic Format Bytes MOVBZ Rb Rbm mn 2 MOVBZ reg mem C2RRMMMM 4 MOVBZ men reg C5 RRMMMM 4 108 197 PROGRAMMING MANUAL MUL MUL Syntax Operation Data Types Description Flags Addressing Modes Signed Multiplication MUL 1 op2 MD lt 1 op2 WORD Performs a 16 bit by 16 bit signed multiplication using the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register E
8. or Rb datag 0A 4 BFLDL bitoffg maskg datag 0B 2 MUL RWm 0 2 ROL RWm 00 2 JMPR cc_UC rel 2 BCLR 2 bitaddra 10 2 ADDC RWm 11 2 ADDCB Rb Rbm 12 4 ADDC reg mem 13 4 ADDCB reg mem 14 4 ADDC mem reg 15 4 ADDCB mem reg 16 4 ADDC reg data 17 4 ADDCB reg 1 18 2 ADDC Rw or Rwy or 19 2 ADDCB Rb Rwj or Rb or Rb datas 1A 4 BFLDH bitoffg maskg datag 1B 2 MULU RWm 1C 2 ROL Rwp 1D 2 JMPR cc NET rel Table 21 Instruction set ordered by Hex code 38 197 571 PROGRAMMING MANUAL Standard Instruction Set Number of Bytes Mnemonic Operand TE 2 BCLR bitaddrg 1 1F 2 BSET bitaddrg 1 20 2 SUB RWm 21 2 SUBB Rbm 22 4 SUB reg mem 23 4 SUBB reg mem 24 4 SUB mem reg 25 4 SUBB mem reg 26 4 SUB reg data 27 4 SUBB reg 1 28 2 SUB Rw or Rwy or 29 2 SUBB Rb Rwj Rb or Rb datag 2A 4 BCMP bitaddrz z bitaddro 2B 2 PRIOR RWm 2C 2 ROR RWm 2D 2 JMPR cc rel or cc Z rel 2E 2 BCLR bitaddra 2 2F 2 BSET bitaddra 2 30 2 SUBC RWm 31 2 SUBCB Rbm 32 4 SUBC reg mem 33 4 SUBCB reg mem 34 4 SUBC
9. 0 or 2 States The minimum time of 4 state times for standard jumps into the internal ROM space will be extended by 2 additional state times if the branch target instruction is a double word instruction at a non aligned double word location xxx2h xxx6h xxxAh xxxEh as shown in the following example label EOM any non aligned double word instruction e g at location OFFEh JMPA cc UC label if a standard branch is taken i 2 States 6 States A cache jump which normally requires just 2 state times will be extended by 2 additional state times if both the cached jump target instruction and the following instruction are non aligned double word instructions as shown in the following example label E apia any non aligned double word instruction e g at location 12FAh I any non aligned double word instruction n 1 omm mos i e g at location 12FEh JMPR cc_UC label provided that a cache jump is taken i 2 States 4 States If necessary these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses xxxOh xxx4h xxx8h xxxCh Testing Branch Conditions Tj444 0 or 1 States NO extra time is usually required for a conditional branch instructions to decide whether a branch condition is met or not However an additional state time is required if the preceding instruction writes to
10. 4 ADDCB mem 13 RR MM MM 4 ADDCB 15 4 PROGRAMMING MANUAL AND AND Syntax Operation Data Types Description Flags Addressing Modes Logical AND AND 1 op2 1 lt op1 op2 WORD Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E 2 V C N x 0 0 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z V Always cleared C Always cleared N Cleared otherwise Mnemonic AND RWm AND Rw AND Rw AND AND reg dataig AND reg mem AND mem reg Format 60 nm 68 n 10ii 68 111 68 n O 66 RR 62 RR MM MM 64 RR MM MM Set if result equals zero Cleared otherwise Set if the most significant bit of the result is set Bytes 2 AA 59 197 PROGRAMMING MANUAL AN D B Logical AND Syntax ANDB op1 op2 Operation op1 lt op1 op2 Data Types BYTE Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 Flags Addressing Modes 60 197 E 2 V C N x 0 0 Set if the value of op2 represents the lowest pos
11. Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description 168 197 Unsigned Multiply Accumulate Parallel Data Move amp Optional Round Multiply Multiply Accumulate Instructions CoMACMu 1 op2 tmp lt op1 op2 ACC lt ACC tmp IDX lt 10 CoMACMu op1 op2 rnd tmp lt op1 op2 lt ACC tmp 00 0000 8000p MAL lt 0 IDX amp lt 10 op1 op2 tmp lt op1 op2 ACC lt ACC tmp DX amp lt IDX CoMACMRu op2 tmp lt op1 op2 ACC lt tmp IDX lt IDX CoMACMRu op2 rnd tmp lt op1 op2 ACC lt tmp ACC 00 0000 8000 MAL lt 0 IDX amp lt 10 PP jm DOUBLE WORD 40 bit signed value Multiplies the two signed 16 bit source operands op1 and op2 The unsigned 32 bit product is first zero extended then optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s
12. XOR The flag contains the logical XORing of the two specified bit operands The contains the original value of the specified bit operand The contains the complemented value of the specified bit operand 50 197 Table 25 List of flags PROGRAMMING MANUAL Standard Instruction Set If the PSW register is specified as the destination operand of an instruction the flags can not be interpreted as described This is because the PSW register is modified according to the data format of the instruction For word operations the PSW register is overwritten with the word result For byte operations the non addressed byte is cleared and the addressed byte is overwritten For bit or bit field operations on the PSW register only the specified bits are modified If the flags are not selected as destination bits they stay unchanged i e they maintain the state existing after the previous instruction In all cases if the PSW is the destination operand of an instruction the PSW flags do NOT represent the flags of this instruction in the normal way 1 6 8 Addressing modes Specifies available combinations of addressing modes The selected addressing mode combination is generally specified by the opcode of the corresponding instruction However there are some arithmetic and logical instructions where the addressing mode combination is not specified by the identical
13. nm 20 00 4 CoMACu Rw Rwm rnd No 11 00 4 CoMACRu Rwy No A3 nm 30 00 4 CoMACRu Rwj Rwm rnd No nm 31 00 4 CoMACu IDX amp Yes 93 Xm 10 rrrr rqqq 4 CoMACu IDX amp Rwm 8 Yes 93 Xm 20 rrrr rqqq 4 CoMACu IDX amp Rw 8 Yes 93 Xm 11 rrrr rqqq 4 CoMACRu IDX amp Rwm8 Yes 93 Xm 30 rrrr rqqq 4 CoMACRu IDX amp Rw rnd Yes 93 Xm 31 4 CoMACu Rwy Rwm8 Yes 83 10 rrrr rqqq 4 CoMACu Rwy RWm Yes 83 20 rrrr rqqq 4 CoMACu Rw rnd Yes 83 11 rrrr rqqq 4 CoMACRu Rwy Rwm8 Yes 83 30 rrrr rqqq 4 CoMACRu Rw rnd Yes 83 nm 31 rrrr rqqq 4 Examples CoMACu R5 R8 rnd R5 R8 rnd CoMACu R2 R7 ACC lt ACC R2 R7 CoMACu R11 QRO ACC lt ACC IDXO R11 R11 lt R11 IDXO lt IDXO QX0 Repeat 3 times CoMACu IDX1 R9 lt IDX1 R9 RQ R9 2 IDX1 lt IDX1 2 Repeat MRW times CoMACu R7 lt R3 R7 R7 lt R7 CoMACRu 1 R4 rnd ACC lt IDX1 R4 ACC rnd IDX1 lt IDX1 160 197 571 PROGRAMMING MANUAL CoMAC R us CoMAC R us Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syn
14. 2 rnd MAE MAL 2 SV SL MS x 8000 8000 x 00 4000 0000 0 0 0 0 MS x 7FFF 7FFFp 0 00 SFFF 0001 0 0 0 0 1 00 3FFF 0000 0 0 0 0 8001 F456 0 00 2 F456 0 0 0 0 1 00 2 0000 0 0 0 0 0 00 0001 0 0 0 0 1 00 0000 0 0 0 0 181 197 CoMULus PROGRAMMING MANUAL CoMULus Mixed Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMULus 1 op2 Operation ACC lt op1 op2 Syntax CoMULus 1 op2 Operation ACC lt op1 op2 Syntax CoMULus 1 op2 rnd Operation ACC lt op1 2 00 0000 8000 MAL lt 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiply the two 16 bit unsigned and signed source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended then it is optionally either negated or rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register The option is used to negate the specified product while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is
15. N V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPB Rb 41 nm 2 Rb 49 n 10ii 2 Rw 49 n 11ii 2 CMPB datag 49 n O 2 CMPB datay g 47 RR 4 CMPB reg mem 43 4 PROGRAMMING MANUAL CMPD1 CMPD1 Syntax Operation Data Types Description Flags Addressing Modes Integer Compare amp Decrement by 1 CMPD1 2 0 1 lt gt 0 2 1 lt 0p1 1 WORD This instruction is used to enhance the performance and flex ibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is decre mented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Set if result equals zero Cleared otherwise
16. x7h Rw or Rb datag x8h xBh Rw Rw or Rw xCh xFh Rw Rw or Rw For these instructions only the lowest four GPRs RO to R3 can be used as indirect address pointers 2 These instructions are encoded by means of additional bits in the operand field of the instruction 00 EXTS or ATOMIC 01 10 EXTSR or EXTR 11 EXTPR Notes on the JMPR instructions The condition code to be tested for the JMPR instructions is specified by the opcode Two mnemonic representation alternatives exist for some of the condition codes Notes on the BCLR and BSET instructions The position of the bit to be set or to be cleared is specified by the opcode The operand pitaddrg where q 0 to 15 refers to a particular bit within a bit addressable word ky 37 197 Standard Instruction Set PROGRAMMING MANUAL Notes on the undefined opcodes A hardware trap occurs when one of the undefined opcodes signified by is decoded by the CPU Hex coda Number of Bytes Mnemonic Operand 00 2 ADD RWm 01 2 ADDB Rbm 02 4 ADD reg mem 03 4 ADDB reg mem 04 4 ADD mem reg 05 4 ADDB mem reg 06 4 ADD reg data 07 4 ADDB reg datay 08 2 ADD Rw or Rw or 09 2 ADDB Rwj or Rb
17. 110 FAMILY PROGRAMMING MANUAL September 2013 PROGRAMMING MANUAL Table of Contents 1 6 8 2 4 1 2 4 2 2 4 3 2 197 Standard Instruction Set 5 Addressing modes 5 Short adressing modes 5 Long addressing mode 6 DPP override mechanism 8 Indirect addressing modes 9 Constants 10 Branch target addressing modes 11 Instruction execution times 12 Definition of measurement units 12 Minimum state times 14 Additional state times 15 Instruction set summary 17 Instruction set ordered by functional group 21 Instruction set ordered by opcodes 37 Instruction conventions 45 Instruction name 46 Syntax 46 Operation 46 Data Sete alien JEN Soe ee METER 48 Description 48 Condition code 48 Flags eese Seat eee as eae 50 Addressing modes 51 ATOMIC and EXTe
18. 4 Disable interrupts and Class A traps SFR range Extended DO WHILE count 0 AND Class B trap condition z TRUE Next Instruction count count 1 END WHILE count 0 SFR range Standard Enable interrupts and traps Causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The value of op1 defines the length of the effected instruction sequence The EXTR instruction must be used carefully see ATOMIC and EXTended instructions on page 53 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes EXTR 01 10 0 2 93 197 EXTS PROGRAMMING MANUAL EXTS Begin EXTended Segment Sequence Syntax EXTS 1 op2 Operation count lt op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Segment op1 DO WHILE count 0 AND Class B trap condition z TRUE Next Instruction count count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps ar
19. lt 0 count lt count 1 END WHILE Data Types ACCUMULATOR Result 40 bit signed value Description Shifts the ACC register right by as many times as specified by the operand op1 The most significant bits of the result are filled with zeros accordingly Only shift values contained between 0 and 8 are allowed op1 can be either a 5 bit unsigned immediate data or the least significant 5 bits considered as unsigned data of any register directly or indirectly addressed operand The MS bit of the MCW register does not affect the result This instruction is repeatable when op 1 is not an immediate operand MAC Flags N 2 SV E SL x x 0 x Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Cleared always SV Not affected E Set if the MAE is used Cleared otherwise SL Not affected Addressing Modes Mnemonic Rep Format Bytes CoSHR Rw Yes rrrr r000 4 CoSHR datas No A300 92 ssss s000 4 CoSHR Yes 83 4 Examples CoSHR 3 ACC lt ACC gt gt 3 CoSHR R3 CoSHR R10 QRO lt gt gt R3 4 o lt gt gt 10 40 R10 R10 QRO 191 197 CoSTORE PROGRAMMING MANUAL CoSTORE Store a MAC Unit Register Group Transfer Instructions Syntax CoSTORE 1 op
20. qE QQ 2 64 197 PROGRAMMING MANUAL BCMP BCMP Syntax Operation Data Types Description Flags Addressing Modes Bit to Bit Compare BCMP op1 op2 op1 lt gt op2 BIT Performs a single bit comparison of the source bit specified by operand 1 to the source bit specified by operand op2 No result is written by this instruction Only the flags are updated E 2 V N NOR OR AND XOR o Always cleared Contains the logical NOR of the two specified bits Contains the logical OR of the two specified bits Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits lt N m Mnemonic Format Bytes BCMP bitaddrz z bitaddrg 2A QQ ZZ qz 4 65 197 BFLDH PROGRAMMING MANUAL BFLDH Bit Field High Byte Syntax BFLDH op2 op3 Operation tmp lt op1 high byte tmp lt high byte tmp 2 v op3 op1 lt tmp Data Types WORD Description Replaces those bits in the high byte of the destination word operand op1 which are selected by an 1 in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3 Note Bits which are masked off by a 0 in the AND mask op2 may be unintentionally altered if the corresponding bit in the OR mask contains 1 Flags Addressing Modes 66 197 E 2 V 0 E 0 0 E Always cleared 2 Se
21. A new instruction CoSTORE transfers a value from a MAC register to any location in memory This instruction uses a specific addressing mode for the MAC registers called CoReg The following table gives the 5 bit addresses of the MAC registers corresponding to this CoReg addressing mode Unused addresses are reserved for future revisions Register Description Address MSW MAC Unit Status Word 00000 MAH MAC Unit Accumulator High 00001 MAS limited MAH 00010 MAL MAC Unit Accumulator Low 00100 MCW MAC Unit Control Word 00101 MRW MAC Unit Repeat Word 00110 Table 28 MAC register addresses for CoReg 2 2 MAC instruction execution time The instruction execution time for MAC instructions is calculated in the same way as that of the standard instruction set To calculate the execution time for MAC instructions refer to Instruction execution times on page 12 considering MAC instructions to be 4 byte instructions with a minimum state time number of 2 140 197 5 PROGRAMMING MANUAL MAC Instruction set 2 3 MAC instruction set summary Mnemonic Addressing Modes Rep Mnemonic Addressing Modes Rep CoMUL RWm No CoMACM IDX amp Yes CoMULu IDX amp RWm No CoMACMu CoMULus RWm8 No CoMACMus CoMULsu CoMACMsu CoMUL CoMULu CoMULus CoMACMus CoMULsu CoMACMsu CoMUL rnd CoMACM rnd CoMULu rnd
22. E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JNB bitaddrg rel 9A QQ rr q0 4 103 197 JNBS PROGRAMMING MANUAL JNBS Syntax Operation Data Types Description Flags Addressing Modes 104 197 Relative Jump if Bit Clear amp Set Bit JNBS op1 op2 IF op1 0 THEN op1 1 IP lt IP sign extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is set allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNBS instruction If the specified bit was set the instruction following the JNBS instruction is executed E 2 0 0 0 Always cleared Z Contains logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Mnemonic Format Bytes JNBS bitaddrg rel BA QQ rr q0 4 PROGRAMMING MANUAL MOV MOV Syntax Operation Data Types Description Flags Addressing Modes Move Data MOV 1 op2
23. E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes SRVWDT A7 58 A7 A7 4 131 197 SUB PROGRAMMING MANUAL SU B Integer Subtraction Syntax SUB op1 op2 Operation op1 lt op1 op2 Data Types WORD Description Performs a 2 s complement binary subtraction of the source operand specified by op2 from the destination operand specified by op1 The result is then stored in op1 Flags Addressing Modes 132 197 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SUB 20 2 SUB Rw 28 n 10ii 2 SUB Rw 28 n 1lii 2 SUB 28 n 0 2 SUB reg data 26 4 SUB reg mem 22 4 SUB mem reg 24 4 PROGRAMMING MANUAL SUBB SUBB Syntax Operation Data Types Description Flags Addressing Modes Integer Subtraction SUBB op1 op2 1 lt 1 op2 Performs 2 s compleme
24. FFFF 0 0 1 111 l CoADD2 0 0001 2000 FF C000 0001 100 0000 0003 0 0 1 0 CoADD2 0 0001 1800 FF C000 0001 FF F000 0003 1 0 0 0 CoADD 0 4 1 73 2 00 7241 00 E604 5564 0 0 0 1 1 00 7FFF FFFF 0 0 0 0 1 CoADD 0 4 1 2 FF 8241 AOC3 FF 2604 5564 1 0 1 1 1 FF 8000 0000 1 0 1 0 1 CoADD 0 B4A1p 73 2 B241 80 2604 5564 1 0 0 1 1 CoADD 0 4 1 2 80 0241 7F A604 5564 0 0 1 1 1 150 197 571 PROGRAMMING MANUAL CoASHR CoASHR Group Syntax Operation Data Types Result Description MAC Flags Accumulator Arithmetic Shift Right with Optional Round Shift Instructions CoASHRop1 CoASHRop1 rnd count lt op1 C lt 0 DO WHILE count 0 lt n 0 38 count lt count 1 END WHILE IF rnd THEN ACC 00008000 MAL lt 0 END IF ACCUMULATOR 40 bit signed value Arithmetically shifts the ACC register right by as many times as specified by the operand op1 To preserve the sign of the ACC register the most significant bits of the result are filled with sign 0 if the original most significant bit was a 0 or with sign 1 if the original most significant bit was 1 Only shift values between 0 and 8 are allowed op1 can be either a 5 bit unsigned immediate data or the least significant 5 bits consid
25. The DPP override mechanism temporarily bypasses the DPP addressing scheme The EXTP R and EXTS R instructions override this addressing mechanism Instruction EXTP R replaces the content of the respective DPP register while instruction EXTS R concatenates the complete 16 bit long address with the specified segment base address The overriding page or segment be specified directly as a constant pag seg or by a word GPR Rw i 15 14 13 EXTP R 16 bit Long Address LI pag 14 bit page offset 24 bit Physical Address EXTS R 15 0 16 bit Long Address seg TT 16 bit segment offset Y Figure 2 Overriding the DPP mechanism 24 bit Physical Address 8 197 571 PROGRAMMING MANUAL Standard Instruction Set 1 1 4 Indirect addressing modes Indirect addressing modes can be considered as a combination of short and long addressing modes In this mode long 16 bit addresses are specified indirectly by the contents of a word GPR which is specified directly by a short 4 bit address Rw 0 to 15 Some indirect addressing modes add a constant value to the GPR contents before the long 16 bit address is calculated Other indirect addressing modes allow decrementing or incrementing of the indirect address pointers GPR content by 2 or 1 referring to words or bytes In each case one of the four DPP registers is used to specify the physical 18 bit or 24 bit
26. 1h Table 24 Condition codes 49 197 Standard Instruction Set PROGRAMMING MANUAL 1 6 7 Flags This section shows the state of the N C V Z and E flags in the PSW register The resulting state of the flags is represented by the following symbols Symbol Description The flag is set according to the following standard rules Most significant bit of the result is set N 0 Most significant bit of the result is not set C 1 Carry occurred during operation 0 Carry occurred during operation 1 Arithmetic Overflow occurred during operation V 0 No Arithmetic Overflow occurred during operation Z 1 Result equals zero Z 0 Result does not equal zero E 1 Source operand represents the lowest negative number either 8000h for word data or 80h for byte data E 0 Source operand does not represent the lowest negative number for the spec ified data type The flag is set according to non standard rules Individual instruction pages or the ALU status flags description The flag is not affected by the operation The flag is cleared by the operation NOR The flag contains the logical NORing of the two specified bit operands AND The flag contains the logical ANDing of the two specified bit operands Op The flag contains the logical ORing of the two specified bit operands
27. 3956 00 E604 5564 FF 8CA7 C2D6 1 0 1 0 CoSUB 0 FFFF FFFF 7F FFFF FFFF 80 00000000 1 0 1 111 l 1 OO7FFFFFFF o o 1 1 fo 1 CoSUB2 0 0000 3000 7 FFFF 7F 9FFFFFFF 0 0 0 J 1 l CoSUB2 0 0001 0000 80 0000 0000 7 FFFFFFFE 0 0 0 1 1 l 1 FF 80000000 1 0 0 1 0 1 194 197 ky PROGRAMMING MANUAL Revision History 3 Revision History Document revision history Revision 1 Revision 2 Revision 1 Definition of measurement units on page 12 ALE Cycle Time corrected Integer Addition with Carry on page 58 Instruction name changed from ADDBC to ADDCB Revision 3 Revision 2 CoSUB2r replaced CoSUBr2 In MAC instructions lower case r replaced upper case R for optional repeat Revision 4 Revision 3 Function codes Table 30 and addressing modes of the following instructions corrected CoMULsu CoMULus CoMAC r su CoMAC r us COMACM r su CoMAC rus CONOP CoSHL CoSHR CoASHR and CoSTORE Condition flags corrected for JBC and JNBS instructions Updated Table 21 Instruction set ordered by Hex code to include section CO FF MAC instructions and working register indexes Instruction CoMULus corrected Seg address range corrected in Table 5 Branch target address summary Condition Code Mnemonic cc_N corrected in Table 24 Condition codes Sentence added to Section 2 4 7 Repeated instruction syntax Clarified
28. 6 8 10 14 4 set PCALL reg Push direct word register onto system 10 6 8 10 14 4 stack and call absolute subroutine TRAP trap7 Call interrupt service routine via immediate 4 8 4 5 6 8 2 trap number Table 16 Jump and Call Instructions Continued zz Mnemonic Description Q 5 5 8 z z 333 POP reg Pop direct word register from system stack 2623462 PUSH Push direct word register onto system stack 2623462 SCXT data g Push direct word register onto system stack and 218 416 811214 update register with immediate data SCXT reg mem Push direct word register onto system stack and 218 416 811214 update register with direct memory Table 17 System Stack Instructions 51 5 Description T c 5 5 zz 3 El E S RET Return from intra segment subroutine 418 415161812 Return from interrupt service subroutine 41814156182 RETP reg Return from intra segment subroutine and pop di 4 8 4 5 6 8 2 rect word register from system stack RETS Return from inter segment subroutine 41814156182 Table 18 Return Instructions 35 197 Standard Instruction Set PROGRAMMING MANUAL Mnemonic Description 5 9 2233223 ATOMIC data Begin ATOMIC sequence 2 6 2 3 4 6 2 DISWDT Disable Watchdog Timer 2 8 4 6 8 12 4 EINIT Signify End of Initialization on RSTOU
29. Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes DIV Rw 4B nn 2 86 197 PROGRAMMING MANUAL DIVL DIVL Syntax Operation Data Types Description Flags Addressing Modes 32 by 16 Signed Division DIVL op1 MDL lt MD 1 MDH MD mod op1 WORD DOUBLEWORD Performs an extended signed 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E 2 V 0 S 0 E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes DIVL 6B 2 87 197 DIVLU PROGRAMMING MANUAL DIVLU 32 by 16 Unsigned Division Syntax DIVLU Operation MDL MD op1 MDH MD mod op1 Data Types WORD DOUBLEWORD Desc
30. DPPi Page offset 5 Post Incremented indirect address pointers Rw incremented by a data type dependent value A 1 for byte operations A 2 for word operations GPRPointer GPRPointer A optionalstep 9 197 Standard Instruction Set PROGRAMMING MANUAL The following indirect addressing modes are provided Mnemonic Notes Rw Most instructions accept any GPR R15 R0 as indirect address pointer Some instructions however only accept the lower four GPRs R3 R0 Rw The specified indirect address pointer is automatically incremented by 2 or 1 for word or byte data operations after the access Rw The specified indirect address pointer is automatically decremented by 2 or 1 for word or byte data operations before the access Rw data A 16 bit constant and the contents of the indirect address pointer are added before the long 16 bit address is calculated Table 3 Table of indirect address modes 1 1 5 Constants The ST10 Family instruction set supports the use of wordwide or bytewide immediate constants For optimum utilization of the available code storage these constants are represented in the instruction formats by either 3 4 8 or 16 bits Therefore short constants are always zero extended while long constants can be truncated to match the data format required for the operation see table below Mnemonic Word
31. E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise iy PROGRAMMING MANUAL CoLOAD 2 Addressing Modes Mnemonic CoLOAD CoLOAD CoLOAD2 CoLOAD2 CoLOAD CoLOAD CoLOAD2 CoLOAD2 CoLOAD CoLOAD CoLOAD2 CoLOAD2 Rwm Rwm Rwm RWm IDX amp IDX amp IDX amp Rw IDX amp Rw Rwy RWm RW RWm Rwy RWm 9 9 9 9 22 00 2 00 62 00 6A 00 93 Xm 22 0 0qqq 93 Xm 2A 0 0qqq 93 Xm 62 0 0qqq 93 Xm 6A 0 0qqq 83 nm 22 0 0qqq 83 nm 2A 0 0qqq 83 nm 62 0 0qqq 83 nm 6A 0 0qqq Bytes A RA HRA HRA HRA HAA 155 197 CoMAC R PROGRAMMING MANUAL CoMAC R Multiply Accumulate amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMAC opt op2 Operation IF MP 1 THEN tmp lt op1 2 lt lt 1 ACC lt tmp ELSE tmp lt op1 op2 ACC lt tmp END IF Syntax CoMAC op1 op2 rnd Operation IF MP 1 THEN tmp lt op1 2 lt lt 1 ACC lt ACC tmp 00 0000 8000 ELSE tmp lt op1 op2 ACC lt ACC tmp 00 0000 8000 END IF MAL lt 0 Syntax CoMAC 1 op2 Operation IF MP 1 THEN tmp lt op1 2 lt lt
32. SHR Rw mem 4 BAND bitaddrz z bitaddra 4 CMP B RWm BCMP Rw 2 BMOV Rw 2 BMOVN data 2 BXOR reg data 4 reg mem 4 BCLR bitaddro 2 CALLA cc caddr 4 BSET JMPA BFLDH bitoffg maskg datag 4 CALLI 2 BFLDL JMPI Table 8 Mnemonic vs address mode amp number of bytes 19 197 Standard Instruction Set PROGRAMMING MANUAL Mnemonic Addressing modes 8 Mnemonic Addressing modes 8 a a MOV B 2 CALLS seg caddr 4 Rw data 2 JMPS Rw 2 CALLR rel 2 Rwm 2 JMPR rel 2 RW 2 JB bitaddro rel 4 Rwm Rw 2 JBC 2 JNB Rw RW 2 JNBS Rwm 2 PCALL reg caddr reg datai 4 POP reg RWmt datay 4 PUSH Rw data 6 4 RETP Rw mem 4 SCXT reg datay mem Rw 4 reg mem reg mem 4 PRIOR mem reg 4 MOVBS Rwy 2 TRAP trap7 MOVBZ reg mem 4 ATOMIC data mem reg 4 EXTR EXTS Rw datas EXTP Rwy datas EXTSR seg gt EXTPR pag datas NOP 2 SRST IDLE PWRDN RETI SRVWDT RETS DISWDT EINIT Table 8 Mnemonic vs address mode amp number of bytes Continued 1 Byte oriented instructions suffix B use Rb instead of Rw not with Rwj 20 197 PROGRAMMING MANUAL Standard Instruction Set 1 4 Instruction set orde
33. addresses Any word or byte data within the entire memory space can be addressed indirectly Note that EXTP R and EXTS R instructions override the DPP mechanism Instructions using the lowest four word GPRs R3 RO as indirect address pointers are specified by short 2 bit addresses Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP registers are initialized in a way that all indirect long addresses are directly mapped onto the identical physical addresses Physical addresses are generated from indirect address pointers by the following algorithm 1 Calculate the physical address of the word GPR which is used as indirect address pointer by using the specified short address Rw and the current register bank base address CP GPRAddress CP 2 x ShortAddress A optionalstep 2 Pre decremented indirect address pointers Rw are decremented by a data type dependent value A 1 for byte operations A 2 for word operations before the long 16 bit address is generated GPRAddress GPRAddress A optionalstep 3 Calculate the long 16 bit address by adding a constant value if selected to the content of the indirect address pointer Long Address GPR Pointer Constant 4 Calculate the physical 18 bit or 24 bit address using the resulting long address and the corresponding DPP register content see long mem addressing modes Physical Address
34. and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC Flags N 2 SV E SL 0 0 Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Always cleared SL Not affected 184 197 PROGRAMMING MANUAL CoMULsu Addressing Modes Mnemonic Rep Format Bytes CoMULsu RWm No 40 00 4 CoMULsu Rw Rw 48 00 4 CoMULsu Rw Rw rnd No A3nm 41 00 4 CoMULsu IDX amp Rwm 8 No 93Xm400 0qqq 4 CoMULsu IDX amp Rw 2 No 93Xm480 0qqq 4 CoMULsu IDX amp Rw rnd No 93Xm410 0qqq 4 CoMULsu Rw No 83nm400 0qqq 4 CoMULsu Rwy No 83nm480 0qqq 4 CoMULsu Rw Rw rnd No 83nm410 0qqq 4 Examples CoMULsu RO R1 rnd ACC lt RO R1 rnd CoMULsu R2 R64 R2 R6 R6 2 CoMULsu IDXO R11 IDX0 R11 R11 lt R11 2 CoMULsu IDX1 R15 ACC lt IDX1 R15 IDX1 lt IDX1 2 CoMULsu IDX0 QX0 R9 QR1 rnd ACC lt IDXO R9 rnd R9 R9 QR1 IDXO lt Multiplication Examples Cases opi 2 rnd MAE MAH MAL N 2 SV SL MS x 8000 8000 x C000 0000
35. post increment source pointer by 2 MOV Rw Rw Move indirect word memory by base plus 4 1016 8 10114 4 constant to direct GPR MOV Rw Rw Move direct word GPR to indirect memory by 2 8 4 6 8 12 4 base plus constant MOV Rw mem Move direct word memory to indirect memory 2 8 4 6 8 12 4 MOV mem Rw Move indirect word memory to direct memory 2 8 4 6 8 12 4 MOV reg mem Move direct word memory to direct register 2 8 4 6 8 12 4 MOV mem reg Move direct word register to direct memory 2 8 4 6 8 12 4 MOVB Rb Rb Move direct byte GPR to direct GPR 21623462 MOVB Rb data Move immediate byte data to direct GPR 21623462 MOVB datay Move immediate byte data to direct register 2 8 4 6 8 12 4 MOVB Rb Rw Move indirect byte memory to direct GPR 2162346 2 MOVB Rb Rw Move indirect byte memory to direct GPRand 2 6 2 3 4 6 2 post increment source pointer by 1 MOVB Rw Rb Move direct byte GPR to indirect memory 2162346 2 MOVB Rw Rb Pre decrement destination pointer 1 and 2 6 2 3 4 6 2 move direct byte GPR to indirect memory MOVB Rw Move indirect byte memory to indirect memo 2 6 2 3 4 6 2 MOVB Rw Rw Move indirect byte memory to indirect memo 2 6 2 3 4 6 2 ry and post increment destination pointer by 1 MOVB Rw Rw Move indirect byte memory to indirect memo 2 6 2 3 4 6 2 ry and post in
36. 0 1 MS x 1 00 7FFE 0000 0 0 0 0 0 4001 F456 0 FF FD15 7456 1 0 0 0 1 0 FF FA2A E8ACh 1 0 0 0 0 1 FF FD15 0000 1 0 0 0 1 1 FF 2 0000 1 0 0 0 179 197 CoMULu PROGRAMMING MANUAL CoMULu Unsigned Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMULu 1 op2 Operation op1 op2 Syntax CoMULu 1 op2 Operation ACC lt 1 op2 Syntax CoMULu 1 op2 rnd Operation ACC lt op1 2 00 0000 8000 MAL 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiply the two unsigned 16 bit source operands op1 and op2 The unsigned 32 bit product is first zero extended and then it is optionally either negated or rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag of the MCW register The option is used to negate the specified product while the rnd option is used to round the product using two s comple ment rounding The default sign option is and the default round option is no round When rnd option is used MAL register is auto matically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC
37. 0 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ORB Rb Rbm 71 2 ORB Rb 79 n 10ii 2 ORB Rb 79 n 1lii 2 ORB Rb datas 79 n 0 HHE 2 ORB reg data16 77 RR 4 ORB reg mem 73 4 75 4 115 197 PCALL PROGRAMMING MANUAL PCALL Push Word amp Call Subroutine Absolute Syntax PCALL Operation tmp SP lt SP SP lt imp SP SP SP IP IP op2 Data Types WORD Description Pushes the word specified by operand op1 and the value of the instruction pointer IP onto the system stack and branches to the absolute memory location specified by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine Flags Addressing Modes 116 197 E 2 V Set if the value of the pushed operand op1 sents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed operand
38. 1 0 0 0 MS x 7 7FFFp 0 00 0001 0 0 0 0 1 00 SFFF 0000 0 0 0 0 MS x 8001 F456 0 8505 F456 1 0 0 0 1 8506 0000 1 0 0 0 185 197 CoNEG PROGRAMMING MANUAL CoNEG Group Syntax Operation Data Types Result Description MAC Flags Addressing Modes Examples Negate Accumulator with Optional Rounding 32 bit Arithmetic Instructions CoNEG CoNEG rnd IF rnd THEN ACC lt 0 ACC 00 0000 8000 MAL lt 0 ELSE ACC 0 ACC END IF ACCUMULATOR 40 bit signed value The Accumulator content is subtracted from zero and the result is optionally rounded before being stored in the accumulator register With rnd option MAL is cleared When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respec tively This instruction is not repeatable N 2 SV E SL N Set if the m s b of the result is set Cleared otherwise Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise N Mnemonic Rep Format Byte
39. 2 V 0 j S 0 Always cleared Z Set if the result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes MUL Rwy RWm 0B nm 2 109 197 MULU PROGRAMMING MANUAL M U LU Unsigned Multiplication Syntax MULU 1 op2 Operation MD op1 op2 Data Types WORD Description Performs a 16 bit by 16 bit unsigned multiplication using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register Flags E 2 V 0 0 E Always cleared 2 Set the result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes MULU 1 2 110 197 PROGRAMMING MANUAL NEG N EG Integer Two s Complement Syntax NEG Operation 1 lt 0 op1 Data Types WORD Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 Flags E 2 V 5 Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used t
40. 4 84 4 MOV mem 85 86 4 87 4 IDLE 88 2 MOV RWm 89 2 MOVB Rwm Rb 8A 4 JB bitaddro rel 8B 8C 8D 2 JMPR C rel or cc ULT rel 8E 2 BCLR bitaddra 8F 2 BSET bitaddrg 90 2 CMPI2 data 91 2 CPL Rw 92 4 CMPI2 mem 93 4 Coxxx IDXi amp Rw 94 4 MOV mem 95 96 4 CMPI2 data 46 97 4 PWRDN 98 2 MOV Rwm 99 2 MOVB Rb Rwm 9A 4 JNB bitaddrg rel 9B 2 TRAP trap7 9C 2 JMPI cc Rwy 9D 2 JMPR cc NC rel or cc_UGE rel 9E 2 BCLR bitaddrg 9F 2 BSET bitaddra 2 CMPD1 data A1 2 NEGB Rb Table 21 Instruction set ordered by Hex code Continued 42 197 571 PROGRAMMING MANUAL Standard Instruction Set Number of Bytes Mnemonic Operand A2 4 CMPD1 mem 4 Rwy RWm A4 4 MOVB mem A5 4 DISWDT A6 4 CMPD1 data46 A7 4 SRVWDT A8 2 MOV RW A9 2 MOVB Rb AA 4 JBC bitaddro rel AB 2 CALLI cc Rw AC 2 ASHR RWm AD 2 JMPR SGT rel AE 2 BCLR bitaddrg AF 2 BSET bitaddrg BO 2 CMPD2 data B1 2 CPLB Rb B2 4 CMPD2 mem B3 4 CoSTORE Rw CoReg B4 4 MOVB Rw B5 4 EINIT B6 4 CMPD2 B7 4 S
41. 90 n 2 CMPI2 datay 96 Fn 4 CMPI2 mem 92 Fn MM MM 4 PROGRAMMING MANUAL CPL CPL Syntax Operation Data Types Description Flags Addressing Modes Integer One s Complement CPL op1 1 lt 1 WORD Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 E 2 V x 0 0 s E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CPL 91 2 83 197 CPLB PROGRAMMING MANUAL CPLB Integer One s Complement Syntax CPL 1 Operation op1 lt 1 Data Types BYTE Description Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 Flags E 2 V 0 0 Set if the value of op1 represents the lowest Addressing Modes 84 197 possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CPLB Rb B1 nO 2 PROGRAMMING MANUAL DISWDT DISWD
42. ADDC mem reg Add direct word register to direct memory with Carry 2 8 4 6 8 12 4 ADDCB Rb Rb Add direct byte GPR to direct GPR with Carry 216234612 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry 2 6 2 31 41 6 2 24 197 Table 9 Arithmetic instructions PROGRAMMING MANUAL Standard Instruction Set 3 5 5 Mnemonic Description O x 2 c css 2 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry 2 6 2 3 4 6 2 and post increment source pointer by 1 ADDCB Rb dataz Add immediate byte data to direct GPR with Carry 2 6 2 3 4 6 2 ADDCB reg data g Add immediate byte data to direct register with Carry 2 8 4 6 8 12 4 ADDCB reg mem Add direct byte memory to direct register with Carry 2 8 416 8 12 4 ADDCB mem reg Add direct byte register to direct memory with 2 8 4 6 8 12 4 CPL Rw Complement direct word GPR 2161213462 CPLB Rb Complement direct byte GPR 2161213462 DIV Rw Signed divide register MDL by direct GPR 20 24 20 21 22 24 2 16 16 bit DIVL Rw Signed long divide register MD by direct GPR 20 24 20 21 22 24 2 32 16 bit DIVLU Rw Unsigned long divide register MD by direct GPR 20 24 20 21 22 24 2 32 16 bit DIVU Rw Unsigned divide register MDL by direct GPR 20 24 20 21 22 24 2 16 16 b
43. B2 CoSHR datas 92 CoABS 1A CoSHR other 9A CoABS op1 op2 CA CoASHR datas A2 CoSTORE wwww w000 CoASHR other AA CoMOV 00 CoASHR rnd datas B2 CoASHR rnd other BA Table 30 MAC instruction function code hexa Continued 143 197 MAC Instruction set PROGRAMMING MANUAL 2 4 MAC instruction conventions This section details the conventions used to describe the MAC instruction set 2 4 1 Operands Operand Description opX Specifies the immediate constant value of opX opX Specifies the contents of opX OpX Specifies the contents of bit n of opX opX Specifies the contents of opX i e opX is used as pointer to the actual operand rnd plus 00 0000 8000 2 4 2 Operations Diadic opX opY opY is MOVED into opX operations opX opY opX is ADDED to opX opY opY is SUBTRACTED from opX opX opY opX is MULTIPLIED by opY opX lt gt opY opY is COMPARED against opX opX opY opX is CONCATANATED to opY LSW Max opX opY MAXIMUM value between opX and opY Min opX opY MINIMUM value between opX and opY Monadic opX opX is Logically SHIFTED Left Operations gt gt Logically SHIFTED Right OpX gt gt opX is Arithmetically SHIFTED Right Abs opX ABSOLUTE value of opX 144 197 571 PROGRAMMING MANUAL MAC Ins
44. CoMACMu rnd CoMULus rnd CoMACMus rnd CoMULsu rnd CoMACMsu rnd CoMAC RWm No CoMACMR CoMACu IDX amp Yes CoMACMRu CoMACus RWm Yes CoMACMRus CoMACsu CoMACMRsu CoMAC CoMACMR rnd CoMACu CoMACMRu rnd CoMACus CoMACMRus rnd CoMACsu CoMACMRsu rnd CoMAC rnd CoADD RWm No CoMACu rnd CoADD2 IDX amp Rw 8 Yes CoMACus rnd CoSUB RWm8 Yes CoMACsu rnd CoSUB2 CoMACR CoSUBR CoMACRu CoSUB2R CoMACRus CoMAX CoMACRsu CoMIN CoMACR rnd CoLOAD RWm No CoMACRu rnd CoLOAD IDX amp CoMACRus rnd CoLOAD2 Rwy No CoMACRsu rnd CoLOAD2 CoCMP Table 29 MAC instruction mnemonic by addressing mode and repeatability 141 197 MAC Instruction set PROGRAMMING MANUAL Mnemonic Addressing Modes Rep Mnemonic Addressing Modes Rep CoNOP Yes CoSHL Rwy Yes IDX amp RW Yes CoSHR datas No CoASHR Rwm8 Yes CoNEG No CoASHR rnd CoNEG rnd CoABS No CoRND RWm No CoSTORE Rw CoReg No IDX amp CoReg Yes Rwy No CoMOV IDX amp Yes Table 29 MAC instruction mnemonic by addressing mode and repeatability The following table gives the MAC Function Code of each instruction This Function Code is the third byte of the new instruction and is used by the co processor as its operation code Unused function
45. Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Mnemonic Format Bytes BOR bitaddrz z bitaddrg 5A ZZ qz 4 PROGRAMMING MANUAL BSET BSET Syntax Operation Data Types Description Flags Addressing Modes Bit Set BSET op1 1 lt 1 BIT Sets the bit specified by op1 This instruction is primarily used for peripheral and system control E 2 0 B 0 0 B E Always cleared 2 Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Mnemonic Format Bytes BSET bitaddrg qF QQ 2 71 197 BXOR PROGRAMMING MANUAL BXOR Bit Logical XOR Syntax BXOR 1 op2 Operation 1 lt 1 op2 Data Types BIT Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by operand op2 with the destination bit specified by operand op1 The XORed result is then stored in op1 Flags Addressing Modes 72 197 2 V OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the t
46. E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes CALLR rel BB rr 2 75 197 CALLS PROGRAMMING MANUAL CALLS Call Inter Segment Subroutine Syntax CALLS op2 Operation SP lt SP 2 SP lt CSP SP lt SP 2 SP lt IP CSP lt 1 IP lt op2 Description A branch is taken to the absolute location specified by op2 Condition Codes Flags Addressing Modes 76 197 within the segment specified by op1 The value of the instruc tion pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address to the calling routine The previous value of the CSP is also placed on the system stack to insure correct return to the calling segment See condition code Table 24 on page 48 E 2 V Cc N E Not affected 2 Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes CALLS seg caddr DA ss MM MM 4 PROGRAMMING MANUAL CMP CMP Syntax Operation Data Types Description Flags Addressing Modes Integer Compare CMP 1 op2 1 lt gt op2 WORD The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s comple ment binary subtraction of op2 from
47. Flags N 2 SV E SL 0 0 Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Always cleared SL Not affected 180 197 PROGRAMMING MANUAL CoMULu Addressing Modes Mnemonic CoMULu CoMULu CoMULu CoMULu CoMULu CoMULu CoMULu CoMULu CoMULu Rep Format Bytes Rwy RWm No 00 00 4 RWm 08 00 4 rnd No A3nm 01 00 4 IDX amp Rwm 93 00 0 0qqq 4 IDX amp Rwm 93 08 0 0qqq 4 IDX amp Rwm rnd 93 Xm 01 0 0qqq 4 83 00 0 09 4 Rw RWm2 No 83 08 0 0qqq 4 Rw RWm rnd 83nm 01 0 0qqq 4 Notes The result of CoMULu is never saturated whatever the value of MS bit is see multiplication examples below Examples CoMULu RO R1 rnd RO R1 rnd CoMULu R2 R6 R2 R6 R6 lt R6 2 CoMULu IDXO R11 IDX0 R11 R11 lt R11 2 CoMULu IDX1 15 lt IDX1 R15 R15 lt R15 IDX1 lt IDX1 2 CoMULu IDX0 QX0 R9 ACC lt IDXO R9 rnd R9 lt R9 2 IDXO lt IDXO QXO Multiplication Examples Cases opi
48. Indirect addressing modes See 1 3 4 and 5 respectively GPRAddress 2 x ShortAddress LongAd dress GPRAddress Constant PhysicalAddress DPPi LongAddress 3FFFh and GPRPAddress GPRDAddress A See Section 1 2 3 Additional state times Jumps into the internal ROM Space example code Section 1 4 Instruction set ordered by functional group See teh columns Table 9 10 11 12 13 14 15 16 17 18 and 19 All column 16 bit N MUX 16 bit MUX 8 bit N MUX 8 bit MUX 20 Mar 2009 Rev 7 Standardized revision history and added revision number to title page 25 Sep 2013 Rev 8 Updated disclaimer 196 197 PROGRAMMING MANUAL Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is g
49. N V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPD1 data AO iin 2 CMPD1 Rw Fn 4 CMPD1 mem A2FnMMMM 4 79 97 2 PROGRAMMING MANUAL CMPD2 Syntax Operation Data Types Description Flags Addressing Modes 80 197 Integer Compare amp Decrement by 2 CMPD2 op1 op2 1 lt gt op2 op1 lt op1 2 WORD This instruction is used to enhance the performance and flex ibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is decre mented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table N Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the
50. Power Down Mode This instruction causes the part to enter the power down mode In this mode all peripherals and the CPU are powered down until the part is externally reset To insure that this instruction is not accidentally executed it is implemented as a protected instruction To further control the action of this instruction the PWRDN instruction is only enabled when the non maskable interrupt pin NMI is in the low state Other wise this instruction has no effect E 2 V C N E Not affected 2 Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes PWRDN 97 68 97 97 4 PROGRAMMING MANUAL RET RET Syntax Operation Description Flags Addressing Modes Return from Subroutine RET IP lt SP SP lt SP 2 Returns from a subroutine The IP is popped from the system stack Execution resumes at the instruction following the CALL instruction in the calling routine E 2 V C N E Not affected 2 Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes RET CB 00 2 121 197 RETI PROGRAMMING MANUAL RETI Return from Interrupt Routine Syntax RETI Operation IP SP SP lt SP 2 IF SYSCON SGTDIS 0 THEN CSP SP SP lt SP 2 END IF PSW SP SP lt SP 2 Description Returns from an interrupt routine The PSW IP and CSP are popped o
51. Syntax Operation Syntax Operation Syntax Operation Syntax Operation Multiply Accumulate Parallel Data Move amp Optional Round Multiply Multiply Accumulate Instructions CoMACM op1 op2 IF 1 THEN tmp lt 1 2 lt lt 1 ACC lt ACC tmp ELSE tmp lt op1 op2 ACC lt ACC tmp END IF IDX amp IDX CoMACM 1 op2 rnd IF MP 1 THEN tmp lt 1 2 lt lt 1 ACC lt ACC tmp 00 0000 8000 ELSE tmp lt 1 2 ACC ACC tmp 00 0000 8000 END IF MAL lt 0 DX amp lt IDX CoMACM 1 op2 IF 1 THEN tmp 1 2 lt lt 1 ACC lt ACC tmp ELSE tmp lt 0 1 0 2 ACC lt ACC tmp END IF DX amp 10 CoMACMR op1 op2 IF MP 1 THEN tmp 1 2 lt lt 1 ACC lt tmp ACC ELSE tmp lt 0 1 0 2 ACC lt tmp ACC END IF IDX lt IDX 165 197 CoMACM R PROGRAMMING MANUAL Syntax Operation Data Types Result Description MAC Flags 166 197 CoMACMR 1 op2 rnd IF MP 1 THEN tmp lt 0 1 0 2 lt lt 1 ACC lt tmp 00 0000 8000 ELSE tmp lt 1 2 ACC lt tmp ACC 00 0000 8000 END IF MAL lt 0 DX
52. Tijg ROM 6 States Unlike internal ROM program execution the minimum time Timin ext to process an external instruction also depends on instruction length Timin ext is either 1 ALE Cycle Time for most of the 2 byte instructions or 2 ALE Cycle Times for most of the 4 byte instructions The following formula represents the minimum execution time of instructions fetched from an external memory via a 16 bit wide data bus For2 byte instructions Timin ext 1 Timin ROM 2 States For 4 byte instructions Timin ext 2 ROM 2 States Note For instructions fetched from an external memory via an 8 bit wide data bus the minimum number of required ALE Cycle Times is twice the number for those of a 16 bit wide bus 1 2 3 Additional state times Some operand accesses can extend the execution time of an instruction Since the additional time Tlaga is generally caused by internal instruction pipelining it may be possible to minimize the effect by rearranging the instruction sequences Simulators and emulators offer a high level of programmer support for program optimization The following operands require additional state times Internal ROM operand reads Tiaqq 2 States Both byte and word operand reads always require 2 additional state times Internal RAM operand reads via indirect addressing modes Tj444 0 or 1 State Reading a GPR or any other directly addressed operand within the
53. a 40 bit arithmetic overflow underflow occurs Addressing Modes Mnemonic Rep Format Bytes CoSUB RWm No 00 4 CoSUBR RWm 12 00 4 CoSUB2 RWm No A3 nm 4A 00 4 CoSUB2R RWm No A3 nm 52 00 4 CoSUB IDX amp Rwa6 Yes 93 Xm 4 CoSUBR IDX Rwm Yes 93 12 rrrrrqqq 4 CoSUB2__ IDX Rwm Yes 93 Xm 4A rrrerqqq 4 CoSUB2R IDX Rwm Yes 93 Xm 52 rrrr rqqq 4 CoSUB Yes 83 OA rrrr rqqq 4 CoSUBR Yes 83 12 rrrr rqqq 4 CoSUB2 Rwy Rwm8 Yes 83 AA 4 CoSUB2R Rwy Rwm8 Yes 83 52 rrrrirqqq 4 Examples CoSUB RO R1 ACC lt ACC R1 RO CoSUB2 R2 R6 ACC lt ACC 2 R6 R2 R6 lt R6 2 Repeat 3 times CoSUB IDX1 QX1 R10 QRO ACC lt ACC R10 IDX1 R10 lt R10 IDX1 lt IDX1 QX1 Repeat MRW times CoSUB2R R4 R8 QR1 2 R8 R4 R8 lt R8 QR1 Subtraction Examples Instr MS op 1 2 ACC before after 7 5 SL CoSUB x 183A 72AC 00 7FFF FFFF 00 0053 E7C5p 0 0 0 0 CoSUBR 183A 72AC 00 7FFF FFFF FF 2 183B 1 0 1 0 CoSUB2 x 0C1D 3956 00 E604 5564 00 7358 3D2A 0 0 0 0 CoSUB2R x 0C1D
54. a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes DIVU 5 2 89 197 EINIT PROGRAMMING MANUAL EINIT Syntax Operation Description Flags Addressing Modes 90 197 End of Initialization EINIT End of Initialization This instruction is used to signal the end of the initialization portion of a program After a reset the reset output pin RSTOUT is pulled low It remains low until the EINIT instruc tion has been executed at which time it goes high This enables the program to signal the external circuitry that it has successfully initialized the microcontroller After the EINIT instruction has been executed execution of the Disable Watchdog Timer instruction DISWDT has no effect To insure that this instruction is not accidentally executed it is implemented as a protected instruction E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes EINIT B5 4A B5 B5 4 PROGRAMMING MANUAL EXTP EXTP Syntax Operation Description Note Flags Addressing Modes Begin EXTended Page Sequence EXTP 1 op2 count lt op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Page op1 DO WHILE count 0 AND Class B trap condition z TRUE N
55. affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes TRAP trap7 9B 0 2 PROGRAMMING MANUAL XOR XOR Syntax Operation Data Types Description Flags Addressing Modes Logical Exclusive OR XOR 1 op2 1 lt op1 0 2 WORD Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E 2 V 0 0 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table ZO lt N Mnemonic XOR Rwy Rwm XOR Rw Rwi XOR Rw XOR XOR reg dataig XOR reg mem XOR mem reg Always cleared Always cleared Format 50 58 n 10ii 58 11 58 n O 56 52 54 Set if result equals zero Cleared otherwise Set if the most significant bit of the result is set Cleared otherwise Bytes AA 9 137 197 XORB PROGRAMMING MANUAL XORB Syntax Operation Data Types Description Flags Addressing Modes 138 197 Logical Exclusive OR XORB op1 op2 1 lt op1 op2 BYTE Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1
56. amp lt 10 DOUBLE WORD 40 bit signed value Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended then and on condition the MP flag is set it is one bit left shifted and next it is optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product option is used to negate the accu mulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and This instruction might be repeated and performs two parallel memory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the over written data depends on the operation executed on IDX as explained by the following table Addressing Mode Overwritten Address IDX no change IDX 2 IDX IDX 2 IDX QX IDX QX 2 SV E SL
57. bit source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended and then it is optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified product option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and allows up to two parallel memory reads 163 197 CoMAC R su PROGRAMMING MANUAL MAC Flags N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Examples CoMACsu CoMAC
58. carry flag Cleared for a shift count of zero C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SHR 6 2 SHR Rwy data4 7C n 2 129 197 SRST PROGRAMMING MANUAL SRST Software Reset Syntax SRST Operation Software Reset Description This instruction is used to perform a software reset A software reset has the same effect on the microcontroller as an externally applied hardware reset To insure that this instruction is not acci dentally executed it is implemented as a protected instruction Flags Addressing Modes 130 197 E 2 V C 0 0 0 0 0 E Always cleared 2 Always cleared V Always cleared C Always cleared N Always cleared Mnemonic Format Bytes SRST B7 48 B7 B7 4 PROGRAMMING MANUAL SRVWDT SRVWDT Syntax Operation Description Flags Addressing Modes Service Watchdog Timer SRVWDT Service Watchdog Timer This instruction services the Watchdog Timer It reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte on every occurrence Once this instruction has been executed the watchdog timer cannot be disabled To insure that this instruction is not accidentally executed it is implemented as a protected instruction
59. codes are treated as Function Code by the MAC Mnemonic Function Code Mnemonic Function Code CoMUL CO CoMACM D8 CoMULu 00 CoMACMu 18 CoMULus 80 CoMACMus 98 CoMULsu 40 CoMACMsu 58 CoMUL C8 CoMACM E8 CoMULu 08 CoMACMu 28 CoMULus 88 CoMACMus A8 CoMULsu 48 CoMACMsu 68 CoMUL rnd C1 rnd 09 CoMULu rnd 01 CoMACMu rnd 19 CoMULus rnd 81 CoMACMus rnd 99 CoMULsu rnd 41 CoMACMsu rnd 59 CoMAC DO CoMACMR F9 CoMACu 10 CoMACMRu 38 CoMACus 90 CoMACMRus B8 CoMACsu 50 CoMACMRsu 78 CoMAC EO CoMACMR rnd F9 CoMACu 20 CoMACMRu rnd 39 CoMACus CoMACMRus rnd B9 CoMACsu 60 CoMACMRsu rnd 79 Table 30 MAC instruction function code hexa 142 197 PROGRAMMING MANUAL MAC Instruction set Mnemonic Function Code Mnemonic Function Code CoMAC rnd D1 CoADD 02 CoMACu rnd 11 CoADD2 42 CoMACus rnd 91 CoSUB 0A CoMACsu rnd 51 CoSUB2 4A CoMACR FO CoSUBR 12 CoMACRu 30 CoSUB2R 52 CoMACRus BO CoMAX 3A CoMACRsu 70 CoMIN 7A CoMACR rnd F1 CoLOAD 22 CoMACRu rnd 31 CoLOAD 2A CoMACRus rnd B1 CoLOAD2 62 CoMACRsu rnd 71 CoLOAD2 6A CoNOP 5A CoCMP C2 CoNEG 32 CoSHL datas 82 CoNEG rnd 72 CoSHL other 8A CoRND
60. description of Instruction CoSHL Only shift values from 0 to 8 inclusive IDX amp addressing mode and example removed from instruction CoNOP Reference to this addressing mode removed from Table 29 Table 29 Condition flag Z corrected for instruction BCLR MAC instruction descriptions ordered alphabetically Paragraph added to Section 2 1 Addressing modes Fcpu chaged to 0 50MHz in Section 1 2 1 Definition of mea surement units 195 197 Revision History PROGRAMMING MANUAL Revision 5 Revision 4 Current document 7096626 is a reformatted version of docu ment 42 1735 05 gt In MAC instructions upper case has replaced lower case for Reverse operation data gt datas In MAC instructions immediate shift value uses 5 bits to be coded not 4 Table 30 Function codes for Instr CoMACMus Instr Mus Instr CoMACMus rnd and Instr COMACR are 98 8 99 and F9 respectively The mneumonics and formats of the following addressing modes of Instr COMACM R su are CoMACRsu IDX amp 7 93 Xm 70 rrrr rqqq CoMACRsu IDX amp Rwm 8 rnd 93 Xm 71 rrrr rqqq CoMACRsu rnd 93 Xm 71 rrrr rqqq Correction in Multiplication examples CoMULu and coMULus For instructions BMOV BMOVN JNBS MUL MULU SUBCB Flag Z Z Z N N and Z corrected Jan 2000 Rev 6 First EDOCs release Section 1 1 4
61. i e the interrupt jump vector table For further information on the relation between trap numbers and interrupt or trap sources refer to the device user manual section on Interrupt and Trap Functions 11 197 Standard Instruction Set PROGRAMMING MANUAL 1 2 Instruction execution times The instruction execution time depends on where the instruction is fetched from and where the operands are read from or written to The fastest processing mode is to execute a program fetched from the internal ROM In this case most of the instructions can be processed in just one machine cycle All external memory accesses are performed by the on chip External Bus Controller EBC which works in parallel with the CPU Instructions from external memory cannot be processed as fast as instructions from the internal ROM because it is necessary to perform data transfers sequentially via the external interface In contrast to internal ROM program execution the time required to process an external program additionally depends on the length of the instructions and operands on the selected bus mode and on the duration of an external memory cycle Processing a program from the internal RAM space is not as fast as execution from the internal ROM area but it is flexible i e for loading temporary programs into the internal RAM via the chip s serial interface or end of line programming via the bootstrap loader The following description evaluates the mini
62. in the currently active context register bank Both Rw and Rb require four bits in the instruction format The base address of the current register bank is determined by the content of register CP Rw specifies a 4 bit word GPR address relative to the base address CP while Rb specifies a 4 bit byte GPR address relative to the base address CP Specifies direct access to any E SFR or GPR in the currently active context register bank reg requires eight bits in the instruction format Short reg addresses from 00h to EFh always specify E SFRs In this case the factor A equals 2 and the base address is 00 F000h for the standard SFR area or 00 FEOOh for the extended ESFR area reg accesses to the ESFR area require a preceding EXT R instruction to switch the base address Depending on the opcode of an instruction either the total word for word opera tions or the low byte for byte operations of an SFR can be addressed via reg Note that the high byte of an SFR cannot be accessed by the reg addressing mode Short reg addresses from FOh to FFh always specify GPRs In this case only the lower four bits of reg are significant for physical address generation therefore it can be regarded as identi cal to the address generation described for the Rb and Rw addressing modes Specifies direct access to any word in the bit addressable memory space bitoff requires eight bits in the instruction format Depending o
63. least significant 5 bits considered as unsigned data of any register directly or indirectly addressed operand When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is repeatable when op1 is not an immediate operand N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Carry flag is set according to the last most significant bit shifted out of ACC SV Set if the last shifted out bit is different from N E Set if the MAE is used Cleared otherwise SL Set if the content of the ACC is automatically saturated Not affected otherwise 189 197 CoSHL PROGRAMMING MANUAL Addressing Modes Examples 190 197 Mnemonic CoSHL CoSHL CoSHL CoSHL CoSHL CoSHL Rep Format Bytes Rw Yes nn rrrr r000 4 datas No A3 00 82 ssss s000 4 RW Yes 83 mm rrrr rqqq 4 3 ACC ACC lt lt 3 R3 ACC lt lt lt R3 4 0 R10 ACC lt lt lt R10 4 9 R10 R10 PROGRAMMING MANUAL CoSHR CoSHR Accumulator Logical Shift Right Group Shift Instructions Syntax CoSHR Operation count 1 C lt 0 DO WHILE count 0 lt 4 n 0 38
64. no round When rnd option is used MAL register is automatically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads MAC Flags N 2 SV E SL 0 0 T N Set if the most significant bit of the result is set Cleared otherwise 2 Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Always cleared SL Not affected 182 197 67 PROGRAMMING MANUAL CoMULus Addressing Modes Mnemonic Rep Format Bytes CoMULus RWm No A3nm 80 00 4 CoMULus Rw RWm A3 nm 88 00 4 CoMULus Rwm rnd No A3nm 81 00 4 CoMULus IDX amp No 93Xm800 0qqq 4 CoMULus IDX amp 93Xm880 0qqq 4 CoMULus IDX amp Rwm rnd No 93 81 0 0qqq 4 CoMULus 83nm800 0qqq 4 CoMULus Rwy No 83nm880 0qqq 4 CoMULus Rw RWwm8 rnd No 88nm810 0qqq 4 Examples CoMULus RO R1 rnd ACC lt RO R1 rnd CoMULus R2 R6 ACC R2 R6 R6 lt R6 2 CoMULus IDX1 QX0 R11 QRO IDX1 R11 R11 lt R11 IDX1 lt IDX1 QX0 CoMULus IDXO R15 lt IDX0 R15 CoMULus IDX0 QXO0 R9 QR1 rnd ACC lt IDX0 R9 rnd R9 lt R9 QR1 IDXO lt Multiplicati
65. op1 The flags are set according to the rules of subtraction The operands remain unchanged E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMP Rwy RWm 40 nm 2 CMP 48 n 10ii 2 CMP Rw 48 n 11ii 2 CMP 48 n OTHHE 2 CMP reg datay 46 RR 4 CMP reg mem 42RRMMMM 4 77 197 PROGRAMMING MANUAL CM PB Integer Compare Syntax CMPB op1 op2 Operation 1 lt gt Data Types BYTE Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s comple ment binary subtraction of op2 from op1 The flags are set according to the rules of subtraction The operands remain unchanged Flags Addressing Modes 78 197 E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Set if result equals zero Cleared otherwise
66. post increment source pointer by 1 ANDB Rb data Bitwise AND immediate byte data with direct GPR 2 6 21 3 41 6 2 ANDB data g Bitwise AND immediate byte data with direct register 2 8 4 6 8 12 4 ANDB reg mem Bitwise AND direct byte memory with direct register 2 8 4 6 8 12 4 reg Bitwise AND direct byte register with direct memory 2 8 4 6 8 12 4 Table 10 Logical instructions ky 27 197 Standard Instruction Set PROGRAMMING MANUAL Mnemonic Description 5 E 5 S 2 7 8 a 3 amp OR Rw Rw Bitwise OR direct word GPR with direct GPR 2623462 OR Rw Rw Bitwise OR indirect word memory with direct GPR 2 6 2 3 4 6 2 OR Rw Rw Bitwise OR indirect word memory with direct GPR 2 6 21 31 4 6 2 and post increment source pointer by 2 OR Rw datag Bitwise OR immediate word data with direct GPR 2623462 reg data Bitwise OR immediate word data with direct register 2 8 4 6 8 12 4 OR reg mem Bitwise OR direct word memory with direct register 2 8 4 6 8 12 4 OR mem reg Bitwise OR direct word register with direct memory 2 8 4 6 8 12 4 ORB Rb Rb Bitwise OR direct byte GPR with direct GPR 2161213141612 ORB Rb Rw Bitwise OR indirect byte memory with direct GPR 216123462 ORB Rb Rw Bitwise OR indirect byte memory with direct GPR 216123462 andpost in
67. set when a 40 bit arithmetic overflow underflow occurs 149 197 CoADD 2 PROGRAMMING MANUAL Addressing Modes Mnemonic Rep Format Bytes CoADD RWm No A3 nm 02 00 4 CoADD2 Rwy No A3 nm 42 00 4 CoADD Rwm Yes 93 Xm 02 rrrr rqqq 4 CoADD2 IDX amp Rwg9 Yes 93 Xm 42 rrrr rqqq 4 CoADD Yes 83 nm 02 rrrr rqqq 4 CoADD2 Yes 83 42 rrrr rqqq 4 Examples CoADD RO R1 lt ACC R1 RO CoADD2 R2 R6 ACC lt ACC 2 R6 R2 R6 lt R6 2 Repeat times CoADD IDX1 QX1 R10 QRO ACC lt ACC R10 IDX1 R10 lt R10 QRO IDX1 lt IDX1 QX1 Repeat MRW times CoADD2 R4 R8 QR1 ACC lt ACC 2 R8 R4 R8 lt R8 QR1 Addition Examples Instr MS 1 2 ACC before ACC after N 2 SV E 51 CoADD 0000 FFFF 00 0100 0000 00 OOFF 0000 0 0 1 0 CoADD2 0000 0200 00 0300 0000 00 0700 0000 0 0 0 0 CoADD 0 0000 4000 BFFF FFFF 7F FFFF FFFF 0 0 0 1 CoADD 0 0001 4000 7F BFFF 80 0000 0000 1 0 0 111 j CoADD 0 FFFF FFFF FF FFFF FFFF FF FFFF FFFE 1 0 1 0 CoADD 0 FFFFp 00 0000 0001 00 0000 0000 0 1 1 0 CoADD 0 FFFF FFFF 80 0000 0000 7
68. specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPD2 Rw data BO n 2 CMPD2 Rwy datay B6 Fn 4 CMPD2 B2FnMMMM 4 PROGRAMMING MANUAL CMPI1 CMPI1 Syntax Operation Data Types Description Flags Addressing Modes Integer Compare amp Increment by 1 CMPI1 1 op2 1 lt gt op2 1 op1 1 WORD This instruction is used to enhance the performance and flex ibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is incre mented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most sign
69. the internal Dual Port RAM except for the CoMOV instruction The following table shows the various combinations of pointer post modification for each of these 2 new addressing modes Symbol Mnemonic Address Pointer Operation IDX amp stands for IDX IDX lt IDX no op IDX IDX IDX 2 i 0 1 IDX lt IDX 2 i 0 1 IDX IDX i 20 1 lt IDX i 20 1 Rw 8 stands for Rwy Rw lt Rw Rw lt 2 n 0 15 lt Rw 2 0 15 Rw Rw lt n 0 15 20 1 QR 0 15 0 1 Table 27 Pointer post modification for Rw and IDXi amp addressing modes 1 IDX can only contain even values Therefore bit 0 always equals zero When using pointer post modification addressing modes the address pointed to i e the value in the IDX or Rw register must be a legal address even if its content is not modified An odd value e g in RO when using RO post modification adressing mode will trigger the class B hardware Trap 28h Illegal Word Operand Access Trap ILLOPA In this document the symbols Rw amp and IDX amp are used to refer to these addressing modes 139 197 MAC Instruction set PROGRAMMING MANUAL
70. to 21814 6 8 12 4 decrement GPR by 1 CMPD2 Rw data Compare immediate word data to direct GPR and 2 6 2 3 4 6 2 decrement GPR by 2 CMPD2 Rw Compare immediate word data to direct GPR and 2 8 4 6 8 12 4 decrement GPR by 2 CMPD2 Rw mem Compare direct word memory to direct GPR 21814 6 8 12 4 decrement GPR by 2 Table 12 Compare and loop instructions 30 197 67 PROGRAMMING MANUAL Standard Instruction Set pare amp Description T c 5 5 zz 3 s 3 1 Rw Compare immediate word data to direct and 2 6 2 3 4 6 2 increment GPR by 1 CMPI1 Rw Compare immediate word data to direct GPR and 2 8 4 6 8 12 4 increment GPR by 1 CMPI1 Rw mem Compare direct word memory to directGPR 21814 6 8 12 4 increment GPR by 1 CMPI2 Rw data Compare immediate word data to direct GPR and 2 6 2 3 4 6 2 increment GPR by 2 CMPI2 Rw Compare immediate word data to direct GPR and 2 8 4 6 8 12 4 increment GPR by 2 CMPI2 Rw mem Compare direct word memory to 21814 6 8 12 4 increment GPR by 2 Table 12 Compare and loop instructions Continued 5 Mnemonic Description 5 5 3 E z 32m PRIO
71. 1 op2 WORD Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly E 2 V Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Mnemonic Format Bytes MOV RWm FO nm 2 MOV Rw data EO n 2 MOV reg datay E6 RR 4 MOV A8 nm 2 MOV RWm 98 2 MOV RW 8 nm 2 MOV Rwm 88 nm 2 MOV Rw RW C8 2 MOV Rw 08 2 MOV Rwy Rwm E8 nm 2 MOV Rwy RwaHfdataqg D4 nm fit 4 MOV Rw data _ Rw 4 nm 4 MOV mem 84 0n MM MM 4 MOV mem 94 0n MM MM 4 MOV reg mem 2 4 MOV mem reg F6 4 105 197 MOVB PROGRAMMING MANUAL MOVB Syntax Operation Data Types Description Flags Addressing Modes 106 197 Move Data MOVB 1 op2 op1 lt op2 BYTE Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the flags a
72. 1 ACC lt tmp ELSE tmp op1 op2 ACC lt tmp END IF Syntax CoMACR 1 op2 Operation IF MP 1 THEN tmp lt op1 2 lt lt 1 lt tmp ACC ELSE tmp lt op1 op2 lt tmp ACC END IF Syntax CoMACR op1 op2 rnd Operation IF MP 1 THEN tmp lt op1 2 lt lt 1 lt tmp ACC 00 0000 8000 ELSE 156 197 571 PROGRAMMING MANUAL CoMAC R Data Types Result Description MAC Flags tmp op1 op2 lt tmp 00 0000 8000 END IF MAL 0 DOUBLE WORD 40 bit signed value Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended then the condition MP flag is set it is one bit left shifted then it is optionally negated prior being added subtracted to from the 40 bit ACC register content Finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The option is used to negate the specified product the R option is used to negate the accumulator content and finally the rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as w
73. 2 tmp lt op1 op2 ACC lt tmp IDX lt IDX CoMACMRus op2 rnd tmp lt op1 op2 ACC lt tmp 00 0000 8000 MAL lt 0 IDX amp lt 10 P P jo DOUBLE WORD 40 bit signed value Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended it is then option ally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specified product option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and This instruction might be repeated and performs two iy PROGRAMMING MANUAL CoMACM R us parallel memory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as illustrated by the following table
74. 2 Operation op1 lt op2 Data Types WORD Description Moves the contents of a MAC Unit register specified by the source operand op2 to the location specified by the destination operand op1 This instruction is repeatable with destination indirect addressing mode for example to clear a table in memory MAC Flags N 2 SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected Addressing Modes Note Examples 192 197 SL Not affected Mnemonic Rep Format Bytes CoSTORE Rw CoReg No wwww w000 00 4 CoSTORE Rw CoReg Yes nn wwww w000 rrrr rqqq 4 Due to pipeline side effects COSTORE cannot be directly followed by a MOV instruction the source operand of which is also a MAC Unit register such as MSW MAH MAL MAS MRW or MCW In this case NOP must be inserted between the CoSTORE and MOV instruction CoSTORE R11 QR1 MAS 11 lt limited ACC R11 lt R11 QR1 R2 lt MAL R2 lt R2 2 Repeat 3 times CoSTORE R2 MAL PROGRAMMING MANUAL CoSUB 2 R CoSUB 2 R Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description MAC Flags Subtract Arithmetic Instructions CoSUB op1 op2 tmp lt op2 op1 ACC lt ACC tmp CoSUB2 op1 op2 tmp lt 2 2 1 ACC lt ACC tmp CoSUBR op1 op2 t
75. CoMACus RW Yes 83nm90r rr rqqq 4 CoMACus Rwy RW Yes 83 AO rrrr rqqq 4 CoMACus Rw rnd Yes 83 91 rrrrirqqgq 4 CoMACRus Rw Rwm8 Yes 83 rrrr rqqq 4 CoMACRus Rwy rnd Yes 83 1 rrrrirqqq 4 Examples CoMACus R5 R8 rnd ACC lt ACC R5 R8 rnd CoMACus R2 R7 ACC lt ACC R2 R7 CoMACus IDXO R11 QRO ACC lt ACC IDXO R11 R11 lt R11 lt IDXO Repeat 3 times CoMACus IDX1 R9 lt ACC IDX1 R9 162 197 571 PROGRAMMING MANUAL CoMAC R su CoMAC R su Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description Mixed Multiply Accumulate amp Optional Round Multiply Multiply Accumulate Instructions CoMACsu op1 op2 tmp lt op1 op2 ACC lt tmp CoMACsu 1 op2 rnd tmp lt op1 op2 ACC lt tmp 00 0000 8000 MAL lt 0 CoMACsu op1 op2 tmp lt op1 op2 lt tmp CoMACRsu 2 tmp lt op1 op2 lt tmp ACC CoMACRsu op2 rnd tmp lt op1 op2 ACC lt tmp ACC 00 0000 8000 MAL lt 0 DOUBLE WORD 40 bit signed value Multiplies the two signed and unsigned 16
76. E 354 XORB Rb Rw Bitwise XOR indirect byte memory with direct GPR 2 6 2 3 4 6 2 and post increment source pointer by 1 XORB Rb data Bitwise immediate byte data with direct GPR 2 16 21 31 4 6 2 XORB data Bitwise immediate byte data with direct register 2 8 4 6 8 12 4 XORB reg mem Bitwise direct byte memory with direct register 2 8 4 6 8 12 4 XORB reg Bitwise direct byte register with direct memory 2 8 4 6 8 12 4 Table 10 Logical instructions Continued Mnemonic Description Q 3 BAND AND direct bit with direct bit 2181416 8 12 4 bitaddr bitaddr BCLR bitaddr Clear direct bit 216123 Compare direct bit to direct bit 2 8 4 8 12 bitaddr bitaddr BFLDH Bitwise modify masked high byte of bit addressable 2 8 4 6 8 12 4 bitoff maskg datag direct word memory with immediate data BFLDL Bitwise modify masked low byte of bit addressable 2 8 4 6 8 12 4 bitoff maskg datag direct word memory with immediate data BMOV Move direct bit to direct bit 21814 6 8 1214 bitaddr bitaddr BMOVN Move negated direct bit to direct bit 218 4 6 8 1214 bitaddr bitaddr BOR OR direct bit with direct bit 21814 6 8 1214 bitaddr bitaddr BSET bitaddr Set direct bit 314 XOR direct bit with direct bit 12 bitaddr bitaddr CMP Rw Rw Compare direct word GPR to direct GPR CMP Rw Rw Compare indirect word memory to di
77. GRAMMING MANUAL CoADD 2 CoADD 2 Group Syntax Operation Syntax Operation Data Types Result Description MAC Flags Note Add 40 bit Arithmetic Instructions CoADD op1 op2 tmp lt op2 op1 lt ACC tmp CoADD2op1 op2 tmp lt 2 2 1 ACC lt ACC tmp DOUBLE WORD 40 bit signed value Adds a 40 bit operand to the 40 bit Accumulator contents and store the result in the accumulator The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended 2 option indicates that the 40 bit operand is also multiplied by two prior being added to ACC When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFFy or FF 8000 0000 respectively This instruction is repeatable with indirect addressing modes and allows up to two parallel memory reads Set if the most significant bit of the result is set Cleared otherwise Z Setifthe result equals zero Cleared otherwise C Set if a carry is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected otherwise E Set if MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise The E flag is set when the nine highest bits of the accumulator are not equal The SV flag is
78. MANUAL CoLOAD 2 Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description MAC Flags 154 197 Load Accumulator 40 bit Arithmetic Instructions CoLOAD op1 op2 tmp lt op2 op1 ACC lt 0 tmp CoLOAD op1 op2 tmp lt op2 op1 ACC lt 0 tmp CoLOAD2 op1 op2 tmp lt 2 2 1 ACC lt 0 tmp CoLOAD2 op1 op2 tmp lt 2 2 1 ACC lt 0 tmp DOUBLE WORD 40 bit signed value Loads the accumulator with a 40 bit source operand The 40 bit source operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended 2 and options indicate that the 40 bit operand is also multiplied by two or and negated respectively prior being stored in the accumu lator The option indicates that the source operand is 2 s comple mented When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is not repeatable and allows up to two parallel memory reads N 2 SV E SL N Set if the most significant bit of the result is set Cleared other wise Z Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Not affected
79. MM 4 99 197 PROGRAMMING MANUAL J M Pl Indirect Conditional Jump Syntax JMPI 1 op2 Operation IF op1 1 THEN IP lt 0 2 ELSE Next Instruction END IF Description If the condition specified by op1 is met a branch to the Condition Codes Flags Addressing Modes 100 197 absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPI instruction is executed normally See Condition code Table 24 on page 48 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JMPI cc Rwy 9C cn 2 PROGRAMMING MANUAL JMPR JMPR Syntax Operation Description Condition Codes Flags Addressing Modes Relative Conditional Jump JMPR 1 op2 IF op1 1 THEN IP lt IP sign_extend op2 ELSE Next Instruction END IF If the condition specified by op1 is met program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction If the specified condition is not met program execution continues normally with the instruction following the JMPR instruct
80. R Rw Rw Determine number of shift cycles to normalize direct 2161213141612 word GPR and store result in direct word GPR Table 13 Prioritize instructions 5 Description 5 5 9 E 3 ASHR Rw Rw Arithmetic sign bit shift right direct word GPR 2161213141612 number of shift cycles specified by direct GPR ASHR Rw data Arithmetic sign bit shift right direct word GPR 2161213141612 number of shift cycles specified by immediate data Table 14 Shift and rotate instructions 31 197 Standard Instruction Set PROGRAMMING MANUAL um lt Mnemonic Description T c 5 5 9 3 ROL Rw Rw Rotate left direct word GPR number of shift cycles 2 6 2 3 4 6 2 specified by direct GPR ROL Rw data Rotate left direct word GPR number of shift cycles 2 6 2 3 4 6 2 specified by immediate data ROR Rw Rw Rotate right direct word GPR number of shift cycles 2 6 2 3 4 6 2 specified by direct GPR ROR Rw data Rotate right direct word GPR number of shift cycles 2 6 2 3 4 6 2 specified by immediate data SHL Rw Rw Shift left direct word GPR number of shift cycles 262346 2 specified by direct GPR SHL Rw data Shift left direct word GPR number of shift cycles 262346 2 specified by immediate data SHR Rw Rw Shift right direct word GPR num
81. RMALLY ESCC QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky 197 197
82. RST B8 2 MOV Rwm RW B9 2 MOVB Rw Rb BA 4 JNBS bitaddrg rel BB 2 CALLR rel BC 2 ASHR data BD 2 JMPR cc_SLE rel BE 2 BCLR bitaddrg 11 BF 2 BSET bitaddrg 11 CO 2 MOVBZ Rbm C1 C2 4 MOVBZ reg mem Table 21 Instruction set ordered by Hex code Continued 43 197 Standard Instruction Set PROGRAMMING MANUAL at Number of Bytes Mnemonic Operand 4 Rw CoReg C4 4 MOV Rw t data Rw C5 4 MOVBZ mem reg C6 4 SCXT reg datay C7 C8 2 MOV C9 2 MOVB CA 4 CALLA caddr CB 2 RET CC 2 NOP CD 2 JMPR SLT rel CE 2 BCLR bitaddro 12 CF 2 BSET bitaddrg 12 DO 2 MOVBS Rbm D1 2 ATOMIC EXTR gt 02 4 MOVBS reg mem D3 4 10 18 Rwn 04 4 MOV Rw t data D5 4 MOVBS mem reg D6 4 SCXT reg mem D7 4 EXTP R EXTS R pag datas D8 2 MOV Rw 09 2 MOVB Rw DA 4 CALLS seg caddr DB 2 RETS DC 2 EXTP R EXTS R RW datas DD 2 JMPR cc_SGE rel DE 2 BCLR bitaddrg DF 2 BSET bitaddrg EO 2 MOV Rwp E1 2 MOVB Rb data4 E2 4 PCALL reg caddr 4 4 MOVB Rw data Rb Table 21 Instruction set ordered by Hex code Continued 44 197 PROGRAMMING MANUAL S
83. T Syntax Operation Description Flags Addressing Modes Disable Watchdog Timer DISWDT Disable the watchdog timer This instruction disables the watchdog timer The watchdog timer is enabled by a reset The DISWDT instruction allows the watchdog timer to be disabled for applications which do not require a watchdog function Following a reset this instruction can be executed at any time until either a Service Watchdog Timer instruction SRVWDT or an End of Initial ization instruction EINIT are executed Once one of these instructions has been executed the DISWDT instruction will have no effect To insure that this instruction is not acciden tally executed it is implemented as a protected instruction E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes DISWDT A5 5A A5 A5 4 85 197 DIV PROGRAMMING MANUAL DIV 16 by 16 Signed Division Syntax DIV Operation MDL lt MDL op1 MDH lt MDL mod op1 Data Types WORD Description Performs a signed 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags E 2 V 0 E S 0 E Always cleared Z Set if result equals zero
84. T pin 2 8 4 6 8 124 EXTR data Begin EXTended Register sequence 216 2 3 4 6 2 EXTP Rw data Begin EXTended Page sequence 216213146 2 EXTP data Begin EXTended Page sequence 2181416 8 124 EXTPR Rw datay Begin EXTended Page and Register sequence 2 16 2 3 46 2 pag datap Begin EXTended Page and Register sequence 2 8 4 6 8 12 4 EXTS Rw data Begin EXTended Segment sequence 216 2 3 4 6 2 EXTS data Begin EXTended Segment sequence 218 4 6 8 12 4 EXTSR Rw datao Begin EXTended Segment and Register sequence 9216123146 2 EXTSR seg 4 gt Begin EXTended Segment and Register sequence 92181416 8 1214 IDLE Enter Idle Mode 2 8 4 6 8 124 PWRDN Enter Power Down Mode supposes NMI pin is 2 8 4 6 8 12 4 SRST Software Reset 2181416 8 112 4 SRVWDT Service Watchdog Timer 2 8 41 61 8112 4 Table 19 System Control Instructions Mnemonic Description amp 8 Null operation 26234162 Table 20 Miscellaneous instructions 36 197 571 PROGRAMMING MANUAL Standard Instruction Set 1 5 Instruction set ordered by opcodes The following pages list the instruction set ordered by their hexadecimal opcodes This is used to identify specific instructions when reading executable code i e during the debugging phase Notes for Opcode Lists 1 These instructions are encoded by means of additional bits in the operand field of the instruction xOh
85. al groups Multiply and Multiply Accumulate Instructions 40 bit Arithmetic Instructions Shift Instructions Compare Instructions Transfer Instructions The instructions are described in alphabetical order 5 147 197 CoABS PROGRAMMING MANUAL CoABS Group Syntax Operation Syntax Operation Data Types Result Description MAC Flags Addressing Modes 148 197 Absolute Value 40 bit Arithmetic Instructions CoABS ACC lt Abs ACC CoABS op1 op2 ACC lt Abs 2 1 ACCUMULATOR DOUBLE WORD 40 bit signed value Compute the absolute value of the Accumulator if no operands are specified or the absolute value of a 40 bit source operand and load the result in the Accumulator The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended This instruction is not repeatable N 2 SV E SL 0 _ N Set if the most significant bit of the result is set Cleared other wise 2 Set if the result equals zero Cleared otherwise C Always cleared SV Not affected E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Mnemonic Rep Format Bytes CoABS No A3 00 1A 00 4 CoABS 00 4 IDX amp 93 Xm 0 0qqq 4 CoABS Rwy No 83 nm CA 0 0qqq 4 PRO
86. and op2 MSW which is then sign extended If the contents of the ACC register is greater than the 40 bit operand then the ACC register is loaded with it Otherwise the ACC register remains unchanged The MS bit of the MCW register does not affect the result This instruction is repeatable with indirect addressing modes N Z SV E SL 0 Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Cleared always SV Not affected E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC register is changed Not affected otherwise lt min ACC R6 R5 Mnemonic Rep Format Bytes CoMIN RWm No A3 nm 7A 00 4 CoMIN Yes 93 7Arrrrrqqqg 4 CoMIN RWm8 Yes 83 4 Examples CoMIN IDX1 QX0 R11 QR1 ACC lt min ACC R11 IDX1 R11 lt R11 QR1 IDX1 lt IDX1 QX0 CoMIN R1 R10 ACC lt min ACC R10 R1 R6 lt R6 QRO 175 197 CoMOV PROGRAMMING MANUAL CoMOV Memory to Memory Move Group Transfer Instructions Syntax CoMOV opt op2 Operation 1 lt op2 Data Types WORD Description Moves the contents of the memory location specified by the source operand op2 to the memory location specified by the destination opera
87. ands op1 and op2 The obtained unsigned 32 bit product is first zero extended and then optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified product option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and This instruction might be repeated and allows up to two parallel memory reads N 2 SV E SL 159 197 CoMAC R u PROGRAMMING MANUAL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACu Rwp RWm No nm 10 00 4 CoMACu RWm No
88. ber of shift cycles 2 6 2 3 4 6 2 specified by direct GPR SHR Rw data Shift right direct word GPR number of shift cycles 2 6 2 3 4 6 2 specified by immediate data Table 14 Shift and rotate instructions Continued 5 3 Description E glg 8 2 gt Elala MOV Rw Rw Move direct word GPR to direct GPR 2162346 2 MOV Rw data4 Move immediate word data to direct GPR 21623462 MOV datay Move immediate word data to direct register 2 8 4 6 8 12 4 MOV Rw Rw Move indirect word memory to direct GPR 2162346 2 MOV Rw Rw Move indirect word memory to direct GPR 2162346 2 and post increment source pointer by 2 MOV Rw Rw Move direct word GPR to indirect memory 2162314 2 MOV Rw Pre decrement destination pointer by 2 2 6 2 3 4 6 2 move direct word GPR to indirect memory MOV Rw Move indirect word memory to indirect 2 6 2 3 4 6 2 ory Table 15 Data movement instructions 32 197 ky PROGRAMMING MANUAL Standard Instruction Set Mnemonic Description 9 2 gt S tn MOV Rw Rw Move indirect word memory to indirect mem 2 6 2 3 4 6 2 ory amp post increment destination pointer by 2 MOV Rw Rw Move indirect word memory to indirect 2 6 2 3 4 6 2 ory amp
89. caddr must always contain a 0 otherwise a hardware trap would occur Represents an 8 bit signed word offset address relative to the current Instruction Pointer contents which points to the instruction after the branch instruction Depending on the off set address range either forward 00h to 7Fh or backward rel 80h to FFh branches are possible The branch instruction itself is repeatedly executed when rel 1 for a word sized branch instruction or 2 for double word sized branch instruction The 16 bit branch target instruction address is determined indirectly by the content of a word GPR In contrast to indirect data addresses indirectly specified code addresses are NOT calculated by additional pointer registers e g DPP registers Branches MAY NOT be taken to odd code addresses Therefore to prevent a hardware trap the least signifi cant bit of the address pointer GPR must always contain a 0 Specifies an absolute code segment number All devices support 256 different code seg ments so only the eight lower bits of the seg operand value are used for updating the CSP register Specifies a particular interrupt or trap number for branching to the corresponding interrupt or trap service routine by a jump vector table Trap numbers from to 7Fh can be spec ified which allows access to any double word code location within the address range 00 0000h 00 01FCh in code segment 0
90. carefully see ATOMIC and EXTended instructions on page 53 E 2 V C N E Not affected 2 Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes ATOMIC gt D1 00 0 2 PROGRAMMING MANUAL BAND BAND Syntax Operation Data Types Description Flags Addressing Modes Bit Logical AND BAND 1 op2 1 lt op1 op2 BIT Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 2 V OR AND XOR E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Mnemonic Format Bytes BAND bitaddrz z bitaddro 6A ZZ qz 4 63 197 BCLR PROGRAMMING MANUAL B L R Bit Clear Syntax BCLR Operation 1 lt 0 Data Types BIT Description Clears the bit specified by op1 This instruction is primarily used for peripheral and system control Flags E 2 0 0 0 Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Addressing Modes Mnemonic Format Bytes BCLR bitaddrg
91. cesses via the bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any long or indirect address an EXTSR instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits A15 A0 The value of op2 defines the length of the effected instruction sequence The EXTSR instruction must be used carefully see ATOMIC and EXTended instructions on page 53 E 2 V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes EXTSR Rwnm datas DC 10 2 EXTSR seg datao 07 10 0 55 00 4 95 197 IDLE PROGRAMMING MANUAL IDLE Syntax Operation Description Flags Addressing Modes 96 197 Enter Idle Mode IDLE Enter Idle Mode This instruction causes the part to enter the idle mode In this mode the CPU is powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt occurs To insure that this instruction is not accidentally executed it is implement
92. complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and R This instruction might be repeated and performs two parallel memory iy PROGRAMMING MANUAL CoMACM R u reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as illustrated by the following table Addressing Mode Overwritten Address IDX no change IDX IDX 2 IDX IDX 2 IDX QX IDX IDX QXj IDX MAC Flags N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACMu 0 Rwm8 Yes 93 Xm 18rrrr rqqq 4 CoMACMu IDX amp Yes 93 Xm 28 rrrr rqqq 4 CoMACMu IDX amp Rwm 8 rnd Yes 93 Xm 19 rrrr rqqq 4 C
93. crement source pointer by 1 MOVB Rb Rw data g Move indirect byte memory by base plus 4 10 6 8 10 14 4 stant to direct GPR MOVB Rw Ro Move direct byte GPR to indirect memory 2 8 4 6 8 12 4 base plus constant MOVB Rw mem Move direct byte memory to indirect memory 2 8 4 6 8 12 4 MOVB mem Rw Move indirect byte memory to direct memory 2 8 4 6 8 12 4 MOVB reg mem Move direct byte memory to direct register 2 8 4 6 8 12 4 MOVB mem reg Move direct byte register to direct memory 21814 6181124 Table 15 Data movement instructions Continued 6571 33 197 Standard Instruction Set PROGRAMMING MANUAL Mnemonic Description 2 2 MOVBS Rw Rb Move direct byte GPR with sign extensionto 2 6 2 3 4 6 2 direct word GPR MOVBS reg mem Move direct byte memory with sign extension 2 8 4 6 8 12 4 to direct word register MOVBS mem reg Move direct byte register with sign extension 2 8 4 6 8 12 4 to direct word memory MOVBZ Rw Rb Move direct byte GPR with zero extensionto 2 6 2 3 4 6 2 direct word GPR MOVBZ reg mem Move direct byte memory with zero extension 2 8 4 6 8 12 4 to direct word register MOVBZ mem reg Move direct byte register with zero extension 2 8 4 6 8 12 4 to direct word
94. crement source pointer by 1 ORB Rb data3 Bitwise OR immediate byte data with direct GPR 2162346 2 ORB reg data Bitwise OR immediate byte data with direct register 2 8 4 6 8 1214 ORB reg mem Bitwise OR direct byte memory with direct register 2 8 4 6 8 12 4 ORB mem reg Bitwise OR direct byte register with direct memory 2 8 4 6 8 121 4 XOR Rw Rw Bitwise XOR direct word GPR with direct GPR 2161213141612 XOR Rw Rw Bitwise indirect word memory with direct GPR 2 6 2 3 4 6 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR 2 6 2 3 4 16 2 and post increment source pointer by 2 XOR Rw datag Bitwise XOR immediate word data with direct GPR 2 6 2 314 6 2 XOR Bitwise XOR immediate word data with direct regis 2 8 4 6 8 12 4 ter XOR reg mem Bitwise direct word memory with direct register 2 8 4 6 8 12 4 XOR mem reg Bitwise direct word register with direct memory 2 8 4 6 8 12 4 XORB Rb Rb Bitwise XOR direct byte GPR with direct GPR 21612134162 XORB Rb Rw Bitwise indirect byte memory with direct GPR 2 6 2 3 4 6 2 Table 10 Logical instructions Continued 28 197 571 PROGRAMMING MANUAL Standard Instruction Set TOME Mnemonic Description Q c 5 5 Shs 8 EL
95. ct immediate byte data from direct register 21841618112 4 SUBB Subtract direct byte memory from direct register 2181416 811214 SUBB Subtract direct byte register from direct memory 21841618112 4 SUBC Rw Rw Subtract direct word GPR from direct GPR with Cary 2 6 2 3 4 6 2 SUBC Rw Rw Subtract indirect word memory from direct GPR with 216234 6 2 Carry SUBC Rw Rw Subtract indirect word memory from direct GPR with 2161234612 Carry and post increment source pointer by 2 SUBC data3 Subtract immediate word data from direct GPR with 2 6 2 4 6 2 Carry SUBC data g Subtract immediate word data from direct register 2 8 4 6 8 12 4 with Carry SUBC Subtract direct word memory from direct register with 2 8 4 6 8 12 4 Carry SUBC reg Subtract direct word register from direct memory with 2 8 4 6 8 12 4 Carry SUBCB Rb Rb Subtract direct byte GPR from direct GPR with Cary 2 6 2 3 4 6 2 SUBCB Rb Rw Subtract indirect byte memory from direct GPR with 2 6 2 3 46 2 Carry SUBCB Rb Rw Subtract indirect byte memory from direct GPR 2 6 2 3 46 2 Carry and post increment source pointer by 1 SUBCB Rb datag Subtract immediate byte data from direct GPR with 2 6 2 3 4 6 2 Carry Table 9 Arithmetic instructions Continued 26 197 PROGRAMMING MANUAL Standard Instruction Set
96. d O N The carry flag is set according to the last most significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SHL RWm 4 2 SHL Rwy 5C n 2 PROGRAMMING MANUAL SHR SHR Syntax Operation Data Types Description Flags Addressing Modes Shift Right SHR 1 op2 count lt op2 lt 0 V lt 0 DO WHILE count z 0 C v V lt 10 0 1 lt op1 5 4 N 0 14 1 15 lt count count 1 END WHILE WORD V 8 Shifts the destination word operand op1 right by as many times as specified by the source operand op2 The most significant bits of the result are filled with zeros accordingly Since the bits shifted out effectively represent the remainder the Overflow flag is used instead as a Rounding flag This flag together with the Carry flag helps the user to determine whether the remainder bits lost were greater than less than or equal to one half an least significant bit Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E 2 V 0 5 5 Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the shift operation a 1 is shifted out of the
97. d product R option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that rnd and are exclusive as well as and This instruction might be repeated and performs two iy PROGRAMMING MANUAL CoMACM R su parallel memory reads In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDX overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDX as illustrated by the following table Addressing Mode Overwritten Address IDX no change IDX 10 2 IDX IDX 2 IDX QX QX IDX MAC Flags N Z SV E SL N Set if the m s b of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes Mnemonic Rep Format Bytes CoMACMsu IDX amp Rwm8 Yes 93 Xm 58 rr
98. ddr Direct 16 bit jump target address Updates the Instruction Pointer seg Direct 8 bit segment address Updates the Code Segment Pointer rel Signed 8 bit jump target word offset address relative to the Instruction Pointer of the following instruction trap7 Immediate 7 bit trap or interrupt number Extension operations The EXT instructions override the standard DPP addressing scheme pag Immediate 10 bit page address seg Immediate 8 bit segment address 22 197 ky PROGRAMMING MANUAL Standard Instruction Set Branch condition codes cc Symbolically specifiable condition codes cc_UC Unconditional cc_Z Zero cc_NZ Not Zero cc_V Overflow cc_NV No Overflow cc_N Negative cc_NN Not Negative cc_C Carry cc_NC No Carry cc_EQ Equal cc_NE Not Equal cc_ULT Unsigned Less Than cc_ULE Unsigned Less Than or Equal cc_UGE Unsigned Greater Than or Equal cc_UGT Unsigned Greater Than cc_SLE Signed Less Than or Equal cc_SLT Signed Less Than cc_SGE Signed Greater Than or Equal cc_SGT Signed Greater Than cc_NET Not Equal and Not End of Table ky 23 197 Standard Instruction Set PROGRAMMING MANUAL 5 3 Mnemonic Description 9 lt ra 2 zzi ADD Rw Rw Add direct word GPR to direct GPR 262134612 ADD Rw Rw Add indirect word memory to direct GPR 216234612 ADD Rw Rw Add indirect word
99. e locked The EXTS instruction becomes immediately active such that no addi tional NOPs are required For any long or indirect address in EXTS instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits 15 0 The value of op2 defines the length of the effected instruction sequence Note The EXTS instruction must be used carefully see ATOMIC and EXTended instructions on page 53 Flags Addressing Modes 94 197 E 2 V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes EXTS Rwm datap DC 00 2 EXTS gt 07 00 0 55 00 4 iy PROGRAMMING MANUAL EXTSR EXTSR Syntax Operation Description Note Flags Addressing Modes Begin EXTended Segment amp Register Sequence EXTSR op2 count lt op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Segment op1 AND SFR range Extended DO WHILE count 0 AND Class B trap condition z TRUE Next Instruction count count 1 END WHILE count 0 Data Page DPPx AND SFR range Standard Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit ac
100. ed DO WHILE count 0 AND Class B trap condition z TRUE Next Instruction count count 1 END WHILE count 0 Data Page DPPx AND SFR range Standard Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked For any long or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 AO is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence The EXTPR instruction must be used carefully see ATOMIC and EXTended instructions on page 53 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes EXTPR Rwnm DC 11 m 2 EXTPR data D7 11 0 pp 0 00pp 4 iy PROGRAMMING MANUAL EXTR EXTR Syntax Operation Description Note Flags Addressing Modes Begin EXTended Register Sequence EXTR op1 count op1 1 op1
101. ed as a protected instruction E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes IDLE 87 78 87 87 4 PROGRAMMING MANUAL JB JB Syntax Operation Data Types Description Flags Addressing Modes Relative Jump if Bit Set JB 1 op2 IF op1 1 THEN IP lt IP sign_extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JB instruction If the specified bit is clear the instruction following the JB instruction is executed E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JB bitaddrg rel 8A QQ rr q0 4 97 197 JBC PROGRAMMING MANUAL JBC Syntax Operation Data Types Description Flags Addressing Modes 98 197 Relative Jump if Bit Set amp Clear Bit JBC 1 op2 IF op1 1 THEN op1 0 IP IP sign extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is set program execution cont
102. ell as and This instruction might be repeated and allows up to two parallel memory reads N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise 157 197 CoMAC R PROGRAMMING MANUAL Addressing Modes Examples CoMAC R3 R4 rnd CoMAC R2 R64 CoMAC IDXO QXO RM QRO Repeat MRW times CoMAC R3 R7 CoMACR IDX1 84 rnd 158 197 Repeat 3 times CoMAC IDX1 QX1 R9 QR1 ACC lt ACC IDX1 R9 Mnemonic Rep Format Bytes CoMAC No nm DO 00 4 CoMAC Rw No 00 4 CoMAC rnd 01 00 4 CoMACR No F000 4 CoMACR Rwm rnd No A3 nm F1 00 4 CoMAC IDX amp Yes 93XmD0Orrrr rqqq 4 CoMAC IDXj amp Yes 93 Xm EO 4 CoMAC IDX amp 91 rnd Yes 93 Xm D1 rrrrirqqq 4 CoMACR IDX amp 8 Yes 93 Xm rrrr rqqq 4 CoMACR IDX amp rnd Yes 93 Xm F1 rrrr rqqq 4 CoMAC RWm8 Yes 83 nm DO rrr
103. ered as unsigned data of any register directly or indirectly addressed operand Without rnd option the MS bit of the MCW register does not affect the result While with rnd option and if the MS bit is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is repeatable when op 1 is not an immediate operand N 2 SV E SL N Set if the most significant bit of the result is set Cleared other wise Z Set if the result equals zero Cleared otherwise C Set if a carry is generated rnd Cleared otherwise SV Setif an arithmetic overflow occurred rnd Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated rnd Not affected otherwise 151 197 CoASHR PROGRAMMING MANUAL Addressing Modes Examples 152 197 Mnemonic CoASHR CoASHR CoASHR CoASHR CoASHR CoASHR CoASHR CoASHR CoASHR Rwy rnd datas datas rnd Rwm8 rnd 3 rnd R3 R10 Rep Format Yes AA rrrr r000 Yes rrrr r000 No A3 00 A2 ssss s000 No A3 00 B2 ssss s000 Yes 83 mm AA rrrr rqqq Yes 83 mm BA rrrr rqqq lt ACC gt gt a 3 rnd lt gt gt 4 0 lt ACC gt gt R10 4 9 R10 R10 QRO 2
104. erwise C Set if a carry is generated from the most signifi cant bit of the specified data type Cleared other wise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ADDB Rb Rbm 01 nm 2 ADDB Rb 09 10 2 ADDB Rbp Rw 09 n 11ii 2 ADDB Rb datag 09 n O 2 ADDB reg dataig 07 RR 4 ADDB reg mem 03 RR MM MM 4 ADDB mem reg 05 RRMMMM 4 PROGRAMMING MANUAL ADDC ADDC Syntax Operation Data Types Description Flags Addressing Modes Integer Addition with Carry ADDC 1 op2 op1 lt op1 op2 C WORD Performs a 2 s complement binary addition of the source operand specified by op2 the destination operand specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic E 2 V C N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most signifi cant bit of the specified data type Cleared other wise N Set if the most significant bit of the result is set Cleared otherwise M
105. es to the SP register as shown in the following example SP 0FB00h explicit update of the stack pointer SCXT R1 10008 implicit decrement of the stack pointer H 2 States In each of these above cases the extra state times can be avoided by putting other suitable instructions before the instruction 4 reading the SFR External operand reads 1 ACT Any external operand reading via a 16 bit wide data bus requires one additional ALE Cycle Time Reading word operands via an 8 bit wide data bus takes twice as much time 2 ALE Cycle Times as the reading of byte operands External operand writes 0 State 1 ACT Writing an external operand via a 16 bit wide data bus takes one additional ALE Cycle Time For timing calculations of external program parts this extra time must always be considered The value of which must be considered for timing evaluations of internal program parts may fluctuate between 0 state times and 1 ALE Cycle Time This is because external writes are normally performed in parallel to other CPU operations Thus could already have been considered in the standard processing time of another instruction Writing a word operand via an 8 bit wide data bus requires twice as much time 2 ALE Cycle Times as the writing of a byte operand 16 197 571 PROGRAMMING MANUAL Standard Instruction Set Jumps into the internal ROM space
106. ext Instruction count count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTP instruction becomes immediately active such that no addi tional NOPs are required For any long or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits 13 0 is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence The EXTP instruction must be used carefully see ATOMIC and EXTended instructions on page 53 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes EXTP Rwm DC 01 m 2 EXTP pag 4 gt 07 01 0 0 00 4 91 197 EXTPR PROGRAMMING MANUAL EXTPR Syntax Operation Description Note Flags Addressing Modes 92 197 Begin EXTended Page amp Register Sequence EXTPR op2 count lt op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Page op1 AND SFR range Extend
107. ff the system stack Execution resumes at the instruction which had been interrupted The previous system state is restored after the PSW has been popped The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register Flags Addressing Modes 122 197 2 V C N S S S S E Restored from the PSW popped from stack 2 Restored from the PSW popped from stack V Restored from the PSW popped from stack C Restored from the PSW popped from stack N Restored from the PSW popped from stack Mnemonic Format Bytes RETI FB 88 2 PROGRAMMING MANUAL RETP RETP Syntax Operation Data Types Description Flags Addressing Modes Return from Subroutine amp Pop Word RETP 1 lt SP SP lt SP 2 tmp lt SP SP lt SP 2 op1 lt tmp WORD Returns from a subroutine The IP is first popped from the System stack and then the next word is popped from the system stack into the operand specified by op1 Execution resumes at the instruction following the CALL instruction in the calling routine E Set if the value of the word popped into operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Set if the value of the word popped into operand op1 equals zero Cleared otherwise V Not affected C Not affected N Set if the most sign
108. fset 3 bit Encoding IDXO Th no op 1n IDXO 2n 2h IDXO IDXO 4n QRO 4n IDXO 5n QRO 5n IDXO QX1 6h QR1 6h IDXO QX1 7n QR1 7n IDX1 9n IDX1 An IDX1 IDX1 Ch IDX1 QXO Dy IDX1 QX1 En IDX1 QX1 Table 31 IDX Addressing Mode Encoding GPR offset Encoding 2 4 6 Flag states Flag Description Unchanged Modified 2 4 7 Repeated instruction syntax Repeatable instructions CoXXX are expressed as follows when repeated Repeat datas times CoXXX or Repeat MRW times CoXXX When is invoked the instruction is repeated MRW 1 times therefore the maximum number of times an instruction can be repeated is 8 192 213 times datas is an integer value specifying the number of times an instruction is repeated datas must be less than 32 Therefore CoXXX can only be repeated less than 32 times When the MRW register is used in the repeat instruction the 5 bit repeat field is set to 1 146 197 571 PROGRAMMING MANUAL MAC Instruction set 2 4 8 Shift value The shifter authorizes only 8 bit left right shifts Shift values must be between 0 8 inclusive 2 5 MAC instruction descriptions Each instruction is described in a standard format See MAC instruction conventions on page 144 for detailed information about the instruction conventions The MAC instruction set is divided into 5 function
109. g ZZ 8 bit word address of the destination bit bitoff THE 8 bit immediate constant datag Qo 8 bit immediate constant maskg pp 0 00pp 10 bit page address pag10 MM MM 16 bit address mem or caddr low byte high byte THE HH 16 bit immediate constant data46 low byte high byte Table 26 Instruction format symbols 52 97 ky PROGRAMMING MANUAL Standard Instruction Set Number of bytes Specifies the size of an instruction in bytes All ST10 instructions are either 2 or 4 bytes Instructions are classified as either single word or double word instructions Representation in the N2N N4N N6N N8N Assembler Listing ILJ 1 3 J 3 J High Byte 2nd word Low Byte 2nd word High Byte 1st word Low Byte ist word Internal Organization MSB lt Bits in ascending order LSB d Fd Figure 3 Instruction format representation 1 7 ATOMIC and EXTended instructions ATOMIC EXTR EXTP EXTS EXTPR EXTSR instructions disable standard and PEC inter rupts and class A traps during a sequence of the following 1 4 instructions The length of the sequence is determined by an operand 1 or op2 depending on the instruction The EXTended instructions also change the addressing mechanism during this sequence see detailed instruction description The ATOMIC and EXTended instructions become active immediately so no additional NOPs are required All instructions requiring multiple cycles or hold sta
110. gns gogns tpa my x eyepg My x ney my 934 elgg NAH HOH 8 umy my gg lt lans gans ans gans ans gans ans Sgns gns gans anog lt odav goday oady goaav odav MAW x MH ASYN E umy W3W 53H WAN 9 eyeps ely mg u mu mu UU aav aav saav aav saav aav amp IX 2X X V sx 9 1X 8 6 4X 18 197 PROGRAMMING MANUAL Standard Instruction Set Table 8 lists the instructions by their mnemonic and identifies the addressing modes that may be used with a specific instruction and the instruction length depending on the selected addressing mode in bytes Mnemonic Addressing modes 8 Addressing modes 8 a a RWm 2 2 ADDC B 2 AND B Rw 2 DIV 2 OR B datag 2 DIVL SUBIB reg dataig 4 DIVLU SUBCI B reg mem 4 DIVU XOR B mem reg 4 MUL 2 MULU ASHR Rw RWm 2 CMPD1 2 Rw data ROL ROR Rw data 2 CMPI1 2 Rw datay SHL
111. ificant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPH Rw data 80 n 2 CMPI1 Rw datay 86 Fn 4 CMPI1 Rw mem 82 Fn MM MM 4 81 197 CMPI2 PROGRAMMING MANUAL CMPI2 Syntax Operation Data Types Description Flags Addressing Modes 82 197 Integer Compare amp Increment by 2 CMPI2 1 op2 1 lt gt op2 1 op1 2 WORD This instruction is used to enhance the performance and flex ibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is incre mented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table N Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes CMPI2 Rw data
112. ificant bit of the word popped into operand op1 is set Cleared otherwise Mnemonic Format Bytes RETP reg EB RR 2 123 197 RETS PROGRAMMING MANUAL RETS Return from Inter Segment Subroutine Syntax RETS Operation IP lt SP SP lt SP 2 CSP lt SP SP lt SP 2 Description Returns from an inter segment subroutine The IP and CSP are popped from the system stack Execution resumes at the instruction following the CALLS instruction in the calling routine Flags E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Addressing Mode Mnemonic Format Bytes RETS DB 00 2 124 197 PROGRAMMING MANUAL ROL ROL Syntax Operation Data Types Description Flags Addressing Modes Rotate Left ROL 1 op2 count lt op2 lt 0 DO WHILE count z 0 lt 1 15 0p1 lt op15 1 1 15 10 lt C count count 1 END WHILE WORD Rotates the destination word operand left by as many times as specified by the source operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E 2 V 0 0 S Always cleared Set if result equals zero Cleared otherwise Always cleared The carry flag is set according to the la
113. ified for System Control Instructions and for those of the branch instructions which do not access any explicitly addressed data 1 6 5 Description Describes the operation of the instruction 1 6 6 Condition code The following table summarizes the 16 possible condition codes that can be used within Call and Branch instructions and shows the mnemonic abbreviations the test executed for a specific condition and the 4 bit condition code number Condition Code Test Description Condition Code Mnemonic cc Number c cc_UC 1 1 Unconditional Oh 7 2 1 Zero 2h cc NZ Z 0 Not zero 3h cc_V V 1 Overflow 4h cc NV V 0 No overflow 5h cc_N N 1 Negative 6h NN N 0 Not negative 7h cc_C 1 Carry 8h cc_NC 0 carry 9h cc EQ Z 1 Equal 2h cc_NE Z 0 Not equal 3h Table 24 Condition codes 48 197 571 PROGRAMMING MANUAL Standard Instruction Set Condition Code a Condition Code Test Description Mnemonic cc Number c cc ULT 1 Unsigned less than 8h cc_ULE ZvC 1 Unsigned less than or equal Fh cc_UGE 0 Unsigned greater than or equal 9 cc_UGT 2 0 Unsigned greater than Eh cc SLT V 1 Signed less than Ch cc SLE Zv N 6 V 1 Signed less than or equal Bh cc SGE G6 V 0 Signed greater than or equal Dh cc SGT Zv NG V 0 Signed greater than Ah cc NET ZvE 20 Not equal AND not end of table
114. internal RAM space does NOT cause additional state times However reading an indirectly addressed internal RAM operand will extend the processing time by 1 state time if the preceding instruction auto increments or auto decrements a GPR as shown in the following example In MOV R1 RO auto increment RO Ina MOV R2 if R2 points into the internal RAM space Tladd 1 State In this case the additional time can be avoided by putting another suitable instruction before the instruction 4 4 indirectly reading the internal RAM 15 197 Standard Instruction Set PROGRAMMING MANUAL Internal SFR operand reads 0 1 State or 2 States SFR read accesses do NOT usually require additional processing time In some rare cases however either one or two additional state times will be caused by particular SFR operations Reading an SFR immediately after an instruction which writes to the internal SFR space as shown in the following example n MOV TO 10008 write to Timer O0 In 1 ADD R3 Ti read from Timer 1 1 State Reading the PSW register immediately after an instruction which implicitly updates the flags as shown in the following example In ADD RO 1000h implicit modification of PSW flags nel BAND Qa read from PSW 2 States Implicitly incrementing or decrementing the SP register immediately after an instruction which explicitly writ
115. inues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is cleared allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JBC instruction If the specified bit was clear the instruction following the JBC instruction is executed E 2 0 0 0 Always cleared Z Contains logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Mnemonic Format Bytes JBC bitaddrg rel AA QQ rr q0 4 PROGRAMMING MANUAL JMPA JMPA Syntax Operation Description Condition Codes Flags Addressing Modes Absolute Conditional Jump JMPA 1 op2 IF op1 1 THEN IP lt op2 ELSE Next Instruction END IF If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed normally See Condition code Table 24 on page 48 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JMPA caddr EA c0 MM
116. ion See condition code Table 24 on page 48 E 2 V C N E Not affected 2 Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JMPR CC rel cD rr 2 101 197 PROGRAMMING MANUAL JMPS Syntax Operation Description Flags Addressing Modes 102 197 Absolute Inter Segment Jump JMPS 1 op2 CSP lt 1 IP lt op2 Branches unconditionally to the absolute address specified by op2 within the segment specified by op1 E Z V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes JMPS seg caddr FA ss MM MM 4 PROGRAMMING MANUAL JNB JNB Syntax Operation Data Types Description Flags Addressing Modes Relative Jump if Bit Clear JNB 1 op2 IF op1 0 THEN IP lt IP sign_extend op2 ELSE Next Instruction END IF BIT If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNB instruction If the specified bit is set the instruction following the JNB instruction is executed
117. ister remains unchanged The MS bit of the MCW register does not affect the result This instruction is repeatable with indirect addressing modes N 2 SV E SL 0 Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Cleared always SV Not affected E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC register is changed Not affected otherwise Mnemonic Rep Format Bytes CoMAX RWm No A3 nm 3A 00 4 CoMAX Rwm Yes 93 4 CoMAX RWm8 Yes 83 4 Examples CoMAX IDX1 QX0 R11 QR1 ACC lt Max ACC R11 IDX1 R11 lt R11 QR1 IDX1 lt IDX1 QX0 CoMAX R1 R10 ACC lt Max ACC R10 R1 Repeat 23 times CoMAX R5 R6 QRO ACC lt Max ACC R6 R5 R6 lt R6 174 197 5 PROGRAMMING MANUAL CoMIN CoMIN Group Syntax Operation Data Types Result Description MAC Flags Addressing Modes Repeat 23 times CoMIN R5 R6 QRO Compare Instructions CoMIN op1 op2 tmp lt 2 1 ACC lt min ACC tmp DOUBLE WORD 40 bit signed value Compares a signed 40 bit operand against the ACC register content The 40 bit operand results from the concatenation of the two source operands op1 LSW
118. it MUL Rw Rw Signed multiply direct GPR by direct GPR 16 16 bit 10 14 10 11112 14 2 MULU Rw Rw Unsigned multiply direct GPR by direct GPR 10 14 10 11 121 14 2 16 16 bit NEG Rw Negate direct word GPR 21612134612 Rb Negate direct byte GPR 216234612 SUB Rw Rw Subtract direct word GPR from direct GPR 262346 2 SUB Rw Rw Subtract indirect word memory from direct GPR 26234 6 2 SUB Rw Rw Subtract indirect word memory from direct GPR amp 2 6 2 3 46 2 post increment source pointer by 2 SUB Rw datag Subtract immediate word data from direct GPR 2161213141612 SUB reg Subtract immediate word data from direct register 2 8 4 61 81 12 4 SUB reg mem Subtract direct word memory from direct register 21841618112 4 Table 9 Arithmetic instructions Continued ky 25 197 Standard Instruction Set PROGRAMMING MANUAL 3 5 5 Mnemonic Description O lt 2 SS Ella dla SUB mem reg Subtract direct word register from direct memory 21841618112 4 SUBB Rb Rb Subtract direct byte GPR from direct GPR 21612131416 2 SUBB Rb Rw Subtract indirect byte memory from direct GPR 2161213462 SUBB Rb Rw Subtract indirect byte memory from direct GPR amp 2161213462 post increment source pointer by 1 SUBB Rb datag Subtract immediate byte data from direct GPR 2161213141612 SUBB data g Subtra
119. ize the operand op2 so that its most signif icant bit is equal to one If the source operand op2 equals zero a zero is written to operand op1 and the zero flag is set Otherwise the zero flag is cleared Flags Addressing Modes 118 197 E 2 V 0 0 0 0 Always cleared Z Set if the source operand op2 equals zero Cleared otherwise V Always cleared C Always cleared N Always cleared Mnemonic Format Bytes PRIOR Rw RWm 2B 2 PROGRAMMING MANUAL PUSH PUSH Syntax Operation Data Types Description Flags Addressing Modes Push Word on System Stack PUSH op1 tmp lt op1 SP SP 2 SP lt tmp WORD Moves the word specified by operand 1 to the location in the internal system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two E 2 V Set if the value of the pushed word represents the lowest possible negative number Cleared other wise Used to signal the end of a table Z Set if the value of the pushed word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the pushed word is set Cleared otherwise Mnemonic Format Bytes PUSH reg EC RR 2 119 197 PWRDN PROGRAMMING MANUAL PWRDN Syntax Operation Description Flags Addressing Modes 120 197 Enter Power Down Mode PWRDN Enter
120. m execution execution time has no dependence on instruction length except for some special branch situations To evaluate the execution time for the injected target instruction of a cache jump instruction it can be considered as if it was executed from the internal ROM regardless of which memory area the rest of the current program is really fetched from For some of the branch instructions the table below represents both the standard number of state times i e the corresponding branch is taken and additional Timin value in parentheses which refers to the case where either the branch condition is not met or a cache jump is taken Instruction Timin ROM States Timin ROM 20MHz CPU clk CALLI CALLA 4 2 200 100 CALLS CALLR PCALL 4 200 JB JBC JNB JNBS 4 2 200 100 JMPS 4 200 JMPA JMPI JMPR 4 2 200 100 MUL MULU 10 500 DIV DIVL DIVU DIVLU 20 1000 MOVI B Rn Rm amp data g 4 200 RET RETI RETP RETS 4 200 TRAP 4 200 All other instructions 2 100 Table 6 Minimum instruction state times Unit ns Instructions executed from the internal RAM require the same minimum time as they would if they were fetched from the internal ROM plus an instruction length dependent number of state times as follows 14 197 571 PROGRAMMING MANUAL Standard Instruction Set e For 2 byte instructions Timin RAM Timin ROM 4 States For 4 byte instructions Tisi RAM
121. mem reg 35 4 SUBCB mem reg 36 4 SUBC reg datai 37 4 SUBCB reg data 38 2 SUBC Rw or or 39 2 SUBCB Rb Rw or Rb or Rb datag 3A 4 BMOVN bitaddrz z bitaddra 3B 3C 2 ROR Rwp 3D 2 JMPR NE rel or cc_NZ rel 3E 2 BCLR bitaddra Table 21 Instruction set ordered by Hex code Continued 39 197 Standard Instruction Set PROGRAMMING MANUAL Number of Bytes Mnemonic Operand 3F 2 BSET bitaddrg 40 2 CMP RWm 41 2 Rbm 42 4 reg mem 43 4 CMPB reg mem 44 45 46 4 reg data 47 4 CMPB reg datay 48 2 CMP Rw or Rw or 49 2 CMPB Rb Rwj or Rb or Rb datas 4A 4 BMOV bitaddrz z bitaddro 4B 2 DIV Rw 4C 2 SHL 40 2 cc V rel 4E 2 BCLR bitaddro 4 4F 2 BSET bitaddro 4 50 2 XOR RWm 51 2 XORB Rbm 52 4 XOR reg mem 53 4 XORB reg mem 54 4 XOR mem reg 55 4 XORB mem reg 56 4 XOR reg 16 57 4 XORB reg datay 58 2 XOR Rw or Rw or data 59 2 XORB Rwj or Rb or Rb datag 5A 4 BOR bitaddrz z bitaddrg 5B 2 DIVU 5 2 SHL Rwp 5D 2 JMPR cc NV rel 5E 2 BCLR bitaddrg 5 5F 2 BSET bitaddrg 5 Table 21 Instructi
122. memory Table 15 Data movement instructions Continued 5 5 Description 5 5 ale x 9 815 2 CALLA Call absolute subroutine if condition is 4 2 10 8 6 4 8 6 10 8 14 12 4 CALLI cc Rw Call indirect subroutine if condition is met 4 2 8 6 4 2 5 3 6 4 8 6 2 CALLR rel Call relative subroutine 418140516 8 2 CALLS seg Call absolute subroutine in any code seg 4 10 6 8 10 14 4 ment JB bitaddr rel Jump relative if direct bit is set 4 106 8 10 14 4 JBC bitaddr rel Jump relative and clear bit if direct bitis 4 10 6 8 10 14 4 cc Jump absolute if condition is met 4 2 10 8 6 4 8 6 10 8 14 12 4 JMPI Rw Jump indirect if condition is met 4 2 8 6 4 2 5 3 6 4 8 6 2 rel Jump relative if condition is met 4 2 8 6 4 2 5 3 6 4 86 2 JMPS seg caddr Jump absolute to a code segment 4 106 8 10 14 4 JNB bitaddr rel Jump relative if direct bit is not set 4 106 8 10 14 4 Table 16 Jump and Call Instructions 34 197 ky PROGRAMMING MANUAL Standard Instruction Set ET Q uu Mnemonic Description 5 8 1 1 2 JNBS bitaddr rel Jump relative and set bit if direct bitis not 4 10
123. memory to direct GPR and post 2 62 3 46 2 increment source pointer by 2 ADD Rw data Add immediate word data to direct GPR 2161213141612 ADD reg data Add immediate word data to direct register 21841618112 4 ADD reg mem Add direct word memory to direct register 21841618112 4 ADD mem reg Add direct word register to direct memory 21841618112 4 ADDB Rb Rb Add direct byte GPR to direct GPR 216121314 6 2 ADDB Rb Rw Add indirect byte memory to direct GPR 216234612 ADDB Rb Rw Add indirect byte memory to direct GPR and 2 6 2131416 2 crement source pointer by 1 ADDB Rb Add immediate byte data to direct GPR 2161213416 2 ADDB data g Add immediate byte data to direct register 21841618112 4 ADDB reg mem_ Add direct byte memory to direct register 21841618112 4 ADDB mem reg Add direct byte register to direct memory 21841618112 4 ADDC Rw Rw Add direct word GPR to direct GPR with Carry 2161213141612 ADDC Rw Rw Add indirect word memory to direct GPR with Carry 2 6 2 31 41 6 2 ADDC Rw Rw Add indirect word memory to direct GPR with Cary 2 6 2 3 4 6 2 and post increment source pointer by 2 ADDC Rw datag Add immediate word data to direct GPR with Carry 2 6 2 3 4 6 2 ADDC data Add immediate word data to direct register with Carry 2 8 4 6 8 12 4 ADDC reg direct word memory to direct register with 2 8 4 6 8 12 4
124. mp lt op2 op1 ACC lt tmp ACC CoSUB2R op1 op2 tmp lt 2 2 1 ACC lt tmp ACC DOUBLE WORD 40 bit signed value Subtracts a 40 bit operand from the 40 bit Accumulator contents or vice versa when the R option is used and stores the result in the accumulator The 40 bit operand results from the concatenation of the two source operands 1 LSW and 2 MSW which is then sign extended The 2 option indicates that the 40 bit operand is also multiplied by 2 prior to being subtracted added from to the ACC negated ACC When the most significant bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFFFFFF or FF 8000 0000 respectively This instruction is repeatable with indirect addressing modes and allows up to two parallel memory reads N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise 193 197 CoSUB 2 R PROGRAMMING MANUAL SL Set if the contents of the ACC is automatically saturated Not affected otherwise Note The E flag is set when the nine highest bits of the accumulator are not equal The SV flag is set when
125. mum and maximum program execution times which is sufficient for most requirements For an exact determination of the instructions state times the facilities provided by simulators or emulators should be used This section defines measurement units summarizes the minimum standard state times of the 16 bit microcontroller instructions and describes the exceptions from the standard timing 1 2 1 Definition of measurement units The following measurement units are used to define instruction processing times fcpu CPU operating frequency may vary from 1 MHz to 50 MHz State One state time is specified by one CPU clock period Therefore one State is used as the basic time unit because it represents the shortest period of time which has to be considered for instruction timing evaluations i State 1 fopuls for variable 50 ns for 20 MHz 12 197 571 PROGRAMMING MANUAL Standard Instruction Set CPU operating frequency may vary from 1 MHz to 50 MHz ALE Address Latch Enable Cycle Time specifies the time required to perform one external memory access One ALE Cycle Time consists of either two for demultiplexed external bus modes or three for multiplexed external bus modes state times plus a number of state times which is determined by the number of waitstates programmed in the MCTC Memory Cycle Time Control and MTTC Memory Tristate Time Control bit fields of
126. n the specified bitoff range different base addresses are used to generate physical addresses Short bitoff addresses from 00h to 7Fh use 00 FDOOh as a base address therefore they specify the 128 highest internal RAM word locations 00 FDOOh to 00 FDFEh Short bitoff addresses from 80h to EFh use OO FFOOh as a base address to specify the highest internal SFR word locations 00 FFOOh to 00 FFDEh or use 00 F100h as a base address to specify the highest internal ESFR word locations 00 F100h to O0 F1DERh bitoff accesses to the ESFR area require a pre ceding EXT R instruction to switch the base address short bitoff addresses from FOh to FFh only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR Any bit address is specified by a word address within the bit addressable memory space see bitoff and by a bit position bitpos within that word Thus bitaddr requires twelve bits in the instruction format 1 1 2 Long addressing mode Long addressing mode uses one of the four DPP registers to specify a physical 18 bit or 24 bit address Any word or byte data within the entire address space can be accessed in this mode All devices support an override mechanism for the DPP addressing scheme see section 1 1 3 Note 6 197 Word accesses on odd byte addresses are not executed but rather trigger a hardware trap After reset the DPP registe
127. nd and are exclusive as well as and R This instruction might be repeated and allows up to two parallel memory reads 161 197 CoMAC R us PROGRAMMING MANUAL MAC Flags N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry or borrow is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Addressing Modes R9 lt R9 2 IDX1 lt IDX1 2 Repeat MRW times CoMACus R7 lt R3 R7 R7 lt R7 CoMACRus IDX1 R4 lt IDX1 R4 ACC rnd IDX1 IDX1 Mnemonic Rep Format Bytes CoMACus Rwp RWm No nm 90 00 4 CoMACus Rwp RWm No A3 nm A000 4 CoMACus Rwm rnd No A3nm 91 00 4 CoMACRus RWm A3 nm 00 4 CoMACRus Rw Rw rnd nm B100 4 IDX Yes 93 Xm 90 rrrr rqqq 4 IDX Yes 93 Xm 0 4 CoMACus IDX amp RwaG rnd Yes 93 Xm 91 rrrr rqqq 4 CoMACRus IDX amp Rw 8 Yes 93XmBoOrrrr rqqq 4 CoMACRus IDX amp Rw rnd Yes 93 Xm B1 rrrr rqqq 4
128. nd op1 This instruction is repeatable Note that unlike for the other instructions IDX can address the entire memory This instruc tion does not affect the Mac Flags but modify the CPU Flags as any other MOV instruction CPU Flags E 2 V Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise MAC Flags Addressing Modes Examples N 2 SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected SL Not affected Mnemonic Rep Format Bytes CoMOV 0 Yes D3XmOOrrrr rqqq 4 Repeat 24 times CoMOV IDX1 QX0 R11 QR1 IDX1 lt 811 176 197 R11 lt R11 QR1 IDX1 lt IDX1 PROGRAMMING MANUAL CoMUL CoMUL Group Syntax Operation Syntax Operation Syntax Operation Data Types Result Description MAC Flags Signed Multiply amp Optional Round Multiply Multiply Accumulate Instructions CoMUL op1 op2 IF MP 1 THEN ACC lt 1 2 lt lt 1 ELSE ACC lt op1 op2 END IF CoMUL op1 op2 IF MP 1 THEN ACC lt 0p1 2 lt lt 1 ELSE l
129. nded instructions 53 Instruction descriptions 54 MAC Instruction set 139 Addressing modes 139 MAC instruction execution time 140 MAC instruction set summary 141 MAC instruction conventions 144 Operands 144 Operations 144 5 145 PROGRAMMING MANUAL 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 5 3 Data addressing modes 145 Instruction format 145 Flag states 146 Repeated instruction syntax 146 Shift value 147 MAC instruction descriptions 147 Revision History 195 3 197 PROGRAMMING MANUAL Introduction This programming manual details the instruction set for the ST10 family of products The manual is arranged in two sections Section 1 details the standard instruction set and includes all of the basic instructions Section 2 details the extension to the instruction set provided by the MAC The MAC instructions are only available to devices containing the MAC refer to the datasheet for device specific information In the standard instruction set addressing modes inst
130. nemonic Format Bytes ADDC RWm 10 nm 2 ADDC Rw 18 n 10ii 2 ADDC Rw 18 11 2 ADDC datas 18 n 0 2 ADDC 16 RR 4 ADDC reg mem 12 RR MM MM 4 ADDC mem reg 14 RR MM MM 4 57 97 ADDCB PROGRAMMING MANUAL AD DC B Integer Addition with Carry Syntax ADDCB op2 Operation op1 lt op1 op2 C Data Types BYTE Description Performs a 2 s complement binary addition of the source operand specified by op2 the destination operand specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic Flags Addressing Modes 58 197 E 2 V C N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table 2 Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a carry is generated from the most signifi cant bit of the specified data type Cleared other wise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ADDCB Rb Rbm 11 nm 2 ADDCB 19 n 10ii 2 ADDCB 19 11 2 ADDCB datag 19 n O 2 ADDCB reg datay 17 RR
131. now 1 0 AON _ 13H dON 6 97192 mg Tm sanr tpg my x 53H09 Mu x EE umy my 9401550 gAOW LINI 1388 AOW UTIN HHSV E Bun l my m 99 umy my Gg H sig EM Sie z 4 aawo goan taawo yxxxoo itamsia taawo 1 AON oar mvo 3 8 31a o ZdWO ziano umy anr dens x mal FE IBS wan smy 2000 AOW NOMA SAOW gy Waw wu my mg 5 uano DAN 5 xoo ar Emi 0 HO umy 8 8 8 x Mg x x SN PAP HESS baee md HHS 12 mul my PPeLIG PPELIG umy lt aNv gany aNv gany gany gany YHS 12 HOX HOX HOX HOX SHOX HOX umy m x eyepg Mg x EM my WAN 938 NIN Steyep Dau my my Hog IHS Ho wu my umy my ano ad ND SdWO dWO gano AOWS Ald HS X ogns gogns ogns goans oans goans oans gogns o
132. nt binary subtraction of the source operand specified by op2 from the destination operand specified by op1 The result is then stored in op1 E 2 V 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred ie the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SUBB Rb Rbm 21 2 SUBB Rb 29 n 10ii 2 SUBB Rb Rwj 29 n 1lii 2 SUBB Rb datag 29 n 0 2 SUBB reg data46 27 RR 4 SUBB reg mem 23 4 SUBB mem reg 25RRMMMM 4 133 197 SUBC PROGRAMMING MANUAL SU BC Integer Subtraction with Carry Synta SUBC op1 op2 Operation 1 lt op1 op2 Data Types WORD Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic Flags Addressing Modes 134 197 E 2 V 5 5 Set if the value of op2 represents the lowest possible negative
133. ntax depends on the addressing mode All of the available addressing modes are summarized at the end of each single instruction description 1 6 3 Operation The following symbols are used to represent data movement arithmetic or logical operators operator lt opY is MOVED into opX opx opX is ADDED to opx opy opY SUBTRACTED from opx opy opX is MULTIPLIED by Diadic operations opx opy opX is DIVIDED by opY opx opy opX is logically ANDed with opx v opy opX is logically ORed with is logically EXCLUSIVELY ORed with lt gt opX is COMPARED against opx mod opy opX is divided MODULO opY Monadic operator opX tihei is logically COMPLEMENTED Table 22 Instruction operation symbols 46 197 571 PROGRAMMING MANUAL Standard Instruction Set Missing or existing parentheses signifies that the operand specifies an immediate constant value an address or a pointer to an address as follows Specifies the immediate constant value of opX opX Specifies the contents of opX opX Specifies the contents of bit n of opX Specifies the contents of the contents of opX i e is used as pointer to the actual operand The f
134. number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SUBC 30 nm 2 SUBC 38 n 10ii 2 SUBC Rw Rw 38 n 1lii 2 SUBC Rw 38 n 0 2 SUBC reg datay 36 RR 4 SUBC reg mem 32 4 SUBC mem reg 34 4 PROGRAMMING MANUAL SUBCB SUBCB Syntax Operation Data Types Description Flags Addressing Modes Integer Subtraction with Carry SUBCB 2 1 lt 1 op2 C Performs 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic E 2 V 5 5 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the re
135. o signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Addressing Modes Mnemonic Format Bytes NEG 81 2 571 111 197 PROGRAMMING MANUAL N EG B Integer Two s Complement Syntax NEGB 1 Operation op1 lt 0 op1 Data Types BYTE Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 Flags E 2 V 5 Set if the value of op1 represents the lowest Addressing Modes 112 197 possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes NEGB Rb A1 nO 2 PROGRAMMING MANUAL NOP NOP Syntax Operation Description Flags Addressing Modes No Operation NOP No Operation This instruction causes a null operation to be performed A null operation causes no change in
136. oMACMRu IDX amp Rwm8 Yes 93 Xm 38 rrrr rqqq 4 CoMACMRu IDX amp Rwm 8 rnd Yes 93 Xm 39 rrrr rqqq 4 Examples CoMACMu IDX1 QX0 R10 QR1 lt IDX1 R10 rnd R10 lt R10 QR1 IDX1 QX0 lt IDX1 IDX1 lt IDX1 ACC lt IDXO R8 R8 lt R8 IDX0 QX0 IDX0 IDXO lt IDXO ACC lt IDX1 R7 ACC R7 lt R7 IDX1 QX1 lt IDX1 IDX1 lt IDX1 QX1 Repeat 3 times CoMACMu IDXO R8 QR0 Repeat MRW times CoMACMRu IDX1 QX1 R7 QRO ky 169 197 CoMACM R us PROGRAMMING MANUAL CoMACM R us Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description 170 197 Mixed Multiply Accumulate Parallel Data Move amp Optional Round Multiply Multiply Accumulate Instructions CoMACMus 2 tmp lt op1 op2 ACC lt ACC tmp DX amp lt 10 CoMACMus op2 rnd tmp lt op1 op2 lt ACC tmp 00 0000 8000p MAL lt 0 IDX amp lt 10 CoMACMus 2 tmp lt 1 2 ACC lt ACC tmp IDX lt IDX CoMACMRus op
137. ollowing abbreviations are used to describe operands Abbreviation Description Context Pointer register CSP Code Segment Pointer register IP Instruction Pointer MD Multiply Divide register 32 bits wide consists of MDH and MDL MDL MDH Multiply Divide Low and High registers each 16 bit wide PSW Program Status Word register SP System Stack Pointer register SYSCON System Configuration register C Carry flag in the PSW register V Overflow flag in the PSW register SGTDIS Segmentation Disable bit in the SYSCON register count Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation tmp Temporary variable for an intermediate result 0 1 2 Constant values due to the data format of the specified operation Table 23 Operand abbreviations 47 197 Standard Instruction Set PROGRAMMING MANUAL 1 6 4 Data types Specifies the particular data type according to the instruction Basically the following data types are used BIT BYTE WORD DOUBLEWORD Except for those instructions which extend byte data to word data all instructions have only one particular data type Note that the data types mentioned here do not take into account accesses to indirect address pointers or to the system stack which are always performed with word data Moreover no data type is spec
138. on Examples Cases op 1 op2 MAE 2 SV SL MS x 8000 8000 x FF C000 0000 1 0 0 0 7FFF 7FFF 0 00 0001 0 0 0 0 1 00 0000 0 0 0 0 MS x 8001 F456 0 FA2A F456 1 0 0 0 1 FA2Bp 0000 1 0 0 0 183 197 CoMULsu PROGRAMMING MANUAL CoMULsu Mixed Multiply amp Optional Round Group Multiply Multiply Accumulate Instructions Syntax CoMULsu 1 op2 Operation ACC op1 op2 Syntax CoMULsu 1 op2 Operation ACC lt op1 2 Syntax CoMULsu 1 op2 rnd Operation ACC lt op1 op2 00 0000 8000 MAL 0 Data Types DOUBLE WORD Result 32 bit signed value Description Multiply the two 16 bit signed and unsigned source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended then it is optionally either negated or rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register The option is used to negate the specified product while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared rnd
139. on set ordered by Hex code Continued 40 197 ky PROGRAMMING MANUAL Standard Instruction Set Number of Bytes Mnemonic Operand 60 2 AND Rw 61 2 Rbm 62 4 AND reg mem 63 4 ANDB reg mem 64 4 AND mem reg 65 4 ANDB mem reg 66 4 AND reg datay 67 4 ANDB reg datay 68 2 AND Rw or Rwy Rw or 69 2 ANDB Rb Rwj or Rb or Rb datas 6A 4 BAND bitaddrz z bitaddra 6B 2 DIVL Rw 6C 2 SHR RWm 6D 2 JMPR cc_N rel 6E 2 BCLR bitaddrg 6F 2 BSET bitaddrag 70 2 OR RWm 71 2 ORB Rb Rbm 72 4 OR reg mem 73 4 ORB reg mem 74 4 OR mem reg 75 4 ORB mem reg 76 4 OR reg datay 77 4 ORB reg datay 78 2 OR Rwp Rw or Rwy Rw or 79 2 ORB Rb Rwj or Rba or Rb datas 7A 4 BXOR bitaddrz z bitaddro 7B 2 DIVLU 7C 2 SHR Rwp 7D 2 JMPR NN rel 7E 2 BCLR bitaddrg 7 7F 2 BSET bitaddrg 7 80 2 CMPI1 Rwp Table 21 Instruction set ordered by Hex code Continued 41 197 Standard Instruction Set PROGRAMMING MANUAL Number of Bytes Mnemonic Operand 81 2 Rw 82 4 CMPI1 Rw mem 83
140. op1 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the pushed operand is set Cleared otherwise Mnemonic Format Bytes PCALL caddr 4 PROGRAMMING MANUAL POP POP Syntax Operation Data Types Description Flags Addressing Modes Pop Word from System Stack POP op1 tmp SP SP SP 2 op1 lt tmp WORD Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1 The Stack Pointer is then incremented by two E 2 V Set if the value of the popped word represents the lowest possible negative number Cleared other wise Used to signal the end of a table Z Set if the value of the popped word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the popped word is set Cleared otherwise Mnemonic Format Bytes POP reg FC RR 2 117 197 PRIOR PROGRAMMING MANUAL PRIOR Prioritize Register Syntax PRIOR op2 Operation tmp lt op2 count 0 DO WHILE 5 1 AND count 15 AND op2 0 lt tmpn 1 count lt count 1 END WHILE 0p1 count Data Types WORD Description This instruction stores a count value in the word operand specified by op1 indicating the number of single bit shifts required to normal
141. opcodes but by particular bits within the operand field In the individual instruction description the addressing mode is described in terms of mnemonic format and number of bytes Mnemonic gives an example of which operands the instruction will accept Format specifies the format of the instruction as used in the assembler listing Figure 3 shows the reference between the instruction format representation of the assembler and the corresponding internal organization of the instruction format nibble 4 bits The following symbols are used to describe the instruction formats 51 197 Standard Instruction Set PROGRAMMING MANUAL 00 through Instruction Opcodes 0 1 Constant Values Pee Each of the 4 characters immediately following a colon represents a single bit ii 2 bit short GPR address 5 8 bit code segment number seg nGHE 2 bit immediate constant 3 bit immediate constant 4 bit condition code specification n 4 bit short GPR address Rw Rb m 4 bit short GPR address Rw or Rbm q 4 bit position of the source bit within the word specified by QQ 2 4 bit position of the destination bit within the word specified by ZZ 4 bit immediate constant data QQ 8 bit word address of the source bit bitoff rr 8 bit relative target address word offset rel RR 8 bit word address re
142. operation Byte operation datag 0000 datag 00 datag data 0000 data 00 data datag 0000 datag datag 46 data4g FF mask 0000 mask mask Table 4 Table of constants Note Immediate constants are always signified by a leading number sign 10 197 PROGRAMMING MANUAL Standard Instruction Set 1 1 6 Branch target addressing modes Jump and Call instructions use different addressing modes to specify the target address and segment Relative absolute and indirect modes can be used to update the Instruction Pointer register IP while the Code Segment Pointer register CSP can only be updated with an absolute value A special mode is provided to address the interrupt and trap jump vector table situated in the lowest portion of code segment 0 Mnemo Target Address Target Segment Valid Address Range caddr IP caddr caddr 0000h FFFER rel IP IP 2 rel rel 00h 7Fh Rw IP 1 2 rel t rel 80h FFh IP 2 Rw Rw 0 15 seg CSP seg seg 0 255 trap7 IP 00001 4 trapz CSP 0000h trapz 00h 7Fh caddr rel Rw seg trap7 Table 5 Branch target address summary Specifies an absolute 16 bit code address within the current segment Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of
143. ower part of the ACC register MAL is cleared When the MS bit of the MCW register is set and when a 32 bit overflow or underflow occurs the obtained result becomes 00 7FFF FFFF or FF 8000 0000 respectively This instruction is not repeatable N 2 SV E SL N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise C Set if a carry is generated Cleared otherwise SV Set if an arithmetic overflow occurred Not affected other wise E Set if the MAE is used Cleared otherwise SL Set if the contents of the ACC is automatically saturated Not affected otherwise Mnemonic Rep Format Bytes CoRND No A300B200 4 CoRND is equivalent to COASHR 0 rnd CoRND lt rnd PROGRAMMING MANUAL CoSHL CoSHL Group Syntax Operation Data types Result Description MAC Flags Accumulator Logical Shift Left Shift Instructions CoSHL op1 count lt op1 C lt 0 DO WHILE count 0 C lt ACC lt 1 n 1 39 lt 0 count lt count 1 END WHILE ACCUMULATOR 40 bit signed value Shifts the ACC register left by the number of times specified by the operand op1 The least significant bits of the result are filled with zeros Only shift values from 0 to 8 inclusive are allowed op1 can be either a 5 bit unsigned immediate data or the
144. peration Description Data Types Flags Addressing Modes Switch Context SCXT 1 op2 tmp1 lt op1 tmp2 lt Si SP lt SP SP lt 007 0 1 lt tmp2 Used to switch contexts for any register Switching context is push and load operation The contents of the register specified by the first operand 1 are pushed onto the stack That register is then loaded with the value specified by the second operand 2 WORD E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes SCXT reg datay C6 RR 4 SCXT reg mem D6 RRMMMM 4 127 197 SHL PROGRAMMING MANUAL SHL Shift Left Syntax SHL 1 op2 Operation count lt op2 C lt 0 DO WHILE count z 0 lt 0 1 5 opin lt Coty 1 n 1 15 opo lt une ake 1 END WHILE Data Types WORD Description Shifts the destination word operand op1 left by as many times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The most significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Addressing Modes 128 197 E 2 V 0 0 5 Always cleared Set if result equals zero Cleared otherwise Always cleare
145. r rqqq 4 CoMAC Rw Yes 83 EO 4 CoMAC Rw rnd Yes 83 1 4 CoMACR Rwy Rwm8 Yes 83nmFOrrrr rqqq 4 CoMACR Rwy rnd Yes 83 1 4 lt R3 R4 rnd lt ACC R2 R6 R6 lt R6 2 IDXO R11 R11 lt R11 IDXO IDXO QX0 R9 lt R9 QR1 IDX1 lt IDX1 QX1 lt ACC R3 R7 R7 lt R7 IDX1 R4 ACC rnd R4 lt R4 2 PROGRAMMING MANUAL CoMAC R u CoMAC R u Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description MAC Flags iy Unsigned Multiply Accumulate amp Optional Round Multiply Multiply Accumulate Instructions CoMACu op1 op2 tmp lt op1 op2 ACC lt tmp op1 op2 rnd tmp lt op1 op2 ACC lt tmp 00 0000 8000 MAL lt 0 CoMACu op1 op2 tmp lt op1 op2 ACC lt ACC tmp CoMACRu op1 op2 tmp op1 op2 lt tmp ACC CoMACRu op1 op2 rnd tmp lt op1 op2 ACC lt tmp ACC 00 0000 8000 MAL lt 0 DOUBLE WORD 40 bit signed value Multiplies the two unsigned 16 bit source oper
146. ranted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS B AERONAUTIC APPLICATIONS C AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS AND OR D AEROSPACE APPLICATIONS OR ENVIRONMENTS WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE UNLESS PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS PRODUCTS FO
147. re updated accordingly E 2 V Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Mnemonic Format Bytes MOVB Rb Rbm F1 nm 2 MOVB data E1 n 2 MOVB reg dataig E7 RR 4 MOVB Rb A9 nm 2 MOVB Rb Rwm 99 nm 2 MOVB Rw Rb B9 nm 2 MOVB Rwm Rb 89 nm 2 MOVB Rwa C9 2 MOVB Rw RW 09 2 MOVB Rwy Rwm E9 nm 2 MOVB Rw data F4 nm 4 MOVB Rwm data 6 Rb E4 nm 4 MOVB Rw mem A4 MM MM 4 MOVB mem Rw B4 0n MM 4 MOVB reg mem F3RRMMMM 4 MOVB mem reg 7 4 PROGRAMMING MANUAL MOVBS MOVBS Syntax Operation Data Types Description Flags Addressing Modes Move Byte Sign Extend MOVBS 1 2 low byte op1 lt IF op27 1 THEN high byte op1 lt FF ELSE high byte op1 lt 00 END IF WORD BYTE Moves and sign extends the contents of the source byte specified by op2 to the word location specified by the destina tion operand op1 The contents of the moved data is examined and the flags are updated accordingly E 2 V 0
148. rect GPR 2 2 2 Table 11 Boolean bit map instructions ky 29 197 Standard Instruction Set PROGRAMMING MANUAL m lt Mnemonic Description 25 3 E E CMP Rw Rw Compare indirect word memory to direct GPR and 2 6 2 3 4 6 2 post increment source pointer by 2 CMP Rw datag Compare immediate word data to direct GPR 21623462 reg 5 Compare immediate word data to direct register 218 4 6 8 1214 CMP reg Compare direct word memory to direct register 218 4 6 8 1214 CMPB Rb Rb Compare direct byte GPR to direct GPR 21623462 CMPB Rb Rw Compare indirect byte memory to direct GPR 2623462 CMPB Rb Rw Compare indirect byte memory to direct GPR and 2 6 2 3 4 6 2 post increment source pointer by 1 CMPB Rb datag Compare immediate byte data to direct GPR 21623462 CMPB data g Compare immediate byte data to direct register 2 12 4 CMPB reg mem Compare direct byte memory to direct register 2 12 4 Table 11 Boolean bit map instructions Continued 58 Description amp c 5 5 8 E d CMPD1 Rw data Compare immediate word data to direct GPR and 2 6 2 3 4 6 2 decrement GPR by 1 CMPD1 Rw data g Compare immediate word data to direct GPR and 2 8 4 6 8 1214 decrement GPR by 1 CMPD1 Rw mem Compare direct word memory
149. red by functional group The minimum number of state times required for instruction execution are given for the following configurations internal ROM internal RAM external memory with a 16 bit demultiplexed and multiplexed bus or an 8 bit demultiplexed and multiplexed bus These state time figures do not take into account possible wait states on external busses or possible additional state times induced by operand fetches The following notes apply to this summary Data addressing modes Rw Word GPR RO R1 R15 Rb Byte GPR RLO RHO RL7 RH7 reg SFR or GPR in case of a byte operation on an SFR only the low byte can be accessed via reg mem Direct word or byte memory location Indirect word or byte memory location Any word GPR be used as indirect address pointer except for the arithmetic logical and compare instructions where only RO to R3 are allowed bitaddr Direct bit in the bit addressable memory area bitoff Direct word in the bit addressable memory area data Immediate constant the number of significant bits that can be user specified is given by the appendix x maskg Immediate 8 bit mask used for bit field modifications Multiply and divide operations The MDL and MDH registers are implicit source and or destination operands of the multiply and divide instructions 5 21 197 Standard Instruction Set PROGRAMMING MANUAL Branch target addressing modes ca
150. ription Performs an extended unsigned 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH Flags Addressing Modes 88 197 E 2 V 0 Y S 0 Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes Rw 7B nn 2 PROGRAMMING MANUAL DIVU DIVU Syntax Operation Data Types Description Flags Addressing Modes 16 by 16 Unsigned Division DIVU op1 MDL lt MDL 1 lt MDL mod op1 WORD Performs an unsigned 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH E 2 V 0 5 5 0 2 E Always cleared Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in
151. rr rqqq 4 CoMACMsu _ IDX Rwm8 Yes 93 Xm 68 rrrr rqqq 4 CoMACMsu IDX amp Rw 8 rnd Yes 93 Xm 59 rrrr rqqq 4 CoMACMRsu IDX amp Yes 93 Xm 78 rrrr rqqq 4 CoMACMRsu IDX amp Rwm rnd Yes 93 Xm 79 rrrr rqqq 4 Example CoMACMsu IDX1 QX0 R10 QR1 rnd ACC ACC IDX1 R10 rnd R10 lt R10 QR1 IDX1 QX0 lt IDX1 IDX1 lt IDX1 Repeat 3 times CoMACMsu IDXO R8 QRO rnd ACC lt ACC IDXO R8 R8 lt R8 IDXO QX0 lt IDX0 IDXO lt IDXO Repeat times CoMACMRsu IDX1 QX1 R7 rnd ACC lt IDX1 R7 ACC rnd R7 lt R7 QRO IDX1 QX1 lt IDX1 IDX1 lt IDX1 QX1 ky 173 197 PROGRAMMING MANUAL CoMAX Group Syntax Operation Data Types Result Description MAC Flags Addressing Modes Maximum Compare Instructions CoMAX op1 op2 tmp lt op2 op1 ACC lt max ACC tmp DOUBLE WORD 40 bit signed value Compares a signed 40 bit operand against the ACC register content The 40 bit operand results from the concatenation of the two source operands op1 LSW and op2 MSW which is then sign extended If the contents of the ACC register is smaller than the 40 bit operand then the ACC register is loaded with it Otherwise the ACC reg
152. rs are initialized so that all long addresses are directly mapped onto the identical physical addresses within segment 0 PROGRAMMING MANUAL Standard Instruction Set Long addresses 16 bit are treated in two parts Bits 13 0 specify a 14 bit data page offset and bits 15 14 specify the Data Page Pointer 1 of 4 The DPP is used to generate the physical 24 bit address see figure below selects Data Page Pointer 16 bit Long Address DPPO DPP1 DPP2 DPP3 9 23 15 14 13 y 0 14 bit page offset 1413 0 24 bit Physical Address Figure 1 Interpretation of a 16 bit long address All ST10 devices support an address space of up to 16 MByte so only the lower ten bits of the selected DPP register content are concatenated with the 14 bit data page offset to build the physical address The long addressing mode is referred to by the mnemonic mem Mnemo Physical Address Long Address Range Scope of Access mem mem43FFFh 0000h 3FFFh Any Word or Byte DPP1 mem43FFFh 4000h 7FFFh DPP2 mem43FFFh 8000h BFFFh DPP3 mem43FFFh Coo0h FFFFh mem pag mem43FFFh 0000h FFFFh 14 bit Any Word or Byte mem seg mem 0000h FFFFh 16 bit Any Word or Byte Table 2 Summary of long address modes 7 197 Standard Instruction Set PROGRAMMING MANUAL 1 1 3 DPP override mechanism
153. ruction execution times minimum state times and the causes of additional state times are defined Cross reference tables of instruction mnemonics hexadecimal opcode address modes and number of bytes are provided for the optimization of instruction sequences Instruction set tables ordered by functional group can be used to identify the best instruction for a given application Instruction set tables ordered by hexadecimal opcode can be used to identify specific instructions when reading executable code i e during the de bugging phase Finally each instruction is described individually on a page of standard format using the conventions defined in this manual For ease of use the instructions are listed alphabetically The MAC instruction set is divided into its 5 functional groups Multiply and Multiply Accumulate 32 Bit Arithmetic Shift Compare and Transfer Instructions Two new addressing modes supply the MAC with up to 2 new operands per instruction Cross reference tables of MAC instruction mnemonics by address mode and MAC instruction mnemonic by functional code can be used for quick reference As for the standard instruction set each instruction has been described individually in a standard format according to defined conventions For convenience the instructions are described in alphabetical order 4 197 6571 PROGRAMMING MANUAL Standard Instruction Set 1 Standard Instruction Set 1 1 Addressing modes 1 1 1 Short adres
154. s CoNEG No 00 3200 4 CoNEG rnd No A3007200 4 CoNEG ACC lt 0 ACC CoNEG lt 0 ACC rnd Instr MS rnd ACC before ACC after N 2 SV CoNEG No 00 1234 5678 FF EDCB A988 0 0 CoNEG Yes 00 1234 5678 FF EDCC 0000 1 1 0 0 186 197 PROGRAMMING MANUAL CoNOP CoNOP Group Syntax Operation Description MAC Flags Addressing Modes Example No Operation 40 bit Arithmetic Instructions CoNOP No Operation Modifies the address pointers without changing the internal MAC Unit registers N Z C SV E SL N Not affected Z Not affected C Not affected SV Not affected E Not affected SL Not affected Mnemonic Rep Format Bytes CoNOP Yes 93 1m rrrr rqqq 4 CoNOP _ IDX Yes 93 rrrr rqqq 4 CoNOP IDX0 QX1 R11 QR1 R11 lt R11 QR1 IDXO IDXO QX1 187 197 CoRND PROGRAMMING MANUAL CoRND Group Syntax Operation Data Types Result Description MAC Flags Addressing Modes Notes Example 188 197 Round Accumulator Shift Instructions CoRND ACC lt ACC 00 0000 8000 MAL lt 0 ACCUMULATOR 40 bit signed value Rounds the ACC register contents by adding 0000 8000h to it and store the result in the ACC register and the l
155. sible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ANDB Rb Rbm 61 nm 2 ANDB Rb 69 n 10ii 2 ANDB Rb Rw 69 n 11ii 2 ANDB Rb datag 69 0 2 ANDB reg dataig 67 RR 4 ANDB reg mem 63 RR MM MM 4 ANDB mem reg 65 RR MM MM 4 PROGRAMMING MANUAL ASHR ASHR Syntax Operation Data Types Description Flags Addressing Modes Arithmetic Shift Right ASHR 1 op2 lt 0 lt 0 DO WHILE count lt me vv ROR 10 Opty lt op15 1 N 0 14 count lt count 1 END WHILE WORD count lt op2 V C V Arithmetically shifts the destination word operand op1 right by as many times as specified in the source operand op2 To preserve the sign of the original operand op1 the most signif icant bits of the result are filled with zeros if the original most significant bit was 0 or with ones if the original most signifi cant bit was a 1 The Overflow flag is used as a Rounding flag The least significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used E 2 V 0 j S S E Always cleared 2 Se
156. sing modes The ST10 family of devices use several powerful addressing modes for access to word byte and bit data This section describes short long and indirect address modes constants and branch target addressing modes Short addressing modes use an implicit base offset address to specify the 24 bit physical address Short addressing modes give access to the GPR SFR or bit addressable memory space PhysicalAddress BaseAddress A x ShortAddress Note A 1 for byte GPRs A 2 for word GPRs Mnemo Physical Address Short Address Range Scope of Access Rw CP 2 Rw Rw 0 15 GPRs Word 16 values Rb CP 1 Rb Rb 0 15 GPRs Byte 16 values reg OO FEO0h 2 reg reg 00h EFh SFRs Word Low byte OO F000h 2 reg reg 00h EFh ESFRs Word Low byte CP 2 reg OFh FOh FFh GPRs Word 16 values CP 1 reg OFh FOh FFh GPRs Bytes 16 values bitoff OO FDOOh 2 bitoff bitoff 00h 7Fh Bit word offset 128 values OO FFOOh 2 bitoff FFh bitoff 80h EFh SFR Bit word offset 128 values CP 2 bitoff OFh bitoff FOh FFh GPR Bit word offset 16 values bitaddr Word offset as with bitoff bitoff 00h FFh single bit Immediate bit position bitpos 0 15 Table 1 Short addressing mode summary 5 197 Standard Instruction Set PROGRAMMING MANUAL Rw Rb reg bitoff bitaddr Specifies direct access to any GPR
157. st most significant bit shifted out of op1 Cleared for a rotate count of zero N Set if the most significant bit of the result is set Cleared otherwise lt Mnemonic Format Bytes ROL RWm 0C nm 2 ROL Rw data 1C n 2 125 197 PROGRAMMING MANUAL ROR Rotate Right Syntax ROR op1 op2 Operation count lt op2 lt 0 V lt 0 DO WHILE count V lt ae v C C lt opo 0 1 lt op15 4 n O 14 0p145 lt C count lt count 1 END WHILE Data Types WORD Description Rotates the destination word operand op1 right by as many times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used Flags Addressing Modes 126 197 E 2 V 0 Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the rotate operation a 1 is shifted out of the carry flag Cleared for a rotate count of zero C The carry flag is set according to the last least significant bit shifted out of 1 Cleared for a rotate count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ROR RWm 2C nm 2 ROR Rw data 2 PROGRAMMING MANUAL SCXT SCXT Syntax O
158. su CoMACsu Repeat 3 times Repeat MRW times CoMACRsu 164 197 Mnemonic Rep Format Bytes CoMACsu Rwy No A3nm 5000 4 CoMACsu Rwy No A3nm 6000 4 CoMACsu RW rnd No A3nm 51 00 4 CoMACRsu Rw Rwm No A3nm 70 00 4 CoMACRsu Rw rnd No 71 00 4 CoMACsu IDX amp Rwm Yes 93 Xm 50 rrrr rqqq 4 IDX amp Rwm Yes 93 60 rrrr rqqq 4 CoMACsu IDX amp Rwm rnd Yes 93 Xm 51 rrrr rqqq 4 CoMACRsu IDX amp Rw Yes 93 Xm 70 rrrr rqqq 4 CoMACRsu IDX amp Rw rnd Yes 93 Xm 71 rrrrirqqq 4 CoMACsu Rw RW 2 Yes 83 50 4 CoMACsu Rwy Yes 83 60 4 CoMACsu Rw rnd Yes 83 51 4 CoMACRsu Rw Rw Yes 83 70rrrr rqqq 4 CoMACRsu Rwy RWm8 rnd Yes 83 71 rrrrirqqq 4 R5 R8 rnd ACC lt ACC R5 R8 rnd R2 R7 ACC lt ACC R2 R7 R11 lt ACC IDXO R11 R11 lt R11 QRO IDXO lt IDXO CoMACsu IDX14 R9 lt ACC IDX1 R9 R9 lt R9 2 IDX1 lt IDX1 2 CoMACsu R7 ACC lt R3 R7 R7 lt R7 QRO IDX1 R4 rnd lt IDX1 R4 IDX1 lt IDX1 QX0 PROGRAMMING MANUAL CoMACM R CoMACM R Group
159. sult cannot be represented in the specified data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes SUBCB Rb Rb 31 nm 2 SUBCB Rb 39 10 2 SUBCB Rb Rw 39 n 11ii 2 SUBCB Rb data 39 n 0 2 SUBCB datayg 37 RR 4 SUBCB reg mem 33 MM MM 4 SUBCB reg 35 4 135 197 PROGRAMMING MANUAL TRAP Syntax Operation Description Flags Addressing Modes 136 197 Software Trap TRAP 1 SP lt SP 2 SP lt PSW IF SYSCON SGTDIS 0 THEN SP lt SP 2 SP lt CSP CSP lt 0 END IF SP lt SP 2 SP lt IP IP lt zero_extend 0p1 4 Invokes a trap or interrupt routine based on the specified operand 1 The invoked routine is determined by branching to the specified vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI return from interrupt instruction is used to resume execution after the trap or interrupt routine has completed The CSP is pushed if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register E 2 V Not
160. t op1 op2 END IF CoMUL 1 op2 rnd IF MP 1 THEN ACC lt 1 2 lt lt 1 00 0000 8000 ELSE ACC lt op1 2 00 0000 80004 END IF MAL lt 0 DOUBLE WORD 32 bit signed value Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended then and on condition MP is set it is one bit left shifted and finally it is optionally either negated or rounded before being stored in the 40 bit ACC register The option is used to negate the specified product while the rnd option is used to round the product using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared rnd and are exclusive This non repeatable instruction allows up to two parallel memory reads N 2 SV E SL 0 Set if the most significant bit of the result is set Cleared otherwise Z Set if the result equals zero Cleared otherwise 177 197 CoMUL PROGRAMMING MANUAL Addressing Modes Examples CoMUL RO R1 rnd CoMUL R2 R6 CoMUL IDX0 QX1 R114 CoMUL IDX1 R15 QRO CoMUL 178 197 C Always cleared SV Not affected E Always cleared when MP is cleared otherwise only set in case of 8000 by 8000 multiplica
161. t IDX1 IDX1 lt IDX1 QX1 5 171 197 CoMACM R su PROGRAMMING MANUAL CoMACM R su Group Syntax Operation Syntax Operation Syntax Operation Syntax Operation Syntax Operation Data Types Result Description 17297 Mix Multiply Accumulate Parallel Data Move amp Optional Round Multiply Multiply Accumulate Instructions CoMACMsu op2 tmp lt 0 1 0 2 lt ACC tmp IDX lt 10 CoMACMsu op2 rnd tmp lt op1 op2 lt ACC tmp 00 0000 8000p MAL lt 0 IDX amp lt 10 CoMACMsu op2 tmp lt 0 1 0 2 ACC lt ACC tmp IDX lt IDX CoMACMRsu 1 op2 tmp lt 0p1 op2 ACC lt tmp ACC IDX lt IDXj CoMACMHsu op2 rnd tmp lt op1 op2 ACC lt tmp ACC 00 0000 8000 MAL lt 0 IDX amp lt 10 P P jo DOUBLE WORD 40 bit signed value Multiplies the two signed 16 bit source operands op1 and op2 The obtained signed 32 bit product is first sign extended it is then option ally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register option is used to negate the specifie
162. t is examined and the flags are updated accordingly Flags E 2 V 0 0 0 Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always cleared N Contains the previous state of the source bit Addressing Modes Mnemonic Format Bytes BMOV bitaddrz 7 bitaddrg q 4A QQ ZZ 42 4 68 197 PROGRAMMING MANUAL BMOVN BMOVN Bit to Bit Move amp Negate Syntax BMOVN op2 Operation 1 2 Data Types BIT Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly Flags E 2 0 0 0 Always cleared Z Contains the logical negation of the previous state of the source bit V Always cleared C Always cleared N Contains the previous state of the source bit Addressing Modes Mnemonic Format Bytes BMOVN bitaddrz bitaddrgg 3AQQZZqz 4 571 69 197 PROGRAMMING MANUAL BOR Bit Logical OR Syntax BOR 1 op2 Operation op1 lt op1 v op2 Data Types BIT Description Performs a single bit logical OR of the source bit specified by operand op2 with the destination bit specified by operand op1 The ORed result is then stored op1 Flags Addressing Modes 70 197 2 V OR AND XOR E Always cleared Z
163. t if result equals zero Cleared otherwise V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared for a shift count of zero C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes ASHR Rwy RWm AC nm 2 ASHR Rw BC n 2 61 197 PROGRAMMING MANUAL ATOMIC Syntax Operation Description Note Flags Addressing Modes 62 197 Begin ATOMIC Sequence ATOMIC 1 count lt op1 1 op1 lt 4 Disable interrupts and Class A traps DO WHILE count 0 AND Class B trap condition z TRUE Next Instruction count count 1 END WHILE count 0 Enable interrupts and traps Causes standard and PEC interrupts and class A hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active so that no additional NOPs are required Depending on the value of op1 the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC instruction The ATOMIC instruction must be used
164. t if the word result equals zero Cleared other wise V Always cleared C Always cleared N Set if the most significant bit of the word result is set Cleared otherwise Mnemonic Format Bytes BFLDH bitoffg maskg datag 1A QQ 4 PROGRAMMING MANUAL BFLDL BFLDL Syntax Operation Data Types Description Note Flags Addressing Modes Bit Field Low Byte BFLDL 1 op2 op3 tmp lt op1 low byte tmp lt low byte tmp 2 v op3 op1 tmp WORD Replaces those bits in the low byte of the destination word operand op1 which are selected by an 1 in the AND mask op2 with the bits at the corresponding positions in the OR mask specified by op3 Bits which are masked off by a 0 in the AND mask op2 may be unintentionally altered if the corresponding bit in the OR mask contains 1 E 2 V 0 0 0 Always cleared Z Set if the word result equals zero Cleared other wise V Always cleared C Always cleared N Set if the most significant bit of the word result is set Cleared otherwise Mnemonic Format Bytes BFLDL bitoffg maskg datag 0AQQ 4 67 197 BMOV PROGRAMMING MANUAL BMOV Bit to Bit Move Syntax BMOV 01 op2 Operation op1 lt op2 Data Types BIT Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bi
165. tandard Instruction Set ae Number of Bytes Mnemonic Operand E6 4 MOV reg data E7 4 MOVB reg datay E8 2 MOV Rwm 2 MOVB Rwm EA 4 JMPA cc caddr EB 2 RETP reg EC 2 PUSH reg ED 2 JMPR cc_UGT rel EE 2 BCLR bitaddrg 14 EF 2 BSET bitaddrg 14 FO 2 MOV RWm F1 2 MOVB Rb Rbm F2 4 MOV reg mem F3 4 MOVB reg mem F4 4 MOVB Rb Rw data F5 F6 4 MOV mem reg F7 4 MOVB mem reg F8 a F9 gt FA 4 JMPS seg caddr FB 2 RETI FC 2 POP reg FD 2 JMPR cc_ULE rel FE 2 BCLR bitaddrg 15 FF 2 BSET bitaddra 15 Table 21 Instruction set ordered by Hex code Continued 1 This instruction only applies to products including the MAC 1 6 Instruction conventions This section details the conventions used in the individual instruction descriptions Each individual instruction description is described in a standard format in separate sections under the following headings 45 197 Standard Instruction Set PROGRAMMING MANUAL 1 6 1 Instruction name Specifies the mnemonic opcode of the instruction 1 6 2 Syntax Specifies the mnemonic opcode and the required formal operands of the instruction Instructions can have either none one two or three operands which are separated from each other by commas MNEMONIC op2 op3 The operand sy
166. tax Operation Data Types Result Description Mixed Multiply Accumulate amp Optional Round Multiply Multiply Accumulate Instructions CoMACus op1 op2 tmp lt op1 op2 ACC lt tmp CoMACus op1 op2 rnd tmp lt op1 op2 ACC lt tmp 00 0000 8000 MAL lt 0 CoMACus op1 op2 tmp lt op1 op2 lt ACC tmp CoMACRus 2 tmp lt op1 op2 lt tmp ACC CoMACRus 2 rnd tmp lt op1 op2 ACC lt tmp ACC 00 0000 8000 MAL lt 0 DOUBLE WORD 40 bit signed value Multiplies the two unsigned and signed 16 bit source operands op1 and op2 respectively The obtained signed 32 bit product is first sign extended and then it is optionally negated prior being added subtracted to from the 40 bit ACC register content finally the obtained result is optionally rounded before being stored in the 40 bit ACC register The result is never affected by the MP mode flag contained in the MCW register option is used to negate the specified product option is used to negate the accumulator content and finally rnd option is used to round the result using two s complement rounding The default sign option is and the default round option is no round When rnd option is used MAL register is automatically cleared Note that r
167. tes to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC and EXTended instructions CAUTION When a Class B trap interrupts an ATOMIC or EXTended sequence this sequence is terminated the interrupt lock is removed and the standard condition is restored before the trap routine is executed The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions CAUTION When using the ATOMIC and EXTended instructions with other system control or branch instructions CAUTION When using nested ATOMIC and EXTended instructions There is ONE counter to control the length of this sort of sequence i e issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with value of the new instruction 571 53 197 Standard Instruction Set PROGRAMMING MANUAL 1 8 Instruction descriptions This section contains a detailed description of each instruction listed in alphabetical order 54 197 ky PROGRAMMING MANUAL ADD ADD Syntax Operation Data Types Description Flags Addressing Modes Integer Addition ADD 1 op2 op1 lt op1 op2 WORD Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The sum is then stored in op1 E 2 V
168. the PSW register as shown in the following example I BSET USRO implicit modification of PSW flags n I JMPR 2 label test condition flag in PSW 1 State 1 1 In this case the extra state time can be intercepted by putting another suitable instruction before the conditional branch instruction 1 3 Instruction set summary The following table lists the instruction mnemonic by hex code with operand Table 7 Instruction mnemonic by hex code with operand 5 17 197 PROGRAMMING MANUAL Standard Instruction Set N e o lt a o Qiu 24 gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt gt lt Peepy my W3W 93H umyToippmy NIN 93S dOd 15 AON GAOW AOW SAOWN SAOW AOW S8 OW Sanr Bs fal Veyepg Mg uaavo oau 9 pprumy my muy my yaava 22 934 d AOW Tvod on AON SAOW vanr dia HSnd BPE SEAOW my eva oas hei 5 ese AON osu wan XOS 9 91 9 aow gaon STivo uaixa 9 ps m Ymy Tu uaavo 99 5 zaAOW _za
169. the SYSCON BUSCONx registers For demultiplexed external bus modes 1 2 15 MCTC 1 MTTC States 100 900 ns for 20 MHz For multiplexed external bus modes 1 3 15 MCTC 1 MTTC States 150 ns 950 ns for 20 MHz The total time Trot taken to process a particular part of a program can be calculated by the sum of the single instruction processing times Tjj of the considered instructions plus an offset value of 6 state times which takes into account the solitary filling of the pipeline Ttot Tin 6 States The time Tin taken to process a single instruction consists of a minimum number Timin plus an additional number of instruction state times and or ALE Cycle Times Tin 13 197 Standard Instruction Set PROGRAMMING MANUAL 1 2 2 Minimum state times The table below shows the minimum number of state times required to process an instruction fetched from the internal ROM Timin ROM This table can also be used to calculate the minimum number of state times for instructions fetched from the internal RAM Timin RAM or ALE Cycle Times for instructions fetched from the external memory Timin ext Most of the 16 bit microcontroller instructions except some branch multiplication division and a special move instructions require a minimum of two state times For internal ROM progra
170. the status of the flags E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes NOP CC 00 2 113 197 OR PROGRAMMING MANUAL OR Logical OR Syntax OR 1 op2 Operation op1 lt op1 v op2 Data Types WORD Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 Flags Addressing Modes 114 197 E 2 V 0 0 Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Mnemonic Format Bytes OR Rwy RWm 70 2 OR Rw Rwj 78 n 10ii 2 OR Rw 78 n 1lii 2 Rw datag 78 2 OR reg datay 76 RR 4 OR reg mem 72 4 OR mem reg 74 4 PROGRAMMING MANUAL ORB ORB Syntax Operation Data Types Description Flags Addressing Modes Logical OR ORB op1 op2 op1 lt op1 v op2 BYTE Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 E 2 V 0
171. tion SL Not affected when MP or MS are cleared otherwise only set in case of 8000 by 8000 multiplication Mnemonic Rep Format Bytes CoMUL RWm No 00 4 CoMUL Rwp RWm No nm 8 00 4 CoMUL Rw rnd No A3nm 1 00 4 CoMUL J IDX amp No 93 0 0qqq 4 CoMUL IDX amp 8 No 93 Xm C8 0 0qqq 4 CoMUL IDX amp Rwm8 93 Xm C1 0 0qqq 4 CoMUL 83nm 0 0qqq 4 CoMUL Rw No 83nm C8 0 0qqq 4 CoMUL Rw rnd 83nm C1 0 0qqq 4 ACC lt RO R1 rnd ACC lt R2 R6 R6 lt R6 2 lt IDX0 R11 R11 lt R11 2 IDXO lt IDXO QX1 ACC IDX1 R15 R15 lt R15 IDX1 lt IDX1 2 IDX1 QX0 R9 QR1 ACC lt IDX1 R9 rnd R9 R9 QR1 IDX1 lt IDX1 PROGRAMMING MANUAL CoMUL Multiplication Examples Cases op 1 op2 rnd MAE MAL N Z Sv E SL 0 MS x 8000 8000 0 00 4000 0000 0 0 0 0 1 5 0 0 00 8000 0000 0 0 0 1 1 1 0 00 7FFF FFFF 0 0 0 0 1 0 MS x 7FFF 7FFF 0 00 3FFFp 0001 0 0 0 0 1 MS x 0 00 7FFE 0002 0 0 0
172. truction set 2 4 3 Abbreviations Abbreviation Description Carry in the MSW register MP MP mode in the MCW register MS MS mode in the MCW register MAE 8 most significant bits of the accumulator lowest byte of the MSW register 2 4 4 Data addressing modes Addressing mode Description Or General Purpose Registers GPRs where any value between 0 and 15 Indirect word memory location CoReg MAC Unit Register MSW MAH MAL MAS MRW MCW Accumulator consisting of lowest byte of MSW MAH MAL data Immediate constant the number of significant bits is represented by x 2 4 5 Instruction format The instruction format is the same as that of the standard instruction set In addition the following new symbols are used Instruction Description X 4 bit IDX addressing mode encoding see following table 26444 3 bit GPR offset encoding for new GPR indirect with offset encoding 5 bit repeat field WWWW W 5 bit CoReg address for CoSTORE instructions SSSS 4 bit immediate shift value SSSS S 5 bit immediate shift value 145 197 MAC Instruction set PROGRAMMING MANUAL Addressing Mode 4 bit Encoding GPR Of
173. value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally See condition code Table 24 on page 48 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes CALLI cc Rw AB cn 2 PROGRAMMING MANUAL CALLR CALLR Syntax Operation Description Condition Codes Flags Addressing Modes Call Subroutine Relative CALLR SP lt SP 2 SP lt IP IP lt IP sign extend op1 A branch is taken to the location specified by the instruction pointer IP plus the relative displacement op1 The displace ment is a two s complement number which is sign extended and counts the relative distance in words The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine The value of the IP used in the target address calculation is the address of the instruction following the CALLR instruction See condition code Table 24 on page 48
174. wo specified bits Mnemonic Format Bytes BXOR bitaddrz bitaddrg ZZ qz 4 PROGRAMMING MANUAL CALLA CALLA Syntax Operation Description Condition Codes Flags Addressing Modes Call Subroutine Absolute CALLA 1 op2 IF op1 THEN SP lt SP 2 SP lt IP IP lt op2 ELSE next instruction END IF If the condition specified by op1 is met a branch to the absolute memory location specified by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally See condition code Table 24 on page 48 E 2 V Not affected Z Not affected V Not affected C Not affected N Not affected Mnemonic Format Bytes CALLA cc CAcOMMMM 4 73 97 CALLI PROGRAMMING MANUAL CALLI Call Subroutine Indirect Syntax CALLI op1 op2 Operation IF op1 THEN SP lt SP 2 SP lt IP IP lt op2 ELSE next instruction END IF Description If the condition specified by op1 is met a branch to the Condition Codes Flags Addressing Modes 74 197 location specified indirectly by the second operand op2 is taken The

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