Michael Brett - MacSphere
Contents
1. RETURN 9 0 h ACTR TRANSMISSION ROUTINE AC2 MESSAGE ADDRESS JSR 1 SENDM ERROR RETURN NORMAL RETURN NO MESSAGES RETURNED ALL ACCUMULATORS AND CARRY DESTROYED 9 90 9 5 SAVE RETURN ADDRESS IN HEADER SENDM SYNC ADDRESS CAPTURE ACTR CONTROL SAVE ADDRESS OF MESSAGE POINT AC2 PAST HEADER WORDS STORE IN TRANSMISSION POINTER GET WORD COUNT SAVE IT REALLY NEED WC 1 GET START CONTROL BITS GET DATA ADDRESS GET ACTUAL DATA PUT IN TRANSMITTER BUFFER NOW DETERMINE PARITY IS CONTROL WORD NON ZERO YES INC PARITY COUNTER NOW DO DATA WORD IS SHIFTED BIT SET YES INC PARITY COUNTER FINISHED DATA WORD NO CONTINUE IN LOOP GET PARITY ON BITS ODD OF BITS SET 2 YES PUT ODD PARITY BITS INTO CONTROL WORD PUT IN TRANSMITTER BUFFER START TRANSMISSION WAIT FOR ACKNOWLEDGEMENT GET CONTROL BITS IS IT NON ZERO YES TRANSMISSION ERROR GET END OF TRANSMISION BITS WAS END OF MESSAGE SENT MASTER CPU 55 CHECK IF MESSAGE IS TO RETURNED SLAVE CPU TAKE NORMAL EXIT NO RETURN MESSAGES IN SLAVE CPU 10407 LINK 01 92 83 04 05 6 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 90110 152400 02111 014434 001127000402 00113030425 001142. HNDL IXMT REC RTRN UIEX XMT 802932 5 31 000033 5 32 000202 9 21 000037 5 48 000034 5 26 000141 6 18 0002227 10 17 000140 6 47 000121 7 33 000213 10 07 000126 6 46 000132 6 15 0000015 XD 4 23 000016 5 31 0000007 EN 4 35 000062 gt 6 24 000090 4 22 9 27 000116 6 54 000247 11 19 000225 9 17 020143 25 34 000142 5 37 000152 7 19 002047 EN 4 36 000135 5 18 000137 6 22 0000025 4 24 000133 6 42 000145 6 20 000147 6 36 000144 7 28 000146 5 13 000150 EN 4 38 000014 5 14 000201 9 48 0000257 XN 4 18 000166 XN 4 28 090015 5 12 0000317 XN 4 21 0001237 XN 4 19 5 41 5 42 10 03 5 51 5 48 6 24 10 30 7 86 7 44 18 15 7 41 7 15 9 45 5 59 5 11 7 08 4 37 10 20 7 18 11 27 9 38 6 44 8 20 9 15 6 11 6 13 8 16 9 41 8 11 6 21 8 27 8 23 8 26 9 06 5 26 9 51 5 39 6 14 5 22 5 43 5 29 10 25 6 43 5 27 7 35 8 18 11 31 10 15 7 41 6 53 10 35 10 21 9 19 9 38 19 11 8 13 9 36 8 24 11 27 9 16 8 10 7 13 18 39 11 85 9 40 10 26 9 25 9 37 50 9 05 11 17 10 03 10 40 9 33 9 2 11 1 19 4 APPENDIX DIAGNOSTICS 2 52 2881 MACRO REV 04 00 _ 18 49 23 01 08 11 21 lt k k K K OR K kk R R R
3. ASYNCHRONOUS TRANSMITTER RECEIVER el Desig Bit June 3 1976 Sheet 3 of 3 ACTR DEVICE FLAGS Figure 3 10 and can respond to INTA instruction by returning its device code When the processor realizes that a new data word is present in the receiver the information is strobed into specified ac cumulators under program control allow the processor to sense the state of the ACTR it places its Busy and Done flags on the SELB and SELD lines whenever it its device cade The transmitter buffers are loaded from the I O bus by the DATOA data word and DATOB control bits signals e ively The transmission of data is controlled by 3 clocks retriggerable the Data Separation pulse the Trans mitter Clock pulse and the Data Width pulse The Data Separation pulse its name suggests is used to separate the individual bit transmissions to provide the receiver hardware time to act on each one This pulse is initially triggered by the STRT signal from the processor The STRT signal also sets the Busy flag which remains high as long as the transmission 16 in progress It is assumed that when the STRT signal is issued by the processor the information to be transmitted is already in the buffer the falling edge of the Data aration the Transmitter Clock pulse is triggered This pulse is used to s
4. both zero the device is idle and cannot perform operations To start device the program must set Busy to 1 and set Done to 0 When device has finished its operation ji Busy to O and Done to 1 The ACTR being essentially two devices in one 39 o 2 ac cops DEVICE CODE 4 5 6 V 8 10 11 12 13 14 15 I O INSTRUCTION FORMAT Figure 8 21 transmitter and receiver does not conforn to the standard DG flag configuration begin transmission the ACTR Busy flag must be set When the transmission is completed the ACTR will clear the Busy flag When a reception is completed the ACTR sets its Done flag The format for the I O instructions is illustrated in Figure 8 Bits 9 2 are 11 bits 3 4 specify the accumulator bits 5 7 contain the operation code bits 8 9 control the Busy and Done flags in the device and bits 10 15 specify the code of the device The six bits provided for the device code in the I 0 format mean that 6h unique device codes are available for use Some of these device codes however are reserved for the CPU and certain processor options Most of ue remaining codes have been assigned to particular device by General The device code normally chosen for the is In st ndard DG hardware this corresponds to amp Synchronous Communication Receiver SCR amp device which vill not be used a system with an ACT
5. INTERPROCESSOR COMMUNICATION LINK AN INTERPROCESSOR COMMUNICATION LINK FOR DATA GENERAL MINICOMPUTERS By MICHAEL EDWARD BRETT B SC Project Report Submitted to the School of Graduate Studies in Partial Fulfilment of the Requirements for the Degree Master of Engineering MeMaster University 1977 MASTER OF ENGINEERING 1977 McMASTER UNIVERSITY Engineering Physics Hamilton Ontario TITLE An interprocessor communication link for Data General minicomputers AUTHOR Michael Edward Brett B Sc Brock University SUPERVISOR Professor T J Kennett NUMBER OF PAGES iv 65 ABSTRACT The ACTR Asynehronous Communications Receiver is a serial data transfer link for the Data General ECLIPSE and NOVA minicomputer lines The ACTR allows the interconnection of computers in the NOVA and ECLIPSE lines into amp multiprocessor system by permitting blocks of data to be transferred through the computers program I O facitities Such a small computer multiprocessor system is amp powerful high flexible alternative to a 5 48 82 6 large in many applications The major appli cation of the ACTR is in systems where the linked processors are either far remote from one another or where the system is so con figured that a master slave environment is practical This report will deal with the theory of Operation of the hardware as vell as the software control of the ACTR A method of
6. by the processor s channel facilities typical data rates for a single link range from TO KHz a pair of NOVA computers to 140 KHz for NOVA line computers with the high speed data channel feature This report will deal with the implemention of asyn chronous data link of the program I O variety for Data General NOVA and ECLIPSE minicomputers The Data General Corporation NOVA and ECLIPSE lines of computers general purpose four accumulator stored program conputers with a word length of 16 bits The basic instruction set contains instructions that perform fixed point arithmetic between accumulators transfer of operands between accumulators and main storage and logic Operations between amp ccumulators In addition to an assembler and a macroassembler there amp re higher level language processors available which in clude ALGOL BASIC FORTRAN IV and 5 There is wide array of operating systema available for the NOVA ECLIPSE line of mini computers These range from the Stand Alone Operating System SOS to the Real time Dise Operating System RDOS The ACTR Asynchronous Communication Transmitter Receiver is a self clocking data unit which consists Df udspendeHt transmitter and receiver sub sections Information is clocked bit by bit onto transmission line complete word transfer consists of the movement of 20 bits 16 bit data word and 4 control status bits Each Bit 18 RE by a
7. 20031 000130 CONTD 00232 002046 TICK 00033 000113 5 00034 0000009 TIME 00235 0022020 SAVE 09036 000000 LOAP 00037 022004 4 00000 TOTAL ERRORS ee 99 WRITE ENDUP 52 INT CODE 14 40 9 11111 CONT CLOCK MASK G 0 0 4 START 000900 PASS 1 ERRORS 62 ZREL 3 PAGE 0 CONSTANT STORAGE 0012 ACTR AHEAD BACK BACKD CLOCK CODE CODE 1 CODER CONT CONTD END ENDUP ERRI FINIS HOLD INT INTPT LEAVE LOAP LOOP MASK MASKD MESI 0510 513 MES2 520 521 522 523 MES31 540 541 542 543 55 56 MEST 58 59 MESSA MORE NO OUT OUTPT 2 RETUR RITER SAVE SERVI SERV2 STAR START 229241 5 19 220261 8 12 2888 30 9 85 2880 46 2 51 098271 5 83 029385 6 18 23 8 15 078130 4 09 202031 8 35 4 14 2090210 4 15 020001 2 35 9 11 200222 5 10 000251 25 39 888218 4 21 000026 8 11 9000365 8 04 002022 2 22 000362 1 24 000036 6 08 099140 4 18 200113 3 48 009033 8 32 009520 2 34 229786 8 19 720 9 16 000544 2 39 201011 8 49 000512 3 15 200616 3 21 090642 3 26 001220 4 10 201037 5 01 201054 5 05 021101 5 09 201125 5 11 000743 8 41 200763 8 45 001160 9 18 291284 9 22 000666 8 13 998446 2 27 999322 6 6 27 4 11 02003417 1 11 209265 4 55 001135 1
8. INTERRUPT SERVICE ROUTINE GET DEVICE CODE CAUSING INT 14 CODE OF RTC RTC CAUSED INTERRUPT 40 CODE OF ACTR ACTR CAUSED INTERRUPT UNKNOWN INTERRUPT WRITE ERROR MESSAGE OUTPUT DEVICE CODE 18 DONE NO WRITE MESSAGE GO TO ENDUP CLOCK INTERRUPT SERVICE ROUTINE OK CLOCK STABILIZED OK INTERRUPT CLEARED OK ACTR MASK OPERATIONAL TO REACH HERE ACTR INTERRUPT HAS FAILED PRINT INTERRUPT ERROR MESSAGE DID TRANSMISSION TERMINATE NO a NO PRINT MESSAGE DID RECEPTION OCCUR YES NO PRINT mESSAGE TERMINAL 110021 109099 ACTR 81 a2 03 4 95 06 01 08 09 00421 014002 SERV2 00430 002030 00431 014005 00432 00424 00433 006000 9434 001160 00435 002001 00436 01 4003 00437 900404 00440 006000 0441 720 00442 0062001 0443 66 0 0 0 444 001204 00445 002001 DSZ 252 JSR MEST JMP DSZ JMP JSR TAGI eBACKD TAG 4 RITER END TAG2 4 TER MES13 JSR MES8 END RITER END 60 ACTR INTERRUPT SERVICE ROUTINE OK ACTR INTERRUPT GENERATED INTERRUPT DURING CLOCK STAB 52 WRITE ERROR MESSAGES TERMINAL ERROR INTERRUPT AFTER NIOC YES WRITE ERROR MESSAGES TERMINAL ERROR INTERRUPT HAD TO BE GENERATED DURING MASK OUT TESTS WRITE ERROR MESSAGES TERMINAL ERROR
9. 002227126000 002237065140 000000 0090091 00224 000726 AHEAD LDA 3 RDATA STA 3 8 2 DSZ WC JMP 2 JMP FINISH SUB 0 9 DOAS 0 ACTR INC 2 2 JMP RECM FINISH LDA 0 AND 1 SNR JMP ERROR SUB 0 0 DOAS ACTR MASTER NEXIT ENDC IFE MASTER JSR HNDLR JMP RECM ENDC ERROR ADC 1 1 DOAS l ACTR IFN MASTER JMP FLOP ENDC IFE MASTER JMP RECM ENDC e 9 9 ve 48 GET RECEIVED DATA STORE IT DECREMENT WC 0 CHECK ETX SEND OK MESSAGE INCREMENT POINTER GET NEXT RECEPTION GET ETX BITS WAS ETX RECEIVED NO ERROR YES PUT SEND DATA OK MESSAGE MASTER CPU COMPLETED RECM TAKE NORMAL EXIT SLAVE CPU JUMP TO ROUTINE AWAIT NEXT MESSAGE TO HANDLE RECEPTION ERROR EXIT FROM RECM 1 1 SEND DATA ERROR MESSAGE a MASTER CPU TAKE ERROR EXIT FROM SENDM SLAVE CPU AWAIT NEXT MESSAGE 10011 LINK 01 02 03 04 05 06 7 08 89 18 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 21 28 29 30 31 32 33 34 35 02000 TOTAL ERRORS 002257102400 PARITY SUB 0 0 98226 024715 002277125122 002307101400 002317125004 002327000775 002337024707 002347125122 002357101400 002367125004 00237
10. 02 3 3 94 5 NAME ACTR SR ASYNCHROUS COMUNICATION TRANSMITTER 35 3 RECEIVER DIAGNOSTICS 6 3 097 AUTHOR MICHAEL BRETT 08 3 99 3 REVISION HISTORY 12 3 REV DATE 3 00 AUG 1 76 12 3 j 13 3 NARRATIVE 14 3 THIS PROGRAM WILL FIRST DISABLE RDOS THE FLAGS AND 15 3 INTERRUPTS OF THE ACTR WILL THEN BE TESTED NEXT 16 3 TRANSMISSION TESTS WILL BE CARRIED OUT APPROPRIATE 17 ERROR MESSAGES WILL BE OUTPUTTED EXECUTION OF THE 18 3 PROGRAM WILL BE TERMINATED WHEN AN INTERRUPT OR 19 5 FLAG ERROR 15 DETECTED THE ERROR OUTPUT FROM THE 20 3 THE TRANSMISSION PHASE CAN BE TERMINATED BY TYPING 21 3 CONTROL C ERROR STATISTICS WILL STILL BE OUTPUTTED 22 3 AT THE TEST TERMINATION CONTROL IS RETURNED TO RDOS 23 3 24 3 OPERATION 25 3 CONNECT RECEIVER INPUT TO TRANSMITTER OUTPUT 26 3 AND START PROGRAM M 21 3 THIS 15 STAND ALONE TEST OF SINGLE ACTR BOARD 28 3 AND REQUIRES USE THE RTC 29 3 30 3 NOTE 2 E 31 3 THIS PROGRAM CAN BE USED TO TEST THE INTERPROCESSOR 32 LINK BY RUNNING THIS PROGRAM IN THE MASTER CPU AND 33 3 USING THE SLAVE CPU TO REFLECT THE DATA 34 3 35 18002 ACTR 01 000401 000040 00000006017 START 000010210200 00002000491 00003 101400 00004 040034 00005060277 00006020001 000071 040035 0200210 020022 00011040001 00012 102400 000130962011 020014 006000
11. KEYBOARD TO ACIsCLEAR FLAG MASK OUT TO 7 BITS IS IT CONTROL P NO INVALID CONTINUE OUTPUT YES CONTROL P 8 TERMINATE PRINTING ERRORS STOP 1 RETURN TO MAINLINE NOW STOP HAS BEEN PUT 1 NOW STOP WHICH IS CORRECT FOR NON SUPPRESSION QUTPUT TRANSMITTED WORD PRINT MESSAGE OUTPUT RECEIVED WORD PRINT MESSAGE RETURN MAINLINE 10208 01 22 93 04 05 09365 965477 20366 932024 200367 146415 00370 088416 00371 238825 00372 146415 00373 000434 00374 044026 20375 006090 209376 000666 00377 0240926 88490 206823 004010636409 00402 000403 00403 006008 08404 008706 00405 002001 00406 014005 04407 002032 00410 0140203 00411 0 2033 00412 414004 220413 92931 00414 006000 90415 000743 202416 63649 094 7 8403 0420 006000 02421 200 763 00422 063640 00423 000403 00424 006000 00425 001011 0426 002001 DIB 1 LDA 25 14 SUB 231 SNR JMP SERVI LDA 25 49 SUBA 2515SNR JMP SERV2 STA 1 HOLD JSR TER MES9 LDA 1 gt HOLD JSR CODER SKPDN ACTR JMP 43 JSR RITER MES1 JMP END DSZ TAG JMP eTICK DSZ TAG2 JMP eMASKD DSZ TAG3 JMP CONTD JSR eRI TER MESS SKPDN ACTR JMP 43 JSR RI TER MES6 SKPDN ACTR JMP 3 JSR eRI TER 520 JMP END we Wee 29
12. such data analysis or data collection from the remote processors In critical real time situations this redundancy may give measure of safety to a total system assuring continued operation even when catastrophic failure occurs in major system component In order to implement multi processor system of any description reliable method of processor processor communication is needed In the Data General NOVA and ECLIPSE minicomputer lines data transfer links can be divided into two classes with each class characterized by the method of input Oqtput that it employs The first class involves all devices that transfer in formation through the use of the data channel facility A device connected to the data channel can at its own request gain direct access to memory using a minimum of processor time The second class involves all devices that process data through program 1 0 all imput output through accumulators Handling data transfers between external devices and memory under control requires an interrupt plus the execution of several instructions for each word transferred Data General s Multiprocessor Communications Adapter MCA is amp data transfer link of the data 2 variety The MCA facilitates the interconnection of up to fifteen computers j ine NOVA and ECLIPSE lines into a multiprocessor system by blocks of data to be transferred at high speeds from one computer to another Data rates are
13. 00015 000446 00016063511 00017900777 00020 062677 00021063440 00022000404 00023 006000 00024 000520 00025 002091 00026 063640 00021 000404 00039 00 6000 009031 000544 99932 992991 00033 102400 00034 040005 20035 121428 22036 040092 90037 040003 28040 640004 60041 61214 00042 68177 0043 0600114 000944 4 1 26045 000777 00046 126440 CLOCK 00047 044002 00858 125400 00051 044005 ACTR ENT START 1 400 1 DUSR 1520 SYSTM GHRZ JMP 1 INC 0 0 STA 0 TIME INTDS LDA 851 STA sSAVE LDA sINTPTR STA 0 1 SUB 0 0 0 CPU JSR TER MESSA SKPBZ TTO JMP 1 1057 SKPBN JMP JSR RITER MESI END SKPDN ACTR JMP 4 JSR eRITER MES2 JMP END SUB 6 8 STA 0 INC 0 0 STA TAGI STA s 2 STA sTAG3 DOA s INTEN NIOS RTC JMP 1 e i SUBO 1 1 STA 1 TAGI INC 1 1 STA 1 TAG e 5 5 Wwe lov B ACTR DIAGNOSTIC START OF DIAGNOSTIC 53 GET SYSTEM RTC FREQUENCY INCREMENT IT BY 1 STORE 17 DISABLE INTERRUPT GET RDOS INTERRUPT POINTER SAVE IT GET ADDRESS OF SERV ROUTINE STORE IN LOCATION 1 CLEAR INT WRITE TITLES
14. RITER MES23 END SUB 151 STA 1sTAG2 INC 151 STA 1 7 6 STA 1 1 1 TAG3 NIOS RTC NIOS CPU JMP 1 JMP 1 LDA 1 200 MSKO 1 SUBO 1 1 STA 1 gt 63 INC 151 STA 1 gt 1 STA 1sTAG STA 1 TAG2 NIOS RTC NIOS ACTR I NTEN JMP 1 JMP 1 we lov we TAG2 1 TAG3 1 START RTC 5 RTC STABILIZED AT 10 HZ START TRANSMITTER ENABLE INTERRUPT WAIT FOR INTERRUPT CLEAR FLAG TEST SKIP IF 0 OK DONE IS 1 ERROR PRINT ERROR MESSAGE CLEAR DONE AND BUSY IS BUSY 9 YES OK NO WRITE MESSAGE TERMINAL ERROR 15 0 YES NO WRITE ERROR MESSAGE TERMINAL ERROR TAG2 9 1 1 1 TAG3 1 START RTC ENABLE INTERRUPT WAIT FOR INTERRUPT PRECEDING TESTS IF NIOC WILL CLEAR INTERRUPT REQUEST OF ACTR TEST FOR ACTR MASK OUT ACTR MASK MASK OUT ACTR INTERRUPT 1 6350 TAGi 1 TAG 1 62 1 START START TRANSMITTER ENABLE INTERRUPT NO OP FOR INTERRUPT 0004 81 02 93 04 45 06 07 08 09 00130 006000 001317001220 00132 0209021 00133 040012 00134 102400 00135 00136 0400 1 06137 4091 3 001 4 022012 100 00141 01 4012 00142 0004092 00143 0900445 00144 0
15. WAIT FOR TTO TO FINISH CLEAR ALL FLAGS SKIP IF BUSY 1 OK FLAG ERROR 1 BUSY SHOULD EQUAL 9 TERMINAL ERROR SKIP IF DONE 1 OK FLAG 9 ERROR 11 DONE SHOULD EQUAL TERMINAL ERROR SET UP INTERRUPT FLAGS TAG 0 61 1 TAG2 1 TAG3 1 SET CLOCK FREQUENCY 1 HZ ENABLE INTERRUPT START CLOCK PERFORM NO OP TO WAIT FOR INTERRUPT PREVIOUS SECTION USED TO STABILIZE RTC FOR ACTR INTERRUPT TESTS TAGI 1 0003 ACTR 90052 044003 01 02 95 00053 044004 00054 060114 00055060140 00056060177 00057000401 000600007771 00061063740 00062 000404 00063 006000 00064000572 00065 002001 00066060240 00067 063449 200070 000404 00071 0060090 08872 000616 00073 802001 08874 063640 00075 0090404 00076 006800 77 000642 00100002001 00101126400 00102 044093 00103125400 00104 044005 00105 044002 00106 044004 00107060114 00110060177 00111000401 00112000777 00113 024006 00114 06601 00115 126440 00116 044004 00117125400 00120 044002 00121 044005 00122 044003 00123 060114 00124060140 00125060177 00126000401 00127000777 STA STA 1 2 STA 1 NIOS NIOS ACTR INTEN JMP 1 JMP 1 SKPDZ JMP 4 JSR RITER MES21 JMP END NIOC ACTR SKPBN ACTR JMP 4 JSR RITER 522 JMP END SKPDN ACTR JMP 4 JSR
16. clock pulse which is teed to activate the clocking cycle of the ACTR receiver in the other system When ier ception of the incoming wera is completed the receiver sets flag The ACTR receiver is connected to the interrupt system i e tne ACTR receiver can generate an interrupt request 5 3 DATA SEPARATION STRTP 4123 DATOP 4 8 PULSE TET DATA ranas loo 15 DLP TRANSMITTER DevseL m clock Pulse DATAO gt ns ol DATA WIDTH 5 SHIPT DATA PULSE bur wa 2 10 250 5 n az lo 5 6 7 41 9 E Y A io 16 smr 1 D 22 oft ee 45 17 T OUTGOING 4 DATA COUNTERS TRANSMISSION c LING 732 13 stare ASYNCHRONOUS COMMUNICATION TRANSMITTER RECEIVER Design uL June 3 1976 Sheet 101 3 TRANSMITTER Figure 1 DATART DATA CONTROL WORD 4 BITS RECEPTION COMPLETION CLOCK 6 2 n Done 5 8 1 INCOMING TRANSMISSION 4 4 45 E je bara Seek CLOCK Wo 45 Cie Bits d uk 46 mj 56 15 15 46 ASYNCHRONOUS COMMUNICATION TRANSMITTER RECEIVER ed Design Mek June 3 1976 ACTR RECEIVER Figure 2 3 85 INTR INTR DATA
17. e the processor to recognize data transmission amp s soon as it is received rather than periodically checking the ACTR new messege Use is made of the level interrupt scheme operating systems such as Data General RDOS Real Time Disc T Operating System and RTOS Real Time Operating System These Systems supply a multi priority level interrupt handler Devices are included in this handler either at system generation or during run time When an interrupt 15 detected by the hardware the currently executing program is suspended and control goes to an interrupt dispatch program This routine directs control to the correct servicing ise by using the devi e code obtained by INTA instruction as an index into an interrupt branch table The entry in this table is the address of a device control table DCT associated vith the device service routine This table contains the service mask that is to be ORed with the current 21 interrupt mask while control is in the device service routine This mask establishes whick devices if any will be allowed to interrupt the currently interrupting device Since interrupts amp re enabled when control 18 passed to device service routine the interrupt service mask must contain the mask bit Pas the device being serviced The handling of the through the facilities of RDOS RTOS relieves the programmer of the responsibilities of maintainig program contin
18. k k k kk k kk 85 SUBROUTINES THE LINK STRING MUST INCLUDE A FILE WHICH DEFINES THE PARAMETER MASTER MASTER 1 FOR A MASTER CPU COMPILE AND MASTER 0 FOR A SLAVE CPU COMPILE THIS EQUATE MUST APPEAR FIRST IN MAC STRING K Kk k k k k k k k k k k k k k k k k K k k e k k kk kk k h k k kk kk k k e e k k e kx ke ke fle kk k 06 EXTERNAL DATA we EXTN IXMT EXTN XMT EXTN REC EXTN UIEX IFE MASTER EXTD HNDLR EXTD TABLE ENDC RDOS RTOS TASK CALL RDOS RTOS TASK CALL RDOS RTOS TASK CALL RDOS RTOS TASK CALL SLAVE COMPUTER LOCATION OF HANDLER TABLE LOCATION OF RECEPTION 9 Kk k x k k k k k k k k k k k k k k kk kk kk kk k k k kh kk kk k k k k k 07 PROGRAM 9 DUSR 40 DEUR EJSR 6401 ENT IDACTR ENT SENDM MASTER ACTR ENDC NREL PAGE l RELOCATABLE 10005 LINK 02 04 05 06 07 98 09 19 11 12 13 14 15 16 17 18 19 28 23 22 23 24 25 26 27 28 29 38 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 000007054415 000017020545 000027024412 IDACTR 000037006017 000047021007 000057063077 000067020527 000077126000 000107077777 000117063077 000127030403 000137001001 00014 000034 00015 00009
19. 20 8 08 6 91 6 11 6 23 5 36 4 51 4 18 2 60 2 58 3 91 3 02 4 44 4 43 4 46 4 45 6 15 11 31 5 17 4 58 11 05 11 25 11 17 7 37 11 11 1738 11 14 11 36 11 26 6 32 6 25 6 35 5 39 4756 4 19 3 31 3 32 3 29 3 33 1 21 11 19 1 31 11 21 6 11 5 21 7 04 6 34 5 41 1 05 4 22 3 54 3 53 3 55 3 51 11 18 11 22 6 16 11 33 5 50 1 91 4 23 8 28 9 04 8 31 8 34 6 22 1 28 11 15 9 07 11 27 9 13 11 29 6 33 1 26 11 10 11 98 BIBLIOGRAPHY ECLIPSE Line Real Time Operating System User s Manual Rev Off Southboro Mass Data General Corporation 1975 j ECLIPSE Line Real Time Disc Operating System User s Manual Rev 01 Southboro Mass Data General Corporation 1975 How to Use Nova Computers Rev 99 Southboro Mass Data General Corporation 297 Introduction to ECLIPSE Line Real Time Operating System 00 Southboro Mass Data General Corporation 1975 Introduction to ECLIPSE Line Real Time Disc Operating System Rev 20 Southboro Mass Data General Corporation 1975 User s Manual ECLIPSE Macro Assembler Rev 00 Southboro Mass Data General Corporation 1975 Programmer s Reference Manual ECLIPSE Line Computers Rev Southboro Mass Data General Corporation 1975 65
20. 44416 00247 010414 0250 020011 00251 025413 00252 197415 00253 092419 00254 004411 00255 125300 00256 1917415 292257 02404 222639 024485 00261 81843 20262 0807 7 00263 0020200 RETURN 00264 000200 ENDUP ERRI PT 00265 063511 OUTPT 90266 009T1171 002671 965111 002712001400 540 LDA 1 CT2 JSR CODE JSR RITER 34 LDA 15 1 JSR CODE JSR RITER MES42 JSR RITER MES43 SKPBZ TTO JMP 1 LDA 1 SAVE STA 151 1082 DSZ TIME JMP 2 JMP AHEAD LDA 05 4 LDA 15 5 8 9 1 SNR SUB 151 DOAS 1 INTEN SYSTM RTN STA LDA STA 152 3 RETURN 1 5 GRETURN 1 RETURN LDA 0 377 LDA 15 PT AND 6 1 SNR JMP RETURN JSR OUTPT MOVS 151 AND 515SNR JMP RETURN JSR OUTPT 157 PT JMP ERRI 2 SKPBZ TTO JMP DOAS 1 TTO JMP 9 3 oo 69 tee ee um ON OF INCORRECT CONTROL WORDS TRANSFERRED WRITE INFORMATION ON OF INCORRECT DATA WORDS TRANSFERRED TERMINATION OF PROGRAM WRITE MESSAGE WAIT FOR TTO TO FINISH GET ADDRESS OF RDOS INT HAND PUT IT IN LOCATION 1 CLEAR ALL FLAGS I IS THERE A SYSTEM CLOCK YES NO 4 SYSTEM FREQUENCY IS IT 4 4 60 HZ 1 FOR SETTING CLOCK TO 60 HZ SET FREQ AND STA
21. In Systems of videly differing speeds such as a teletypewriter vers s fixed head disc the programmer may wish to set up multiple level interrupt scheme Hardware and instructions are available on the NOVA ECLIPSE computers to allov the implementation of priority interrupts Each of the I 0 devices is to bit in the 16 bit priority mask Devices which operate at roughly the same amp peed are connected to the same bit in the mask Even standard mask bit assignments have higher number bits assigned to low speed devices no implicit ordering is intended The manner in which these priority levels ordered is completely up to the programmer The condition of the priority mask is altered by the MASK OUT instruction If a bit in the priority mask is set to 1 26 then 11 devices in the priority level corresponding to that bit will be prevented from requesting on interrupt when they complete an operation In addition all pending interrupt requests from devices in that priority level are disabled The priority mask bit for the ACTR is bit 8 If the receiving computer has many calculations to jar form it cannot handle an incoming ACTR transmission by contin ually testing the state of the Done It is necessary then to use the interrupt system to allow the processor to do other com puting between interrupts Sac rere ere the ACTR when it has received a complete scheme also allows
22. kk k k k kk k k kk k k k kk k kk k kk k n k ik k k kx kx 03 DESCRIPTION NARRATIVE THIS ROUTINE IS A SOFTWARE INTERFACE TO THE ACTR IT OPERATES IN A MASTER SLAVE ENVIROMENT WITH THE MASTER CPU INITIATING ALL DATA TRANSEERS MESSAGE FORMAT IS DESTINATION WORD COUNT MESSAGE ACTUAL MESSAGE WORD COUNT DOES NOT INCLUDE LEADING OR DESTINATION MESSAGE CORRESPONDS TO A TABLE ENTRY IN SLAVE CPU IGNORED IN RECEPTION IN MODEL DESTINATION IN MODEL IS 1 IF NO RETURN MESSAGE IS EXPECTED CONTAINS RECEPTION ADDRESS IF RETURN IS EXPECTED IGNORED IN THE SLAVE FIRST 2 WORDS OF MESSAGE ARE NOT TRANSMITTED WHEN SENDM IS CALLED AC2 MUST CONTAIN A POINTER TO THE START Or THE MESSAGE AN STX IS SENT WITH THE WORD COUNT AND AN ETX WITH THE LAST WORD THE RECEIVING COMPUTER WILL PERFORM A PARITY CHECK ON THE INCOMING DATA IF AN ERROR IS DETECTED IT WILL SEND AN ERROR MESSAGE IN THE DATA ACKNOWLEDGEMENT IF SENDM RECEIVES AN ERROR MESSAGE NO FURTHER TRANSFERS WILL BE ATTEMPTED AND THE ERROR EXIT WILL BE TAKEN IDACTR WILL IDEF THE ACTR TO RTOS RDOS AND RELEASE THE SENDM SYNC WORD SO THAT SENDM CAN BE ACCESSED THE SLAVE CPU RECEPTION TASK ACTR WILL USE THE MESSAGE TO FIND THE RECEPTION AREA FROM AN EXTERNAL TABLE TABLE AND TO FIND THE HANDLING ROUTINE FOR THE MESSAGE FROM ANOTHER EXTERNAL TABLE HNDLR ACTR MUST BE TASKED OFF DURING SYSTEM INITIALIZATION KK kk k k k k k k k k k
23. the Qoupl tion clock falls it clocks the DONE over 1 This can be determined by sensing the DONE flag or through the interrupt standard on the NOVA ECLIPSE line Since reception of data can normally occur 85 any time the normal operating environment for amp system using the ACTR would be with the interrupts end tud so that the CPU can respond to data reception whenever it happens In every instruction cycle the processor generates RQENB 122 places ewe interrupt request signal INTR on the bus from given device i e sets its INT REQ flip flop if its Done flag is set and its Interrupt Disable flag is clear Under control the processor will generate the MSKO signal to set up the Interrupt Disable flags of all devices according to the infor mation on the data lines 1 to set the Interrupt Disable and DATAB 0 to clear the ACTR Int rrupt Disable In the ACTR interface the actual flag is amp INT ENABLE but it responds to amp generated MSKO instruction as any standard DG interface would After thiexeupt has been recognized program control will go to the interrupt handler specified in 16 memory location 2 of the processor The interrupt Bandler can determine which device needs service by sensing Done or it can issue INTA to read the device code of the nearest device requesting an interrupt When an INTA instruction is executed by the processor the INTP IN signal i
24. 0 090016 050414 00017 054414 00020 064440 000217244522 000227065640 000237044517 000247126000 000257077777 000267063077 000277030403 000307034403 020317077777 000327020000 000337000000 000347000037 000357000377 00036 000016 000377000010 AYDCT AC2 AC3 AYDCT AREA 9 9 94 STA 3 RTRN LDA l AYOCT SYSTM IDEF HALT LDA SSEND ADC 1 1 XMT HALT LDA 2 RTRN JMP 1 2 AYDCT 0 STA 2 2 STA DIA 1 STA l RCONT DIBC 1 ACTR STA 1 RDATA ADC 1 1 IXMT HALT LDA 2 AC2 LDA 3 AC3 UIEX AREA 371 IACTR BLK 8 h3 IDENTIFY ACTR TO RTOS RDOS NO ACCUMULATORS PASSED CALL JSR 1 IDACTR RETURN ALL ACCUMULATORS AND CARRY DESTROYED 9 we w SAVE RETURN ADDRESS DEVICE CODE OF ACTR ADDRESS OF ACTR DCT IDENTIFY ACTR TO SYSTEM SYSTEM ERROR ADDRESS OF SENDM SYNC MAKE ACl NON ZERO NOW SAFE TO RELEASE SENDM SYSTEM ERROR GET RETURN ADDRESS BUMP BY ONE FOR EXTENDED CALL RETURN TO CALL ADDRESS OF ACTR DCT RETURN ADDRESS ACTR INTERRUPT HANDLER SAVE AC2 SAVE AC3 GET CONTROL WORD SAVE IT GET DATA WORD AND CLEAR INTERRUPT SAVE DATA WORD MAKE NON ZERO SIGNAL MESSAGE RECEIV
25. 01707034752 LDA 3 RDATA 41 00171 8300025 LDA 2 TABLE 42 001727173000 ADD 3 2 43 001737031002 LDA 2 0 2 44 45 00174 0240815 LDA 1 HNDLR 46 00175 1370900 ADD 1 3 47 00176 035400 LDA 3 0 3 48 001777054402 STA 3 HNDLR 49 890208 000752 56 51 00201 000000 HNDLR 0 52 ENDC e e Se ne 9 9 w w 1 9 vo SLAVE RECEIVER TASK IDENTIFY ACTR TO SYSTEM NOW AWAIT RECEPTION IN ROUTINE RECM RECEPTION ROUTINE RECEIVER WAIT SYNC WAIT FOR RECEPTION DO PARITY CHECK NOW CHECK FOR STX GET CONTROL BITS WAS STX SENT NO JMP AROUND MASTER CPU GET WC WC FIRST WORD RECEIVED STORE IT IN WC SLAVE CPU GET RECEPTION AREA FOR SLAVE WC AC3 M 2 FROM WORD COUNT TAKES CARE WC AND MESSAGE 8 GET RECEPTION SYNC WAIT FOR RECEPTION CHECK PARITY GET MESSAGE i START OF RECEPTION TABLE G T RECEPTION AREA POINTER GET RECEPTION AREA GET START OF TABLE GET HANDLER ADDRESS STORE IN POINTER RECEIVE NEXT WORD HANDLING ROUTINE POINTER 10610 LINK 81 02 03 04 05 06 07 08 09 00202 7034740 002037055004 202047014741 002057002402 00206 000405 002077102400 002107061140 002117151400 002127000749 002137020725 002147107415 002157000405 002167102400 002177061140 000000 000001 00220 006761 002217000731
26. 08 99 18 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 001327000000 001337000134 001347000000 00135 000136 00136 090000 001377000001 001407000002 001417000000 001427000000 001437000000 001447000003 001457000000 00146000040 001477000014 HEAD TRANS SSEND STX ETX DATPTR RDATA RCONT 3 40 14 CONTROL WORDS 1 atl QQ Sw ACTR 14 56 FOR ACTR ROUTINES e lt e 9 START MESSAGE TRANSMISSION SYNC SENDM CONTROL SYNC STX CONTROL BIT ETX CONTROL BIT MESSAGE POINTER RECEIVED DATA WORD RECEIVED CONTROL WORD WORD COUNT DEV CODE OF ACTR PARITY INDICATORS _ 83 10099 LINK 61 62 04 95 000001 IFE MASTER 06 00150 006401 ACTR EJSR IDACTR 07 020000 g8 69 18 ENDC 11 12 13 14 15 001527020761 RECM LDA TRANS 16 001537000101 17 001547004451 JSR PARITY 18 001557020762 LDA 0 STX 19 001567024765 LDA l RCONT 20 001577107415 AND 1 SNR 21 00160 000422 JMP AHEAD 22 000099 IFN MASTER 23 LDA 1 RDATA 24 25 STA 1 WC 26 ENDC 27 009091 MASTER 28 29 H5 30 001617030761 LDA 2 RDATA 31 001627176120 ADCZL 3 3 32 001637173000 ADD 3 2 33 001647050761 STA 2 WC 34 35 36 00165 020746 LDA 0 5 37 001667000153 38 001677004436 JSR PARITY 39 40 0
27. 10010 ACTR 09446 005015 02464 020840 00515 0096411 80528 052502 00542 006411 09544 047504 00566 096411 00572 941501 006147006411 00616 052502 006237 004440 00642041504 00663 004440 00666 47125 007060205015 00120041501 001417006411 00143041501 00163041516 01027006411 01011041519 01035006411 01037020042 01054 041440 01077006411 01101042040 01122004531 01125 042440 01135053440 01150053440 01160 241581 01201 9004524 81204 041501 01220 046106 81237 020114 91261 020123 21316 00641 1 01326 9020103 000900 MESSA MESI MES2 MES21 MES22 MES23 59 510 513 55 56 520 540 541 MES42 MES43 PT1 PT2 MEST MESS 041531 61 3 TITLES AND ERROR MESSAGES lt 15 gt lt 12 gt ACTR DIAGNOSTICS lt 15 gt lt 12 gt lt 12 gt FIRST FLAGS AND INTERRUPTS WILL BE TESTED lt 15 gt lt 12 gt lt 12 gt TXT BUSY FLAG DOES NOT RESPOND IORST lt 15 gt lt 12 gt TXT DONE FLAG DOES NOT RESPOND IORST lt 15 gt gt 12 gt TXT ACTR INTERRUPT GENERATED WHEN DONE 9 15 12 TXT BUSY FLAG DOES NOT RESPOND TO NIOC lt 15 gt lt 12 gt TXT DONE FLAG DOES NOT RESPOND TO NIOC lt 15 gt lt 12 gt TXT UNKNOWN INTERRUPT CODE lt 15 gt lt 12 gt AND ACTR 1 lt 15 gt lt 12 gt ACTR INTERRUPT NOT CLEARED BY lt 15 g
28. 26012 00145 914012 00146 000402 00147 900441 00150 030014 00151 147400 00152061240 00153066140 00154063640 00155 000777 00156 0710440 00157075640 00160 040015 00161 044016 9098162 850817 00163 054020 00164 142415 00165000403 00166 004541 00167 0109007 00170 024016 00171 044015 001712 034020 00173 0540117 001 74 136415 00175 000743 00176 010010 20177 014013 00200000402 00201000403 00202 0240921 00203 004462 00204 010 213 00205 229491 00206 004521 00207000131 JSR RITER MES3I LDA 90 NO STA STRPTR SUB 9 0 STA STA CT2 STA 0 5 LDA STRPTR DSZ STRPTR JMP 2 JMP FINISH LDA 1 8 STRPTR DSZ STRPTR JMP 2 JMP FINISH LDA 2 17 AND 2 1 DOAC DOBS 1 SKPDN ACTR JMP 1 DIA 2 DIBC 3 ACTR STA O TEMO STA 1 1 STA 2 TEM2 STA 3 SUB 2 0 SNR 43 JSR TRANS 152 LDA 1 STA 1 LDA 3 STA 3 2 SUB 153 SNR JMP LOOP 157 CT2 DSZ STOP JMP 2 JMP 3 LDA i STAR JSR OUTPT ISZ STOP t JSR TRANS LOOP 00210 006000 5 JSR RITER eo 99 fos lor 959 169 255 IF EXECUTION REACHES FLAG TESTS COMPLET
29. 32 001159 1 34 000263 5 34 998988 2 26 4 60 8 18 11 5 35 2 21 000406 8 01 008421 8 19 000821 4 54 0000090 EN 2 04 5 21 11 29 11 29 11 31 5 91 6 29 11 24 11730 11 30 4 42 4 50 2 490 9 17 11 86 5 48 4 25 8 14 11 23 11 23 1 09 6 28 4 48 11 32 11 32 19 67 19 18 19 19 19 89 19 24 19 11 19 13 19 15 19 37 19 26 19 27 19 29 19 31 19 21 18 22 19 34 19 36 19 17 19 94 6 30 11 28 1 11 5 42 19 32 19 33 5 35 2 33 5 04 8 40 5 14 8 28 9 04 11 22 2 14 6 26 5 06 5 02 3 16 9 23 4 60 11 27 1 21 11 35 4 59 6 31 1 25 5 46 5 37 2 38 5 08 8 44 11 34 11 39 1 28 11 12 11 13 3 22 11 06 1 35 5 52 5 41 3 14 5 19 8 48 1 32 3 27 1 36 6 14 5 45 3 20 7 29 9 09 11 24 8 20 6 27 5 49 3 25 1 33 9 15 63 8 50 4 89 8 12 9 21 0013 STOP STRPT TAG TAGI TAG2 TAG3 TASK TEMO TEM 1 TEM2 TEM3 TEMP TICK TIME TRANS WRITE 14 17 ETT 2 229213 002012 000005 0O00902 28888 3 200004 000401 000015 002016 99981 080820 000324 32 200034 000321 286244 000024 999 14 000363 000026 090364 3099911 009031 880825 000323 000325 022326 000264 4 16 11 16 4 12 2 42 2 44 2 45 2 46 2 06 4 35 4 36 4 31 4 38 6 10 8 29 2 18 4 41 5 34 8 05 4 26 1 12 3 48 17715 5 38 5
30. 7000775 00240 024703 002417101212 002427000405 002437020704 002447107405 022457001400 002467020754 002477920700 902507107400 002517106405 002527001400 802537000747 ODD LDA 1 RCONT MOVZL 1 1 52 INC 0 0 MOV 1 1 522 3 LDA 1 RDATA MOVZL 1 1 52 INC 0 8 MOV 1 1 S2R JMP LDA 1 RCONT MOVR 0 0 52 JMP ODD LDA AND JMP JMP 0 14 9 1 SNR 8 3 ERROR LDA AND SUB JMP JMP 0 14 9 1 8 1 SNR 8 3 END 9 96 9 9 00000 PASS 1 ERRORS 49 RECEPTION PARITY CHECK ZERO PARITY COUNTER GET CONTROL BITS BIT SET YES INC PARITY COUNTER FINISHED WORD NO CONTINUE IN LOOP GET DATA WORD BIT IN WORD 2 YES INC PARITY COUNTER FINISHED DATA WORD NO CONTINUE IN LOOP PARITY COUNT LOOP COMPLETED GET CONTROL BITS EVEN OF BITS SET NO CHECK THAT ODD PARITY BITS ARE SET FOR EVEN NONE ARE SET GET PARITY MASK ARE PARITY BITS SET NO TAKE NORMAL RETURN YES TAKE ERROR EXIT GET PARITY ASK AND CONTROL TO PARITY ARE BOTH BITS SET YES TAKE NORMAL RETURN NO TAKE ERROR EXIT 0012 LINK 2 AHEAD AREA AYDCT ERROR ETX EXIT FINIS FLOP HEAD HNDLR IACTR IDACT LOOP MASTE NEXIT ODD PARIT RCONT RDATA RECM SENDM SSEND STX TABLE TRANS WC 14 3 40
31. 7010425 001157000745 50 2 2 52 JMP 2 LDA 2 152 000000 MASTER 25 26 27 28 29 38 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 IFBACK ENDC 00116 024426 001177032413 001207133000 001217020414 001227126000 001237000010 001247063077 001257001000 00126 032404 001277151400 001307151400 001317000770 EXIT FLOP LDA 2 HEAD LDA 2 1 2 2 2SNR JMP NEXIT JMP RECM LDA 1 3 LDA 2 HEAD ADD 1 2 LDA 6 SSEND ADC 1 1 XMT HALT JMP 0 2 LDA 2 HEAD INC 2 2 INC 2 2 JMP EXIT w 9 w 99 we 99 45 T SEND LAST WORD NORMAL CONTROL BITS DECREMENT WORD COUNT NOT AT ZERO AT ZERO GET ETX BITS INCREMENT STORAGE POINTER SEND NEXT WORD MASTER CPU MESSAGE RETURN CHECK GET START OF MESSAGE GET DESTINATION ADDRESS IS IT l1 YES NO RETURN EXPECTED NO RECEIVE MESSAGE AC2 RECEPTION AREA SETUP FOR NORMAL RETURN 3 GET RETURN ADDRESS BUMP BY 3 FOR NORMAL RETURN SENDM EXIT GET ADDRESS OF SENDM SYNC MAKE NON ZERO RELEASE SENDM CONTROL SYSTEM ERROR RETURN TO CALL SETUP FOR ERROR EXIT GET MESSAGE ADDRESS BUMP BY 2 FOR ERROR RETURN LEAVE SENDM 10008 LINK 01 092 03 04 05 06 07
32. ACTR Control Master Slave Message Format iv Page 11 13 1 17 20 29 1 INTRODUCTION The most rapidly growing use of the world s links is for data transmission The most rapidly groving area in the exploding data processing industry is teleprocessing he reason is the versatility that the interlinking of bring plus the potential benefits to the individual of having f this computing power at nis fingertips mhe phenomenal growth of the minicomputer industry in the last decade has been highly influential in tie field of data transuiauion In situations characterized by relatively simple mathe matical operations and substantial data communication and for matting requirements a minicomputer multi processor is often less and far more flexible chan any Single medium to large scale computers capable of meeting all the job requirements A minicomputer multi processor system is usually char amp cterized by large central computer complete with mass storage amp nd hard copy devices which is connected to a number of smaller remote processors The remote systems can control 8 some process or series of processes continually as the central computer stands ready to assume a remote system function in the event of a failure of remote CPU While in this backup node the main computer can be employed on lower priority tasks
33. E CODE ASCII CODE FOR 0 WAS OLD BIT A ZERO MAKE CODE FOR 1 OUTPUT CODE TO TTO GET CODE INTO PROPER POSITION RESTORE CODE ROTATE ACI X LEFT STORE CODE MASK OUT TO 3 BITS MAKE CODE ASC I OUPUT CODE TO TTO FINISHED YET NOT FINISHED RETURN TO CALL 1 12027 ACTR 02321 054433 TRANS 02330 014013 00331 000403 02332 910013 00333 242 09334 0636190 00335 9000412 09336 030425 00337 964610 00340 1471400 003414030423 90342 146414 343 2 4 4 08344 126528 002345 044013 080346 0272414 99347 1242 OUT 00350 040013 02351 0246 15 00352 004717 090353 006000 00354 001135 00355 024011 00356004713 00357 006000 02360001150 00361002401 00362000000 LEAVE 00363 0901771 00364 000003 STA 3 DSZ STOP JMP 152 STOP JMP eLEAVE SKPDN TTI JMP OUT LDA 25 177 DIAC 1 TTI AND 2 1 LDA 25 3 SUBA 2 1 SZR JMP OUT SUBZL 151 STA 1 STOP JMP LEAVE SUB 0 0 STA 9 STOP LDA 1 gt 0 JSR CODE JSR RITER PTI LDA 15TEM2 JSR CODE JSR RITER PT2 JMP LEAVE 177 3 69 Wwe we we 58 OUTPUT TRAN RECEPTION ERRORS STORE RETURN ADDRESS STOP 1 15 PRINT SUPPRESS NO PRINT SUPPRESS YES SUPPRESS OUTPUT PUT STOP 1 AGAIN RETURN TO MAINLINE HAS KEYBOARD BEEN STRUCK NO OUTPUT CODES YES
34. ED SYSTEM ERROR 111 RESTORE AC2 RESTORE AC3 RETURN CONTROL TO SYSTEM AC2 STORAGE AC3 STORAGE COMPATIBILTITY WITH RTOS INTERRUPT SERVICE MASK INTERRUPT SERVICE POINTER RTOS SAVE AREA 10006 LINK 01 02 4 5 6 07 08 09 16 11 12 13 14 15 16 17 18 19 29 21 22 23 24 25 26 27 28 29 38 31 32 33 34 35 4 36 37 38 39 40 41 42 43 44 000477055000 000507020465 000517077777 000527050460 000537151400 000547151400 000557050464 000567025000 200577044466 00060 7014465 000617030456 000627034457 200637035400 002647076040 000657102400 000667151004 000677101400 020707175122 000717101402 000727175004 000737000775 000747024453 000757101222 000767133000 000777071140 001007020433 001017000051 001027024441 001037125004 00104000422 00105 024433 001067147414 000220 000001 001077000407 SENDM LOOP CALL 79 no STA 3 0 2 LDA SSEND 5 INC INC STA LDA STA 055 LDA 2 HEAD 2 2 2 2 2 DATPTR 1 9 2 1 WC WC 2 STX LDA LDA DOB 3 DATPTR 3 0 3 3 ACTR SUB 0 0 MOV 2 2 SZR INC 9 9 140721 3 3 52 INC 0 0 MOV 3 3 S2R JMP 3 LDA 1 14 MOVZR 0 0 52 ADD 1 2 DOAS 2 ACTR LDA TRANSM LDA 1 RCONT MOV 1 1 322 JMP FLOP LDA 1 AND 2 1 SZR MASTER ENDC JMP IFBACK IFE MASTER
35. ED ALL FLAGS AND INTERRUPTS ARE OPERATIONAL NOW PROCEEDING WITH TRANSMISSION TESTS WRITE TEST DESCRIPTIONS NO OF WORDS TO BE TRANSMITTED LOOP COUNTER FOR TRANSMISSION ZERO ERROR COUNTER 1 ZERO ERROR COUNTER 2 STOP IS FOR PRINT SUPPRESS LOAD DATA WORD LOOP COMPLETED NO YES WRITE OUT TRANS STATS LOAD CONTROL WORD LOOP COWPLETED NO YES WRITE OUT TRANS STATS 17 15 A 4 MASK CONTROL WORD 15 4 BITS LONG OUTPUT DATA WORD TO BUFFER OUTPUT CONTROL WORD TO BUFFER HAS DATA BEEN RECEIVED NO READ DATA WORD FROM RECEIVER READ CONTROL BITS FROM RECEIVER SAVE ALL THE ACCUMULATORS DOES REC TRANS DATA YES NO INCREMENT ERROR COUNTER TEMO TEMI TEM2 TEM3 DOES TRAN CONTROL BITS YES NO ERROR 1111111 INCREMENT ERROR COUNTER STOP 1 FOR PRINT SUPPRESS GET ASCII FOR STAR 3 OUTPUT IT ee RESTORE STOP OUTPUT ERROR INFORMATION WRITE INFORMATION 0005 ACTR 00211 0010937 00212 024010 00213004456 00214 006009 00215 001054 00216 0240201 09217904452 00220 0060200 002217001101 0222 8620 0 223 1001125 224 0 3511 00225090177 00226 024035 002271044001 002320626717 00231 014034 00232 000402 00233 000406 0o234 02003T 00235 024034 00236 1606415 60231 126408 02240 065114 30241 060177 AHEAD 242 006017 33243 004400 00244 054417 WRITE 00245 026416 0246
36. ES DATA AND MSKO 15 THE ONTO BUS SAME AS FOR 57278 DATA INPUT AND OUTPUT INF 156 RESPECTIVELY di PUN SON 1 IF PRESENT 052 5 MAXIMUM TIME Vos n 1100 ers FROM LEADING EDGE DATAS 15 rm OF STRT CLR 1150 150 IOPLS TO STATE DATOA DATOB QUTPUT 350 MIN ____ IN SELB STRT CLR xr SELD AND INTR IS OR 408 5 _ 350 MIN _ 250 NS IF PRESENT INPUT 050 5 SKip SELB SELD 050 5 GATE BUSY DONE ONTO SELB SELD LINES PROGRAMMED TRANSFERS IN OUT INSTRUCTIONS MN RQENB 350 MIN DEVICE DONE INT DISABLE pt INTP IN V INTP OUT INTA 500 MIN 250 MAX 200 DATAG 15 en DEVICE 050 5 5 CODE OF THIS te DEVICE CLR H DEVICE NOT DONE DEVICE SETS DONE PROGRAM GETS CODE PROGRAM CLEARS NO INTERRUPT AND REQUESTS OF NEAREST DEVICE DONE AND INT REQ REQUESTED INTERRUPT REQUESTING INTERRUPT PROGRAM INTERRUPT TIMING Figure 7 18 in the two connected interfaces must be tuned to one another by adjusting the appropriate trimpots so as to obtain the ECT data transfer rate possible given the characteristics of the connecting transmiss
37. R In order to operate the ACTR transmitter the program must first sucuri that the device is not currently some operation This is done by testing the Busy flag for a state by SKPBZ ACTR IS BUSY ZERO JMP 1 3NO CONTINUE CHECKING ACTR NOT BUSY Next the control duo words must be loaded into the transmitter buffer The control bits can be used to inform the receiving computer of the nature of the data transfer i e start of mes sage end of message data acknowledgement etc After loading the data into the interface amp Start pulse 8984 be sent to the hardware to begin the actual transmission set Busy to 1 LOAD ACTR BUFFER A WITH DATA FROM ACS LOAD ACTR BUFFER B WITH CONTROL BITS FROM ACD NO 2 0 TRANSFER S SETS BUSY TO 1 BEGIN TRANSMISSION DOA ACS ACTR DOB ACD ACTR NIOS ACTR we we Since the start pulse can be isdded as soon as the hardware buffers are loaded this ET Gb of instructions can be shortened to DOA ACS ACTR DOBS ACD ACTR Once the datum has been sent the transmitter subsection of the ACTR has no way of knowing whether the other computer has received it and strobed the data into the processor i e it is ready to accept more data It is therefore advisable to have the receiving computer send amp data message using its own transmitter When a transmission is received the acis Done is set to 1 The method of asc
38. RT CLOCK ENABLE INTERRUPT RETURN CONTROL TO CLI WRITE MESSAGE ROUTINE LOCATION OF MESS POINTER LOCATION OF MESSAGE STORE IN INCREMENT RETURN ADDRESS CHECK FOR 9 15 THE TERMINATOR OUTPUT THE CHARACTER CHECK FOR OUTPUT CHARACTER INCREMENT POINTER FETCH 2 MORE CHARACTERS SKIP IF TTO NOT BUSY OUTPUT 1 TO TELETYPE RETURN TO MAIN PROGRAM 0006 902171 054431 00212034431 00273 054936 125100 09275 044427 0021716 0244217 00277 1250092 00399 125400 00301 00 4764 00302 24422 00393 125199 00304 04442 00305024417 CODE1 00306 1251009 00307 125190 00319 12510909 00311 944413 00312039414 90313 147406 00314 930411 00315 147090 00316 004747 00317 014036 00320 02027165 003210902401 00322200000 003230000245 00324 000000 00325000060 68326 229297 CODE MORE 5 TEMP 60 17 STA 3 MORE LDA 35 5 STA 3 LOAP MOVL 151 STA 1 LDA 15 60 MOV 1 1 52 INC 1 1 JSR OUTPT LDA 1 TEMP MOVL 151 STA 1 LDA 1 MOVL 151 MOVL 151 MOVL 151 STA 1 LDA 2 AND 2 1 LDA 23 69 ADD 2 1 JSR OUTPT DSZ LOAP JMP CODE JMP MORE 5 60 we we we loo 24 THIS SUBROUTINE PRINTS OUT AC IN OCTAL STORE RETURN ADDRESS INIT LOOP COUNTER ROTATE BIT 0 TO CARRY STOR
39. and T requests for devices which are busy Through the queuing facility RDOS RTOS makes it possible to achieve maximum and continuous overlap of multi tasks without direct intervention by the tasks themselves The handler for the in the master slave environment to these requirements enabling tasks to access the ACTR with minimal pre processing The handler for the ACTR is composed of three sections _a transmission routine SENDM a reception routine RECM and amp n identification and interrupt routine IDACTR These routines exist with only minor differences in both the master and slave processor p The call to the routine SENDM is similar in structure to a RDOS RTOS SYSTEM call as it incorporates both an error and normal return Control of SENDM is allocated on a basis to calling tasks through use of the RDOS RTOS facility of sync 33 3h DESTINATION WORD COUNT MESSAGE ACTUAL MESSAGE ACTR MASTER SLAVE MESSAGE FORMAT Figure 10 35 words Once a task of SENDM through a ine word ett ts exclusive Contrat until all data transmissions re quested by that task are completed A calling task passed SENDM the address of the message to be transmitted This message must be Soret in accord with the format illustrated in Figure IO The actual message transmitted begins with the word count the first two words are for the use of SENDM only and no
40. clock pulse which is used by the receiver in the thes CPU to indicate the data strobe cycle No computer intervention is needed in the receiving system until all 29 bits are received and shifted into place in the receiver buffers For amp cable length of 20 feet full 24 bits can be strobed into the sscelves E T in 8 0 micro seconds With a minimal handler no error checking both processors typical data rates would be approximately 26 kHz for NOVA 1210 and 37 KHz for a ECLIPSE S 200 The MCA is not required in systems with only modest inter communication requirements In such aysteus an interconnection Of processors using an asynchronous interface is simpler and less expensive The MCA cannot be used in systems where the linked processors are not contained in the same frame as the transfer distance for MCA cannot exceed 15 feet The ACTR has able transfer clocks which allow the respective transmitter and receiver to be tuned to allow for the type and length of trans nission line between them The MCA achieves its Buch Sea pay transfer rate by eapleyine sufficient lines to move whole words at a time and provide all control signals The ACTR on the other hand requires only cables and employs line drivers and receivers on each cable to increase the transmission range far beyond the limit of the MCA since clock pulses are transmitted with each datum bit synchronization between the two computer sys
41. ded that the bit in the interrupt seta es mask bit 8 corresponds to the priority level of the device is 0 If the mask bit is 1 the ACTR can set its Done o 1 but does not place an interrupt request on the interrupt request line If the Interrupt On f amp agis 1 at the time the processor completes execution of any instruction the processor honours any requests on the interrupt request line If the Interrupt 2 On flag is the CPU does not look at the interrupt request line it Just continues to the next sequential instruction The CPU honours an interrupt request by setting phe iterat On flag to O so that no interrupts can interrupt the first part of the interrupt service routine The CPU then places the up dated program counter into physical memory location and executes a JMP 1 instruction It is assumed that physical location 1 contains the address either direct or indirect of the in terrupt service routine Once the CPU has transferred kontrai to the interrupt service routine it is up to that routine to save any akora that will be used save the carry bit if it will be used deter mine which device requested the interrupt amp nd then service the interrupt The determination of which device needs service can be done by 0 SKP instructions or the routine can use the INTERRUPT ACKNOWLEDGE instruction The INTERRUPT ACKNOWLEDGE instruction INTA returns the 6 bit code of the device requesting
42. e message after it has been completely assembled in the core After control is returned from this post reception processing the ACTR task awaits the next message The message handling routines called from RECM in the slave CPU may 11 SENDM to return message io master com puter or introduce changes in the control functions of the slave CPU The action taken by these called is left completely up to the user For the ACTR handlers RECM and SENDM to propsudy it is necessary that an interrupt handler for the ACTR be included in the interrupt dispatch table of RTOS RDOS his can be done itket at SYSGEN or during the execution program Any device that issues an interrupt that is not included in the dispatch table will have its interrupt cleared with a resulting loss of information The routine IDACTR links the ACTR interrupt handler IACTR into the RTOS RDOS interrupt structure through use of a run time system call It then releases control of the SENDM syne word io the dy Locking BENDM the devica identifisation is completed the users of the are assured that information _ vill be lost during system initialization P As was mentioned before SENDM RECM vary slightly between the master and slave computers Through use of the cap abilities of the DG MACRO Assembler one source file be to include both the master and slave version
43. ertaining this condition will be dealt with in some length shortly but for now let us assume that we know that a reception has been completed The A buffer of the receiver data word must be loaded into an as well the B buffer control pits The Done flag also must be put to by a clear pulse 23 DIA ACS READ DATA WORD INTO ACS DIBC ACD ACTR READ CONTROL BITS INTO ACD 3 CLEAR DONE FLAG Once the ACTR has completed the reception of word 20 bits it sets Done to 1 The program can determine this Gomes dition in one of two ways using the 1 0 SKP instruction the program can test the condition of the Done flag SKPDN ACTR IS DONE 17 JMP 1 I 3NO CONTINUE TO WAIT YES MESSAGE RECEIVED Another way is to utilize the intereunt system that is standard on the NOVA ECLIPSE computer The interrupt system is made up of an interrupt request line to which each 1 0 device is con nected an Interrupt On flag in the CPU and a 16 bit interrupt priority mask The Interrupt On flag controls the status of the interrupt system If the flag is set to 1 the CPU will respond to and process interrupts If the flag is set to f the CPU will not respond to any interrupts An interrupt request is initiated by an I O device when it completes its operation When the ACTR completes message r c ntion as well as setting Done it also places interrupt request on the interrupt request line provi
44. ever occur In this 688 the master computer would always initiate communication between tis two processors The slave system would only transmit to fulfill requests from the master The task facilities of RDOS RTOS allows one task to be dedicated to servicing the ACTR in the slave CPU This task would gain CPU control only when the receiver generates an Once the message reception is completed this t amp sk would determine what further action has to be taken Appendix A of this report vill deal with the of napa for the in a multi tasking casi gas for master slave system DIB DOA DOB NIO SKP INTA ac MSKO ac IORST 29 ACTR COMMAND ACTR read receiver control bits read receiver data word lt f gt send data word to transmitter f ACTR send control bits to transmitter 1 0 transfer lt t skip 1744715 true BN tests for Busy 1 BZ tests for Busy 0 DN tests for Done 1 DZ tests for Done 0 C will clear Done and clear ACTR interrupt request S will set Busy and begin transmission CENTRAL PROCESSOR FUNCTIONS will return 46 to specified accumulator if the is the nearest device to the processor requesting amp n interrupt will prevent the ACTR from generating an interrupt if bit 8 is set in the specified accumulator will clear the Done and Busy of
45. handling the ACTR in multi tasking environment under the Data General operating systems RDOS RTOS will also be developed ACKNOWLEDGEMENTS The author would first like to thank my supervisors Dr T J Kennett for giving me a sound base in uiuicoup ter theory and operation and the confidence to continue on in this line into the industrial world I would also like to acknowledge the assis tance of Gord Cormick and Kenrick Chin who combined to teach me a great deal about the practical side of minicomputers and digital elettronici Special thanks are due to Litton Systems Canada Limited for the use of their ECLIPSE 200 computer system in the 46551865 ment of some of the software presented in this report Finally I M like to extend my appreciation to the Engineering Physics Department of McMaster University for both accepting me graduate student and providing me with very challenging and rewarding course of study di TABLE OF CONTENTS ABSTRACT ACKNOWLEDGEMENTS TABLE OF CONTENTS LIST OF FIGURES CHAPTER 1 INTRODUCTION 2 THEORY OF OPERATION 3 PROGRAMMING THE CONCLUSIONS APPENDIX ACTR MASTER SLAVE HANDLING ROUTINES APPENDIX B ACTR DIAGNOSTICS BIBLIOGRAPHY Page di iii iv 19 31 51 65 LIST OF FIGURES ACTR Transmitter ACTR Receiver ACTR Device Flags transmitted Pulse Clocking Receiver Clocking Interrupt Timing 1 0 Format
46. hift the next bit into position to be transmitted The rising edge of the ransmitter Clock generates the Data Width pulse This pulse is ANDed with the datum bit to be sent to produce a pulse of a specified width This pulse 15 then com bined with the clock pulse and placed Transmission line Figure 4 details the actual pulse that is transmitted Due to 1 us 1 15 Ls clock data clock data Times shown are characteristic of a 0 ft co axial cable Negative clock pulse 18 sent for greater noise immunity TRANSMITTED PULSE Figure 4 12 the manner in which the incoming information is clocked into the receiver buffer the Data Width must be at least a factor of two longer than the Transmitter Clock The falling edge of the data width pulse increments a counter network which is responsible for terminating the clocking cycle at the end of the transmission When the counter reaches 26 the Busy flag is clocked over to When Busy is in the state the Transmitter Clock pulse cannot be generated the falling edge of the Data Separation pulse and the clocking se quence is halted The counter is zeroed at the start of each transmission by the STRT pulse The complete sequence for the transmitter is outlined in Figure 5 The receiver is activated on the falling edge of the incoming datum pulse the negative of the Transmitter clock This edge triggers the Data Seek and Reception Completion clock
47. ion and the latency of the interface elements The next chapter will deal with the software aspects of data transfer with the ACTR The 1 0 structure of the NOVA minicomputers will be reviewed with special attention to the pros gram of ACTR 3 PROGRAMMING The software control of the is very straight for ward but to be able to use this device effectively iHa 1 0 handling facilities of the NOVA ECLIPSE must be well understood This chapter will be devoted to a detailed description of the pro gramming concepts of the 1 0 system with specific references to the handling of the ACTR In order for the processor to perform useful work for the user there must be some method for the program to transfer information outside the machine The input output 1 0 instruction set provides this facility There are eight 1 0 instructions which allow the program to communicate with 1 0 devices control the 1 0 interrupt system control certain processor options and to perform certain processor functions The NOVA ECLIPSE line has 6 bit device selection network corresponding to bits 10 15 in the I O instruction format Each device is connected to this network such a way that it will only respond to commands with its own device code Each device also has two flags Busy and Done which control its In conventional DG devices und
48. k k k k k K k K k k k k k k k k k k k RE K k k k k k k eee eee WH WE 99 10203 LINK 01 02 03 04 85 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 AL Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k e k e S 04 CALLING SEQUENCE SENDM AC2 START OF MESSAGE HEADER CALL JSR 8 41 SENDM ERROR RETURN NORMAL RETURN RETURN NONE ALL ACCUMULATORS AND CARRY DESTROYED S INN NO ACCUMULATORS PASSED CALL JSR 1 IDACTR RETURN NONE ALL ACCUMULATORS AND CARRY DESTROYED IDACTR anna ACTR CREATED AS ACTR RECEPTION TASK IN SLAVE CPU K Kk K K X k k k k k k k k k k k k k k k k k k k k k e dee k k e ee de dee R ee dede k k K k ede e ke ke 30004 LINK 01 92 3 4 5 06 97 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 39 31 32 33 34 35 36 37 38 39 40 41 42 000001 000040 006401 000001 42 Kk k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k
49. nization is not a problem The slower speed of the ACTR when compared with the MCA is out weighed in many applications by its increased range and error checking capabilities The reliability of the ACTR hardware is such that its transfer rate can be safely saa by the elimination of all error checking The user should however use the ACTR diagnostic in APPENDIX B to ensure that the hardware transfer clocks are not marginelly adjusted Minicomputer multiprocessor systems UH ac those based on Data General NOVA and ECLIPSE processors represent one of the most rapidly growing areas in computer development Their 5522 32 inherent versatility and sizable computer power make them an ideal medium for real time instrumentation control and simulation systems With the reliance these systems place on shared processor resources data transfer devices such as the will continue to be an important system compound APPENDIX A ACTR MASTER SLAVE HANDLING ROUTINES An important function of any real time operating system is the efficient handling of input output Operations Optimum usage of machine devices and central processor time in the ac E of tasks is the real reason for designing sad dapianenting multi tasking system The responsibility of RDOS RTOS 1 0 control is to react during program execution to the structuring I O re quests making assignment of requests to machine devices when they are idle
50. part of the reception task ACTR which is responsible for all receptions and transmission in that processor RECM awaits each incoming data transmission by a REC to a syne word This sync word is activated by an IXMT from the ACTR interrupt handler upon the reception of data into the re ceiver buffers Once RECM is unsuspended b parity check is performed on the incoming data If a parity error is detected in the received words an error message is returned to the trans mitting computer in the data acknowledgement If no ae detected the received data is stored successful reception is signalled In the CRU the Zure area for the reception of data from the slave is in the DESTINATION word of the message that initiated the response from the slave Once the entire message is received control of the ACTR is returned to the system and the normal return is taken from 1 the event of amp reception error ACTR control is relinquished and the error return is The slave CPU uses RECM as part of the ACTR service task The system initializer is responsible for tasking off this mon itoring task entry point ACTR No other task in the v CPU is allowed any access to the ACTR The the received message number to determine the core area that is to be used to 37 store the incoming transmission This message number also de termines which subroutine is to be called to handle th
51. s The Data Seek pulse must remain high for more than half the length of the Data Width of the transmitting The Data Seek is used to indicate when the actual transmitted datum is incoming i e when the clocking signal that begins each transmission is completed The falling edge of the Data Seeks generates the Receiver Clock Pulse which actually shifts the incoming datum bit into the receiver buffer The Reception Completion clock is incoming transmission This clock is set to fall in a time that corresponds to approximately 1 times the period GP 1 bit transmission Each incoming data transmission will re trigger this clock put the clock cycle back to the beginning PULSE STRETCHER 1 DATA BIT TRANSMITTER CLOCKING Figure 5 14 INCOMING DATA TRAIN RECEPTION COMPLETION DATA SEEK RECEIVER CLOCK Data clocked into buffers on negative edge of receiver clock RECEIVER CLOCKING Figure 6 15 that the Reception Completion clock will not fall until the transmission of all 20 bits is completed The entire clocking sequence of the receiver is illustrated in Figure 6 The clocking times shown in Figures 1 and 2 are repre sentitive of system with a cable length of 20 feet These times will vary witn the length type of used to connect the P However they do give a base point at which to start tuning ACTR pair When
52. s RDOS and RTOS Chapter serves as a summary of ACTR and its place in data between Data General minicomputers Appendix is hanaling routine for the in master slave multi tasking Appendix B is hardware diagnostic for the ACTR CHAPTER 2 THEORY OF OPERATION The ACTR is an asynchronous self clocking data link that conforms to Standard General interface logic in all but its use of the Busy and Done flags The ACTR Done flag is used to indicate the state of the receiver section while tlie Busy flag reflects the current condition of the transmitter The ACTR is attached to the I O bus of the computer and is nected to the ACTR of the other computer by dual transmission lines Although mounted single circuit board con tains independent receiver and transmitter and receiver subsections The complete ACTR assembly is shown in Figures 1 3 Each data word is sent under program control complete transmission consists of the transfer of 20 bits 16 data bits DG word sand control bits transmission status bits for pro gram use After data bits strobed into the transmitter the data transfer is initiated by setting the Busy flag After the transmitter has sent all 20 Vita it clears the Busy flag The subsection cannot iutersups when it has its operation Accompanying each trans mitted bit is amp
53. s The assembly of 38 the respective relocatable binary files is controlled by an equate switch MASTER When the switch MASTER 1 the master CPU version is assembled and when MASTER 0 ino code is gen erated This switch must be defined in an equate file which proceeds the handler source file INTERLINK in the MAC string version of the handler presented in this Appendix is that appropriate to the slave CPU Those parts of the source file that applied only to the master computer are listed but have not generated any code 6 9 0001 LINK MACRO REV 04 09 09 21 06 02 27 77 39 kkxkkkkxkkkkkkkkkkkkkkkkkkkkkkxkkkkkkkkkkkkxkxkxkxkkkkxkkk 01 TITLE TITL LINK HANDLER 02 IDENTIFICATION INTERLINK 5 PURPOSE THIS PROGRAM SUPPLIES TRANSMISSION AND ROUTINES ACTR AUTHOR MICHAEL BRETT ORIGINAL ISSUE DATE 1 2 71 ISSUE 1 DATE OF ISSUE 1 2 77 amp k k k k k k k k k k k k k k k k k k k k k k k t k k k k k k e dece R R ehe R e R R RO o 10002 LINK 0 4 02 03 04 85 6 7 8 09 19 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 48 41 42 43 44 45 46 40 K K k k k k k k k k k k k k k kk
54. s generated The ACTR will receive this if INT REQ flip flop is set device closer to the processor on the bus the INTP must be terminated at the first device where the INT REQ 48 Set second signal INTA is erated at a tine sufficiently long afterwards to ensure that the INTP signal has been terminated The INTA signal is used by the device which terminated the INTP to clock its device code onto data lines 10 15 of the I O bus This data is strobed into the processor at the end of the INTA The timing of the logic signals that control the interrupt sequence is outlined in Figure T Once execution of the INTA instruction is completed the device code received can be used to vector control to the ap routine to service the interrupt The interrupt service routine for the ACTR must strobe the received data into the processor by issuing DATIA data word and DATIB control bits signal over the 1 0 Bus The interrupt handler must clear Done by issuing CLR signal so that the ACTR will not immediately request anothef interrupt for the same reception when the interrupt system is turned on and Interrupt Disable is Clearing Done also clears INT REQ disabling INTR The timing of the various clocks in the ACTR is controlled by resistor trimpot capacitor pairs The clocking systems 17 050 5 DATIA DATIB 08 DATIC PTT TIMING FOR INTA DATAQ 15 DATI GAT
55. t lt 12 gt ACTR INTERRUPT GENERATED lt 15 gt lt 12 gt TXT NON TERMINATION OF TRANSMISSION BUSY 1 lt 15 gt lt 12 gt TXT HOWEVER TRANSMISSION TERMINATED DONE 1 lt 15 gt lt 12 gt TXT TRANSFER INFORMATION 15 12 TXT CONTROL WORDS TRANSFERRED INCORRECTLY lt 15 gt lt 12 gt TXT WORDS TRANSFERRED INCORRECTLY lt 15 gt lt 12 gt TXT END OF lt 15 gt lt 12 gt WAS TRANSMITTED AND WAS RECEIVED 15 12 TXT ACTR INTERRUPT NOT CLEARED BY IORST lt 15 gt lt 12 gt x TXT MASK OUT FALLURE lt 15 gt lt 12 gt FLAGS AND INTERRUPT OPERATIONAL lt 15 gt lt 12 gt NOW PROCEEDING WITH TRANSMISSION TESTS lt 15 gt lt 12 gt TERMINATE LISTING OF ERROR WORDS lt 15 gt lt 12 gt TYPE CONTROL C lt 15 gt lt 12 gt lt 12 gt NOLOC 0 19811 ACTR 02 03 04 20200 000244 RI TER 900001 000222 END 00002 600000 TAGI 00003 000000 TAG2 00004 0000002 TAGS 000905 000000 TAG g20006 000200 200 0000901 000090 00010 0020000 90011 000317T 371 00012 000000 STRPTR 00013 000000 STOP 00014 000017 17 00015 0000009 00016 000000 TEMI 00017 000000 TEM2 00020 000000 00021 090052 STAR 02022 000365 INTPTR 002023 2990211 CODER 00024 000014 14 00025 000040 40 00026 000000 HOLD 027 077777 NO 00030 200061
56. t included 18 the word count The control bits which accompany each transmitted data vord are used to indicate the start of a transmission end of trans mission and the parity of the transmitted data The control bits are generated by SENDM and are not passed beyond the routines After each data is transmitted the SENDM routine goes into task suspension awaiting the reception of the data amp cknowledgement from the receiving Once the reception acknowledgement is received it is checked for amp data error message data error is confirmed the transmission is terminated ACTR control is released the error return is taken from SENDM If task in the master CPU that calls SENDM expects amp return message from the slave CPU the DESTINATION word in the message that it passes to SENDM must contain the address for the reception of the incoming data If no expected this word must be set to 1 When SENDM has sole ced transmitting its message ine DESTINATION is checked for amp valid address If it is found control is passed to RECM the reception handler otherwise the control of SENDM is released to the system and the 36 anormal return is taken back to the calling task The reception routine RECM is not disectiy acceuat ls to the user is called by SENDM in the master CPU if return is expected from the slave CPU In the slave CPU is
57. tems is not a problem AS the distance between the processors the greater the chance of reception errors occuring The four control bits Of the ACTR can be used to sap parity checks as well as STX start of text and ETX end of text capabilities to the user The major use of the ACTR is for data transmission in systems where time is not a crucial factor or where the inter connected processors are too remote to use the faster MCA Such system could consist of remote processor controlling Multi channel Periodically an energy NS would be transferred from the remote CPU iod central with mass storage capabilities moving or fixed head disc magnetic tape tape etc This transfer of data would take place the times that the remote System was not actively involved in amp mon itoring activity so that no new information is lost The central processor could handle number of such remote systems and provide amp n economical means of recording information by eliminating the need for storage facilities on each remote system Chapter 2 of this report will deal with the hardware aspects of the ACTR by outlining the clocking sequences of the transmitter and the receiver and the interface of the ACTR to the computer 1 0 hardware In chapter 3 I will be discussing the software control of the ACTR the linkage of the ACTR into the Dat amp General Operating System
58. the ACTR and the Interrupt Disable flag equivalent of MSKO with 8 0 The Interrupt Request of the ACTR will also be cleared CONTROL SUMMARY Figure 9 In summary the logically out of the DG commands allow complete the interrupt structure 30 control logic for the ACTR arises quite I O structure small number of I o control of the ACTR and its link into and the general control store of the central processor Figure 9 contains a brief resume of the dedicated instructions that control the ACTR and the central processor functions that influence the ACTR part of their general operation CHAPTER 4 CONCLUSIONS The transfer of usable information between any computer ie amp lways amp complex undertaking the information must be put into a format that the other processor can accept and act on the integrity of the transferred information must be ensured SS the systems must be accomplished so that data is not lost between the systems and data must be moved between the as quickly as possible The ACTR can fulfill the above requirenents used in the proper operating environment The ACTR master slave handler will transmit by the user and perform parity checking on all received information Since data is completely assembled in the ACTR receiver before it is read in and data acknowledgements are nec ssary processor processor synchro
59. the interrupt If more than one device is requesting service the code returned is the code of that device requesting an interrupt which 28 physically closest to the CPU on the 0 bus After servicing the devices the inter rupt routine should restore all saved values set the Interrupt On flag to 1 and return to the interrupted yo instruction that sets the Interrupt On flag to 1 interrupt Enable allows the processor to execute one more instruction if the Interrupt Enable instruction changed the condition of the on flag before the next interrupt can take place In order to prevent the interrupt service youtin from locking itself inta 25 loop this next instruction should be the instruction that returns control to the interrupted program Since the pasta value of the counter was placed in location by the CPU before honouring the the interrupt routine has to do after restoring the AC s and the carry bit is to execute an INTERRUPT ENABLE instruction and a JMP 8 f instruction and control will be returned to the interrupted program If the Interrupt On flag remains 0 the interrupt service routine the interrupt routine cannot be interrupted and there is only 1 level of device priority This level is deter mined by either the order in which the I O SKP instructions are issued or if the INTERRUPT ACKNOWLEDGE is used by the physical location of the devices on the bus
60. uity during interrupts and implementing a multi level interrupt TEET RDOS RTOS is very useful in handling two problems which arise as a result of design constraints of the IN a multi tasking environment there will be competition fos system resources the ACTR among many others A task cur rently using the ACTR must be assured that no other routine will also attempt to initiate a data transfer The RDOS RTOS facility of sync words in amp multi tasking environment allows a to gain exclusive control of the hardware and software maintain control until it has finished its transmission end any accompanying receptions control would always be allocated on a priority basis and any requests for the ACTR that are issued while it is in use would be queued until the ACTR beeame free When using the ACTR the transmitting computer must await an acknowledgement of reception before sending more data If both systems in the ACTR begin to transmit simultaneously data could easily be lost when the ACTR receiver routines mistake incoming data for an acknowledgement of the data it has sent 28 The user must design the ACTR handlers to be able to accommodate occurence of this kind or so design the system configuration to the possibility of the two CPU s attempting to transmit simultaneously In master slave environment the competition for the ACTR hardware between systems can n
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