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Rabbit ® 4000 Microprocessor User`s Manual

1. Bit s Value Description 76 00 Disable Quadrature Decoder 2 inputs Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement 01 Quadrature Decoder 2 inputs from Parallel Port D bits 3 2 10 Quadrature Decoder 2 inputs from Parallel Port E bits 3 and 2 11 Quadrature Decoder 2 inputs from Parallel Port E bits 7 and 6 5 0 Eight bit quadrature decoder counters both channels 1 Ten bit quadrature decoder counters both channels 4 This bit is reserved and should be written as zero 32 00 Disable Quadrature Decoder 1 inputs Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement 01 Quadrature Decoder 1 inputs from Parallel Port bits 1 and 0 10 Quadrature Decoder 1 inputs from Parallel Port E bits 1 and 0 11 Quadrature Decoder 1 inputs from Parallel Port E bits 5 and 4 1 0 00 Quadrature Decoder interrupts are disabled 01 Quadrature Decoder interrupt use Interrupt Priority 1 10 Quadrature Decoder interrupt use Interrupt Priority 2 11 Quadrature Decoder interrupt use Interrupt Priority 3 Quad Decode Count Register QDC1R Address 0x0094 QDC2R Address 0x0096 Bit s Value Description 7 0 read The current value of bits 7 0 of the Quadrature Decoder counter is reported Quad Decode Count High Register QDC1HR Address 0x0095 QDC2HR Address 0x0097
2. D1LAOR Address 0x019C D2LAOR Address 0x01AC D3LAOR Address 0x01BC D4LAOR Address 0x01CC D5LAOR Address 0x01DC D6LAOR Address 0x01EC D7LAOR Address 0x01FC Bit s Value Description 7 0 Bits 7 0 of the link address are stored in this register DMA y Link Addr 15 8 Register DOLA1R Address 0x018D D1LA1R Address 0x019D D2LA1R Address 0x01 AD D3LA1R Address 0x01BD D4LA1R Address 0x01CD D5LA1R Address 0x01DD D6LA1R Address 0x01ED D7LA1R Address 0x01FD Bit s Value Description 7 0 Bits 15 8 of the link address are stored in this register DMA y Link Addr 23 16 Register DOLA2R Address 0x018E D1LA2R Address 0x019E D2LA2R Address 0x01AE D3LA2R Address 0x01BE D4LA2R Address 0x01CE D5LA2R Address 0x01DE D6LA2R Address 0x01EE D7LA2R Address 0x01FE Bit s Value Description 7 0 Bits 23 16 of the link address are stored in this register 200 Rabbit 4000 Microprocessor User s Manual 20 10BASE T ETHERNET 20 1 Overview Network Port A implements all of the required digital elements of the 10Base T standard and is normally used with two channels of the DMA controller The receiver provides 32 bytes of buffering and the transmitter has 16 bytes of buffering Network Port A connects externally through six dedicated pins The network port can operate in either hal
3. 100 12 23 Other Register si ea re 101 12 24 e A a e 101 IPAE mL Em 101 12 4 Register Descriptions teo et P E EROR EGER E RERO ER 102 Chapter 13 Timer A 107 T3 T OVeEVIe Was KA O pe sic ee cuo 107 I3 ET Block Di gtram eet c Oe EU IPS 109 13 1 2 Registers iet L 110 13 2 Dependencies i ette tert er e Eve ee PU Qn eee ves usta 110 13 22 o A Ae MAL A ce toos i M t e ME 110 13 22 C ffe KS rere Le ode odio ee aL Ee o 110 13 25 Other erret quee ere ipu IV cure pet E ee Yee 110 13 2 4 Interr pts ia REO AND EO AFTER rep ahaa FR RE Rer 111 13 3 Operatioti ct 111 13 3 1 Handling Interrupts 15 nettes eiae ree Dr pre ui 111 13 3 2 Example IS Ro se iier ertet teh Re eripere aee te Hxc te PO RTI 111 13 4 Register Descriptions Dee eee a e e e ree 112 Chapter 14 Timer B 115 QVELVIE Ws iss i 115 14 1 1 Block Diagram 5 et ern e E ERE 115 UL o M D EXE 116 14 2 Dependencies 116 4 2 1 I O Pins uet TA i Ee ge B 116 14 222 ClOCKS ie eene TM A 116 14 2 3 Other Registers e oet 116 14 24 Intertupts eet SPERO nOD OD ea pr ha ote E eet ote 116
4. M 1 272 26 2 Operation oi E bois a EBORE 273 26 2 Unused Pins ote toi e ere prete Haeret dee le geben eunte e tne 273 26 22 Clock R tes erroe eene eee 273 26 2 3 Short Chip Select erdt re e RR UO PA E EORR 274 26 2 4 Self Timed Chip Selects roiie ttti e sehen teca eei 279 26 3 Register Descriptions oue omoi qim PoR kE EE 280 Chapter 27 System User Mode 283 27 OVervIe W 5 eta aeta AGATA AOS n ete hei o teer tied 283 PIANI T MIA 284 27 25 ee EROR a pe erae Ot e ardere 285 27 2 1 Bi e deme 285 27 22 Clocks sed Ae Ssh Riel RT Bn an dea aise etie ep netos pen 285 2722 3 Other Registers 285 27 2 4 Intetr pts 1 caet i eti ge er ab Pedir ime T 286 27 3 Opet tion epit a E ie Hp 287 27 31 Memory Protection Only a b mte 287 27 3 2 Mixed System User Mode Operation nennen eene enne 288 27 3 3 Complete Operating System nere ptt e RE iE 288 27 3 4 Enabling the System User Mode essere ener nennen nennen nen 289 27 3 5 System User Mode Instructions 0 mem nnenenenennnnennenznnnnnnnznnanznznnzsn nr eiT ri eene 290 27 3 6 System Mode Violation Interrupt
5. HDLC Mode Only SFSR Address 0x00DB Bit s Value Description 7 0 The receive data register is empty 1 There is a byte in the receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 6 4 00 The byte in the receive buffer is data 01 The byte the receive buffer was followed by an abort 10 The byte in the receive buffer is the last in the frame with valid CRC 11 The byte in the receive buffer is the last in the frame with a CRC error 5 0 The receive buffer was not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 3 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer unless the byte is marked as 1 Pu i the last in the frame Transmit interrupts are cleared when the transmit buffer is written or when any value which will be ignored is written to this register 2 00 Transmit interrupt due to buffer empty condition Transmitter finished sending CRC An interrupt is generated at the end of the 01 CRC transmission Data written in response to this interrupt will cause only one flag to be transmitted between frames and no interrupt will be generated by this flag 10 Transmitter finished sending an abort An interrupt is generated at the end of an abort transmiss
6. Offset 0x0000 0x0100 0x00 Periodic Interrupt 0 10 Secondary Watchdog 0x20 RST 10 0x30 RST 18 0x40 RST20 0x50 RST 28 0x60 Syscall instruction 0x70 RST 38 PWM 0x80 Slave Port Sys User Mode Violation 0x90 Write Protect Violation Quadrature Decoder OxAO Timer A Input Capture OxBO Timer B Stack Limit Violation 0xCO Serial Port A Serial Port E OxDO Serial Port B Serial Port F OxEO Serial Port C Network Port A OxFO Serial Port D Timer C 66 Rabbit 4000 Microprocessor User s Manual Table 6 2 shows the structure of the external interrupt vector table Each interrupt vector falls on a 16 byte boundary inside the table Table 6 2 External Interrupt Vector Table Structure Offset 0x0000 0x00 External Interrupt 0 0x10 External Interrupt 1 0x20 0x30 0 40 Breakpoints 0x50 0 60 0x70 0 80 DMA Channel 0 0x90 DMA Channel 1 0 DMA Channel 2 0 0 DMA Channel 3 OxCO DMA Channel 4 OxDO DMA Channel 5 OxEO DMA Channel 6 OxFO DMA Channel 7 There is a priority among interrupts if multiple requests are pending as shown in Table 6 3 Interrupts marked as cleared automatically have their requests cleared when the inter rupt is first handled Chapter 6 Interrupts 67 Table 6 3 Interrupt Priorities Priority Interrupt Source Action Required to Clear the In
7. 119 Global Control Status 22220 296 TBCR eines 118 Register 20 QDER ese 237 TBESR 2s 118 Global Output Control 236 TBEXR 119 Register 23 QDEXHR 237 TBMXR 119 Network Port A Control QDCXR 237 TBSLXR 2 119 Register 24 QDUER 296 5 119 DMA channels 176 RAMSR 58 TBUER nm 297 DMA Master Auto Load RTEER stent ies 37 TCBAR 5 127 Register 187 RICKR A iuis 37 TEBER iii ke er 128 DMA Master Control RTUER ii me 294 TCCR oe 126 Register 188 SAUER nee 298 TEESR 126 DMA Master Control Status SBUER 298 TCDHR 126 Register 187 SCUER nen 298 TEDER 126 DMA Master Halt Register SDUER 2 298 TCRxHR 187 SEGSIZ eet 55 TERXER nme 127 DMA Master Request 0 SEUER eene 298 TCSxHR 127 Control Register 190 SFUER eee 299 TESXER sissa 127 DMA Master Request 1 SPCR 29 75 80 171 256 TCUER 12000000020 297 Control Register 191 170 VRAMO0 VRAMIF 40 DMA Master Timing SPSR seems 170 WDTCR 37 Control Register 189 SPUER 2
8. Timer C Divider Low Register TCDLR Address 0x0502 Bit s Value Description 7 0 The eight LSBs of the divider limit value for Timer C are stored Timer C Divider High Register TCDHR Address 0x0503 Bit s Value Description 7 0 The eight MSBs of the divider limit value for Timer C are stored 126 Rabbit 4000 Microprocessor User s Manual Timer Set x Low Register TCSOLR Address 0x0508 TCS1LR Address 0x050C TCS2LR Address 0x0518 TCS3LR Address 0x051C Bit s Value Description 7 0 Eight LSBs of the match value to set Timer C Output x Timer C Set x High Register TCSOHR Address 0x0509 TCS1HR Address 0x050D TCS2HR Address 0x0519 TCS3HR Address 0x051D Bit s Value Description 7 0 Eight MSBs of the match value to set Timer C Output x Timer Reset x Low Register TCROLR Address 0x050A TCR1LR Address 0x050E TCR2LR Address 0x051A TCR3LR Address 0x051E Bit s Value Description 7 0 Eight LSBs of the match value to reset Timer C Output x Timer C Reset x High Register TCROHR Address 0x050B TCR1HR Address 0x050F TCR2HR Address 0x051B TCR3HR Address 0x051F Bit s Value Description 7 0 Eight MSBs of the match value to reset Timer C Output x Timer C Block Access Register TCBAR Add
9. Of Os O gt gt VDDINT VSSINT VDDIO VSSIO O PB3 l Q o Og O8 O e e n gt O Of O8 Os Os Os gt T Q8 O8 OF O8 Os O8 O2 OF O LU TA a e N Og O O8 Oz Ox O2 Q gt gt gt gt O8 O O2 Os OO gt gt o AUL gt X gt PCO 1 2 VSSINT PC4 PC3 PCS VSSIO VDDIO PD1 PDO PC7 PC6 PD4 PD3 PD2 VDDIO PD7 PD5 VBAT O O OUD 0 OO G 0 X 5 SMODEO VBATIO VSSIO OO OO G CT CO O VDDIO BUFEN VSSIO CLK32K JIOWR WDTOUT RESET RESOUT PD6 NORD SMODET 51 PE2 PEO Figure 29 4 Ball Grid Array Pinout Looking Through the Top of Package Rabbit 4000 Microprocessor User s Manual 324 29 2 2 Mechanical Dimensions and Land Pattern TOP VIEW BOTTOM VIEW 7 8 9 10 11 10 00 0 05 OO0O000 0 0 000 0 Oj Rc gt B D E F G H j K L M 10 00 0 05 Ball Pitch 0 80 mm Ball Diameter 0 3 mm 0 25 0 35 1 20 max Figure 29 5 BGA Package Outline Chapter 29 Package Specifications and Pinout
10. bubes sends ee tote Fort 235 22 4 Register Descriptions Tr 236 Chapter 23 Pulse Width Modulator 239 23 OVetVIEW i RR pen RE e perpe e ee ME 239 23 1 1 Block nei 241 23 1 2 Registers iO p PEE Fee RR erit quee 241 232 e 242 232 1 A a 242 DB DD CLOCKS ite E RU a i p o DRE emt PES 242 23 2 3 Other Registers 2t es e EU Ur ERE pa a 242 23 24 Interr pts ectetuer eee RI UI Satta teeth geen ah eR IER E 242 23 3 sere p estre esteem qe 243 23 5 Handling 22 243 23 32 Bxample ISR OO 243 23 4 Register Descriptions erp eee genere ede tette eredibus 244 Chapter 24 External I O Control 247 24 T Overview xc mte EPI MERE aU EE 247 24 1 1 Auxiliary VO Bus re e Pr 247 24 12 LO Strobes cu a a e a 248 2413 Handshake 90 3 anes asi Ep ete pho ate te Pere EO eed io 249 24 1 4 Block or eer trt tei ente eie tide eene tees 250 24 1 5 RegiStetS 5c tL tenen eese epi ERO 250 24 2 Dependencies rte eee e e rp JADATTA Ib Ie 251 24 2 l VO eb aeree edi dete et at e Ag eh She 251 24 22 CLOCKS sis tin a RD RODEO URDU URP dr
11. Timer Count LSB TBCLR Address 0x00BF Bit s Value Description 7 0 read The current value of the eight LSBs of the Timer B counter are reported Global Control Status Register GCSR Address 0x0000 Bit s Value Description 4 2 000 Processor clock from the main clock divided by eight Peripheral clock from the main clock divided by eight 001 Processor clock from the main clock divided by eight Peripheral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Processor clock from the 32 kHz clock optionally divided via GPSCR Peripheral clock from the 32 kHz clock optionally divided via GPSCR Processor clock from the 32 kHz clock optionally divided via GPSCR 101 Peripheral clock from the 32 kHz clock optionally divided via GPSCR The fast clock is disabled 110 Processor clock from the main clock divided by four Peripheral clock from the main clock divided by four 111 Processor clock from the main clock divided by six Peripheral clock from the main clock divided by six 120 Rabbit 4000 Microprocessor User s Manual 15 15 1 Overview The Timer peripheral is 16 bit up counter clocked by the peripheral clock divided by 2 b
12. 222 223 Timer B 117 physical and logical memory example ISR 223 example ISR MM 117 mapping 42 load parallel port output regis Timer C 124 125 register descriptions 53 ters ssa e a eu 220 125 registers 44 45 46 measure pulse widths memory protection 22 340 Rabbit 4000 Microprocessor User s Manual Parallel Port 81 pltiQUE ps een en 327 alternate input functions 81 BGA package 324 Network Port 201 alternate output functions 81 LQFP package 321 block diagram 203 block diagram 82 power consumption 17 clock 4444 9 0440 201 83 pulse width modulator clocks 205 dependencies 83 See PWM M ADM m operation 8 PWM toon caveat eoi 239 transfers OVETVIEW 81 block diagram 241 Ethernet interface circuit 209 PCDR setup 81 channels Tes ana 242 high level protocols 202 default sostna 82 242 interrupts 205 207 register descriptions 84 dependencies 242 operation 206 Iegisters 82 DMA cha
13. 119 register descriptions 138 Quad Decode User Enable Timer B Step MSB x registers 132 Register 296 Register 119 SPI clock modes 129 Real Time Clock User Timer C 123 ton fo 129 Enable Register 294 Global Control Status use of clocked Serial Port C Serial Port A User Enable Register 18 133 Register 298 Timer Block Access use of clocked Serial Port D Serial Port B User Enable Register 133 Register 298 Timer Block Pointer Serial Port C User Enable Register 128 Register 298 346 Rabbit 4000 Microprocessor User s Manual serial ports continued Serial Ports 145 asynchronous mode 145 block diagram 146 clocks md 148 dependencies 148 HDLC data encoding 152 HDLC mode 145 DPLL counter 152 interrupts 149 operation 150 asynchronous mode 150 HDLC mode 150 OVETVIEW LL 145 USE LL 148 register descriptions 155 registers eese 147 SXSR iine sting 145 slave port 77 161 addresses 161 block diagram 162 bootstrap processor 162 CLOCKS euet 163 de
14. 126 Encryption RAM 40 Serial Port F User Enable Timer C Divider High Global Control Status 299 Register 126 Register 36 Slave Port User Enable Timer C Divider Low Global CPU Register 39 Register 294 Register 126 Global Output Control Timer A User Enable Timer C Reset x High Register ene 39 Register 297 Register 127 Global Revision Register 39 Timer B User Enable Timer C Reset x Low Real Time Clock Control Register sisien 297 Register 127 Register 37 Timer User Enable Timer C Set x High Register Real Time Clock x Regist n cs kisi 2920 127 Register 37 110 Timer Set x Low Register Secondary Watchdog Timer Global Control Status 0 0 22 2 2 2 127 Register 38 Register 114 25 Watchdog Timer Control Timer A Control Register block diagram 25 Register ST 1 suere esie 113 dependencies 26 Watchdog Timer Test Timer A Control Status operation 27 Register 38 Register 112 register descriptions 29 System User mode 284 Timer A Prescale Register 26 Enable Dua
15. 73 cesso uiii 100 example ISR 235 alternate output functions 73 Interrupts Sg rg 101 Operation 235 block diagram 73 MP radon aie 101 OVerVieW 231 Clocks ies 74 Mac NL LE ae register descriptions 236 external I O data bus 73 PEDR setup PAN 97 registers 233 Operation 74 Sq 2 OVerView 73 ES 199 R register description 79 pene Rabbit 2000 6 register descriptions 75 T IN al ius 3000 6 registers Lu 73 A 7 iN A 1 eve poH daa bise 5 alternate pin functions p n x ISTE RIA TERRE UE Parallel Port 77 dion DL E h other Rabbi Outputs 329 comparison WILI oter auxiliary I O bus 77 Paralel Ear Ce dE f B i RU block diagram 78 DU TNI x erus MEE 1 Clocks iuste 78 Doro po Dp de 271 ir eT Eth ME cod EE 78 pin functions 327 DEMEL 3 operation 79 OVETVIEW disse 77 parallel ands Our i 2 opas a 2 esi te den ets 79 puts nde 329 put capture channe 5 TE ISTENS siio 78 parallel Pot CD ance a 2 dive portendbled 7
16. Serial Port x Status Register SASR Address 0x00C3 Asynchronous Mode Only SBSR Address 0x00D3 SCSR Address 0x00E3 SDSR Address 0x00F3 Bit s Value Description 7 0 The receive data register is empty 1 There is a byte in the receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 6 0 The byte in the receive buffer is data received with a valid stop bit 1 The byte in the receive buffer is address or a byte with a framing error If an address bit is not expected and the data in the buffer is all zeros this is a break 5 0 The receive buffer was not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 The byte in the receive buffer has no parity error or was not checked for parity 1 The byte in the receive buffer had a parity error 3 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when 1 the transmitter takes a byte from the transmit buffer Transmit interrupts cleared when the transmit buffer is written or any value which will be ignored is written to this register 2 0 The transmitter is idle The transmitter is sending a byte An interrupt is generated when the transmitter 1 clears this bit which occurs only if the transmitter is ready to start sending another byte
17. Pin Name Alt Out 0 Alt Out 1 Alt Out 2 Alt Out 3 PE7 I7 ACT PWM3 SCLKC PE6 16 PWM2 TXE PES 5 LINK PWMI RCLKE PEA 14 0 PWMO TCLKE PE3 23 TIMER C3 SCLKD PE2 12 A22 TIMER C2 TXF 21 RCLKF PEO 10 A20 TIMER CO TCLKF Chapter 12 Parallel Port E 97 Table 12 2 Parallel Port E Pin Alternate Input Functions Fin Name ne Suns DMA ue Eliemet PE7 DREQI PE6 DREQO ECLK 5 RCLKE INTI PEA TCLKE INTO PE3 RXC RXF DREQI QRD2A 2 5 DREQO QRD2B RXD RCLKF INTI QRDIA PEO SCLKD TCLKF INTO QRDIB 98 Rabbit 4000 Microprocessor User s Manual 12 1 1 Block Diagram Parallel Port E l a en PEDR PEBxR Serial Ports A F 7 0 Tx Rx Clocks External I O Strobes 7 0 and Handshake e em Ethernet Clock 7 5 LEDs 4 0 AO 23 20 PWM Output 74 Timer Output 3 0 extemal interupts 2410 7 6 3 2 3 0 232 TimerB2 0 Chapter 12 Parallel Port E 99 12 1 2 Registers Register Name Mnemonic Address R W Reset Port E Data Register PEDR 0x0070 R W XXXXXXXX Port E Alternate Low Register PEALR 0x0072 00000000 Port Alternate High Register PEAHR 0x00
18. asynchronous mode is 1 8 or 1 16 the data clock rate selectable However in the clocked serial mode the byte data rate is equal to the data clock rate as generated from the appropriate Timer A timer or from the dedicated 15 bit divider Timer A7 When Serial Port A is used in the asynchronous bootstrap mode the 32 kHz clock is used to generate the expected 2400 bps data rate An external clock must be supplied for the clocked serial bootstrap mode 130 Rabbit 4000 Microprocessor User s Manual The behavior of the serial port during break line held low is configurable character assembly can continue during the break condition to allow for timing the break or charac ter assembly can be inhibited to reduce the interrupt overhead 16 1 1 Block Diagram Serial Ports A D SxDHR Peripheral 15 bit Serial Port Clock Divider Serial Data Control SxDHR Clock SxCR SxDLR SxER Timer Ax Output Rx Buffer Latched SxDR SxAR SxLR Latched Tx Buffer A SxDR SxAR SxLR Serial Port Interrupt Status Request SxSR Chapter 16 Serial Ports D 131 16 1 2 Registers Register Name Mnemonic Address R W Reset Serial Port A Data Register SADR 0 00 0 Serial Port A Address Register SAAR 0 00 1 W XXXXXXXX Serial Port A Long Stop Register SALR 0x00C2 W XXXXXXXX Serial Po
19. 00111 12 ns nominal low time 01000 13 ns nominal low time 01001 14 ns nominal low time 01010 15 ns nominal low time 01011 16 ns nominal low time 01100 17 ns nominal low time 01101 18 ns nominal low time 01110 19 ns nominal low time 01111 20 ns nominal low time 10001 3 ns nominal low time 10010 4 ns nominal low time 10011 5 ns nominal low time other Any bit combination not listed is reserved and must not be used 282 Rabbit 4000 Microprocessor User s Manual 27 SYSTEM USER MODE 27 1 Overview The Rabbit 4000 provides support for two tiers of control in the processor System Mode which provides full access to all processor resources and User Mode a more restricted mode Table 27 1 describes the essential differences between the System Mode and the User Mode The System Mode is essentially the same as the normal operation when the System User Mode is disabled Table 27 1 Differences Between System Mode and User Mode System Mode User Mode All peripherals accessible No peripherals accessible by default All processor control registers available No processor control registers available All interrupt priorities available Interrupt Priority 3 not allowed IDET instruction causes Priority 3 System IDET instruction has no effect mode violation interrupt No write protection when 0x00 is written to Write t
20. 19 0 Tadr gt edes gt 165 OEx HEB gt Ie ToEx D 7 0 A 19 0 CSx IWEX D 7 0 Figure 28 1 Memory Read and Write Cycles 306 Rabbit 4000 Microprocessor User s Manual Memory Read no wait states A 19 0 CSx _ gt f Tosx gt lt OEx E Togx gt TloEx D 7 0 A 19 0 CSx IWEX D 7 0 Figure 28 2 Memory Read and Write Cycles Early Output Enable and Write Enable Timing Chapter 28 Specifications 307 28 3 3 External I O Reads Table 28 6 Preliminary External Read Time Delays VDDcogg 1 8 V 10 VDDio 3 3 V 10 TA 40 C to 85 C Parameter Symbol Loading Min Typ Max 30 pF 6ns Clock to Address Delay 60 pF 8 ns 90 pF 11 ns 30 pF 6 ns Clock to Memory Chip Select Delay Tcsx 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to I O Chip Select Delay Tiocsx 60 8 ns 90 pF 11 ns 30 pF 6ns Clock to I O Read Strobe Delay TioRp 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to I O Buffer Enable Delay TBUFEN 60 pF 8 ns 90 pF 11 ns Data Setup Time Tsetup ns Data Hold Time Thold z 1 ns 308 Rabbit 4000 Microprocessor User s Manual 28 3 4 External I O Writes Table 28 7 Preliminary External I O Write Time Delays VDDcore 1 8 V 10
21. Bit s Value Description 7 6 00 Parallel Port D bit 7 alternate output 0 IA7 01 Parallel Port D bit 7 alternate output 1 I7 10 Parallel Port D bit 7 alternate output 2 PWM3 11 Parallel Port D bit 7 alternate output 3 SCLKC 5 4 00 Parallel Port D bit 6 alternate output 0 TXA 01 Parallel Port D bit 6 alternate output 1 I6 10 Parallel Port D bit 6 alternate output 2 PWM2 11 Parallel Port D bit 6 alternate output 3 3 2 00 Parallel Port D bit 5 alternate output 0 IA6 01 Parallel Port D bit 5 alternate output 1 I5 10 Parallel Port D bit 5 alternate output 2 PWM1 11 Parallel Port D bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port D bit 4 alternate output 0 TXB 01 Parallel Port D bit 4 alternate output 1 I4 10 Parallel Port D bit 4 alternate output 2 PWMO 11 Parallel Port D bit 4 alternate output 3 TCLKE Parallel Port D Function Register PDFR Address 0x0065 Bit s Value Description 7 0 0 corresponding port bit functions normally 1 The corresponding port bit carries its alternate signal as an output See Table 11 1 260 Rabbit 4000 Microprocessor User s Manual Parallel Port E Alternate Low Register PEALR Address 0x0072 Bit s Value Description 7 6 00 Parallel Port E bit 3 alternate output 0 13
22. Rabbit 4000 Microprocessor User s Manual 019 0152 070720 Rabbit 4000 Microprocessor User s Manual Part Number 019 0152 e 070720 H Printed in U S A 2006 2007 Rabbit Semiconductor Inc All rights reserved No part of the contents of this manual may be reproduced or transmitted in any form or by any means without the express written permission of Rabbit Semiconductor Permission is granted to make one or more copies as long as the copyright page contained therein is included These copies of the manuals may not be let or sold for any reason without the express written permission of Rabbit Semiconductor Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit and Dynamic C are registered trademarks of Rabbit Semiconductor Inc Rabbit 4000 is a trademark of Rabbit Semiconductor Inc The latest revision of this manual is available on the Rabbit Semiconductor Web site www rabbit com for free unregistered download Rabbit Semiconductor Inc www rabbit com Rabbit 4000 Microprocessor User s Manual TABLE OF CONTENTS Chapter 1 The Rabbit 4000 Processor 1 141 InttoductiOBs ee ra a 1 1 2 ej 1 1 3 0 4 1 4 Basic 3 1 5 Comparin
23. 00010 7 ns nominal low time 00011 8 ns nominal low time 00100 9 ns nominal low time 00101 10 ns nominal low time 00110 11 ns nominal low time 00111 12 ns nominal low time 01000 13 ns nominal low time 01001 14 ns nominal low time 01010 15 ns nominal low time 01011 16 ns nominal low time 01100 17 ns nominal low time 01101 18 ns nominal low time 01110 19 ns nominal low time 01111 20 ns nominal low time 10001 3 ns nominal low time 10010 4 ns nominal low time 10011 5 ns nominal low time other Any bit combination not listed is reserved and must not be used Rabbit 4000 Microprocessor User s Manual Global Output Conirol Register GOCR Address 0x000E Bit s Value Description 7 6 00 CLK pin is driven with peripheral clock 01 CLK pin is driven with peripheral clock divided by 2 10 CLK pin is low 11 CLK pin is high 5 4 00 STATUS pin is active low during a first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 3 2 00 WDTOUT pin functions normally 01 Enable WDTOUT for test mode Rabbit Semiconductor internal use only 10 WDTOUT pin is low 1 cycle min 2 cycles max of 32 kHz 11 This bit combination is reserved and should not be used 1 0 00 BUFEN pin is active low during
24. 266 handling unused pins 273 Ethernet 185 example ISR 267 operation 273 HDLC serial ports 185 DMA channels 174 177 179 esee 271 PWM and Timer 185 example ISR 179 register descriptions 280 DMA control 173 external interrupt vector table Tegisters 272 67 self timed chip selects 279 E i short chip selects 274 external interrupts 69 70 ESD block diagram 69 LQFP package design guidelines 334 CLOCKS 5 1 70 mechanical dimensions 322 ESD sensitivity 2 334 dependencies 70 M Ethernet interface circuit 209 example ISR 70 Ethernet interrupt vectors 70 memory See Network Port A operation 70 read and write cycles no wait external I O control 247 register descriptions 71 states seen 307 auxiliary bus 247 registers 70 memory management 41 block diagram 250 input capture channels 222 223 block diagram 43 clocks 251 example ISR 223 ete 45 dependencies 251 internal interrupt vector table dependencies NEN 45 handshake e uo
25. 27 jA Register Descriptions eere etri ge 29 Chapter 4 System Management 31 1 MIN CT VIS D D LE E 9 31 4 1 1 Block Dia Sram iii is Pana Rey Rete 32 Em 32 2 2 WS POMC GIE Sa i A te 33 42 1 FO PNS ii eem 33 ADD CIOCKS Bn 33 pe Ox 33 4 5 Ke e Ke Deeks KESE 34 4 5 1 Interrupt 34 432 Real Time Clock ett a 34 4 3 3 Walchdos TIMET 35 4 3 4 Secondary Watchdog Timer ieissar noaei e ii iaie 35 4 4 Register Descriptions seserimis nises 36 Table of Contents Chapter 5 Memory Management 41 REO ABE tees du tu elu a 41 9 11 Block Diagram ee ae emet ar ERR 43 BIA L AT 44 9 2 IDEPENJENCIES xi A e Saba B jeb ASh 45 9 24 MO PINS tosses A a tt Tas Ti Hn REB ER 45 RM EE 45 52 3 Other Registers eee eie pre RO OPE PODER RR HERE OE p nre 45 9 24 Li serena i eri PODES MI USUS 45 5 3 Operation il piz ime Ded eiTe nU 46 5 3
26. 27 3 6 System Mode Violation Interrupt The following steps describe how to set up the System Mode Violation interrupt 1 2 3 Write the vector to the interrupt service routine to the internal interrupt table Enable the system user mode by writing to EDMR The interrupt request is cleared automatically when handled A sample interrupt handler is shown below sysmode isr push af handle the system mode violation here pop af sures ipres ret Chapter 27 System User Mode 291 27 3 7 Handling Interrupts the System User Mode Interrupts RSTs SYSCALL and SCALL all enter the System Mode automatically There will be times however that an interrupt should be handled in the User Mode The solution to this is for System Mode interrupt vector to reenter the User Mode before calling the User Mode interrupt handler An example of both system and user interrupt handling is shown in Figure 27 4 When enabled for User Mode access a peripheral interrupt if it is capable of generating an interrupt can only be requested at Priority 2 or 1 INTERRUPT UNDER SYSTEM CONTROL ISR system Application code user Application code user INTERRUPT UNDER USER CONTROL Application ISR user Application code user Application code user Figure 27 4 Interrupt Handing in the System User Mode 292 Rabbit 4000 Microprocessor User s Manual Some sample code for both System Mode interrupts User Mod
27. 10 2 Dependencies 10 2 1 I O Pins Parallel Port C uses pins PCO through PC7 These pins can be used individually as data inputs or outputs as serial port transmit and receive for Serial ports A F as clocks for Serial Ports as external I O strobes or as outputs for the PWM and Timer periph erals The input capture peripheral can also watch pins PC7 PC5 and PC1 On startup PC4 PC2 and PCO are outputs set high PC6 is set low and the other pins are inputs for compatibility with the Rabbit 3000 The individual pins can be set to be open drain via PCDCR See the associated peripheral chapters for details on how they use Parallel Port C 10 2 2 Clocks outputs on Parallel Port C are clocked by the peripheral clock 10 2 3 Other Registers Register Function SACR SBCR SCCR Select a Parallel Port C pin as serial data and SDCR SECR SFCR optional clock input Select a Parallel Port C pin as a start stop condition ICSIR ICS2R input 10 2 4 Interrupts There are no interrupts associated with Parallel Port C 10 3 Operation The following steps must be taken before using Parallel Port C 1 Select the desired input output direction for each pin via PCDDR 2 Select driven or open drain functionality for outputs via PCDCR 3 If an alternate peripheral output function is desired for a pin select it via PCALR or PCAHR and then enable it via PCFR Refer to the appropriate pe
28. 11 Parallel Port bit 4 alternate output 3 TCLKE Parallel Port C Drive Control Register PCDCR Address 0x0054 Bit s Value Description 7 0 0 The corresponding port bit as an output is driven high and low 1 The corresponding port bit as an output is open drain Parallel Port C Function Register PCFR Address 0x0055 Bit s Value Description 7 0 0 The corresponding port bit functions normally 1 The corresponding port bit carries its alternate signal as an output See Table 10 1 Chapter 10 Parallel Port C 85 86 Rabbit 4000 Microprocessor User s Manual 11 PARALLEL PORT 11 1 Overview Parallel Port D is byte wide port with each bit programmable for data direction and drive level These are simple inputs and outputs controlled and reported in the Port D Data Register PDDR All of the Parallel Port D pins have alternate output functions and all of them can be used as inputs to various on chip peripherals When used as outputs the Parallel Port D bits are buffered with the data written to PDDR transferred to the output pins on a selected timing edge Either the peripheral clock or the outputs of Timer 1 Timer Bl or Timer B2 can be used for this function with each nib ble of the port having a separate select field to control this timing Each bit can either be programmed as open drain or driven high and low Because
29. 110 interrupts 108 111 example ISR 111 Operation 111 Overview 107 register descriptions 112 registers oe 110 reload register operation 107 Timer B eee 115 block diagram 115 COCKS vices hte 116 dependencies 116 interrupts 116 117 example ISR 117 Operation 117 OVETVIEW L 115 PWM operation 115 register descriptions 118 registers 116 Timer C eee 121 block diagram 122 clocks enne 124 dependencies 124 DMA control 121 interrupts 124 125 example ISR 125 Operation 125 OVETVIEW 121 register descriptions 126 registers 123 timing diagrams R W cycles 310 memory R W cycles 306 memory R W cycles early output enable and write enable 307 slave port R W cycles 168 169 Index 347 watchdog timer primary watchdog timer 35 primary secondary watchdog timer bug 35 335 secondary watchdog timer 35 SettIngs uere 35 348 Rabbit 4000 Microprocessor User s Manual
30. 2 42 330 ACCESS parallel port inputs 331 onchip encryption RAM 3 SPCR setup 77 parallel ports 2 Index 341 Rabbit 4000 registers registers features continued alphabetic listing continued alphabetic listing continued protected operating systems 193 213 E EE E 3 DxTMR 193 NATCR 5 216 PWM outputs 2 DyCR ue 196 NATSR e 211 quadrature decoder EDMR 5 ens 299 PADR enn 75 channels 2 GCDR 22 282 PAUER 294 METS cene A 2 GCMOR 21 PBDDR 79 revision history 333 GCMIR 21 PBDR 79 specifications 5 GCPU niet 39 PBUER 294 Rabbit Semiconductor 20 36 114 120 PCARR 85 258 history 5 1 128 280 22222222 84 257 registers GOGCR ee 23 39 PCDCR ii iss 85 alphabetic listing GPSCR 281 PEDDR 84 ACSXxCR 58 GREV ae gosse 39 PEDR 84 268 IBUER 296 85 258 269 ICCR kie iii 226 PCUER sisien 294 BXAIR sisien 269 ICCSR 225 PDAHR 93 260 BXAQR 269 ICL
31. Chapter 4 System Management 35 4 4 Register Descriptions Global Control Status Register GCSR Address 0x0000 Bit s Value Description 7 6 00 No reset or watchdog timer timeout since the last read rd only 01 watchdog timer timed out These bits cleared by a read of this register 10 This bit combination is not possible 11 Reset occurred These bits are cleared by a read of this register 5 0 No effect on the periodic interrupt This bit will always be read as zero 1 Force a periodic interrupt to be pending 23 000 Processor clock from the main clock divided by eight Peripheral clock from the main clock divided by eight 001 Processor clock from the main clock divided by eight Peripheral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock ol Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Processor clock from the 32 clock optionally divided via GPSCR Peripheral clock from the 32 kHz clock optionally divided via GPSCR Processor clock from the 32 clock optionally divided via GPSCR 101 Peripheral clock from the 32 kHz clock optionally divided via GPSCR The main clock is disabled 110 Processor clock from the main clock divided by four Peripheral clock from the main clock divided by four 111 Processor clock from the ma
32. WRITE STROBE READ i READ STROBE CHIP SELECT STROBE EXTERNAL I O TIMING with 1 wait state Figure 24 1 Auxiliarv Bus Cvcles 248 Rabbit 4000 Microprocessor User s Manual The strobes be enabled to come out on Parallel Ports or E By default the I O strobes are configured as read only chip selects with 15 wait states and normal timing These settings will affect the IORD IOWR and BUFEN signals for external I O writes even if no other strobe outputs are enabled in the parallel port registers 24 1 3 Handshake An external I O handshake input can be enabled on one of the Parallel Port E pins for any combination of the I O banks The external device holds this signal active high or low when it is busy and cannot accept a transaction The Rabbit 4000 will then hold midway through the transaction until either the handshake signal goes inactive or a timeout occurs The timeout can be defined anywhere from 32 to 2048 clocks When the timeout occurs the transaction ends and a status bit is set This bit must be checked by the program attempting the write no interrupt is generated The I O handshake signal is sampled at the end of the first wait state Tw When the hand shake signal is disabled the transition will start at the beginning of the Tw phase and con tinue to completion ADDR Ea i WRITE DATA m WRITE STROBE READ DATA a READ STROBE i
33. 8 Powerdown Modes sleepv 32 kHz 32 kHz 32 kHz Powerdown Modes ultra sleepv 16 8 2 kHz 16 8 2 kHz Short and Short and Low Power Memory Control Self Timed Chip Self Timed Chip None Selects Selects Extended Memory Timing for High Yes Yes Rabbit 2000C Frequency Operation Number of 8 bit I O Ports 5 7 5 Auxiliary I O Data Address Bus Yes Yes None Number of Serial Ports 6 6 4 Serial Ports Capable of SPI Clocked Serial 4 A B C D 4 A B C D 2 A B Serial Ports Capable of SDLC HDLC 2 E F 2 E F None Rabbit 4000 Microprocessor User s Manual Feature Rabbit 4000 Rabbit 3000 Rabbit 2000 Asynch Serial Ports With Support for 6 6 None IrDA Communication Serial Ports with Support for SDLC HDLC IrDA Communication 2 mene Maximum Asynchronous Baud Rate Clock Speed 8 Clock Speed 8 Clock Speed 32 Ethernet Port 10Base T None None Input Capture Units 2 2 None Chapter 1 The Rabbit 4000 Processor Rabbit 4000 Microprocessor User s Manual 2 CLOCKS 2 1 Overview The Rabbit 4000 supports up to three separate clocks the main clock the 32 kHz clock and the 20 MHz Ethernet clock The main clock is used to derive the processor clock and the peripheral clock inside the processor The 32 kHz clock is used to drive the asynchro nous serial bootstrap the real time clock the periodic interrupt and the watchdog timers The Rabbit 4000 has a spectrum spreader on the main clock tha
34. Bit s Value Description 7 2 read These bits are reserved and will always read as zeros 1 0 read The current value of bits 9 8 of the Quadrature Decoder counter is reported Chapter 22 Quadrature Decoder 237 238 Rabbit 4000 Microprocessor User s Manual 23 PULSE WIDTH MODULATOR 23 1 Overview The Pulse Width Modulator PWM consists of a 10 bit free running counter and four width registers A PWM output consists of a train of periodic pulses within a 1024 count frame with a duty cycle that varies from 1 1024 to 1024 1024 Each PWM output is high for n 1 counts out of the 1024 clock count cycle where is the value held in the width register The PWM is clocked by the output of Timer A9 which is used to set the period Each PWM output high time can optionally be spread throughout the cycle to reduce rip ple on the externally filtered PWM output The PWM outputs can be passed through a fil ter and used as a 10 bit D A converter The outputs can also be used to directly drive devices such as motors or solenoids that have intrinsic filtering The PWM outputs can trigger a PWM interrupt on every PWM cycle every other cycle every fourth cycle or every eighth cycle In addition the PWM output can be suppressed every other cycle three out of every four cycles or seven out of every eight cycles These options provide support for driving servos and to generate audio signals The setup for this interrupt is done
35. Serial Port x Data Register SADR Address 0 00 0 SBDR Address 0 0000 SCDR Address 0x00E0 SDDR Address 0x00F0 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with a data byte for transmission Serial Port x Address Regisiter SAAR Address 0x00C1 SBAR Address 0x00D0 SCAR Address 0x00E0 SDAR Address 0x00F0 Bit s Value Description Returns the contents of the receive buffer Reading the data from this register in 7 0 Read the clocked serial mode automatically causes the receiver to start a byte receive operation eliminating the need for software to issue the start receive command Loads the transmit buffer with an address byte marked with a zero address bit for transmission Writing the data to this register in the clocked serial mode Write causes the transmitter to start byte transmit operation eliminating the need for the software to issue the start transmit command Serial Port x Long Stop Register SALR Address 0x00C2 SBLR Address 0 0000 SCLR Address 0x00E0 SDLR Address 0 00 0 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with an address byte marked with a one address bit for transmission 138 Rabbit 4000 Microprocessor User s Manual
36. Table of Contents T43 Operation EE 117 14 3 1 Handling Interrupts tte L se 117 14 3 2 Example ISR 5 oen tee fee deer Te 117 14 4 Register Descriptions uper eet etes epe np sey Te penetret tee sere 118 Chapter 15 Timer C 121 15 1 OVERVIEW eet iter ph epa De er ER ER PEE Ple TS 121 15 11 Block Diagram iei Herr tette e a peeled ed de eco eeu 122 15 12 123 15 2 Dependen ies i oir A PO a 124 Pins e RR ae n 124 15 227 CIoCkS siti a e un e EOD PET Ree Dept 124 15 23 Other Resistens M 124 15 24 Tntetrupts ied 124 INEO oT 125 15 3 1 Handling Intert pts ione po Re tte tiet Beas 125 15 8 2 Example ISR lecce ee eite pp o ti e yet 125 154 Register Descriptions 2 aree rer e eter tere e duit ee Ere ed 126 Chapter 16 Serial Ports A D 129 I6 Ts OVERVIEW eese PERDU ERR ERR E EO ERE UE 129 16 11 Bl ck 131 16 1 2 RegiStetS 132 16 2 Dependencies iie Date tette Een e Ove ERO 133 16 2 T 070 nire eH edere 133 16 2 2 Cloc KS ii i ert Rei e e e enr did 134 16 2 3 Oth
37. The ping pong buffer where there are only two buffers is the simplest version of a circular queue The application can operate on one buffer while the other buffer is being loaded 19 3 5 5 Linked Array The linked array is simply a linked list of buffer arrays where the last buffer in each array is linked to the first buffer in the next array which can be located anywhere in memory This method could be useful where a message is broken down into separate transfers but entire messages could be scattered gathered from anywhere in memory 184 Rabbit 4000 Microprocessor User s Manual 19 3 6 DMA with Peripherals When the DMA is directed towards an internal I O address the DMA transfer request signals will be connected as appropriate for that peripheral For example when a DMA transfer is performed to Serial Port D s data register the transfer request will be enabled whenever the serial port transmit buffer is empty and will be disabled whenever it is not 19 3 6 1 DMA with HDLC Serial Ports The HDLC serial ports receive special handing by the DMA When the DMA destination is Serial Port E s or Serial Port F s data register SxDR the final byte of the transfer will be written to the appropriate last data register SxLDR as required to complete an HDLC packet and append the CRC value In addition the value in the appropriate status register SxSR will be written to the status byte in the buffer descriptor pointed to
38. 01 Parallel Port E bit 3 alternate output 1 23 10 Parallel Port E bit 3 alternate output 2 TIMER C3 11 Parallel Port E bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port E bit 2 alternate output 0 12 01 Parallel Port E bit 2 alternate output 1 22 10 Parallel Port E bit 2 alternate output 2 TIMER C2 11 Parallel Port E bit 2 alternate output 3 TXF 3 2 00 Parallel Port E bit 1 alternate output O I1 01 Parallel Port E bit 1 alternate output 1 A21 10 Parallel Port E bit 1 alternate output 2 TIMER 11 Parallel Port E bit 1 alternate output 3 RCLKF 1 0 00 Parallel Port E bit 0 alternate output 0 IO 01 Parallel Port E bit O alternate output 1 A20 10 Parallel Port E bit 0 alternate output 2 TIMER 11 Parallel Port E bit 0 alternate output 3 TCLKF Chapter 24 External I O Control 261 Parallel Port E Alternate High Register PEAHR Address 0x0073 Bit s Value Description 7 6 00 Parallel Port E bit 7 alternate output 0 17 01 Parallel Port E bit 7 alternate output 1 ACT 10 Parallel Port E bit 7 alternate output 2 PWM3 11 Parallel Port E bit 7 alternate output 3 SCLKC 5 4 00 Parallel Port E bit 6 alternate output 0 I6 01 Parallel Port E bit 6 alternate output 1 10 Parallel Port E bit 6 alternate output 2 PWM2 11 Parallel Port E bit 6 alternate output 3
39. 0x00AA Bit s Value Description 7 0 Time constant for the Timer A counter This time constant will take effect the next time that the Timer A counter counts down to zero The timer counts modulo 1 where is the programmed time constant Chapter 13 Timer A Global Control Status Register GCSR Address 0x0000 Bit s Value Description db 000 Processor clock from the main clock divided by eight Peripheral clock from the main clock divided by eight 001 Processor clock from the main clock divided by eight Peripheral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Processor clock from the 32 clock optionally divided via GPSCR Peripheral clock from the 32 kHz clock optionally divided via GPSCR Processor clock from the 32 kHz clock optionally divided via GPSCR 101 Peripheral clock from the 32 kHz clock optionally divided via GPSCR The fast clock is disabled 110 Processor clock from the main clock divided by four Peripheral clock from the main clock divided by four 111 Processor clock from the main clock divided by six Peripheral clock from the main clock divided by six 114 Rabbit 4000 Microprocessor User s Manual 14 TIMER B 14 1 Overview The
40. 1 The individual Timer A capabilities are summarized in the table below There is a bit in the control status register to disable all ten timers globally Timer Interrupt Associated Peripheral from 1 Al No Yes Parallel Ports D E Timer A2 Yes Yes Serial Port E A3 Yes Yes Serial Port F A4 Yes Yes Serial Port A 5 Serial Port A6 Yes Yes Serial Port C 7 Serial Port 8 Input Capture 9 Pulse Width Modulator 10 Quadrature Decoder There is one interrupt vector for Timer A and a common interrupt priority A common status register TACSR has bits for timers A1 A7 that indicate if the output pulse for that timer has taken place since the last read of the status register These bits are cleared when the status register is read No bit will be lost Either it will be read by the status register read or it will be set after the status register read is complete If a bit is on and the corresponding interrupt is enabled an interrupt will occur when priorities allow However a separate interrupt is not guaranteed for each bit with an enabled interrupt If the bit is read in the status register it is cleared and no further interrupt corresponding to that bit will be requested It is possible that one bit will cause an interrupt and then one or more additional bits will be set before the sta tus register is read After these
41. 1 0 7 Second 5 4 3 2 1 0 7 6 Third 4 3 2 1 0 7 6 5 Fourth 3 2 1 0 7 6 5 4 Fifth 2 1 0 7 6 5 4 3 Sixth 1 0 7 6 5 4 3 2 Seventh 0 7 6 5 4 3 2 1 19 3 5 Buffer Descriptor Modes Flags in the control byte of a buffer descriptor which gets loaded into DyCR describe whether to halt on completion of the transfer or load another descriptor and whether the next descriptor is adjacent in memory which implies that the current descriptor is only 12 bytes long or located at the link address Each descriptor can also be set to generate an interrupt on completion of the transfer By using these options in various ways the Rabbit 4000 DMA can be operated in a number of conventional DMA modes The most common options are described here others are certainly possible by different use of the available linking methods Chapter 19 DMA Channels 181 19 3 5 1 Single Buffer In the simplest mode a single descriptor is set to halt and interrupt on completion Single Buffer Initial Buffer Descriptor Address 12 bytes Interrupt 19 3 5 2 Buffer Array In this mode an array of 12 byte descriptors is set up adjacent in memory only the last buffer is set to halt on completion The last buffer is also typically set to interrupt on com pletion but other buffer descriptors in the array can also generate interrupts Buffer Array Initial Buffer Descriptor Address 12 bytes Buffer Descriptor
42. 10 The upper nibble peripheral clock is the output of Timer 11 The upper nibble peripheral clock is the output of Timer B2 3 2 These bits are ignored and should be written with zero 1 0 00 The lower nibble peripheral clock is CLK 2 01 lower nibble peripheral clock is the output of Timer 1 10 The lower nibble peripheral clock is the output of Timer B1 11 The lower nibble peripheral clock is the output of Timer B2 Chapter 12 Parallel Port E 103 Parallel Port Function Register PEFR Address 0x0075 Bit s Value Description 7 0 0 The corresponding port bit functions normally The corresponding port bit carries its alternate signal as an output See Table 12 1 Parallel Port E Drive Control Register PEDCR Address 0x0076 Bit s Value Description 7 0 0 The corresponding port bit as an output is driven high and low 1 The corresponding port bit as an output is open drain Parallel Port E Data Direction Register PEDDR Address 0x0077 Bit s Value Description 7 0 0 The corresponding port bit is input 1 The corresponding port bit is an output Parallel Port E Bit 0 Register PEBOR Address 0x0078 Bit s Value Description 7 1 These bits are ignored The port buffer bit 0 is written with the value of this bit The port buffer will be 0 Write transferred to the port output register
43. 105 Parallel Port E Bit 4 Register 105 Parallel Port E Bit 5 Register 105 Parallel Port E Bit 6 Register 106 Parallel Port E Bit 7 Register 106 Parallel Port E Control Register 103 Parallel Port E Data Direction Register 104 Parallel Port E Data Register 102 Parallel Port E Drive Control Register 104 Parallel Port E Function Register 104 PWM 241 PWM Block Access Register 245 PWM Block Pointer Register 245 PWM LSB 0 Register 244 PWM LSB 1 Register 244 PWM LSB x Register 245 PWM MSB x Register 245 quadrature decoder 233 Quad Decode Control Register 237 Quad Decode Control Status Register 236 Quad Decode Count High Register 237 Quad Decode Count Register 237 registers continued i c 26 reset bootstrap Slave Port Control Register tm 29 Serial Ports 132 Serial Port x Address Register 138 Serial Port x Control Register 141 Serial Port x Data Register 138 Serial Port x Divider High Register 144 Serial Port x Divider Low Register 143 Serial Port x Extended R
44. DOIAOR Address 0x010C D1IAOR Address 0x011C D2IAOR Address 0x012C D3IAOR Address 0x013C DAIAOR Address 0x014C D5IAOR Address z 0x015C D6IAOR Address 0x016C D7IAOR Address 0x017C Bit s Value Description 7 0 Bits 7 0 of the initial address are stored in this register DMA y Initial Addr 15 8 Register DOIA1R Address 0x010D D1IA1R Address 0x011D D2IA1R Address 0x012D D3IA1R Address 0x013D DAIA1R Address z 0x014D D5IA1R Address z 0x015D D6IA1R Address 0x016D D7IA1R Address 0x017D Bit s Value Description 7 0 Bits 15 8 of the initial address are stored in this register DMA Initial Addr 23 16 Register DOIA2R Address 0x010E D1IA2R Address 0x011E D2IA2R Address 0x012E D3IA2R Address 0x013E DAIA2R Address 0x014E D5IA2R Address 0x015E D6IA2R Address 0x016E D7IA2R Address 0x017E Bit s Value Description 7 0 Bits 23 16 of the initial address are stored in this register 194 Rabbit 4000 Microprocessor User s Manual State Machine Register DOSMR Address 0x0180 015 Address 0x0190 D2SMR Address 0x01A0 D3SMR Address 0x01B0 D4SMR Address 0x01C0 D5SMR Address 0x01D0 D6SMR Address 0x01E0 D7SMR Address 0x01F0 Bit s Value Description 7 0 11111110 Idle
45. IB4CR Address 0x0084 IB5CR Address 0x0085 IB6CR Address 0x0086 IB7CR Address 0x0087 Bit s Value Description 7 6 00 Fifteen wait states for accesses in this bank 01 Seven wait states for accesses in this bank 10 Three wait states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The I signal is an I O chip select 01 The I signal is an I O read strobe 10 The I signal is an I O write strobe 11 The I signal is an I O data read or write strobe 3 0 Writes are not allowed to this bank Transactions are normal in every other way only the write strobe is inhibited 1 Writes are allowed to this bank 2 0 Active low I signal 1 Inverted active high I signal 1 0 Normal I O transaction timing Shorten read strobe by one clock cycle and write strobe by one half clock cycle 1 Transaction length remains the same This guarantees one clock cycle hold time for both address and data for I O transactions 0 0 Use I O bus if enabled 1 Always use memory data bus Chapter 24 External I O Control 255 Slave Port Control Register SPCR Address 0x0024 Bit s Value Description 7 0 Program fetch as a function of the SMODE pins 1 Ignore the SMODE pins program fetch function 6 5 Read These bits report the state of the SMODE pins Write These bits are ignored and should be written with zero 4 2 000 Disable the sl
46. Memory Bank 3 Control Register MB3CR 0x0017 MMU Expanded Code Register MECR 0x0018 00000000 Memory Timing Control Register MTCR 0x0019 00000000 Memory Alternate Control Register MACR 0x001D 00000000 Advanced CSO Control Register ACSOCR 0x0410 00000000 Advanced CS1 Control Register ACSICR 0 0411 00000000 RAM Segment Register RAMSR 0x0448 00000000 Write Protect Control Register WPCR 0x0440 00000000 Write Protect x Register WPxR 0 460 W 00000000 Write Protect Segment A Register WPSAR 0x0480 W 00000000 Write Protect Segment A Low Register WPSALR 0x0481 W 00000000 Write Protect Segment A High Register WPSAHR 0x0482 W 00000000 Write Protect Segment B Register WPSBR 0x0484 W 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Stack Limit Control Register STKCR 0x0444 R W 00000000 Stack Low Limit Register STKLLR 0x0445 W XXXXXXXX Stack High Limit Register STKHLR 0x0446 W XXXXXXXX 44 Rabbit 4000 Microprocessor User s Manual 5 2 Dependencies 5 2 1 Pins There are three chip select pins CSO CS1 and CS2 two read strobes OEO and OE1 and two write strobes WEO and WEI There are eight dedicated data bus pins DO through D7 If the 16 bit mode is enabled then PDO PD7 automatically act as the upper byte of the data bus D8 through D15 There are 20 dedic
47. SALR or dummy write to SASR Rx Read from SBDR or SBAR Serial Port B Tx Write to SBDR SBAR SBLR dummy write to SBSR Rx Read from SCDR or SCAR Serial Port C Tx Write to SCDR SCAR SCLR or dummy write to SCSR Read from SDDR or SDAR Lowest Serial Port D Tx Write to SDDR SDAR SDLR or dummy write to SDSR 68 Rabbit 4000 Microprocessor User s Manual 7 EXTERNAL INTERRUPTS 7 1 Overview The Rabbit 4000 has six external interrupts available and they share two interrupt vectors In the case of multiple interrupts sharing an interrupt vector the data register correspond ing to the parallel port s being used can be read Each interrupt vector can be set to trigger on a rising edge a falling edge or either edge The signal on the external interrupt pin must be present for at least three peripheral clock cycles to be detected In addition the Rabbit 4000 has a minimum latency of 10 clocks to respond to an interrupt so the minimum external interrupt response time is three periph eral clock cycles plus 10 processor clock cycles 7 2 Block Diagram External Interrupts Enable and FDO Edge Detection Enable and Interupt 0 PEU Edge Detection Interrupt 0 PE4 Enable and Edge Detection Request Enable and 1 Edge Detection External Enable and Interrupt 1 Edge Detection D Generation Request PE5 Enable and Edge Detection Chapter 7 External Inter
48. TXE 3 2 00 Parallel Port E bit 5 alternate output 0 I5 01 Parallel Port E bit 5 alternate output 1 LINK 10 Parallel Port E bit 5 alternate output 2 PWM1 11 Parallel Port bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port E bit 4 alternate output 0 14 01 Parallel Port E bit 4 alternate output 1 0 10 Parallel Port E bit 4 alternate output 2 PWMO 11 Parallel Port E bit 4 alternate output 3 TCLKE Parallel Port E Function Register PEFR Address 0x0075 Bit s Value Description 7 0 0 The corresponding port bit functions normally 1 i corresponding port bit carries its alternate signal as an output See Table 12 262 Rabbit 4000 Microprocessor User s Manual 25 BREAKPOINTS 25 1 Overview The Rabbit 4000 contains seven hardware breakpoints to support debugging Each hard ware breakpoint consists of a 24 bit address match register and a 24 bit mask register A breakpoint can be generated on an address match for address execution data read data write or any combination thereof The mask register serves to mask off selected address bits from the address compare A one in a particular bit position in the mask register inhibits the corresponding bit in the address match register from contributing to the address match condition When a match occurs a Level 3 breakpoint interrupt is generated Note that this means that breakpoints behave differently when the processor is running at Interrupt Priority
49. The network port receiver uses two pins with various options for the behavior The network port transmitter uses four pins to provide differential signals with wave shaping capability See Section 20 4 for more details 20 1 1 Block Diagram 10Base T Network Port PE6 CPU Network Port Clock Control Divide by 2 ee Network Multicast Rx Buffer RxD Receiver Filter 32 bytes NAMHR NADR NAMExR TxD Tx Buffer Network TxDD 16 bytes Transmitter TxD NADR TxDD Error NALDR Counters NACDR Network Port Interrupt Status Request NAMER Chapter 20 10Base T Ethernet 203 20 1 2 Registers Register Name Address R W Reset Network Port A Data Register NADR 0x0200 R W XXXXXXXX Network Port A Last Data Register NALDR 0 0201 XXXXXXXX Network Port A Transmit Status Register NATSR 0x0202 R 00000000 Network Port A Receive Status Register NARSR 0x0203 R 00000000 Network Port A Control Status Register NACSR 0x0204 R W 00000000 Network Port A Status Register NASR 0x0205 R 00000000 Network Port A Reset Register NARR 0x0206 W 00000000 Network Port Control Register NACR 0x0207 R W 00000000 Network Port Pin Control Register NAPCR 0x0208 R W 000000xx Network Port Transmit Control Register NATCR 0x020A R W 00000000 Network Port Receive Control Register NARCR 0x020B R W 00000000 Network Port
50. VDDjo 3 3 V 10 T4 40 C 85 C Parameter Symbol Loading Min Typ Max 30 pF 6ns Clock to Address Delay 60 pF 8 ns 90 pF 11 ns 30 pF 6 ns Clock to Memory Chip Select Delay Tcsx 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to I O Chip Select Delay Tiocsx 60 8 ns 90 pF 11 ns 30 pF 6ns Clock to I O Write Strobe Delay TiowR 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to I O Buffer Enable Delay TBUFEN 60 pF 8 ns 90 pF 11 ns 30 pF 10 ns High Z to Data Valid Relative to Clock 60 12 ns 90 pF 15 ns 30 pF 10 ns Data Valid to High Z Relative to Clock TpvHz 60 12 ns 90 pF 15 ns Chapter 28 Specifications 309 External I O Read no extra wait states lt T1 gt lt Tw gt lt T2 gt ot LI LI LI A 15 0 Tadr ICSx osx NOCSx lt gt Tlocsx lt gt NORD TioRDI BUFEN BUFEN TBUFEN gt setup lt D 7 0 QUUM External I O Write no extra wait states I T1 gt lt Tw se T2 gt qd uw 15 0 Tadr ICSx Zi gt NOCSx X LLL 21 Tlocsx Tiocsx lt BUFEN TBUFEN TBUFEN gt D 7 0 2 Tpvuz lt gt Figure 28 3 Read and Write Cycles No Extra Wait States NOTE IOCSx be programmed
51. Value Description 7 0 read The LSB of the checksum for the completed frame is returned in this register Network Port A Checksum 1 Register NAC1R Address 0x0225 Bit s Value Description 7 0 read The MSB of the checksum for the completed frame is returned in this register Network Port A Missed Frame Register NAMFR Address 0x0226 Bit s Value Description The current value of the missed frame counter is returned This counter is cleared 7 0 read by aread of this register 218 Rabbit 4000 Microprocessor User s Manual 21 INPUT CAPTURE 21 1 Overview The input capture peripheral consists of two channels each of which contains a 16 bit counter and edge detection circuitry The input capture channels are usually used to deter mine the time between events An event is signaled by a rising or falling edge or option ally by either edge on one of 12 input pins that can be selected as the input for either of the two channels The input capture channels synchronize their inputs to the input capture clock from Timer A8 providing a low pass filter functionality on the inputs as shown in Section 21 2 4 Each channel can be used in one of two modes input capture or input count 21 1 1 Input Capture Mode In the input capture mode the channel starts stops the counter clocked by Timer A8 according to the signal edges on various parallel port pins providing the ability to
52. handle jabber done pop af ipres ret handle rx err ioi 14 a NARSR check why error occurred ret handle tx err ioi 14 NATSR check why error occurred ret handle jabber ld a 0x00 ioi 14 NATCR ld a 0x80 ioi ld NARR a ld a 0x80 ioi ld NATCR a ret The network port interrupt is automatically cleared by reading NACSR A sample interrupt handler is shown below read the interrupt status save status byte for later did receive error occur recover network status byte did transmit error occur did link change or jabber occur get current status to check which one did jabber condition occur get receiver status and respond accordingly get transmitter status and respond accordingly disable transmitter reset transmitter enable transmitter Chapter 20 10Base T Ethernet 207 20 3 5 Multicast Addressing A physical address match requires that the received frame address is a physical address that matches every bit of the programmed receive address A broadcast address match requires that all 48 bits of the received frame address be ones A multicast address match requires the received frame address to be a multicast address LSB of the address is one and a match in the multicast address filter The multicast address filter uses the six most significant bits of the CRC calculated on the receive address as an index into a 64 by 1 bit table writ
53. les counts les counts les counts les counts 258 spread les counts les counts 65 counts les counts 259 spread 65 counts les counts 65 counts les counts n 259 normal 1 260 counts The DMA channels on the Rabbit 4000 are designed to work with fixed I O addresses To allow DMA control of the PWM a separate PWM Block Access Register PWBAR and PWM Block Pointer Register PWBPR are available The pointer register contains the address of the PWM register to be accessed via the access register Each read or write of the access register automatically increments the pointer register through the sequence shown below Note that only the lower three bits of the pointer register actually change This allows the DMA to write to a fixed internal I O location but still program all of the PWM registers The pointer register can be written and read if necessary Normally the 240 Rabbit 4000 Microprocessor User s Manual pointer register is initialized to 0x88 the first PWM register and the DMA then transfers blocks of eight bytes to completely reprogram the PWM 0x88 gt 0x89 gt Ox8A gt 0x8B gt 0x8C gt 0x8D gt Ox8E gt Ox8F gt When the DMA destination address is the PWBAR the DMA request from the PWM is automatically connected to the DMA 23 1 1 Block Diagram Pulse Width Modulator erclk PWM Channel Width Register Interrupt
54. n present in this buffer descriptor which is now 12 bytes long 1 Use the link address field as a pointer to the next buffer descriptor This buffer descriptor is 16 bytes long 5 0 No special treatment for last byte Internal Source status byte written to initial buffer descriptor before last data 1 Internal Destination Last byte written to offset address for frame termination All others No effect 4 0 No interrupt on completing this transfer 1 Interrupt on completing this transfer 3 2 00 Source address is fixed internal I O two byte address 01 Source address is fixed external I O two byte address 10 Source address is memory three byte address auto decrement 11 Source address is memory three byte address auto increment 1 0 00 Destination address is fixed internal I O two byte address 01 Destination address is fixed external I O two byte address 10 Destination address is memory three byte address auto decrement 11 Destination address is memory three byte address auto increment 196 Rabbit 4000 Microprocessor User s Manual y Length 7 0 Register DOLOR Address z 0x0182 D1LOR Address z 0x0192 D2LOR Address 0x01A2 D3LOR Address 0x01B2 D4LOR Address 0x01C2 D5LOR Address 0x01D2 D6LOR Address 0x01E2 D7LOR Address 0x01F2 Bit s Value Description Bits 7 0 of the buffer length value are stored in this register The DMA does a 7 0
55. sleep modes 318 spectrum spreader 9 13 stack protection 52 system management 31 block diagram 32 Clocks iine 33 dependencies 33 Interrupts LL 33 onchip encryption RAM 31 operation periodic interrupt 34 real time clock 34 watchdog timer 35 other registers 31 register 31 GOCR register 31 GREV register 31 periodic interrupt 31 real time clock 31 register descriptions 36 Iegisters 32 watchdog timers 31 System User mode 283 dependencies 285 differences between System mode and User mode 283 inaccessible addresses in User MODE anti 285 interrupts 286 292 Opcodes 290 operation 287 complete operating system 288 enabling 289 memory protection 287 mixed operation 288 System User mode continued OVerVieW Lewn 283 register descriptions 294 TEQISTETS 284 use memory protection 287 T timers 107 block diagram 109 capabilities 108 clocks essem 110 dependencies
56. 0 Disable User Mode access to External Interrupt 1 I O address 0 0099 1 Enable User Mode access to External Interrupt 1 I O addresses 0 0099 0 0 Disable User Mode access to External Interrupt 0 I O address 0x0098 1 Enable User Mode access to External Interrupt 0 I O addresses 0 0098 Timer A User Enable Register TAUER Address 0x03A0 Bit s Value Description 7 0 Disable User Mode access to Timer A I O addresses OxOOAO Ox00AF 1 Enable User Mode access to Timer A I O addresses 0xX00A0 0x00AF 6 0 These bits are reserved and should be written with zeros Timer B User Enable Register TBUER Address 0x03B0 Bit s Value Description vi 0 Disable User Mode access to Timer I O addresses 0 00 0 0 00 1 Enable User Mode access to Timer B I O addresses 0 00 0 0 00 6 0 These bits are reserved and should be written with zeros Timer C User Enable Register TCUER Address 0x03F8 Bit s Value Description 7 0 Disable User Mode access to Timer I O addresses 0 0500 0 050 and 0 00 8 0 00 9 1 Enable User Mode access to Timer C I O addresses 0x0500 0x050F and Ox00F8 0x00F9 6 0 These bits are reserved and should be written with zeros Chapter 27 System User Mode 297 Serial Port A User Enable Register SAUER Address 0x03C0 Bit s Value Description i 0 Disable User Mode
57. 00 6 0 These bits are reserved and should be written with zeros 298 Rabbit 4000 Microprocessor User s Manual Serial Port F User Enable Register SFUER Address 0x03D8 Bit s Value Description 7 0 Disable User Mode access to Serial Port F I O addresses 0xX00D8 0x00DF 1 Enable User Mode access to Serial Port I O addresses 0x00D8 0x0ODF 6 0 These bits are reserved and should be written with zeros Enable Dual Mode Register EDMR Address 0x0420 Bit s Value Description 7 6 00 Default Rabbit 2000 3000 instruction set 01 This bit combination is reserved and must not be used 10 This bit combination is reserved and must not be used 11 Enhanced Rabbit 4000 instruction set 5 1 These bits reserved and should be written with zeros 0 0 Normal System Mode only operation 1 Enable System Normal operation Chapter 27 System User Mode 299 300 Rabbit 4000 Microprocessor User s Manual 28 SPECIFICATIONS 28 1 DC Characteristics Table 28 1 Preliminary DC Electrical Characteristics Parameter Symbol Min Typ Max Operating Temperature TA 40 C 85 C Storage Temperature 55 C 125 C Core Supply Voltage VDDcoRE 1 65 V 1 8V 1 90 V g Core Current 29 4912 MHz 25 C 6 0 mA 5 Core current 7 3728 MHz 25 IconE 3 7 mA Core c
58. 0x0000 Watchdog Timer Control Register WDTCR 0x0008 Watchdog Timer Test Register WDTTR 0x0009 Global Clock Modulator 0 Register GCMOR 0x000A Global Clock Modulator 1 Register GCMIR 0x000B Secondary Watchdog Timer Register SWDTR 0x000C Global Power Save Control Register GPSCR 0x000D Global Output Control Register GOCR 0 000 Global Clock Double Register GCDR 0 000 Instruction Data Register MMIDR 0x0010 Stack Segment Register STACKSEG 0 0011 Data Segment Register DATASEG 0x0012 Segment Size Register SEGSIZE 0x0013 Memory Bank 0 Control Register MBOCR 0x0014 Memory Bank 1 Control Register MBICR 0 0015 Memory Bank 2 Control Register MB2CR 0x0016 Memory Bank 3 Control Register MB3CR 0x0017 MMU Expanded Code Register MECR 0x0018 Memory Timing Control Register MTCR 0x0019 Stack Segment Low Register STKSEGL 0x001A Stack Segment High Register STKSEGH 0x001B Breakpoint Debug Control Register BDCR 0x001C Memory Alternate Control Register MACR 0x001D Data Segment Low Register DATSEGL 0 001 Chapter 27 System User Mode 285 Table 27 2 I O Addresses Inaccessible in User Mode continued Register Name Mnemonic Address Data Segment High Register DATSEGH 0x001F DMA registers 0x0100 0 01 Network Port A registers 0x0200 0 02 User Enable and Breakpoint registers 0x0300 0 03 Memory Protection registers 0x0400 OxO4FF 27 2 4 Interrupts The System Mode Violati
59. 0x53 Restart watchdog timer with 250 millisecond timeout Ox5F Restart the secondary watchdog timer The watchdog timer also contains a special test mode that speeds up the timeout period by clocking it with the peripheral clock instead of the 32 KHz clock This mode can be enabled by writing to WDTTR 4 3 4 Secondary Watchdog Timer The secondary watchdog timer is disabled on reset unless the reset occurs because the primary watchdog timer times out while the secondary watchdog timer is enabled The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing Ox5F to WDTCR The following steps explain how to use the secondary watchdog timer 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Write the desired timeout period to SWDTR This also enables the secondary watchdog timer 3 Restart the secondary watchdog timer by either writing the timeout period to SWDTR or writing Ox5F to WDTCR If the secondary watchdog timer counts down to zero a Priority 3 secondary watchdog interrupt will occur This interrupt request is cleared by writing a new timeout value to SWDTR A sample interrupt handler is shown below secwd isr push af determine why the interrupt occurred and take appropriate action ld a 0x40 timeout period of 0x40 32kHz 1 95ms ioi 1 SWDTR a Clear the interrupt request pop af ipres ret
60. 12 bytes Buffer Descriptor 12 bytes Buffer Descriptor 12 bytes Interrupt The advantage of the buffer array is that its descriptors require less memory than a full 16 byte descriptor The simplest version of the buffer array is a double buffer which is frequently used to provide a reserve buffer in case the application is slow in handling the first buffer once received in this case both buffers are enabled to interrupt on completion 182 Rabbit 4000 Microprocessor User s Manual 19 3 5 3 Linked List A linked list is similar to a buffer array except that 16 byte descriptors are used and the descriptors are not necessarily adjacent in memory The advantage of this mode is the ability to spread descriptors Linked List Initial Buffer Descriptor Address 16 bytes Link Address Buffer Descriptor 16 bytes Link Address Buffer Descriptor 16 bytes Interrupt Chapter 19 DMA Channels 183 19 3 5 4 Circular Queue A circular queue is a buffer array or linked list where the final buffer is linked back to the first buffer in the sequence This method allows for continuous reception of transfers with out having to reload the initial address for the DMA buffer descriptor sequence Circular Queue Initial Buffer Descriptor Address 16 bytes Interrupt Link Address Buffer Descriptor 16 bytes Interrupt Link Address Buffer Descriptor 16 bytes Interrupt Link Address
61. 16 Register 199 SAR nmm 138 155 Register 270 DMA x Destination SxSR asynch mode Breakpoint x Mask 2 Addr 7 0 Register 199 139 156 Register 270 DMA x Initial Addr 15 8 SxSR clocked serial mode Breakpoint Debug Control Register 194 ed 140 Register 268 DMA x Initial Addr 23 16 SxSR HDLC mode 157 Clocks 545 sie 10 Register 194 113 Global Clock Double DMA x Initial Addr 7 0 TACSR 5 112 Register 22 Register 194 ues 112 Global Clock Modulator 0 DMA x Length 15 8 TATXR 113 Register 21 Register 197 TAUER 297 Global Clock Modulator 1 DMA x Length 7 0 enne 120 Register 21 Register 197 Index 343 registers DMA channels continued DMA x Link Addr 15 8 Register 200 x Link Addr 23 16 Register 200 x Link Addr 7 0 Register 200 DMA x Source Addr 15 8 Register nes 198 DMA x Source Addr 23 16 Register eue 198 DMA x State Machine Register 195 DMA x Termination Byte Register 193 DMA x Termination Mask Register 193 external I O control 250 I O Bank x Control Register MR ERE EUR REUS 255 I O
62. 2 1 TXD TXD 10 TIMER CO TCLKF Table 10 2 Parallel Port C Pin Alternate Input Functions Pin Capture dote PC7 x RXA RXE PC6 m amp RXB RCLKE PC4 TCLKE PC3 RXC PC2 PCI RXD RCLKF TCLKF Chapter 10 Parallel Port 81 After reset the default condition for Parallel Port is four outputs the even numbered bits and four inputs the odd numbered bits For compatibility with the Rabbit 2000 and the Rabbit 3000 microprocessors these outputs are driven with a logic zero low on PC6 and a logic one high on PC4 PC2 and PCO When PCDR is read the value of the volt age on the pin is returned If the pin is an output the value it is set to is returned 10 1 1 Block Diagram Parallel Port C Data PCDR Serial Ports Tx Rx Clocks 10 1 2 Registers Register Name Mnemonic I O Address R W Reset Port C Data Register PCDR 0x0050 R W 00010101 Port Data Direction Register PCDDR 0x0051 01010101 Port Alternate Low Register PCALR 0 0052 00000000 Port Alternate High Register PCAHR 0x0053 00000000 Port Drive Control Register PCDCR 0x0054 R W_ 00000000 Port C Function Register PCFR 0x0055 00000000 82 Rabbit 4000 Microprocessor User s Manual
63. 3 the interrupt is generated but will not be handled until the processor drops to a lower priority In most cases a code execution interrupt will be handled at the end of the instruction in which the match occurred However because of the time required to perform a 24 bit address match in the processor a code execution breakpoint that is set on a single byte 2 clock instruction will not yet be enabled at the end of that instruction and the interrupt will instead occur at the end of the next instruction Note that a breakpoint may be forced to be pending by setting the corresponding bit in BDCR This feature allows a breakpoint request to be used as a virtual single step request by always setting the appropriate bit in the interrupt handler There is a particular sequence of instructions required to exit properly when the interrupt is left pending DMA transfers are treated as normal data reads and writes although the DMA transfer will complete before the interrupt is taken Breakpoints can be enabled for the User Mode the System Mode or both Another breakpoint feature is the ability to disable the RST 28h instruction The RST 28h vector was often used as a breakpoint feature by adding that instruction to code by enabling a bit in BDCR the RST 28h instruction will execute as a NOP instead providing an easy way to disable that type of breakpoint Note that hardware breakpoints do not differentiate between memory and I O accesses
64. 3 Other Registers Register Function GCSR Select peripheral clock mode PCFR PCALR PDFR PDALR Alternate port output selection PEFR PEALR 15 2 4 Interrupts A Timer C interrupt is enabled in TCCR and will occur whenever the count limit value is reached The interrupt request is cleared when TCCSR is read 124 Rabbit 4000 Microprocessor User s Manual 15 3 Operation The following steps explain how to set up a Timer timer 1 2 6 Select perclk 2 perclk 16 or countdown timer Al in TCCR Load the desired upper limit for the counter into TCDLR and TCDHR overall clock count per Timer C cycle will be the value loaded into the divider registers plus one Load the desired set and reset values for the Timer C outputs into the set and reset registers TCSxLR TCSxHR TCRxLR and TCRxHR If you intend to use DMA control of Timer C use TCBAR to access the Timer C register pointed to by TCBPR Enable the desired output pins for Timer C by writing to the appropriate parallel port function and alternate output registers Enable Timer C by writing a 1 to bit 0 of TCCSR 15 3 1 Handling Interrupts The following steps explain how an interrupt is used 2 Write the vector to the interrupt service routine to the internal interrupt table Configure TCCR to select the interrupt priority note that interrupts will be enabled once this value is set The interrupt r
65. A Phys Addr 7 0 Register NAPAOR 0x0210 W XXXXXXXX Network Port Phys Addr 15 8 Register NAPAIR 0x0211 W XXXXXXXX Network Port Phys Addr 23 16 Register NAPA2R 0x0212 W XXXXXXXX Network Port Phys Addr 31 24 Register NAPA3R 0x0213 W XXXXXXXX Network Port Phys Addr 39 32 Register NAPA4R 0x0214 W XXXXXXXX Network Port Phys Addr 47 40 Register NAPASR 0x0215 W XXXXXXXX Network Port A Multi Filter 7 0 Register NAMFOR 0x0218 R W XXXXXXXX Network Port A Multi Filter 15 8 Register NAMFIR 0x0219 R W XXXXXXXX Network Port A Multi Filter 23 16 Register NAMF2R 0x021A R W XXXXXXXX Network Port A Multi Filter 31 24 Register NAMF3R 0x021B R W XXXXXXXX Network Port A Multi Filter 39 32 Register NAMF4R 0x021C R W XXXXXXXX Network Port A Multi Filter 47 40 Register NAMFSR 0x021D R W XXXXXXXX Network Port A Multi Filter 55 48 Register NAMF6R 0 021 R W XXXXXXXX Network Port A Multi Filter 63 56 Register NAMF7R 0 021 R W XXXXXXXX Network Port A Multicast Hash Register NAMHR 0x0220 R 00000000 Network Port A Collision Detect Register NACDR 0 0221 R 00000000 Network Port A Alignment Error Register NAAER 0 0222 R 00000000 Network Port A CRC Error Register NACER 0x0223 R 00000000 Network Port Checksum 0 Register NACOR 0x0224 R 00000000 Network Port Checksum 1 Register NACIR 0x0225 R 00000000 Network Port A Missed Frame Register NAMFR 0x0226 R 00000000 204 Rabbit 4000 Mic
66. B8 A 19 0 Output Address Bus various various CPU Buses D 7 0 Bidirectional Data Bus various various WDTOUT Output Watchdog Timer Timeout 41 L4 Status amp STATUS 2 Fetch First 4 Cl Control Om je ee mus CSO Output Memory Chip Select 0 9 D3 Chip Selects CS1 Output Memory Chip Select 1 46 M5 CS2 Output Memory Chip Select 2 3 B2 Output JOEO Output Memorv Output Enable 0 5 C2 Enables OE1 Output Memorv Output Enable 1 94 D9 Write WEO Output Memory Write Enable 83 F12 Enables WEI Output Memory Write Enable 98 B12 BUFEN Output Buffer Enable 40 KA Control IORD Output I O Read Enable 39 M3 IOWR Output I O Write Enable 38 L3 PA 7 0 Input Output I O Parallel Port A 99 106 various PB 7 0 Input Output Parallel Port B 112 119 various Ports PC 7 0 Input Output Parallel Port C 61 73 66 70 various PD 7 0 Input Output Parallel Port D 52 57 59 60 various PE 7 0 Input Output T O Parallel Port E 28 31 34 37 various Chapter 29 Package Specifications and Pinout 327 Table 29 3 Rabbit 4000 Pin Descriptions Pin Group Pin Name Direction Function LQFP Pin TFBGA Ball TXD B3 TXD 4 Output Network Transmit 124 127 TXDD A4 Network TXDD A3 RXD 5 5 Input Network Receive 121 122 RXD 5 328 Rabbit 4000 Microprocessor User s Manual APPENDIX A PARALLEL PORT PINS WITH ALTERNATE FUNCTIONS A 1 Alternate Parallel Port Pin Outputs Table A
67. Generation Suppress and Spread Interrupt Request Output IL Select PyFR PWLxR PYAHR PWMxR 23 1 2 Registers Register Name Mnemonic Address R W Reset PWM LSB 0 Register PWLOR 0 0088 R W 00 PWM MSB 0 Register PWMOR 0x0089 PWM LSB Register PWLIR 0x008A 00 PWM MSB 1 Register PWMIR 0x008B PWM LSB 2 Register PWL2R 0 008 00 PWM MSB 2 Register PWM2R 0x008D PWM LSB 3 Register PWL3R 0 008 R W 00 PWM MSB 3 Register PWM3R 0 008 PWM Block Access Register PWBAR 0 00 8 W XXXXXXXX PWM Block Pointer Register PWBPR 0 00 9 W 10001000 Chapter 23 Pulse Width Modulator 241 23 2 Dependencies 23 2 1 Pins Each PWM channel can be output on up one of three pins which can be selected via the parallel port alternate output registers 23 2 2 Clocks PWM Output Pins Channel 0 PC4 PD4 PE4 Channel 1 5 PD5 PES Channel 2 6 PD6 PE6 Channel 3 PC7 PD7 PE7 The PWM counter is clocked from the output of Timer 9 and can run at rates from perclk 2 down to perclk 512 by writing the appropriate value to TATOR 23 2 3 Other Registers Register Function TATOR Time constant for PWM clock PCFR PCAHR PDFR PDAHR Alternate port output selection PEFR PEAH
68. Grid Array aee eee rete a dee need 324 202 PInOUt eor PU B p AE RD ed 324 29 2 2 Mechanical Dimensions and Land Pattern 325 29 3 Rabbit Pin Descriptions ett e eee Pepe Poder iieiaei 327 Appendix Parallel Port Pins with Alternate Functions 329 A 1 Alternate Parallel Port Pin Outputs 329 2 Alternate Parallel Port Pin Inputs erede ee eee pedes 331 Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds 333 B ESD SensitiVity niet e ertet tt e t Neteco p eite eti etie 334 B 1 1 ESD Design Guidelines iecore eren eterno aie PD een 334 S bone verte redit et a eu e tree tee teret ette bere 335 Index 339 Rabbit 4000 Microprocessor User s Manual 1 THE RABBIT 4000 PROCESSOR 1 1 Introduction Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium scale single board computers The first microprocessors were the Rabbit 2000 and the Rabbit 3000 The latest microprocessor is the Rabbit 4000 Rabbit microprocessor designers have had years of experience using Z80 Z180 and HD64180 microprocessors in small single board computers The Rabbit microprocessors share a similar architecture and a high degree of compatibility with these microprocessors but represent a vast improvement Th
69. Handshake Control Register 253 I O Handshake Select Register 254 I O Handshake Timeout Register 254 Parallel Port C Alternate High Register 258 Parallel Port C Alternate Low Register 257 Parallel Port C Function Register 258 Parallel Port D Alternate High Register 260 Parallel Port D Alternate Low Register 259 Parallel Port D Function Register 260 Parallel Port E Alternate High Register 262 Parallel Port E Alternate Low Register 261 Parallel Port E Function Register 262 Slave Port Control Register m 256 external interrupts 70 Interrupt x Control Register Brust Pb IPS Reb 71 registers continued input capture channels 221 Input Capture Control Register 226 Input Capture Control Status Register 225 Input Capture LSB x Register 228 Input Capture MSB x Register 229 Input Capture Source x Register se 228 Input Capture Trigger x Register 227 low power operation 272 Global Clock Double Register 282 Global Control Status Register 280 Global Power Save Control Register 281 memory management 44 46 Advanced Chip Select x Contr
70. ISCS p EE EE i Tsu SCS I Th SCS SA1 SAO e Tsu SA ur Th SA SWR gt Tw SWR SDI7 0 EL kT SD oi Tsu SD SRD 1 1 Tsu SRD SWR Figure 18 2 Slave Port R W Timing Diagram 168 Rabbit 4000 Microprocessor User s Manual The following table explains the parameters used Figure 18 2 Symbol Parameter ae PR Tsu SCS SCS Setup Time 9 Th SCS SCS Hold Time 0 Tsu SA SA Setup Time 5 Th SA SA Hold Time 0 Tw SRD SRD Low Pulse Width 40 Ten SRD SRD to SD Enable Time 0 Ta SRD SRD to SD Access Time 30 Tdis SRD SRD to SD Disable Time 15 Tsu SRW SRD SWR High to SRD Low Setup Time 40 Tw S WR SWR Low Pulse Width 40 Tsu SD SD Setup Time 10 Th SD SD Hold Time 5 Tsu SRD SWR SRD High to SWR Low Setup Time 40 Chapter 18 Slave Port 169 18 4 Register Descriptions Slave Port Data x Registers SPDOR Address 0x0020 SPD1R Address 0x0021 SPD2R Address 0x0022 Bit s Value Description 7 0 Read The corresponding byte of the slave port is read Write The corresponding byte of the slave port is written Slave Port Status Register SPSR Address 0x0023 Bit s Value Description 7 0 Processor wrote to SPSR 1 Master wrote to Dat
71. Initial Address 23 16 Register DyIA2R 0 01 R W State Machine Register DySMR 0 0120 2 8 11111111 Control Register DyCR 0 0171 2 8 00000000 DMA y Buffer Length 7 0 Register DyLOR 0 0172 z y 8 R W XXXXXXXX DMA y Buffer Length 15 8 Register DvLIR 0 0173 2 8 R W XXXXXXXX DMA Source Address 7 0 Register DySAOR 0 0124 z y 8 W XXXXXXXX DMA y Source Address 15 8 Register DySAIR 0 0125 z2y 8 XXXXXXXX DMA y Source Address 23 16 Register DySA2R 0 0126 2 8 W XXXXXXXX DMA y Destination Address 7 0 Register DyDAOR 0 0128 z y 8 W XXXXXXXX DMA y Destination Address 15 8 Register DyDAIR 0 0129 z y 8 W XXXXXXXX DMA Destination Address 23 16 Register DyDA2R 0 012 z y 8 W XXXXXXXX DMA y Link Address 7 0 Register DyLAOR 0 012 z y 8 R W xxxxxxxx DMA Link Address 15 8 Register DyLAIR 0 012 2 8 R W xxxxxxxx DMA y Link Address 23 16 Register DyLA2R 0 012 z y 8 R W NOTE The DMA expresses the DMA channel number 0 7 176 Rabbit 4000 Microprocessor User s Manual 19 2 Dependencies 19 2 1 I O Pins External DMA Request 0 can be enabled from pins PD2 PE2 or PE6 External DMA Request can be enabled from pins PD3 PE3 or PE7 The DMA can use either the memory management unit or the auxiliary I O bus to perform its transfers and so will use t
72. Pin Divide by 2 Real Time Clock Periodic Interrupt Asynch Serial Bootstrap Watchdog Timer 2 1 2 Registers Register Name Mnemonic Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Global Clock Modulator 0 Register GCMOR 0x000A W 00000000 Global Clock Modulation 1 Register GCMIR 0x000B W 00000000 Global Clock Double Register GCDR 0 000 R W 00000000 10 Rabbit 4000 Microprocessor User s Manual 2 2 Dependencies 2 2 1 Pins The main clock input is on the CLKI pin There is an internal Schmitt trigger on this pin to remove problems with noise on slowly transitioning signals The main clock disable output is on the CLKIEN pin Its state is changed by one of the bit combinations of bits 4 2 in GCSR The 32 kHz clock input is on the CLK32K pin There is an internal Schmitt trigger on this pin as well The peripheral clock or peripheral clock divided by 2 may be optionally output on the CLK pin by enabling it via bits 7 6 in GOCR The Ethernet clock may be input on pin PEG by enabling it via bits 7 6 in It may be set to use the processor clock or processor clock divided by 2 in that register as well Note that there is not an internal Schmitt trigger on PE6 it is highly recommended that an exter nal Schmitt trigger be placed on this pin if it is to be used as the Ethernet clock 2 2 2 Other Registers Register Function GOCR Used to
73. Port C bit 1 alternate output 0 TXD 01 Parallel Port C bit 1 alternate output 1 I1 10 Parallel Port bit 1 alternate output 2 TIMER 11 Parallel Port C bit 1 alternate output 3 RCLKF 1 0 00 Parallel Port C bit 0 alternate output 0 TXD 01 Parallel Port bit 0 alternate output 1 IO 10 Parallel Port C bit 0 alternate output 2 TIMER CO 11 Parallel Port C bit 0 alternate output 3 TCLKF Chapter 24 External I O Control 257 Parallel Port Alternate High Register PCAHR Address 0x0053 Bit s Value Description 7 6 00 Parallel Port C bit 7 alternate output 0 TXA 01 Parallel Port bit 7 alternate output 1 17 10 Parallel Port C bit 7 alternate output 2 PWM3 11 Parallel Port C bit 7 alternate output 3 SCLKC 5 4 00 Parallel Port C bit 6 alternate output 0 TX A 01 Parallel Port C bit 6 alternate output 1 16 10 Parallel Port C bit 6 alternate output 2 PWM2 11 Parallel Port bit 6 alternate output 3 3 2 00 Parallel Port C bit 5 alternate output 0 TXB 01 Parallel Port bit 5 alternate output 1 15 10 Parallel Port C bit 5 alternate output 2 PWM1 11 Parallel Port bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port C bit 4 alternate output 0 TXB 01 Parallel Port C bit 4 alternate output 1 I4 10 Parallel Port C bit 4 alternate output 2 1
74. QRD2A RXC RXF PD2 DREQO QRD2B SCLKC PDI Yes INTI QRDIA RXD RCLKF PDO INTO QRDIB SCLKD TCLKF PE7 Yes DREQI Yes QRD2A SCS RXA RXE 6 DREQO QRD2B PES Yes INTI Yes QRDIA RXB RCLKE Appendix A Parallel Port Pins with Alternate Functions 331 Table A 3 Alternate Parallel Port Pin Inputs continued Pin AURA DMA jen P Es shake Decoder A D E F PE4 INTO Yes ORDIB TCLKE PE3 Yes DREQI Yes QRD2A RXC RXF 2 DREQO Yes QRD2B 5 INTI Yes QRDIA RXD 0 INTO Yes ORDIB SCLKD TCLKF 332 Rabbit 4000 Microprocessor User s Manual APPENDIX RABBIT 4000 ESD DESIGN GUIDELINES AND BUG WORKAROUNDS The Rabbit 4000 began shipping in 2006 and has undergone one minor respin since that time Several bugs were found in the design after the chip was produced and are discussed in this appendix Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds 333 B 1 ESD Sensitivity A small number of the original Rabbit 4000 LQFP processors had somewhat greater ESD sensitivity between the VBAT pin and VSScorg making the VBAT pin more sensitive to ESD events than any of the other pins Devices with the following markings have this sensitivity e AT582
75. Read The current value of the 48 bit real time clock counter is returned Write Writing to the RTCOR transfers the current count of the real time clock to a holding register while the real time clock continues counting Watchdog Timer Control Register WDTCR Address 0x0008 Bit s Value Description 7 0 Ox5A Restart the watchdog timer with a 2 second timeout period 0x57 Restart the watchdog timer with a 1 second timeout period 0x59 Restart the watchdog timer with a 500 ms timeout period 0x53 Restart the watchdog timer with a 250 ms timeout period 0 5 Restart the secondary watchdog timer other No effect on watchdog timer or secondary watchdog timer Chapter 4 System Management 37 Watchdog Timer Test Register WDTTR Address 0x0009 Bit s Value Description 7 0 0 51 Clock the least significant byte of the watchdog timer from the peripheral clock 0 52 Clock the most significant byte of the watchdog timer from the peripheral clock 0x53 Clock both bytes of the watchdog timer in parallel from the peripheral clock Disable the watchdog timer This value by itself does not disable the watchdog 0x54 timer Only a sequence of two writes where the first write is 0x51 0x52 or 0x53 followed by a write of 0x54 actually disables the watchdog timer The watchdog timer will be re enabled by any other write to this register other Norm
76. SxLR Latched Tx Buffer Tx Buffer 4 bytes SxDR SxAR SxLR Rx Pins Tx Pins Serial Port Status SxSR Interrupt Request 146 Rabbit 4000 Microprocessor User s Manual 17 1 2 Registers Register Name Mnemonic I O Address R W Reset Serial Port E Data Register SEDR 0 00 8 R W XXXXXXXX Serial Port E Address Register SEAR 0 00 9 W XXXXXXXX Serial Port E Long Stop Register SELR 0x00CA W XXXXXXXX Serial Port E Status Register SESR 0 00 R 0xx00000 Serial Port E Control Register SECR 0 00 xx000000 Serial Port E Extended Register SEER 0x00CD R W 00000000 Serial Port E Divider Low Register SEDLR 0 00 Serial Port E Divider High Register SEDHR 0 00 R W OXXXXXXX Serial Port F Data Register SFDR 0 0008 R W XXXXXXXX Serial Port F Address Register SFAR 0x00D9 W XXXXXXXX Serial Port F Long Stop Register SFLR 0x00DA W XXXXXXXX Serial Port F Status Register SFSR 0x00DB R 0 00000 Serial Port Control Register SFCR 0x00DC R W xx000000 Serial Port F Extended Register SFER 0x00DD R W 00000000 Serial Port F Divider Low Register SFDLR 0 00 Serial Port F Divider High Register SFDHR 0 00 R W OXXXXXXX Chapter 17 Serial Ports 147 17 2 Dependencies 17 2 1 I O Pins Serial Port E can transmit on parallel port pins PC6 PD6 or PE6 and can receive o
77. TERRI UIS 251 242253 Other REGISTELS cott rete reto tae tyne cease 251 24 2 4 Interrupts secet A RP eae Ade M 251 Rabbit 4000 Microprocessor User s Manual 24 3 Operation e eere ee g 252 24 3 VO BUS ce eri RT tee ire e EHE RR pe EE rhe 252 24 3 2 WO Strobes eee tr tede ete reote ee a Mere 252 24 3 5 Handshake si ii bien beet dip ted ee Pen e 252 24 4 Register Descrptions ie etie nep he 253 Chapter 25 Breakpoints 263 25 Dm PEE nempe 263 25 1 1 Block a N 264 23 1 2 RegIStets 265 25 2 Dependen ies e a A se ea 266 23 21 T O PIS nig ete p REPRE PO DR A a T 266 VEA CIE 266 28 23 70 266 25 20 Interr pts oe reist ree Ute 266 25 8 Operation enu 266 25 3 Interrupts nere tete idee e eet Ree ET 266 25 32 Example ISR eia reete petite o trie 267 25 4 Register Descriptions nore pie eit CER ee 268 Chapter 26 Low Power Operation 271 26 T OVervie Waco S oec ota del EU e mE oui ES 271 POEM Sous E
78. The byte is available in the buffer after the final bit is sampled The status of each serial port is available in the Serial Port Status Registers SxSR and contains information on whether a received byte is available the receive buffer was over run a parity error was received and the transmit buffer is empty or busy sending a byte The status is updated when the final bit of a received byte is sampled or when the final bit of a transmitted byte is sent out Serial Ports E and F support the HDLC mode with either an internal or an external clock separate pins may be used for the transmit and receive clocks or the transmit and receive clocks may be combined onto a single pin The HDLC packet flag encapsulation flag escapes and CRC calculation and check are handled automatically by the processor The serial port can detect end of frame short frame and CRC errors Interrupts are generated by the reception of an end of frame at the end of a transmission of a CRC by an abort sequence or by a closing flag Transmit and receive operations are essentially automatic The standard CRC CCITT polynomial x 1 is implemented for the CRC with the generator and checker preset to all ones It is possible to send packets with or without a CRC appended It is also possible to select whether an abort or flag will be transmitted if the transmitter underflows A packet under transition can be aborted and the abort pattern sent The idle co
79. The pro cessor skips the read of those bytes if a 12 byte descriptor is selected and always skips the reads of the bytes marked not used Table 19 1 DMA Buffer Descriptor Byte 0 Byte 1 Byte 2 Byte 3 Bytes 0 3 Frame Status Channel Control Buffer Length 15 0 Bytes 4 7 Source Address 23 0 Not Used Bytes 8 11 Destination Address 23 0 Not Used Bytes 12 15 Link Address 23 0 Not Used It is possible to abort a DMA transfer by writing the appropriate bit to the halt register DMHR It is also possible to restart a DMA transfer using the already loaded register values by writing to DMCSR The following steps explain how to set up a DMA channel 1 Select the DMA transfer and interrupt priorities by writing to DMCR 2 Select the DMA channel priority maximum bytes per burst and minimum clocks between bursts by writing to DMTCR 3 Write the interrupt vector for the interrupt service routine to the external interrupt table 4 Enable an external request line by writing to DMROCR or DMRICR Make sure that the pin selected is set up as an input Note that this enable will be logical ANDed to any internal DMA enables if the DMA transfer is to from an internal peripheral 5 Enable the internal timed transfer request by writing to DTRCR Select the divider value by writing to DTRDLR and DTRDHR Note that this enable will be logical ANDed to any internal DMA enables if the DMA transfer is to from
80. Timer B peripheral consists of a ten bit free running up counter two match registers and two step registers Timer B is driven by perclk 2 by perclk 16 or by the output of timer 1 Timer generates output pulse whenever the counter reaches the match value This output pulse can generate an interrupt and will set a status bit in the status reg ister The processor may then write a new value to the match register This allows Timer B to be used for pulse width or pulse position modulation because the outputs of Timer B can clock the outputs on Parallel Ports D and E The compare value comes from either the match register or the value internally generated via the step register When using the match register a new match value must be written to the match register after each match condition LSB first When using the step register the hardware automatically calculates the next match value by adding the contents of the step register to the current match value This allows Timer B matches to be generated at regular periods without calculating the new match value during the interrupt service routine 14 1 1 Block Diagram Timer B perclk 2 perclk 16 Interrupt Interrupt Timer 1 Counter Generation Request Timer Bx Parallel Ports Timer Bx Reload Registers TBMxR TBLxR TBSMxR TBSLxR Chapter 14 Timer B 115 14 1 2 Registers Register Name Mnemonic I O Address R W Reset Timer B Contro
81. Value Description 7 0 The receive data register is empty 1 There is a byte in the receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 6 0 The byte in the receive buffer is data received with a valid stop bit 1 The byte the receive buffer is address or a byte with a framing error If an address bit is not expected and the data in the buffer is all zeros this is a break 5 0 The receive buffer was not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 The byte in the receive buffer has no parity error or was not checked for parity 1 The byte in the receive buffer had a parity error 3 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when 1 the transmitter takes a byte from the transmit buffer Transmit interrupts cleared when the transmit buffer is written or any value which will be ignored is written to this register 2 0 The transmitter is idle The transmitter is sending a byte An interrupt is generated when the transmitter 1 clears this bit which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty 1 0 00 These bits are always zero in async mode 156 Rabbit 4000 Microprocessor User s Manual Serial Port x Status Register SESR Address 0x00CB
82. Write transferred to the port output register on the next rising edge of the peripheral clock 96 Rabbit 4000 Microprocessor User s Manual 12 PARALLEL PORT 12 1 Overview Parallel Port E is a byte wide port with each bit programmable for data direction and drive level These are simple inputs and outputs controlled and reported in the Port E Data Register PEDR All of the Parallel Port E pins have alternate output functions and all of them can be used as inputs to various on chip peripherals When used as outputs the Parallel Port E bits are buffered with the data written to PEDR transferred to the output pins on a selected timing edge Either the peripheral clock or the outputs of Timer 1 Timer Bl or Timer B2 can be used for this function with each nib ble of the port having a separate select field to control this timing Each bit can either be programmed as open drain or driven high and low Because of the buffered nature of Parallel Port E using a read modify write type of opera tion can lead to old data being written to PEDR To alleviate this potential problem each bit of the port can be written individually using a separate address for each bit Bit 7 of Parallel Port E is used as the default chip select input for the slave port when the slave port is enabled either for parallel bootstrap or under program control Table 12 1 Parallel Port E Pin Alternate Output Functions
83. XR esc eme 228 PDALR 92 259 BxCR eei 268 ICMXR 5 eene 229 PDBOR iss eme 94 BxMOR 270 ICSXR ed 228 PDBIR eese 94 270 nme 227 PDB2R 95 BxM2R 270 ICUER iie 295 PDB3R ik iii in 95 DATASEG 54 THOR 253 PDBAR eme 95 DATASEGH 54 nee 254 PDBSR eee 95 DATASEGL 54 nS 254 PDBOR wissiet 96 DMALR 187 IOXCR iii 255 PDB7R 96 DMGR nmm 188 IUER 297 PDGR 93 187 71 PDDGR 94 DMHR 187 MACR nee 57 PDDDR men 94 DMROCR 190 MBXCR 55 PDDR sissa 92 DMRICR 191 MECR 56 PDER unen 94 260 DMTCR 189 MMIDR 53 PDUER iii 295 DIRER 192 56 PEARR 103 262 DTRDHR 192 NAAER 218 PEALR 102 261 DTRDLR 192 NACOR eese 218 104 DXBER 188 NACIR 218 PEBLR iii nee 104 DxBUOR 193 217 PEB2R 105 DxBUIR 194 NACE
84. access to Serial Port A I O addresses 0 00 0 0 00 7 1 Enable User Mode access to Serial Port A I O addresses 0x00C0 0x00C7 6 0 These bits are reserved and should be written with zeros Serial Port B User Enable Register SBUER Address 0x03D0 Bit s Value Description 7 0 Disable User Mode access to Serial Port B I O addresses 0xX00D0 0x00D7 1 Enable User Mode access to Serial Port B I O addresses 0x00D0 0x00D7 6 0 These bits are reserved and should be written with zeros Serial Port C User Enable Register SCUER Address 0x03E0 Bit s Value Description 7 0 Disable User Mode access to Serial Port I O addresses 0 00 0 0 00 7 1 Enable User Mode access to Serial Port I O addresses 0 00 0 0 00 7 6 0 These bits are reserved and should be written with zeros Serial Port D User Enable Register SDUER Address 0x03F0 Bit s Value Description 7 0 Disable User Mode access to Serial Port D I O addresses 0xOOFO 0x00F7 1 Enable User Mode access to Serial Port D I O addresses 0xOOFO 0x00F7 6 0 These bits are reserved and should be written with zeros Serial Port E User Enable Register SEUER Address 0x03C8 Bit s Value Description 7 0 Disable User Mode access to Serial Port E I O addresses 0 00 8 0 00 1 Enable User Mode access to Serial Port E I O addresses 0 00 8 0
85. address offset to use if SEGSIZ 7 4 lt Addr 15 12 lt Write OxE Data Segment Register DATSEG Address 0x0012 Bit s Value Description 7 0 Read The current contents of this register are reported Write Eight LSBs MSBs are set to zero by write of physical address offset to use if SEGSIZ 3 0 lt Addr 15 12 lt SEGSIZ 7 4 Data Segment Low Register DATSEGL Address 0x001E Bit s Value Description 7 0 Eight LSBs of physical address offset to use if SEGSIZ 3 0 lt Addr 15 12 lt SEGSIZ 7 4 Data Segment High Register DATSEGH Address 0x001F Bit s Value Description 74 These bits reserved and should always be written as zero These bits always return zeros when read 3 0 Four MSBs of physical address offset to use if SEGSIZ 3 0 lt Addr 15 12 lt SEGSIZ 7 4 54 Rabbit 4000 Microprocessor User s Manual Segment Size Register SEGSIZ Address 0x0013 Bit s Value Description 7 0 Read The current contents of this register are reported 7 4 Write Boundary value for switching from DATSEG to STKSEG for translation 3 0 Write Boundary value for switching from none to DATSEG for translation Memory Bank x Conirol Register MBOCR Address 0x0014 MB1CR Address 0x0015 MB2CR Address 0 0016 Address 0 0017 Bit s Value Description 7
86. and the transmit buffer is empty 1 0 00 These bits are always zero in async mode Chapter 16 Serial Ports D 139 Serial Port x Status Register SASR Address 0x00C3 Clocked Serial Mode Only SBSR Address 0x00D3 SCSR Address 0x00E3 SDSR Address 0x00F3 Bit s Value Description 7 0 The receive data register is empty 1 There is a byte the receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 6 0 This bit is always zero in the clocked serial mode 5 0 The receive buffer was not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 This bit is always zero in the clocked serial mode 3 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when 1 the transmitter takes a byte from the transmit buffer Transmit interrupts cleared when the transmit buffer is written or any value which will be ignored is written to this register 2 0 The transmitter is idle The transmitter is sending a byte An interrupt is generated when the transmitter 1 clears this bit which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty 1 0 00 These bits are always zero in the clocked serial mode 140 Rabbit 4000 Microprocessor Us
87. bit as an output is driven high and low 1 The corresponding port bit as an output is open drain Parallel Port D Data Direction Register PDDDR Address 0x0067 Bit s Value Description 7 0 0 The corresponding port bit is input 1 The corresponding port bit is an output Parallel Port D Bit 0 Register PDBOR Address 0x0068 Bit s Value Description 7 1 These bits are ignored The port buffer bit 0 is written with the value of this bit The port buffer will be 0 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port D Bit 1 Register PDB1R Address 0x0069 Bit s Value Description 7 2 0 These bits are ignored The port buffer bit 1 is written with the value of this bit The port buffer will be 1 Write transferred to the port output register on the next rising edge of the peripheral clock 94 Rabbit 4000 Microprocessor User s Manual Parallel Port D Bit 2 Register PDB2R Address 0x006A Bit s Value Description 7 3 1 0 These bits are ignored The port buffer bit 2 is written with the value of this bit The port buffer will be 2 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port D Bit 3 Register PDBS3R Address z 0x006B Bit s Value Description
88. bits are cleared they cannot cause an interrupt The proper rule to follow is for the interrupt routine to handle all bits that it sees set 108 Rabbit 4000 Microprocessor User s Manual 13 1 1 Block Diagram Timer A Parallel Ports D E Control Timer B percik Timer C perclk 2 Timer A1 Serial Ports Timer A7 Input Capture 2 Quadrature Timer A10 Decoder Timer Ax Input Clock Output Interrupt Interrupt Generation Request TACR TACSR Reload Register TATXR Chapter 13 Timer A 109 13 1 2 Registers Register Name Mnemonic Address R W Reset Timer A Control Status Register TACSR 0x00A0 R W 00000000 Timer A Prescale Register TAPR 0x00A1 R W xxxxxxxl Timer A Time Constant 1 Register TATIR 0x00A3 Timer A Control Register TACR 0x00A4 R W 00000000 Timer A Time Constant 2 Register TAT2R 0x00A5 Timer Time Constant 8 Register TAT8R 0x00A6 Timer Time Constant 3 Register TAT3R 0x00A7 Timer Time Constant 9 Register TATOR 0x00A8 Timer Time Constant 4 Register TAT4R 0x00A9 Timer A Time Constant 10 Register 10 0x00AA Timer Time Constant 5 Register TATSR 0 00 Timer A Time Constant 6 Register TAT6R 0x00AD Timer
89. by the initial address registers not necessarily the buffer descriptor that is currently being used These features allow an application to automatically send and receive packets via DMA only requiring direct handling of a packet when an error occurs 19 3 6 2 DMA with Ethernet The Ethernet network peripheral also receives special handing by the DMA When the DMA destination is the network data register the final byte of the transfer will be written to the last data register NALDR as required to complete an Ethernet packet and append the CRC value In addition the value in the network status register NASR will be written to the status byte in the buffer descriptor pointed to by the initial address registers not necessarily the buffer descriptor that is currently being used These features allow the processor to only handle interrupts when an error occurs 19 3 6 3 DMA with PWM and Timer C The PWM and Timer C peripherals have special support for DMA the block access and pointer registers in each of these peripherals provide a means for the DMA to update the settings of these peripherals at some desired rate This allows complex PWM waveforms to be generated by using the DMA timed request to update the PWM duty cycles at regular intervals 19 3 7 DMA Bug Workarounds Appendix B 2 19 3 7 1 DMA HDLC Ethernet Interaction A specific bug can manifest itself when the following conditions are present The HDLC or Ethernet p
90. can be write protected against accidental writes by user code and stack over underflows can be trapped by high priority interrupts Security features were also introduced in the Rabbit 4000 Portions of the new instruction set were introduced to dramatically increase encryption algorithm speeds and 32 bytes of battery backed onchip encryption RAM store an encryption key away from prying eyes The Rabbit 4000 has new peripherals DMA access and on chip Ethernet The Rabbit 4000 supports eight channels of DMA access to external memory internal I O addresses and the auxiliary I O bus Directing a DMA channel to or from an internal peripheral such as a serial port or the Ethernet port automatically connects DMA enable signals Burst size priority and guaranteed cycles for the processor are all under program control The Rabbit 4000 contains a fully featured 10Base T Ethernet peripheral Designed to operate with the DMA peripheral the Ethernet peripheral is fully compliant with the 802 3 Ethernet standard including support for auto negotiation link detection multicast filter ing and broadcast addresses All digital components of the 10Base T MAC and PHY are present inside the Rabbit 4000 all that is needed to interface to an Ethernet network is some simple analog filtering and wave shaping components Chapter 1 The Rabbit 4000 Processor 3 1 3 Block Diagram o
91. clocks minimum 56 Rabbit 4000 Microprocessor User s Manual Memory Alternate Control Register MACR Address 0x001D Bit s Value Description 7 6 These bits are reserved and must not be used 5 4 00 Normal 8 bit operation for CS1 Use MBxCR for wait states unless Page Mode 01 Advanced 16 bit operation for CS1 Enable prefetch mechanism for instructions and word write accelerator for 16 bit write operations Enable byte lane swapping for byte data reads Byte writes are not supported Only aligned word writes to CS1 are allowed Use ACSICR for wait states 10 Enable basic 16 bit operation for CS1 Reads and writes are still byte wide but byte lane swapping is enabled for reads Data is replicated for writes Use MBxCR for wait states unless Page Mode Advanced 16 bit operation for CS1 Enable prefetch mechanism for instructions and word write accelerator for 16 bit write operations Enable byte lane swapping for byte data reads Byte writes are supported Use ACSICR for wait states Page mode operation disabled for CS1 Page mode operation enabled for CS1 Pages are 16 bytes Page mode accesses for program fetches only Use ACSICR for wait states 2 1 00 Normal 8 bit operation for CSO Use MBxCR for wait states unless Page Mode 01 Advanced 16 bit operation for 50 Enable prefetch mechanism for instructions and word write accelerato
92. consecutive banks each of which can be mapped to an individual chip select enable strobe pair The banks can be set for equal sizes ranging from 128KB up to 4MB providing a total physical memory range from 512KB up to 16MB Figure 5 1 shows a sample configuration OxFFFFF 1 wait state l Memorv Bank 3 CS2 256KB 0x86 OE1 SRAM 0 0000 OxBFFFF 0 wait states Memory Bank 2 51 2 0xC5 OE1 WE 0 80000 7 1 MB1CR 0xCO 0 wait states 0x40000 CSO Ox3FFFF OEO WEO Memory Bank 0 MBOCR 0xCO 0x00000 Figure 5 1 Mapping Rabbit 4000 Physical Memory Space Chapter 5 Memory Management 41 Either of the two most significant address bits which used to select the quadrant can be inverted providing the ability to bank switch other pages from a larger memory device into the same memory bank Code is executed in the 64KB logical memory space which 15 divided into four segments root data stack and XMEM The root segment is mapped directly to physical address 0 000000 while the data and stack segments can be mapped to 4KB boundaries anywhere in the physical space The boundaries between the root and data segments and the data and stack segments can be adjusted in 4KB blocks as well The XMEM segment is a fixed 8KB and points to a physical memory address specified in the XPC register It is possible to run code in the XMEM window provi
93. control the priority between separate DMA channels There are three channel priority options in the Rabbit 4000 The first is fixed priority after every byte where the priority of each channel is equal to its number i e if both DMA Channels 3 and 4 have a pending transfer request DMA Channel 4 will always be enabled first If at any point a channel with higher priority than the one currently transferring has a DMA request pending the current transfer will be terminated and the new channel s transfer will start With this setting DMA Channel 7 will always have priority over all other channels and DMA Channel 0 will transfer only if no other channels have pending requests The other two settings rotate the priority between channels as shown in Table 19 4 after the seventh rotation the priority sequence restarts at the top of the table One option is to rotate priority after every byte analogous to the fixed priority setting The priority list is updated after each byte transferred and if a higher priority channel has a pending request the current transfer will be terminated and the new channel transfer will start The other option is to rotate after every burst this will guarantee that reasonable amounts of data are transferred by each channel before a switchover occurs Table 19 4 Rotating DMA Channel Priority Rotation Channel Priority High to Low Initial and eighth 7 6 5 4 3 2 1 0 First 6 5 4 3 2
94. from interrupts Interrupts SYSCALL RST 27 3 4 Enabling the System User Mode User Mode Application code User defined interrupts The following steps describe how to enable the System User Mode 1 If a peripheral needs to be accessed while in User Mode write to the appropriate user enable register to allow that access 2 Write a 1 to bit 0 of EDMR to enable System User Mode 3 Execute the SETUSR instruction to enter User Mode After the User Mode is entered the limitations described earlier are in effect writes to protected registers will be ignored Priority 3 is not available and executing an IDET will cause a System Mode Violation interrupt Other features such as write protection may be effect for user mode as well Chapter 27 System User Mode 289 27 3 5 System User Mode Instructions Seven instructions exist primarily to support the System User Mode and are listed in Table 27 3 Note that IDET shares the value of LD E E in the opcode table and will always perform that operation but will have special behavior when the System User Mode is enabled and the processor is in System Mode In addition if the ALTD prefix appears before the instruction LD E E is always executed and the special behavior does not occur Table 27 3 System User Mode Instructions Instruction Bytes clk SZVC Operation Priv SETUSR 2 4 l l l SU SU 5 0 0x01 Yes PUSH SU 2 9
95. high 100 RXD single ended true input RXD not used by receiver 110 RXD single ended negative input RXD not used by receiver RXD singled ended true input RXD is the valid signal qualifier xxl RXD is XORd with NAPCR 7 and RXD is XORd with NAPCR 6 to provide level inversion 4 0 These bits are unused and should be written with zeros Network Port A Pin Conirol Register NAPCR Address 0x0208 network port clock disabled in NACR Bit s Value Description 7 6 These bits are unused and should be written with zero 5 Current state of TXDD Write Drive TXDD with value 4 Read Current state of TXD Write Drive TXD with value 3 Read Current state of TXDD Write Drive TXDD with value 2 Read Current state of TXD Write Drive TXD with value 1 Read Current state of RXD Write Ignored 0 Read Current state of RXD Write Ignored Chapter 20 10Base T Ethernet 215 Network Port A Transmit Control Register NATCR Address 0x020A Bit s Value Description 7 0 Disable transmitter 1 Enable transmitter 6 0 DMA request when FIFO is half empty 1 DMA request when FIFO is one fourth empty 5 0 These bits are reserved and should be written with zeros Network Port A Receive Control Register NARCR Address 0x020B Bit s Value Description 7 0 Disable receiver 1 Enable receiver 6 0 DMA request wh
96. in the Rabbit 4000 can be run in six different modes using the main oscillator full speed divided by 2 4 6 or 8 and the processor clock divided by 8 with the peripheral clock at full speed If the clock doubler is enabled the options also include twice the main oscillator frequency and the main oscillator divided by 3 In addition the 32 clock can be used for the processor and peripheral clocks the 32 kHz clock can also be divided by 2 4 8 or 16 which provides dramatically lower power consumption Table 26 1 lists the options for the clock modes and the processor clock frequency Table 26 1 Clock Modes Main Oscillator Clock 32 kHz Processor Clock GCSR Setting Doubler Divider Frequency Full On 2 x Main Oscillator Full Off Main Oscillator Divided by 2 On Divided by 2 Off Main Oscillator 2 Divided by 4 On N A Divided by 6 On Main Oscillator 3 Divided by 4 Off Main Oscillator 4 Divided by 8 On Divided by 6 Off Main Oscillator 6 Divided by 8 Off Main Oscillator 8 Disabled 32 768 kHz 2 16 384 kHz Off 32 kHz divider N A 14 8 192 kHz used 8 4 096 kHz 16 2 048 kHz Chapter 26 Low Power Operation 273 Depending the application the processor can continue executing code normally when the main oscillator is divided down to a lower value However when the processor clock is running off of the 32 kHz clock it is rec
97. inhibits the address compare for TH that bit position Breakpoint x Mask 1 Register BOM1R Address 0x0309 B1M1R Address 0x0319 B2M1R Address 0x0329 Address 0 0339 B4M1R Address 0x0349 B5M1R Address 0x0369 6 Address 0x0379 Bit s Value Description 7 0 Breakpoint x Mask 15 8 A one in a bit position inhibits the address compare for that bit position Breakpoint x Mask 2 Register BOM2R Address 0x030A B1M2R Address 0x031A B2M2R Address 0x032A B3M2R Address 0x033A B4M2R Address 0x034A B5M2R Address 0x036A B6M2R Address 0x037A Bit s Value Description 7 0 Breakpoint x Mask 23 16 A one in a bit position inhibits the address compare for that bit position 270 Rabbit 4000 Microprocessor User s Manual 26 LOW POWER OPERATION 26 1 Overview The Rabbit 4000 contains several power saving features Since the power consumed by the processor is proportional to the clock speed the Rabbit 4000 provides 12 clock modes that can go as low as 2 kHz To further reduce power consumption in those ultra sleepy modes various shortened chip select strobes are available to reduce current draw by the attached memory devices Figure 26 1 shows a typical current draw as a function of the main clock frequency The values shown do not include any current consumed by external oscillators or mem
98. interrupt operation 01 Suppress PWM interrupts seven of eight iterations of PWM counter 10 Suppress PWM interrupts three out of four iterations of PWM counter 11 Suppress PWM interrupts one out of two iterations of PWM counter 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle 244 Rabbit 4000 Microprocessor User s Manual PWM LSB x Register PWL2R Address 0x008C PWL3R Address 0x008E Bit s Value Description 7 6 Least significant two bits for the Pulse Width Modulator count 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 1 These bits are ignored and should be written with zero 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle PWM MSB x Register PWMOR Address 0x0089 PWM1R Address 0x008B PWM2R Address 0x008D PWMSR Address 0 008 Bit s Value Description Most significant eight bits for the Pulse Width Modulator count With a count of 7 0 the PWM output will be High for 1 clocks out of the 1024 clocks of the PWM counter PWM Block Access Register PWBAR Address 0 00 8 Bit s Value Description 7 0 Access PWM register poi
99. interrupts when the count goes from 0x00 to OxFF or from OxFF to 0x00 An interrupt can occur each time the count over flows or underflows The Quadrature Decoder contains digital filters on the inputs to pre vent false counts The external signals are synchronized with an internal clock provided by the output of Timer A10 Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower nibble of Parallel Ports D and E The I signal is input on an odd numbered port bit while the Q signal is input on an even numbered port bit There is also a disable selection which is guaranteed not to generate a count increment or decrement on either entering or exiting the disabled state The operation of the counter as a function of the I and Q inputs is shown below INPUT Q INPUT COUNTE 10 BIT AE COUNTER Interrupt Chapter 22 Quadrature Decoder 231 The Quadrature Decoders clocked by the output of Timer 10 giving a maximum clock rate from perclk 2 down to perclk 512 The time constant of Timer A10 must be fast enough to sample the inputs properly Both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock period wide In addition the clock rate must be high enough that transitions on the I and Q inputs are sampled in different clock cycles Input capture may be used to measure the pulse width on the I inputs because they come from the o
100. measure pulse widths and time intervals between external events time stamp signal changes on a pin and measure time intervals between a software start and an external event An inter rupt can also be generated when an edge is detected or when a counter rolls over A 16 bit counter is used to record the time at which the event takes place The counter is driven by the output of Timer 8 and can be set to count at a rate ranging from the full clock speed perclk 2 down to 1 256 the clock speed perclk 512 Two events are recognized a start condition and a stop condition start condition may be used to start counting and the stop condition to stop counting However the counter may also run continuously or run until a stop condition is encountered The start and stop condi tions may also be used to latch the current count at the instant the condition occurs rather than actually start or stop the counter The same pin may be used to detect the start and stop condition for example a rising edge could be the start condition and a falling edge could be the stop condition The start and stop condition can also be input on separate pins The input capture channels can be used to measure the width of fast pulses This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse In this case the maximum error in the measurement is approxi mately 2 periods of the clock used to coun
101. nF 1000 RECEIVE 10 RxD 1kQ optional 3 3 V e 10 nF l TE 10 100 4 eT x 270 PFT to nF jual 8250 T 77220 pF Gor 3l 270pF l E mA 22kQ 820 nH 470nH 2 1100 TxDD 270 470 nH 820 nH op S 18W 270 10nF TRANSMIT 1 65kQ 220pF l 40 nF E 270 470 nH 820 nH TxD cf Y Y 2 TxDD 10 nF 10 nF 1kV 1kV PE6 43 3 V E E 100 nF E CLOCK 3 3 V IN 4 0 AW LINK optional 4700 5 0 5 5 54 20MHz NC7SP14 NC7SU04 Bs 4700 i 3 33 pF 4 L L The transmit data output pins consist of two pins for each side of the differential signal The two pins on each side should be connected through a resistor network as shown to provide proper wave shaping of the outgoing signal Chapter 20 10Base T Ethernet 209 The receive data input for the network port uses two pins with the exact definition of the two pins under program control via NAPCR according to the table below NAPCR 7 5 RXD RXD Comment 000 RXD RXD Normal differential input 010 RXD RXVAL True input with valid data qualifier 100 RXD unused Single ended true input data 110 RXD unused Single ended negative input data True input with valid data qualifier xxl RXD RXVAL RxD is KORA with NAPCR to provide level i
102. of the buffered nature of Parallel Port D using a read modify write type of oper ation can lead to old data being written to PDDR To alleviate this potential problem each bit of the port can be written individually using a separate address for each bit Parallel Port D acts as the upper byte of the data bus when the 16 bit mode is enabled all other functionality of Parallel Port D will be automatically disabled when 16 bit mode is in effect Table 11 1 Parallel Port D Pin Alternate Output Functions Pin AltOuto AltOuti AltOut2 AltOut3 PD7 IA7 17 PWM3 SCLKC D15 PD6 TXA 16 PWM2 TXE D14 PD5 IA6 I5 PWMI RCLKE D13 PD4 TXB 14 PWMO TCLKE D12 PD3 IA7 TIMER C3 SCLKD 11 PD2 SCLKC D TIMER C2 TXF D10 PD1 IA6 TIMER RCLKF D9 PDO SCLKD 10 TIMER CO TCLKF D8 Chapter 11 Parallel Port D 87 Table 11 2 Parallel Port Pin Alternate Input Functions Name eae ear DMA RS PD7 x RXA RXE PD6 PDS x RXB RCLKE PD4 TCLKE PD3 x RXC RXF DREQI QRD2A PD2 SCLKC DREQO QRD2B PDI x RXD RCLKF INTI ORDIA PDO SCLKD TCLKF INTO QRDIB 88 Rabbit 4000 Microprocessor User s Manual 11 1 1 Block Diagram Parallel Port D Data PDDR PDBxR Serial Ports A F Tx Rx Clocks 16 bit Data Bus 7 0 upper byte Exte
103. see Table 28 8 resulting in a minimum clock low time of 80 x 16 ns 12 8 ns e clock to output enable is 5 ns assuming 20 pF load spectrum spreader is on in ns mode resulting in a loss of 4 5 ns worst case see Table 28 9 e main clock asymmetry is 52 48 resulting in a loss of 4 of the clock period or 1 4 ns The output enable access time is given by access time T min clock low clock to output enable spreader delay asymmetry delay data setup time 34 ns 12 8 ns 5 ns 4 5 ns 1 4 ns 36 ns Chapter 28 Specifications 313 28 4 Clock Speeds 28 4 1 Recommended Clock Memory Configurations The preferred configuration for a Rabbit based system is to use an external crystal or reso nator that has a frequency one half of the maximum internal clock frequency The oscillator frequency can be doubled or divided by 2 4 6 or 8 giving a variety of operating speeds from the same crystal frequency In addition the 32 768 kHz oscillator that drives the battery backable clock can be used as the main processor clock and to save the substantial power consumed by the fast oscillator the fast oscillator can be turned off This scenario is called the sleepy mode where the clock speed is from 2 kHz to 32 kHz and the operating system current consumption of 10 to 120 uA depends on frequency and voltage Table 28 10 describes some recommended clock and memory configurations for both 8 bit and 16 bit mem
104. sess 291 27 3 7 Handling Interrupts in the System User Mode 292 27 4 Register pete cor rte eO TP eet E rp E pI SET dg 204 Chapter 28 Specifications 301 28 1 DE Characteristics sies eoe e ere itte edited rs 301 28 2 AC Characteristics eue pel mde enata e 303 28 3 Memory A ess i ne Eee Ee EXER 304 28 3 1 Memory Reads nc eene Ree se An ni 304 28 3 2 Memory ee ehem pie tee eere 305 28 3 3 External VO Reads si i i 308 28 3 4 External Writes iere derer p eh etr pe 309 28 3 5 Memory A ess TIMES oe testes RE REESE EE URP n IRI 311 26 4 beaten a be bap teeta genet 314 28 4 1 Recommended Clock Memory Configurations 314 Table of Contents 28 5 Power and Current Consumption eese 317 28 5 1 Sleepy Mode Current Consumption eese enne 318 28 5 2 Battery Backed Clock Current Consumption sese 319 Chapter 29 Package Specifications and Pinout 321 29 1 LOFP Pack ages eot e eite estne emerit tme erede eee d 321 29 T Pmout Ate ete A ed BRL hen she RBS RUE 321 29 1 2 Mechanical Dimensions and Land Pattern see meennnnnnennzznnenenzzznenzznenznzzznnennnzzna 322 29 2 Ball
105. set up the CLK output pin NACR Used to set up the Ethernet clock Chapter 2 Clocks 11 2 3 Operation 2 3 1 Main Clock The main clock is input on the CLKI pin and is optionally sent through the spectrum spreader and then the clock doubler Both of these are described in greater detail below Different main clock modes may be selected via the GCSR as shown in Table 2 1 Note that one GCSR setting slows the processor clock while the peripheral clock operates at full speed this allows some power reduction while keeping settings like serial baud rates and the PWM at their desired values Table 2 1 Clock Modes GCSR Setting Processor Clock Peripheral Clock 010 Main clock Main clock 011 Main clock 2 Main clock 2 xxx110xx Main clock 4 Main clock 4 xxxilixx Main clock 6 Main clock 6 000 Main clock 8 Main clock 8 default on startup 001 Main clock 8 Main clock 32 kHz clock possiblv divided 100 32 kHz clock possibly divided via GPSCR 32 kHz clock possibly divided 101 main clock disabled via CLKIEN output signal 32 kHz clock possibly divided via GPSCR When the 32 kHz clock is enabled in GCSR it can be further divided by 2 4 6 or 8 to generate even lower frequencies by enabling those modes in bits 0 2 of GPSCR See Table 2 4 for more details 12 Rabbit 4000 Microprocessor User s Ma
106. six Peripheral clock from the main clock divided by six 128 Rabbit 4000 Microprocessor User s Manual 16 SERIAL PORTS A D 16 1 Overview Serial Ports A B C and D are identical except for the source of the data clock and the transmit receive and clock pins Serial Port A is special because it can be used to boot strap the processor Each serial port can be used in the asynchronous or the clocked serial mode with an internal or external clock In the asynchronous mode either 7 or 8 data bits can be transferred and a parity bit and or an additional address 0 or long stop 1 bit can be appended as well Parity and the address long stop bits are also detected when they are received The asynchronous mode is full duplex while the clocked mode can be half or full duplex Both transmit and receive have one byte of buffering a byte may be read while another byte is being received or the next byte to be transmitted can be loaded while the current byte is still being transferred out The byte is available in the buffer after the final bit is sampled The status of each serial port is available in the Serial Port Status Registers SxSR and contains information on whether a received byte is available the receive buffer was over run a parity error was received and the transmit buffer is empty or busy sending a byte The status is updated when the final bit of a received byte is sampled or when the final bit
107. slowing the clock when less computing activity is taking place The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme Chapter 2 Clocks 17 2 3 4 32 The 32 768 kHz clock is used to drive the asynchronous serial bootstrap the real time clock the periodic interrupt and the watchdog timers If these features are not used in a design the use of the 32 kHz clock is optional A simplified version of the recommended oscillator circuit for the Rabbit 4000 is shown below The values of resistors and capacitors may need to be adjusted for various frequen cies and crystal load capacitances Technical Note TN235 External 32 768 kHz Oscilla tor Circuits is available on the Rabbit Semiconductor web site and goes into this circuit in detail TEE R1 and R2 control the power consumed by the R1 unbuffered inverter SN74AHC1GU04 U1A U2A NC7SP14 2 C 5 12 pF 32 768 2 215 A C1 values may vary or C1 C2 C1 be eliminated Figure 2 4 Basic 32 768 kHz Oscillator Circuit The 32 768 kHz circuit consumes microampere level currents and has a very high imped ance making it susceptible to noise moisture and environmental contaminants It is strongly recommended to conformally coat this circuit to limit effects of temperature and humidity on the oscillation frequency Details abou
108. will occur every 488 us It is cleared by reading GCSR It can operate at Priority 1 2 or 3 The secondary watchdog interrupt will occur whenever the secondary watchdog is enabled and allowed to count down to zero It is cleared by restarting the secondary watch dog by writing to WDTCR The secondary watchdog interrupt always occurs at Priority 3 Chapter 4 System Management 33 4 3 Operation 4 3 1 Periodic Interrupt The following steps explain how a periodic interrupt is used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Enable the periodic interrupt by writing to GCSR 3 The interrupt request is cleared by reading from GCSR A sample interrupt handler is shown below periodic isr push af ioi 14 GCSR Clear the interrupt request and get status handle any periodic tasks here pop af ipres ret 4 3 2 Real Time Clock The real time clock consists of six 8 bit registers that together comprise a 48 bit value The real time clock is not synchronized to the read operation so the least significant bit should be read twice and checked for matching values if the two reads do not match then the real time clock may have been updating during the read and should be read again Writing to RTCOR latches the current real time clock value into the RTCxR holding regis ters so the following sequence should be used to read the real time clock 1 Write any value to RTCOR and then read b
109. with other Rabbit interrupts 266 MICTOPFOCESSOTS 6 example ISR 267 memory vs I O accesses 263 D block diagram Operation 266 design considerations bootstrap 25 nU 263 aoe breakpoints 264 register descriptions 268 2 clocks 10 Tegisters cesse 265 Heb T DMA channels 175 bugs external I O control 250 workarounds 335 325 external interrupts 69 advanced 16 bit mode 336 i 2 input capture channels 220 DMA requests to internal EU I BE iss memory management 43 registers 186 336 125 Network Port A 203 DMA block copy 5 5 Parallel Port 73 interaction 186 336 2 2 E 181 Parallel Port 78 DMA HDLC Ethernet i er en e Moda isi Parallel Pott 82 185 335 channel priorities mi Parallel Port 89 stack protection DMA ee Parallel Port 99 interaction 35 52 335 ae e PWM ees 24 EER Rite nr quadrature decoder 23 C UE copy M on T i eu o od UEEDUS sua sds ge 12 external requests ses 173 Seral Pons AD LLLI E RR Ue 174177179 Serial Ports E P 146 oscillator circuit 18 2 EN MA
110. 010 Timed DMA request supplied to DMA Channel 2 011 Timed DMA request supplied to DMA Channel 3 100 Timed DMA request supplied to DMA Channel 4 101 Timed DMA request supplied to DMA Channel 5 110 Timed DMA request supplied to DMA Channel 6 111 Timed DMA request supplied to DMA Channel 7 DMA Timed Request Divider Low Register DTRDLR Address 0x0116 Bit s Value Description 7 0 Write The eight LSBs of the limit value for the DMA timed request timer are stored DMA Timed Request Divider High Register DTRDHR Address 0x0117 Bit s Value Description 7 0 Write The eight MSBs of the limit value for the DMA timed request timer are stored 192 Rabbit 4000 Microprocessor User s Manual DMA y Termination Byte Register DOTBR Address 0x0108 D1TBR Address 0x0118 D2TBR Address 0x0128 D3TBR Address 0x0138 D4TBR Address 0x0148 D5TBR Address 0x0158 D6TBR Address 0x0168 D7TBR Address 0x0178 Bit s Value Description 7 0 Byte value that if matched will terminate a buffer DMA y Termination Mask Register DOTMR Address 0x0109 DITMR Address 0x0119 D2TMR Address 0x0129 D3TMR Address 0x0139 D4TMR Address 0x0149 D5TMR Address 0x0159 D6TMR Address 0x0169 D7TMR Address 0x0179 Bit s Value Description Mask for termination byte A on
111. 040 R W OOxxxxxx Port B Data Direction Register PBDDR 0 0047 R W 11000000 9 2 Dependencies 9 2 1 I O Pins Parallel Port B uses pins PBO through PB7 These pins can be used individually as data inputs or outputs as the address bits for the auxiliary I O bus as control signals for the slave port or as clocks for Serial Ports A and B On startup bits 6 and 7 are outputs set low for backwards compatibility with the Rabbit 2000 All other pins are inputs Note that when the auxiliary I O bus or slave port is enabled in SPCR the Parallel Port B pins associated with those peripherals perform those actions no matter what the settings are in PBDR or PBDDR See the associated peripheral chapters for details on how they use Parallel Port B 9 2 2 Clocks All outputs on Parallel Port B are clocked by the peripheral clock perclk 9 2 3 Other Registers Register Function Sets the Parallel Port B function for some pins if the oe slave port or auxiliary I O bus is enabled 78 Rabbit 4000 Microprocessor User s Manual 9 2 4 Interrupts There are no interrupts associated with Parallel Port B 9 3 Operation The following steps must be taken before using Parallel Port B 1 Select the desired input output direction for each pin via PBDDR Note that this setting is superseded for some pins if the slave port or auxiliary I O bus is enabled in SPCR or if the clocked serial mode is enabled for s
112. 06 0LIT LQFP DAT58206 ULIT LQFP There is no danger to the chip as long as normal ESD precautions are taken and there is no greater ESD sensitivity on the VBAT pin once the chip is installed in a design as long as the design guidelines recommended below are followed The design was respun to improve the ESD protection on the VBAT pin Rabbit 4000 processors with the following markings have this additional protection e AT58206 UL2T LQFP e AT58206 JCT2T TFBGA NOTE All Rabbit processors are sensitive to ESD and should be handled appropriately B 1 1 ESD Design Guidelines The following design guidelines are recommended for designs incorporating a Rabbit 4000 processor with ESD sensitivity on VBAT Note that these guidelines should be considered standard for all Rabbit Semiconductor products and are good design recommendations for all Rabbit processors 1 1 8 V supply for VBAT should be provided by a regulator with at least 2 kV ESD protection human body model 2 The 3 3 V supply should have smaller 0 1 uF 0 01 uF and 2 2 nF bypass capacitors throughout the layout In addition the 3 3 V supply should also have a large value bulk capacitor 10 uF 3 The power going to VBAT should also be protected by a diode and two resistors See a Rabbit Semiconductor schematic for a RabbitCore module based on the Rabbit 4000 for more details 334 Rabbit 4000 Microprocessor User s Manual 2 05 The following b
113. 1 Alternate Parallel Port A and B Pin Outputs Alternate Output Options Serial Clock Mode Slave Mode PA 7 0 Data 7 1 5 SLVATN PB6 IA4 PB5 IA3 PB4 2 PB3 2 IAO 1 SCLKA IA7 PBO SCLKB IA6 Appendix A Parallel Port Pins with Alternate Functions 329 Table 2 Alternate Parallel Port D Pin Outputs Alternate Output Option ix 0 1 2 3 16 bit Data 17 PWM3 SCLKC PC6 TXA 16 PWM2 TXE 5 15 PWMI RCLKE PC4 TXB 14 PWMO TCLKE TIMER C3 SCLKD PC2 TXC 12 TIMER C2 TXF PCI TXD TIMER RCLKF PCO TXD 10 TIMER TCLKF PD7 IA7 I7 PWM3 SCLKC D15 PD6 TXA I6 PWM2 TXE D14 PD5 IA6 I5 PWMI RCLKE D13 PD4 TXB 14 PWMO TCLKE D12 PD3 IA7 13 TIMER C3 SCLKD D11 PD2 SCLKC D TIMER C2 TXF D10 PDI TA6 TIMER RCLKF D9 PDO SCLKD 10 TIMER TCLKF D8 PE7 7 ACT PWM3 SCLKC 6 16 PWM2 TXE PES 15 LINK PWMI RCLKE PE4 14 0 PWMO TCLKE PE3 I3 A23 TIMER C3 SCLKD 2 12 22 TIMER C2 TXF PEI 21 TIMER RCLKF PEO 10 A20 TIMER TCLKF When Serial Port C is enabled in the clocked serial mode with an internal clock PD2 becomes SCLKC and is not available fo
114. 1 Memory Management Unit MMU sese enr 46 3 3 2 8 bit Operation neuen aos ee asa SUI enata erae 47 5 3 3 16 bit and Page Modes 3033 uere A 49 5 3 4 Separate Instruction and Data Space sse 52 5 3 5 Memory Protection federe ee e pei ee 52 923262 Stack Protect ON eee pere apetece ot peto s e n 52 54 Register Descrptlons nee eO eee nare 53 Chapter 6 Interrupts 65 6 1 65 6 2Operatiotii sie A B 66 6 3 Interrupt Fables wn e a A A au 66 Chapter 7 External Interrupts 69 IM OVCRVIS Wa sch ie fecere ete e ea Oe a i e 69 7 2 Diagram A pepe re eret e OR Rr der oe amu 69 21 toe eed 70 7 3 Dependenci s t A p epo e P Rd ETE Ep beo rete ipe tp oe 70 13 1 UO Bins A dte Ha co e A Bite 70 7 322 CLOCKS ehe a RD L m e bp 70 WESEL TWO set stirata bnadi ee aR 70 TA Operation uere ten etn acai eae ede eden JA 70 PAM Example ISR isa ie 70 7 5 Register Descriptions a 71 Chapter 8 Parallel Port A 73 821 OVERVIEW iia tese ctae ee a ie ise te See ease iret toe Nach B p i
115. 1 Parallel Port C bit 4 alternate output 3 TCLKE Parallel Port C Function Register PCFR Address 0x0055 Bit s Value Description 7 0 0 corresponding port bit functions normally 1 i corresponding port bit carries its alternate signal as an output See Table 10 258 Rabbit 4000 Microprocessor User s Manual Parallel Port D Alternate Low Register PDALR Address 0 0062 Bit s Value Description 7 6 00 Parallel Port D bit 3 alternate output 0 IA7 01 Parallel Port D bit 3 alternate output 1 I3 10 Parallel Port D bit 3 alternate output 2 TIMER C3 11 Parallel Port D bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port D bit 2 alternate output 0 SCLKC 01 Parallel Port D bit 2 alternate output 1 I2 10 Parallel Port D bit 2 alternate output 2 TIMER C2 11 Parallel Port D bit 2 alternate output 3 TXF 3 2 00 Parallel Port D bit 1 alternate output 0 IA6 01 Parallel Port D bit 1 alternate output 1 I1 10 Parallel Port D bit 1 alternate output 2 TIMER C1 11 Parallel Port D bit 1 alternate output 3 RCLKF 1 0 00 Parallel Port D bit O alternate output 0 SCLKD 01 Parallel Port D bit 0 alternate output 1 10 10 Parallel Port D bit 0 alternate output 2 TIMER 11 Parallel Port D bit O alternate output 3 TCLKF Chapter 24 External I O Control 259 Parallel Port D Alternate High Register PDAHR Address 0x0063
116. 2 10 2 2250 ort rere ea 83 10 52 15 aa Mer oot rte hee 83 10 2 2 CLOCKS En 83 10 2 3 Other Re SISters serere OO a a 83 10 24 83 10 3 Operation ii EUM 83 10 4 Register Description S xii repe PH n SAT 84 Chapter 11 Parallel Port D 87 PDD OV CLV IC E A sAn A A 87 11 11 Block Diagram eee OPERE RUE ee 89 115152 REGISTERS i i e 90 1152 D pendencles oce rt sta Se 90 11 2 b D OF PIS 245 is A 90 tetro ert tette 90 11 2 3 Other RE EA HERE eee 91 14 22 24 Tnterr pts sce bene ep sd e E ERE E 91 11 53 Operation sie se aii SIR Ie diae 91 lil REGISTER Descriptions oe eerte Pc petere pa eee eere ne 92 Chapter 12 Parallel Port E 97 L2 I OVERVIEW i i a ei oe uinum Ini 97 12 TT Block Di aerate uet eger EE UI FERE B A a 99 12 12 Registers 3 ioco rrr E PER 100 12 2 Dependenci s eot retener eee ER ne PARU a te Ue Peel essere EAA EA E wk 100 12 Dil ds tenete ta 100 12 22 CIOGKS
117. 3 20 1 2 Registers 204 20 2 Deperidencies eite eene teo coe etes tee 205 202251 TO Pins cnet ims ete SR ete mE etu egeat S 205 20 222 CIOCKS i sr E erbe ee 205 20 2 3 Other Registers meteo pee ette rie Pe preise ee ettet 205 20 2 4 Interrupts beet ERO EP ED rb Ee Phe DR E ISL 205 PUES ci RH C M 206 20 3 T a e 206 20 3 2 Tran SMit eri 206 20 3 3 e 206 20 34 Handlin snterrupts ibniet ie e RUD EOD EH de 207 20 3 5 Multicast Addressing 208 20 4 Ethernet Interface Circuits in ie cre rH 209 20 5 Register Descriptions 210 Table of Contents Chapter 21 Input Capture 219 PANES A H 219 21 1 1 Inp t Capture ii i rere aere E ee e VTS 219 21 12 Input Co unt Mode 220 21 1 3 Block Diagram re eet aeo ue ero eh 220 21 VAs Registers oe coU ERE GEH a EEEE ASEET ERS 221 21 2 Dependercles e Po CERVUS go ea use Ne E 222 212 1 I O P
118. 325 Table 29 1 Ball and Land Size Dimensions Nominal Ball Tolerance 5 Nominal Land Land Ball Pitch Diameter Variation Diameter Variation mm mm mm mm mm 0 3 0 35 0 25 0 8 0 25 0 25 0 20 The design considerations in Table 29 2 are based 5 mil design rules and assume sin gle conductor between solder lands Table 29 2 Design Considerations all dimensions in mm Key Feature Recommendation A Solder Land Diameter 0 254 0 010 B NSMD Defined Land Diameter 0 406 0 016 C Land to Mask Clearance min 0 050 0 002 D Conductor Width max 0 127 0 005 E Conductor Spacing typ 0 127 0 005 F Via Capture Pad max 0 406 0 016 G Via Drill Size max 0 254 0 010 Land Trace 326 Rabbit 4000 Microprocessor User s Manual 29 3 Rabbit Pin Descriptions Table 29 3 lists all the pins on the Rabbit 4000 along with the data direction of the pin its function and the pin number on the die Table 29 3 Rabbit 4000 Pin Descriptions Pin Group Pin Name Direction Function LQFP Pin TFBGA Ball CLK Output Internal Clock Output 2 Bl CLK32K Input 32 kHz Clock In 48 K6 RESET Input Master Reset 45 L5 Hardware RESOUT Output Reset Output 49 L6 CLKI Input Main Clock In 108 C8 CLKIEN Output Main Clock Enable 109
119. 5 3 2 d 8 0 o k b 00 2 g lt X 0 0 2 gt v 9 GB H 8 o D 7 0 8 bit mode Data or E C due External Interface bit mode CPU SYSTEM USER 1 1 1 Address Memory ipl 1 652 51 630 34 K Management Memory cnp IOE1 OE Control o Jla i Clock 08 Doubler 05 Parallel Ports KS 1 1 6 1 1 SK Fast Global Power Clock Save amp Clock 71 Distribution PC 7 1 1 1 p PotD 1 l 1 PotE rer 7 1 TIMER C 3 0 lt Timer C 1 l 1 i Serial PotA 1 1 TimerA Ach Synch TXA RXA CLKA VBAT RAM 1 ATXA ARXA incl 32 bytes Timer B Bootstrap Bootstrap battery backable i i Asynch Serial IrDA U 1 IrDA Bootstrap Serial Pors 1 1 CLK32K 5 Paine ke tA BCD lock Inpu i ana p RXC CLKC Watchdog ia DILDO 148 Asineh rpa lt TAD RXD CLKD 1 1 lt 1 Secondary Watchdog i TXE RXE lt i l Asynch HDLC 1 TCLKE RCLKE Periodic l l Serial SDLC 1 1 Asynch Serial IrDA RXF Interrupt 2 1 TCL KF RCLKF 1 i HDLC SDLC IrDA External I O ID 7 0 lt xternal
120. 5 1 The DATASEG and STACKSEG registers provide backwards compatibility to the Rabbit 2000 and 3000 processors these registers map directly to DATASEGL and STACKSEGL but the corresponding uppermost four bits are set to zero Table 5 1 Memory Management Registers Register Segment Size Comments Maps to DATASEGL Date 8 bits DATASEGH set to 0x00 DATASEGL Data 8 bits DATASEGH Data 4 bits Maps to STACKSEGL STACKSEG Stack 8 bits STACKSEGH set to 0x00 STACKSEGL Stack 8 bits STACKSEGH Stack 4 bits Loaded via instructions APG XMEM S Di LD XPC AandLD Loaded via instructions EXEC MEM 12 bits LD LXPC HLand LD HL LXPC Each of these registers provides a 4KB offset that is added to the logical address to pro vide a physical address as shown in Figure 5 3 46 Rabbit 4000 Microprocessor User s Manual DATASEGH DATASEG DATASEGL 16 bit logical address ES 20 bit physical address 24 bit physical address STKSEGH STKSEG STKSEGL 16 bit logical address 24 bit physical address 16 bit logical address 20 bit physical address 24 bit physical address Figure 5 3 MMU Operation 5 3 2 8 bit Operation On startup Memory Bank 0 is enabled to use 50 OEO and WEO with four wait states and write protection enabled it is expected that an external flash device containing startup code be attached to those strobes The other
121. 6 00 Four five for writes wait states for accesses in this bank 01 Two three for writes wait states for accesses this bank 10 One two for writes wait states for accesses in this bank 11 Zero one for writes wait states for accesses in this bank 5 0 Pass bank select address MSB for accesses in this bank 1 Invert bank select address MSB for accesses in this bank 4 0 Pass bank select address LSB for accesses in this bank 1 Invert bank select address LSB for accesses in this bank 3 2 00 OEO and WEQ are active for accesses in this bank 01 OEI and are active for accesses in this bank 10 0 only is active for accesses in this bank i e read only Transactions are normal in every other way 1 only is active for accesses in this bank 1 read only Transactions are normal in every other way 1 0 00 50 is active for accesses in this bank 01 CS1 is active for accesses in this bank 10 CS2 is active for accesses in this bank 11 This bit combination is reserved and should not be used Chapter 5 Memory Management 55 MMU Expanded Code Regisier MECR Address 0x0018 Bit s Value Description 7 5 000 Bank select address is A 19 18 001 Bank select address is A 20 19 010 Bank select address is A 21 20 O11 Bank select address is A 22 21 100 Bank select address is A 23 22 101 This bit combination is reserved and shoul
122. 7 4 2 0 These bits are ignored The port buffer bit 3 is written with the value of this bit The port buffer will be 3 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port D Bit 4 Register PDB4R Address 0x006C Bit s Value Description 7 5 3 0 These bits are ignored The port buffer bit 4 is written with the value of this bit The port buffer will be 4 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port D Bit 5 Register PDB5R Address z 0x006D Bit s Value Description 7 6 4 0 These bits are ignored The port buffer bit 5 is written with the value of this bit The port buffer will be 5 Write transferred to the port output register on the next rising edge of the peripheral clock Chapter 11 Parallel Port D 95 Parallel Port D Bit 6 Register PDB6R Address 0x006E Bit s Value Description 7 5 0 These bits are ignored The port buffer bit 6 is written with the value of this bit The port buffer will be 6 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port D Bit 7 Register PDB7R Address 0x006F Bit s Value Description 6 0 These bits are ignored The port buffer bit 7 is written with the value of this bit The port buffer will be 7
123. 73 R W 00000000 Port E Control Register PECR 0x0074 R W xx00xx00 Port E Function Register PEFR 0x0075 R W 00000000 Port E Drive Control Register PEDCR 0x0076 R W 00000000 Port E Data Direction Register PEDDR 0x0077 R W 00000000 Port E Bit 0 Register PEBOR 0x0078 W XXXXXXXX Port E Bit 1 Register PEBIR 0x0079 W XXXXXXXX Port E Bit 2 Register PEB2R 0x007A W XXXXXXXX Port E Bit 3 Register PEB3R 0x007B W XXXXXXXX Port E Bit 4 Register PEB4R 0x007C W XXXXXXXX Port E Bit 5 Register 5 0x007D W XXXXXXXX Port E Bit 6 Register PEB6R 0 007 W XXXXXXXX Port E Bit 7 Register PEB7R 0x007F W XXXXXXXX 12 2 Dependencies 12 2 1 I O Pins Parallel Port E uses the pins PEO through PE7 These pins can be used individually as data inputs or outputs as serial port transmit and receive for Serial Ports E and F as clocks for Serial Ports C F as external I O strobes as outputs for the PWM and Timer C peripher als as the upper address bits A 23 20 or as the Ethernet clock and status LEDs for the on chip network peripheral The input capture peripheral can also watch pins PE7 5 and PEI There is also an option to provide the slave port chip select on PE7 pins are set as inputs on startup The individual bits can be set to be open drain via PEDCR See the associated peripheral chapters for details on how they use Parallel Port E 12 2 2 Clocks outputs on Parallel Port E are clocked by the peripheral
124. 77 19 37 CHE 178 19 34 Handling Interr pts i ene 179 19 32 Example ISR irte eet pene ene Hee pe e 179 19 3 3 DMA Priority with the Processor esee enne en tenere 179 19 3 4 DMA Channel Priority 181 19 3 5 Buffer Descriptor Modes 2 nentes enne en netten eene 181 19 3 5 T Sangle BUffer 182 19 35 52 Buffer Array outer EURO e EE NER scp ISO ee ERE E eC E PER 182 19 3 5 3 Linked List inne URP EOD RR DE see 183 19354A Circulat Queue a Etant uim aiunt 184 19 3 5 5 Linked Arr y iecore relieta eves cu et RH GERE 184 19 3 6 DMA with Peripherals tette 185 19 3 6 1 DMA with HDLC Serial Ports 2 2 185 19 3 6 2 DM A EU tr ee ete inner 185 19 3 6 3 DMA with PWM and Timer C eese enne ener enne 185 19 3 7 DMA Bug Workarounds Appendix B 2 L essere rennen nennen rennen 185 19 3 7 1 DMA HDLC Ethernet Interaction eene eene rennen 185 19 3 8 DM A Block Copy Interaction sos eret m ete Seu PRI Qr eit 186 19 3 9 Single Byte DMA Requests to internal I O Registers 186 19 4 Register Descriptions rone L par eR CE IEEE EP D 187 Chapter 20 10Base T Ethernet 201 20 L OvetvIe Wo UE ER e PRI HERR RE EE 201 20 1 1 Block is iem dee RERO RO E EP E ge 20
125. 94 WDTTR 222200000050 38 DMA Source Addr 7 0 62 WPER 59 Register 198 63 WPSxHR 62 DMA Timed Request STKLLR 62 WPSxLR 61 Control Register 192 STKSEG 53 WPSXR 61 DMA Timed Request Di STKSEGH 54 WPxR eene 60 vider High Register 192 STKSEGL 54 bootstrap 26 DMA Timed Request Di SWDTR 38 breakpoints 265 vider Low Register 192 SxAR eee 138 155 Breakpoint x Address 0 DMA x Buffer Complete 158 Register 269 Register 188 tennis 141 Breakpoint x Address 1 DMA x Buffer Unused 15 8 SxDHR 144 160 Register 269 Register 194 SxDLR 143 160 Breakpoint x Address 2 DMA x Buffer Unused 7 0 SxDR 138 155 Register 269 Register 193 SxER asynch mode Breakpoint x Control DMA x Control Register 196 142 159 Register 268 DMA x Destination SxER clocked serial mode Breakpoint x Mask 0 Addr 15 8 Register 199 Geist lenders EE 143 Register 270 DMA x Destination SxER HDLC mode 160 Breakpoint x Mask 1 Addr 23
126. A Time Constant 7 Register TAT7R 0 00 13 2 Dependencies 13 2 1 Pins The output of Timer A does not come out directly on any of the I O pins It can be used to control when the output occurs on Parallel Ports D E and can affect the output times of Serial Ports and the PWM 13 2 2 Clocks The timers in Timer A can be clocked by either perclk or perclk 2 as selected in TAPR In addition timers A2 A7 can be clocked by the output of timer A1 by selecting that option in TACSR 13 2 3 Other Registers Register Function GCSR Select peripheral clock mode 110 Rabbit 4000 Microprocessor User s Manual 13 2 4 Interrupts A Timer A interrupt can be generated whenever timers 1 7 decrement to zero by enabling the appropriate bit in TACSR The interrupt request is cleared when TACSR is read The Timer A interrupt vector is in the IIR at offset OxOAO It can be set as priority 1 2 or 3 in TACR 13 3 Operation The following steps explain how to set up a Timer A timer 1 Select perclk as the Timer A input clock in TAPR default is perclk 2 2 Select the source clocks for timers A2 A7 in TACR 3 Write the desired divider value to TATXR for all timers that will be used 4 Enable Timer by writing a 1 to bit 0 of TACSR 13 3 1 Handling Interrupts The following steps explain how an interrupt is set up and used Remember to set up the interr
127. ADHR Address 0x00C7 SBDHR Address 0x00D7 SCDHR Address 0x00E7 SDDHR Address 0x00F7 Bit s Value Description 7 0 Disable the serial port divider and use the output of Timer A to clock the serial port 1 Enable the serial port divider and use its output to clock the serial port The serial port divider counts modulo n and is clocked by the peripheral clock 6 0 Seven MSBs of the divider that generates the serial clock for this channel 144 Rabbit 4000 Microprocessor User s Manual 17 SERIAL PORTS 17 1 Overview Serial Ports E and F are identical to each other and their asynchronous operation is identi cal to that of Serial Ports A D except for the source of the data clock the buffer sizes and the transmit receive and clock pins Each serial port can be used in the asynchronous or the HDLC mode with an internal or external clock In the asynchronous mode either 7 or 8 data bits can be transferred and both a parity bit and or an additional address 0 or long stop 1 bit can be appended as well Parity and the address long stop bits are also detected when they are received The asynchronous mode is full duplex The transmit and receive buffers of Serial Ports E and F have 4 bytes each this reduces the interrupt overhead requirements A serial port interrupt is generated whenever at least one byte is available in the receive buffer or whenever a byte is shifted out of the transmit buffer
128. CE RERO ERR er 163 18 2 T I O PIns ep PERPE ERE RUPEE PETERET RP Ie 163 T3222 cM 163 18 23 A A e a RE 163 Rabbit 4000 Microprocessor User s Manual 18 3 Operation e Deere Elena e eR T ptite HEP DE Pr 164 18 3 1 Master Setup i aicut ORI e rd ette e pU On DEO edes 165 IX VALDE DEM EE 165 18 3 3 Master Slave Communication sees nnne 166 18 3 4 Slave Master Communication sms nne nennen erret rennen nee 166 18 3 5 Handling Interrupts pine a n iee Se en 166 18 3 6 Example ISR pete ed te Det et eripe a Pe b 166 18 3 7 Other Configurations Se tete esrb se SS 167 18 3 8 Timing Diagrams etna me PE B Eon ETETE pi 168 18 4 Resister Descriptions eoe eene e ne e ierit od uti i dnte 170 Chapter 19 DMA Channels 173 19 1 EEG Sia 173 I9 1 1 Block IS a N 175 T9 1 2 e ee ERU Ese 176 192 D pendencies Ere ne ex R E a tenis 177 192251 VO PINS 2 a p f ER Ta i IPIS HE 177 19 2 2 ea A Ta EUIS RED UIROS 177 19 2 5 ure CERE RR ANREDE E repe rwr eet e ER E eoOres 1
129. CHIP SELECT STROBE l O HANDSHAKE ACTIVE LOW TA gg EXTERNAL I O HAN Ds HAKE Figure 24 2 External I O Handshake Timing Diagram Chapter 24 External I O Control 249 24 1 4 Block Diagram External I O Control Address and Data Memory Bus or Access Parallel Ports A and B External 1 Address Select IBxCR I O Handshake Control Handshake Select I O Handshake Timeout IHTR Parallel Port E Pin Parallel Port E Pin Parallel Port E Pin Bank x Control Select IBXCR PUR PyALR 24 1 5 Registers Register Name Mnemonic I O Address R W Reset Handshake Control Register IHCR 0x0028 00000000 I O Handshake Select Register IHSR 0x0029 R W 00000000 I O Handshake Timeout Register IHTR 0x002A R W 00000000 I O Bank 0 Control Register IBOCR 0x0080 W 00000000 I O Bank 1 Control Register IBICR 0x0081 W 00000000 I O Bank 2 Control Register IB2CR 0x0082 W 00000000 I O Bank 3 Control Register IB3CR 0x0083 W 00000000 I O Bank 4 Control Register IBACR 0x0084 W 00000000 I O Bank 5 Control Register 5 0 0085 W 00000000 I O Bank 6 Control Register IB6CR 0x0086 W 00000000 I O Bank 7 Control Register IB7CR 0x0087 W 00000000 250 Rabbit 4000 Microprocessor User s Manual 24 2 Dependencies 24 2 1 Pins The auxiliary I O bus uses PAO PA7 for data and either PB2 PB7 or PBO PB7 for address lines depending on t
130. D2 or 2 NOTE When Serial Port C is used as a clocked serial port and 8 bit memories are used the serial clock is transmitted on PD2 and so PD2 will not be available for other use Serial Port D can transmit on parallel port pins PC1 or PCO and can receive on pins PC1 PD1 or PEL If the clocked serial mode is enabled and 8 bit memories are used the serial clock will be transmitted on PDO and can be received on either PDO or PEO The serial clock may also be transmitted on PC3 PD3 or PE3 When 16 bit memories are used the serial clock can be transmitted on PC3 or PE3 and can be received on PDO or PEO NOTE When Serial Port D is used as a clocked serial port and 8 bit memories are used the serial clock is transmitted on PDO and so PDO will not be available for other use Table 16 2 Pin Usage Serial Ports A D Function Serial Port A Serial Port B Serial Port C Serial Port D Transmit PC7 PC6 PD6 5 PC4 PD4 PC3 PC2 PCO Receive PD7 PE7 5 PD5 PES PC3 PD3 PE3 PCI PD1 PE1 PD2 PDO Transmit Clock PBI PBO x PC7 PD7 PE7 PC3 PD3 Receive Clock PBI PBO PD2 PE2 PDO PEO The options in parentheses may be used in addition to PD2 or PDO for the corresponding serial port One of the highlighted pins not on Parallel Port D must be used for the clocked output when you are using the serial port in the clocked serial mode and you are using 16 bit memori
131. DER Address 0x00F5 Bit s Value Description 7 0 Normal clocked serial operation 1 Timer synchronized clocked serial operation 6 0 Timer synchronized clocked serial uses Timer B1 1 Timer synchronized clocked serial uses Timer B2 5 4 00 Normal clocked serial clock polarity inactive high Internal or external clock 01 Normal clocked serial clock polarity inactive low Internal clock only 10 Inverted clocked serial clock polarity inactive low Internal or external clock 11 Inverted clocked serial clock polarity inactive high Internal clock only 3 0 Normal bit order LSB first for transmit and receive 1 Reverse bit order MSB first for transmit and receive 2 0 Serial clock input mode only from Parallel Port D SCER and SDER only 1 Serial clock input mode only from Parallel Port E SCER and SDER only 1 0 No effect on transmitter 1 Terminate current clocked serial transmission No effect on buffer 0 0 No effect on receiver 1 Terminate current clocked serial reception Serial Port x Divider Low Register SADLR Address 0x00C6 SBDLR Address 0x00D6 SCDLR Address 0 00 6 SDDLR Address 0x00F6 Bit s Value Description Eight LSBs of the divider that generates the serial clock for this channel This divider is not used unless the MSB of the corresponding SxDHR is set to one Chapter 16 Serial Ports D 143 Serial Port x Divider High Register S
132. DHR SFDHR Address 0x00CF Address 0x00DF Bit s Value Description Disable the serial port divider and use the output of Timer A to clock the serial port Enable the serial port divider and use its output to clock the serial port The serial port divider counts modulo n and is clocked by the peripheral clock 6 0 Seven MSBs of the divider that generates the serial clock for this channel 160 Rabbit 4000 Microprocessor User s Manual 18 SLAVE PORT 18 1 Overview The slave port is a parallel communication port that can be used to communicate with an external master device The slave port consists of three data input and data output regis ters and a status register The data input registers are written by the master the external device and are read by the processor The data output registers are written by the processor and are read by the master Note that the data registers are named from the point of view of the processor The slave device can only read the data input registers and write to the data output registers Similarly the master device can only read the data input registers and write the data output registers Both devices can read and write to the status register The status register contains the interrupt status bits and a status flag corresponding to each data input or data output register to indicate the empty or full status of the data register Data re
133. DOBCR Address 0x0103 D1BCR Address z 0x0113 D2BCR Address z 0x0123 D3BCR Address z 0x0133 DABCR Address z 0x0143 D5BCR Address 0x0153 D6BCR Address 0x0163 D7BCR Address 0x0173 Bit s Value Description The DMA increments a counter at the start of the next buffer This count is latched in this register and can be used along with the buffer unused count to 7 0 Read determine the actual amount of data transferred by the DMA This counter is initialized by a start command or when the DMA is automatically rewound to the initial address Writing to this register loads the counter This feature is intended only for testing Write because the DMA automatically resets the counter to all ones when fetching from the initial address The counter is incremented whenever the DMA fetches a new buffer length value from a descriptor DMA Master Conirol Register DMCR Address 0x0104 Bit s Value Description 7 4 These bits reserved and should be written with zeros 32 00 DMA transfers at Priority 0 No DMA transfers while CPU operates at Priority 3 2 or 1 01 DMA transfers at Priority 1 No DMA transfers while CPU operates at Priority 3 or 2 10 DMA transfers at Priority 2 No DMA transfers while CPU operates at Priority 3 11 DMA transfers at Priority 3 DMA transfers at any time 1 0 00 DMA interrupts are disabled 01 DMA interrupts use Inter
134. E 174 slave 162 power consumption 18 1 system management 32 block diagram 10 i Timer ET 109 clock doubler 15 16 2 2 sig register descriptions 87 eee TEBISTETS 176 doubling dividing 9 9 178 339 DMA channels continued modes 2 219 L single byte DMA requests input capture mode 219 to internal I O registers input count mode 219 land pattern PENNE 186 336 operation 223 BGA package 325 timed requests 173 input capture mode 224 LQFP package 322 transfer 186 336 input count mode 220 low power operation 271 transfer priorities 179 219 clock rates 273 transfer priority 179 register descriptions 225 clock modes 273 transfer rates 180 registers 221 current draw for ultra sleepy transfers 174 start and stop events 219 modes 4 272 use with peripherals 185 interrupt priorities 68 current draw vs clock DMA HDLC Ethernet 65 frequency sss 271 interaction 185 335 breakpoints
135. Error Register 218 Network Port A Data Register 210 Network Port A Last Data Register 210 Network Port A Missed Frame Register 218 Network Port A Multicast Filter x Register 217 Network Port A Multicast Hash Register 217 Network Port A Physical Address x Register 217 Network Port A Pin Control Register network port disabled 215 Network Port A Pin Control Register network port enabled 215 Network Port A Receive Control Register 216 Network Port A Receive Status Register 211 Network Port A Reset Reg ISlet itte 213 Network Port A Status Reg 213 Network Port A Transmit Control Register 216 Network Port A Transmit Status Register 211 344 Rabbit 4000 Microprocessor User s Manual registers continued Parallel Port 73 Parallel Port A Data Register 75 Slave Port Control Register PET repris 75 Parallel Port 78 Parallel Port Data Direction Register 79 Parallel Port Data Register 79 Slave Port Control Register ppp 80 Parallel Port C 82 Parallel Port C Alternate High Register 85 Parallel Port C Alternate Low Register 84 Parallel Port C Data Direction Register 84 P
136. Hardware breakpoints are triggered by both memory and by internal I O reads and writes This behavior could potentially make it hard to detect a low memory situation when using breakpoints if internal I O reads writes are occurring but it allows inadvertent I O accesses to be identified Chapter 25 Breakpoints 263 25 1 1 Block Diagram Breakpoint x Interrupt Interrupt Generation Request Code Execution Match Type Address Paces Data Read Enabl E Data Write Address nabte Mask ompare BxCR BxMOR BxM1R BxM2R 264 Rabbit 4000 Microprocessor User s Manual 25 1 2 Registers Register Name Mnemonic Address R W Reset Breakpoint Debug Control Register BDCR 0x001C R W 00000000 Breakpoint 0 Control Register BOCR 0x030B R W 00000000 Breakpoint 1 Control Register 0x031B 00000000 Breakpoint 2 Control Register B2CR 0x032B 00000000 Breakpoint 3 Control Register B3CR 0x033B 00000000 Breakpoint 4 Control Register B4CR 0x034B 00000000 Breakpoint 5 Control Register 5 0 035 00000000 Breakpoint 6 Control Register B6CR 0x036B 00000000 Breakpoint 0 Address 0 2 Register BOAxR 0x030C x R W 00000000 Breakpoint 1 Address 0 2 Register BIAxR 0x031C x 00000000 Breakpoint 2 Address 0 2 Register B2AxR 0x032C x R W 00000000 Breakpoint 3 Address 0 2 Registe
137. Hz Ethernet Clock Frequency on PE6 fin 20 MHz Chapter 28 Specifications 303 28 3 Memory Access Times All access time measurements are taken at 50 of signal height 28 3 1 Memory Reads Table 28 4 Preliminary Memory Read Time Delays VDDcore 1 8 V 10 VDDjo 3 3 V 10 T4 40 C to 85 C Parameter Symbol Loading Min Typ Max 30 pF 6 ns Clock to Address Delay Tar 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to Memory Chip Select Delay Tcsx 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to Memory Read Strobe Delay Torx 60 pF 8 ns 90 pF 11 ns Data Setup Time Tsetup 1 ns Data Hold Time Thold 0 ns 304 Rabbit 4000 Microprocessor User s Manual 28 3 2 Memory Writes Table 28 5 Preliminary Memory Write Time Delays VDDcore 1 8 V 10 VDDjo 3 3 V 10 T4 40 C to 85 C Parameter Symbol Loading Min Typ Max 30 pF 6ns Clock to Address Delay 60 pF 8 ns 90 pF 11 ns 30 pF 6 ns Clock to Memory Chip Select Delay Tcsx 60 pF 8 ns 90 pF 11 ns 30 pF 6ns Clock to Memory Write Strobe Delay Twex 60 pF 8 ns 90 pF 11 ns 30 pF 10 ns High Z to Data Valid Relative to Clock Tpuzv 60 pF 12 ns 90 pF 15 ns 30 pF 10 ns Data Valid to High Z Relative to Clock 60 12 ns 90 pF 15 ns Chapter 28 Specifications 305 Memory Read wait states 106 1 E y axd LIL
138. I O banks the handshake is active for by writing to IHSR 3 Select the handshake timeout value by writing to IHTR Once enabled the handshake will be checked for every external I O transaction in a bank that was enabled in IHSR After these transactions the program should check for a time out by reading IHTR 252 Rabbit 4000 Microprocessor User s Manual 24 4 Register Descriptions l O Handshake Control Register IHCR Address 0x0028 Bit s Value Description 7 5 These bits reserved and should be written with zeros 4 0 T O handshake is active low I O transaction held until signal goes high 1 T O handshake is active high I O transaction held until signal goes low 3 This bit is reserved and should be written with zero 2 0 000 Use Parallel Port E bit 0 for I O handshake 001 Use Parallel Port E bit 1 for I O handshake 010 Use Parallel Port E bit 2 for I O handshake 011 Use Parallel Port E bit 3 for I O handshake 100 Use Parallel Port E bit 4 for I O handshake 101 Use Parallel Port E bit 5 for I O handshake 110 Use Parallel Port E bit 6 for I O handshake 111 Use Parallel Port E bit 7 for I O handshake Chapter 24 External I O Control 253 Handshake Select Register IHSR Address 0x0029 Bit s Value Description 7 0 Disable I O handshake for I O Bank 7 1 Enable I O ha
139. ICL1R ICL2R Address z 0x005A Address 0x005E Bit s Value Description 7 0 Read The least significant eight bits of the latched Input Capture count are returned Reading the LSB of the count latches the MSB of the count to avoid reading stale data Reading the MSB of the count opens these latches on the MSB of the count In Counter operation if no latching condition is specified the value written to this register is returned Write The eight LSBs of the match value for counter mode are stored 228 Rabbit 4000 Microprocessor User s Manual Input Capture MSB x Register ICM1R Address 0x005B ICM2R Address 0x005F Bit s Value Description The most significant eight bits of the latched Input capture count are returned In 7 0 Read Counter operation if no latching condition is specified the value written to this register is returned Write The eight MSBs of the match value for counter mode are stored Chapter 21 Input Capture 229 230 Rabbit 4000 Microprocessor User s Manual 22 QUADRATURE DECODER 22 1 Overview The Rabbit 4000 has a two channel Quadrature Decoder that accepts inputs via specific pins on Parallel Ports D and E Each channel has two inputs the in phase I input and the 90 degree or quadrature phase Q input An 8 or 10 bit up down counter counts encoder steps in the forward and backward directions and provides
140. IS iacet Rad ae PU et e re t de 222 2122 CLOCKS eee L estre egt f a A AN ENS 222 21 23 Other utere eren ed n pei EIE ee 222 eorr rene te rene eene eer eut ne eee tete eee oe eee ees eee dee 222 21537 Operam a a S EA 223 21 3 1 Input Capture Channel ere edere reperit pb erre ri 223 21 3 2 Handling Interrupts ieee ses oret etera EEA 223 21 3 3 Example ISR toes e 223 21 3 4 Capture Mode 131 sus eie pieta pete n pt rte o Heiden 224 21 3 5 Count Mode cerae eee e e EA A 224 2144 Register DeSCrIptOnS ee esu ted tee esi rrt quip 225 Chapter 22 Quadrature Decoder 231 22 T OVERVIEW ds piae RE A AERE ERR I ERU b DR e 231 22 1 1 Block i iii kie tee ee eie tec Hie ib Pest 233 22 1 2 Registers eee pde Oen Ite teo te ep HERB UH a Re 233 22 2 Dependenties iii ji e p 234 ae i mea 234 22 22 CLOCKS ed iet terit Rev m ote 234 22 2 5 Other devon ean a P PUO Dp Dire orare nier tee inge 234 2224 Interr pts ete teet eter nente 234 2213 Opefation 5 bre ett 235 22 3 Handling Interr pts rete PRI ege rie 235 22 3 2 Example ISR
141. It can be set as Priority 1 2 or 3 The status bits in the QDCSR are set coincident with the interrupt request and are reset when QDCSR is read 234 Rabbit 4000 Microprocessor User s Manual 22 3 Operation The following steps explain how to set up a Quadrature Decoder channel 1 Configure Timer A10 via TATIOR to provide the desired Quadrature Decoder clock speed 2 Configure QDCR to select the input pins for the two channels 3 Reset the counters by writing to QDCSR 22 3 1 Handling Interrupts The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure QDCR to select the interrupt priority note that interrupts will be enabled once this value is set The following actions occur within the interrupt service routine e Since a Quadrature Decoder interrupt occurs when the counter rolls over determine exactly why the interrupt occurred by reading the status bits in QDCSR and adjust any software counters accordingly This will also clear the interrupt request e The current counter value can be read from QDCxR and QDCxHR if the 10 bit counter is enabled 22 3 2 Example ISR A sample interrupt handler is shown below qd isr push af Save used registers ioi 14 a QDCSR Clear the interrupt request and get status perform any necessary software counter adjustments here read current counter value s po
142. Microprocessor User s Manual 2 3 3 Clock Doubler The clock doubler allows a lower frequency crystal to be used for the main oscillator and to provide an added range over which the clock frequency can be adjusted The clock dou bler is controlled via the Global Clock Double Register GCDR The clock doubler uses an on chip delay circuit that must be programmed by the user at startup if there is a need to double the clock Table 2 3 lists the recommended delays for the GCDR for various oscillator frequencies Table 2 3 Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value Frequency Range OxOF lt 7 3728 MHz OxOB 7 3728 11 0592 MHz 0x09 11 0592 16 5888 MHz 0x06 16 5888 20 2752 MHz 0x03 20 2752 52 8384 MHz 0x01 52 8384 70 0416 MHz 0x00 270 0416 MHz Chapter 2 Clocks 15 When the clock doubler is used and there is no subsequent division of the clock the output clock will be asymmetric as shown in Figure 2 3 Oscillator Oscillator delayed and inverted Doubled clock Delay gt time Address CS Example Write Data out Cycle Write pulse Early write pulse 7 option Address CS X Example Read Cycle Output enb Early output enb E O option Data out from mem Figure 2 3 Effec
143. O bus Parallel Port is used for the data bus and Parallel Port B 7 0 is used for the address bus 1 0 00 Slave port interrupts are disabled 01 Slave port interrupts use Interrupt Priority 1 10 Slave port interrupts use Interrupt Priority 2 11 Slave port interrupts use Interrupt Priority 3 Chapter 18 Slave Port 171 172 Rabbit 4000 Microprocessor User s Manual 19 DMA CHANNELS 19 1 Overview There are eight independent DMA channels on the Rabbit 4000 All eight channels are identical and are capable of transferring data to or from memory external I O or internal The priority between the channels be either fixed or rotating and the DMA use of the bus can be limited to guarantee interrupt latency or CPU throughput The DMA channels are capable of special handling for the last byte of data when sending data to selected internal I O addresses such as the HDLC serial ports or to the Ethernet peripheral and can also transfer end of frame status after transferring data from selected internal I O addresses The DMA channels can watch the data being transferred and can terminate a transfer when a particular byte is matched A mask is available for the byte match to allow termi nation only on particular bit settings in the data instead of an exact byte match Memory to memory transfers proceed at the maximum transfer rate unless they are gated by an external request signal or the internal timed request Tra
144. Prioritv 3 stack violation interrupt occurs when a stack based write occurs within the 16 bvtes below the upper limit or within the 16 bvtes above the lower limit Note that the writes will still occur even if thev are within the 16 bvtes surrounding the limits but the interrupt can serve as a warning to the application that the stack is in danger of being over or underrun The stack checking can be enabled or disabled bv writing to STKCR When stack protection is enabled and a DMA transfer is occurring the stack protection interrupt will occur if the lower 16 bits of a DMA transfer s phvsical write address match the 16 bits of the stack protection s logical address limits 52 Rabbit 4000 Microprocessor User s Manual 5 4 Register Descriptions MMU Instruction Data Register MMIDR Address 0x0010 Bit s Value Description Internal I O addresses are decoded using only the lower eight bits of the internal 7 0 address bus This restricts internal I O addresses to the range 0 0000 OxOOFF Internal I O addresses are decoded using all 15 bits of the address internal I O 1 address bus This option must be selected to access internal I O addresses of 0x0100 and higher 6 This bit is reserved an must be written with zero 5 0 Enable A16 and bank select address MSB inversion independent of instruction data 1 Enable A16 and bank select address MSB inversion for data a
145. Pulse Width 1A 7 0 1 Chip Interface t Modulation PWMI 0 7 0 Ld i i QD1A QD1B 1 Quadrature 1 QD2A QD2B J INTOA INT1A External Decoder i AQD1A AQD1B INTOBSINTAB Interrupts AQD2A AQD2B PC 7 53 1 DREQO B A 9 DMA Input lt DREQ B A 8 channels l Capture LE 1 1 20 MHz Slave Port 00 0 ILINK 41 l 10 Slave Port Sait RXD 1 0 Ethernet i ISCS ISRD ISWR TXD 5 0 l 1 ISLAVEATIN A 1 Rabbit 4000 Microprocessor User s Manual 1 4 Basic Specifications Table 1 1 Rabbit 4000 Specifications and Features Package 128 pin LQFP 128 ball TFBGA Package Size 16 mm x 16 mm x 1 5 mm 10 mm x 10 mm x 1 2 mm Operating Voltage 1 8 V DC core 3 3 V DC I O ring Operating Current 0 35 mA MHz 1 8 V 3 3 V Operating Temp 409 to 85 C Maximum Clock Speed 60 MHz Digital 40 arranged in five 8 bit ports Serial Ports 6 CMOS compatible Ethernet Port 10Base T Baud Rate Clock speed 8 max asynchronous Address Bus 20 24 bit Data Bus 8 16 bit Timers Ten 8 bit one 10 bit with 2 match registers and one 16 bit with 8 match registers Real Time Clock Yes battery backable RTC Oscillator Circuitry External Watchdog Timer Sup
146. R 218 PEB3R su 105 DxDAOR 199 NACR 22020002000 24 214 PEBAR ee 105 DxDAIR 199 NACSR 212 PEBSR 105 DxDA2R 199 NADR nette 210 PEBOR nme 106 DxIAOR 194 210 PEBZR mes 106 DIAIR si une 194 218 103 DxIAJR 194 217 PEDOR siket 104 DILOR 197 NAMHR 217 PEDBR ine 104 DXLAR eme 197 NAPAXR 217 PEDR sisisi 102 DxLAOR 200 NAPCR network port PEFR es 104 262 DxLAIR 200 disabled 215 PEUER eR 295 DxLA2R 200 NAPCR network port PWBAR 245 DxSAOR 198 enabled 215 PWBPR 245 DxSAJAR 198 005006 216 244 DxSA2R 198 NARR 213 PWLIR 244 DxSMR eme 195 NARSR esses 211 PWEXR ue 245 342 Rabbit 4000 Microprocessor User s Manual registers registers registers alphabetic listing continued alphabetic listing continued clocks continued PWMXR 245 TBCMR
147. R 23 2 4 Interrupts The PWM can generate an interrupt for every PWM counter rollover every second roll over every fourth rollover or every eighth rollover This option is selected in PWLIR The interrupt request is cleared by a write to any PWM register The PWM interrupt vector is in the IIR at offset 0x170 It can be set as Priority 1 2 or by writing to PWLOR 242 Rabbit 4000 Microprocessor User s Manual 23 3 Operation The following steps explain how to set up a PWM channel 1 Configure Timer 9 via TATOR to provide the desired PWM clock frequency 2 Configure PWLXR to select whether to spread the PWM output throughout the cycle 3 Configure PWLXR to select whether to suppress the PWM output 4 Configure the duty cycle by writing to PWLxR and PWMxR 23 3 1 Handling Interrupts The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure PWLOR to select the PWM interrupt priority and PWLIR to select PWM interrupt suppression if an interrupt is desired The following actions occur within the interrupt service routine e Any PWM values may be updated e interrupt request should be cleared by writing to any PWM register 23 3 2 Example ISR A sample interrupt handler is shown below pwm isr push af save used registers ld a 0x55 ioi ld PWMOR a update a PWM value note that i
148. R Address 0x021E NAMF7R Address 0x021F Bit s Value Description Eight bits of the multicast filter At the end of a received multicast address the 70 Write 9 six bits of CRC are used as an index into this 64 bit table If the corresponding bit is zero the frame is discarded If the corresponding bit is one the frame is accepted Network Port A Multicast Hash Register NAMHR Address 0x0220 Bit s Value Description 72 ad The latest hash value the upper six bits of the CRC calculation latched at the end of the destination address field is returned 1 0 These bits are unused and will always read as zero Network Port A Collision Detect Register NACDR Address 0x0221 Bit s Value Description The current value of the collision detect counter is returned This counter is 7 0 cleared by a read of this register Chapter 20 10Base T Ethernet 217 Network Port A Alignment Error Register NAAER Address 0x0222 Bit s Value Description The current value of the alignment error counter is returned This counter is 7 0 read cleared by a read of this register Network Port A CRC Error Register NACER Address 0x0223 Bit s Value Description 70 reai The current value of the CRC error counter is returned This counter is cleared by a read of this register Network Port A Checksum 0 Register NACOR Address 0x0224 Bit s
149. R 0 0007 R XXXXXXXX Watchdog Timer Control Register WDTCR 0x0008 W 00000000 Watchdog Timer Test Register WDTTR 0x0009 W 00000000 Secondary Watchdog Timer Register SWDTR 0x000C W 11111111 Global Output Control Register GOCR 0 000 00000000 Global CPU Configuration Register GCPU 0 002 R 0xx00010 Global Revision Register GREV 0 002 R 0xx00000 2 Onchip Encryption RAM Byte 1 0x0600 0x061F R W 32 Rabbit 4000 Microprocessor User s Manual 4 2 Dependencies 4 2 1 I O Pins The CLK STATUS WDTOUT and BUFEN pins are controlled by GOCR Each of these pins can be used as general purpose outputs by driving them high or low e the CLK pin can output the peripheral clock the peripheral clock divided by two or be driven high or low e the STATUS pin can be active low during the first byte of each opcode fetch active low during an interrupt acknowledge or driven high or low e the WDTOUT pin can be active low whenever the watchdog timer resets the device or driven low and e the BUFEN pin can be active low during external I O cycles active low during data memory cycles or driven high or low The values in the battery backed onchip encryption RAM bytes are cleared If the signal on the SMODE pins changes state 4 2 2 Clocks The periodic interrupt real time clock watchdog timer and secondary watchdog timer require the 32 kHz clock 4 2 3 Interrupts The periodic interrupt is enabled in GCSR and
150. R will reflect its current output value but any value written to an input pin will not appear until that pin becomes an output Chapter 12 Parallel Port E 101 12 4 Register Descriptions Parallel Port E Data Register PEDR Address 0x0070 Bit s Value Description 7 0 Read The current state of Parallel Port E pins 7 is reported The Parallel Port buffer is written with this value for transfer to the Parallel Write 225 Port E output register on the next rising edge of the peripheral clock Parallel Port E Alternate Low Register PEALR Address 0x0072 Bit s Value Description 7 6 00 Parallel Port E bit 3 alternate output 0 13 01 Parallel Port E bit 3 alternate output 1 23 10 Parallel Port E bit 3 alternate output 2 TIMER C3 11 Parallel Port E bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port E bit 2 alternate output 0 12 01 Parallel Port E bit 2 alternate output 1 22 10 Parallel Port E bit 2 alternate output 2 TIMER C2 11 Parallel Port E bit 2 alternate output 3 3 2 00 Parallel Port E bit 1 alternate output 0 11 01 Parallel Port E bit 1 alternate output 1 A21 10 Parallel Port E bit 1 alternate output 2 TIMER 11 Parallel Port E bit alternate output 3 RCLKF 1 0 00 Parallel Port E bit 0 alternate output 0 10 01 Parallel Port E bit 0 alternate output 1 20 10 Para
151. SP 1 SU SP SP 1 Yes POP SU 2 7 SU SP SP SP 1 Yes SURES 2 4 l l l SU SU 1 0 SU 7 2 Yes Performs LD E E but if EDMF amp amp SU 0 then the System IDET 2 Violation interrupt flag is set if ALTD 2D appears before it always does LD E E RDMODE 2 4 1 5 0 Yes SP SP 2 PC R v where 2 19 17171717 y SYSCALL offset Ne SP 1 SP 2 PCL SP 3 SU SCALL 2 15 SP SP 3 01100000 No SU SU 5 0 00 SU SP PCL SP 1 SP 2 SRET 2 12 7 spe spy3 No SETUSRP mn 4 15 eee lc E No SP 2 SP SP 2 SU SU 1 0 SU 7 2 tmpl SP SETSYSP mn 4 12 tmph SP 1 SP SP 2 No if tmp mn System Violation The processor keeps a one byte stack called the SU register that is analogous to the IP register that keeps track of the interrupt priority Every time SETUSR is executed to enter the User Mode or an interrupt occurs or SYSCALL or RST is executed to enter System Mode the current mode is pushed onto the SU register When a SURES is executed the previous mode is popped off the SU register 290 Rabbit 4000 Microprocessor User s Manual The effects of each instruction are The SETUSR instruction puts the processor into the User Mode by pushing the correct value into the SU register PUSH SU an
152. TUS 14 93 A11 5 92 9 A10 06 91L1 8 VDDINT B 7 VDDINT VSSINT 8 89 VSSINT 50 19 88 A13 D7 10 87 14 VSSIO B 11 86 VDDIO VDDIO 12 85W VSSIO D6 13 84 A17 D5 14 83 D4 115 82 A18 D3 16 81 A16 D2 17 80 A15 D1 18 791 A12 DO 19 78 7 AO 20 77 6 VSSIO 21 76 VDDIO VDDIO 22 75 vssio 1 23 740 5 2 24 73 4 VDDINT 25 72 VDDINT VSSINT 26 1 VSSINT 27 70 128 69 PC1 129 68 PC2 PE5 130 67 PC3 4 131 66 4 VSSIOM VDDIO o onon 2 2255 22 2225582550002 og5roo9u zxrxsopo 9 a gt gt gt gt gt na 2 Figure 29 1 Package Outline and Pin Assignments Chapter 29 Package Specifications and Pinout 321 29 1 2 Mechanical Dimensions Land Pattern 16 00 0 25 mm 14 00 0 10 mm 14 00 0 10 mm 16 00 0 25 mm 64 0 18 0 05 mm 0 40 mm 1 40 0 05 mm 0 10 0 05 mm The same pin dimensions apply along the x axis and the y axis 0 10 mm lt 0 60 _ 0 15 Figure 29 2 Mechanical Dimensions Rabbit LQFP Package 322 Rabbit 4000 Microprocessor User s Manual Figure 29 3 shows PC b
153. These bits report the state of the SMODE pins write These bits are ignored and should be written with zero 4 2 000 Disable the slave port Parallel Port A is a byte wide input port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the slave port with SCS from Parallel Port E bit 7 011 Enable the auxiliary T O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination is reserved and should not be used 101 This bit combination is reserved and should not be used 110 Enable the slave port with SCS from Parallel Port B bit 6 11 Enable the auxiliary I O bus Parallel Port A is used for the data bus and Parallel Port B 7 0 is used for the address bus 1 0 00 Slave port interrupts are disabled 01 Slave port interrupts use Interrupt Priority 1 10 Slave port interrupts use Interrupt Priority 2 11 Slave port interrupts use Interrupt Priority 3 Chapter 8 Parallel Port A 75 76 Rabbit 4000 Microprocessor User s Manual 9 PARALLEL PORT 9 1 Overview Parallel Port B is a byte wide port with each bit programmable for direction The Parallel Port B pins are also used to access other peripherals on the chip the slave port the auxiliary I O address bus and clock I O for clocked serial mode option for Serial Ports A and B The Slave Port Control Register SPCR is used to configure how Parallel Port B is used when sel
154. W Reset Slave Port Data 0 Register SPDOR 0x0020 Slave Port Data 1 Register SPDIR 0 0021 Slave Port Data 2 Register SPD2R 0x0022 Slave Port Status Register SPSR 0x0023 R 00000000 Slave Port Control Register SPCR 0x0024 0xx00000 162 Rabbit 4000 Microprocessor User s Manual 18 2 Dependencies 18 2 1 I O Pins When the slave port is enabled by writing to SPCR the following pins are enabled for slave port mode Note that enabling the slave port mode will override any general purpose or auxiliary I O bus settings for these pins when the slave port is enabled they will perform slave port functionality Table 18 2 Slave Port Pin Functionality Pin s Direction Functionality 7 SDO SD7 Bidirectional Slave data bus PB7 SLVATTN Output Slave interrupt request output PB6 SCS Input Slave chip select 4 5 5 0 5 1 Input Slave address bus PB3 SRD Input Slave port read strobe PB2 SWR Input Slave port write strobe PE7 SCS Input Alternate slave chip select 18 2 2 Clocks slave port operations are based on the processor clock 18 2 3 Interrupts A slave port interrupt occurs on the slave device whenever the master writes to SPDOR The SLVATTN pin is asserted whenever the slave device writes to SPDOR Either if these conditions is cleared when either the
155. WTR 73 8 1 1 Block Diagram sss i i a A a aka sea p a a segs teg 73 8 1 2 eee ee pdt tues casi deese i ntt ese eo attese 73 8 2 Dependencies eee eie Deed a Seer eae arse tenes 74 82 I O PIS tuto i Sr buen tee les 74 8 22 CloCKS et e ab exte 74 8 2 3 Other RESISETS nee e Fe Ure 74 RIPE Mire 74 8 3 OperatiOn P ERU t Pee ERO Der rr be 74 8 4 Register Descriptions oe eet ei It RE Hd ced eh a Mes ei e ie e Edge ees 75 Chapter 9 Parallel Port B 77 77 9 14 Block Diagram eee BRE 78 9 12 Cus M 78 9 2 Dependencles ssp Siete athena ht iene iat eb eee eed eoa 78 VERA MIO Sua EE 78 lt e 78 9 2 3 Other Registers nnconnesee cte totemp eene ream a e B P RIRs 78 9 24 Intetrupts o a Rae tere ee dui erit pt AS OREL PEE saei 79 9 3 Operation ene ete A A A een aerate 79 94 Register DesCcHptlofls xci pet e UR MIRI aetna 79 Rabbit 4000 Microprocessor User s Manual Chapter 10 Parallel Port 81 I teed 81 10 11 Block Diagram e ia 82 10 1 2 e 8
156. a Register 0 6 0 Slave port read byte 2 is empty 1 Slave port read byte 2 is full 5 0 Slave port read byte 1 is empty 1 Slave port read byte 1 is full 4 0 Slave port read byte 0 is empty 1 Slave port read byte 0 is full 3 0 Master wrote to SPSR 1 Processor wrote to SPDOR 2 0 Slave port write byte 2 is empty 1 Slave port write byte 2 is full 1 0 Slave port write byte is empty 1 Slave port write byte 1 is full 0 0 Slave port write byte 0 is empty 1 Slave port write byte 0 is full 170 Rabbit 4000 Microprocessor User s Manual Slave Port Control Register SPCR Address 0x0024 Bit s Value Description 7 0 Program fetch as a function of the SMODE pins 1 Ignore the SMODE pins program fetch function 6 5 Read These bits report the state of the SMODE pins Write These bits are ignored and should be written with zero 4 2 000 Disable the slave port Parallel Port A is a byte wide input port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the slave port with SCS from Parallel Port E bit 7 011 Enable the auxiliary T O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination is reserved and should not be used 101 This bit combination is reserved and should not be used 110 Enable the slave port with SCS from Parallel Port B bit 6 11 Enable the auxiliary I
157. a byte is available in the receive buffer or when a byte is finished being transmitted out of the trans mit buffer In the HDLC mode interrupts are also generated by the reception of an end of frame with abort valid CRC or CRC error at the end of a transmission of a CRC by an abort sequence or by a closing flag The serial port interrupt vectors are located in the as follows e Serial Port E at offset Ox1CO e Serial Port F at offset OXIDO Each of them can be set as Priority 1 2 or 3 in SxCR where x is E F for the two serial ports Chapter 17 Serial Ports E F 149 17 3 Operation 17 3 1 Asynchronous Mode The steps to set up Serial Ports E F for asynchronous operation are identical to those described in Section 16 3 1 to set up Serial Ports A D 17 3 2 HDLC Mode The following steps explain how to set up Serial Ports E F for the HDLC mode When the internal clock is selected the Rabbit 4000 is in control of all transmit and receive operations so an interrupt is not required When an external clock is selected operations can be han dled by either polling the status byte or by a serial port interrupt the performance will be better with an interrupt 1 Write the interrupt vector for the interrupt service routine to the internal interrupt table 2 Set up the desired data transmit and clock pins by writing to the appropriate parallel port function register PxER and alternate output register PxALR
158. a pul lup resistor is required on CS1 to keep the RAM deselected during powerdown RESOUT The RESOUT pin is high during reset and powerdown but low at all other times and can be used to control an external power switch to disconnect VDDIO from VBATIO when the main power source is removed 3 2 2 Clocks The processor requires a 32 kHz clock input to generate the 2400 bps internal clock required for asynchronous serial bootstrap No 32 kHz clock is required for either clocked serial or slave port bootstrap When the processor comes out of reset the CPU clock and peripheral clocks are both in divide by 8 mode 3 2 3 Other Registers Register Function Enable disable processor monitoring of SMODE SECR pins read current state of SMODE pins 3 2 4 Interrupts There are no interrupts associated with reset or bootstrap 26 Rabbit 4000 Microprocessor User s Manual 3 3 Operation Pulling the RESET pin low will initialize everything in the Rabbit 4000 except for the real time clock registers and the onchip encryption RAM The reset of the Rabbit 4000 is delayed until the completion of any write cycles in progress reset takes effect immedi ately when no write cycles are occurring The reset sequence requires a minimum of 128 cycles of the main clock to complete in either case During reset the impedance of the CS1 pin is high and all other memory and I O control signals are held high The special beh
159. able User Mode access to I O Bank 3 and internal I O addresses 0 0083 2 0 Disable User Mode access to I O Bank 2 and internal I O address 0 0082 1 Enable User Mode access to I O Bank 2 and internal I O addresses 0x0082 1 0 Disable User Mode access to I O Bank 1 and internal I O address 0 0081 1 Enable User Mode access to I O Bank 1 and internal I O addresses 0 0081 0 0 Disable User Mode access to I O Bank 0 and internal I O address 0 0080 1 Enable User Mode access to I O Bank 0 and internal I O addresses 0 0080 PWM User Enable Register PWUER Address 0x0388 Bit s Value Description 7 0 Disable User Mode access to the PWM I O addresses 0x0088 0x008F and 0 00 8 0 00 9 1 Enable User Mode access to the PWM I O addresses 0 0088 0 008 and 0 00 8 0 00 9 6 0 These bits are reserved and should be written with zeros Quad Decode User Enable Register QDUER Address 0x0390 Bit s Value Description Disable User Mode access to the Quadrature Decoder I O addresses 0 0090 7 0 0 0097 1 Enable User Mode access to the Quadrature Decoder I O addresses 0 0090 0 0097 6 0 These bits are reserved and should be written with zeros 296 Rabbit 4000 Microprocessor User s Manual External Interrupt User Enable Register IUER Address 0x0398 Bit s Value Description 3 2 These bits are reserved and should be written with zeros 1
160. accept the two encoder inputs from one of three different locations as shown in the table below Each channel can select a different input option Note that these pins can be used for other peripherals at the same time as the Quadrature Decoder peripheral one example of this use is to use measure pulse width on the I channels with the input capture peripheral Channel 1 Channel 2 Inputs Option 1 PDI PDO PD3 PD2 Option 2 PEI PEO PE3 PE2 Option 3 5 PE4 PE7 PE6 22 2 2 Clocks The 8 10 bit Quadrature Decoder counters are clocked from the output of Timer A10 and can run at rates from the peripheral clock divided by 2 down to the peripheral clock divided by 512 by writing the appropriate value to TATIOR The clock rate must be high enough that transitions on the inputs are sampled in different clock cycles In addition both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock periods wide 22 2 3 Other Registers Register Function 10 Time constant for Quadrature Decoder clock 22 2 4 Interrupts Each Quadrature Decoder channel can generate an interrupt whenever the counter incre ments from OxOFF Ox3FF in 10 bit mode to 0x00 or when the counter decrements from 0 000 to OxOFF Ox3FF for 10 bit mode The interrupt request is cleared when QDCSR is read The Quadrature Decoder interrupt vector is in the at offset 0x190
161. aces such as a flash file system However the processor will be running the application code in the User Mode most of the time The application code can request direct access to a peripheral and or interrupt from the System Mode If allowed the System Mode can create an interrupt vector as described in Section 27 3 7 that will execute the user code interrupt handler When the application code wants to perform an action that is controlled by the System Mode it can request the particular action by loading the appropriate value into HL and executing SYSCALL This requires generating a list of all the actions that the application code would want to do assigning values to each action and implementing a SYSCALL handler in the System Mode that parses the value passed to it and calls the appropriate function Write protection should be enabled User Mode only for all blocks containing system code and data as well as any critical memory regions If any critical interrupts occur stack limit violation system mode violation write protec tion violation System Mode handlers can perform any of a number of operations restart the application code signal another device halt operation and so on 288 Rabbit 4000 Microprocessor User s Manual Figure 27 3 shows overview of this level of operation System Mode Interrupt handlers Flash file system SYSCALL handler Figure 27 3 System User Mode Setup for Operating System Return
162. ack a value from RTCOR 2 Write a value to RTCOR again and again read back a value from RTCOR 3 If the two values do not match repeat Step 2 until the last two readings are identical 4 At this point registers RTCIR through RTC6R can also be read and used Note that the periodic interrupt and the real time clock are clocked by the same edge of the 32 kHz clock if read from the periodic interrupt the count is guaranteed to be stable and only needs to be read once assuming it occurs within one clock of the 32 kHz clock The real time clock can be reset by writing the sequence 0x40 0x80 to RTCCR It can be reset and left in the byte increment mode by writing 0x40 OxCO to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real time clock The byte increment mode is disabled by writing 0x00 to RTCCR 34 Rabbit 4000 Microprocessor User s Manual 4 3 3 Watchdog Timer The watchdog timer is enabled on reset with a 2 second timeout Unless specific data are written to WDTCR before that time expires the processor will be reset The watchdog timer can be disabled by writing a sequence of two bytes to WDTTR as described in the register description Table 4 1 Watchdog Timer Settings WDTCR Value Effect 0 5 Restart watchdog timer with 2 second timeout 0 57 Restart watchdog timer with l second timeout 0 59 Restart watchdog timer with 500 millisecond timeout
163. al clocking 32 kHz clock for the watchdog timer Secondary Watchdog Timer Register SWDTR Address 0x000C Bit s Value Description The time constant for the secondary watchdog timer is stored This time constant will take effect the next time that the secondary watchdog counter counts down 7 0 to zero The timer counts modulo 1 where is the programmed time constant The secondary watchdog timer can be disabled by writing the sequence Ox5A 0x52 0x44 to this register 38 Rabbit 4000 Microprocessor User s Manual Global Output Control Register GOCR Address 0x000E Bit s Value Description 7 6 00 CLK pin is driven with peripheral clock 01 CLK pin is driven with peripheral clock divided by 2 10 CLK pin is low 11 CLK pin is high 5 4 00 STATUS pin is active low during a first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 3 2 00 WDTOUT pin functions normally 01 Enable WDTOUT for test mode Rabbit Semiconductor internal use only 10 WDTOUT pin is low 1 cycle min 2 cycles max of 32 kHz 11 This bit combination is reserved and should not be used 1 0 00 BUFEN pin is active low during external I O cycles 01 BUFEN is active low during data memory accesses 10 BUFEN pin is low 11 BUFEN
164. alternate output 3 3 2 00 Parallel Port C bit 1 alternate output 0 TXD 01 Parallel Port C bit 1 alternate output 1 I1 10 Parallel Port C bit 1 alternate output 2 TIMER C1 11 Parallel Port C bit 1 alternate output 3 RCLKF 1 0 00 Parallel Port C bit 0 alternate output 0 TXD 01 Parallel Port C bit 0 alternate output 1 IO 10 Parallel Port C bit 0 alternate output 2 TIMER 11 Parallel Port C bit 0 alternate output 3 TCLKF 84 Rabbit 4000 Microprocessor User s Manual Parallel Port Alternate High Register PCAHR Address 0x0053 Bit s Value Description 7 6 00 Parallel Port C bit 7 alternate output 0 TXA 01 Parallel Port bit 7 alternate output 1 17 10 Parallel Port C bit 7 alternate output 2 PWM3 11 Parallel Port C bit 7 alternate output 3 SCLKC 5 4 00 Parallel Port C bit 6 alternate output 0 TX A 01 Parallel Port C bit 6 alternate output 1 16 10 Parallel Port C bit 6 alternate output 2 PWM2 11 Parallel Port bit 6 alternate output 3 3 2 00 Parallel Port C bit 5 alternate output 0 TXB 01 Parallel Port bit 5 alternate output 1 15 10 Parallel Port C bit 5 alternate output 2 PWM1 11 Parallel Port bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port C bit 4 alternate output 0 TXB 01 Parallel Port bit 4 alternate output 1 14 10 Parallel Port C bit 4 alternate output 2
165. an be used to perform periodic tasks The real time clock RTC consists of a 48 bit counter that is clocked by the 32 kHz clock It is powered by the VBAT pin and so can be battery backed The value in the counter is not affected by reset and can only be set to zero by writing to the RTC control register The 48 bit width provides a 272 year span before rollover occurs There are two watchdog timers in the Rabbit 4000 both clocked by the 32 kHz clock The main watchdog timer can be set to time out from 250 ms to 2 seconds and resets the pro cessor if not reloaded within that time Its purpose is to restart the processor when it detects that a program gets stuck or disabled The secondary watchdog timer can time out from 30 5 up to 7 8 ms and generates Priority 3 secondary watchdog interrupt when it is not reset within that time The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt if the secondary watchdog is reloaded in the periodic interrupt it will count down to zero if the periodic interrupt stops occurring In addition it can be used as a periodic interrupt on its own The battery backed onchip encryption RAM consists of 32 bytes of memory that are powered by the VBAT pin Their values are not affected by reset but are erased if the state of the SMODE pins changes These 32 bytes are intended for storing sensitive data such as an encryption key somewhere other than an external mem
166. an internal peripheral 6 Select a byte to terminate the transfer on by writing to the appropriate DyTBR and DyTMR registers 7 The desired control length and address registers should be written to a buffer descrip tor or descriptors in memory if not done already 178 Rabbit 4000 Microprocessor User s Manual 8 The initial address registers DyIAnR should be loaded with the physical address of the first buffer descriptor 9 The buffer descriptor can be loaded and the DMA transfer started by writing to the appropriate bit of DMALR 19 3 1 Handling Interrupts The DMA interrupt request is cleared automatically when the interrupt is handled A DMA interrupt will occur at the end of a transfer for any buffer descriptor that has bit 4 of DyCR set 19 3 2 Example ISR A sample interrupt handler is shown below dma_isr push af do something with the data in the current buffer the interrupt request is automatically cleared pop af ipres ret 19 3 3 DMA Priority with the Processor Since the Rabbit 4000 DMA uses the memory management unit to perform transfers normal code execution cannot occur while the DMA is active This includes handling interrupts so it is important to limit the amount of time that the DMA can operate This is handled in several ways First of all the DMA transfers can be set to take place whenever the processor is operating at one of the four priority levels 0 3 note that there is a singl
167. ansfer write the byte to SxAR which will automatically start the transfer If the internal clock is selected the transmission will begin immediately if an external clock is selected the transmission will begin when the clock is detected To receive a byte write 01 to bits 6 7 of SxCR to start the receive operation If the internal clock is selected the clock will begin immediately and the data will be read if an external clock is selected the receive will occur when the clock is detected 136 Rabbit 4000 Microprocessor User s Manual A sample clocked serial interrupt handler is shown below for Serial Port clocked serb isr push af ioi 14 SASR bit a 7 push af jr 2 check for tx rx ready ioi ld a SADR do something with ld 0 41 ioi 14 SACR check for tx pop af bit a 3 jr nz done a 4 9 me save used registers get status check if bvte readv in RX buffer save status for next check read bvte and clear interrupt received bvte here me get next bvte to be ioi ld SADR done pop af ipres ret a me set bits 6 7 to 01 the other bits should represent the desired SACR setup start a new receive operation check if TX buffer was emptied transmitted into A here load TX buffer with next bvte and clear interrupt restore used registers Chapter 16 Serial Ports D 137 16 4 Register Descriptions
168. anual 19 4 Register Descriptions DMA Masier Control Status Register DMCSR Address 0x0100 Bit s Value Description 7 0 0 No effect on the corresponding DMA channel Start or restart the corresponding DMA channel using the contents of the DMA Write 1 channel registers This command should only be issued after all the DMA only channel registers source destination length and link if applicable have been loaded 70 0 The corresponding DMA channel is either disabled or has completed the last 4 buffer descriptor Read 1 The corresponding DMA channel is enabled and active These bits are set by the only start command and remain set until the completion of the last buffer DMA Master Auto Load Register DMALR Address 0x0101 Bit s Value Description 7 0 0 No effect of the corresponding DMA channel Start using auto load the corresponding DMA channel using the buffer 1 descriptor in memory addressed by the channel initial address register This command should only be issued after the initial address has been loaded DMA Master Halt Register DMHR Address 0x0102 Bit s Value Description 7 0 0 No effect of the corresponding DMA channel 1 Halt the corresponding DMA channel DMA registers retain the current state and the DMA can be restarted using the DMCSR Chapter 19 DMA Channels 187 Buffer Complete Register
169. arallel Port C Data Register 84 Parallel Port C Drive Control Register 85 Parallel Port C Function Register 85 Parallel Port D 90 Parallel Port D Alternate High Register 93 Parallel Port D Alternate Low Register 92 Parallel Port D Bit 0 Register 94 Parallel Port D Bit 1 Register 94 Parallel Port D Bit 2 Register 95 Parallel Port D Bit 3 Register 95 Parallel Port D Bit 4 Register 95 Parallel Port D Bit 5 Register 95 Parallel Port D Bit 6 Register 96 Parallel Port D Bit 7 Register 96 Parallel Port D Control Register 93 Parallel Port D Data Direction Register 94 Parallel Port D Data Register 92 registers Parallel Port D continued Parallel Port D Drive Control Register 94 Parallel Port D Function Register 94 Parallel Port E 100 Parallel Port E Alternate High Register 103 Parallel Port E Alternate Low Register 102 Parallel Port E Bit 0 Register iun 104 Parallel Port E Bit 1 Register 104 Parallel Port E Bit 2 Register 105 Parallel Port E Bit 3 Register
170. atch Normal DMA transfers of data begin once an address match occurs and continue until the end frame delimiter is recognized or the line goes idle because of a collision The network receiver calculates the CRC across the entire frame in parallel with character assembly and reports the result when the end frame delimiter is recognized Normally frames with bad CRC are discarded The receiver also reports misaligned end frame delimiters those that do not occur on byte boundaries To help with handling high level protocols such as TCP IP the network port receiver accu mulates a 16 bit checksum across the entire received frame except for the first 14 bytes The first 14 bytes are the destination address field six bytes source address field six bytes and the frame length field two bytes which are not part of the TCP IP payload This checksum is initialized to all zeros during the address compare time and then each pair of bytes is added to the checksum with the carry from the previous add carried to the following add The first received byte adds to the lower byte of the checksum and the second received byte adds to the upper byte of the checksum In the case of a frame with an odd length the second received byte value is filled with zeros for the 16 bit add The checksum at the end of the frame is transferred a holding register so that it can be read by software The network port implements the NLP receive link integrity test state mach
171. ate Machine Buffer Complete Counter DxBCR Buffer Unused Counter DxBUyR Channel Adresses DxlAyR Termination Byte Detect Chapter 19 DMA Channels 175 19 1 2 Registers Register Name Mnemonic Address R W Reset DMA Master Control Status Register DMCSR 0x0100 R W 00000000 DMA Master Auto load Register DMALR 0x0101 W 00000000 DMA Master Halt Register DMHR 0x0102 W 00000000 DMA y Buffer Complete Register DyBCR 0 01 3 R 00000000 DMA Master Control Register DMCR 0x0104 R W 00000000 DMA Master Timing Control Register DMTCR 0x0105 R W 00000000 DMA Master Request 0 Control Register DMROCR 0x0106 R W 00000000 DMA Master Request 0 Control Register DMRICR 0x0107 R W 00000000 DMA Timed Request Control Register DTRCR 0 0115 R W 00000000 DMA Timed Request Divider Low Register DTRDLR 0x0116 R W Timed Request Divider High Register DTRDHR 0 0117 R W DMA Termination Byte Register DyTBR 0 01 8 R W DMA y Termination Mask Register DyTMR 0 01 9 R W 00000000 Buffer Unused 7 0 Register DyBUOR 0 01 00000000 DMA y Buffer Unused 15 8 Register DyBUIR 0 01 00000000 DMA Initial Address 7 0 Register DyIAOR 0 01 R W DMA y Initial Address 15 8 Register DyIAIR 0 01 R W
172. ated address pins AO through A19 Up to four more address pins can be enabled on PEO PE3 representing A20 through A23 Pin PE4 can be enabled as 0 to allow byte reads and writes in 16 bit SRAM devices 5 2 2 Clocks All memory operations are clocked by the processor clock 5 2 3 Other Registers Register Function PEFR PEALR Enable A20 A23 and AO 5 2 4 Interrupts When a write is attempted to a write protected 64KB or 4KB block a write protection violation interrupt is generated The interrupt request is cleared when it is handled The write protection violation interrupt vector is in the IIR at offset 0x090 It is always set to Priority 3 When a stack related write is attempted to a region outside that set by the stack limit regis ters a stack limit violation occurs The interrupt request is cleared when it is handled The stack limit violation interrupt vector is in the at offset Ox 1BO It is always set to Priority 3 Chapter 5 Memory Management 45 5 3 Operation 5 3 1 Memory Management Unit MMU Code execution takes place in the 64KB logical memory space which is divided into four segments root data stack and extended The root segment is always mapped starting at physical address 0 000000 but the other segments be remapped to start at any physical 4KB block boundary The data and stack segment mappings are set by writing to the appropriate register as shown in Table
173. ave port Parallel Port A is a byte wide input port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the slave port with SCS from Parallel Port E bit 7 011 Enable the auxiliary T O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination is reserved and should not be used 101 This bit combination is reserved and should not be used 110 Enable the slave port with SCS from Parallel Port B bit 6 11 Enable the auxiliary I O bus Parallel Port A is used for the data bus and Parallel Port B 7 0 is used for the address bus 1 0 00 Slave port interrupts are disabled 01 Slave port interrupts use Interrupt Priority 1 10 Slave port interrupts use Interrupt Priority 2 11 Slave port interrupts use Interrupt Priority 3 256 Rabbit 4000 Microprocessor User s Manual Parallel Port Alternate Low Register PCALR Address 0x0052 Bit s Value Description 7 6 00 Parallel Port C bit 3 alternate output 0 TXC 01 Parallel Port bit 3 alternate output 1 13 10 Parallel Port C bit 3 alternate output 2 TIMER C3 11 Parallel Port bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port C bit 2 alternate output 0 TXC 01 Parallel Port bit 2 alternate output 1 12 10 Parallel Port C bit 2 alternate output 2 TIMER C2 11 Parallel Port bit 2 alternate output 3 3 2 00 Parallel
174. avior of CS1 allows an external RAM to be powered by the same source as the VBATIO pin which powers CS1 In this case a pullup resistor is required on CS1 to keep the RAM deselected during powerdown The RESOUT pin is high during reset and powerdown but low at all other times and can be used to control an external power switch to disconnect VDDIO from VBATIO when the main power source is removed Table 3 1 lists the condition of the processor after reset takes place The state of all regis ters after reset is provided in the chapter describing the specific peripheral Table 3 1 Rabbit 4000 Condition After Reset Function Operation After Reset CPU Clock T Peripheral Clock Pade ay Bande Clock Doubler Clock Dither Memory Bank 0 CSO OEO write protected Control Register 4 wait states Memory Advanced 8 bit interface Control Register CPU Registers PC SP IIR EIR 0x0000 SU HTR Interrupt Priority OxFF Priority 3 IP Register Watchdog Timer Enabled 2 seconds Secondary Watchdog Timer The processor checks the SMODE pins after RESET signal is inactive Table 3 2 summarizes what happens e If both SMODE pins are zero the Rabbit 4000 begins fetching instructions from the memory device on CSO and OEO If a 16 bit memory is used on CSO the first section of code must immediately select the 16 bit bus mode Chapter 5 provides a short pro gram to d
175. ays be read as zeros Chapter 21 Input Capture 225 Input Capture Control Register ICCR Address 0x0057 Bit s Value Description 7 0 Input Capture operation for Input Capture 2 1 Input Count operation for Input Capture 2 6 0 Input Capture operation for Input Capture 1 1 Input Count operation for Input Capture 1 5 2 These bits are reserved and should be written with zero 1 0 00 Input Capture interrupts are disabled 01 Input Capture interrupt use Interrupt Priority 1 10 Input Capture interrupt use Interrupt Priority 2 11 Input Capture interrupt use Interrupt Priority 3 226 Rabbit 4000 Microprocessor User s Manual Input Capture Trigger x Register ICT1R Address 0x0058 ICT2R Address 0x005C Bit s Value Description 7 6 00 Disable the counter Applies even in Counter operation 01 The counter runs from the Start condition until the Stop condition 10 The counter runs continuously 11 The counter runs continuously until the Stop condition 5 4 00 Disable the count latching function this case and with Counter operation only the ICLxR and ICMXR return the programmed match value 01 Latch the count on the Stop condition only 10 Latch the count on the Start condition only 11 Latch the count on either the Start or Stop condition 3 2 00 Ignore the starting input 01 The Start condition is the rising edge of th
176. be written to SPDOR 3 The slave responds to the interrupt reading the data from the slave port data registers 18 3 4 Slave Master Communication 1 The slave writes data to the appropriate slave port data register If it is writing multiple bytes SPDOR should be written last which enables the SLVATTN line 2 The master receives an external interrupt from the SLVATTN line and reads the data out of the slave port data registers via external I O reads on the data bus 18 3 5 Handling Interrupts The interrupt request on the slave is cleared by either the master or the slave accessing one of the slave port registers To clear the interrupt without affecting the register values a dummy write can be made to SPSR 18 3 6 Example ISR A sample interrupt handler is shown below slave isr push af save used registers read the data sent bv the master ioi 14 SPD2R ld to siv 42 a ioi 14 SPDIR 14 to siv 41 a ioi 14 SPDOR 14 to siv 40 if a response is required perform it here ld to mas 42 ioi 1 SPD2R a ld to mas dl ioi 1 SPDIR a ld to mas 40 ioi 1 SPDOR this write asserts SLVATTN the interrupt request is cleared by any read write of the registers pop af restore used registers ipres ret 166 Rabbit 4000 Microprocessor User s Manual 18 3 7 Other Configurations There are other slave port configurations possible e The master could use the a
177. bytes depending on the 16 bit alignment of the instruction are reloaded and presented to the processor as instructions when execution is rewound after the DMA transfer The result of this mismatch is that the block copy instruction does not complete The only way to prevent this from occurring is to prevent DMA transfers during block copy instructions either by disabling the DMA or by increasing the processor priority above the priority of the DMA transfer There is a workaround The processor s BC register is used as a program counter by the block copy instructions and will be nonzero if the block copy instruction did not com plete By checking the value of BC and jumping back to the block copy instruction if it is nonzero the block copy instruction is restarted with all the current register values source and destination pointers and will continue where it left off Rabbit Semiconductor s Dynamic C compiler automatically includes this wrapper code whenever it identifies a block copy instruction 19 3 9 Single Byte DMA Requests to internal I O Registers When timed or external DMA requests are enabled and set to transfer a single byte at a time to an internal I O register two bytes will actually be transferred The simplest workaround is to double each data byte in the buffer two bytes will be transmitted but they will be identical so the actual I O register setting will not change 186 Rabbit 4000 Microprocessor User s M
178. can be generated by an Ethernet frame received correctly a frame received with error a frame transmitted correctly a frame transmitted with error error counter overflow jabber detection or link status change The events that generate an inter rupt can be selected in NACSR The network port interrupt vector is in the at offset 0 1 0 It can be set as Priority 1 2 or 3 by writing to NACSR Chapter 20 10Base T Ethernet 205 20 3 Operation High level support for TCP IP and other protocols is beyond the scope of this manual but this section will describe the low level operation of the 10Base T Ethernet peripheral 20 3 1 Setup The following steps explain how to set up the network port Write the interrupt vector for the interrupt service routine to the external interrupt table Select the desired interrupts and interrupt priority by writing to NACSR Select the desired network port pin configuration by writing to NAPCR Write the device s physical MAC address to the physical address registers NAPAXR Write to the multicast filter registers to generate a multicast filter Enable the network port transmitter by writing to NATCR A t NY Enable the network port receiver by writing to NARCR 20 3 2 Transmit The following steps explain how to transmit an Ethernet packet 1 Set up a DMA buffer descriptor that will read the packet data from memory and write it to NADR Write the b
179. ccesses only This enables the instruction data split 4 0 Normal CS1 operation Force CS1 always active This will not cause any conflicts as long as the 1 memory using CS1 does not also share an output enable or write enable with another memory 3 0 Normal operation 1 For data segment access invert bank select address MSB before MBxCR decision 2 0 Normal operation 1 For a data segment access invert 16 1 0 Normal operation 1 For a root segment access invert bank select address MSB before MBxCR decision 0 0 Normal operation 1 For a root segment access invert 16 Stack Segment Register STKSEG Address 0x0011 Bit s Value Description 7 0 Read The current contents of this register are reported Writ Eight LSBs MSBs are set to zero by write of physical address offset to use if rite SEGSIZ 7 4 lt Addr 15 12 lt OxE Chapter 5 Memory Management 53 Stack Segment Low Register STKSEGL Address 0x0014 Bit s Value Description 7 0 Read The current contents of this register are reported Write 2 LSBs of physical address offset to use if SEGSIZ 7 4 lt Addr 15 12 lt Stack Segment High Register STKSEGH Address 0x001B Bit s Value Description 7 4 These bits are reserved and should alwavs be written as zero These bits alwavs return zeros when read 3 0 Read The current contents of this register are reported Four MSBs of physical
180. cis ete SAF gut making a 66 interrupts Ls 45 operation 252 interrupt priorities 68 logical memory space 42 auxiliary I O bus 252 memory management 45 mapping physical memory A See 252 Network Port A 205 207 41 252 Operation 66 MMU operation 47 e date iore 247 Parallel Port D 91 Operation 46 register descriptions 253 Parallel Port E 101 16 bit and page modes 49 IeglSters oes 250 priority levels 65 8 bit operation 47 248 PWM 239 242 243 advanced memory modes example ISR QAR Meta Bees 49 H quadrature decoder 232 234 instruction and data space example ISR 235 eene 52 Serial Ports 134 memory protection 52 Serial Ports 149 MMU ES 46 slave port 161 163 166 read and write transactions eue nte xa 5i example ISR 166 EE LO block diagram 220 ys Du Ia 422224 8 System User mode 286 292 stack protection DMA CLOCKS eoe eser ees 222 Timer A 108 111 interaction oana 52 335 dependencies 222 example SR ded 111 OVETVIEW coore tiarna 41 interrupts
181. clock doubler is used this will cause an additional asymmetry between alternate clock cycles Both normal and strong modes reduce clock harmonics by approximately 15 dB for fre quencies above 100 MHz for lower frequencies the strong setting has a greater effect in reducing the peak spectral strength as shown in Figure 2 2 15 f Strong Spreading 8 10 5 E Normal Spreading S 50 100 150 200 250 300 350 Frequency MHz Figure 2 2 Peak Spectral Amplitude Reduction by Spectrum Spreader Two registers control the clock spectrum spreader These registers must be loaded in a spe cific manner with proper time delays GCMOR is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by storing 0x080 in GCMIR If GCMIR is cleared when disabling the spectrum spreader there is up to a 500 clock delay before the spectrum spreader is actually disabled The proper procedure is to clear GCMIR wait for 500 clocks set GCMOR and then enable the spreader by storing 0x080 in GCMIR The spectrum spreader is applied to the main clock before the clock doubler so if both are enabled there will be additional asymmetry between alternate clock cycles If the clock doubler is used the spectrum spreader affects every other cycle and reduces the clock high time If the doubler is not used then the spreader affects every clock cycle and the clock low time is reduced 14 Rabbit 4000
182. clock unless changed in PECR where the option of updating the Parallel Port E pins can be synchronized to the output of Timer A1 Timer or Timer B2 100 Rabbit 4000 Microprocessor User s Manual 12 2 3 Other Registers Register Function SACR SBCR SCCR Select a Parallel Port E pin as serial data and SDCR SECR SFCR optional clock input Select a Parallel Port E pin as a start stop condition ICSIR ICS2R input QDCR Select a Parallel Port E pin as a decoder input Select a Parallel Port E pin as an external interrupt IOCR input Select a Parallel Port E pin as an external DMA DMROCR DMRICR request input NACR Select PE6 as the Ethernet clock input SPCR Select slave chip select on PE7 IHSR IHTR 12 2 4 Interrupts External interrupts can be accepted from pins PES PE4 1 or PEO see Chapter 7 for more details 12 3 Operation The following steps must be taken before using Parallel Port E 1 Select the desired input output direction for each pin via PEDDR 2 Select high low or open drain functionality for outputs via PEDCR 3 If an alternative peripheral output function is desired for a pin select it by via PEALR or PEAHR and then enable it via PEFR Refer to the appropriate peripheral chapter for further use of that pin Once the port is set up data can be read or written by accessing PEDR The value of an output pin read in from PED
183. d 7 on Parallel Port D by writing to PDALR PDAHR and PDFR 3 Set the I O timing for a particular device by writing to the appropriate IBxCR register for the I O bank desired 4 If a strobe other than IORD IOWR or BUFEN is required enable the output of the IBxCR register by writing to the appropriate Px ALR PxAHR and PxFR registers Once the auxiliary I O bus is enabled all memory read write instructions prefixed with an IOE will go to either the memory bus or auxiliary I O bus depending on the setup in that bank s IBxCR register 24 3 2 I O Strobes The following steps must be taken before using an I O strobe 1 Set the strobe type and timing for a particular device by writing to the appropriate IBxCR register for the I O bank desired 2 If signals other than IORD IOWR and BUFEN are required enable the output of the IBxCR register by writing to the appropriate Px ALR PxAHR and PxFR registers On startup the I O strobes are set as chip selects with 15 wait states read only active low signaling and will use the auxiliary I O bus These settings will be used for the dedicated strobe pins IORD IOWR and BUFEN whenever an external I O write occurs even if not I O strobe signals are being output on parallel port pins 24 3 3 Handshake The following steps must be taken before using the I O handshake 1 Select the active level and desired port E bit to use as input by writing to IHCR 2 Select which
184. d POP SU push and pop the single byte SU register on off the SP stack SURES pops the current processor mode off the SU register returning it to the previous mode IDET causes an interrupt if executed in the User Mode and does nothing in System Mode It is intended to be placed in system level code and trap any execution of that code while in the User Mode RDMODE returns the current mode in the carry flag 0 for System Mode 1 for User Mode SYSCALL is essentially a new RST instruction and was added to allow User Mode access to the System Mode without using one of the existing RST instructions It will put the processor into the System Mode and execute code in the corresponding interrupt vector table entry SCALL is another RST instruction that vectors to the same address as SYSCALL The difference is that it also pushes the value of the SU register as well as the return address onto the stack SRET is the companion instruction to SCALL it expects both SU and the return address to be on the stack SETSYSP and SETUSRP are support functions for handing user mode interrupts pushes a 16 bit compare value onto the stack and enters user mode SETSYSP pops a 16 bit value off the stack and compares it to the provided value a system mode viola tion interrupt occurs if they do not match These two instructions provide protection for User Mode interrupts by checking for both main stack and SU stack mismatches when the User Mode handler returns
185. d not be used 110 This bit combination is reserved and should not be used 111 Bank select address is A 18 17 4 3 These bits are reserved and should be written with zeros Read returns zeros 2 0 000 Normal operation 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 For an XPC access use MBOCR independent of bank select address 101 For an XPC access use MB1CR independent of bank select address 110 For an XPC access use MB2CR independent of bank select address 111 For an XPC access use MB3CR independent of bank select address Memory Timing Control Register MTCR Address 0x0019 Bit s Value Description 7 4 These bits reserved and should be written with zeros 3 0 Normal timing for 1 rising edge to rising edge one clock minimum 1 Extended timing for OE1 one half clock earlier than normal 2 0 Normal timing for OEO rising edge to rising edge one clock minimum 1 Extended timing for OEO one half clock earlier than normal 1 0 N ormal timing for WEI rising edge to falling edge one and one half clocks minimum 1 Extended timing for WE1 falling edge to falling edge two clocks minimum 0 0 N ormal timing for WEO rising edge to falling edge one and one half clocks minimum 1 Extended timing for WEQ falling edge to falling edge two
186. dd numbered port bits The operation of the digital filter is shown below PERICLOCK I 1L TL LT LJ LJ LJ LI LI TIMER A10 REJECTED ACCEPTED The Quadrature Decoder generates an interrupt when the counter increments from OxFF Ox3FF in 10 bit mode to 0x00 or when the counter decrements from 0x00 to OxFF Ox3FF in 10 bit mode The timing for the interrupt is shown below Note that the status bits in the QDCSR are set coincident with the interrupt and the interrupt and status bits are cleared by reading the QDCSR PERI CLOCK 10 Q INPUT COUNTER or Ox3FF INTERRUPT 232 Rabbit 4000 Microprocessor User s Manual 22 1 1 Block Diagram Quadrature Decoder Channel x perclk gt Timer A10 TAT10R Parallel Interrupt Interrupt Port Pins Request QDSCR QDCxR QDCxHR 22 1 2 Registers Register Name Mnemonic Address R W Reset Quad Decode Ctrl Status Register QDCSR 0x0090 R W XXXXXXXX Quad Decode Control Register QDCR 0 0091 R W 00000000 Quad Decode Count Register QDCIR 0 0094 R XXXXXXXX Quad Decode Count High Register QDCIHR 0x0095 R XXXXXXXX Quad Decode Count 2 Register QDC2R 0x0096 R XXXXXXXX Quad Decode Count 2 High Register QDC2HR 0x0097 R XXXXXXXX Chapter 22 Quadrature Decoder 233 22 2 Dependencies 22 2 1 Pins Each Quadrature Decoder channel can
187. ding an easy means of storing and executing code beyond the 64KB logical memory space Special call and return instructions to physical addresses are provided that automatically update the XPC register as necessary d mE SEGSIZE DATA REGISTER SEGMENT 0 13 7 43 0 SEGMENT LOGICAL PHYSICAL ADDRESS MAP ADDRESS MAP Figure 5 2 Logical and Physical Memory Mapping 42 Rabbit 4000 Microprocessor User s Manual The Rabbit 2000 and 3000 had numerous instructions for reading and writing data to logical addresses but only limited support for reading and writing data to a physical memory address This has changed for the Rabbit 4000 a wide range of instructions has been pro vided to read and write to physical addresses It is possible to use the same instructions to write to logical addresses as well The 64KB logical memory space limitation can also be expanded by using the separate instruction and data space mode When this mode is enabled address bit A16 is inverted for all data accesses in the root and or data segments while address bit A19 is inverted for all data accesses in the root and or data segments before bank selection physical device occurs These two features allow both code and data to access separate 64KB logical spaces instead of sharing a single space It is possible to protect memory in the Rabbit 4000 at three different levels each of the memory banks can be made read only physical m
188. disabled 11111100 Fetching control byte next during start up 11111010 Fetching control byte next during chaining 11110100 Fetching Byte Count 0 next 11110010 Fetching Byte Count next 11101110 Fetching Source Address 0 next 11101100 Fetching Source Address 1 next 11101010 Fetching Source Address 2 next 11011110 Fetching Destination Address 0 next 11011100 Fetching Destination Address 1 next 11011010 Fetching Destination Address 2 next 10111110 Fetching Link Address 0 next 10111100 Fetching Link Address next 10111010 Fetching Link Address 2 next 01111110 Transferring data next 01111100 Transferring receive status next 01111010 Transferring last received byte next 01111000 Transferring last transmitted byte next Chapter 19 DMA Channels 195 Control Register DOCR Address 0x0181 D1CR Address 0x0191 D2CR Address 0x01A1 D3CR Address 0x01B1 D4CR Address 0x01C1 D5CR Address 0x01D1 D6CR Address 0x01E1 D7CR Address 0x01F1 Bit s Value Description 7 0 Continue to next buffer descriptor 1 Final buffer descriptor Stop DMA operation upon completion of this transfer Use sequential address for next buffer descriptor The link address field is not 6 0 id
189. e normal or the strong spreader setting is used and depending on the operating voltage If the clock doubler is used the spectrum spreader affects every other cycle and reduces the clock high time If the doubler is not used then the spreader affects every clock cycle and the clock low time is reduced Of course the spec trum spreader also lengthens clock cycles but only the worst case shortening is relevant for calculating worst case access times The numbers given for clock shortening with the dou bler disabled are the combined shortening for two consecutive clock cycles worst case The required memory address and output enable access time for some typical clock speeds are given in Table 28 8 below It is assumed that the clock doubler is used that the clock spreader is enabled in the normal mode that the memory early output enable is on and that the address bus has a load of 60 pF Table 28 8 Preliminary Memory Requirements VDDcong 1 8 V 10 VDDio 3 3 V 10 T4 40 C to 85 C address bus loading 60 pF Clock Period Clock Doubler Memory Address Memory Output Frequency Nominal Delay Access Enable Access MHz ns ns ns ns 22 11 45 20 78 51 29 49 34 16 56 36 44 24 22 5 10 33 5 22 58 98 17 6 22 19 Chapter 28 Specifications 311 All important signals on the Rabbit 4000 are output synchronized with the internal clock The internal clock is closely synchr
190. e Rabbit 4000 is a high performance microprocessor with low electromagnetic interfer ence EMI and is designed specifically for embedded control communications and Ethernet connectivity The 8 bit Rabbit 4000 outperforms most 16 bit processors without losing the efficiency of an 8 bit architecture Extensive integrated features and glueless architecture facilitate rapid hardware design while a C friendly instruction set promotes efficient development of even the most complex applications The Rabbit 4000 is fast running at up to 60 MHz with compact code and support for up to 16 MB of memory Operating with a 1 8 V core and 3 3 or 1 8 V I O the Rabbit 4000 boasts an internal 10Base T Ethernet interface eight channels of DMA six serial ports with IrDA 40 digital I O quadrature decoder PWM outputs and pulse capture and measure ment capabilities It also features a battery backable real time clock glueless memory and interfacing and ultra low power modes Four levels of interrupt priority allow fast response to real time events Its compact instruction set and high clock speeds give the Rabbit 4000 exceptionally fast math logic and I O performance 1 2 Features The Rabbit 4000 has several powerful design features that practically eliminate EMI prob lems which is essential for OEMs that need to pass CE and regulatory radiofrequency emissions tests The amplitude of any electromagnetic radiation is reduced by the internal spectr
191. e first Timer A8 clock after the mode is selected and the stop condition is generated when the count matches the value written into the counter MSB and LSB registers This allows an interrupt to be generated and the counter halted when a particular count is reached The stop condition will never occur if no value is written into the registers 21 1 3 Block Diagram Input Capture Channel x perclk Counter ICLxR Parallel Interrupt Port Pins Request ri Edge rst ICCR ICSxR ICTxR ICTxR Interrupt Generation ICCSR 220 Rabbit 4000 Microprocessor User s Manual 21 1 4 Registers Register Name Mnemonic Address R W Reset Input Capture Ctrl Status Register ICCSR 0x0056 R W_ 00000000 Input Capture Control Register ICCR 0 0057 W 00000000 Input Capture Trigger 1 Register ICTIR 0x0058 R W 00000000 Input Capture Source 1 Register ICSIR 0x0059 Input Capture LSB 1 Register ICLIR 0x005A R XXXXXXXX Input Capture MSB 1 Register ICMIR 0x005B R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0x005C R W 00000000 Input Capture Source 2 Register ICS2R 0x005D Input Capture LSB 2 Register ICL2R 0 005 R XXXXXXXX Input Capture MSB 2 Register ICM2R 0 005 R XXXXXXXX Chapter 21 Input Capture 221 21 2 Dependencies 21 2 1 I O Pins Each input capture channel can accept inpu
192. e in a bit position enables the corresponding bit of the termination byte to be used in the compare to generate the termination 7 0 condition A zero in a bit position disables the corresponding bit from contributing to the termination condition A value of all zeros in this register disables the termination byte match feature DMA y Buffer Unused 7 0 Register DOBUOR Address 0x010A D1BUOR Address 0x011A D2BUOR Address 0x012A D3BUOR Address 0x013A DABUOR Address 0x014A D5BUOR Address 0x015A D6BUOR Address 0x016A D7BUOR Address 0x017A Bit s Value Description Bits 7 0 of the buffer unused length value are stored in this register The DMA copies the buffer remaining length to this register at the completion of the 7 0 transfer Normally the buffer remaining length is zero but if the transfer terminates early under source control or because of a termination byte match the number of unused bytes in the buffer is written Chapter 19 DMA Channels 193 Buffer Unused 15 8 Register DOBU1R Address 0x010B D1BU1R Address 0x011B D2BU1R Address 0x012B D3BU1R Address 0x013B D4BU1R Address 0x014B D5BU1R Address 0x015B D6BU1R Address 0x016B D7BU1R Address 0x017B Bit s Value Description 7 0 Bits 15 8 of the buffer unused length value are stored in this register DMA y Initial Addr 7 0 Register
193. e interrupts is shown below The use of SETUSRP and SETSYSP provides checks against stack mismatches and incorrect System User Modes coming out of the User Mode handler svstemmode isr handle interrupt sures ipres ret usermode isr push su setusrp 0x1234 call user handler setsysp 0x1234 sures ipres ret jumped to from interrupt vector table reenter previous mode restore previous interrupt priority jumped to from interrupt vector table still in system mode at this point preserve current SU stack enter user mode with stack compare value handle interrupt at user level return to system mode reenter previous mode restore previous interrupt priority Chapter 27 System User Mode 293 27 4 Register Descriptions Real Time Clock User Enable Register RTUER Address 0x0300 Bit s Value Description 7 0 Disable User Mode access to the RTC I O addresses 0 0002 0 0007 1 Enable User Mode access to the RTC I O addresses 0 0002 0 0007 6 0 These bits are reserved and should be written with zeros Slave Port User Enable Register SPUER Address 0x0320 Bit s Value Description E 0 Disable User Mode access to the slave port I O addresses 0 0020 0 0027 1 Enable User Mode access to the slave port I O addresses 0 0020 0 0027 6 0 These bits are reserved and should be written with zeros Parallel Port A User Enable Regist
194. e priority level for all DMA transfers Setting an interrupt priority to something greater than the DMA transfer priority will ensure that no DMA activity occurs during that interrupt handler Note that when both an interrupt and a DMA transfer are pending the DMA transfer will be selected for execution first provided its priority is equal or greater than the current processor priority level Table 19 2 DMA Transfer Priority DMA Transfers at Operation ee DMA transfers only allowed when Priority 0 n processor priority at 0 das DMA transfers only allowed when Priority 1 processor priority at 0 or 1 ae DMA transfers only allowed when Priority 2 57 processor priority at 0 1 or 2 Priority 3 DMA transfers allowed at any time Chapter 19 DMA Channels 179 When a DMA transfer is occurring normal code execution will not occur until the transfer is completed To prevent DMA transfers from excessively blocking interrupts or otherwise interfering with normal code execution two options can be set in DMTCR First the max imum limit of a DMA transfer can be set from to 64 bytes which sets an upper limit on interrupt latency arising from a DMA transfer Second the minimum number of clocks before the DMA can be active again can be set from 12 to 512 clocks guaranteeing processing time for the application The values providing roughly equal access to the memory bus for both the processor and the DMA is
195. e starting input 10 The Start condition is the falling edge of the starting input 11 The Start condition is either edge of the starting input 1 0 00 Ignore the ending input These two bits are ignored in Counter operation 01 The Stop condition is the rising edge of the ending input 10 The Stop condition is the falling edge of the ending input 11 The Stop condition is either edge of the ending input Chapter 21 Input Capture 227 Input Capture Source x Register ICS1R Address 0x0059 ICS2R Address 0x005D Bit s Value Description 7 6 00 Parallel Port C used for Start condition input 01 Parallel Port D used for Start condition input 10 Parallel Port E used for Start condition input 11 This bit combination is reserved and should not be used 5 4 00 Use port bit 1 for Start condition input 01 Use port bit 3 for Start condition input 10 Use port bit 5 for Start condition input 11 Use port bit 7 for Start condition input 3 2 00 Parallel Port C used for Stop condition input 01 Parallel Port D used for Stop condition input 10 Parallel Port E used for Stop condition input 11 This bit combination is reserved and should not be used 1 0 00 Use port bit 1 for Stop condition input 01 Use port bit 3 for Stop condition input 10 Use port bit 5 for Stop condition input 11 Use port bit 7 for Stop condition input Input Capture LSB x Register
196. eakpoint interrupt will always be handled first 25 3 Operation The following steps must be taken to enable breakpoints 1 Write the vector to the interrupt service routine to the external interrupt table 2 Write the desired breakpoint addresses to the appropriate breakpoint address registers BxAyR where x is the breakpoint and y is the byte of the address 0 2 3 Write an address mask for the given breakpoints BxMyR 4 Select the breakpoint address match type execute data read data write by writing to the appropriate BxCR 5 Enable the desired breakpoints by writing to BDCR 25 3 1 Handling Interrupts The following actions occur within the interrupt service routine e Which breakpoints are pending should be determined by reading BDCR This also clears the pending breakpoints e The desired breakpoint action should be taken e If single step functionality is desired the breakpoint interrupt should be re enabled by writing the appropriate bit to BDCR If this is done the interrupt handler needs to be exited in a particular manner see below 266 Rabbit 4000 Microprocessor User s Manual 25 3 2 Example ISR A sample interrupt handler is shown below breakpoint isr push af ioi ld BDCR determine which interrupts are pending and clear the interrupt request handle all breakpoints here r reenable any breakpoints by writing to BDCR r pop af ipres you must exit the handler with th
197. ecting the slave port or the auxiliary I O bus modes When the slave port is enabled either under program control or during parallel bootstrap Parallel Port B pins carry the Slave Attention output signal and four of the inputs carry the Slave Read strobe Slave Write strobe and Slave Address bits The Slave Chip Select can also be programmed to come from a Parallel Port B pin When the auxiliary I O bus option is enabled either six or eight pins carry the external I O address signals selected in SPCR Two pins are used for the clocks for Serial Ports A and B when they are configured for the clocked serial mode These two inputs can be used as clock outputs for these ports if selected in the respective serial port control registers Note that the clocked serial output clock selection overrides all other programming for the two relevant Parallel Port B pins Table 9 1 Parallel Port B Pin Alternate Output Functions Pin Name Slave Port ile Dore y o PB7 SLVATN IA5 PB6 5 IA4 PB5 SA1 gt 4 5 0 IA2 PB3 SRD Al PB2 SWR SCLKA IA7 PBO SCLKB IA6 Chapter 9 Parallel Port B 77 9 1 1 Block Diagram Parallel Port B 7 0 oe PBDR SA1 SAO SLAVATTN 7 2 SCS SRD SWR External I O 7 2 7 0 EL AN Serial Ports A amp B 1 0 Clocks 9 1 2 Registers Register Name Mnemonic I O Address R W Reset Port B Data Register PBDR 0x0
198. eg ister asynch mode 142 Serial Port x Extended Reg ister clocked serial mode use en eine 143 Serial Port x Long Stop Register 138 Serial Port x Status Register asynch mode 139 Serial Port x Status Register clocked serial mode 140 Serial Ports 147 Serial Port x Address Register 155 Serial Port x Control Register 158 Serial Port x Data Register 155 Serial Port x Divider High Register 160 Serial Port x Divider Low Register 160 Serial Port x Extended Reg ister asynch mode 159 Serial Port x Extended Reg ister HDLC mode 160 Serial Port x Long Stop Register 155 Serial Port x Status Register asynch mode 156 Serial Port x Status Register HDLC mode 157 slave port 162 Slave Port Control Register ater 171 Slave Port Data x Registers DUO egere E Re 170 Index 345 registers slave port continued Slave Port Status Register registers System User mode cont d Serial Port D User Enable registers Timer C continued Timer C Control Register 170 Register 208 system management 32 Serial Port E User Enable Timer C Control Status Battery Backed Onchip Register e 298 Register
199. egister PEB5R Address 0x007D Bit s Value Description 7 6 4 0 These bits are ignored The port buffer bit 5 is written with the value of this bit The port buffer will be 5 Write transferred to the port output register on the next rising edge of the peripheral clock Chapter 12 Parallel Port E 105 Parallel Port E Bit 6 Register PEB6R Address 0x007E Bit s Value Description 7 5 0 These bits are ignored The port buffer bit 6 is written with the value of this bit The port buffer will be 6 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 7 Register PEB7R Address 0x007F Bit s Value Description 6 0 These bits are ignored The port buffer bit 7 is written with the value of this bit The port buffer will be 7 Write transferred to the port output register on the next rising edge of the peripheral clock 106 Rabbit 4000 Microprocessor User s Manual 13 TIMER A 13 1 Overview The Timer A peripheral consists of ten separate eight bit countdown timers 1 10 Each counter counts down from a programmed time constant which is automatically reloaded into the respective counter when the count reaches zero For example if the reload register contains 127 then 128 pulses enter on the left before a pulse exits on the right see Figure 13 1 If the reload register conta
200. eight bytes per burst and 64 clocks between bursts When starting up the DMA requires several cycles of overhead This overhead comes about because the DMA actually uses part of the processor to perform the data transfers and consists of one instruction fetch time plus three clock cycles The byte fetched during the instruction fetch time is discarded and will be refetched at the completion of the DMA burst At the end of the DMA burst two clock cycles are required before this first instruc tion fetch starts An individual DMA channel transfers data without any overhead between bytes but there is always one clock cycle of dead time when switching between DMA channels Table 19 3 shows the number of clock cycles required per burst assuming a sin gle DMA channel transfer and no wait states Table 19 3 Maximum DMA Transfer Rates Setting Total Clocks o M byte per burst 11 clocks 11 2 bytes per burst 15 clocks 7 5 3 bytes per burst 19 clocks 6 3 4 bytes per burst 23 clocks 5 8 8 bytes per burst 39 clocks 4 9 16 bytes per burst 71 clocks 4 4 32 bytes per burst 135 clocks 4 2 64 bytes burst 263 clocks 4 1 The total number of clocks listed in Table 19 3 is related to the number of bystes per burst by the following formula Total Clocks 4 x Number of Bytes per Burst 7 for overhead 180 Rabbit 4000 Microprocessor User s Manual 19 3 4 DMA Channel Priority It is possible to
201. el Port A is a byte wide output port 010 Enable the slave port with SCS from Parallel Port E bit 7 011 Enable the auxiliary T O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination is reserved and should not be used 101 This bit combination is reserved and should not be used 110 Enable the slave port with SCS from Parallel Port B bit 6 11 Enable the auxiliary I O bus Parallel Port A is used for the data bus and Parallel Port B 7 0 is used for the address bus 1 0 00 Slave port interrupts are disabled 01 Slave port interrupts use Interrupt Priority 1 10 Slave port interrupts use Interrupt Priority 2 11 Slave port interrupts use Interrupt Priority 3 80 Rabbit 4000 Microprocessor User s Manual 10 PARALLEL PORT 10 1 Overview Parallel Port is byte wide port with each bit programmable for data direction and drive level These are simple inputs and outputs controlled and reported in the Port C Data Reg ister PCDR All the Parallel Port C pins have alternate output functions and most of them can be used as inputs to various on chip peripherals Table 10 1 Parallel Port C Pin Alternate Output Functions Pin Name Alt Out 0 Alt Out 1 Alt Out 2 Alt Out 3 PC7 TXA 17 PWM3 SCLKC PC6 TXA 16 PWM2 TXE 5 15 PWMI RCLKE PCA TXB 14 PWMO TCLKE PC3 TXC SCLKD PC2 TXC 12
202. emory can be write protected in 64KB blocks and two of those 64KB blocks can be protected with a granularity of 4KB A Priority 3 interrupt will occur if a write is attempted in one of the protected 64KB or 4KB blocks In addition it is possible to place limits around the code execution stack and gen erate an interrupt if a stack related write occurs within 16 bytes of those limits 5 1 1 Block Diagram Interrupt Interrupt Handler Request Physical ICSx Logical Address Memorv Memorv Bank IWEx Address Protection Control lOEx D 15 0 WPCR A 23 0 WPxR WPSyR WPSyLR WPSyHR SEGSIZE STKCR STKzLR Chapter 5 Memory Management 43 5 1 2 Registers Register Name Mnemonic Address R W Reset MMU Instruction Data Register MMIDR 0x0010 00000000 Stack Segment Register STKSEG 0x0011 00000000 Stack Segment LSB Register STKSEGL 0x001A R W 00000000 Stack Segment MSB Register STKSEGH 0x001B R W 00000000 Data Segment Register DATSEG 0x0012 R W 00000000 Data Segment LSB Register DATSEGL 0 001 R W 00000000 Data Segment MSB Register DATSEGH 0 001 R W 00000000 Segment Size Register SEGSIZE 0x0013 R W 11111111 Memory Bank 0 Control Register MBOCR 0x0014 00001000 Memory Bank 1 Control Register MBICR 0 0015 Memory Bank 2 Control Register MB2CR 0x0016
203. en FIFO is half full 1 DMA request when FIFO is one fourth full 5 0 Normal receiver operation 1 Place receiver in Monitor mode Receiver operates normally but does not buffer frames to memory 4 0 Receive frames less than 64 bytes in length discarded 1 Receive frames as short as 8 bytes accepted 3 0 Receive frames with errors discarded Reclaim buffer space 1 Receive frames with errors accepted Do not reclaim buffer space 2 0 Receive frames with broadcast address ignored 1 Receive frames with broadcast address accepted 1 0 Receive frames with multicast addresses ignored 1 Receive frames with multicast addresses accepted if passing hashing filter 0 0 Receive frames with mismatched physical addresses are ignored 1 Receive frames with any physical address accepted Promiscuous mode 216 Rabbit 4000 Microprocessor User s Manual Network Port A Physical Address x Register Address 0x0210 NAPA1R Address 0x0211 NAPA2R Address 0x0212 NAPA3R Address 0x0213 NAPA4R Address 0x0214 NAPA5R Address 0x0215 Bit s Value Description 7 0 Write Byte of physical address for receive address filtering Network Port A Multicast Filter x Register NAMFOR Address 0x0218 NAMF1R Address 0x0219 NAMF2R Address 0x021A Address 0x021B NAMF4R Address 0x021C NAMF5R Address 0x021D NAMF6
204. ent with the interrupt request and are reset when read from the ICSxR peRICLOCK IL LL LT LLL FL LJ LI LI TIMER A8 CPT INPUT INTERRUPT 222 Rabbit 4000 Microprocessor User s Manual 21 3 Operation 21 3 1 Input Capture Channel The following steps explain how to set up an input capture channel 1 Configure Timer 8 via TAT8R to provide the desired input capture clock 2 Configure ICTxR to provide the desired start stop operation and conditions 3 Configure ICSXR to select the input pins for the start and stop conditions 4 Configure ICCR to select either the count or the capture mode 5 Reset the counter by writing to ICCSR 21 3 2 Handling Interrupts The following steps explain how an interrupt is used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure the Input Capture Control Status Register ICCSR to select events that will generate an interrupt 3 Configure the Input Capture Control Register ICCR to select the interrupt priority note that interrupts will be enabled once this value is set this step should be done last The following actions occur within the interrupt service routine e If needed the current counter value can be read from ICLxR and LCMxR reading from latches the value of ICLxR so ICLxR should always be read first e Ifthe counter is expected to roll over determine if that is why the interrupt occurred b
205. equest is cleared by reading from TCCSR 15 3 2 Example ISR A sample interrupt handler is shown below timerC isr push af Save used registers ioi 14 TCCSR clear the interrupt request and get status handle all interrupts flagged in TCCSR here pop af restore used registers ipres ret Chapter 15 Timer C 125 15 4 Register Descriptions Timer C Conirol Status Register TCCSR Address 0x0500 Bit s Value Description 7 2 These bits are always read as zero 1 0 Timer C divider has not reached its maximum value Read 1 Timer divider has reached its maximum value This status bit is cleared by the only read of this register as is the Timer C interrupt 0 0 The main clock for Timer C the peripheral clock divided by 2 is disabled 1 The main clock for Timer C the peripheral clock divided by 2 is enabled Timer C Control Register TCCR Address 0x0501 Bit s Value Description 7 4 These bits are reserved and should be written with zero 3 2 00 Timer C clocked by the peripheral clock divided by 2 01 Timer clocked by the output of Timer 1 10 Timer C clocked by the peripheral clock divided by 16 11 Timer C clocked by the peripheral clock divided by 16 1 0 00 Timer C interrupts are disabled 01 Timer interrupt uses Interrupt Priority 1 10 Timer C interrupt uses Interrupt Priority 2 11 Timer C interrupt uses Interrupt Priority 3
206. er s Manual Serial Port x Control Register SACR Address 0x00C4 SBCR Address 0x00D4 SCCR Address 0x00E4 SDCR Address 0 00 4 Bit s Value Description 7 6 00 No operation These bits are ignored in the asynchronous mode 01 the clocked serial mode start byte receive operation 10 In the clocked serial mode start a byte transmit operation T In the clocked serial mode start a byte transmit operation and a byte receive operation simultaneously 5 4 00 Parallel Port is used for input 01 Parallel Port D is used for input 10 Parallel Port E is used for input 11 Disable the receiver input 3 2 00 Asynchronous mode with 8 bits per character 01 Asynchronous mode with 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data 10 Clocked serial mode with external clock 11 Clocked serial mode with internal clock 1 0 00 The serial port interrupt is disabled 01 The serial port uses Interrupt Priority 1 10 The serial port uses Interrupt Priority 2 11 The serial port uses Interrupt Priority 3 Chapter 16 Serial Ports D 141 Serial Port x Extended Register SAER Address 0x00C5 Asynchronous Mode Only SBER Address 0x00D5 SCER Address 0x00E5 SDER Address 0x00F5 Bi
207. er PAUER Address 0x0330 Bit s Value Description 7 0 Disable User Mode access to Parallel Port A I O addresses 0 0030 0 0037 1 Enable User Mode access to Parallel Port A I O addresses 0 0030 0 0037 6 0 These bits are reserved and should be written with zeros Parallel Port B User Enable Register PBUER Address 0x0340 Bit s Value Description 7 0 Disable User Mode access to Parallel Port B I O addresses 0x0040 0x0047 1 Enable User Mode access to Parallel Port I O addresses 0 0040 0 0047 6 0 These bits are reserved and should be written with zeros Parallel Port C User Enable Register PCUER Address 0x0350 Bit s Value Description 7 0 Disable User Mode access to Parallel Port I O addresses 0 0050 0 0055 1 Enable User Mode access to Parallel Port C I O addresses 0 0050 0 0055 6 0 These bits are reserved and should be written with zeros 294 Rabbit 4000 Microprocessor User s Manual Parallel Port D User Enable Register PDUER Address 0x0360 Bit s Value Description 7 0 Disable User Mode access to Parallel Port D I O addresses 0 0060 0 006 1 Enable User Mode access to Parallel Port D I O addresses 0 0060 0 006 6 0 These bits are reserved and should be written with zeros Parallel Port E User Enable Register PEUER Address 0x0370 Bit
208. er R giSters erecto rre nO a RF as Ree ki 134 cere Eee teg d 134 16 3 Operation i i eet rr OX UBRO GERNE ERFURT IEEE 135 16 3 1 Asynchronous tette ree a pe tree f 135 16 3 2 Clocked Serial Mode si eee 136 16 4 Register Descriptions uere ueteri rt Ee Se ee eee Nd 138 Chapter 17 Serial Ports E F 145 WEBS AU M 145 171 1 Block Diagr tai etae eene E DE 146 1 1 2 utc Pm 147 17 2 Dependencies Shea shines ERU A eret he et ee ERES 148 17 21 W O PMS Er Pb ed P OU e 148 1722 COCKS Em 148 17 2 3 Other R gistets nedir a eene beeen AE ori 148 149 17 9 150 17 3 1 Oy ite i gees 150 17 3 2 L i Geach 150 17 3 3 More on Clock Synchronization and Data Encoding 2 151 17 4 Register Descriptions dote see steed sot iei 155 Chapter 18 Slave Port 161 SONUS 161 18 11 Block Diagram si a EHE ae 162 18 1 2 ERE ei 162 18 2 Pependencies einer tete etie Ce Ie e Ap ERR RU Ee er ce ted EVER
209. erial ports A or B 2 If the slave port or the auxiliary I O bus is selected refer to the chapters for those peripherals for further setup information Once the port is set up data can be read or written by accessing PBDR The value in PBDR of an output pin will reflect its current output value but any value written to an input pin will not appear until that pin becomes an output 9 4 Register Descriptions Parallel Port B Data Register PBDR Address 0x0040 Bit s Value Description 7 0 Read The current state of Parallel Port B pins 7 is reported The Parallel Port B buffer is written with this value for transfer to the Parallel ML Port B output register on the next rising edge of the peripheral clock Parallel Port B Data Direction Register PBDDR Address z 0x0047 Bit s Value Description 7 0 0 corresponding port bit is input 1 The corresponding port bit is an output Chapter 9 Parallel Port 79 Slave Port Control Register SPCR Address 0x0024 Bit s Value Description 7 0 Program fetch as a function of the SMODE pins 1 Ignore the SMODE pins program fetch function 6 5 Read These bits report the state of the SMODE pins Write These bits are ignored and should be written with zero 4 2 000 Disable the slave port Parallel Port A is a byte wide input port 001 Disable the slave port Parall
210. eripherals are being fed bytes for transmit via DMA The current DMA buffer has been marked with special treatment for last byte The buffer has not been marked as final buffer The DMA fills the transmit FIFO with the next to last byte of the buffer and then either switches to another channel or releases the bus The DMA then returns to the channel before the transmitter has had a chance to transmit a single byte freeing space in the transmit FIFO Chapter 19 DMA Channels 185 When all these conditions occur the DMA will overwrite the next to last byte in the transmit FIFO and that particular byte will never be transmitted There are several ways to avoid this bug Always mark the buffer that contains the end of frame byte as the final buffer and restart the DMA once that buffer has been transmitted Make sure that the DMA will not return to this channel before the transmitter has sent one byte from the transmit FIFO Place the end of frame byte a separate DMA buffer The Ethernet driver provided by Rabbit Semiconductor in Dynamic C is written so that this bug never occurs 19 3 8 DMA Block Copy Interaction When a DMA transfer occurs during a block copy instruction LDIR LDDR COPY COPYR UMA or UMS while executing code out of 16 bit memory with the advanced 16 bit mode enabled the code prefetch queue and program counter will become out of synch This means that one or two incorrect
211. ers during block copy instructions either by disabling the DMA or by increasing the processor priority above the priority of the DMA transfer There is a workaround The processor s BC register is used as a program counter by the block copy instructions and will be nonzero if the block copy instruction did not com plete By checking the value of BC and jumping back to the block copy instruction if it is nonzero the block copy instruction is restarted with all the current register values source and destination pointers and will continue where it left off Rabbit Semicon ductor s Dynamic C compiler automatically includes this wrapper code whenever it identifies a block copy instruction 5 Single byte timed and external DMA requests to internal I O registers when timed or external DMA requests are enabled and set to transfer a single byte at a time to an internal I O register two bytes will actually be transferred The simplest workaround is to double each data byte in the buffer two bytes will be transmitted but they will be identical so the actual I O register setting will not change 6 Wait states when moving from advanced 16 bit mode to basic modes a wait state may be missed when certain instructions transfer execution from a device operating in the advanced 16 bit mode to a device operating in a different memory interface mode Depending on the characteristics of the memory being accessed this can lead to a missed or inco
212. ervisor Yes Clock Modes 1x 2x 2 3 4 6 8 Power Down Modes Sleepy 32 kHz Ultra Sleepy 16 8 2 kHz Auxiliary I O Bus 8 data 8 address lines Chapter 1 The Rabbit 4000 Processor 1 5 Comparing Rabbit Microprocessors The Rabbit 2000 Rabbit 3000 and Rabbit 4000 features are compared below Feature Rabbit 4000 Rabbit 3000 Rabbit 2000 Maximum Clock Speed industrial 60 MHz 55 5 MHz 30 MHz Maximum Clock Speed commercial 60 MHz 58 8 MHz 30 MHz Maximum Crystal Frequency Main Oscillator may be doubled internally up 60 MHz 30 MHz 30 MHz to maximum clock speed 32 768 kHz Crystal Oscillator External External Internal Operating Voltage core PEVE i 3 3 1 8 V 3 3 V 1096 5 0 10 Operation Voltage I O 10 Maximum I O Input Voltage 3 6 5 5 V 5 5 V Current Consumption Tos 2 mA MHz 3 3 V 4mA MHz 6 5 V Number of Package Pins 128 128 100 Size of Package LOFP PQFP 16x16x1 5mm 16x 16x 1 5 mm 24x 18x 3mm Spacing Between Package Pins 0 4 mm 16 mils 0 4 mm 16 mils 0 65 mm 26 mils Size of Package TFBGA 10x 10x 1 2 mm 10 x 10 1 2 mm Not available Spacing Between Package Pins 0 8 mm 0 8 mm Separate Power and Ground for I O Buffers EMI reduction is M Clock Spectrum Spreader Yes Yes Rabbit 2000B C 1 2x 2 3 1x 2x 2 3 Clock Modes 4 16 18 4 16 18 1 2x 4
213. es Chapter 16 Serial Ports D 133 16 2 2 Clocks The data clocks for Serial Ports A D are based on the peripheral clock and are divided by either a Timer A divider or a dedicated 15 bit divider In either case the overall clock divider will be the value in the appropriate register plus one 16 2 3 Other Registers Register Function TAT4R Time constant for Serial Port A TATSR Time constant for Serial Port B TAT6R Time constant for Serial Port C TAT7R Time constant for Serial Port D PCFR PCAHR PCALR PDFR PDAHR PDALR Alternate port output selection PEFR PEAHR PEALR 16 2 4 Interrupts A serial port interrupt can be generated whenever a byte is available in the receive buffer or when a byte is finished being transmitted out of the transmit buffer The serial port interrupt vectors are located in the as follows e Serial Port A at offset OxOCO e Serial Port B at offset OxODO e Serial Port C at offset 0 0 0 e Serial Port D at offset OxOFO Each of them can be set as Priority 1 2 or 3 in SxCR where x is A D for the four serial ports 134 Rabbit 4000 Microprocessor User s Manual 16 3 Operation 16 3 1 Asynchronous Mode The following steps explain how to set up Serial Ports A D for asynchronous operation The serial ports can be used by polling the status byte but their performance will be better with an interrupt These instructions also apply to the async
214. ese two ret instructions if you reenabled breakpoints Chapter 25 Breakpoints 267 25 4 Register Descriptions Breakpoint Debug Control Register BDCR Address 0x001C Bit s Value Description 7 0 Normal RST 28h operation 1 RST 28h is NOP 6 0 0 The corresponding Breakpoint request is not pending The corresponding Breakpoint request is pending Reading this register Read 1 automatically clears all pending breakpoint requests 6 0 0 No effect on the corresponding Breakpoint request Write 1 Make the corresponding Breakpoint request pending Breakpoint x Control Register BOCR Address 0x030B B1CR Address 0x031B B2CR Address 0x032B Address 0x033B B4CR Address 0x034B B5CR Address 0x036B B6CR Address 0x037B Bit s Value Description 7 6 00 No Breakpoint x on execute address match 01 Breakpoint x on User Mode execute address match 10 Breakpoint x on System Mode execute address match 11 Breakpoint x on System or User Mode execute address match 5 4 00 No breakpoint x data read address match 01 Breakpoint x on User Mode data read address match 10 Breakpoint x on System Mode data read address match 11 Breakpoint x on System or User Mode data read address match 3 2 00 No breakpoint x on write address match 01 Breakpoint x on User Mode write address match 10 Breakpoint x on System M
215. external I O cycles 01 BUFEN is active low during data memory accesses 10 BUFEN pin is low 11 BUFEN pin is high Chapter 2 Clocks 23 Network Port Conirol Regisiter NACR Address 0x0207 Bit s Value Description 7 6 00 Disable the Ethernet clock 01 Ethernet clock from PE6 on Parallel Port 10 Ethernet clock from peripheral clock 11 Ethernet clock from peripheral clock divided by 2 5 4 These bits unused and should be written with zero 3 0 Normal operation 1 Restart auto negotiation process 2 0 Disable auto negotiation function 1 Enable auto negotiation function 1 0 half duplex operation If auto negotiation is enabled only half duplex operation will be advertised Enable full duplex operation If auto negotiation is disabled this forces full 1 duplex operation If auto negotiation is enabled this allows advertising full duplex capability 0 This bit is unused and should be written with zero 24 Rabbit 4000 Microprocessor User s Manual 3 RESET AND BOOTSTRAP 3 1 Overview The Rabbit 4000 s RESET pin initializes everything in the processor except for the real time clock registers and the contents of the battery backed onchip encryption RAM If a write cycle is in progress it waits until the write cycle is completed to avoid potential memory corruption After reset the Rabbit 4000 checks the sta
216. f duplex or full duplex mode selected via auto negotiation The network port requires an accurate 20 MHz clock to generate the 10 Mbits s serial rate of 10Base T This clock can come from the main system clock or a dedicated 20 MHz input under program control The clock for the network port may also be disabled to con serve power The network port contains synchronization circuitry to allow operation from the 20 MHz reference clock while the main system clock runs independently The network port transmitter precedes the transmit data automatically with a preamble and start frame delimiter and appends CRC and the end frame delimiter after the last byte Frame transmission starts automatically once the transmit FIFO is full and any interframe gap time or back off time has expired Transmission is aborted if a collision is detected and is retried up to 16 times using the standard random back off time algorithm Detection of a collision causes the transmitter to send a 32 bit jam pattern of all ones to guarantee that all receivers in the network recognize the collision The transmitter uses the 10 most significant bits of the CRC checker starting with bit 22 and increasing to generate the initial seed for the back off algorithm Collisions that occur later than one slot time 512 bit times are reported as late collisions but are otherwise treated identically to normal collisions If a transmission is not successful after 16 attempts the
217. g Rabbit Microprocessors 40 40 1 nennen eene nn nt nn nr 6 Chapter 2 Clocks 9 DM QV CD M 9 2 1 1 Block Diagram 3 idee Dee ERO te e RERO HEN EEEE 10 2 4122 Juro I A 10 2 2 Dependencies eode niente Gd nO OPEP E ion ent ante 11 22E Ne a E A E E ER E EE EE E E ORE EEE 11 2 252 left MM EE 11 PESCE c 12 2 3 Mam Clock i RIMIS UNI UIN 12 2 5 2 Spectrum Spreader eee ertet hee DS SERE P EET eoe e UR REPRE eR HER Un 13 Doublet C 15 2 3 4 32 KHz Clock atti eterne EAE EE ene 18 24 cag Ng ED A E 20 Chapter 3 Reset and Bootstrap 25 21 QV CTV IC Ws ses Ue ge 25 3 1 1 Block e MH P M 25 3 1 2 TUE CECI OC DO QU LI DITE 26 3 2 Dependenties 26 221 e A enisi as fein p 26 3 2 2 E E 26 3 2 3 a e 26 3 2 4 icum Be Dm 26 EE Scc
218. gisters are marked full when written by the source side of the interface and are marked empty when read by the destination side of the interface The hardware interface to the external master consists of an 8 bit bidirectional data bus with a read strobe write strobe and chip select There are two address lines that select one of the three data registers or the status register Table 18 1 Slave Port Addresses Slave Port Address Slave Port Register 00 Data Register 0 01 Data Register 1 10 Data Register 2 11 Status Register A slave attention signal is asserted when the processor writes to one of the slave port data registers SPDOR and can be deasserted by the master by performing a dummy write to the status register This signal can be used to interrupt the master to indicate that the mas ter needs to read data from the slave The slave port interrupt is asserted when the master writes to SPDOR The processor clears this interrupt condition by writing to the status register Chapter 18 Slave Port 161 The slave port can be used to bootstrap the processor by setting the SMODE pins appro priately See Chapter 3 for more information on this mode 18 1 1 Block Diagram Slave Port ISLVATTN SDO SD7 5 0 5 1 SRD ISWR ISCS 18 1 2 Registers Slave ATTN Interrupt Interrupt Request Generation Request Bus Processor Interface Register Name Mnemonic I O Address R
219. handler is shown below extint isr respond to external interrupt here interrupt is automaticallv cleared bv interrupt acknowledge ipres ret 70 Rabbit 4000 Microprocessor User s Manual 7 5 Register Descriptions Interrupt x Control Register IOCR Address 0x0098 H CR Address 0x0099 Bit s Value Description 7 6 00 Parallel Port D low nibble interrupt disabled 01 Parallel Port D low nibble interrupt on falling edge 10 Parallel Port D low nibble interrupt on rising edge 11 Parallel Port D low nibble interrupt on both edges 5 4 00 Parallel Port E high nibble interrupt disabled 01 Parallel Port E high nibble interrupt on falling edge 10 Parallel Port E high nibble interrupt on rising edge 11 Parallel Port E high nibble interrupt on both edges 3 2 00 Parallel Port E low nibble interrupt disabled 01 Parallel Port E low nibble interrupt on falling edge 10 Parallel Port E low nibble interrupt on rising edge 11 Parallel Port E low nibble interrupt on both edges 1 0 00 This external interrupt is disabled 01 This external interrupt uses Interrupt Priority 1 10 This external interrupt uses Interrupt Priority 2 11 This external interrupt uses Interrupt Priority 3 Chapter 7 External Interrupts 71 72 Rabbit 4000 Microprocessor User s Manual 8 PARALLEL PORT 8 1 Overview Parallel Port A is a byte wide port that can be used as a
220. he appropriate pins for each operation 19 2 2 Clocks The DMA peripheral uses the peripheral clock for all operations If the timed request option is enabled then the 16 bit timed request counter will be clocked by the peripheral clock and will provide a DMA request each time it counts down to zero 19 2 3 Interrupts Each DMA channel has its own dedicated interrupt that can occur at the end of any DMA transfer as specified in DyCR normally loaded from the buffer descriptor The interrupt request is automatically cleared when the interrupt is handled The DMA interrupt vectors are in the EIR starting at offset 0x080 for DMA Channel 0 and ending at offset OxOFO for DMA Channel 7 They can be set as Priority 1 2 or 3 Chapter 19 DMA Channels 177 19 3 Operation It is possible to set up and start a DMA operation by writing directly to all the relevant address length and control registers but it is expected that the typical operation would be to create a buffer descriptor in memory write the address of that descriptor to the initial address registers DyIAnR and use a write to DMALR to auto load the values from memory into the registers and start the transfer The DMA transfer will then continue read ing buffer descriptors until a buffer marked halt is completed The descriptor can be either 12 or 16 bytes in length a bit in the channel control byte which corresponds to DyCR selects whether the link address is present or not
221. he basic mode Using this option will produce a loss of performance Finally this bug is best avoided by not using the basic 16 bit mode unless absolutely necessary It is highly likely that any SRAM device that you are executing code in will support the advanced 16 bit mode with byte writes enabled which will also improve the overall performance as a result of the 16 bit data fetches Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds 337 338 Rabbit 4000 Microprocessor User s Manual Numerics bootstrap 25 Ethernet clock 9 block diagram 25 maximum clock speed 17 32 kHz clock 18 dependencies 26 operation 12 oscillator circuit 18 memory fetch 28 OVerVieW 9 A onchip encryption SRAM 28 power consumption 17 register descriptions 29 register descriptions 20 auxiliary I O bus 247 registers 26 YegIStets sisisi iesin 10 operation 252 263 sleepy clock modes 19 handshake 252 block diagram 264 spectrum spreader 9 311 strobes 252 dependencies 266 comparison
222. he biphase mark and the biphase space modes this means the transition that defines the end of the last zero of the closing flag Chapter 17 Serial Ports 153 Figure 17 2 shows the adjustment ranges and output clock for the different modes of operation of the DPLL Each mode of operation will be described in turn BITCELL ijiijijiijiiiiiiil NRZI adj ADD ONE ADD TWO NONE NRZI CLOCK BIPHASE LEVEL adj 4 SUBTRACT none ADD ONE IGNORE BIPHASE LEVEL CLOCK BIPHASE SPACE adj Nonej App one M HUN SY NE NONE BIPHASE SPACE CLOCK BIPHASE MARK adjwowe apoowe SUBTRACT BIPHASE MARK CLOCK Figure 17 2 Adjustment Ranges and Output Clock for Different DPLL Modes With NRZ and NRZI encoding all transitions occur on bit cell boundaries and the data should be sampled in the middle of the bit cell If a transition occurs after the expected bit cell boundary but before the midpoint the DPLL needs to lengthen the count to line up the bit cell boundaries This corresponds to the add one and add two regions shown If a transition occurs before the bit cell boundary but after the midpoint the DPLL needs to shorten the count to line up the bit cell boundaries This corresponds to the subtract one and subtract two regions shown DPLL makes no adjustment if the bit cell boundaries are lined up within one count of the divide by 16 counter The regions tha
223. he channel before the transmitter has had a chance to transmit a single byte freeing space in the transmit FIFO When all these conditions occur the DMA will overwrite the next to last byte in the transmit FIFO and that particular byte will never be transmitted There are several ways to avoid this bug Always mark the buffer that contains the end of frame byte as the final buffer and restart the DMA once that buffer has been transmitted Make sure that the DMA will not return to this channel before the transmitter has sent one byte from the transmit FIFO Place the end of frame byte in a separate DMA buffer The Ethernet driver provided by Rabbit Semiconductor in Dynamic C is written so that this bug never occurs Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds 335 4 DMA block copy interaction when a DMA transfer occurs during a block instruction LDIR LDDR COPY COPYR UMA or UMS while executing code out of 16 bit memory with the advanced 16 bit mode enabled the code prefetch queue and program counter will become out of synch This means that one or two incorrect bytes depending on the 16 bit alignment of the instruction are reloaded and presented to the processor as instructions when execution is rewound after the DMA transfer The result of this mismatch is that the block copy instruction does not complete The only way to prevent this from occurring is to prevent DMA transf
224. he data transitions are at the center of the bit cell and the DPLL opera tion is adjusted accordingly Decoding biphase mark or biphase space encoding requires that the data be sampled by both edges of the recovered receive clock 17 4 Register Descriptions Serial Port x Data Register SEDR Address 0x00C8 SFDR Address 0x00D8 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with a data byte for transmission Serial Port x Address Register SEAR Address 0x00C8 SFAR Address 0x00D8 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Loads the transmit buffer with an address byte marked with a zero address bit Write for transmission In the HDLC mode the last byte of a frame must be written to this register to enable subsequent CRC and closing flag transmission Serial Port x Long Stop Register SELR Address 0x00C8 SFLR Address 0x00D8 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with an address byte marked with a one address bit for transmission Chapter 17 Serial Ports E 155 Serial Port x Status Register SESR Address 0x00CB Asynchronous Mode Only SFSR Address 0x00DB Bit s
225. he setting in SPCR Address bits 6 and 7 can also be enabled on pins PD1 PD5 or PD7 which allows PBO and PBI to be used as clocked serial instead of as external I O The IOWR IORD and BUFEN pins are dedicated strobes for external I O accesses The I O strobes can be directed out to pins on Parallel Ports C D or E each bank can be directed to the appropriate pin bank zero on PCO PDO or PEO bank one on PC1 PD1 or PE etc The strobes will affect outputs on IOWR IORD and BUFEN at all times The I O handshake can be input on any one of the Parallel Port E pins PEO PE7 24 2 2 Clocks external I O accesses strobes and handshake timeouts are based on the processor clock 24 2 3 Other Registers Register Function SPCR Enable the auxiliary I O bus PCFR PCALR PCAHR Select Parallel Port C D or E pins as I O strobe PDFR PDALR PDAHR outputs PEFR PEALR PEAHR Select PD1 PD5 or PD7 as address bits 6 7 24 2 4 Interrupts There are no interrupts associated with external I O Chapter 24 External I O Control 251 24 3 Operation 24 3 1 Auxiliary Bus The following steps must be taken before using auxiliary I O bus 1 Enable the auxiliary I O bus by writing to SPCR Select whether 6 or 8 address bits are desired 2 If PBO and PBI are needed for clocked serial use and eight address bits are required enable the alternate outputs of address bits 6 an
226. hould be written with zero 4 3 00 External DMA Request 1 falling edge triggered One byte per request 01 External DMA Request rising edge triggered One transfer per request 10 External DMA Request 1 active low Transfers continue while low 11 External DMA Request active high Transfers continue while high 2 0 000 External DMA Request supplied to DMA Channel 0 001 External DMA Request 1 supplied to DMA Channel 1 010 External DMA Request supplied to DMA Channel 2 011 External DMA Request 1 supplied to DMA Channel 3 100 External DMA Request 1 supplied to DMA Channel 4 101 External DMA Request 1 supplied to DMA Channel 5 110 External DMA Request supplied to DMA Channel 6 111 External DMA Request supplied to DMA Channel 7 Chapter 19 DMA Channels 191 DMA Timed Request Control Register DTRCR Address 0x0115 Bit s Value Description 7 0 Timed DMA request disabled 1 Timed DMA request enabled 6 5 These bits are reserved and should be written with zeros 4 3 00 Timed DMA request transfers one byte per request 01 This bit combination is reserved and should not be used 10 Timed DMA request triggers transfers until current descriptor is complete DMA channel fetches the next descriptor if appropriate 11 This bit combination is reserved and should not be used 2 0 000 Timed DMA request supplied to DMA Channel 0 001 Timed DMA request supplied to DMA Channel 1
227. hronous operation of Serial Ports 1 Write the interrupt vector for the interrupt service routine to the internal interrupt table 2 Setup the desired transmit pin by writing to the appropriate parallel port function register PxFR and alternate output register PXALR or PXAHR 3 Select the appropriate mode by writing to SxCR receive input port and 7 or 8 bits Also select the interrupt priority 4 Select additional options by writing to SxER parity RZI encoding clock polarity and behavior during break 5 Write the desired divider value to for the appropriate serial port or else write a divider value to the dedicated 15 bit divider in SxDLR and SxDHR If the dedicated divider is to be used write a 1 to the most significant bit of SxDHR to enable it A sample asynchronous serial interrupt handler is shown below for Serial Port A async sera isr push af ioi ld a SASR bit a 7 push af jr 2 check for tx rx ready ioi ld a SADR save used registers get status check if bvte readv in RX buffer save status for next check read bvte and clear interrupt do something with bvte here check for tx pop af bit a 3 jr nz done get next bvte to be ioi 14 SADR done pop af ipres ret check if TX buffer was emptied transmitted into A here load next byte into TX buffer and clear interrupt restore used registers To transmit with an address 1 bit appe
228. ia PDDDR 2 Select high low or open drain functionalitv for outputs via PDDCR 3 f an alternative peripheral output function is desired for a pin select it by via PDALR or PDAHR and then enable it via PDFR Refer to the appropriate peripheral chapter for further use of that pin 4 All these settings will be superseded if a 16 bit memory interface is selected since par allel port D is used for the upper half of the data bus in that mode Once Parallel Port D is set up data can be read or written by accessing PDDR The value of an output pin read in from PDDR will reflect its current output value but any value written to an input pin will not appear until that pin becomes an output Chapter 11 Parallel Port D 91 11 4 Register Descriptions Parallel Port D Data Register PDDR Address 0x0060 Bit s Value Description 7 0 Read The current state of Parallel Port D pins PD7 PDO is reported The Parallel Port D buffer is written with this value for transfer to the Parallel Write in Port D output register on the next rising edge of the peripheral clock Parallel Port D Alternate Low Register PDALR Address 0x0062 Bit s Value Description 7 6 00 Parallel Port D bit 3 alternate output 0 IA7 01 Parallel Port D bit 3 alternate output 1 I3 10 Parallel Port D bit 3 alternate output 2 TIMER C3 11 Parallel Port D bit 3 alternate ou
229. in clock divided by six Peripheral clock from the main clock divided by six 1 0 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 36 Rabbit 4000 Microprocessor User s Manual Real Time Clock Control Register RTCCR Address 0 0001 Bit s Value Description No effect on the real time clock counter or disable the byte increment function 7 0 0x00 or cancel the real time clock reset command Arm the real time clock for reset or byte increment This command must be 0x40 written prior to either the real time clock reset command or the first byte increment write Reset all six bytes of the real time clock counter to 0x00 The reset must be 0x80 a preceded by writing 0x40 to arm the reset function 0xCO Reset all six bytes of the real time clock counter to 0x00 and remain in byte increment mode in preparation for setting the time 7 6 01 This bit combination must be used with every byte increment write 5 0 0 No effect on the real time clock counter 1 Increment the corresponding byte of the real time clock counter Real Time Clock x Register RTCOR Address 0x0002 RTC1R Address 0x0003 RTC2R Address 0x0004 RTC3R Address 0x0005 RTC4R Address 0x0006 RTC5R Address 0x0007 Bit s Value Description 7 0
230. in the PWLOR and PWLIR registers The timing is shown below meRATION 0 1 2 3 4 5 56 7 1 8 OUTPUT 1 4 OUTPUT 1 2 OUTPUT 1 8 INTERRUPT 1 4 INTERRUPT 1 2 INTERRUPT Chapter 23 Pulse Width Modulator 239 The spreading function is implemented by dividing each 1024 clock cycle into four quad rants of 256 clocks each Within each quadrant the Pulse Width Modulator uses the eight MSBs of each pulse width register to select the base width in each of the quadrants This is the equivalent to dividing the contents of the pulse width register by four and using this value in each quadrant To get the exact high time the Pulse Width Modulator uses the two LSBs of the pulse width register to modify the high time in each quadrant according to the table below The n 4 term is the base count formed from the eight MSBs of the pulse width register Pulse Width LSBs 1st 2nd 3rd 4th 00 n A 1 n A n A n A 01 4 1 4 4 1 4 10 nl4 1 4 1 4 1 4 11 4 1 4 1 4 1 4 1 The diagram below shows PWM output for several different width values for both modes of operation Operation in the spread mode reduces the filtering requirements on the PWM output in most cases n 255 normal 256 counts 255 64 counts 64 counts 64 counts 64 counts n 256 spread 65 counts 64 counts 64 counts 64 counts n 257 spread
231. ine which requires link integrity pulses to be detected at certain intervals in the absence of other net work activity For this state machine the link test min value is 4 2 ms and the link test max value is 52 5 ms The link loss time constant is 78 7 ms If the network receiver enters the NLP Link Test Fail state because of missing link test pulses this state machine requires seven successive properly timed link test pulses or an equal number of FLP bursts before reporting that the link is again active The reset state of this state machine is link inactive Note that this is a subtle difference relative to the normal 10Base T receive link integrity state machine which requires either link test pulses or carrier sense to make the link active The network port implements the auto negotiation algorithm to determine half duplex or full duplex operation In addition to its normal automatic operation this feature can be disabled or commanded to execute under software control The clock for the network port is initially disabled to conserve power but may be sourced from either a port pin the system clock actually the internal peripheral clock or the sys tem clock divided by two Since the network port requires a 20 000 MHz clock the clock should normally be supplied from the port pin Using the system clock or a derivative to drive the network port precludes the use of the clock modulator 202 Rabbit 4000 Microprocessor User s Manual
232. inputs to monitor the SLVATTN signals from the slaves In this setup the slave port is used as follows e The slave responds to the interrupt and reads the slave port data registers e When the slave wishes to send data to the master it writes the slave port data registers writing SPDOR last which enables the SLVATTN signal e When the master detects the change on SLVATTN it reads the slave port data registers 18 3 1 Master Setup 1 Enable the I O strobes on PD6 and PD7 by writing to the appropriate Parallel Port D pin and external I O registers 2 Enable the external interrupts on PEO and 1 by writing to the appropriate external interrupt registers 18 3 2 Slave Setup 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure SPCR to select the interrupt priority note that interrupts will be enabled once this value is set Chapter 18 Slave Port 165 18 3 3 Master Slave Communication 1 The master writes data to the appropriate external I O address on the data bus for the slave device and register desired For example in the setup described here the master would write to register SPD2R on the first slave by writing to the address 0xC002 0 000 for the 16 strobe and 0x0002 for SPD2R on that slave 2 If the master is writing multiple bytes it should write to SPDOR last since that will trigger an interrupt on the slave device If only one byte is being sent it should
233. ins zero then each pulse on the left results in a pulse on the right that is there is division by one The reload register can contain any number in the range from 0 to 255 The counter divides by n 1 8 bit Reload Register LOAD TL Zero Count 8 bit Down Counter LL En ae Input Clock Count Value 2 1 0 N N 1 Figure 13 1 Reload Register Operation For Timers A1 A7 the terminal count condition is reported in a status register and can be programmed to generate an interrupt Six of these seven timers A2 A7 have the option of being cascaded from Timer A1 but the primary clock for all of the timers is the periph eral clock either directly or divided by 2 the default The output pulses are always one clock wide Clocking of the timers takes place on the negative edge of this pulse When the counter reaches zero the reload register is loaded into the counter on the next input pulse instead of a count being performed Timers A2 A7 can be used to generate baud rates for Serial Ports or they can be used as general purpose timers if the dedicated timers on the Rabbit 4000 serial ports are used The three remaining timers 8 10 serve as prescalers for the input capture PWM and quadrature decoder peripherals respectively The peripherals clocked by these timers can Chapter 13 Timer A 107 generate interrupts but the timers themselves cannot Furthermore these timers cannot be cascaded with Timer
234. ion T The transmitter finished sending a closing flag Data written in response to this interrupt will cause at least two flags to be transmitted between frames 0 0 The byte in the receiver buffer is 8 bits 1 The byte in the receiver buffer is less than 8 bits Chapter 17 Serial Ports 157 Serial Port x Control Register SECR Address 0x00CC SFCR Address 0x00DC Bit s Value Description 7 6 00 No operation These bits are ignored in the asynchronous mode 01 In HDLC mode force receiver flag search mode 10 No operation 11 In HDLC mode transmit an abort pattern 5 4 00 Parallel Port is used for data and optional clock input 01 Parallel Port D is used for data and optional clock input 10 Parallel Port E is used for data and optional clock input 11 Disable the receiver data input Clocks from Parallel Port E 3 2 00 Asynchronous mode with 8 bits per character 01 Asynchronous mode with 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data 10 HDLC mode with external clock The external clocks are supplied via parallel port pins HDLC mode with internal clock The clock is 16x the data rate and the DPLL is 11 used to recover the receive clock If necessary the receiver and transmitter clocks can be output via parallel port pins 1 0 00 The serial port interrup
235. ion Control Register WPCR Address 0 0440 Bit s Value Description 7 1 These bits are reserved and should be written with zeros 0 0 Write protection in User Mode only Write protection in System and User modes Chapter 5 Memory Management 59 Write Protect x Register WPOR Address 0x0460 WP1R Address 0x0461 WP2R Address 0x0462 WP3R Address 0x0463 WP4R Address 0x0464 WP5R Address 0x0465 WP6R Address 0x0466 WP7R Address 0x0467 WP8R Address 0 0468 WP9R Address 0x0469 WP10R Address 0x046A WP11R Address 0x046B WP12R Address 0x046C WP13R Address 0x046D WP14R Address 0x046E WP15R Address 0x046F WP16R Address 0x0470 WP17R Address 0x0471 WP18R Address 0x0472 WP19R Address 0x0473 WP20R Address 0x0474 WP21R Address 0x0475 WP22R Address 0x0476 WP23R Address 0x0477 WP24R Address 0x0478 WP25R Address 0x0479 WP26R Address 0x047A WP27R Address 0x047B WP28R Address 0x047C WP29R Address 0x047D WP30R Address 0x047E WP31R Address 0x047F Bit s Value Description 7 0 0 Disable write protection for the corresponding 64K segment Enable write protection for the corresponding 64K block The 8 MSBs of the 24 bit physical address of any specific 64K block can be used to determine which write protec
236. is device writing a 01 to bits 6 7 of SxCR will force the receiver back into the flag search mode 150 Rabbit 4000 Microprocessor User s Manual sample HDLC interrupt handler is shown below for Serial Port hdlc sere isr push af ioi lda SESR get status bit a 7 check if byte ready in RX buffer push af Save status for next check jr 2 check for tx rx_ready check status byte in A for abort or invalid CRC flags ioi 14 SADR read byte and clear interrupt store byte A here check for tx pop af bit a 3 check if TX buffer was emptied jr nz done check status byte in A for transmit finish reason CRC abort etc get next byte to be transmitted into A here if it is the last bvte of the packet load it into SEAR or SELR instead ioi ld SEDR a load next bvte into buffer and clear interrupt done pop af ipres ret 17 3 3 More on Clock Svnchronization and Data Encoding The transmitter is not capable of sending an arbitrary number of bits but only a multiple of bytes However the receiver can receive frames of any bit length If the last byte in the frame is not eight bits the receiver sets a status flag that is buffered along with this last byte Software can then use the table below to determine the number of valid data bits in this last byte Note that the receiver transfers all bits between the opening and closing flags except for the inserted zeros to the
237. ister TCSOHR 0x0509 Timer Reset 0 Low Register TCROLR 0 050 Timer Reset 0 High Register TCROHR 0 050 Timer Set 1 Low Register TCSILR 0 050 Timer Set 1 High Register TCS1HR 0x050D Timer Reset 1 Low Register TCRILR 0 050 Timer Reset High Register 0 050 R W XXXXXXXX Timer C Set 2 Low Register TCS2LR 0x0518 Timer Set 2 High Register TCS2HR 0x0519 Timer Reset 2 Low Register TCR2LR 0x051A Timer Reset 2 High Register TCR2HR 0x051B Timer Set 3 Low Register TCS3LR 0 051 Timer Set 3 High Register TCS3HR 0x051D Timer Reset 3 Low Register TCR3LR 0 051 Timer Reset 3 High Register TCR3HR 0 051 R W XXXXXXXX Timer C Block Access Register TCBAR 0 00 8 W XXXXXXXX Timer C Block Pointer Register TCBPR 0 00 9 W 00000010 Chapter 15 Timer C 123 15 2 Dependencies 15 2 1 I O Pins The four Timer outputs can be directed to PDO PD3 or PEO PE3 15 2 2 Clocks The timer in Timer C is a 16 bit up counter clocked by the peripheral clock divided by 2 by the peripheral clock divided by 16 or by the output of timer A1 as selected in TCCR 15 2
238. ite enable lines can be interfaced directly with up to six memory devices Up to 1 MB of memory can be accessed directly via the Dynamic C development software and up to 16 MB can be interfaced with additional software development A built in slave port allows the Rabbit 4000 to be used as master or slave in multi processor systems permit ting separate tasks to be assigned to dedicated processors An 8 line data port and five control signals simplify the exchange of data between devices A remote cold boot enables startup and programming via a serial port or the slave port The Rabbit 4000 features five 8 bit parallel ports yielding a total of 40 digital I O Six CMOS compatible serial ports are available All six are configurable as asynchronous including output pulses in IrDA format while four are configurable as clocked serial SPI and two are configurable as SDLC HDLC The various internal peripherals share the parallel port s I O pins The Rabbit 4000 also offers many specialized peripherals Two input capture channels each have a 16 bit counter clocked by the output of an internal timer that can be used to capture and measure pulses These measurements can be extended to a variety of functions such as measuring pulse widths or for baud rate autodetection Two quadrature decoder channels each have two inputs as well as an 8 or 10 bit up down counter Each quadrature decoder channel provides a direct interface to optical encoder units Fo
239. kHz clock even when the processor and peripheral clocks use a divider on the 32 kHz clock Chapter 2 Clocks 19 2 4 Register Descriptions Global Control Status Register GCSR Address 0x0000 Bit s Value Description 7 6 00 No reset or watchdog timer timeout since the last read rd only 01 The watchdog timer timed out These bits are cleared by a read of this register 10 This bit combination is not possible 11 Reset occurred These bits are cleared by a read of this register 5 0 No effect on the periodic interrupt This bit will always be read as zero 1 Force a periodic interrupt to be pending 42 000 Processor clock from the main clock divided by 8 Peripheral clock from the main clock divided by 8 001 Processor clock from the main clock divided by 8 Peripheral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by 2 Peripheral clock from the main clock divided by 2 100 Processor clock from 32 clock optionally divided via GPSCR Peripheral clock from the 32 kHz clock optionally divided via GPSCR Processor clock from the 32 kHz clock optionally divided via GPSCR 101 Peripheral clock from the 32 kHz clock optionally divided via GPSCR The main clock is disabled 110 Processor clock from the main clock divided by 4 Peripheral clock from the
240. l Mode 112 SMODE pin settings 28 Register e 299 Timer A Time Constant x revision history 333 External Interrupt User Register 113 Enable Register 297 Timer 116 5 VO Bank User Enable Global Control Status serial ports Register 296 Register deep TEE eM 120 clock synchronization and data Input Capture User Enable Timer B Control Register encoding 151 Register eem 295 118 Serial Ports A 129 Parallel Port A User Enable Timer B Control Status block diagram 131 Register 294 Register 118 134 Parallel Port User Enable Timer B Count LSB data cl cks 130 Register EE 294 Register 120 dependencies 133 Parallel Port C User Enable Timer B Count LSB x interrupts 134 Register 294 Register 119 operation 135 Parallel Port D User Enable Timer B Count MSB asynchronous mode 135 Register 295 Register 119 lo ked senal mode Parallel Port E User Enable Timer Count 130 136 Register 295 Register 119 129 PWM User Enable Timer B Step LSB x pin use sedes 133 Register 296 Register
241. l Status Register TBCSR 0 00 0 xxxx0000 Timer B Control Register TBCR 0 00 1 xx000000 Timer B MSB 1 Register TBMIR 0x00B2 Timer LSB 1 Register TBLIR 0x00B3 Timer MSB 2 Register TBM2R 0 00 4 Timer LSB 2 Register TBL2R 0 00 5 Timer Step LSB 1 Register TBSLIR 0 00 Timer Step MSB 1 Register TBSMIR 0 00 Timer Step LSB 2 Register TBSL2R 0 00 Timer Step MSB 2 Register TBSM2R 0x00BD Timer Count MSB Register TBCMR 0 00 R XXXXXXXX Timer B Count LSB Register TBCLR OxOOBF R XXXXXXXX 14 2 Dependencies 14 2 1 I O Pins The output of Timer B does not come out directly on any of the I O pins It can be used to control when the output occurs on Parallel Ports D E 14 2 2 Clocks The timer in Timer B can be clocked by perclk 2 perclk 16 or by countdown timer A1 as selected in TBCR 14 2 3 Other Registers Register Function GCSR Select peripheral clock mode 14 2 4 Interrupts A Timer B interrupt be generated whenever the counter equals one of the match registers by enabling the appropriate bit in TBCSR The interrupt request is cleared when TBCSR is read 116 Rabbit 4000 Microprocessor User s Manual 14 3 Operation The followi
242. le Register ICUER 0x0358 W 00000000 I O Bank User Enable Register IBUER 0x0380 W 00000000 PWM User Enable Register PWUER 0x0388 W 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0x03A0 W 00000000 Timer B User Enable Register TBUER 0x03BO W 00000000 Timer C User Enable Register TCUER Ox3F8 W 00000000 Serial Port A User Enable Register SAUER 0x03CO W 00000000 Serial Port B User Enable Register SBUER Ox3DO W 00000000 Serial Port C User Enable Register SCUER 0 3 0 W 00000000 Serial Port D User Enable Register SDUER Ox3F0 W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port F User Enable Register SFUER Ox3D8 W 00000000 Enable Dual Mode Register EDMR 0x0420 R W 00000000 284 Rabbit 4000 Microprocessor User s Manual 27 2 Dependencies 27 2 1 Pins There no pin dependencies for the System User Mode 27 2 2 Clocks There are no clock dependencies for the System User Mode 27 2 3 Other Registers Any writes to the internal I O registers listed in Table 27 2 are ignored when the System User Mode is enabled and the processor is in the User Mode Table 27 2 I O Addresses Inaccessible in User Mode Register Name Mnemonic Address Global Control Status Register GCSR
243. lel Port A are clocked by the peripheral clock 8 2 3 Other Registers Register Function SPCR Used to set up Parallel Port A 8 2 4 Interrupts There are no interrupts associated with Parallel Port A 8 3 Operation The following steps explain how to set up Parallel Port A 1 Select the desired mode using SPCR 2 If the slave port or auxiliary I O bus is selected refer to the chapters for those peripher als for further setup Once Parallel Port A is set up data can be read or written by accessing PADR Note that Parallel Port A is not available for general purpose I O while the slave port or the auxiliary bus is selected Selecting these options for Parallel Port A affects Parallel Port because Parallel Port B is then used for address and control signals 74 Rabbit 4000 Microprocessor User s Manual 8 4 Register Descriptions Parallel Port A Data Register PADR Address 0x0030 Bit s Value Description 7 0 Read The current state of Parallel Port A pins PA7 PAO is reported Write The Parallel Port A buffer is written with this value for transfer to the Parallel Port A output register on the next rising edge of the peripheral clock Slave Port Control Register SPCR Address 0x0024 Bit s Value Description 7 0 Program fetch as a function of the SMODE pins 1 Ignore the SMODE pins program fetch function 6 5 read
244. lf timed chip selects for read and write 010 170 ns self timed chip selects for read and write 011 110 ns self timed chip selects for read and write 100 290 ns self timed chip selects for read only 101 230 ns self timed chip selects for read only 110 170 ns self timed chip selects for read only 111 110 ns self timed chip selects for read only 4 0 Normal chip select timing for read cycles 1 Short chip select timing for read cycles not available in full speed 3 0 Normal chip select timing for write cycles 1 Short chip select timing for write cycles not available in full speed 2 0 000 The 32 kHz clock divider is disabled 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 32 kHz clock divided by 2 16 384 kHz 101 32 kHz clock divided by 4 8 192 kHz 110 32 kHz clock divided by 8 4 096 kHz 111 32 kHz clock divided by 16 2 048 kHz Chapter 26 Low Power Operation 281 Global Clock Double Register GCDR Address 0x000F Bit s Value Description 7 5 These bits reserved and should be written with zeros 4 0 00000 clock doubler circuit is disabled 00001 6 ns nominal low time 00010 7 ns nominal low time 00011 8 ns nominal low time 00100 9 ns nominal low time 00101 10 ns nominal low time 00110 11 ns nominal low time
245. ll not be asserted with this option Any aligned word writes are recognized internally and are combined into just one write transaction on the external bus Internally the two writes still occur The RAM option for the 16 bit bus does not inhibit byte writes or unaligned word writes and replicates the byte data on both halves of the data bus in these cases In this mode the AO and AO signals must be used by the memory to enable the individual bytes Table 5 3 0 0 Signals for Various Transaction Types Transaction Type AO A0 Word Read prefetch only Low Low Word Write Low Low Byte Read or Write Even Address Low High Byte Read or Write Odd Address High Low of the power saving modes in Chapter 26 can still be used with the 16 bit mode Because it is anticipated that the 16 bit memory may be slower than the normal 8 bit memories separate wait state controls for the 16 bit bus are provided in separate registers ACSOCR and ACSICR The second advanced bus mode is the Page Mode This mode also can be enabled for either CSO or CS1 and can be used with either 8 bit or 16 bit memories connected to these chip selects Page mode memories provide for a faster access time if the requested data is in the same page as the previous data In the Rabbit 4000 and most memory devices a page is 16 bytes Thus if an address is identical to the previous address except in the lower four bits the access ti
246. llel Port E bit 0 alternate output 2 TIMER 11 Parallel Port E bit 0 alternate output 3 TCLKF 102 Rabbit 4000 Microprocessor User s Manual Parallel Port E Alternate High Register PEAHR Address 0x0073 Bit s Value Description 7 6 00 Parallel Port E bit 7 alternate output 0 17 01 Parallel Port E bit 7 alternate output 1 10 Parallel Port E bit 7 alternate output 2 PWM3 11 Parallel Port E bit 7 alternate output 3 SCLKC 5 4 00 Parallel Port E bit 6 alternate output 0 16 01 Parallel Port E bit 6 alternate output 1 no functionality 10 Parallel Port E bit 6 alternate output 2 PWM2 11 Parallel Port E bit 6 alternate output 3 TXE 3 2 00 Parallel Port E bit 5 alternate output O I5 01 Parallel Port E bit 5 alternate output 1 LINK 10 Parallel Port E bit 5 alternate output 2 PWM1 11 Parallel Port E bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port E bit 4 alternate output 0 14 01 Parallel Port E bit 4 alternate output 1 0 10 Parallel Port E bit 4 alternate output 2 PWMO 11 Parallel Port E bit 4 alternate output 3 TCLKE Parallel Port E Control Register PECR Address 0x0074 Bit s Value Description 7 6 These bits are ignored and should be written with zero 5 4 00 The upper nibble peripheral clock is CLK 2 01 The upper nibble peripheral clock is the output of Timer 1
247. m 40 to 85 C This corresponds to maximum clock frequencies of about 60 MHz commercial or industrial If the clock doubler or spectrum spreader is used these maximum ratings must be reduced as shown in Table 28 11 314 Rabbit 4000 Microprocessor User s Manual Table 28 11 Preliminary Maximum Clock Speeds Vpp 410 Temp 40 C to 85 C Industrial Ratings Duty Cycle Conditions Minimum Maximum Requirements Period Frequency ns ns MHz No Doubler or 17 58 8 Spreader Spreader Only 20 500 Normal Spreader Only 21 47 6 Strong Doubler 19 52 6 1 gt clock low 8 ns delay clock high 0 Doubler Only internal 50 20 50 low clock clock high gt 1 Spreader Normal with 4 gt clock low Doubler al FEN clock high gt 2 8 ns delay Spreader Normal with Doubler 8 ns 24 41 6 delay Internal 8 50 Clock Spreader 215 465 Strong Spreader Strong with Doubler 23 qu ecco as deltos clock high gt 6 When the doubler is used the duty cycle of the clock becomes a critical parameter The duty cycle should be measured at the separate clock output pin pin 2 The minimum period must be increased by any amount that the clock high time is greater or less than specified in the duty cycle requirement For example consider a design where the spreader and doubler are enabled with 8 ns nominal delay in the doubler The high and low cl
248. main clock divided by 4 111 Processor clock from the main clock divided by 6 Peripheral clock from the main clock divided by 6 1 0 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 20 Rabbit 4000 Microprocessor User s Manual Global Clock Modulator 0 Register GCMOR Address 0x000A Bit s Value Description Clock dither in 1 ns steps from 0 ns to 26 ns Do not modify while the dither 7 6 00 DP function is enabled 01 Clock dither in 0 5 ns steps from 0 ns to 13 ns 10 Clock dither in 2 ns steps from 0 ns to 52 ns 11 This bit combination is reserved and must not be used 5 0 These bits are reserved and should be written with zeros Global Clock Modulator 1 Register GCM1R Address 0x000B Bit s Value Description Disable the clock dither function Disable does not take effect until the dither 7 0 pattern has returned to the 0 ns base delay value 1 Enable the clock dither function 6 0 These bits are reserved and should be written with zeros Chapter 2 Clocks 21 Global Clock Double Register GCDR Address 0x000F Bit s Value Description 7 5 These bits reserved and should be written with zeros 4 0 00000 clock doubler circuit is disabled 00001 6 ns nominal low time
249. master or slave reads or writes any of the slave port registers The slave port interrupt vector is in the IIR at offset 0x080 It can be set as Priority 1 2 or 3 by writing to SPCR Chapter 18 Slave Port 163 18 3 Operation Figure 18 1 shows a typical slave port connection between a Rabbit processor as the master and two slaves MASTER Rabbit First SLAVE Rabbit 00 07 SRD Second SLAVE Rabbit JSLAVEATTN ISCS Figure 18 1 Master Slave Port Connections 164 Rabbit 4000 Microprocessor User s Manual These connections are summarized in Table 18 3 Table 18 3 Typical Slave Port Connections Master Slave 1 Slave 2 Data Bus D0 D7 SDO SD7 PAO PA7 SDO SD7 PAO PA7 Address Bus 0 1 SAO SAI 4 5 SAO SAI PB4 PB5 I O Read Strobe NORD SRD PB3 SRD PB3 Write Strobe IOWR SWR PB2 SWR PB2 Slave 1 Chip Select I O strobe 16 EDO Ines PEO Slave 2 Chip Select I O strobe I7 PD m m BBO External Interrupt 0 from Slave 1 PEO SLVATTN PB7 External Interrupt 1 from Slave 2 PEI SLVATTN PB7 Note that the slave port on the master Rabbit processor is not used the master uses the data bus to send and receive data to the slave port data registers on the slave devices In this setup pins PD6 and PD7 are set up as I O strobe chip selects for the two slave devices and PEO and 1 are used as external interrupt
250. me is assumed to be faster These wait state options are also controlled in the ACSOCR and ACSICR In Page Mode the chip select and OE remain active from one page access to the next and only the four least significant bits of the address change to request the new data This obviously interferes with a number of the power saving modes and will take precedence over them for CSO or CS1 accesses as appropriate The power saving modes will still apply to the other chip select and output enable signals The logic recognizes which OE is being used with each chip select in the Page Mode As mentioned previously the ACSOCR and ACSICR registers each contain three settings to control the generation of wait states in the advanced bus modes These settings are used in place of the wait state setting in MBxCR when an advanced bus mode is enabled When the 16 bit bus is enabled from one to seven automatic wait states for memory read bus cycles can be enabled This setting is also used for the first access when the Page Mode is enabled a second setting selects the number of wait states for all subsequent reads in the 50 Rabbit 4000 Microprocessor User s Manual Page Mode allowing from zero to three automatic wait states for the same page accesses in the Page Mode The third setting selects from five to nine automatic wait states for memory write bus cycles The choices available for the advanced bus wait states are suffi cient to allow interfacing to a
251. memory banks come up undefined and should be set via the appropriate MBxCR register to a valid setting before use The size of the memory banks can be defined in the MECR register The default size is 256KB the bank selection looks at address bits 18 and 19 but this value can be adjusted down to 128KB or up to 4MB per bank Chapter 5 Memory Management 47 The two address bits used to select the bank can be inverted MBxCR which enables mapping different sections of a memory device larger than the current memory bank into memory An example of this feature is shown in Figure 5 4 OxFFFFF 0xC0000 OxBFFFF 1MB 0x80000 Mamoy exzFFFF Device 0x40000 0 40000 Ox3FFFF 0x00000 0x00000 OxFFFFF 0xC0000 OxBFFFF Memory 0 80000 1 A18 normal Device 19 inverted 0x40000 Ox3FFFF 0x40000 Ox3FFFF Memory Bank 0 0x00000 0x00000 Figure 5 4 Mapping Different Sections of a Memory Device Larger Than the Current Memory Bank It is possible to extend the timing of the OE and or WE strobes by one half of a clock This provides slightly longer strobes for slower memories see the timing diagrams in Chapter 28 These options are available in MTCR It is possible to force CS1 to be always active in MMIDR enabling this will cause con flicts only if a device shares a OE or WE strobe with another device This option allows faster access to
252. ming error at start and one character garbage at completion 0 This bit is ignored in the asynchronous mode Chapter 17 Serial Ports 159 Serial Port x Extended Register SEER Address 0x00CD HDLC Mode Only SFER Address 0x00DD Bit s Value Description 7 5 000 NRZ data encoding for HDLC receiver and transmitter 010 NRZI data encoding for HDLC receiver and transmitter 100 Biphase level Manchester data encoding for HDLC receiver and transmitter 110 Biphase space data encoding for HDLC receiver and transmitter 111 Biphase mark data encoding for HDLC receiver and transmitter 4 0 Normal HDLC data encoding 1 Enable RZI coding 4 bit cell IrDA compliant This mode can only be used with an internal clock and NRZ data encoding 3 0 Idle line condition is flags 1 Idle line condition is all ones 2 0 Transmit flag on underrun 1 Transmit abort on underrun 1 0 Separate HDLC external receive and transmit clocks 1 Combined HDLC external and transmit clock from transmit clock pin 0 This bit is ignored in HDLC mode Serial Port x Divider Low Register SEDLR Address 0x00CE SFDLR Address 0x00DE Bit s Value Description 70 Eight LSBs of the divider that generates the serial clock for this channel This divider is not used unless the MSB of the corresponding SxDHR is set to one Serial Port x Divider High Register SE
253. mps back to the start of the ROM program and responds according to the current state In addition by writing to bit 7 of the Slave Port Control Register SPCR the processor can be told to ignore the state of the SMODE pins and continue normal operation Note that the processor can be told to reenter bootstrap mode at any time by setting bit 7 of SPCR low once this occurs and the least significant four bits of the current PC address are zero the processor will sample the state of the SMODE pins and respond accordingly This feature allows in line downloading from the selected bootstrap port once the down load is complete bit 7 of SPCR can be set high and the processor will continue operating from where it left off As a security feature any attempt to enter bootstrap mode from either the SMODE pins or by writing to bit 7 of SPCR will erase the data stored in the onchip encryption RAM This prevents loading a small program in memory to read out the data 28 Rabbit 4000 Microprocessor User s Manual 3 4 Register Descriptions Slave Port Control Register SPCR Address 0x0024 Bit s Value Description 7 0 Program fetch as a function of the SMODE pins 1 Ignore the SMODE pins program fetch function 6 5 Read These bits report the state of the SMODE pins Write These bits are ignored and should be written with zero 4 2 000 Disable the slave port Parallel Port A is a byte wide inp
254. n below D 7 0 2 ICSx IoEx Operation at 2 kHz 276 Rabbit 4000 Microprocessor User s Manual 23 0 D 7 0 4 R ICSx d 1 ir Operation at 4 kHz AI23 0 _ i 0 ICSx Operation at 8 kHz Chapter 26 Low Power Operation 277 A 23 0 bp ICSx Operation at 16 kHz X im X o 3 ICSx Operation at 32 kHz 278 Rabbit 4000 Microprocessor User s Manual 26 2 4 Self Timed Chip Selects Self timed chip selects can be enabled via GPSCR to reduce power consumption even more when running off the 32kHz oscillator When self timed chip selects are enabled the chip select is only active for a short selectable period of time A sample read and write timing diagram is shown below 100 lt Chapter 26 Low Power Operation 279 26 3 Register Descriptions Global Control Status Register GCSR Address 0x0000 Bit s Value Description 7 6 00 No reset or watchdog timer timeout since the last read rd only 01 watchdog timer timed out These bits are cleared by a read of this register 10 This bit combination is not possible 11 Reset occurred These bits are cleared by a read of this register 5 0 No effect on the periodic interru
255. n input or an output port Parallel Port A is also used as the data bus for the slave port and auxiliary I O bus The Slave Port Control Register SPCR is used to configure how Parallel Port A is used Parallel Port A is an input at startup or reset If the SMODE pins have selected the slave port bootstrap mode Parallel Port A will be the slave port data bus until disabled by the processor Parallel Port A can also be used as an external I O data bus to isolate external I O from the main data bus Table 8 1 Parallel Port A Pin Alternate Output Functions Slave Port Auxiliary I O fat SII Data Bus Bus PA 7 0 SD 7 0 ID 7 0 8 1 1 Block Diagram Parallel Port A 7 0 ees PADR Slave Data External I O Data 8 1 2 Registers Register I O Address R W Reset Port A Data Register PADR 0x0030 R W XXXXXXXX Chapter 8 Parallel Port A 73 8 2 Dependencies 8 2 1 I O Pins Parallel Port A uses pins PAO through PA7 These pins can be used as follows e General purpose 8 bit data input write 0x080 to SPCR e General purpose 8 bit data output write 0x084 to SPCR e Slave port data bus write 0 088 to SPCR e Data bus of the auxiliary I O bus write 0 08 to SPCR All Parallel Port A bits are inputs at startup or reset See the associated peripheral chapters for details on how they use Parallel Port A 8 2 2 Clocks Any outputs on Paral
256. n pins PC7 PD7 or PE7 If the HDLC mode is enabled the transmit serial clock is either trans mitted or received on PC4 PD4 or PE4 while the receive serial clock is either transmitted or received on 5 PDS or PES Serial Port F can transmit on parallel port pins PC2 PD2 or PE2 and can receive on pins PC3 PD3 or PE3 If the HDLC mode is enabled the transmit serial clock is either trans mitted or received on PCO PDO or PEO while the receive serial clock is either transmitted or received on PD1 or PEL Table 17 1 Serial Ports E and F Pin Usage Function Serial Port E Serial Port F Transmit PC6 PD6 PE6 PC2 PD2 PE2 Receive PC7 PD7 PE7 PC3 PD3 PE3 Transmit Clock PC4 PD4 PE4 PCO PDO PEO Receive Clock 5 PD5 PES PD1 PEI 17 2 2 Clocks The data clocks for Serial Ports E F are based on the peripheral clock and divided by either a Timer A divider or a dedicated 15 bit divider In either case the overall clock divider will be the value in the appropriate register plus one 17 2 3 Other Registers Register Function TAT2R Time constant for Serial Port E TAT3R Time constant for Serial Port F PCFR PCAHR PCALR PDFR PDAHR PDALR PEFR PEAHR PEALR Alternate port output selection 148 Rabbit 4000 Microprocessor User s Manual 17 2 4 Interrupts In the asynchronous mode a serial port interrupt can be generated whenever
257. nded write the data to SxAR instead of SxDR to append a long stop 0 bit write to SxLR instead Chapter 16 Serial Ports D 135 16 3 2 Clocked Serial Mode The following steps explain how to set up Serial Ports A D for the clocked serial mode When the internal clock is selected the Rabbit 4000 is in control of all transmit and receive operations When an external clock is selected the other device controls all trans mit and receive operation For both situations the decision between polling and interrupt driven methods is application dependent 1 2 Write the interrupt vector for the interrupt service routine to the internal interrupt table Set up the desired data transmit and clock pins by writing to the appropriate parallel port function register PxER and alternate output register PxALR or PxAHR Select the appropriate mode by writing to SxCR receive input port and clock source Also select the interrupt priority Select additional options by writing to SxER clock polarity bit order and clock source if external Write the desired divider value to TATXR for the appropriate serial port or else write a divider to the dedicated 15 bit divider in SxDLR and SxDHR If the dedicated divider is to be used write a 1 to the most significant bit of SxDHR to enable it There are two methods to transfer a byte write the byte to SxDR and then write 10 or 11 to bits 6 7 of SxCR to enable the tr
258. ndition of the line can be flags or all ones Chapter 17 Serial Ports E F 145 Several types of data encoding are available in HDLC mode NRZ NRZI biphase level Manchester biphase space and biphase mark IrDA compliant RZI encoding is also available in HDLC mode it reduces the bit widths to 1 4 the normal width which allows the serial port signal to be connected directly to an IrDA transceiver If an internal clock is selected the serial port data clocks can be generated from the appro priate 8 bit timer Timer A2 for Serial Port E and Timer A3 for Serial Port F or from a dedicated 15 bit divider In HDLC mode the byte data rate is equal to the data clock rate divided by 16 When using an external clock a 1x same speed as the data rate clock is supported In this case the maximum data rate is 1 6 of the peripheral clock rate The receive clock is gener ated from the transitions in the data stream via a digital phase locked loop DPLL The timing of this synchronization is adjusted with each incoming transition allowing for track ing if the two external clocks differ slightly in frequency For more on the clock synchro nization and data encoding see Section 17 3 3 17 1 1 Block Diagram Serial Ports E F SxDHR Peripheral 15 bit Serial Port Clock Divider Serial Data Control SxDHR Clock SxCR SxDLR SxER Timer Ax Output Rx Buffer Latched 4 bytes Rx Buffer SxDR SxAR
259. ndshake for I O Bank 7 6 0 Disable I O handshake for I O Bank 6 1 Enable I O handshake for I O Bank 6 5 0 Disable I O handshake for I O Bank 5 1 Enable I O handshake for I O Bank 5 4 0 Disable I O handshake for I O Bank 4 1 Enable I O handshake for I O Bank 4 3 0 Disable I O handshake for I O Bank 3 1 Enable I O handshake for I O Bank 3 2 0 Disable I O handshake for I O Bank 2 1 Enable I O handshake for I O Bank 2 1 0 Disable I O handshake for I O Bank 1 1 Enable I O handshake for I O Bank 1 0 0 Disable I O handshake for I O Bank 0 1 Enable I O handshake for I O Bank 0 Handshake Timeout Register IHTR Address 0x002A Bit s Value Description 7 0 No I O handshake timeout has occurred since the last read of this register An I O handshake timeout has occured since the last read of this register This bit is cleared by a read of this register 6 This bit is reserved and should be written with zero Time constant for the I O handshake timeout counter This time constant times 32 selects the number of clocks that the I O handshake input may delay completion of an I O transaction before the I O transaction will complete automatically 5 0 254 Rabbit 4000 Microprocessor User s Manual Bank x Control Register IBOCR Address 0x0080 IB1CR Address 0 0081 2 Address 0x0082 Address 0x0083
260. ng steps explain how to set up a Timer countdown timer 1 Select perclk 2 perclk 16 or countdown timer Al in TBCR 2 Use TBCR to select whether countdown timers 1 2 operate normally with the match registers or whether they use the step registers to calculate match values 3 Enable Timer by writing a 1 to bit 0 of TBCSR 14 3 1 Handling Interrupts The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure TBCSR to select which match registers will generate an interrupt 3 Configure TBCR to select the interrupt priority note that interrupts will be enabled once this value is set this step should be done last The interrupt request is cleared by reading from TBCSR 14 3 2 Example ISR A sample interrupt handler is shown below timerB isr push af save used registers ioi 14 TBCSR clear the interrupt request and get status handle all interrupts flagged in TBCSR here reload match register s if necessary pop af restore used registers ipres ret Chapter 14 Timer 117 14 4 Register Descriptions Timer B Control Status Register TBCSR Address 0 00 0 Bit s Value Description 7 3 These bits always read as zero 2 1 0 The corresponding Timer B comparator has not encountered a match condi
261. nnels 240 multicast addressing 208 parallel Port 24422224 87 interrupts 239 242 243 206 alternate input functions 88 example ISR 243 transmit sss 206 alternate output functions 87 operation 243 OVerVieW 201 block diagram 89 239 240 TeCeiver 202 CLOCKS i i as 90 OVETVIEW 239 register descriptions 210 dependencies 90 register descriptions 244 registers 204 Interrupts eee 91 ii bus 241 Setup 206 Operation 91 spreading function 240 transmitter 201 OVerVieW 22222222 87 PDDR setup 87 Q register descriptions 22 quadrature decoder 231 onchip Ethernet TEQISLETS 90 block diagram 233 See Network Port A Parallel Port E 97 Code d unen 232 234 opcodes alternate input functions 98 counter operation 231 System User mode 290 alternate output functions 97 dependencies 234 block diagram 99 IMPULS 231 100 oe 232 234 235 Parallel Port
262. no collisions 1 Frame transmission encountered at least one collision 0 0 Frame transmission encountered no late collisions later than one slot time 1 Frame transmission encountered a late collision later than one slot time Network Port A Receive Status Register NARSR Address 0x0203 Bit s Value Description 7 4 0000 Receiver is disabled or has not yet received a frame after being enabled Oxxl Frame discarded because of FIFO overrun during reception The missed frame counter is incremented by each frame discarded because of a FIFO overrun Frame discarded because of alignment error The alignment error counter is 0 1 incremented by each frame discarded because of an alignment error 01 Frame discarded because of CRC error The CRC error counter is incremented by each frame discarded because of a CRC error Frame received without error If the receiver is in monitor mode the missed 1000 Gu frame counter is incremented with each frame received without error other All other bit combinations not listed are illegal and will never occur 3 2 00 These bits are reserved and will always return zeros 1 0 00 Received frame had a physical address match 01 Received frame did not have an address match promiscuous mode 10 Received frame had a multicast address match 11 Received frame had a broadcast address match Chapter 20 10Base T Ethernet 211 Netw
263. nsfers to or from a number of internal I O addresses are controlled by transfer request signals These transfer request signals are connected automatically as a function of the internal I O address loaded into the DMA channel Note that if both the source and the destination are internal I O the source transfer request is used by the DMA channel The DMA channels are inherently byte oriented so while DMA transfers can be done from a 16 bit memory DMA transfers to a 16 bit memory can only be done if the 16 bit memory is set up to allow byte writes See Chapter 5 for more information There are two inputs available for requests linked to external I O devices These two exter nal requests may be assigned to any DMA channel These requests may also be used by a channel that has an internal I O as a destination In this case the external request acts as a flow control signal for the DMA transfers because the external request is ANDed with the automatically connected internal request To facilitate periodic DMA transfers there is also an internal timed request This request is generated from a programmable 16 bit counter and may be assigned to any DMA channel As in the case of the external requests this request is ANDed with any internal or exter nal request that is also assigned to that DMA channel This periodic request can be pro grammed to transfer one byte or an entire buffer The single byte option is useful for driving an out
264. nsmit FIFO 4 0 No operation 1 Purge the network port receive FIFO 3 0 These bits are ignored and should always be written as zeros Chapter 20 10Base T Ethernet 213 Network Port Control Register NACR Address 0 0207 Bit s Value Description 7 6 00 Disable the network port clock 01 Network port clock from Parallel Port E6 10 Network port clock from system clock 11 Network port clock from system clock divided by 2 5 4 These bits unused and should be written with zero 3 0 Normal operation 1 Restart auto negotiation process 2 0 Disable auto negotiation function 1 Enable auto negotiation function 1 0 Force half duplex operation If auto negotiation is enabled only half duplex operation will be advertised Enable full duplex operation If auto negotiation is disabled this forces full 1 duplex operation If auto negotiation is enabled this allows advertising full duplex capability 0 This bit is unused and should be written with zero 214 Rabbit 4000 Microprocessor User s Manual Network Port Pin Conirol Register NAPCR Address 0x0208 network port clock enabled in NACR Bit s Value Description T5 000 RXD and RXD normal operation differential inputs 010 RXD singled ended true input RXD is the valid signal qualifier active
265. nt the buffer descriptor is only 12 bytes long A memory address for either source or destination causes the DMA channel to fetch three bytes from the corresponding field in the buffer descriptor An internal I O or exter nal I O address for either source or destination causes the DMA channel to fetch two bytes from the corresponding field in the buffer descriptor DMA memory addresses are always physical addresses and are never translated by the MMU All DMA memory addresses use the memory control signals wait states and flipped bits as selected in the Master Memory Bank Control registers All DMA external addresses use the I O control signals and wait states as selected in the external I O registers The first byte in the first buffer descriptor the byte pointed to by the initial address is reserved for status information when transferring data from an internal serial or network device This automatic status transfer means that the processor does not need to service any interrupts from a serial or network receiver except in the case of an error condition When transferring data to an internal HDLC serial or network transmitter the last byte of the last buffer will automatically be written to a special destination address to tag the data as the last in the frame without processor intervention However this function is not available in the case where the buffer contains only one byte of data If this case should occur the buffer descrip
266. nted to by the PWBPR The PWBPR is automatically updated to the next PWM register address in the sequence PWM Block Pointer Register PWBPR Address 0 00 9 Bit s Value Description 7 3 These bits are ignored and should be written with zero 2 0 Three least significant bits of the PWM register address for indirect access Chapter 23 Pulse Width Modulator 245 246 Rabbit 4000 Microprocessor User s Manual 24 EXTERNAL I O CONTROL 24 1 Overview The Rabbit 4000 s external I O space consists of 64KB that is accessed by prefixing a read or write instruction with the IOE instruction These accesses can go onto the memory bus or onto the external I O bus described below There are three dedicated signal pins IORD IOWR BUFEN that toggle for all external I O accesses and eight I O strobes that can be associated with this external I O space and directed out of Parallel Ports C D or E In addition a handshaking signal input can be enabled on a Parallel Port E pin and used to pause an external I O transaction until the external device is ready to complete the transac tion A timeout period can be defined to ensure that the processor is not held indefinitely by a misbehaving external device 24 1 1 Auxiliary Bus The Rabbit 4000 can enable a separate auxiliary I O bus for external devices to keep bus loading on the memory bus at an acceptable level This bus consists of eight data lines on Parallel Por
267. nterrupt request is also cleared by register write above pop af restore used registers ipres ret Chapter 23 Pulse Width Modulator 243 23 4 Register Descriptions PWM LSB 0 Register PWLOR Address 0x0088 Bit s Value Description 7 6 Least significant two bits for the Pulse Width Modulator count 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 This bit is ignored and should be written with zero 2 1 00 Pulse Width Modulator interrupts are disabled 01 Pulse Width Modulator interrupts use Interrupt Priority 1 10 Pulse Width Modulator interrupts use Interrupt Priority 2 11 Pulse Width Modulator interrupts use Interrupt Priority 3 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle PWM LSB 1 Register PWL1R Address 0x008A Bit s Value Description 7 6 Least significant two bits for the Pulse Width Modulator count 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 This bit is ignored and should be written with zero 2 1 00 Normal PWM
268. nual 2 3 2 Spectrum Spreader When enabled the spectrum spreader stretches and compresses the main clock in a complex pattern that spreads the energy of the clock harmonics over a wider range of frequencies 0 JA EE PER OI Spectrum Spreader oer detto a ee 4 30 Hj 50 400 Disabled Spectrum Spreader Enabled normal setting 405 410 mm i 415 420 425 FREQUENCY MHz Figure 2 1 Effects of Spectrum Spreader 440 There three settings that correspond to normal and strong spreading in the 0 50 MHz and gt 50 MHz main clock range Each setting will affect the clock cycle differently the maximum cycle shortening at 1 8 V and 25 C is shown in Table 2 2 below Table 2 2 Spectrum Spreader Settings 0 50 MHz gt 50MHz CCMOR Description Max Cycle Value Shortening Normal spreading of frequencies over Normal 0x40 50 MHz 2 3 ns Normal spreading of frequencies up to Normal Strong 0x00 50 MHz strong spreading of 3 ns frequencies over 50 MHz Strong spreading of frequencies up to Strong 0 80 50 MHz normal spreading of 4 5 ns frequencies over 50 MHz Chapter 2 Clocks 13 The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi mum of 3 ns for the normal spreading and up to 5 ns for the strong spreading If the
269. nversion 20 5 Register Descriptions Network Port A Data Register NADR Address 0x0200 Bit s Value Description 7 0 Read Returns the contents of the receive buffer This register is not normally accessed by the processor but is accessed by the DMA channels Write Loads the transmit buffer with a data byte for transmission Network Port A Last Data Register NALDR Address 0x0201 Bit s Value Description 70 Read Returns the contents of the receive buffer This register is not normally accessed by the processor but is accessed by the DMA Loads the transmit buffer with the last data byte of a frame to enable the Write subsequent transmission of the CRC The DMA automatically writes the last byte of the frame to this address 210 Rabbit 4000 Microprocessor User s Manual Network Port A Transmit Status Register NATSR Address 0x0202 Bit s Value Description 7 4 0000 Transmitter is disabled or has not yet sent frame after being enabled Oxx1 Frame transmission aborted because of a FIFO underrun Ox1x Frame transmission aborted because of excessive collisions 16 01 Transmitter is deferring frame transmission 1000 Frame transmitted without error other All other bit combinations not listed are illegal and will never occur 3 2 00 These bits are reserved and will always return zeros 1 0 Frame transmission encountered
270. o protected segment causes Priority 3 WPCR write protection in User mode only write protection violation interrupt Difficult to enter system mode requires Easy to enter user mode SETUSR instruction interrupt SYSCALL or RST instruction The main intent of the System User Mode is to protect critical code for example code that performs remote firmware updates data and the current processor state memory setup peripheral control etc from inadvertent changes by the user s standard code By removing access to the processor s I O registers and preventing memory writes to critical regions the user s code can run without the danger of locking up the processor to the point where it cannot be restarted remotely and or new code uploaded Chapter 27 System User Mode 283 27 1 1 Registers Register Name Mnemonic Address R W Reset Enable Dual Mode Register EDMR 0x0420 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Parallel Port A User Enable Register PAUER 0x0330 W 00000000 Parallel Port B User Enable Register PBUER 0x0340 W 00000000 Parallel Port C User Enable Register PCUER 0x0350 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x0370 W 00000000 Input Capture User Enab
271. o this Chapter 3 Reset and Bootstrap 27 e If either of the SMODE pins is high the processor will enter the bootstrap mode accept triplets from either Serial Port A or the slave port It is good practice to place pulldown resistors on the SMODE pins to ensure proper operation of your design Table 3 2 SMODE Pin Settings SMODE Pins 1 0 Operation 00 No bootstrap code is fetched from address 0x0000 on 50 OEO 01 Bootstrap from the slave port 10 Bootstrap from Serial Port A clocked mode 11 Bootstrap from Serial Port A asynchronous mode In bootstrap mode the processor inhibits the normal memory fetch from CSO and instead fetches instructions from a small internal boot ROM This program reads triplets of three bytes from the selected peripheral The first byte is the most significant byte of a 16 bit address the second byte is the least significant byte of the address and the third byte is the data to be written If the uppermost bit of the address is 1 then the address is assumed to be an internal register address instead of a memory address and the data are written to the appropriate register instead The boot ROM program waits for data to be available each byte received automatically resets the watchdog timer with a 2 second timeout Bytes must be received quickly enough to prevent timeout or the watchdog must be disabled The device checks the state of the SMODE pins each time it ju
272. oard land pattern for the Rabbit 4000 chip in 128 LQFP package This land pattern is based on the IPC SM 782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pat tern Standard IPC Northbrook IL 1999 16 85 mm max 13 75 mm min 15 3 mm 0 28 mm max lt 13 75 16 85 1 55 Y 124 mm 15 3 mm TOLERANCE AND SOLDER JOINT ANALYSIS J4 0 29 0 55 mm e max 16 85 mm gt gt Toe Fillet Lmin 2 Jy 0 29 0 604 mm Gmin 13 75 mm Heel Fillet Jg 0 01 0 077 mm X 0 28 mm max Side Fillet J Solder fillet min max toe heel and side respectively L Toe to toe distance across chip S Heel to heel distance across chip T Toe to h eel distance on pin W Width of pin Figure 29 3 PC Board Land Pattern for Rabbit 4000 128 pin LQFP Chapter 29 Package Specifications and Pinout 323 29 2 Ball Grid Array Package 29 2 1 Pinout 0202 Ot Of Of ORO OF O8 O amp O Of O8 O8 _ o Oz OF Of Oz Of OF OP OF O O8 O2 Of OF OF
273. oces sor is running at 3 3 V normally A circuit to switch between a 1 8 2 0 V battery and the main power can use the RESOUT pin to switch the power source for the VBATIO pin R is a current limiting resistor that should be adjusted for the battery voltage a good value to use for a 3 0 V battery is 150 kQ 3 3 Main Power t FDV302P p channel Rabbit 4000 RESOUT gt VBATIO Figure 28 7 Switching Circuit for VATIO Pin Table 28 12 shows the typical current consumption for these pins while the remainder of the Rabbit 4000 is powered down Table 28 12 Typical Battery Backed Current Consumption 40 C to 85 C Pin Voltage Current VBAT 18 1 7 uA VBATIO 1 8 V 0 1 Chapter 28 Specifications 319 320 Rabbit 4000 Microprocessor User s Manual 29 PACKAGE SPECIFICATIONS AND PINOUT 29 1 LQFP Package 29 1 1 Pinout 04441241492 oou 9 aE gt bl l l l gt gt aodaanaonananaxsxs soo raonaoaoaaaaa gt a a a a vonom S 58838888 22z222222 28858889898 6598989 5Ab vssio 2 O 95 A19 ICS2 13 94 OE1 STA
274. ock are equal to within 1 ns This violates the duty cycle requirement by 3 ns since clock low clock high can be as small as 1 ns but the requirement is that it not be less than 2 ns Thus 3 ns must be added to the minimum period of 21 ns giving a minimum period of 24 ns and a maximum frequency of 41 6 MHz commercial Chapter 28 Specifications 315 Since the built in high speed oscillator buffer generates a clock that is very close to having a 50 duty cycle to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty cycle adjustment by changing the resistance of the power and ground connections as shown below Adjust the values of these resistors to XTALA1 varv the dutv cvcle Figure 28 4 External Oscillator Buffer 316 Rabbit 4000 Microprocessor User s Manual 28 5 Power and Current Consumption Various mechanisms contribute to the current consumption of the Rabbit 4000 processor while it is operating including current that is proportional to the voltage alone leakage current and dependent on both voltage and frequency switching and crossover current To reduce current consumption the clock can be divided down in one of the sleepy modes see Table 26 1 for more details Figure 28 5 shows a typical current draw as a function of the main clock frequency The values shown do not include any current consumed by external oscillators or memory It is a
275. ode write address match 11 Breakpoint x on System or User Mode write address match 1 0 These bits are reserved and should be written with zeros 268 Rabbit 4000 Microprocessor User s Manual Breakpoint x Address 0 Register BOAOR Address 0x030C B1A0R Address 0x031C B2A0R Address 0x032C B3A0R Address 0x033C B4A0R Address 0x034C B5A0R Address 0x036C 6 Address 0x037C Bit s Value Description 7 0 Breakpoint x Address 7 0 Breakpoint x Address 1 Register BOA1R Address 0x030D B1A1R Address 0x031D B2A1R Address 0x032D B3A1R Address 0x033D B4A1R Address 0x034D B5A1R Address 0x036D B6A1R Address 0x037D Bit s Value Description 7 0 Breakpoint x Address 15 8 Breakpoint x Address 2 Register BOA2R Address 0x030E B1A2R Address 0x031E B2A2R Address 0x032E B3A2R Address 0x033E B4A2R Address 0x034E B5A2R Address 0x036E B6A2R Address 0x037E Bit s Value Description 7 0 Breakpoint x Address 23 16 Chapter 25 Breakpoints 269 Breakpoint x Mask 0 Register BOMOR Address 0x0308 B1MOR Address 0x0318 B2MOR Address 0x0328 B3MOR Address 0x0338 BAMOR Address 0x0348 B5MOR Address 0x0368 6 Address 0x0378 Bit s Value Description Breakpoint x Mask 7 0 A one in a bit position
276. of a transmitted byte is sent out Each serial port has a separate interrupt vector that will be requested whenever the transmit buffer is emptied or the receive buffer contains a full byte four common SPI clock modes are supported and the bit order of the data may be either MSB or LSB first The transmit and receive operations are under program control as well Chapter 16 Serial Ports D 129 eik modeoo LT O LU LW II CLK Mode 01 Rx bit reversed ERCHERCHERER ERES Figure 16 1 Serial Ports A D Operation in Clocked Serial Mode In the asynchronous mode IrDA compliant RZI encoding can be enabled to reduce the bit widths to 3 16 the normal width 1 8 the normal width if the serial data clock 1s 8x instead of 16x which allows the serial port signal to be connected directly to an IrDA transceiver It is possible to select the same pin on Parallel Port C for both transmit and receive opera tion This allows glueless support for bidirectional serial protocols It is possible to synchronize a clocked serial trans fer to the match registers of Timer B to generate Table 16 1 Timer A Data Clocks precisely timed transmissions Serial Port Data Clock The serial port data clocks can be generated from the appropriate 8 bit timer from Timer A shown in Table 16 1 or from a dedicated 1 15 bit divider B In either case the resulting byte data rate in the C Timer A6 D A Timer A4 Timer A5
277. ol Register 58 Data Segment High Register EE 54 Data Segment Low Register fepe ie 54 Data Segment Register 54 Memory Alternate Control Register 57 Memory Bank x Control Register 55 Memory Timing Control Register 56 MMU Expanded Code Register 56 MMU Instruction Data Register 53 RAM Segment Register 58 Segment Size Register 55 Stack High Limit Register 63 Stack Limit Control Register 62 Stack Low Limit Register 62 Stack Segment High Register 54 Stack Segment Low Register 54 Stack Segment Register 53 Write Protect Segment x High Register 62 registers memory management d Write Protect Segment x Low Register 61 Write Protect Segment x Register 61 Write Protect x Register 60 Write Protection Control Register 59 Network Port 204 Network Port A Alignment Error Register 218 Network Port A Checksum 0 Register 218 Network Port A Checksum 1 Register 218 Network Port A Collision Detect Register 217 Network Port A Control Register 214 Network Port A Control Status Register 212 Network Port A CRC
278. ommended that the Rabbit 4000 be performing a tight polling loop waiting for a wakeup event 26 2 3 Short Chip Selects When running at a reduced clock speed it is likely that the chip selects for external devices will not need to be active for an entire clock cycle By reducing the width of the chip select the power consumption of the memory chip can be reduced without having any affect on the processor itself For reduced processor speeds based on the main oscillator a short chip select can be enabled in GPSCR this feature is not available when the processor is running at full speed This feature can be enabled separately for both reads and writes When enabled the chip select signals will be the width of two undivided clocks and located at the end of the transaction The read data in the figures below is sampled by the rising edge of CLKI that terminated the T2 cycle Wait states are inserted between T1 and T2 so they do not affect the width of the strobe Divide by 8 Mode 274 Rabbit 4000 Microprocessor User s Manual Divide by 6 Mode Divide by 4 Mode Chapter 26 Low Power Operation 275 Divide by 2 Mode When the processor is running off the 32 kHz clock the short chip select option will pro duce chip select signal that is the width of a single 32 kHz clock 30 5 microseconds oth erwise the timing is identical to the short chip select options based off the main oscillator Read strobe figures are show
279. on interrupt occurs whenever the IDET instruction is executed while the System User mode is enabled and the processor is in the User Mode Its purpose is to trap when system code is being executed while the processor is in the User Mode The System Mode Violation interrupt vector is in the IIR at offset 0 180 It always occurs at Priority 3 Note that Priority 3 is not available while the System User Mode is enabled and the pro cessor is in the User Mode If the processor is placed into Priority 3 either by an instruc tion or an interrupt it will respond as if it was set to Priority 2 When the System User Mode is enabled it is critical to handle the SU stack in interrupts as well as the IP stack always perform a SURES before the IPRES at the end of the interrupt 286 Rabbit 4000 Microprocessor User s Manual 27 3 System User Mode is designed to work with the memory and stack protection features of the Rabbit 4000 processor to provide a seamless framework for protection of critical code However there are many levels at which the System User Mode can be used some examples are described here 27 3 1 Memory Protection Only At the beginning of the user program all necessary peripherals are enabled all peripheral interrupts to be used are set up for the User Mode critical memory regions are protected stack limits are set and the various system memory stack violation interrupts are enabled The processo
280. on the next rising edge of the peripheral clock Parallel Port E Bit 1 Register PEB1R Address 0x0079 Bit s Value Description 7 2 0 These bits are ignored The port buffer bit 1 is written with the value of this bit The port buffer will be 1 Write transferred to the port output register on the next rising edge of the peripheral clock 104 Rabbit 4000 Microprocessor User s Manual Parallel Port Bit 2 Register PEB2R Address 0x007A Bit s Value Description 7 3 1 0 These bits ignored The port buffer bit 2 is written with the value of this bit The port buffer will be 2 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 3 Register Address 0x007B Bit s Value Description 7 4 2 0 These bits are ignored The port buffer bit 3 is written with the value of this bit The port buffer will be 3 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 4 Register PEB4R Address 0x007C Bit s Value Description 7 5 3 0 These bits are ignored The port buffer bit 4 is written with the value of this bit The port buffer will be 4 Write transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 5 R
281. onized with the external clock which is available on the CLK pin The delay in signal output depends on the capacitive load on the output lines In the case of the address lines which are critically important for establishing memory access time requirements the capacitive loading is usually in the range of 25 100 pF and the load is due to the input capacitance of the memory devices and PC trace capacitance Delays are expressed from the waveform midpoint in keeping with the convention used by memory manufacturers Table 28 9 lists the delays in gross memory access time for several values of VDDjo Table 28 9 Preliminary Data and Clock Delays Vpp 10 Temp 40 C to 85 Clock to Address Worst Case SUE Output Delay Data Setup Spectrum Spreader Delay m ns Time Delay ns 30 pF 60 pF 90 pF ns 0 5 ns setting 1 ns setting 2 ns setting p p p no dbl dbl no dbl dbl no dbl 3 3 6 8 11 1 2 3 2 3 3 4 5 4 5 9 1 8 18 24 33 3 7 6 5 8 12 11 22 When the spectrum spreader is enabled with the clock doubler every other clock cycle is shortened or lengthened by a maximum amount given in the table above The shortening takes place by shortening the high part of the clock If the doubler is not enabled then every clock is shortened during the low part of the clock period The maximum shortening for a pair of clocks combined is shown in the table The gross memory access time is 2T where T is
282. or PxAHR 3 Select the appropriate mode by writing to SxCR receive input port and clock source Also select the interrupt priority 4 Select additional options by writing to SxER data encoding idle line condition under run behavior and combined or separate clocks 5 Write the desired divider value to for the appropriate serial port or else write a divider to the dedicated 15 bit divider in SxDLR and SxDHR If the dedicated divider is to be used write a to the most significant bit of SxDHR to enable it In either case the overall clock divider will be the value in the appropriate register plus one 6 To start transmission of a packet write the first byte to SxDR If internal clock is selected the transmission will begin immediately if an external clock is selected the transmission will begin when the clock is detected 7 Continue writing bytes when space is available in the transmit buffer until the final byte of the packet If a CRC is to be appended to the packet write the final byte to SxAR If no CRC is required write the final byte to SxLR and just a closing flag will be appended If it is desirable to abort the current packet write 11 to bits 6 7 of SxCR and an abort pattern will be transmitted 8 The receiver will be synchronized on flag bytes and will reset the CRC By monitoring the received bytes decisions can be made about the incoming packet if it is not desired 1 it is not addressed to th
283. ork Port Control Status Register NACSR Address 0x0204 Bit s Value Description 7 2 0 The corresponding interrupt is disabled Write NC only 1 The corresponding interrupt is enabled These bits and the network port interrupt are automatically cleared by a read of li read this register The individual interrupt enables not affected 7 0 No frame received Read 1 Frame received error free only 6 0 No error on received frame Read 1 Frame received with error either CRC error alignment error or FIFO overflow only Frames received with error are discarded and memory buffer space is reclaimed 5 0 Frame transmission not complete 1 Frame transmitted without error only 4 0 No error on frame transmission Read 1 Frame transmission aborted because of error either excessive collisions FIFO only underrun or jabber condition The memory buffer space is not reclaimed 3 0 None of the error counters have overflowed Read 1 or more of the error counters have overflowed The overflow condition is only flagged when one or more of the error counters reaches 080h 2 0 No link failure or jabber condition Read 5 a only 1 Either link status change or jabber condition has been detected 1 0 00 The Network Port interrupt is disabled 01 Network Port uses Interrupt Priority 1 10 The Network Port uses Inte
284. ory It is assumed that approximately 30 pF is connected to each address line 70 60 50 40 30 20 CURRENT mA 10 0 i i i i i 2 10 20 30 40 50 60 CPU PERPHERAL CLOCKS MHz Figure 26 1 Typical Current Draw as a Function of the Main Clock Frequency Chapter 26 Low Power Operation 271 Figure 26 2 shows a typical current draw for the ultra sleepy modes 26 24 22 20 18 16 CURRENT yA 14 A isis m ee 0 5 10 15 20 25 30 25 CPU PERPHERAL CLOCKS kHz Figure 26 2 Typical Current Draw for the Ultra Sleepy Modes 26 1 1 Registers Register Name Mnemonic I O Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Global Power Save Control Register GPSCR 0x000D R W 00000000 Global Clock Double Register GCDR 0x000F R W 00000000 272 Rabbit 4000 Microprocessor User s Manual 26 2 Operation 26 2 1 Unused Pins Input or bidirectional pins that are unused in a design can pick up noise that may cause the transistors in the input buffer to switch states quickly causing unnecessary current draw To avoid this all unused pins should be connected to a weak pullup or pulldown resistor approximately 100 and left as inputs This provides protection from noise when the pin is an input but also limits the current draw if the pin gets inadvertently enabled as an output 26 2 2 Clock Rates The processor and peripheral clocks
285. ory device The tamper protection erase feature prevents loading a program into the onchip encryption RAM via the programming port and reading out the bytes The following other registers are also described in this chapter e Global Output Control Register GOCR which controls the behavior of the CLK STATUS WDT and BUFEN pins e Global CPU Register which holds the identification number of the processor e Global Revision Register GREV which hold the revision number of the processor Chapter 4 System Management 31 4 1 1 Block Diagram Basic System Peripherals Periodic Interrupt 488 us 32 kHz Clock GCSR Real Time Clock RTCxR RTCCR Interrupt Generation ij Timer WDTCR WDTTR Secondary Watchdog Timer WDTCR SWDTR 4 1 2 Registers Interrupt Generation Interrupt Request Interrupt Request Master Reset WDTOUT Pin Register Name Mnemonic I O Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Real Time Clock Control Register RTCCR 0x0001 W 00000000 Real Time Clock Byte 0 Register RTCOR 0x0002 Real Time Clock Byte 1 Register RTCIR 0x0003 R XXXXXXXX Real Time Clock Bvte 2 Register RTC2R 0 0004 R XXXXXXXX Real Time Clock Byte 3 Register RTC3R 0x0005 R XXXXXXXX Real Time Clock Byte 4 Register RTC4R 0x0006 R XXXXXXXX Real Time Clock Byte 5 Register RTCS
286. ory devices Optimal configurations for using 15 ns 45 55 ns and 70 ns memories are shown Note that there is always at least one wait state in the 16 bit mode Table 28 10 Recommended Clock Memory Configurations Input Internal Recommended Memory Setup Frequency Frequency Use MHz MHz SRAM Flash 7 Fastest 8 61 configuration 29 4912 58 9824 i es 8 d a without wait states run code from SRAM 16 bits 45 55 ns 16 bits 45 55 ns Fastest 16 bit 55 ns configuration 1 wait state 1 wait state without additional wait states 22 1184 44 2368 S bits 15g 8 bits 45 55 ns Fastest 8 bit 55 ns configuration 0 wait states 1 wait state with vastat run code in SRAM 18 4320 36 8640 16 bits 70 ns 16 bits 70 ns Fastest 16 bit 70 ns configuration 1 wait state 1 wait state without additional wait states 14 7456 29 4912 8 bits 45 55 ns 8 bits 45 55 ns Fastest 8 bit 55 ns configuration O wait states O wait states without wait states 11 0592 22 1184 8 bits 70 ns 8 bits 70 ns Fastest 8 bit 70 ns configuration O wait states O wait states without wait states The Rabbit 4000 is rated for a minimum clock period of 16 ns for both commercial and industrial specifications preliminary The commercial rating calls for a 5 voltage variation from 3 3 V and a temperature range from 40 to 70 The industrial ratings stretch the voltage variation to 10 over a temperature range fro
287. p Measure Time Interval from a Software Start to an External Event The following steps explain how to measure the time interval between a software start and the occurrence of an external event 1 Set up the counter to run continuously latch on the stop condition and generate an interrupt on the stop condition 2 Set up the stop condition for the event of interest 3 Reset the counter via ICCSR at the software start 4 In the interrupt handler read the counter as a time duration 21 3 5 Count Mode The following steps explain how to count pulses 1 Enable the input count mode by writing to ICCR and setting the counter to run continu ously until the stop condition occurs and to latch on the start condition in ICTxR 2 If an interrupt is desired at a particular count write that value into the LSB and MSB registers and enable the stop condition interrupt in ICCSR Set the start condition to match the signal type to be counted Reset the counter by writing to ICCSR Read the counter at any time to get the current count A If a match value is enabled and generates an interrupt you can re enable the count mode by clearing the counter via ICCSR and re enable the mode in ICTxR back to run ning continuously until the stop condition occurs 224 Rabbit 4000 Microprocessor User s Manual 21 4 Register Descriptions Input Capt
288. p af restore used registers ipres ret Chapter 22 Quadrature Decoder 235 22 4 Register Descriptions Quad Decode Control Status Register QDCSR Address 0x0090 Bit s Value Description 7 0 Quadrature Decoder 2 did not increment from the maximum count Read 1 Quadrature Decoder 2 incremented from the maximum count to 0 000 This bit only is cleared by a read of his register 6 0 Quadrature Decoder 2 did not decrement from zero Read 1 Quadrature Decoder 2 decremented from zero to the maximum count This bit is only cleared by a read of this register 5 This bit always reads as zero 4 0 No effect on the Quadrature Decoder 2 Write f only 1 Reset Quadrature Decoder 2 to all zeros without causing an interrupt 3 0 Quadrature Decoder 1 did not increment from the maximum count Read 1 Quadrature Decoder 1 incremented from the maximum count to zero This bit is only cleared by a read of this register 2 0 Quadrature Decoder 1 did not decrement from zero Read 1 Quadrature Decoder 1 decremented from zero to the maximum count This bit is only cleared by a read of this register 1 This bit always reads as zero 0 0 No effect on the Quadrature Decoder 1 Write 5 nly 1 Reset Quadrature Decoder to all zeros without causing an interrupt 236 Rabbit 4000 Microprocessor User s Manual Quad Decode Control Register QDCR Address 0x0091
289. p to 64KB of logical memory The RAM segment register RAMSR provides a shortcut for updating code by accessing it as data It provides a window that uses the instruction address decoding when read or written as data The Rabbit 4000 Designer s Handbook provides further details on the use of the separate instruction and data space feature 5 3 5 Memory Protection Memory blocks may be protected at three separate granularities as shown in Table 5 4 Writes can be prevented to any memory bank by writing to MBxCR Writes can be pre vented and trapped at a resolution of 64KB by enabling protection for that block in the appropriate WPxR register For further control two of those 64KB blocks be further subdivided into 4KB blocks by selecting them as the write protect segments A or B When a write is attempted to a block protected in WPxR WPSxLR or WPSxHR Priority 3 write protect interrupt occurs This feature is automatically enabled by writing to the block protection registers to disable it set all the write protect block registers to zero Table 5 4 Memory Protection Options Method Block Size Registers Used Memory Bank 128KB 4MB MBxCR MECR Write Protect Blocks 64KB WPCR WPxR Write Protect Segment A B 4KB WPSxR WPSxLR WPSxHR 5 3 6 Stack Protection The Rabbit 4000 provides stack overflow and underflow protection Low and high logical address limits can be setin STKLLR and STKHLR a
290. particular memory devices 48 Rabbit 4000 Microprocessor User s Manual 5 3 3 16 bit and Page Modes The Rabbit 4000 supports two additional memory modes to access both 16 bit and page mode devices on CSO and CS1 and can be enabled by writing to MACR The first mode supports a 16 bit memory device in addition to the normal 8 bit memory devices With this option the memory device connected to CSO or CS1 or both is assumed to have a 16 bit data path Parallel Port D is used for the high byte of the data and is configured auto matically for this operation when a 16 bit mode is enabled overriding any other Parallel Port D function Table 5 2 Advanced Memory Modes ee Prefetch Word Byte Wait State Primary Mode Bit 3 2 i Queue Writes Writes Register Use Setting 8 bit 00x No N A Yes c5 9M device 3 Data in 16 Basic 16 bit 10x No Yes No ACSxCR bit SRAM 01 Yes Yes No MBxCR peus 2d Advanced it Has 16 bit Code 16 11x Yes Yes Yes ACSxCR bit SRAM Only instruction fetches from the 16 bit memory space actually read 16 bits All data reads from the 16 bit memory space are eight bits with the proper byte lane swapping being done internally by the processor In addition because the processor can only handle a byte wide stream of instructions enabling the advanced 16 bit mode also enables an instruction prefetch queue This queue is three bytes deep in addi
291. pendencies 163 interrupts 161 163 166 example ISR 166 operation 164 configurations 167 connections 165 MAS ett 165 master slave communica iren 166 slave iie 165 slave master communica HOD css erret 166 OVETVIEW Lm 161 PIN USE 163 R W timing 168 register descriptions 170 TEISTETS 162 slave attention 161 timing diagrams 168 sleepy clock modes 19 SMODE pin settings 28 SPCR Parallel Port A setup 73 specifications 5 301 AC characteristics 303 BGA package 324 dimensions 325 land pattern 325 pinout 4 eee 324 specifications continued clock speeds 314 recommended clock mem ory configurations 314 DC characteristics 301 LQFP package 321 dimensions 322 land pattern 322 PC board layout 323 PINOUT 321 memory access times 304 311 external I O reads 308 external I O writes 309 memory reads 304 memory writes 305 package 321 power and current consump TOD scies etude 317 battery backed clock 319
292. peripherals In addition Parallel Port D acts as the upper byte of the data bus D 15 8 when 16 bit addressing is enabled The input capture peripheral can also watch pins PD7 PD5 and All pins are set as inputs on startup The individual bits can be set to be open drain via PDDCR See the associated peripheral chapters for details on how they use Parallel Port D 11 2 2 Clocks All outputs on Parallel Port D are clocked by the peripheral clock unless changed in PDCR where the option of updating the Parallel Port D pins can be synchronized to the output of Timer 1 Timer or Timer 2 90 Rabbit 4000 Microprocessor User s Manual 11 2 3 Other Registers Register Function SACR SBCR SCCR SDCR SECR SFCR Select a Parallel Port D pin as serial data and optional clock input ICSIR ICS2R Select a Parallel Port D pin as a start stop condition input QDCR Select a Parallel Port D pin as a decoder input IOCR Select a Parallel Port D pin as an external interrupt input DMROCR DMRICR Select a Parallel Port D pin as an external DMA request input MACR Enable 16 bit data bus 11 2 4 Interrupts External interrupts be accepted from pins 1 or see Chapter 7 for more details 11 3 Operation The following steps must be taken before using Parallel Port D 1 Select the desired input output direction for each pin v
293. pin is high Global CPU Register GCPU Address 0x002E Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00010 CPU identifier for this version of the chip Global Revision Register GREV Address 0x002F Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 Revision identifier for this version of the chip Chapter 4 System Management 39 Battery Backed Onchip Encryption RAM VRAMOO Address 0x0600 through through VRAM1F Address 0x061F Bit s Value Description 7 0 General purpose RAM locations Cleared by Intrusion Detect conditions 40 Rabbit 4000 Microprocessor User s Manual 5 5 1 Overview The Rabbit 4000 supports both 8 bit and 16 bit external flash and SRAM devices three chip selects and two read write enable strobes allow up to six external devices to be attached at once The 8 bit mode allows 0 1 2 or 4 wait states to be specified for each device and the 16 bit mode allows 0 to 9 wait states depending on the settings Both 8 bit and 16 bit page mode devices are also supported The Rabbit 4000 s physical memory space contains four
294. pt s vector begins on a 16 byte boundary inside the vector tables It may be possible to fit a small routine into that space but it is typical to place a call to a separate routine in that location Some Rabbit 4000 instructions are chained atomic which means that an interrupt can not occur between that instruction and the following instruction These instructions are useful for doing things like exiting interrupt handlers properly or updating semaphores Chapter 6 Interrupts 65 6 2 Operation To ensure proper operation all interrupt handler routines should be written according to the following guidelines e Push all registers to be used by the routine onto the stack before use and pop them off the stack before returning from the ISR e Keep the ISR as short and fast as possible e f the ISR will run for some time lower the interrupt priority as soon as possible within the ISR to allow other interrupts to occur e number of special rules apply to interrupts when operating in the system user mode please see the appropriate chapter for more details 6 3 Interrupt Tables Table 6 1 shows the structure of the internal interrupt vector table The first column is the vector address offset within the table The second column shows the vectors in the first 256 bytes of the table and the third column shows the vectors in the second 256 bytes Table 6 1 Internal Interrupt Vector Table Structure
295. pt This bit will always be read as zero 1 Force a periodic interrupt to be pending 42 000 Processor clock from the fast clock divided by 8 Peripheral clock from the fast clock divided by 8 001 Processor clock from the fast clock divided by 8 Peripheral clock from the fats clock 010 Processor clock from the fast clock Peripheral clock from the fast clock 011 Processor clock from the fast clock divided by 2 Peripheral clock from the fast clock divided by 2 100 Processor clock from the 32 clock optionally divided via GPSCR Peripheral clock from the 32 kHz clock optionally divided via GPSCR Processor clock from the 32 kHz clock optionally divided via GPSCR 101 Peripheral clock from the 32 kHz clock optionally divided via GPSCR The fast clock is disabled 110 Processor clock from the fast clock divided by 4 Peripheral clock from the fast clock divided by 4 111 Processor clock from the fast clock divided by 6 Peripheral clock from the fast clock divided by 6 1 0 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 280 Rabbit 4000 Microprocessor User s Manual Global Power Save Conirol Register GPSCR Address 0x000D Bit s Value Description 7 5 000 Self timed chip selects disabled 001 230 ns se
296. put port to create a sampled waveform while the entire buffer option can be used for example to send precisely timed serial messages over a serial port Chapter 19 DMA Channels 173 The DMA operation is controlled by memory structures called buffer descriptors The cur rent buffer descriptor resides in the registers of the DMA channel but may have been placed there either by the processor or loaded directly by the DMA channel itself Buffer descriptors may be used singly to transfer one block of data or they may be linked together for scatter gather operation Each DMA channel also contains an initial address that points to the first buffer descriptor in memory and allows the DMA channel to rewind itself automatically in the case of a transmit retry by the network port Each buffer descriptor contains a control byte a byte count for the data a source address a destination address and an optional link address In addition each DMA channel retains a count of the number of bytes remaining in the buffer to allow software to determine the amount of valid data in a buffer that are terminated early by the source of the data A buffer descriptor in memory consists of either 12 or 16 consecutive bytes organized as shown in Table 19 1 The DMA channel uses the information in the control byte to deter mine the length of the buffer descriptor as well as which information to fetch from the buffer descriptor If no link address field is prese
297. r 16 bit bus read or first page mode read access 110 One wait state for 16 bit bus read or first page mode read access 111 This bit combination is reserved and must not be used 4 3 00 Three wait states for subsequent page mode accesses 01 Two wait states for subsequent page mode accesses 10 One wait states for subsequent page mode accesses 11 Zero wait states for subsequent page mode accesses 2 0 000 Nine advanced or seven basic wait states for 16 bit bus write access 001 Eight advanced or six basic wait states for 16 bit bus write access 010 Seven advanced or five basic wait states for 16 bit bus write access 011 Six advanced or four basic wait states for 16 bit bus write access 100 Five advanced or three basic wait states for 16 bit bus write access 101 Four advanced or two basic wait states for 16 bit bus write access 110 Three advanced or one basic wait states for 16 bit bus write access 111 This bit combination is reserved and must not be used RAM Segment Register RAMSR Address 0x0448 Bit s Value Description 7 2 Compare value for RAM segment limit checking 1 0 00 Disable RAM segment limit checking 01 Select data type MMU translation if PC 15 10 is equal to RAMSR 7 2 10 Select data type MMU translation if PC 15 11 is equal to RAMSR 7 3 11 Select data type MMU translation if PC 15 12 is equal to RAMSR 7 4 58 Rabbit 4000 Microprocessor User s Manual Write Protect
298. r B3AxR 0x033C x R W 00000000 Breakpoint 4 Address 0 2 Register B4AxR 0x034C x R W 00000000 Breakpoint 5 Address 0 2 Register B5AxR 0x035C x R W 00000000 Breakpoint 6 Address 0 2 Register B6AxR 0x036C x R W 00000000 Breakpoint 0 Mask 0 2 Register BOMxR 0x0308 x R W_ 00000000 Breakpoint 1 Mask 0 2 Register BIMxR 0x0318 x R W 00000000 Breakpoint 2 Mask 0 2 Register B2MxR 0x0328 x R W 00000000 Breakpoint 3 Mask 0 2 Register B3MxR 0x0338 x R W 00000000 Breakpoint 4 Mask 0 2 Register B4MxR 0x0348 x 00000000 Breakpoint 5 Mask 0 2 Register B5MxR 0x0358 x R W 00000000 Breakpoint 6 Mask 0 2 Register B6MxR 0x0368 x R W 00000000 Chapter 25 Breakpoints 265 25 2 Dependencies 25 2 1 I O Pins There are no I O pins associated with breakpoints 25 2 2 Clocks There are no clocks associated with breakpoints 25 2 3 Other Registers There are no other registers associated with breakpoints 25 2 4 Interrupts When an enabled address match occurs for a given breakpoint a breakpoint interrupt occurs The breakpoint that caused the interrupt must be determined by reading BDCR which also clears the interrupt Any of the breakpoint interrupts can be enabled by writing to BDCR The breakpoint interrupt vector is in the EIR at offset 0x040 It is always set to Interrupt Priority 3 and is the highest priority interrupt if two Interrupt Priority 3 vectors are pend ing the br
299. r SDSR 0 00 R 0 00000 Serial Port D Control Register SDCR 0 00 4 xx000000 Serial Port Extended Register SDER 0 00 5 00000000 Serial Port Divider Low Register SDDLR 0 00 6 R W XXXXXXXX Serial Port D Divider High Register SDDHR 0 00 7 Oxxxxxxx 132 Rabbit 4000 Microprocessor User s Manual 16 2 Dependencies 16 2 1 Pins Serial Port A can transmit on parallel port pins PC7 PC6 or PD6 and can receive on pins or PET If the clocked serial mode is enabled the serial clock is either transmit ted or received on PB1 When an internal clock is selected in the clocked serial mode PB1 is automatically enabled as a clock output Serial Port B can transmit on parallel port pins PC5 PC4 or PD4 and can receive on pins 5 PDS or PES If the clocked serial mode is enabled the serial clock is either transmit ted or received on PBO When an internal clock is selected in the clocked serial mode PBO is automatically enabled as a clock output Serial Port C can transmit on parallel port pins PC3 or PC2 and can receive on pins PC3 PD3 or PE3 If the clocked serial mode is enabled and 8 bit memories are used the serial clock will be transmitted on PD2 and can be received on either PD2 or PE2 The serial clock may also be transmitted on PC7 PD7 or PE7 When 16 bit memories are used the serial clock can be transmitted on PC7 or PE7 and be received on P
300. r for 16 bit write operations Enable byte lane swapping for byte data reads Byte writes are not supported Only aligned word writes to CSO are allowed Use ACSOCR for wait states 10 Enable basic 16 bit operation for CSO Reads and writes are still bvte wide but byte lane swapping is enabled for reads Data is replicated for writes Use MBxCR for wait states unless Page Mode Advanced 16 bit operation for 50 Enable prefetch mechanism for instructions and word write accelerator for 16 bit write operations Enable byte lane swapping for byte data reads Byte writes are supported Use ACSOCR for wait states Page mode operation disabled for CSO Page mode operation enabled for CSO Pages 16 bytes Page mode accesses for program fetches only Use ACSOCR for wait states Chapter 5 Memory Management 57 Advanced Chip Select x Control Register ACSOCR Address 0x0410 ACS1CR Address 0x0411 Bit s Value Description 7 5 000 Seven wait states for 16 bit bus read or first page mode access 001 Six wait states for 16 bit bus read or first page mode read access 010 Five wait states for 16 bit bus read or first page mode access 011 Four wait states for 16 bit bus read or first page mode read access 100 Three wait states for 16 bit bus read or first page mode read access 101 Two wait states fo
301. r other use However all the Parallel Port D pins are used for the 16 bit data bus and so a pin on another parallel port then has to be selected for the clock output When Serial Port D is enabled in the clocked serial mode with an internal clock PDO becomes SCLKD and is not available for other use However all the Parallel Port D pins are used for the 16 bit data bus and so a pin on another parallel port then has to be selected for the clock output 330 Rabbit 4000 Microprocessor User s Manual A 2 Alternate Parallel Port Pin Inputs Table A 3 Alternate Parallel Port Pin Inputs Pin DMA REF Har eere rare pn Eds pu shake Decoder A D E F PA 7 0 PB7 6 Ex Em SCS 5 SA1 PB4 SA0 PB3 SRD m PB2 a SWR Ll SCLKA PBO SCLKB PC7 Yes RXA RXE PC6 5 RXB RCLKE TCLKE PC3 Yes RXC RXF PC2 RXD RCLKF PCO TCLKF PD7 Yes RXA RXE PD6 a Ex PD5 Yes RXB RCLKE PD4 TCLKE PD3 Yes DREQI
302. r physical address OXF000 0xFFFF in WP Segment x 6 0 Disable write protect for physical address OxEOOO OxEFFF in WP Segment x 1 Enable 4K write protect for physical address 0 000 in WP Segment x 5 0 Disable write protect for physical address OXD000 0xDFFF in WP Segment x 1 Enable write protect for physical address OxD000 0xDFFF in WP Segment x 4 0 Disable write protect for physical address 0OxXCO00 0xCFFF in WP Segment x 1 Enable write protect for physical address 0 000 in WP Segment x 3 0 Disable write protect for physical address 0xBOOO OxBFFF in WP Segment x 1 Enable write protect for physical address 0 000 0 in WP Segment x 2 0 Disable write protect for physical address 000 in WP Segment x 1 Enable write protect for physical address 0xA000 0xAFFF in WP Segment x 1 0 Disable write protect for physical address 0x9000 0x9FFF in WP Segment x 1 Enable write protect for physical address 0x9000 0x9FFF in WP Segment x 0 0 Disable write protect for physical address 0 8000 8 in WP Segment x 1 Enable write protect for physical address 0x8000 0x8FFF in WP Segment x Stack Limit Control Register STKCR Address 0 0444 Bit s Value Description 7 1 These bits are reserved and should be written with zeros 0 0 Disable stack limit checking 1 Enable stack limi
303. r then enters the User Mode and remains in the User Mode for all operations interrupts can be handled however the user desires Obviously the critical interrupts can be handled in the System Mode but at that point the device is typically reset and the error is logged Figure 27 1 shows an overview of this level of operation System Mode User Mode Application Critical code interrupts Critical Interrupts Interrupts Figure 27 1 System User Mode Setup for Memory Protection Only Chapter 27 System User Mode 287 27 3 2 Mixed System User Mode Operation This mode is similar to the previous mode but with some portions of the program written for System Mode for example peripheral interrupts where latency is critical By keep ing the System Mode code sections small potential system crashes are still minimized Figure 27 2 shows an overview of this level of operation System Mode User Mode Return from interrupts Application Critical code interrupts User defined interrupts Time critical interrupts Critical Interrupts Figure 27 2 System User Mode Setup for Mixed Operation 27 3 3 Complete Operating System This section describes a full use of the System User Mode separating all common functions into a System Mode operating system while letting the application specific code run in the User Mode By default the System Mode handles all peripherals and inter rupts as well as high level interf
304. rallel Port D bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port D bit 4 alternate output 0 TXB 01 Parallel Port D bit 4 alternate output 1 I4 10 Parallel Port D bit 4 alternate output 2 PWMO 11 Parallel Port D bit 4 alternate output 3 TCLKE Parallel Port D Control Register PDCR Address z 0x0064 Bit s Value Description 7 6 These bits are ignored and should be written with zero 5 4 00 The upper nibble peripheral clock is the peripheral clock 01 The upper nibble peripheral clock is the output of Timer A1 10 The upper nibble peripheral clock is the output of Timer B1 11 The upper nibble peripheral clock is the output of Timer B2 3 2 These bits are ignored and should be written with zero 1 0 00 The lower nibble peripheral clock is the peripheral clock 01 lower nibble peripheral clock is the output of Timer 1 10 The lower nibble peripheral clock is the output of Timer B1 11 The lower nibble peripheral clock is the output of Timer B2 Chapter 11 Parallel Port D 93 Parallel Port D Function Register PDFR Address 0x0065 Bit s Value Description 7 0 0 The corresponding port bit functions normally The corresponding port bit carries its alternate signal as an output See Table 11 1 Parallel Port D Drive Control Register PDDCR Address 0x0066 Bit s Value Description 7 0 0 The corresponding port
305. ream NRZ data encoding does not guarantee tran sitions in all cases a long string of zeros for example but the other data encodings do NRZI guarantees transitions because of the inserted zeros and the biphase encodings all have at least one transition per bit cell The DPLL counter normally counts by 16 but if a transition occurs earlier or later than expected the count will be modified during the next count cycle If the transition occurs earlier than expected it means that the bit cell boundaries are early with respect to the DPLL tracked bit cell boundaries so the count is shortened by either one or two counts If the transition occurs later than expected it means that the bit cell boundaries are late with 152 Rabbit 4000 Microprocessor User s Manual respect to the DPLL tracked bit cell boundaries so the count is lengthened by either one or two counts The decision to adjust by one or by two depends on how far off the DPLL tracked bit cell boundaries are This tracking allows for minor differences in the transmit and receive clock frequencies With NRZ and NRZI data encoding the DPLL counter runs continuously and adjusts after every receive data transition Since NRZ encoding does not guarantee a minimum density of transitions the difference between the sending data rate and the DPLL output clock rate must be very small and depends on the longest possible run of zeros in the received frame NRZI encoding guarantees at lea
306. receiver data buffer Last Byte Bit Pattern Valid Data Bits bbbbbbbO 7 bbbbbb01 6 bbbbb011 5 bbbb0111 4 bbb01111 3 bb011111 2 b0111111 1 Chapter 17 Serial Ports 151 Several types of data encoding are available in HDLC mode In addition to the normal NRZ they NRZI biphase level Manchester biphase space FMO and biphase mark FM1 Examples of these encodings are shown below Note that the signal level does not convey information in NRZI biphase space and biphase mark Instead it is the placement of the transitions that determine the data In biphase level it is the polarity of the transition that determines the data SERIAL ao LIU L NRZI h h A h i NRZI BIPHASE LEVEL BIPHASE SPACE BIPHASE SPACE BIPHASE MARK BIPHASE MARK DATA Figure 17 1 Examples of Data Encoding In the HDLC Mode In the HDLC mode the internal clock comes from the output of Timer A2 Timer A3 or the dedicated divider The timer divider output is divided by 16 to form the transmit clock and is fed to the digital phase locked loop DPLL to form the receive clock The DPLL is basically just divide bv 16 counter that uses the timing of the transitions on the receive data stream to adjust its count The DPLL adjusts the count so that the DPLL output will be properly placed in the bit cells to sample the receive data To work properly then tran sitions are required in the receive data st
307. ress 0x00F8 Bit s Value Description 70 Access the Timer register pointed to by TCBPR is automatically updated to the next Timer C register address in the sequence Chapter 15 Timer C Timer Block Pointer Register TCBPR Address 0x00F9 Bit s Value Description 7 5 These bits always read as 0 0 4 0 Five least significant bits of the Timer C register address for indirect access Global Control Status Register GCSR Address 0x0000 Bit s Value Description 45 000 Processor clock from the main clock divided by eight Peripheral clock from the main clock divided by eight 001 Processor clock from the main clock divided by eight Peripheral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Processor clock from the 32 clock optionally divided via GPSCR Peripheral clock from the 32 kHz clock optionally divided via GPSCR Processor clock from the 32 kHz clock optionally divided via GPSCR 101 Peripheral clock from the 32 kHz clock optionally divided via GPSCR The fast clock is disabled 110 Processor clock from the main clock divided by four Peripheral clock from the main clock divided by four i Processor clock from the main clock divided by
308. ripheral chapter for further use of that pin Once the port is set up data can be read or written by accessing PCDR The value in PCDR of an output pin will reflect its current output value but any value written to an input pin will not appear until that pin becomes an output Chapter 10 Parallel Port C 83 10 4 Register Descriptions Parallel Port C Data Register PCDR Address 0x0050 Bit s Value Description 7 0 Read The current state of Parallel Port C pins PC7 PCO is reported The Parallel Port buffer is written with this value for transfer to the Parallel Write Port output register on the next rising edge of the peripheral clock Parallel Port C Data Direction Register PCDDR Address 0x0051 Bit s Value Description 7 0 0 The corresponding port bit is an input 1 The corresponding port bit is an output Parallel Port C Alternate Low Register PCALR Address 0x0052 Bit s Value Description 7 6 00 Parallel Port C bit 3 alternate output 0 TXC 01 Parallel Port bit 3 alternate output 1 13 10 Parallel Port C bit 3 alternate output 2 TIMER C3 11 Parallel Port bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port C bit 2 alternate output 0 TXC 01 Parallel Port C bit 2 alternate output 1 12 10 Parallel Port C bit 2 alternate output 2 TIMER C2 11 Parallel Port bit 2
309. ription Two MSBs of the compare value for the Timer B comparator This compare 7 6 value will be loaded into the actual comparator when the current compare detects a match 5 0 These bits are reserved and should be written with zero Timer B Count LSB x Register TBL1R Address 0x00B3 TBL2R Address 0x00B5 Bit s Value Description Eight LSBs of the compare value for the Timer B comparator This compare 7 0 value will be loaded into the actual comparator when the current compare detects a match Timer B Step LSB x Regisiter TBSL1R Address 0x00BA TBSL2R Address 0x00BC Bit s Value Description Eight LSBs of the step size for the Timer B comparator The new compare value 7 0 will be loaded into the actual comparator when the current compare detects a match Timer B Step MSB x Register TBSM1R Address 0x00BB TBSM2R Address 0x00BD Bit s Value Description 7 2 These bits are ignored but should be written with zeros Two MSBs of the step size for the Timer B comparator The new compare value 1 0 will be loaded into the actual comparator when the current compare detects a match Timer B Count MSB Register TBCMR Address 0x00BE Bit s Value Description 7 6 read The current value of the two MSBs of the Timer B counter are reported 5 0 These bits are always read as zeros Chapter 14 Timer B 119
310. rnal I O 7 0 Strobes External I O Address 7 5 3 1 7 6 PWM Output Timer C Output zm External Interrupts Slave Port CS DMA Request 5 2 Quadrature Decoder mn Input Capture LEES SON Chapter 11 Parallel Port D 89 11 1 2 Registers Register Name Mnemonic I O Address R W Reset Port D Data Register PDDR 0x0060 R W XXXXXXXX Port D Alternate Low Register PDALR 0x0062 R W 00000000 Port D Alternate High Register PDAHR 0x0063 R W 00000000 Port D Control Register PDCR 0x0064 R W xx00xx00 Port D Function Register PDFR 0x0065 Port Drive Control Register PDDCR 0x0066 Port Data Direction Register PDDDR 0x0067 00000000 Port D Bit 0 Register PDBOR 0x0068 W XXXXXXXX Port D Bit 1 Register PDBIR 0x0069 W XXXXXXXX Port D Bit 2 Register PDB2R 0x006A W XXXXXXXX Port D Bit 3 Register PDB3R 0x006B W XXXXXXXX Port D Bit 4 Register PDB4R 0 006 W XXXXXXXX Port D Bit 5 Register PDBSR 0x006D W XXXXXXXX Port D Bit 6 Register PDB6R 0 006 W XXXXXXXX Port D Bit 7 Register PDB7R 0x006F W XXXXXXXX 11 2 Dependencies 11 2 1 I O Pins Parallel Port D uses pins PDO through PD7 These pins can be used individually as data inputs or outputs as serial port transmit and receive for Serial Ports A B E and F as clocks for Serial Ports as external I O strobes or as outputs for the PWM and Timer
311. roprocessor User s Manual 20 2 Dependencies 20 2 1 Pins The network port has six dedicated pins two input pins RxD and RxD and four output pins TxD TxD TxDD TxDD These pins can be used as general purpose inputs and outputs if the network port is not being used via NAPCR The 20 MHz clock will typically be input from PEG Pin PE7 can be enabled as a LNK signal that will be active low whenever the device has an active link and inactive high at all other times Pin PES can be enabled as a ACT signal that will be active low for 0 1 seconds following each packet transmission and inactive high at all other times 20 2 2 Clocks The network port requires a 20 MHz clock input for proper 10Base T operation It is expected that this clock is input from pin PE6 but it is also possible to source this clock from the processor clock or the processor clock divided by two assuming a 20 MHz or a 40 MHz clock is installed If the processor clock is used the clock doubler and dither should be disabled NOTE Unlike the other clock inputs on the Rabbit 4000 the PE6 network clock input does not have a Schmitt trigger inside the device It is strongly recommended that you place an external Schmitt trigger on the input to PE6 if PE6 is to be used as the network clock input 20 2 3 Other Registers Register Function PEFR PEAHR Selection of LNK and ACT signals 20 2 4 Interrupts The network interrupt
312. rrect instruction byte being read The exact circumstances that cause the missed wait state are complicated to predict be cause they involve the advanced 16 bit operating mode In this mode a semi autonomous prefetch mechanism fetches words from a 16 bit memory to feed to the instruction decoder The fetched instruction bytes are presented to the instruction decoder on an as needed basis which is only loosely coupled to the operation of the external memory bus The bug can only occur if the following conditions are met 1 One of these three instructions is used JP HL JP IX or JP 2 The jump is from a memory using the advanced 16 bit mode into a memory that is not using the advanced 16 bit mode 3 The destination memory requires wait states Whether the bug occurs is a function of when the instruction decoder accepts the JP instruction relative to the fetch of the next instruction on the bus This in turn depends on both the instructions immediately prior to the JP instruction and the number of wait states used by the prefetch mechanism 336 Rabbit 4000 Microprocessor User s Manual simplest workaround is to not use the instructions listed above The same operation can be handled by the following code sequence PUSH HL or IX or IY RET This code sequence will take more clocks to execute Another way to avoid the bug is to increase the number of wait states if possible on the device operating in t
313. rrupt Priority 2 11 The Network Port uses Interrupt Priority 3 212 Rabbit 4000 Microprocessor User s Manual Network Port Status Register NASR Address 0x0205 Bit s Value Description 7 This bit is unused 6 0 Link operating half duplex 1 Link operating full duplex 5 This bit is unused 4 0 Auto negotiation process not completed 1 Auto negotiation process completed 3 2 These bits are unused 1 0 Link is down 1 Link is up 0 0 No jabber condition detected Jabber condition detected A jabber condition automatically halts the DMA 1 channel sourcing the data for the transmitter and disables the transmit DMA request The network port transmitter must be reset to clear this condition Network Port A Reset Register NARR Address 0x0206 Bit s Value Description 7 0 No operation Reset the network port transmitter This command clears the jabber condition and 1 purges the transmit FIFO It does not affect a transmit operation in progress and should only be written when the transmitter are disabled and in an idle state 6 0 No operation Reset the network port receiver This command clears all of the error counters 1 and purges the receive FIFO It does not affect a receive operation in progress and should only be written when the receiver is disabled and in an idle state 5 0 1 Purge the network port tra
314. rt A Status Register SASR 0x00C3 R 0 00000 Serial Port A Control Register SACR 0 00 4 000000 Serial Port Extended Register SAER 0 00 5 00000000 Serial Port A Divider Low Register SADLR 0 00 6 R W XXXXXXXX Serial Port A Divider High Register SADHR 0x00C7 R W Oxxxxxxx Serial Port B Data Register SBDR 0x00DO R W XXXXXXXX Serial Port B Address Register SBAR 0x00D1 W XXXXXXXX Serial Port B Long Stop Register SBLR 0x00D2 W XXXXXXXX Serial Port B Status Register SBSR 0x00D3 R 0xx00000 Serial Port B Control Register SBCR 0x00D4 R W xx000000 Serial Port B Extended Register SBER 0x00D5 R W 00000000 Serial Port B Divider Low Register SBDLR 0x00D6 R W XXXXXXXX Serial Port B Divider High Register SBDHR 0x00D7 R W Oxxxxxxx Serial Port C Data Register SCDR 0 00 0 Serial Port Address Register SCAR 0 00 1 W XXXXXXXX Serial Port C Long Stop Register SCLR 0 00 2 W XXXXXXXX Serial Port C Status Register SCSR 0 00 R 0xx00000 Serial Port C Control Register SCCR 0 00 4 000000 Serial Port Extended Register SCER 0 00 5 00000000 Serial Port Divider Low Register SCDLR 0 00 6 Serial Port Divider High Register SCDHR 0 00 7 Oxxxxxxx Serial Port Data Register SDDR 0 00 0 R W XXXXXXXX Serial Port D Address Register SDAR 0 00 1 W XXXXXXXX Serial Port D Long Stop Register SDLR 0x00F2 W XXXXXXXX Serial Port D Status Registe
315. rupt Priority 1 10 DMaA interrupts use Interrupt Priority 2 11 DMA interrupts use Interrupt Priority 3 188 Rabbit 4000 Microprocessor User s Manual DMA Master Timing Control Register DMTCR Address 0 0105 Bit s Value Description 7 6 Ox Fixed DMA channel priority Higher channel number has higher priority 10 Rotating DMA channel priority Priority rotates highest channel number to lowest channel number after every byte is transferred T Rotating DMA channel priority Priority rotates highest channel number to lowest channel number after the current channel request is serviced 5 3 000 Maximum one byte per burst 001 Maximum two bytes per burst 010 Maximum three bytes per burst 011 Maximum four bytes per burst 100 Maximum eight bytes per burst 101 Maximum 16 bytes per burst 110 Maximum 32 bytes per burst 111 Maximum 64 bytes per burst 2 0 000 Minimum 12 clocks between bursts 001 Minimum 16 clocks between bursts 010 Minimum 24 clocks between bursts 011 Minimum 32 clocks between bursts 100 Minimum 64 clocks between bursts 101 Minimum 128 clocks between bursts 110 Minimum 256 clocks between bursts 111 Minimum 512 clocks between bursts Chapter 19 DMA Channels 189 DMA Master Request 0 Control Register DMROCR Address 0x0106 Bit s Value Description 7 6 00 External DMA Request 0 disabled 01 External DMA Reque
316. rupt vector before you enable the interrupts 1 Write the vector of the interrupt service routine to the internal interrupt table 2 Configure TACSR to select which timers will generate an interrupt 3 Configure TACR to select the interrupt priority note that interrupts will be enabled once this value is set This should be done last The interrupt request is cleared by reading from TACSR 13 3 2 Example ISR A sample interrupt handler is shown below timerA_isr push af Save used registers ioi 14 TACSR clear the interrupt request and get status handle all interrupts flagged in TACSR here pop af restore registers ipres ret Chapter 13 Timer A 111 13 4 Register Descriptions Timer A Conirol Status Register TACSR Address 0x00A0 Bit s Value Description 74 0 corresponding Timer A counter has not reached its terminal count Read The corresponding Timer A counter has reached its terminal count These status only 1 bits not the interrupt enable bits are cleared by the read of this register as is the Timer A interrupt 74 0 corresponding Timer interrupt is disabled Write 1 The corresponding Timer A interrupt is enabled only 0 0 The main clock for Timer A is disabled 1 The main clock for Timer A perclk is enabled Timer A Prescale Register TAPR Address 0x00A1 Bit s Value Description 7 1 These bits re
317. rupts 69 7 2 1 Registers Register Address R W Reset Interrupt 0 Control Register IOCR 0 0098 000000 Interrupt 1 Control Register 0 0099 000000 7 3 Dependencies 7 3 1 Pins The external interrupts can be enabled on pins PDO PD1 PEO PE4 and PES Each pin is associated with a particular interrupt vector as shown in Table 7 1 below Table 7 1 Rabbit 4000 Interrupt Vectors Vector Register Pins Interrupt 0 IOCR PDO PEO PE4 Interrupt 1 PES 7 3 2 Clocks The external interrupts are controlled by the peripheral clock A pulse must present for at least three peripheral clock cycles to trigger an interrupt 7 3 3 Interrupts An external interrupt is generated whenever the selected edge occurs on an enabled pin The interrupt request is automatically cleared when the interrupt is handled The external interrupt vectors are in the EIR at offsets 0 000 and 0 010 They be set as Priority 1 2 or 3 in the appropriate IxCR 7 4 Operation The following steps must be taken to enable the external interrupts 1 Write the vector s to the interrupt service routine to the external interrupt table 2 Configure IxCR to select which pins are enabled for external interrupts what edges are detected on each pin and the interrupt priority 7 4 1 Example ISR A sample interrupt
318. s 0x01D6 D6SA2R Address 0x01E6 D7SA2R Address 0x01F6 Bit s Value Description 7 0 Bits 23 16 of the source address are stored in this register 198 Rabbit 4000 Microprocessor User s Manual y Destination Addr 7 0 Register DODAOR Address 0x0188 DIDAOR Address 0 0198 D2DAOR Address 0x01A8 D3DAOR Address 0x01B8 DADAOR Address 0x01C8 D5DAOR Address 0x01D8 D6DAOR Address 0x01E8 D7DAOR Address 0x01F8 Bit s Value Description 7 0 Bits 7 0 of the destination address are stored in this register DMA y Destination Addr 15 8 Register DODA1R Address 0x0189 D1DA1R Address 0x0199 D2DA1R Address 0x01A9 D3DA1R Address 0x01B9 D4DA1R Address 0x01C9 D5DA1R Address 0x01D9 D6DA1R Address 0x01E9 D7DA1R Address 0x01F9 Bit s Value Description 7 0 Bits 15 8 of the destination address are stored in this register DMA y Destination Addr 23 16 Register DODA2R Address 0x018A D1DA2R Address 0x019A D2DA2R Address 0x01AA D3DA2R Address 0x01BA D4DA2R Address 0x01CA D5DA2R Address 0x01DA D6DA2R Address 0x01EA D7DA2R Address 0x01FA Bit s Value Description 7 0 Bits 23 16 of the destination address are stored in this register Chapter 19 DMA Channels 199 DMA y Link Addr 7 0 Register DOLAOR Address 0x018C
319. s Value Description 7 0 Disable User Mode access to Parallel Port E I O addresses 0 0070 0 007 1 Enable User Mode access to Parallel Port E I O addresses 0 0070 0 007 6 0 These bits are reserved and should be written with zeros Input Capture User Enable Register ICUER Address 0x0358 Bit s Value Description 7 0 Disable User Mode access to input capture I O addresses 0 0056 0 005 1 Enable User Mode access to input capture I O addresses 0 0056 0 005 6 0 These bits are reserved and should be written with zeros Chapter 27 System User Mode 295 Bank User Enable Register IBUER Address 0x0380 Bit s Value Description 7 0 Disable User Mode access to I O Bank 7 and internal I O address 0x0087 1 Enable User Mode access to I O Bank 7 and internal I O addresses 0 0087 6 0 Disable User Mode access to I O Bank 6 and internal I O address 0 0086 1 Enable User Mode access to I O Bank 6 and internal I O addresses 0 0086 5 0 Disable User Mode access to I O Bank 5 and internal I O address 0x0085 1 Enable User Mode access to I O Bank 5 and internal I O addresses 0 0085 4 0 Disable User Mode access to I O Bank 4 and internal I O address 0 0084 1 Enable User Mode access to I O Bank 4 and internal I O addresses 0 0084 3 0 Disable User Mode access to I O Bank 3 and internal I O address 0 0083 1 En
320. s the DMA to write to a fixed internal I O location but still program all of the relevant Timer registers The pointer register can be written and read if necessary Nor mally the pointer register is initialized to 0x02 the Timer C Divider Low Register and the DMA then transfers blocks of 18 bytes to completely reprogram Timer C 0x502 gt 0x503 gt 0x508 gt 0 509 gt 0 50 gt 0 50 gt 0 50 gt 0x50D gt 0 50 gt 0 50 gt 0 518 gt 0 519 gt 0 51 gt 0x51B gt 0 51 gt 0 51 gt 0 51 gt 0 51 gt When the DMA destination address is the TCBAR the DMA request from Timer is connected automatically to the DMA Chapter 15 Timer C 121 15 1 1 Block Diagram Timer C perclk 2 Interrupt Interrupt perclk 16 Up Generation Request Timer A1 Counter Divider Registers Timer Cx set x Register Parallel Ports reset x Register 122 Rabbit 4000 Microprocessor User s Manual 15 1 2 Registers Register Name Mnemonic Address R W Reset Timer C Control Status Register TCCSR 0x0500 xxxx0000 Timer Control Register TCCR 0x0501 xx000000 Timer Divider Low Register TCDLR 0x0502 00000000 Timer Divider High Register TCDHR 0x0503 00000000 Timer Set 0 Low Register TCSOLR 0x0508 Timer Set 0 High Reg
321. served and should be written with zero 0 0 The main clock for Timer A is the peripheral clock perclk 1 The main clock for Timer A is the peripheral clock divided by two perclk 2 112 Rabbit 4000 Microprocessor User s Manual Timer A Control Register TACR Address 0x00A4 Bit s Value Description 7 0 Timer A7 clocked by the main Timer A clock Timer A7 clocked by the output of Timer 1 Timer A6 clocked by the main Timer A clock Timer A6 clocked by the output of Timer A1 Timer A5 clocked by the main Timer A clock Timer A5 clocked by the output of Timer A1 Timer A4 clocked by the main Timer A clock Timer A4 clocked by the output of Timer 1 Timer A3 clocked by the main Timer A clock Timer A3 clocked by the output of Timer A1 Timer A2 clocked by the main Timer A clock Timer 2 clocked by the output of Timer 1 00 Timer A interrupts are disabled 01 Timer A interrupt use Interrupt Priority 1 10 Timer A interrupt use Interrupt Priority 2 Timer A interrupt use Interrupt Priority 3 Timer A Time Constant x Register TAT1R TAT2R TAT3R TATAR TAT5R TAT6R TAT7R TAT8R TAT9R TAT10R Address 0 00 Address 0 00 5 Address 0x00A7 Address 0x00A9 Address 0x00AB Address 0x00AD Address 0x00AF Address 0x00A6 Address 0x00A8 Address
322. ssumed that approximately 30 pF is connected to each address line 70 60 50 D o 30 20 CURRENT mA 10 0 i i i i i 2 10 20 30 40 50 60 CPU PERPHERAL CLOCKS MHz Figure 28 5 Typical Current Draw as a Function of the Main Clock Frequency Chapter 28 Specifications 317 28 5 1 Sleepy Mode Current Consumption The Rabbit 4000 supports designs with very low power consumption by using features such as the ultra sleepy modes and self timed chip selects At the low frequencies possible in the ultra sleepy modes as low as 2 kHz the external memory devices become signifi cant factors in the current consumption unless one of the short or self timed chip selects are used Figure 28 6 shows a typical current draw for the ultra sleepy modes 26 24 22 20 18 16 CURRENT pA 14 12 l TE ens cime E v 0 5 10 15 20 25 30 35 CPU PERPHERAL CLOCKS kHz Figure 28 6 Typical Current Draw for the Ultra Sleepy Modes 318 Rabbit 4000 Microprocessor User s Manual 28 5 2 Battery Backed Clock Current Consumption For the battery backed features of the Rabbit 4000 to perform while the processor is pow ered down both the VBAT and BATIO pins need to be supplied properly The VBAT pin powers the internal real time clock and the battery backed SRAM while VBATIO powers the RESET CS1 CLK32K and RESOUT pins Note that the VBATIO pin can be powered at 1 8 V during powerdown even if the pr
323. st 0 enabled from Parallel Port D2 10 External DMA Request 0 enabled from Parallel Port E2 11 External DMA Request 0 enabled from Parallel Port E6 5 This bit is reserved and should be written with zero 4 3 00 External DMA Request 0 falling edge triggered One transfer per request 01 External DMA Request 0 rising edge triggered One transfer per request 10 External DMA Request 0 active low Transfers continue while low 11 External DMA Request 0 active high Transfers continue while high 2 0 000 External DMA Request 0 supplied to DMA Channel 0 001 External DMA Request 0 supplied to DMA Channel 1 010 External DMA Request 0 supplied to DMA Channel 2 011 External DMA Request 0 supplied to DMA Channel 3 100 External DMA Request 0 supplied to DMA Channel 4 101 External DMA Request 0 supplied to DMA Channel 5 110 External DMA Request 0 supplied to DMA Channel 6 111 External DMA Request 0 supplied to DMA Channel 7 190 Rabbit 4000 Microprocessor User s Manual DMA Master Request 1 Control Register DMR1CR Address z 0x0107 Bit s Value Description 7 6 00 External DMA Request 1 disabled 01 External DMA Request 1 enabled from Parallel Port D3 10 External DMA Request 1 enabled from Parallel Port E3 11 External DMA Request 1 enabled from Parallel Port E7 5 This bit is reserved and s
324. st one transition every six bits with the inserted zeros Since the DPLL can adjust by two counts every bit cell the maximum dif ference between the sending data rate and the DPLL output clock rate is 1 48 2 With biphase data encoding either biphase level biphase mark or biphase space the DPLL runs only as long as transitions are present in the receive data stream Two consecu tive missed transitions causes the DPLL to halt operation and wait for the next available transition This mode of operation is necessary because it is possible for the DPLL to lock onto the optional transitions in the receive data stream Since they are optional they will eventually not be present and the DPLL can attempt to lock onto the required transitions Since the DPLL can adjust by one count every bit cell the maximum difference between the sending data rate and the DPLL output clock rate is 1 16 6 With biphase data encoding the DPLL is designed to work in multiple access conditions where there might not be flags on an idle line The DPLL will generate an output clock correctly based on the first transition in the leading zero of an opening flag Similarly only the completion of the closing flag is necessary for the DPLL to provide the extra two clocks to the receiver to assemble the data correctly The transition is specified as follows e In the biphase level mode this means the transition that defines the last zero of the closing flag e In t
325. t A and up to eight address lines on Parallel Port B This functionality is mutu ally exclusive with the slave port and regular parallel I O on Parallel Ports A and B When enabled the address lines of the auxiliary I O bus hold their value until a new value is written to them The data lines return to a tristate mode after each transaction See Section 24 1 2 for memory timing for external I O accesses Chapter 24 External I O Control 247 24 1 2 I O Strobes There are eight I O strobes available in the Rabbit 4000 Each has a separate 8KB address range that can be enabled as a chip select read strobe write strobe or a read write strobe The number of wait states can be set to 1 3 7 or 15 and the signal can be active high or low Table 24 1 External I O Strobes Register External I O Address Range IBOCR 0x0000 0x 1 FFF IBICR 0x2000 0x3FFF IB2CR 0 4000 5 IB3CR 0x6000 0x7FFF IB4CR 0 8000 0 9 IBSCR 0xA000 0xBFFF IB6CR 0xC000 0xDFFF IB7CR OxE000 0xFFFF The I O strobes can be used for devices on the memory bus or the auxiliary I O bus and can be enabled to go out on the memory bus alone or both buses It is also possible to shorten the read strobe by one clock cycle and the write strobe by one half a clock cycle by pulling in the trailing edge which guarantees one clock cycle of hold time for transac tions T1 Tw T2 J X5 mq 00 WRITE DATA 0
326. t adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up With biphase level encoding there is a guaranteed clock transition at the center of every bit cell and optional data transitions occur at the bit cell boundaries The DPLL only uses the clock transitions to track the bit cell boundaries by ignoring all transitions occur ring outside a window around the center of the bit cell This window is half a bit cell wide Additionally because the clock transitions are guaranteed the DPLL requires that they always be present If no transition is found in the window around the center of the bit cell for two successive bit cells the DPLL is not in lock and immediately enters the search mode The search mode assumes that the next transition seen is a clock transition and immediately synchronizes to this transition No clock output is provided to the receiver during the search operation Decoding biphase level data requires that the data be sampled at either the quarter or three quarter point in the bit cell The DPLL here uses the quarter point to sample the data 154 Rabbit 4000 Microprocessor User s Manual Biphase mark encoding biphase space encoding are identical as far as DPLL is concerned and are similar to biphase level encoding The primary difference is the place ment of the clock and data transitions With these encodings the clock transitions are at the bit cell boundary t
327. t checking Stack Low Limit Register STKLLR Address 0x0445 Bit s Value Description Lower limit for stack limit checking If a stack operation or stack relative 7 0 memory access is attempted at an address less than STKLLR 0x10 a stack limit violation interrupt is generated 62 Rabbit 4000 Microprocessor User s Manual Stack High Limit Register STKHLR Address 0x0446 Bit s Value Description Upper limit for stack limit checking If a stack operation or stack relative 7 0 memory access is attempted at an address greater than STKHLR OxEF a stack limit violation interrupt is generated Chapter 5 Memory Management 63 64 Rabbit 4000 Microprocessor User s Manual 6 INTERRUPTS 6 1 Overview The Rabbit 4000 can operate at one of four priority levels 0 3 with Priority 0 being the expected standard operating level The current priority and up to three previous priority levels are kept in the processor s 8 bit IP register where bits 0 1 contain the current priority Every time an interrupt is handled or an IPSET instruction occurs the value in the register is shifted left by two bits and the new priority placed in bits 0 1 When an IPRES or IRET instruction occurs the value in IP is shifted right by two bits bits 0 are shifted into bits 6 7 On reset the processor starts at Priority 3 Most interrupts be set to be Priority 1 3 A pending interr
328. t from one of the following parallel port pins 5 7 PD1 PD5 PD7 PE1 PES PE7 Use ICTXR to select which input pin to trigger on Note that these pins can be used for other peripherals at the same time as the input capture peripheral For example you can use input capture to use measure the pulse width on a serial port input to measure the baud rate 21 2 2 Clocks The 16 bit input capture counters are clocked from the output of Timer A8 and can run at rates from perclk 2 down to perclk 512 by writing the appropriate value to TATSR 21 2 3 Other Registers Register Function TAT8R Time constant for input capture clock 21 2 4 Interrupts Each input capture channel can generate an interrupt whenever a start stop condition occurs or when the counter rolls over to zero The interrupt request is cleared when ICCSR is read The input capture interrupt vector is in the IIR at offset Ox1A0 It can be set as Priority 1 2 or 3 The input capture channels synchronize their inputs to the peripheral clock further divided by Timer A8 Since the inputs are only sampled in synch with the peripheral clock any faster state faster changes cannot be detected which is akin to a digital low pass filter functionality on the inputs Because of this there is some delay between the input transition and when an interrupt is requested as shown below The status bits in ICSxR are set coincid
329. t is disabled 01 The serial port uses Interrupt Priority 1 10 The serial port uses Interrupt Priority 2 11 The serial port uses Interrupt Priority 3 158 Rabbit 4000 Microprocessor User s Manual Serial Port x Extended Register SEER Address 0x00CD Asynchronous Mode Only SFER Address 0x00DD Bit s Value Description 7 5 000 Disable parity generation and checking 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 Enable parity generation and checking with even parity 101 Enable parity generation and checking with odd parity 110 Enable parity generation and checking with space always zero parity 111 Enable parity generation and checking with mark always one parity 4 0 Normal asynchronous data encoding 1 Enable RZI coding 3 16 bit cell IIDA compliant 3 0 Normal break operation This option should be selected when address bits are expected 1 Fast break termination At the end of break a dummy character is written to the buffer and the receiver can start character assembly after one bit time 2 0 Asynchronous clock is 16x data rate 1 Asynchronous clock is 8x data rate 1 0 Continue character assembly during break to allow timing the break condition 1 Inhibit character assembly during break One character all zeros with fra
330. t of Clock Doubler The doubled clock low time is subject to wide 5096 variation since it depends on process parameters temperature and voltage The times given above are for a core supply voltage of 1 8 V and a temperature of 25 C The values increase or decrease by 1 for each 5 C increase or decrease in temperature The doubled clock is created by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a slightly different length Since the duty cycle of the built in oscillator can be as asymmetric as 52 48 the clock generated by the clock doubler will exhibit up to a 4 variation in period on alternate clocks Memory access time is not affected because memory bus cycle is 2 clocks long and includes both a long and a short 16 Rabbit 4000 Microprocessor User s Manual clock resulting in no net change due to asymmetry However if odd number of wait states is used then the memory access time will be affected slightly The maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler The only signals clocked on the falling edge of the clock are the mem ory and I O write pulses and the early option memory output enable See Chapter 5 for more information on the early output enable and write enable options The power consumption is proportional to the clock frequency and for this reason power can be reduced by
331. t register to use Since there are 256 64K blocks in the 16MB memory space the 8 MSBs the memory block must be on a 64K boundary of the physical address is divided by 256 In total there are 32 write protect registers so the result is further divided by 32 This number is then added to the address of the first write protect register 0x460 to give the address of the write protect register that controls the 64K 1 block in question physaddr xxxxxxh 1 64 physaddr 16 regnum blk64 3 register address regnum 0x460 Each write protect register controls 8 64K blocks Now that you have the register address you need to know that the register bit selects the correct 64K block This is calculated using b1k64 a value between 0 255 bitnum blk64 amp 0x7 60 Rabbit 4000 Microprocessor User s Manual Write Protect Segment x Register WPSAR Address 0x0480 WPSBR Address 0x0484 Bit s Value Description 70 When these eight bits 23 16 match bits of the physical address write protect that 64K range increments using WPSxLR WPSxHR Write Protect Segment x Low Register WPSALR Address 0x0481 WPSBLR Address 0x0485 Bit s Value Description 7 0 Disable write protect for physical address 0x7000 0x7FFF in WP Segment x 1 Enable write protect for physical address 0x7000 0x7FFF in WP Segment x 6 0 Disable write pro
332. t s Value Description 7 5 000 Disable parity generation and checking 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 Enable parity generation and checking with even parity 101 Enable parity generation and checking with odd parity 110 Enable parity generation and checking with space always zero parity 111 Enable parity generation and checking with mark always one parity 4 0 Normal asynchronous data encoding 1 Enable RZI coding 3 16 bit cell IIDA compliant 3 0 Normal break operation This option should be selected when address bits are expected 1 Fast break termination At the end of break a dummy character is written to the buffer and the receiver can start character assembly after one bit time 2 0 Asynchronous clock is 16x data rate 1 Asynchronous clock is 8x data rate 1 0 Continue character assembly during break to allow timing the break condition 1 Inhibit character assembly during break One character all zeros with framing error at start and one character garbage at completion 0 This bit is ignored in the asynchronous mode 142 Rabbit 4000 Microprocessor User s Manual Serial Port x Extended Register SAER Address 0x00C5 Clocked Serial Mode Only SBER Address 0x00D5 SCER Address 0x00E5 S
333. t shortens and lengthens clock cycles This has the net effect of reducing the peak energy of clock harmonics by spreading the spectral energy into nearby frequencies which reduces EMI and facilitates government mandated EMI testing Gated clocks are used whenever possible to avoid clocking unused portions of the processor and separate power supply pins for the core and ring further reduce EMI from the Rabbit 4000 The main clock can be doubled or divided by 2 4 6 or 8 to reduce EMI and power con sumption The 32 kHz clock which can be divided by 2 4 8 or 16 can be used instead of the main clock to generate processor and peripheral clocks as low as 2 kHz for significant power savings Note that dividing the 32 kHz clock only affects the processor and periph eral clocks the full 32 kHz signal is still provided to the peripherals RTC and watchdog timers that use it directly The periodic interrupt is automatically disabled since there is not enough time to process it when running off the 32 kHz clock The Ethernet clock can be driven by the processor clock the processor clock divided by 2 or by the input on PE6 The Ethernet clock needs to be 20 MHz to conform to the 10Base T specification See Chapter 20 for more details on the Ethernet clock Chapter 2 Clocks 9 2 1 1 Block Diagram Ethernet Clock MAIN CLOCK Clock GCSR Spectrum Clock Divide by GCMxR CPU Clock Peripheral Clock Divide by 2 4 8 16 CLK
334. t the counter If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on either start or stop conditions or both and cause an interrupt each time the count is cap tured The counter can also be cleared and started under software control and then have its value captured in response to an input Chapter 21 Input Capture 219 The capture counter be synchronized with Timer outputs to load parallel port output registers This makes it possible to generate an output signal precisely synchronized with an input signal Usually it will be desired to synchronize one of the input capture counters with the Timer B counter The count offset can be measured by outputting a pulse at a pre cise time using Timer B to set the output time and capturing the output pulse with an input capture channel Once the phase relationship is known between the counters it is then pos sible to output pulses a precise time delay after an input pulse is captured provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B The minimum time delay needed is prob ably less than 10 us if the software is done carefully and the clock speed is reasonably high 21 1 2 Input Count Mode In the input count mode the channel simply increments the counter each time the start condition occurs The count is enabled by th
335. t this requirement are available in Technical Note TN303 Conformal Coating from the Rabbit Semiconductor Web site The 32 768 kHz oscillator is slow to start oscillating after power on For this reason a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure If the clock is battery backed there will be no startup delay since the oscillator is already oscillating The startup delay may be as much as 5 seconds Crys tals with low series resistance R lt 35 kQ will start faster 18 Rabbit 4000 Microprocessor User s Manual The 32 kHz oscillator be used to drive as the processor peripheral clock to provide significant power savings in ultra sleepy modes The 32 kHz oscillator can be divided by 2 4 8 or 16 to provide clock speeds as low as 2 048 kHz Special self timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra sleepy mode is enabled see Chapter 26 for more details on reducing power consumption Table 2 4 Ultra Sleepy Clock Modes GPSCR Processor and Setting Peripheral Clock XXxxx000 32 768 kHz 100 16 384 kHz 101 8 192 kHz 110 4 096 kHz 11 2 048 kHz When the 32 kHz clock is enabled the periodic interrupt is disabled automatically The real time clock and watchdog timers keep running and use the full 32
336. te of the SMODE pins Depending on their state it either begins normal operation by fetching instruction bytes from CSO and OEO or it enters a special bootstrap mode where it fetches bytes from either Serial Port A or the slave port In this mode bytes can be written to internal registers to set up the Rabbit 4000 for a particular configuration or to memory to load a program The processor can begin normal operation once the bootstrap operation is completed 3 1 1 Block Diagram Reset RESOUT RESET Master Reset Rabbit 4000 Bootstrap Asynch Serial Bootstrap SMODEO Bootstrap Clocked Serial Bootstrap SMODE1 Selection Slave Port Bootstrap Normal Operation Chapter 3 Reset and Bootstrap 25 3 1 2 Registers Register Name Mnemonic Address R W Reset Slave Port Control Register SPCR 0x0024 0xx00000 3 2 Dependencies 3 2 1 I O Pins SMODEO SMODE1 When the Rabbit 4000 is first powered up or when it is reset the state of the SMODEO and SMODEI pins controls its operation RESET Pulling the RESET pin low will initialize everything in the Rabbit 4000 except for the real time clock registers and the onchip encryption RAM CS1 During reset the impedance of the CS1 pin is high and all other memory and I O control signals are held high The special behavior of CS1 allows an external RAM to be powered by the same source as the VBATIO pin which powers CS1 In this case
337. tect for physical address 0x6000 0x6FFF in WP Segment x 1 Enable write protect for physical address 0x6000 0x6FFF in WP Segment x 5 0 Disable 4K write protect for physical address 0x5000 0x5FFF in WP Segment x 1 Enable write protect for physical address 0 5000 0 5 in WP Segment x 4 0 Disable write protect for physical address 0x4000 0x4FFF in WP Segment x 1 Enable write protect for physical address 0x4000 0x4FFF in WP Segment x 3 0 Disable write protect for physical address 0x3000 0x3FFF in WP Segment x 1 Enable write protect for physical address 0x3000 0x3FFF in WP Segment x 2 0 Disable write protect for physical address 0x2000 0x2FFF in WP Segment x 1 Enable write protect for physical address 0x2000 0x2FFF in WP Segment x 1 0 Disable write protect for physical address 0 1000 Ox IFFF in WP Segment x 1 Enable write protect for physical address 0x1000 0x1FFF in WP Segment x 0 0 Disable write protect for physical address 0 0000 in WP Segment x 1 Enable write protect for physical address 0x0000 0x0FFF in WP Segment x Chapter 5 Memory Management 61 Write Protect Segment x High Register WPSAHR Address 0x0482 WPSBHR Address 0x0486 Bit s Value Description 7 0 Disable write protect for physical address OXF000 0xFFFF in WP Segment x 1 Enable write protect fo
338. ten under program control A one in the corresponding table entry con stitutes a multicast address match as far as the network port is concerned A table of one set of unique multicast addresses corresponding to each filter bit is shown below The table shows the least significant byte of the multicast address the remaining five bytes of the address are all zeros for this set of multicast addresses Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NAMF7R 0x17 Ox0B 0 05 0 19 0 85 0 99 0 97 Ox8B NAMF6R 0 9 0 5 OxCB OxD7 0 4 0 57 0 59 0 45 5 OxCF OxD3 OxDD OxCl 0 5 0 41 Ox4F 0x53 NAMF4R 0 01 Ox1D 0x13 OxOF 0x93 Ox8F 0 81 0 9 0 5 0 43 Ox4D 0x51 OxCD OxD1 OxDF 0xC3 NAMF2R 0 91 0 8 0 83 Ox9F 0x03 Ox1F 0 11 0x0D NAMFIR 0 87 Ox9B 0x95 0x89 0 15 0 09 0 07 Ox1B NAMFOR 0x49 0x55 0x5B 0x47 OxDB OxC7 0 9 OxD5 208 Rabbit 4000 Microprocessor User s Manual 20 4 Ethernet Interface Circuit This is the recommended circuit for the Rabbit 4000 10Base T Ethernet interface 10 nF 10 nF ale al All resistors 1 16 W 1 113 4700 unless otherwise noted 1kQ RxD 5 4 SN65LVDS2 7 7 10
339. terrupt Highest Breakpoint Read the status from BDCR System Mode Violation Cleared automatically Stack Limit Violation Cleared automatically Write Protection Violation Cleared automatically Secondary Watchdog Restart secondary watchdog by writing to WDTCR External Interrupt 1 Cleared automatically External Interrupt 0 Cleared automatically Periodic Interrupt Read the status from GCSR Quadrature Decoder Read the status from QDCSR Timer B Read the status from TBCSR Timer A Read the status from TACSR Input Capture Read the status from ICCSR PWM Write any PWM register Timer C Read the status from TCCSR Rd Read from SPDOR SPDIR or SPD2R Slave Port Wr Write to SPDOR SPDIR SPD2R or dummy write to SPSR DMA 7 Cleared automatically DMA 6 Cleared automatically DMA 5 Cleared automatically DMA 4 Cleared automatically DMA 3 Cleared automatically DMA 2 Cleared automatically DMA 1 Cleared automatically DMA 0 Cleared automatically Network Port A Read interrupt status from NACSR Rx Read from SEDR or SEAR Serial Port E i Tx Write to SEDR SEAR SELR or dummy write to SESR Rx Read from SFDR or SFAR Serial Port F Tx Write to SFDR SFAR SFLR or dummy write to SFSR Read from SADR or SAAR Serial Port A Tx Write to SADR SAAR
340. the clock period To calculate the actual memory access time subtract the clock to address output time the data in setup time and the clock period shortening due to the clock spectrum spreader from 2T Example Memory Access Time Calculation e clock 29 49 MHz so 34 ns operating voltage is 3 3 e bus loading is 60 pF e clock to address output delay 8 ns see Table 28 9 e data setup time 1 ns spectrum spreader is on in 1 ns mode resulting in a loss of 3 ns worst case see Table 28 9 The access time is given by access time 2T clock to address data setup spreader delay 68 ns 8 ns 1 ns 3 ns 56 ns 312 Rabbit 4000 Microprocessor User s Manual Similarly the gross output enable access time is T minimum clock low time it is assumed that the early output enable option is enabled This is reduced by the spectrum spreader loss the time from clock to output for the output enable signal the data setup time and a correction for the asymmetry of the original oscillator clock Example Output Enable Access Time Calculation NOTE There is some process and temperature variation in the clock doubler settings As a rule of thumb a 20 variation should be considered When the doubler is enabled 80 of the nominal value should be used for the memory access time calculation e clock 29 49 MHz so T 34 ns e operating voltage is 3 3 V the clock doubler has a nominal delay of 16 ns
341. tion Read The corresponding Timer B comparator has encountered a match condition only 1 These status bits but not the interrupt enable bits are cleared by the read of this register as is the Timer B interrupt 2 1 0 The corresponding Timer B interrupt is disabled pes 1 The corresponding Timer interrupt is enabled 0 0 The main clock for Timer B the peripheral clock divided by 2 is disabled 1 The main clock for Timer B the peripheral clock divided by 2 is enabled Timer B Control Register TBCR Address 0x00B1 Bit s Value Description 7 6 These bits are reserved and should be written with zero 5 0 Normal Timer 2 operation using the match registers 1 Enable Timer B2 to use the step registers to calculate match values 4 0 Normal Timer B1 operation using the match registers 1 Enable Timer B1 to use the step registers to calculate match values 3 2 00 Timer B clocked by main Timer B clock perclk 2 01 Timer B clocked by the output of Timer A1 10 Timer B clocked by main Timer B clock divided by 8 perclk 16 11 Timer clocked by main Timer clock divided by 8 perclk 16 1 0 00 Timer B interrupts are disabled 01 Timer interrupt use Interrupt Priority 1 10 Timer B interrupt use Interrupt Priority 2 11 Timer B interrupt use Interrupt Priority 3 118 Rabbit 4000 Microprocessor User s Manual Timer Count MSB x Register TBM1R Address 0x00B2 TBM2R Address 0x00B4 Bit s Value Desc
342. tion to the instruction register but the prefetch mechanism only tries to keep it full with one byte The other two bytes are for those cases where a prefetch was started in anticipation of the queue being emptied The prefetch mechanism tracks the instructions being fetched and executed to minimize bus conflicts between the prefetch mechanism and other bus transactions These conflicts can occur if the execution two clocks per byte minimum is faster than the instruction prefetch three clocks per two bytes minimum The prefetch mechanism also attempts to minimize the impact of program branches If a jump or subroutine call is decoded and the target address is being fetched the prefetch mechanism automatically stops prefetching once all of the target address is in the queue in anticipation of taking the program branch One special case of the prefetch mechanism is the block instructions Because these instructions are interruptible and may rewind the PC the prefetch mechanism will always empty the queue and restart the prefetching when leaving the block sequence while these instructions are being used Chapter 5 Memory Management 49 The 16 bit memory device connected to CSO or CS1 may may not support byte writes so there is an option to select between these two cases Flash devices with a 16 bit bus do not support byte writes so any byte writes or unaligned word writes to the 16 bit memory space will be suppressed i e the WE wi
343. to be active low default or active high 310 Rabbit 4000 Microprocessor User s Manual 28 3 5 Memory Access Times In computing memory requirements the important considerations are the address access time output enable access time and minimum write pulse required Increasing the clock doubler delay increases the output enable time but decreases the memory write pulse width The early write pulse option can be used to ensure a long enough write pulse but then it must be ensured that the write pulse does not begin before the address lines have stabilized The clock doubler has an affect on the memory access times It works by ORing the clock with a delayed version of itself The nominal delay varies from 3 to 20 ns and is set under program control Any asymmetry in the main clock input before it is doubled will result in alternate clocks having slightly different periods Using the suggested oscillator circuit the asymmetry is no worse than 52 48 This results in a given clock being shortened by the ratio 50 52 or 4 worst case The memory access time is not normally affected because the memory bus cycle is two clocks long and includes both a long and a short clock resulting in no net change arising from asymmetry However if an odd number of wait states is used then the memory access time will be affected slightly When the clock spectrum spreader is enabled clock periods are shortened by a small amount depending on whether th
344. tor must contain the special destination address All the DMA channels request interrupts at the same priority level which is set by a field in the DMA Master Control Register but each DMA channel has its own interrupt vector location This speeds up interrupt processing for the DMA interrupts by eliminating the need to resolve which DMA channel is actually requesting an interrupt DMA transfers may be programmed to occur at any priority level If the programmed level is greater than or equal to the current CPU operating level DMA transfers will occur on demand When the CPU operating level is greater than the programmed DMA operating level no DMA transfers can occur This allows interrupt services routines or other critical 174 Rabbit 4000 Microprocessor User s Manual code to with a guarantee that there will be DMA activity during execution Note that a simultaneous interrupt request and DMA transfer request will be resolved in favor of the DMA transfer request The DMA and Ethernet peripherals were optimized to work together if the Rabbit 4000 s built in Ethernet peripheral is used it is expected that two DMA channels will be dedicated for that purpose 19 1 1 Block Diagram DMA PED 3 External Interrupt Interrupt 7 6 Requests Generation Request DMRxCR Peripheral Timed Request Clock Counter DTRCR DTRDLR DTRDHR Master Control DMA Channel x Channel x St
345. tput 3 SCLKD 5 4 00 Parallel Port D bit 2 alternate output 0 SCLKC 01 Parallel Port D bit 2 alternate output 1 I2 10 Parallel Port D bit 2 alternate output 2 TIMER C2 11 Parallel Port D bit 2 alternate output 3 TXF 3 2 00 Parallel Port D bit 1 alternate output 0 IA6 01 Parallel Port D bit 1 alternate output 1 I1 10 Parallel Port D bit 1 alternate output 2 TIMER C1 11 Parallel Port D bit 1 alternate output 3 RCLKF 1 0 00 Parallel Port D bit 0 alternate output 0 SCLKD 01 Parallel Port D bit 0 alternate output 1 IO 10 Parallel Port D bit 0 alternate output 2 TIMER 11 Parallel Port D bit 0 alternate output 3 TCLKF 92 Rabbit 4000 Microprocessor User s Manual Parallel Port D Alternate High Register PDAHR Address 0x0063 Bit s Value Description 7 6 00 Parallel Port D bit 7 alternate output 0 IA7 01 Parallel Port D bit 7 alternate output 1 I7 10 Parallel Port D bit 7 alternate output 2 PWM3 11 Parallel Port D bit 7 alternate output 3 SCLKC 5 4 00 Parallel Port D bit 6 alternate output 0 TXA 01 Parallel Port D bit 6 alternate output 1 I6 10 Parallel Port D bit 6 alternate output 2 PWM2 11 Parallel Port D bit 6 alternate output 3 3 2 00 Parallel Port D bit 5 alternate output 0 IA6 01 Parallel Port D bit 5 alternate output 1 I5 10 Parallel Port D bit 5 alternate output 2 PWM1 11 Pa
346. transfer followed by a decrement of this register so an initial value of 0x0000 will result in a 65536 byte transfer DMA y Length 15 8 Register DOL1R Address 0x0183 D1L1R Address 0x0193 D2L1R Address 0x01A3 D3L1R Address 0x01B3 D4L1R Address 0x01C3 D5L1R Address 0x01D3 D6L1R Address 0x01E3 D7L1R Address 0x01F3 Bit s Value Description 7 0 Bits 15 8 of the buffer length value are stored in this register Chapter 19 DMA Channels 197 DMA Source 7 0 Register DOSAOR Address 0x0184 DISAOR Address 0x0194 025 Address 0 01 4 D3SAOR Address z 0x01B4 DASAOR Address 0x01C4 D5SAOR Address 0x01D4 D6SAOR Address 0x01E4 D7SAOR Address 0x01F4 Bit s Value Description 7 0 Bits 7 0 of the source address are stored in this register DMA Source Addr 15 8 Register DOSA1R Address 0x0185 DISA1R Address 0x0195 025 1 Address 0x01A5 D3SA1R Address 0x01B5 D4SA1R Address 0x01C5 D5SA1R Address 0x01D5 D6SA1R Address 0x01E5 D7SA1R Address 0x01F5 Bit s Value Description 7 0 Bits 15 8 of the source address are stored in this register DMA y Source Addr 23 16 Register DOSA2R Address 0x0186 D1SA2R Address z 0x0196 D2SA2R Address 0x01A6 D3SA2R Address 0x01B6 D4SA2R Address 0x01C6 D5SA2R Addres
347. transmitter halts and reports the failure via an interrupt The transmitter guarantees the 9 6 us inter frame gap and imple ments the fair access algorithm within the inter frame gap The transmitter automatically sends link test pulses even while otherwise disabled every 16 0 ms The transmitter con tains a jabber timer which automatically disables the transmitter after 26 2 ms of continu ous transmission This error condition generates an interrupt and must be answered by resetting the network port The corresponding DMA channel is automatically halted by this error condition and must be restarted after the network port has been reset The Rabbit 4000 does not implement the 10Base T physical layer on chip but provides differential transmit data to simplify the external circuitry required to drive the 10Base T cabling with the required waveform Chapter 20 10Base T Ethernet 201 The network port receiver uses the received preamble to synchronize to the phase of the incoming frame and then waits for the start frame delimiter Character assembly begins at this point and each byte is transferred to the receive FIFO However no interrupt or DMA request will occur until after the first six bytes of the frame have been received and checked for an address match The receiver can receive frames independent of the address promis cuous mode or it can receive frames with a physical address match a broadcast address match or a multicast address m
348. uffer descriptor s address to the DMA s initial address registers see Chapter 19 for more information 2 Enable the DMA transfer by auto loading the buffer 3 The packet transmission will proceed automatically If any interrupts were enabled for any transmitted packet events they will occur upon completion or error Note that network interrupts will occur when the data appears in the network peripheral but DMA interrupts will occur when the DMA transfer is complete 20 3 3 Receive The following steps explain how to receive an Ethernet packet 1 Set up a DMA buffer descriptor that will read the packet data from NADR and write it to memory Write the buffer descriptor s address to the DMA s initial address registers see Chapter 19 for more information 2 Enable the DMA transfer by auto loading the buffer 3 The packet transmission will proceed automatically when data comes in If any inter rupts were enabled for any received packet events they will occur upon completion or error Note that network interrupts will occur when the data appear in the Ethernet peripheral but DMA interrupts will occur when the DMA transfer is complete 206 Rabbit 4000 Microprocessor User s Manual 20 3 4 Handling Interrupts network isr push af ioi 14 NACSR push af bit 6 a jp nz handle rx err pop af bit 4 a jp nz handle tx err we af bit 2 ioi 14 NASR bit 0 jp nz
349. ugs have been identified in the Rabbit 4000 design and are present in all devices currently available 1 Primary secondary watchdog timer interaction if the secondary watchdog timer is enabled when a primary watchdog timeout occurs resetting the processor the sec ondary watchdog timer is still enabled when the device comes out of reset which is not the documented behavior the secondary watchdog should be disabled on reset The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing Ox5F to WDTCR The secondary watchdog timer is then enabled if needed with the define USE SECONDARY WD macro 2 Stack protection DMA interaction when stack protection is enabled and a DMA transfer is occurring the stack protection interrupt will occur if the lower 16 bits of a DMA transfer s physical write address match the 16 bits of the stack protection s logical address limits 3 DMA HDL C Ethernet interaction a specific bug can manifest itself when the following conditions are present The HDLC or Ethernet peripherals are being fed bytes for transmit via DMA The current DMA buffer has been marked with special treatment for last byte buffer has not been marked as final buffer The DMA fills the transmit FIFO with the next to last byte of the buffer and then either switches to another channel or releases the bus The DMA then returns to t
350. um spreader by gated clocks which prevent unnecessary clocking of unused regis ters and by separate power planes for the processor core and I O pins which reduce noise crosstalk An auxiliary I O bus can be used by designers to enable separate buses for I O and memory or to limit loading the memory bus to reduce EMI and ground bounce problems when interfacing external peripherals to the processor The auxiliary I O bus accomplishes this by duplicating the Rabbit s data bus on Parallel Port A and uses Parallel Chapter 1 The Rabbit 4000 Processor 1 Port B to provide the processor s six or eight least significant address lines for interfacing with external peripherals The high performance instruction set offers both greater efficiency and execution speed of compiler generated C code Instructions include numerous single byte opcodes that execute in two clock cycles 16 bit and 32 bit loads and stores 16 bit and 32 bit logical and arith metic operations 16 x 16 multiply executes in 12 clocks long jumps and returns for accessing a full 16 megabytes of memory and one byte prefixes to turn memory access instructions into internal and external I O instructions Hardware supported breakpoints ease debugging by trapping on code execution or data reads and writes The Rabbit 4000 requires no external memory driver or interface logic Its 24 bit address bus 8 bit or 16 bit data bus three chip select lines two output enable lines and two wr
351. upt will be handled only if its interrupt priority is greater than the current processor priority This means that even a Priority 3 interrupt can be blocked if the processor is currently at Priority 3 The System Mode Violation Stack Limit Violation Write Protection Violation secondary watchdog and breakpoint interrupts are always enabled at Priority 3 In addition when the system user mode is enabled and the processor is in the user mode the processor will not actually enter Priority 3 any attempt to enter Priority 3 will actually be requested as Priority 2 When an interrupt is handled a call is executed to a fixed location in the interrupt vector tables this operation requires 10 clocks the minimum interrupt latency for the Rabbit 4000 There are two vector tables the internal and the external interrupt vector tables that be located anywhere in logical memory by setting the processor s and EIR registers The and EIR registers hold the upper byte of each table s address For example if is loaded with OxC4 then the internal interrupt vector table will start at the logical memory address OxC400 The internal interrupt vector table occupies 512 bytes and the external interrupt vector table is 256 bytes in size Since the RST and SYSCALL vectors use all eight bits of the IIR for addressing the lowermost bit of should always be set to zero so to keep some vectors from inadvertently overlapping Each interru
352. ur independent pulse width modulator PWM outputs each based on a 1024 pulse frame are driven by the out put of a programmable internal timer The PWM outputs can be filtered to create a 10 bit D A converter or they can be used directly to drive devices such as motors or solenoids Two external interrupt vectors can multiplex inputs from up to six external pins There are numerous timers available for use in the Rabbit 4000 Timer A consists of ten 8 bit counters each of which has a programmed time constant Six of them can be cas caded from the primary Timer A counter Timer B contains a 10 bit counter two match registers and two step registers An interrupt can be generated or the output pin can be updated when the counter reaches a match value and the match value is then incremented automatically by the step value Timer C is a 16 bit counter that counts up to a program mable limit It contains eight match registers four to set the output of a parallel port pin and four to reset it This allows for the creation of PWM signals both synchronous and variable phase and quadrature signals 2 Rabbit 4000 Microprocessor User s Manual The Rabbit 4000 also provides support for protected operating systems Support for two levels of operation known as system and user modes allow application critical code to operate in safety while user code is prevented from inadvertently disturbing the setup of the processor Memory blocks as small as 4KB
353. ure Control Status Register ICCSR Address 0x0056 Bit s Value Description 7 0 The Input Capture 2 Start condition has not occurred Read 1 The Input Capture 2 Start condition has occurred 6 0 The Input Capture 2 Stop condition has not occurred Read 1 The Input Capture 2 Stop condition has occurred 5 0 The Input Capture 1 Start condition has not occurred Read 1 The Input Capture 1 Start condition has occurred 4 0 The Input Capture 1 Stop condition has not occurred Read 1 The Input Capture 1 Stop condition has occurred 3 0 The Input Capture 2 counter has not rolled over to all zeros Read 1 The Input Capture 2 counter has rolled over to all zeros 2 0 The Input Capture 1 counter has not rolled over to all zeros Read 1 The Input Capture 1 counter has rolled over to all zeros 7 2 These status bits but not the interrupt enable bits are cleared by the read of this Read register as is the Input Capture Interrupt 7 4 0 corresponding Input Capture interrupt is disabled Write 1 The corresponding Input Capture interrupt is enabled 3 0 No effect on Input Capture 2 counter This bit always reads as zero Write 1 Reset Input Capture 2 counter to all zeros and clears the rollover latch 2 0 No effect on Input Capture 1 counter This bit always reads as zero Write 1 Reset Input Capture 1 counter to all zeros and clears the rollover latch 1 0 These bits reserved and should be written with zeros These bits will alw
354. urrent 9 32 768 kHz 25 C 22 uA Ring Supply Voltage 3 3 V 3 0 3 3 V 3 6 V VDDijo I O Ring Supply Voltage 1 8 V 1 65 V 18 1 90 V Ring Current 29 4912 MHz 3 3 V 25 C 12 2 mA Ring Current 7 3728 MHz 3 3 V 25 C 10 5 mA Ring Current 32 768 kHz 3 3 V 25 C 1 1 mA Input Low Voltage VDDjo 3 3 V Vin 0 8 V 9 Input High Voltage VDDyo 3 3 V Vin 2 0 Output Low Voltage VDDjo 3 3 V Vor 0 4 V Output High Voltage VDDjo 3 3 V 2 4 Output drive TXD TXDD TXD TXDD IDRIVE 24 mA All other I O 8 mA Chapter 28 Specifications 301 Table 28 2 Preliminary Battery Backed DC Electrical Characteristics VDDcone 1 8V 10 VDDjo 3 3V 10 T4 40 C to 85 C Parameter Symbol Min Typ Max gt VBAT Supply Voltage VBAT 1 65 V 1 8 1 90 V ga gt VBAT Current device powered down 1 7 2 7 VBATIO Supply Voltage e device powered VBATIO 1 65 V 3 3 V 3 6 V device powered down 1 65 V 1 8V 3 6 gt VBATIO Current device powered down IVBATIO 0 1 0 2 302 Rabbit 4000 Microprocessor User s Manual 28 2 Characteristics Table 28 3 Preliminary AC Electrical Characteristics VDDcogg 1 8 V 10 VDDio 3 3 10 TA 40 C to 85 C Parameter Symbol Min Typ Max Main Clock Frequency on CLKI T nain 60 MHz Real Time Clock Frequency on CLK32K ferc 32 768 k
355. ut port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the slave port with SCS from Parallel Port E bit 7 011 Enable the auxiliary T O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination is reserved and should not be used 101 This bit combination is reserved and should not be used 110 Enable the slave port with SCS from Parallel Port B bit 6 11 Enable the auxiliary I O bus Parallel Port is used for the data bus and Parallel Port B 7 0 is used for the address bus 1 0 00 Slave port interrupts are disabled 01 Slave port interrupts use Interrupt Priority 1 10 Slave port interrupts use Interrupt Priority 2 11 Slave port interrupts use Interrupt Priority 3 Chapter 3 Reset and Bootstrap 29 30 Rabbit 4000 Microprocessor User s Manual 4 SYSTEM MANAGEMENT 4 1 Overview There are a number of basic system peripherals in the Rabbit 4000 processor some of which are covered in later chapters The peripherals covered in this chapter are the periodic interrupt the real time clock the watchdog timers the battery backed onchip encryption RAM and some of the miscellaneous output pins and their control and processor registers that provide the processor ID and revision numbers The periodic interrupt when enabled is generated every 16 clocks of the 32 kHz clock every 488 us or 2 048 kHz This interrupt c
356. uxiliary I O bus instead of the memory bus e All devices could poll the slave port status register to determine when data is present instead of relying on interrupts e The master could write to SPDOR triggering an interrupt on the slave The slave could then simply write a response into SPDOR which the master detects by polling SPSR This configuration is useful when fewer signals are desired or the master device has no external interrupts available If polling is to be used it is important to note that not all bits in the status register may be updated at once it is possible to read a transitional value as the register updates To guar antee a proper polling read the status register should be read twice when the same value is read both times the value is correct Similarly it is possible to receive a scrambled value from a data register if it is read while being written The protocol used should take account of this and prevent it from occurring the protocol described above guarantees this will not occur Chapter 18 Slave Port 167 18 3 8 Timing Diagrams Figure 18 2 shows the sequence of events when the master reads writes the slave port registers Slave Port Read Cycle ISCS SS 5 Th SCS SA1 SAO gt Tsu SA Th SA SRD um SA IEEE gt Tw SRD SD 7 0 te Ten SRD lt gt Tdis SRD 1 Ta SRD ISWR lt gt Teu SWR SRD Slave Port Write Cycle
357. variety of standard memories for any Rabbit 4000 speed grade When 16 bit memory is connected to CSO the first few instructions must program the device to operate in 16 bit mode This code is shown below This code should be the first thing executed by your device Because the processor is fetching bytes from a 16 bit memory device that is not connected to AO only one byte instructions can be used and they must occur in pairs ORG 0000h XOR A lt 00000000 XOR A LD H A h lt 00000000 LD H A SCF SCF RLA a lt 00000001 RLA a lt 00000010 LD B A b lt 00000010 LD B A SCF SCF ADC A B a lt 00000101 ADC A B a lt 00000111 ADD A A a lt 00001110 ADD A A a lt 00011100 SCF SCF ADC A H a lt 00011101 ADC A H LD L A l lt 00011101 LD L A two IOIs same as LD HL B MACR lt 00000010 LD HL B dummy memory write no WE NOP required delay to start NOP up the 16 bit bus Chapter 5 Memory Management 51 5 3 4 Separate Instruction and Data Space To make better use of the 64KB of logical space an option is provided to map code and data accesses in the same address space to separate devices This is accomplished by enabling the inversion of 16 and the most significant bit of the bank select bits for accesses in the root and data segments Careful use of these features allows both code and data to separately use u
358. y reading the status bits in ICCSR and adjusting any software counters accordingly e The interrupt request should be cleared by reading from ICCSR 21 3 3 Example ISR A sample interrupt handler is shown below ic_isr push af ioi 14 ICCSR clear the interrupt request and get status determine which interrupts have occurred if rollover perform any necessary software counter adjustments here read counter values pop af ipres ret Chapter 21 Input Capture 223 21 3 4 Capture Mode Pulse Width or Time Between Events The following steps explain how to measure the pulse width or time between events 1 Select the same input pin to perform a pulse width measurement between the start and stop conditions or select two different input pins to measure time between events on those pins 2 Set the counter to start on the start condition and stop on the stop condition latch on the stop condition and generate an interrupt on the stop condition 3 In the interrupt handler read out the counter to determine the pulse width or time inter val between the two events Time Stamp External Events The following steps explain how to time stamp external events 1 Set the trigger for the desired event type 2 Set the counter to run continuously latch on the start and or stop condition and gen erate an interrupt on the start and or stop condition 3 In the interrupt handler read out the counter as an event timestam
359. y the peripheral clock divided by 16 or by the output of countdown timer 1 The counter counts from zero to the limit programmed into the Timer C divider registers and then restarts at zero so the overall cycle count is the value in the divider registers plus one There are four Timer outputs that are called Timers Each output is controlled by a 16 bit set value and a 16 bit reset value Each output is set to one when the count matches the value in the corresponding set register and is cleared when the count matches the value programmed in the corresponding reset register This allows the creation of quadrature signals or three phase signals with a variable frequency for motor control applications The values in all of the Timer C registers are transferred to holding registers for use during the count cycle when the counter is reloaded with zeros allowing the con trol registers to be reloaded at any time during the count cycle Timer C can generate an interrupt when the count limit value is reached A separate Timer C Block Access Register TCBAR and Timer C Block Pointer Register TCBPR are available to allow DMA control of Timer C The pointer register contains the address of the Timer C register to be accessed via the access register Each read or write of the access register automatically increments the pointer register through the sequence shown below Note that only the lower five bits of the pointer actually change This allow

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Rabbit ® 4000 Microprocessor User`s Manual